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path: root/lib/lufa/LUFA/StudioIntegration/HV1/lufa_hv1_transform.xslt
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2017-07-09Merge commit '8858438a770c1c982f33b296447ca77176c751f7'Jack Humbert
2017-07-07Merge commit '60b30c036397cb5627fa374bb930794b225daa29' as 'lib/lufa'Jack Humbert
374291ab2e86e95a97341fd9c475fcb8 (diff)
Merge commit '1fe4406f374291ab2e86e95a97341fd9c475fcb8'
Diffstat (limited to 'tmk_core/tool')
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-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/export/uvision4_seeed_tiny_ble.uvproj.tmpl431
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-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/export/uvision4_teensy3_1.uvproj.tmpl423
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/export/uvision4_ublox_c027.uvopt.tmpl201
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-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/export/zip.py41
-rwxr-xr-xtmk_core/tool/mbed/mbed-sdk/workspace_tools/export_test.py213
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/hooks.py125
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/__init__.py59
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/default_auto.py36
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/detect_auto.py55
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/dev_null_auto.py50
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/echo.py59
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/echo_flow_control.py48
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/example/BroadcastReceive.py25
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/example/BroadcastSend.py30
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/example/MulticastReceive.py31
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/example/MulticastSend.py30
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/example/TCPEchoClient.py28
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/example/TCPEchoServer.py30
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/example/UDPEchoClient.py28
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/example/UDPEchoServer.py27
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/example/__init__.py16
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/hello_auto.py34
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/host_registry.py36
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/host_test.py397
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/host_tests_plugins/__init__.py68
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/host_tests_plugins/host_test_plugins.py118
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/host_tests_plugins/host_test_registry.py89
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/host_tests_plugins/module_copy_firefox.py76
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/host_tests_plugins/module_copy_mbed.py71
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/host_tests_plugins/module_copy_mps2.py107
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/host_tests_plugins/module_copy_shell.py64
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/host_tests_plugins/module_copy_silabs.py61
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/host_tests_plugins/module_reset_mbed.py72
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/host_tests_plugins/module_reset_mps2.py74
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/host_tests_plugins/module_reset_silabs.py66
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/mbedrpc.py287
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/midi.py72
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/net_test.py27
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/rpc.py56
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/rtc_auto.py50
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/stdio_auto.py56
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/tcpecho_client.py57
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/tcpecho_client_auto.py87
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/tcpecho_server.py50
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/tcpecho_server_auto.py84
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/tcpecho_server_loop.py40
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/udp_link_layer_auto.py145
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/udpecho_client.py55
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/udpecho_client_auto.py77
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/udpecho_server.py29
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/udpecho_server_auto.py68
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/host_tests/wait_us_auto.py69
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/libraries.py121
-rwxr-xr-xtmk_core/tool/mbed/mbed-sdk/workspace_tools/make.py287
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/options.py44
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/patch.py50
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/paths.py109
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/project.py196
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/settings.py114
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/singletest.py237
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/size.py121
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/synch.py373
-rwxr-xr-xtmk_core/tool/mbed/mbed-sdk/workspace_tools/targets.py1272
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/test_api.py1841
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/test_db.py165
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/test_exporters.py235
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/test_mysql.py271
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/test_webapi.py242
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/tests.py1062
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/toolchains/__init__.py745
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/toolchains/arm.py187
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/toolchains/gcc.py257
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/toolchains/iar.py112
-rw-r--r--tmk_core/tool/mbed/mbed-sdk/workspace_tools/utils.py122
4198 files changed, 2016457 insertions, 0 deletions
diff --git a/tmk_core/tool/mbed/mbed-sdk/.gitattributes b/tmk_core/tool/mbed/mbed-sdk/.gitattributes
new file mode 100644
index 000000000..05491d630
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/.gitattributes
@@ -0,0 +1,15 @@
+*.c text
+*.cpp text
+*.h text
+*.s text
+*.sct text
+*.ld text
+*.txt text
+*.xml text
+*.py text
+*.md text
+*.json text
+*.tmpl text
+*.dia binary
+*.elf binary
+*.bin binary
diff --git a/tmk_core/tool/mbed/mbed-sdk/.gitignore b/tmk_core/tool/mbed/mbed-sdk/.gitignore
new file mode 100644
index 000000000..b66af8ba4
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/.gitignore
@@ -0,0 +1,75 @@
+*.py[cod]
+
+# Distribution dir
+dist
+
+# MANIFEST file
+MANIFEST
+
+# Private settings
+private_settings.py
+
+# Default Build Directory
+build/
+
+# Eclipse Project Files
+.cproject
+.project
+.pydevproject
+
+# C extensions
+*.so
+
+# Packages
+*.egg
+*.egg-info
+dist
+build
+eggs
+parts
+bin
+var
+sdist
+develop-eggs
+.installed.cfg
+lib
+lib64
+
+# Installer logs
+pip-log.txt
+
+# Unit test / coverage reports
+.coverage
+.tox
+nosetests.xml
+
+# Translations
+*.mo
+
+# Mr Developer
+.mr.developer.cfg
+
+output.txt
+uVision Project/
+
+# Sublime Text Project Files
+*.sublime*
+
+*.bak
+debug.log
+
+# Ignore OS X Desktop Services Store files
+.DS_Store
+
+# Orig diff files
+*.orig
+
+# PyCharm
+*.idea
+
+# Cscope
+cscope.*
+
+# vim swap files
+*.swp
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/.travis.yml b/tmk_core/tool/mbed/mbed-sdk/.travis.yml
new file mode 100644
index 000000000..a26edf15a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/.travis.yml
@@ -0,0 +1,9 @@
+---
+python:
+ - "2.7"
+script: "python workspace_tools/build_travis.py"
+install:
+ - "sudo $TRAVIS_BUILD_DIR/travis/install_dependencies.sh > /dev/null"
+ - sudo pip install colorama
+ - sudo pip install prettytable
+ - sudo pip install jinja2
diff --git a/tmk_core/tool/mbed/mbed-sdk/CONTRIBUTING.md b/tmk_core/tool/mbed/mbed-sdk/CONTRIBUTING.md
new file mode 100644
index 000000000..353cd58c0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/CONTRIBUTING.md
@@ -0,0 +1,45 @@
+# Description
+This document is cheat sheet for everyone who wants to contribute to mbedmicro/mbed GitHub repository at GitHub.
+All changes in code base should originate from GitHub Issues and take advantage of existing GitHub flows. Goal is to attract contributors and allow them contribute to code and documentation at the same time.
+
+Guidelines from this document are created to help new and existing contributors understand process workflow and align to project rules before pull request is submitted. It explains how a participant should do things like format code, test fixes, and submit patches.
+
+## Where to get more information?
+You can for example read more in our ```docs``` section in [mbedmicro/mbed/doc](https://github.com/PrzemekWirkus/mbed/tree/docs/docs) directory.
+
+# How to contribute
+We really appreciate your contributions! We are Open Source project and we need your help. We want to keep it as easy as possible to contribute changes that get things working in your environment. There are a few guidelines that we need contributors to follow so that we can have a chance of keeping on top of things.
+
+Before a pull request will be merged, the [mbed Contributor Agreement](http://developer.mbed.org/contributor_agreement/) must be signed.
+
+You can pick up existing [mbed GitHub Issue](https://github.com/mbedmicro/mbed/issues) and solve it or implement new feature you find important, attractive or just necessary. We will review your proposal via pull request mechanism, give you comments and merge your changes if we decide your contribution satisfy criteria such as quality.
+
+# Enhancements vs Bugs
+Enhancements are:
+* New features implementation.
+* Code refactoring.
+* Coding rules, coding styles improvements.
+* Code comments improvement.
+* Documentation work.
+
+Bugs are:
+* Issues rose internally or externally by mbedmicro/mbed users.
+* Internally (within mbed team) created issues from Continuous Integration pipeline and build servers.
+* Issues detected using automation tools such as compilers, sanitizers, static code analysis tools etc.
+
+# Gate Keeper role
+Gate Keeper is a person responsible for GitHub process workflow execution and is responsible for repository / project code base. Gate Keeper is also responsible for code (pull request) quality stamp and approves or rejects code changes in project’s code base.
+
+Gate Keepers will review your pull request code, give you comments in pull request comment section and in the end if everything goes well merge your pull request to one of our branches (most probably default ```master``` branch).
+
+Please be patient, digest Gate Keeper's feedback and respond promptly :)
+
+# mbed SDK porting
+* For more information regarding mbed SDK porting please refer to [mbed SDK porting](http://developer.mbed.org/handbook/mbed-SDK-porting) handbook.
+* Before starting the mbed SDK porting, you might want to familiarize with the [mbed SDK library internals](http://developer.mbed.org/handbook/mbed-library-internals) first.
+
+# Glossary
+* Gate Keeper – persons responsible for overall code-base quality of mbedmicro/mbed project.
+* Enhancement – New feature deployment, code refactoring actions or existing code improvements.
+* Bugfix – Issues originated from GitHub Issues pool, raised internally within mbed classic team or issues from automated code validators like linters, static code analysis tools etc.
+* Mbed classic – mbed SDK 2.0 located in GitHub at mbedmicro/mbed.
diff --git a/tmk_core/tool/mbed/mbed-sdk/LICENSE b/tmk_core/tool/mbed/mbed-sdk/LICENSE
new file mode 100644
index 000000000..59cd3f8a3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/LICENSE
@@ -0,0 +1,165 @@
+Apache License
+Version 2.0, January 2004
+http://www.apache.org/licenses/
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
+"License" shall mean the terms and conditions for use, reproduction, and
+distribution as defined by Sections 1 through 9 of this document.
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+
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+outstanding shares, or (iii) beneficial ownership of such entity.
+
+"You" (or "Your") shall mean an individual or Legal Entity exercising
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+"Source" form shall mean the preferred form for making modifications, including
+but not limited to software source code, documentation source, and configuration
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+
+"Work" shall mean the work of authorship, whether in Source or Object form, made
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+5. Submission of Contributions.
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+conditions of this License, without any additional terms or conditions.
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+6. Trademarks.
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+reasonable and customary use in describing the origin of the Work and
+reproducing the content of the NOTICE file.
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+7. Disclaimer of Warranty.
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+Unless required by applicable law or agreed to in writing, Licensor provides the
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+redistributing the Work and assume any risks associated with Your exercise of
+permissions under this License.
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+8. Limitation of Liability.
+
+In no event and under no legal theory, whether in tort (including negligence),
+contract, or otherwise, unless required by applicable law (such as deliberate
+and grossly negligent acts) or agreed to in writing, shall any Contributor be
+liable to You for damages, including any direct, indirect, special, incidental,
+or consequential damages of any character arising as a result of this License or
+out of the use or inability to use the Work (including but not limited to
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+9. Accepting Warranty or Additional Liability.
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+While redistributing the Work or Derivative Works thereof, You may choose to
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+other liability obligations and/or rights consistent with this License. However,
+in accepting such obligations, You may act only on Your own behalf and on Your
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diff --git a/tmk_core/tool/mbed/mbed-sdk/MANIFEST.in b/tmk_core/tool/mbed/mbed-sdk/MANIFEST.in
new file mode 100644
index 000000000..17993153c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/MANIFEST.in
@@ -0,0 +1,3 @@
+graft workspace_tools
+recursive-exclude workspace_tools *.pyc
+include LICENSE
diff --git a/tmk_core/tool/mbed/mbed-sdk/README.md b/tmk_core/tool/mbed/mbed-sdk/README.md
new file mode 100644
index 000000000..d8afa8c8e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/README.md
@@ -0,0 +1,115 @@
+mbed SDK
+========
+
+[![Build Status](https://travis-ci.org/mbedmicro/mbed.png)](https://travis-ci.org/mbedmicro/mbed/builds)
+
+The mbed Software Development Kit (SDK) is a C/C++ microcontroller software platform relied upon by tens of thousands of
+developers to build projects fast.
+
+The SDK is licensed under the permissive Apache 2.0 licence, so you can use it in both commercial and personal projects
+with confidence.
+
+The mbed SDK has been designed to provide enough hardware abstraction to be intuitive and concise, yet powerful enough
+to build complex projects. It is built on the low-level ARM CMSIS APIs, allowing you to code down to the metal if needed.
+In addition to RTOS, USB and Networking libraries, a cookbook of hundreds of reusable peripheral and module libraries
+have been built on top of the SDK by the mbed Developer Community.
+
+Documentation
+-------------
+* [Tools](http://developer.mbed.org/handbook/mbed-tools): how to setup and use the build system.
+* [mbed library internals](http://developer.mbed.org/handbook/mbed-library-internals)
+* [Adding a new target microcontroller](http://developer.mbed.org/handbook/mbed-SDK-porting)
+
+Supported Microcontrollers and Boards
+-------------------------------------
+View all on the [mbed Platforms](https://developer.mbed.org/platforms/) page.
+
+NXP:
+* [mbed LPC1768](http://developer.mbed.org/platforms/mbed-LPC1768/) (Cortex-M3)
+* [u-blox C027 LPC1768](http://developer.mbed.org/platforms/u-blox-C027/) (Cortex-M3)
+* [mbed LPC11U24](http://developer.mbed.org/platforms/mbed-LPC11U24/) (Cortex-M0)
+* [EA LPC11U35](http://developer.mbed.org/platforms/EA-LPC11U35/) (Cortex-M0)
+* mbed LPC2368 (ARM7TDMI-S)
+* LPC810 (Cortex-M0+)
+* [LPC812](http://developer.mbed.org/platforms/NXP-LPC800-MAX/) (Cortex-M0+)
+* [EA LPC4088](http://developer.mbed.org/platforms/EA-LPC4088/) (Cortex-M4F)
+* [EA LPC4088 DM](http://developer.mbed.org/platforms/EA-LPC4088-Display-Module/) (Cortex-M4F)
+* LPC4330 (Cortex-M4F + Cortex-M0)
+* [LPC1347](http://developer.mbed.org/platforms/DipCortex-M3/) (Cortex-M3)
+* [LPC1114](http://developer.mbed.org/platforms/LPC1114FN28/) (Cortex-M0)
+* LPC11C24 (Cortex-M0)
+* [LPC1549](https://developer.mbed.org/platforms/LPCXpresso1549/) (Cortex-M3)
+* [LPC800-MAX](https://developer.mbed.org/platforms/NXP-LPC800-MAX/) (Cortex-M0+)
+* [DipCortex-M0](https://developer.mbed.org/platforms/DipCortex-M0/) (Cortex-M0)
+* [DipCortex-M3](https://developer.mbed.org/platforms/DipCortex-M3/) (Cortex-M3)
+* [BlueBoard-LPC11U24](https://developer.mbed.org/platforms/BlueBoard-LPC11U24/) (Cortex-M0)
+* LPCCAPPUCCINO (Cortex-M0)
+* [Arch](https://developer.mbed.org/platforms/Seeeduino-Arch/) (Cortex-M0)
+* [Arch GPRS](https://developer.mbed.org/platforms/Seeed-Arch-GPRS/) (Cortex-M0)
+* [Arch Pro](https://developer.mbed.org/platforms/Seeeduino-Arch-Pro/) (Cortex-M3)
+
+Freescale:
+* [FRDM-KL05Z](https://developer.mbed.org/platforms/FRDM-KL05Z/) (Cortex-M0+)
+* [FRDM-KL25Z](http://developer.mbed.org/platforms/KL25Z/) (Cortex-M0+)
+* FRDM-KL43Z (Cortex-M0+)
+* [FRDM-KL46Z](https://developer.mbed.org/platforms/FRDM-KL46Z/) (Cortex-M0+)
+* [FRDM-K20D50M](https://developer.mbed.org/platforms/FRDM-K20D50M/) (Cortex-M4)
+* [FRDM-K22F](https://developer.mbed.org/platforms/FRDM-K22F/) (Cortex-M4F)
+* [FRDM-K64F](https://developer.mbed.org/platforms/FRDM-K64F/) (Cortex-M4F)
+
+STMicroelectronics:
+* [Nucleo-F030R8](https://developer.mbed.org/platforms/ST-Nucleo-F030R8/) (Cortex-M0)
+* [Nucleo-F072RB](https://developer.mbed.org/platforms/ST-Nucleo-F072RB/) (Cortex-M0)
+* [Nucleo-L053R8](https://developer.mbed.org/platforms/ST-Nucleo-L053R8/) (Cortex-M0+)
+* [Nucleo-F103RB](https://developer.mbed.org/platforms/ST-Nucleo-F103RB/) (Cortex-M3)
+* [Nucleo-L152RE](https://developer.mbed.org/platforms/ST-Nucleo-L152RE/) (Cortex-M3)
+* [Nucleo-F302R8](https://developer.mbed.org/platforms/ST-Nucleo-F302R8/) (Cortex-M4F)
+* [Nucleo-F334R8](https://developer.mbed.org/platforms/ST-Nucleo-F334R8/) (Cortex-M4F)
+* [Nucleo-F401RE](https://developer.mbed.org/platforms/ST-Nucleo-F401RE/) (Cortex-M4F)
+* [Nucleo-F411RE](https://developer.mbed.org/platforms/ST-Nucleo-F411RE/) (Cortex-M4F)
+* STM32F4XX (Cortex-M4F)
+* STM32F3XX (Cortex-M4F)
+* STM32F0-Discovery (Cortex-M0)
+* STM32VL-Discovery (Cortex-M3)
+* STM32F3-Discovery (Cortex-M4F)
+* STM32F4-Discovery (Cortex-M4F)
+* STM32F429-Discovery (Cortex-M4F)
+* STM32L0-Discovery (Cortex-M0+)
+* [Arch Max](https://developer.mbed.org/platforms/Seeed-Arch-Max/) (Cortex-M4F)
+
+
+Nordic:
+* [nRF51822-mKIT](https://developer.mbed.org/platforms/Nordic-nRF51822/) (Cortex-M0)
+* [Arch BLE](https://developer.mbed.org/platforms/Seeed-Arch-BLE/) (Cortex-M0)
+
+Renesas:
+* [RZ-A1H](http://developer.mbed.org/platforms/Renesas-GR-PEACH/) (Cortex-A9)
+
+
+Supported Toolchains and IDEs
+-----------------------------
+* GCC ARM: [GNU Tools for ARM Embedded Processors](https://launchpad.net/gcc-arm-embedded/4.7/4.7-2012-q4-major)
+* ARMCC (standard library and MicroLib): [uVision](http://www.keil.com/uvision/)
+* IAR: [IAR Embedded Workbench](http://www.iar.com/en/Products/IAR-Embedded-Workbench/ARM/)
+* GCC code_red: [Red Suite](http://www.code-red-tech.com/)
+* GCC CodeSourcery: [Sourcery CodeBench](http://www.mentor.com/embedded-software/codesourcery)
+* GCC ARM: [Em::Blocks](http://www.emblocks.org/web/)
+* GCC ARM: [CooCox CoIDE](http://www.coocox.org/)
+
+API Documentation
+-----------------
+* [RTOS API](http://developer.mbed.org/handbook/RTOS)
+* [TCP/IP Socket API](http://developer.mbed.org/handbook/Socket) (Transports: Ethernet, WiFi, 3G)
+* [USB Device API](http://developer.mbed.org/handbook/USBDevice)
+* [USB Host API](http://developer.mbed.org/handbook/USBHost)
+* [DSP API](http://developer.mbed.org/users/mbed_official/code/mbed-dsp/docs/tip/)
+* Flash File Systems: [SD](http://developer.mbed.org/handbook/SDFileSystem), [USB MSD](http://developer.mbed.org/handbook/USBHostMSD), [semihosted](http://developer.mbed.org/handbook/LocalFileSystem)
+* [Peripheral Drivers API](http://developer.mbed.org/handbook/Homepage)
+
+Community
+---------
+For discussing the development of the mbed SDK itself (Addition/support of microcontrollers/toolchains, build and test system, Hardware Abstraction Layer API, etc) please join our [mbed-devel mailing list](https://groups.google.com/forum/?fromgroups#!forum/mbed-devel).
+
+For every topic regarding the use of the mbed SDK, rather than its development, please post on the [mbed.org forum](http://mbed.org/forum/), or the [mbed.org Q&A](http://mbed.org/questions/).
+
+For reporting issues in the mbed libraries please open a ticket on the issue tracker of the relevant [mbed official library](http://mbed.org/users/mbed_official/code/).
diff --git a/tmk_core/tool/mbed/mbed-sdk/docs/BUILDING.md b/tmk_core/tool/mbed/mbed-sdk/docs/BUILDING.md
new file mode 100644
index 000000000..243bea5cd
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/docs/BUILDING.md
@@ -0,0 +1,601 @@
+# Mbed SDK build script environment
+## Introduction
+Mbed test framework allows users to test their mbed devices’ applications, build mbed SDK library, re-run tests, run mbed SDK regression, add new tests and get all this results automatically. Everything is done on your machine so you have a full control over compilation, and tests you run.
+
+It's is using Python 2.7 programming language to drive all tests so make sure Python 2.7 is installed on your system and included in your system PATH. To compile mbed SDK and tests you will need one or more supported compilers installed on your system.
+
+To follow this short introduction you should already:
+* Know what mbed SDK is in general.
+* Know how to install Python 2.7, ARM target cross compilers.
+* You have C/C++ programming experience and at least willingness to learn a bit about Python.
+
+## Test automation
+Currently our simple test framework allows users to run tests on their machines (hosts) in a fully automated manner. All you need to do is to prepare two configuration files.
+
+## Test automation limitations
+Note that for tests which require connected external peripherals, for example Ethernet, SD flash cards, external EEPROM tests, loops etc. you need to:
+
+* Modify test source code to match components' pin names to actual mbed board pins where peripheral is connected or
+* Wire your board the same way test defines it.
+
+## Prerequisites
+mbed test suite and build scripts are Python 2.7 applications and require Python 2.7 runtime environment and [setuptools](https://pythonhosted.org/an_example_pypi_project/setuptools.html) to install dependencies.
+
+What we need:
+* Installed [Python 2.7](https://www.python.org/download/releases/2.7) programming language.
+* Installed [setuptools](https://pythonhosted.org/an_example_pypi_project/setuptools.html#installing-setuptools-and-easy-install)
+* Optionally you can install [pip](https://pip.pypa.io/en/latest/installing.html) which is the PyPA recommended tool for installing Python packages from command line.
+
+mbed SDK in its repo root directory specifies ```setup.py``` file which holds information about all packages which are dependencies for it. Bear in mind only few simple steps are required to install all dependencies.
+
+First, clone mbed SDK repo and go to mbed SDk repo's directory:
+```
+$ git clone https://github.com/mbedmicro/mbed.git
+$ cd mbed
+```
+
+Second, invoke ```setup.py``` so ```setuptools``` can install mbed SDK's dependencies (external Python modules required by mbed SDK):
+```
+$ python setup.py install
+```
+or
+```
+$ sudo python setup.py install
+```
+when your system requires administrator rights to install new Python packages.
+
+## Prerequisites (manual Python package dependency installation)
+**Please only read this chapter if you had problems installing mbed SDK dependencies to Python packages**.
+
+Below you can find the list of mbed SDK dependencies to Python modules with instructions how to install them manually.
+
+You can skip this part if you've already install [Python 2.7](https://www.python.org/download/releases/2.7) and [setuptools](https://pythonhosted.org/an_example_pypi_project/setuptools.html) and successfully [installed all dependencies](#prerequisites).
+
+* Please make sure you've installed [pip](https://pip.pypa.io/en/latest/installing.html) or [easy_install](https://pythonhosted.org/setuptools/easy_install.html#installing-easy-install)
+Note: Easy Install is a python module (easy_install) bundled with [setuptools](https://pythonhosted.org/an_example_pypi_project/setuptools.html#installing-setuptools-and-easy-install) that lets you automatically download, build, install, and manage Python packages.
+
+* Installed [pySerial](https://pypi.python.org/pypi/pyserial) module for Python 2.7.
+pySerial can be installed from PyPI, either manually downloading the files and installing as described below or using:
+```
+$ pip install pyserial
+```
+or:
+```
+easy_install -U pyserial
+```
+* Installed [prettytable](https://code.google.com/p/prettytable/wiki/Installation) module for Python 2.7.
+prettytable can be installed from PyPI, either manually downloading the files and installing as described below or using:
+```
+$ pip install prettytable
+```
+* Installed [IntelHex](https://pypi.python.org/pypi/IntelHex) module.
+IntelHex may be downloaded from https://launchpad.net/intelhex/+download or http://www.bialix.com/intelhex/.
+Assuming Python is properly installed on your platform, installation should just require running the following command from the root directory of the archive:
+```
+sudo python setup.py install
+```
+This will install the intelhex package into your system’s site-packages directory. After that is done, any other Python scripts or modules should be able to import the package using:
+```
+$ python
+Python 2.7.8 (default, Jun 30 2014, 16:03:49) [MSC v.1500 32 bit (Intel)] on win32
+Type "help", "copyright", "credits" or "license" for more information.
+>>> from intelhex import IntelHex
+>>>
+```
+* You can check if you have correctly installed the above modules (or you already have them) by starting Python and importing both modules.
+```
+$ python
+Python 2.7.8 (default, Jun 30 2014, 16:03:49) [MSC v.1500 32 bit (Intel)] on win32
+Type "help", "copyright", "credits" or "license" for more information.
+>>> import serial
+>>> import prettytable
+>>> from intelhex import IntelHex
+>>>
+```
+* Installed Git open source distributed version control system.
+* Installed at least one of the supported by Mbed SDK workspace tools compilers:
+
+Compiler | Mbed SDK Abbreviation | Example Version
+-----------------------|-----------------------|-----------
+Keil ARM Compiler | ARM, uARM | ARM C/C++ Compiler, 5.03 [Build 117]
+GCC ARM | GCC_ARM | gcc version 4.8.3 20131129 (release)
+GCC CodeSourcery | GCC_CS | gcc version 4.8.1 (Sourcery CodeBench Lite 2013.11-24)
+GCC CodeRed | GCC_CR | gcc version 4.6.2 20121016 (release)
+IAR Embedded Workbench | IAR | IAR ANSI C/C++ Compiler V6.70.1.5641/W32 for ARM
+
+* Mbed board. You can find list of supported platforms [here](https://mbed.org/platforms/).
+
+### Getting Mbed SDK sources with test suite
+So you have already installed Python (with required modules) together with at least one supported compiler you will use with your mbed board. Great!
+
+Now let's go further and try to get Mbed SDK with test suite together. So let's clone latest Mbed SDK source code and configure path to our compiler(s) in next few steps.
+
+* Open console and run command below to clone Mbed SDK repository hosted on [Github](https://github.com/mbedmicro/mbed).
+```
+$ git clone https://github.com/mbedmicro/mbed.git
+Cloning into 'mbed'...
+remote: Counting objects: 37221, done.
+remote: Compressing objects: 100% (3/3), done.
+remote: Total 37221 (delta 0), reused 0 (delta 0), pack-reused 37218
+Receiving objects: 100% (37221/37221), 20.38 MiB | 511.00 KiB/s, done.
+Resolving deltas: 100% (24455/24455), done.
+Checking connectivity... done.
+Checking out files: 100% (3994/3994), done.
+```
+* Now you can go to mbed directory you've just cloned and you can see root directory structure of our Mbed SDK library sources. Just type following commands:
+```
+$ cd mbed
+$ ls
+LICENSE MANIFEST.in README.md libraries setup.py travis workspace_tools
+```
+Directory structure we are interested in:
+```
+ mbed/workspace_tools/ - test suite scripts, build scripts etc.
+ mbed/library/tests/ - mbed SDK tests,
+ mbed/library/tests/mbed/ - tests for mbed SDK and peripherals tests,
+ mbed/library/tests/net/echo/ - tests for Ethernet interface,
+ mbed/library/tests/rtos/mbed/ - tests for RTOS.
+```
+
+### Workspace tools
+Workspace tools are set of Python scripts used off-line by Mbed SDK team to:
+* Compile and build mbed SDK,
+* Compile and build libraries included in mbed SDK repo like e.g. ETH (Ethernet), USB, RTOS or CMSIS,
+* Compile, build and run mbed SDK tests,
+* Run test regression locally and in CI server,
+* Get library, target, test configuration (paths, parameters, names etc.).
+
+### Configure workspace tools to work with your compilers
+Before we can run our first test we need to configure our test environment a little!
+Now we need to tell workspace tools where our compilers are.
+
+* Please to go ```mbed/workspace_tools/``` directory and create empty file called ```private_settings.py```.
+```
+$ touch private_settings.py
+```
+* Populate this file the Python code below:
+```python
+from os.path import join
+
+# ARMCC
+ARM_PATH = "C:/Work/toolchains/ARMCompiler_5.03_117_Windows"
+ARM_BIN = join(ARM_PATH, "bin")
+ARM_INC = join(ARM_PATH, "include")
+ARM_LIB = join(ARM_PATH, "lib")
+
+ARM_CPPLIB = join(ARM_LIB, "cpplib")
+MY_ARM_CLIB = join(ARM_PATH, "lib", "microlib")
+
+# GCC ARM
+GCC_ARM_PATH = "C:/Work/toolchains/gcc_arm_4_8/4_8_2013q4/bin"
+
+# GCC CodeSourcery
+GCC_CS_PATH = "C:/Work/toolchains/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
+
+# GCC CodeRed
+GCC_CR_PATH = "C:/Work/toolchains/LPCXpresso_6.1.4_194/lpcxpresso/tools/bin"
+
+# IAR
+IAR_PATH = "C:/Work/toolchains/iar_6_5/arm"
+
+SERVER_ADDRESS = "127.0.0.1"
+LOCALHOST = "127.0.0.1"
+
+# This is moved to separate JSON configuration file used by singletest.py
+MUTs = {
+}
+```
+
+Note: You need to provide the absolute path to your compiler(s) installed on your host machine. Replace corresponding variable values with paths to compilers installed in your system:
+* ```ARM_PATH``` for armcc compiler.
+* ```GCC_ARM_PATH``` for GCC ARM compiler.
+* ```GCC_CS_PATH``` for GCC CodeSourcery compiler.
+* ```GCC_CR_PATH``` for GCC CodeRed compiler.
+* ```IAR_PATH``` for IAR compiler.
+
+If for example you do not use ```IAR``` compiler you do not have to modify anything. Workspace tools will use ```IAR_PATH`` variable only if you explicit ask for it from command line. So do not worry and replace only paths for your installed compilers.
+
+Note: Because this is a Python script and ```ARM_PATH```, ```GCC_ARM_PATH```, ```GCC_CS_PATH```, ```GCC_CR_PATH```, ```IAR_PATH``` are Python string variables please use double backlash or single slash as path's directories delimiter to avoid incorrect path format. For example:
+```python
+ARM_PATH = "C:/Work/toolchains/ARMCompiler_5.03_117_Windows"
+GCC_ARM_PATH = "C:/Work/toolchains/gcc_arm_4_8/4_8_2013q4/bin"
+GCC_CS_PATH = "C:/Work/toolchains/Sourcery_CodeBench_Lite_for_ARM_EABI/bin"
+GCC_CR_PATH = "C:/Work/toolchains/LPCXpresso_6.1.4_194/lpcxpresso/tools/bin"
+IAR_PATH = "C:/Work/toolchains/iar_6_5/arm"
+```
+
+Note: Settings in ```private_settings.py``` will overwrite variables with default values in ```mbed/workspace_tools/settings.py``` file.
+
+## Build Mbed SDK library from sources
+Let's build mbed SDK library off-line from sources using your compiler. We've already cloned mbed SDK sources, we've also installed compilers and added their paths to ```private_settings.py```.
+We now should be ready to use workspace tools script ```build.py``` to compile and build mbed SDK from sources.
+
+We are still using console. You should be already in ```mbed/workspace_tools/``` directory if not go to ```mbed/workspace_tools/``` and type below command:
+```
+$ python build.py -m LPC1768 -t ARM
+```
+or if you want to take advantage from multi-threaded compilation please use option ```-j X``` where ```X``` is number of cores you want to use to compile mbed SDK. See below:
+```
+$ python build.py -m LPC1768 -t ARM -j 4
+Building library CMSIS (LPC1768, ARM)
+Copy: core_ca9.h
+Copy: core_caFunc.h
+...
+Compile: us_ticker_api.c
+Compile: wait_api.c
+Library: mbed.ar
+Creating archive 'C:\temp\x\mbed\build\mbed\TARGET_LPC1768\TOOLCHAIN_ARM_STD\mbed.ar'
+Copy: board.o
+Copy: retarget.o
+
+Completed in: (42.58)s
+
+Build successes:
+ * ARM::LPC1768
+```
+Above command will build mbed SDK for [LPC1768](http://developer.mbed.org/platforms/mbed-LPC1768/) platform using ARM compiler.
+
+Let's have a look at directory structure under ```mbed/build/```. We can see for ```LPC1768``` new directory ```TARGET_LPC1768``` was created. This directory contains all build primitives.
+Directory ```mbed/TARGET_LPC1768/TOOLCHAIN_ARM_STD/``` conteins mbed SDK library ```mbed.ar```. This directory structure also stores all needed headers which you should use with ```mbed.ar``` when building your own software.
+```
+$ tree ./mbed/build/
+Folder PATH listing
+Volume serial number is 006C006F 6243:3EA9
+./MBED/BUILD
++---mbed
+ +---.temp
+ ¦ +---TARGET_LPC1768
+ ¦ +---TOOLCHAIN_ARM_STD
+ ¦ +---TARGET_NXP
+ ¦ +---TARGET_LPC176X
+ ¦ +---TOOLCHAIN_ARM_STD
+ +---TARGET_LPC1768
+ +---TARGET_NXP
+ ¦ +---TARGET_LPC176X
+ ¦ +---TARGET_MBED_LPC1768
+ +---TOOLCHAIN_ARM_STD
+```
+
+Note: Why ```LCP1768```? For this example we are using ```LPC1768``` because this platform supports all compilers so you are sure you only need to specify proper compiler.
+
+If you are not using ARM Compiler replace ```ARM``` with your compiler nickname: ```GCC_ARM```, ```GCC_CS```, ```GCC_CR``` or ```IAR```. For example if you are using IAR type command:
+```
+$ python build.py -m LPC1768 -t IAR
+```
+
+Note: Workspace tools track changes in source code. So if for example mbed SDK or test source code changes ```build.py``` script will recompile project with all dependencies. If there are no changes in code consecutive mbed SDK re-builds using build.py will not rebuild project if this is not necessary. Try to run last command once again, we can see script ```build.py``` will not recompile project (there are no changes):
+```
+$ python build.py -m LPC1768 -t ARM
+Building library CMSIS (LPC1768, ARM)
+Building library MBED (LPC1768, ARM)
+
+Completed in: (0.15)s
+
+Build successes:
+ * ARM::LPC1768
+```
+
+### build.py script
+
+Build script located in mbed/workspace_tools/ is our core script solution to drive compilation, linking and building process for:
+
+* mbed SDK (with libs like Ethernet, RTOS, USB, USB host).
+* Tests which also can be linked with libraries like RTOS or Ethernet.
+
+Note: Test suite also uses the same build script, inheriting the same properties like auto dependency tracking and project rebuild in case of source code changes.
+
+Build.py script is a powerful tool to build mbed SDK for all available platforms using all supported by mbed cross-compilers. Script is using our workspace tools build API to create desired platform-compiler builds. Use script option ```--h``` (help) to check all script parameters.
+```
+$ python build.py --help
+```
+
+* The command line parameter ```-m``` specifies the MCUs/platforms for which you want to build the mbed SDK. More than one MCU(s)/platform(s) may be specified with this parameter using comma as delimiter.
+Example for one platform build:
+```
+$ python build.py -m LPC1768 -t ARM
+```
+or for many platforms:
+```
+$ python build.py -m LPC1768,NUCLEO_L152RE -t ARM
+```
+
+* Parameter ```-t``` defined which toolchain should be used for mbed SDK build. You can build Mbed SDK for multiple toolchains using one command.
+Below example (note there is no space after commas) will compile mbed SDK for Freescale Freedom KL25Z platform using ARM and GCC_ARM compilers:
+```
+$ python build.py -m KL25Z -t ARM,GCC_ARM
+```
+
+* You can combine this technique to compile multiple targets with multiple compilers.
+Below example will compile mbed SDK for Freescale's KL25Z and KL46Z platforms using ARM and GCC_ARM compilers:
+```
+$ python build.py -m KL25Z,KL46Z -t ARM,GCC_ARM
+```
+
+* Building libraries included in mbed SDK's source code. Parameters ```-r```, ```-e```, ```-u```, ```-U```, ```-d```, ```-b``` will add ```RTOS```, ```Ethernet```, ```USB```, ```USB Host```, ```DSP```, ```U-Blox``` libraries respectively.
+Below example will build Mbed SDK library for for NXP LPC1768 platform together with RTOS (```-r``` switch) and Ethernet (```-e``` switch) libraries.
+```
+$ python build.py -m LPC1768 -t ARM -r -e
+Building library CMSIS (LPC1768, ARM)
+Building library MBED (LPC1768, ARM)
+Building library RTX (LPC1768, ARM)
+Building library RTOS (LPC1768, ARM)
+Building library ETH (LPC1768, ARM)
+
+Completed in: (0.48)s
+
+Build successes:
+ * ARM::LPC1768
+```
+
+* If you’re unsure which platforms and toolchains are supported please use switch ```-S``` to print simple matrix of platform to compiler dependencies.
+```
+$ python python build.py -S
++-------------------------+-----------+-----------+-----------+-----------+-----------+-----------+------------+---------------+
+| Platform | ARM | uARM | GCC_ARM | IAR | GCC_CR | GCC_CS | GCC_CW_EWL | GCC_CW_NEWLIB |
++-------------------------+-----------+-----------+-----------+-----------+-----------+-----------+------------+---------------+
+| APPNEARME_MICRONFCBOARD | Supported | Default | Supported | - | - | - | - | - |
+| ARCH_BLE | Default | - | Supported | Supported | - | - | - | - |
+| ARCH_GPRS | Supported | Default | Supported | Supported | Supported | - | - | - |
+...
+| UBLOX_C029 | Supported | Default | Supported | Supported | - | - | - | - |
+| WALLBOT_BLE | Default | - | Supported | Supported | - | - | - | - |
+| XADOW_M0 | Supported | Default | Supported | Supported | Supported | - | - | - |
++-------------------------+-----------+-----------+-----------+-----------+-----------+-----------+------------+---------------+
+*Default - default on-line compiler
+*Supported - supported off-line compiler
+
+Total platforms: 90
+Total permutations: 297
+```
+
+Above list can be overwhelming so please do not hesitate to use switch ```-f``` to filter ```Platform``` column.
+```
+$ python build.py -S -f ^K
++--------------+-----------+---------+-----------+-----------+--------+--------+------------+---------------+
+| Platform | ARM | uARM | GCC_ARM | IAR | GCC_CR | GCC_CS | GCC_CW_EWL | GCC_CW_NEWLIB |
++--------------+-----------+---------+-----------+-----------+--------+--------+------------+---------------+
+| K20D50M | Default | - | Supported | Supported | - | - | - | - |
+| K22F | Default | - | Supported | Supported | - | - | - | - |
+| K64F | Default | - | Supported | Supported | - | - | - | - |
+| KL05Z | Supported | Default | Supported | Supported | - | - | - | - |
+| KL25Z | Default | - | Supported | Supported | - | - | Supported | Supported |
+| KL43Z | Default | - | Supported | - | - | - | - | - |
+| KL46Z | Default | - | Supported | Supported | - | - | - | - |
+| NRF51_DK | Default | - | Supported | Supported | - | - | - | - |
+| NRF51_DK_OTA | Default | - | Supported | - | - | - | - | - |
++--------------+-----------+---------+-----------+-----------+--------+--------+------------+---------------+
+*Default - default on-line compiler
+*Supported - supported off-line compiler
+
+Total platforms: 9
+Total permutations: 28
+```
+or just give platform name:
+```
+$ python build.py -S -f LPC1768
++----------+---------+-----------+-----------+-----------+-----------+-----------+------------+---------------+
+| Platform | ARM | uARM | GCC_ARM | IAR | GCC_CR | GCC_CS | GCC_CW_EWL | GCC_CW_NEWLIB |
++----------+---------+-----------+-----------+-----------+-----------+-----------+------------+---------------+
+| LPC1768 | Default | Supported | Supported | Supported | Supported | Supported | - | - |
++----------+---------+-----------+-----------+-----------+-----------+-----------+------------+---------------+
+*Default - default on-line compiler
+*Supported - supported off-line compiler
+
+Total platforms: 1
+Total permutations: 6
+```
+
+* You can be more verbose ```-v``` especially if you want to see each compilation / linking command build.py is executing:
+```
+$ python build.py -t GCC_ARM -m LPC1768 -j 8 -v
+Building library CMSIS (LPC1768, GCC_ARM)
+Copy: LPC1768.ld
+Compile: startup_LPC17xx.s
+[DEBUG] Command: C:/Work/toolchains/gcc_arm_4_8/4_8_2013q4/bin\arm-none-eabi-gcc
+-x assembler-with-cpp -c -Wall -Wextra -Wno-unused-parameter -Wno-missing-field-initializers
+-fmessage-length=0 -fno-exceptions -fno-builtin -ffunction-sections -fdata-sections -MMD
+-fno-delete-null-pointer-checks -fomit-frame-pointer -mcpu=cortex-m3 -mthumb -O2
+-DTARGET_LPC1768 -DTARGET_M3 -DTARGET_CORTEX_M -DTARGET_NXP -DTARGET_LPC176X
+-DTARGET_MBED_LPC1768 -DTOOLCHAIN_GCC_ARM -DTOOLCHAIN_GCC -D__CORTEX_M3 -DARM_MATH_CM3
+-DMBED_BUILD_TIMESTAMP=1424903604.77 -D__MBED__=1 -IC:\Work\mbed\libraries\mbed\targets\cmsis
+-IC:\Work\mbed\libraries\mbed\targets\cmsis\TARGET_NXP
+-IC:\Work\mbed\libraries\mbed\targets\cmsis\TARGET_NXP\TARGET_LPC176X -IC:\Work\mbed\libraries\mbed\targets\cmsis\TARGET_NXP\TARGET_LPC176X\TOOLCHAIN_GCC_ARM
+-o C:\Work\mbed\build\mbed\.temp\TARGET_LPC1768\TOOLCHAIN_GCC_ARM\TARGET_NXP\TARGET_LPC176X\TOOLCHAIN_GCC_ARM\startup_LPC17xx.o
+C:\Work\mbed\libraries\mbed\targets\cmsis\TARGET_NXP\TARGET_LPC176X\TOOLCHAIN_GCC_ARM\startup_LPC17xx.s
+[DEBUG] Return: 0
+...
+```
+
+## CppUCheck analysis
+[Cppcheck](http://cppcheck.sourceforge.net/) is a static analysis tool for C/C++ code. Unlike C/C++ compilers and many other analysis tools it does not detect syntax errors in the code. Cppcheck primarily detects the types of bugs that the compilers normally do not detect. The goal is to detect only real errors in the code (i.e. have zero false positives).
+
+Prerequisites:
+* Please install ```CppCheck``` on your system before you want to use it with build scripts.
+* You should also add Cppcheck to your system path.
+
+```build.py``` script supports switching between compilation and building and just static code analysis testing. You can use switch ```--cppcheck``` to perform CppCheck static code analysis.
+
+* When you are using --cppcheck switch all macros, toolchain dependencies etc. are preserved so you are sure you are checking exactly the same code you would compile for your application.
+
+* Cppcheck analysis can take up to few minutes on slower machines.
+
+* Usually you will use switches ```-t``` and ```-m``` to define toolchain and MCU (platform) respectively. You should do the same in case of CppCheck analysis. Please note that build script can also compile and build RTOS, Ethernet library etc. If you want to check those just use corresponding build script switches (e.g. ```-r```, ```-e```, ...).
+
+Example:
+```
+$ python build.py -t uARM -m NUCLEO_F334R8 --cppcheck
+```
+
+# make.py script
+```make.pt``` is a ```mbed/workspace_tools/``` script used to build tests (we call them sometimes 'programs') one by one manually. Script allows you to flash board with test and execute it. This is deprecated functionality and will not be described here. Instead please use ```singletest.py``` file to build mbed SDK, tests and run automation for test cases included in ```mbedmicro/mbed```.
+Note: ```make.py``` script depends on existing already built mked SDK and library sources so you need to pre-build mbed SDK and for example RTOS library to link 'program' (test) with mebd SDK and RTOS library. To pre-build mbed SDK please use ```build.py``` script.
+
+Just for sake of example please see few ways to use ```make.py``` together with Freedom K64F board.
+
+* We need to build mbed SDK (in directory ```mbed/build/```:
+```
+$ python build.py -t GCC_ARM -m K64F -j 8
+Building library CMSIS (K64F, GCC_ARM)
+Building library MBED (K64F, GCC_ARM)
+
+Completed in: (0.59)s
+
+Build successes:
+ * GCC_ARM::K64F
+```
+* We can print all 'programs' (test cases) ```make.py``` can build for us:
+```
+$ python make.py
+.
+[ 0] MBED_A1: Basic
+[ 1] MBED_A2: Semihost file system
+[ 2] MBED_A3: C++ STL
+[ 3] MBED_A4: I2C TMP102
+.
+```
+For example 'program' under index ```2``` is ```MBED_A3``` test case we can build and flash onto K64F board.
+* Building test with ```make.py``` by specifying test case name with ```-n``` option:
+```
+$ python make.py -t GCC_ARM -m K64F -n MBED_A3
+Building project STL (K64F, GCC_ARM)
+Compile: main.cpp
+[Warning] main.cpp@76: In function 'int main()': deprecated conversion from string constant to 'char*' [-Wwrite-strings]
+.
+.
+.
+[Warning] main.cpp@76: In function 'int main()': deprecated conversion from string constant to 'char*' [-Wwrite-strings]
+Compile: test_env.cpp
+Link: stl
+Elf2Bin: stl
+Image: C:\Work\mbed\build\test\K64F\GCC_ARM\MBED_A3\stl.bin
+```
+Because we previously have built mbed SDK we are now able to drive test case compilation and linking with mbed SDK and produce ```MBED_A3``` test case binary in build directory:
+```
+C:\Work\mbed\build\test\K64F\GCC_ARM\MBED_A3\stl.bin
+```
+
+For more help type ```$ python make.py --help``` in your command line.
+
+# project.py script
+```project.py``` script is used to export test cases ('programs') from test case portfolio to off-line IDE. This is a easy way to export test project to IDEs such as:
+* codesourcery.
+* coide.
+* ds5_5.
+* emblocks.
+* gcc_arm.
+* iar.
+* kds.
+* lpcxpresso.
+* uvision.
+
+You can export project using command line. All you need to do is to specify mbed platform name (option ```-m```), your IDE (option ```-i```) and project name you want to export (option ```-n``` or (option ```-p```).
+
+In below example we export our project so we can work on it using GCC ARM cross-compiler. Building mechanism used to drive exported build will be ```Make```.
+```
+$ python project.py -m K64F -n MBED_A3 -i gcc_arm
+Copy: test_env.h
+Copy: AnalogIn.h
+Copy: AnalogOut.h
+.
+.
+.
+Copy: K64FN1M0xxx12.ld
+Copy: main.cpp
+
+Successful exports:
+ * K64F::gcc_arm C:\Work\mbed\build\export\MBED_A3_gcc_arm_K64F.zip
+```
+You can see exporter placed compressed project export in ```zip``` file in ```mbed/build/export/``` directory.
+
+Example export file ```MBED_A3_gcc_arm_K64F.zip``` structure:
+```
+MBED_A3
+├───env
+└───mbed
+ ├───api
+ ├───common
+ ├───hal
+ └───targets
+ ├───cmsis
+ │ └───TARGET_Freescale
+ │ └───TARGET_MCU_K64F
+ │ └───TOOLCHAIN_GCC_ARM
+ └───hal
+ └───TARGET_Freescale
+ └───TARGET_KPSDK_MCUS
+ ├───TARGET_KPSDK_CODE
+ │ ├───common
+ │ │ └───phyksz8081
+ │ ├───drivers
+ │ │ ├───clock
+ │ │ ├───enet
+ │ │ │ └───src
+ │ │ ├───interrupt
+ │ │ └───pit
+ │ │ ├───common
+ │ │ └───src
+ │ ├───hal
+ │ │ ├───adc
+ │ │ ├───can
+ │ │ ├───dac
+ │ │ ├───dmamux
+ │ │ ├───dspi
+ │ │ ├───edma
+ │ │ ├───enet
+ │ │ ├───flextimer
+ │ │ ├───gpio
+ │ │ ├───i2c
+ │ │ ├───llwu
+ │ │ ├───lptmr
+ │ │ ├───lpuart
+ │ │ ├───mcg
+ │ │ ├───mpu
+ │ │ ├───osc
+ │ │ ├───pdb
+ │ │ ├───pit
+ │ │ ├───pmc
+ │ │ ├───port
+ │ │ ├───rcm
+ │ │ ├───rtc
+ │ │ ├───sai
+ │ │ ├───sdhc
+ │ │ ├───sim
+ │ │ ├───smc
+ │ │ ├───uart
+ │ │ └───wdog
+ │ └───utilities
+ │ └───src
+ └───TARGET_MCU_K64F
+ ├───device
+ │ ├───device
+ │ │ └───MK64F12
+ │ └───MK64F12
+ ├───MK64F12
+ └───TARGET_FRDM
+```
+
+After unpacking exporter ```zip``` file we can go to directory and see files inside MBED_A3 directory:
+```
+$ ls
+GettingStarted.htm Makefile env main.cpp mbed
+```
+Exporter generated for us ```Makefile``` so now we can build our software:
+```
+$ make -j 8
+.
+.
+.
+ text data bss dec hex filename
+ 29336 184 336 29856 74a0 MBED_A3.elf
+```
+
+We can see root directory of exporter project is now populated with binary files:
+* MBED_A3.bin.
+* MBED_A3.elf .
+* MBED_A3.hex.
+You have also map file ```MBED_A3.map``` for your disposal.
+```
+$ ls
+GettingStarted.htm MBED_A3.bin MBED_A3.elf MBED_A3.hex MBED_A3.map Makefile env main.cpp main.d main.o mbed
+```
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/docs/COMMITTERS.md b/tmk_core/tool/mbed/mbed-sdk/docs/COMMITTERS.md
new file mode 100644
index 000000000..ecb092dad
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/docs/COMMITTERS.md
@@ -0,0 +1,269 @@
+# Committing changes to mbedmicro/mbed
+* Our current branching model is very simple. We are using ```master``` branch to merge all pull requests.
+* Based on stable ```SHA``` version of ```master``` branch we decide to release and att he same time ```tag``` our build release.
+* Our current release versioning follows simple integer version: ```94```, ```95```, ```96``` etc.
+
+# Committer Guide
+
+## How to decide what release(s) should be patched
+This section provides a guide to help a committer decide the specific base branch that a change set should be merged into.
+
+Currently our default branch is ```master``` branch. All pull requests should be created against ```master``` branch.
+mbed SDK is released currently on master branch under certain tag name (see [Git tagging basics]( http://git-scm.com/book/en/v2/Git-Basics-Tagging)). You can see mbed SDK tags and switch between them to for example go back to previous mbed SDK release.
+```
+$ git tag
+```
+
+Please note: mebd SDK ```master``` branch's ```HEAD``` is our latest code and may not be as stable as you expect. We are putting our best effort to run regression testing (in-house) against pull requests and latest code.
+Each commit to ```master``` will trigger [GitHub's Travis Continuous Integration](https://travis-ci.org/mbedmicro/mbed/builds).
+
+### Pull request
+Please send pull requests with changes which are:
+* Complete (your code will compile and perform as expected).
+* Tested on hardware.
+ * You can use included mbed SDK test suite to perform testing. See TESTING.md.
+ * If your change, feature do not have a test case included please add one (or more) to cover new functionality.
+ * If you can't test your functionality describe why.
+* Documented source code:
+ * New, modified functions have descriptive comments.
+ * You follow coding rules and styles provided by mbed SDK project.
+* Documented pull request description:
+ * Description of changes is added - explain your change / enhancement.
+ * References to existing issues, other pull requests or forum discussions are included.
+ * Test results are added.
+
+After you send us your pull request our Gate Keeper will change the state of pull request to:
+• ``` enhancement``` or ```bug``` when pull request creates new improvement or fixed issue.
+Than we will set for you labels:
+• ```review``` to let you know your pull request is under review and you can expect review related comments from us.
+• ```in progress``` when you pull request requires some additional change which will for now block this pull request from merging.
+At the end we will remove ```review``` label and merge your change if everything goes well.
+
+## C++ coding rules & coding guidelines
+### Rules
+* The mbed SDK code follows K&R style (Reference: [K&R style](http://en.wikipedia.org/wiki/Indent_style#K.26R_style)) with at least 2 exceptions which can be found in the list below the code snippet:
+
+```c++
+static const PinMap PinMap_ADC[] = {
+ {PTC2, ADC0_SE4b, 0},
+ {NC , NC , 0}
+};
+
+uint32_t adc_function(analogin_t *obj, uint32_t options)
+{
+ uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT;
+ switch (options) {
+ case 1:
+ timeout = 6;
+ break;
+ default:
+ timeout = 10;
+ break;
+ }
+
+ while (!adc_hal_is_conversion_completed(instance, 0)) {
+ if (timeout == 0) {
+ break;
+ } else {
+ timeout--;
+ }
+ }
+
+ if (obj->adc == ADC_CHANNEL0) {
+ adc_measure_channel(instance);
+ adc_stop_channel(instance);
+ } else {
+ error("channel not available");
+ }
+
+#if DEBUG
+ for (uint32_t i = 0; i < 10; i++) {
+ printf("Loop : %d", i);
+ }
+#endif
+ return adc_hal_get_conversion_value(instance, 0);
+}
+```
+* Indentation - 4 spaces. Please do not use tabs!
+* Braces - K&R, except for functions where the opening brace is on the new line.
+* 1 TBS - use braces for statements ```if```, ```else```, ```while```, ```for``` (exception from K&R) Reference: [1TBS](http://en.wikipedia.org/wiki/Indent_style#Variant:_1TBS)).
+* One line per statement.
+* Preprocessor macro starts at the beginning of a new line, the code inside is indented accordingly the code above it.
+* Cases within switch are indented (exception from K&R).
+* Space after statements if, while, for, switch, same applies to binary and ternary operators.
+* Each line has preferably at most 120 characters.
+* For pointers, ```*``` is adjacent to a name (analogin_t *obj).
+* Don't leave trailing spaces at the end of lines.
+* Empty lines should have no trailing spaces.
+* Unix line endings are default option for files.
+* Use capital letters for macros.
+* A file should have an empty line at the end.
+and:
+* We are not using C++11 yet so do not write code compliant to this standard.
+* We are not using libraries like ```BOOST``` so please so not include any ```BOOST``` headers to your code.
+* C++ & templates: please take under consideration templates are not fully supported by cross-compilers. You may have difficulties compiling template code few cross-compilers so make sure your template code compilers for more than one compiler.
+
+### Naming conventions
+Classes:
+* Begins with a capital letter, and each word in it begins also with a capital letter (```AnalogIn```, ```BusInOut```).
+* Methods contain small letters, distinct words separated by underscore.
+* Private members starts with an underscore.
+
+User defined types (typedef):
+* Structures - suffix ```_t``` - to denote it is user defined type
+* Enumeration - the type name and values name - same naming convention as classes (e.g ```MyNewEnum```)
+
+Functions:
+* Contain lower case letters (as methods within classes)
+* Distinct words separated by underscore (```wait_ms```, ```read_u16```)
+* Please make sure that in your module all functions have unique prefix so when your module is compiled with other modules function names (and e.g. extern global variable names) are not in naming conflict.
+
+Example code look&feel:
+```c++
+#define ADC_INSTANCE_SHIFT 8
+
+class AnalogIn {
+public:
+ /** Create an AnalogIn, connected to the specified pin
+ *
+ * @param pin AnalogIn pin to connect to
+ * @param name (optional) A string to identify the object
+ */
+ AnalogIn(PinName pin) {
+ analogin_init(&_adc, pin);
+ }
+
+ /** Read the input voltage, represented as a float in the range [0.0, 1.0]
+ *
+ * @returns
+ * A floating-point value representing the current input voltage, measured as a percentage
+ */
+ uint32_t read() {
+ return analogin_read(&_adc, operation);
+ }
+
+protected:
+ analogin_t _adc;
+};
+
+typedef enum {
+ ADC0_SE0 = (0 << ADC_INSTANCE_SHIFT) | 0,
+} ADCName;
+
+struct analogin_s {
+ ADCName adc;
+};
+
+typedef struct analogin_s analogin_t;
+```
+### Doxygen documentation
+All functions / methods should contain a documentation using doxygen javadoc in a header file. More information regarding writing API Documentation, follow [this](https://mbed.org/handbook/API-Documentation) link.
+
+Example of well documentet code:
+```c++
+#ifndef ADC_H
+#define ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** ADC Measurement method
+ *
+ * @param obj Pointer to the analogin object.
+ * @param options Options to be enabled by ADC peripheral.
+ *
+ * @returns
+ * Measurement value on defined ADC channel.
+ */
+uint32_t adc_function(analogin_t *obj, uint32_t options)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+```
+### C/C++ Source code indenter
+In Mbed project you can use AStyle (Reference: [Artistic Style](http://astyle.sourceforge.net/)) source code indenter to help you auto format your source code. It will for sure not correct all your coding styles but for sure will eliminate most of them. You can download AStyle from this location.
+
+Official Mbed SDK styles include below AStyle styles (defined by command line switched):
+```
+--style=kr --indent=spaces=4 --indent-switches
+```
+To format your file you can execute below command. Just replace ```$(FULL_CURRENT_PATH)``` with path to your source file.
+```
+$ astyle.exe --style=kr --indent=spaces=4 --indent-switches $(FULL_CURRENT_PATH)
+```
+
+## Python coding rules & coding guidelines
+Some of our tools in workspace_tools are written in ```Python 2.7```. In case of developing tools for python we prefer to keep similar code styles across all Python source code. Please note that not all rules must be enforced. For example we do not limit you to 80 characters per line, just be sure your code can fit to widescreen display.
+
+Please stay compatible with ```Python 2.7``` but nothing stops you to write your code so in the future it will by Python 3 friendly.
+
+Please check our Python source code (especially ```test_api.py``` and ```singletest.py```) to get notion of how your new code should look like). We know our code is not perfect but please try to fit the same coding style to existing code so source looks consistent and is not series of different flavors.
+
+Some general guidelines:
+* Use Python idioms, please refer to one of many on-line guidelines how to write Pythonic code: [Code Like a Pythonista: Idiomatic Python](http://python.net/~goodger/projects/pycon/2007/idiomatic/handout.html).
+* Please do not use TABs. Please use 4 spaces instead for indentations.
+* Please put space character between operators, after comma etc.
+* Please document your code, write comments and ```doc``` sections for each function or class you implement.
+
+### Static Code Analizers for Python
+If you are old-school developer for sure you remember tools like lint. "lint was the name originally given to a particular program that flagged some suspicious and non-portable constructs (likely to be bugs) in C language source code." Now lint-like programs are used to check similar code issues for multiple languages, also for Python. Please do use them if you want to commit new code to workspace_tools and other mbed SDK Python tooling.
+
+Below is the list Python lint tools you may want to use:
+
+* [pyflakes](https://pypi.python.org/pypi/pyflakes) - Please scan your code with pyflakes and remove all issues reported by it. If you are unsure if something should be modified or not you can skip lint report related fix and report this issue as possible additional commit in your pull request description.
+
+* [pylint](http://www.pylint.org/) - Please scan your code with pylint and check if there are any issues which can be resolved and are obvious "to fix" bugs. For example you may forgot to add 'self' as first parameter in class method parameter list or you are calling unknown functions / functions from not imported modules.
+
+* [pychecker](http://pychecker.sourceforge.net/) - optional, but more the merrier ;)
+
+Example Python look&feel:
+```python
+class HostRegistry:
+ """ Class stores registry with host tests and objects representing them
+ """
+ HOST_TESTS = {} # host_test_name -> host_test_ojbect
+
+ def register_host_test(self, ht_name, ht_object):
+ """ Registers (removes) host test by name from HOST_TESTS registry
+ if host test is not already registered (check by name).
+ """
+ if ht_name not in self.HOST_TESTS:
+ self.HOST_TESTS[ht_name] = ht_object
+
+ def unregister_host_test(self):
+ """ Unregisters (removes) host test by name from HOST_TESTS registry.
+ """
+ if ht_name in HOST_TESTS:
+ self.HOST_TESTS[ht_name] = None
+
+ def get_host_test(self, ht_name):
+ """ Returns HOST_TEST if host name is valid.
+ In case no host test is available return None
+ """
+ return self.HOST_TESTS[ht_name] if ht_name in self.HOST_TESTS else None
+
+ def is_host_test(self, ht_name):
+ """ Function returns True if host name is valid (is in HOST_TESTS)
+ """
+ return ht_name in self.HOST_TESTS
+```
+
+## Testing
+Please refer to TESTING.md document for detais regarding mbed SDK test suite and build scripts included in ```mbed/workspace_tools/```.
+
+## Before pull request checklist
+* Your pull request description section contains:
+ * Rationale – tell us why you submitted this pull request. This is your change to write us summary of your change.
+ * Description – describe changes you’ve made and tell us which new features / functionalities were implemented.
+ * Manual / Cookbook / Handbook – you can put here manual, cookbook or handbook related to your change / enhancement. Your documentation can stay with pull request.
+ * Test results (if applicable).
+* Make sure you followed project's coding rules and styles.
+* No dependencies are created to external C/C++ libraries which are not included already in our repository.
+* Please make sure that in your module all functions have unique prefix (no name space collisions).
+* You reused existing functionality, please do not add or rewrite existing code. E.g. use mbed’s ```FunctionPointer``` if possible to store your function pointers. Do not write another wrapper for it. We already got one. If some functionality is missing, just add it! Extend our APIs wisely!
+* Were you consistent? Please continue using style / code formatting, variables naming etc. in file they are modifying.
+* Your code compiles and links. Also doesn’t generate additional compilation warnings.
diff --git a/tmk_core/tool/mbed/mbed-sdk/docs/TESTING.md b/tmk_core/tool/mbed/mbed-sdk/docs/TESTING.md
new file mode 100644
index 000000000..9d17e4d90
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/docs/TESTING.md
@@ -0,0 +1,877 @@
+# Mbed SDK automated test suite
+## Introduction
+
+Test suit allows users to run locally on their machines Mbed SDK’s tests included in Mbed SDK repository. It also allows users to create their own tests and for example add new tests to test set as they progress with their project. If test is generic enough it could be included into official Mbed SDK test pool just do it via normal pull request!
+
+Each test is supervised by python script called “host test†which will at least Test suite is using build script API to compile and build test source together with required by test libraries like CMSIS, Mbed, Ethernet, USB etc.
+
+## What is host test?
+Test suite supports test supervisor concept. This concept is realized by separate Python script called ```host test```. Host tests can be found in ```mbed/workspace_tools/host_tests/``` directory. Note: In newer mbed versions (mbed OS) host tests will be separate library.
+
+Host test script is executed in parallel with test runner to monitor test execution. Basic host test just monitors device's default serial port for test results returned by test runner. Simple tests will print test result on serial port. In other cases host tests can for example judge by test results returned by test runner is test passed or failed. It all depends on test itself.
+
+In some cases host test can be TCP server echoing packets from test runner and judging packet loss. In other cases it can just check if values returned from accelerometer are actually valid (sane).
+
+## Test suite core: singletest.py script
+
+```singletest.py``` script located in ```mbed/workspace_tools/``` is a test suite script which allows users to compile, build tests and test runners (also supports CppUTest unit test library). Script also is responsible for test execution on devices selected by configuration files.
+
+### Parameters of singletest.py
+
+Test execution script ```singletest.py``` is a fairly powerful tool to run tests for mbed SDK platform. It is flexible and allows users to configure test execution process and define which mbed platforms will be tested.
+
+By specifying external configuration files (in JSON format) you can gain flexibility and prepare many different test scenarios. Just pass configuration file names to your script and run it.
+
+#### MUTs Specification
+You can easily configure your MUTs (Mbed Under Test) by creating configuration file with MUTs description.
+Note: This configuration file must be in [JSON format](http://www.w3schools.com/json/).
+Note: Unfortunately JSON format is not allowing you to have comments inside JSON code.
+
+Let’s see some example and let's try to configure small "test farm" with three devices connected to your host computer. In this example no peripherals (like SD card or EEPROM) are connected to our Mbed boards. We will use three platforms in this example:
+* [NXP LPC1768](https://mbed.org/platforms/mbed-LPC1768) board.
+* \[Freescale KL25Z](https://mbed.org/platforms/KL25Z) board and
+* [STMicro Nucleo F103RB](https://mbed.org/platforms/ST-Nucleo-F103RB) board.
+After connecting boards to our host machine (PC) we can check which serial ports and disks they occupy. For our example let's assume that:
+* ```LPC1768``` serial port is on ```COM4``` and disk drive is ```J:```.
+* ```KL25Z``` serial port is on ```COM39``` and disk drive is ```E:```.
+* ```NUCLEO_F103RB``` serial port is on ```COM11``` and disk drive is ```I:```.
+If you are working under Linux your port and disk could look like /dev/ttyACM5 and /media/usb5.
+
+This information is needed to create ```muts_all.json``` configuration file. You can create in in ```mbed/workspace_tools/``` directory:
+```
+$ touch muts_all.json
+```
+
+Its name will be passed to ```singletest.py``` script after ```-M``` (MUTs specification) switch. Let’s see how this file's content would look like in our example below:
+```json
+{
+ "1" : {"mcu": "LPC1768",
+ "port":"COM4",
+ "disk":"J:\\",
+ "peripherals": []
+ },
+
+ "2" : {"mcu": "KL25Z",
+ "port":"COM39",
+ "disk":"E:\\",
+ "peripherals": []
+ },
+
+ "3" : {"mcu": "NUCLEO_F103RB",
+ "port":"COM11",
+ "disk":"I:\\",
+ "peripherals": []
+ }
+}
+```
+
+Note: We will leave field ```peripherals``` empty for the sake of this example. We will explain it later. All you need to do now is to properly fill fields ```mcu```, ```port``` and ```disk```.
+
+Note: Please make sure files muts_all.json and test_spec.json are in workspace_tools/ directory. We will assume in this example they are.
+Where to find ```mcu``` names? You can use option ```-S``` of ```build.py``` script (in ```mbed/workspace_tools/``` directory) to check all supported off-line MCUs names.
+
+Note: If you update mbed device firmware or even disconnect / reconnect mbed device you may find that serial port / disk configuration changed. You need to update configuration file accordingly or you will face connection problems and obviously tests will not run.
+
+#### Peripherals testing
+When using MUTs configuration file (switch ```-M```) you can define in MUTs JSON file peripherals connected to your device:
+```json
+{
+ "1" : {"mcu" : "KL25Z",
+ "port" : "COM39",
+ "disk" : "E:\\",
+ "peripherals" : ["SD", "24LC256"]}
+}
+```
+You can force test suite to run only common tests (switch ```-C```) or only peripheral tests (switch ```-P```).
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -C
+```
+will not include tests for SD card and EEPROM 24LC256.
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -P
+```
+will only run tests bind to SD card and EEPROM 24LC256.
+
+Note: option ```-P``` is useful for example in cases when you have same platform and different shields you want to test. No need to test common part all the time (timers, RTC, RTOS etc.). You can force to test peripherals only on some devices and for example only common tests on other devices.
+
+#### Additional MUTs configuration file settings
+You can add extra information to each MUT configuration. In particular you can specify which flashing (binary copy method) should be used, how to reset target and for example set reset timeout (used to delay test execution just after reset).
+
+muts_all.json:
+```json
+{
+ "1" : {"mcu" : "LPC1768",
+ "port" : "COM77",
+ "disk" : "G:\\",
+ "peripherals" : ["TMP102", "digital_loop", "port_loop", "analog_loop", "SD"]},
+
+ "2" : {"mcu" : "KL25Z",
+ "port" : "COM89",
+ "disk" : "F:\\",
+ "peripherals" : ["SD", "24LC256", "KL25Z"],
+ "copy_method" : "copy",
+ "reset_type" : "default",
+ "reset_tout" : "2"},
+
+ "3" : {"mcu" : "LPC11U24",
+ "port" : "COM76",
+ "disk" : "E:\\",
+ "peripherals" : []}
+}
+```
+Please note that for MUT no. 2 few extra parameters were defined: ```copy_method```, ```reset_type``` and ```reset_tout```. Using this extra options you can tell test suite more about MUT you are using. This will allow you to be more flexible in terms of how you configure and use your MUTs.
+
+* ```copy_method``` - STRING - tells test suite which binary copy method should be used.
+You may notice that ```singletest.py``` command line help contains description about:
+ * Option ```-c``` (in MUTs file called ```copy_method```) with available copy methods supported by test suite plugin system.
+ * Option ```-r``` (in MUTs file called reset_type) with available reset methods supported by test suite plugin system.
+* ```reset_type``` - STRING - some boards may require special reset handling, for example vendor specific command must be executed to reset device.
+* ```reset_tout``` - INTEGER - extra timeout just after device is reseted. May be used to wait for few seconds so device may finish booting, flashing data internally etc.
+
+Part of help listing for singletest.py:
+```
+ -c COPY_METHOD, --copy-method=COPY_METHOD
+ Select binary copy (flash) method. Default is Python's
+ shutil.copy() method. Plugin support: copy, cp,
+ default, eACommander, eACommander-usb, xcopy
+ -r MUT_RESET_TYPE, --reset-type=MUT_RESET_TYPE
+ Extra reset method used to reset MUT by host test
+ script. Plugin support: default, eACommander,
+ eACommander-usb
+```
+
+----
+
+Now we've already defined how our devices are connected to our host PC. We can continue and define which of this MUTs will be tested and which compilers we will use to compile and build Mbed SDK and tests. To do so we need to create test specification file (let's call it ```test_spec.json```) and put inside our configuration file information about which MUTs we actually want to test. We will pass this file's name to ```singletest.py``` script using ```-i``` switch.
+
+Below we can see how sample ```test_spec.json``` file content could look like. (I've included all possible toolchains, we will change it in a moment):
+```json
+{
+ "targets": {
+ "LPC1768" : ["ARM", "uARM", "GCC_ARM", "GCC_CS", "GCC_CR", "IAR"],
+ "KL25Z" : ["ARM", "GCC_ARM"],
+ "NUCLEO_F103RB" : ["ARM", "uARM"]
+ }
+}
+```
+Above example configuration will force tests for LPC1768, KL25Z, NUCLEO_F103RB platforms and:
+
+* Compilers: ```ARM```, ```uARM```, ```GCC_ARM```, ```GCC_CS```, ```GCC_CR``` and ```IAR``` will be used to compile tests for NXP's ```LPC1768```.
+* Compilers: ```ARM``` and ```GCC_ARM``` will be used for Freescales' ```KL25Z``` platform.
+* Compilers: ```ARM``` and ```uARM``` will be used for STMicro's ```NUCLEO_F103RB``` platform.
+
+For our example purposes let's assume we only have Keil ARM compiler, so let's change configuration in ```test_spec.json``` file and reduce number of compiler to those we actually have:
+```json
+{
+ "targets": {
+ "LPC1768" : ["ARM", "uARM"],
+ "KL25Z" : ["ARM"],
+ "NUCLEO_F103RB" : ["ARM", "uARM"]
+ }
+}
+```
+#### Run your tests
+
+After you configure all your MUTs and compilers you are ready to run tests. Make sure your devices are connected and your configuration files reflect your current configuration (serial ports, devices). Go to workspace_tools directory in your mbed location.
+```
+$ cd workspace_tools/
+```
+and execute test suite script.
+```
+$ python singletest.py -i test_spec.json -M muts_all.json
+```
+To check your configuration before test execution please use ```--config``` switch:
+```
+$ python singletest.py -i test_spec.json -M muts_all.json --config
+MUTs configuration in m.json:
++-------+-------------+---------------+------+-------+
+| index | peripherals | mcu | disk | port |
++-------+-------------+---------------+------+-------+
+| 1 | | LPC1768 | J:\ | COM4 |
+| 3 | | NUCLEO_F103RB | I:\ | COM11 |
+| 2 | | KL25Z | E:\ | COM39 |
++-------+-------------+---------------+------+-------+
+
+Test specification in t.json:
++---------------+-----+------+
+| mcu | ARM | uARM |
++---------------+-----+------+
+| NUCLEO_F103RB | Yes | Yes |
+| KL25Z | Yes | - |
+| LPC1768 | Yes | Yes |
++---------------+-----+------+
+```
+It should help you localize basic problems with configuration files and toolchain configuration.
+Note: Configurations with issues will be marked with ```*``` sign.
+
+Having multiple configuration files allows you to manage your test scenarios in more flexible manner. You can:
+
+* Set up all platforms and toolchains used during testing.
+* Define (using script's ```-n``` switch) which tests you want to run during testing.
+* Just run regression (all tests). Regression is default setting for test script.
+
+You can also force ```singletest.py``` script to:
+* Run only peripherals' tests (switch ```-P```) or
+* Just skip peripherals' tests (switch ```-C```).
+* Build mbed SDK, libraries and corresponding tests with multiple cores, just use ```-j X``` option where ```X``` is number of cores you want to use for compilation.
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -j 8
+```
+* Print test cases console output using ```-V``` option.
+* Only build mbed SDK, tests and dependant libraries with switch ```-O```:
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -j 8 -O
+```
+* Execute each test case multiple times with ```--global-loops X``` option, where ```X``` number of repeats. Additionally use option ```-W``` to continue repeating test cases execution only if they continue to fail.
+```
+$ python singletest.py -i test_spec.json -M muts_all.json --global-loops 3 -W
+```
+* Option ```--loops``` can be used to overwrite global loop count and redefine loop count for particular tests. Define test loops as ```TEST_ID=X``` where ```X``` is integer and separate loops count definitions by comma if necessary. E.g. ```TEST_1=5,TEST_2=20,TEST_3=2```.
+```
+$ python singletest.py -i test_spec.json -M muts_all.json RTOS_1=10,RTOS_2=5
+```
+This will execute test ```RTOS_1``` ten (10) times and test ```RTOS_2``` five (5) times.
+* Force non default copy method. Note that mbed platforms can be flashed with just binary drag&drop. We simply copy file onto mbed's disk and interface chip flashes target MCU with given binary. Force non standard (Python specific) copy method by using option ```-c COPY_METHOD``` where ```COPY_METHOD``` can be shell, command line copy command like: ```cp```, ```copy````, ```xcopy``` etc. Make sure those commands are available from command line!
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -c cp
+```
+* Run only selected tests. You can select which tests should be executed when you run test suite. Use ```-n``` switch to define tests by their ids you want to execute. Use comma to separate test ids:
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -n RTOS_1,RTOS_2,RTOS_3,MBED_10,MBED_16,MBED_11
+```
+* Set common output binary name for all tests. In some cases you would like to have the same name for all tests. You can use switch ```--firmware-name``` to specify (without extension) build script output binary name.
+In below example we would like to have all test binaries called ```firmware.bin`` (or with other extension like .elf, .hex depending on target accepted format).
+```
+$ python singletest.py -i test_spec.json -M muts_all.json --firmware-name firmware
+```
+* Where to find test list? Tests are defined in file ```tests.py``` in ```mbed/workspace_tools/``` directory. ```singletest.py``` uses test metadata in ```tests.py``` to resolve libraries dependencies and build tests for proper platforms and peripherals. Option ```-R``` can be used to get test names and direct path and test configuration.
+```
+$ python singletest.py -R
++-------------+-----------+---------------------------------------+--------------+-------------------+----------+--------------------------------------------------------+
+| id | automated | description | peripherals | host_test | duration | source_dir |
++-------------+-----------+---------------------------------------+--------------+-------------------+----------+--------------------------------------------------------+
+| MBED_1 | False | I2C SRF08 | SRF08 | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\i2c_SRF08 |
+| MBED_10 | True | Hello World | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\hello |
+| MBED_11 | True | Ticker Int | - | host_test | 20 | C:\Work\mbed\libraries\tests\mbed\ticker |
+| MBED_12 | True | C++ | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\cpp |
+| MBED_13 | False | Heap & Stack | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\heap_and_stack |
+| MBED_14 | False | Serial Interrupt | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\serial_interrupt |
+| MBED_15 | False | RPC | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\rpc |
+| MBED_16 | True | RTC | - | host_test | 15 | C:\Work\mbed\libraries\tests\mbed\rtc |
+| MBED_17 | False | Serial Interrupt 2 | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\serial_interrupt_2 |
+| MBED_18 | False | Local FS Directory | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\dir |
+...
+```
+Note: you can filter tests by ```id``` column, just use ```-f``` option and give test name or regular expression:
+```
+$ python singletest.py -R -f RTOS
++--------------+-----------+-------------------------+-------------+-----------+----------+---------------------------------------------------+
+| id | automated | description | peripherals | host_test | duration | source_dir |
++--------------+-----------+-------------------------+-------------+-----------+----------+---------------------------------------------------+
+| CMSIS_RTOS_1 | False | Basic | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\cmsis\basic |
+| CMSIS_RTOS_2 | False | Mutex | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\cmsis\mutex |
+| CMSIS_RTOS_3 | False | Semaphore | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\cmsis\semaphore |
+| CMSIS_RTOS_4 | False | Signals | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\cmsis\signals |
+| CMSIS_RTOS_5 | False | Queue | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\cmsis\queue |
+| CMSIS_RTOS_6 | False | Mail | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\cmsis\mail |
+| CMSIS_RTOS_7 | False | Timer | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\cmsis\timer |
+| CMSIS_RTOS_8 | False | ISR | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\cmsis\isr |
+| RTOS_1 | True | Basic thread | - | host_test | 15 | C:\Work\mbed\libraries\tests\rtos\mbed\basic |
+| RTOS_2 | True | Mutex resource lock | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\mbed\mutex |
+| RTOS_3 | True | Semaphore resource lock | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\mbed\semaphore |
+| RTOS_4 | True | Signals messaging | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\signals |
+| RTOS_5 | True | Queue messaging | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\queue |
+| RTOS_6 | True | Mail messaging | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\mail |
+| RTOS_7 | True | Timer | - | host_test | 15 | C:\Work\mbed\libraries\tests\rtos\mbed\timer |
+| RTOS_8 | True | ISR (Queue) | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\isr |
+| RTOS_9 | True | SD File write-read | SD | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\file |
++--------------+-----------+-------------------------+-------------+-----------+----------+---------------------------------------------------+
+```
+
+* Shuffle your tests. We strongly encourage you to shuffle your test order each time you execute test suite script.
+Rationale: It is probable that tests executed in one particular order will pass and in other will fail. To shuffle your tests’ order please use option ```–u``` (or ```--shuffle```):
+```
+$ python singletest.py -i test_spec.json -M muts_all.json --shuffle
+```
+Above command with force test script to randomly generate shuffle seed and shuffle test order execution. Note: Shuffle seed is float in ```[0.0, 1.0)```.
+
+You can always recreate particular test order by forcing shuffle (```-u``` or ```--shuffle```} switch) and passing shuffle seed back to test suite using ```--shuffle-seed``` switch:
+```
+$ python singletest.py -i test_spec.json -M muts_all.json --shuffle --shuffle-seed 0.4041028336
+```
+Note: You can also supply your own randomly generated shuffle seed to drive particular test execution order scenarios. Just make sure shuffle seed is float in ```[0.0, 1.0)```.
+You can find test shuffle seed in test summary:
+```
+...
+| OK | LPC1768 | ARM | MBED_A9 | Serial Echo at 115200 | 2.84 | 10 | 1/1 |
++--------+---------+-----------+-----------+-----------------------------+--------------------+---------------+-------+
+Result: 1 FAIL / 22 OK
+Shuffle Seed: 0.4041028336
+
+Completed in 234.85 sec
+```
+
+### Exmple of device configuration (one device connected to host computer)
+
+This example will show you how to configure single device, run general tests or only peripheral tests. We will also show some real test result examples.
+
+1. We will test only one board STMIcro Nucleo ```F334R8``` board connected to our PC (port ```COM46``` and disk is ```E:```).
+2. We will also connect EEPROM ```24LC256``` to SDA, SCL pins of our Nucleo board and define 24LC256 peripheral to make sure our test suite will run all available tests for ```24LC256```.
+
+Let's configure our one MUT and set uARM as the only compiler we will use to compiler Mbed SDK and tests.
+We also need to create two configuration files ```muts_all.json``` and ```test_spec.json``` to pass our small testbed configuration to test script.
+
+muts_all.json:
+```json
+{
+ "1" : {
+ "mcu": "NUCLEO_F334R8",
+ "port":"COM46",
+ "disk":"E:\\",
+ "peripherals": ["24LC256"]
+ }
+}
+```
+Note: By defining ```"peripherals": ["24LC256"]``` we are passing to test suite information that this particular board has EEPROM 24LC256 connected to our board.
+
+test_spec.json:
+```json
+{
+ "targets": {
+ "NUCLEO_F334R8" : ["uARM"]
+ }
+}
+```
+Note:
+* Please make sure device is connected before we will start running tests.
+* Please make sure files ```muts_all.json``` and ```test_spec.json``` are in ```mbed/workspace_tools/``` directory.
+Now you can call test suite and execute tests:
+```
+$ python singletest.py -i test_spec.json -M muts_all.json
+...
+Test summary:
++--------+---------------+-----------+-----------+---------------------------------+--------------------+---------------+
+| Result | Target | Toolchain | Test ID | Test Description | Elapsed Time (sec) | Timeout (sec) |
++--------+---------------+-----------+-----------+---------------------------------+--------------------+---------------+
+| OK | NUCLEO_F334R8 | uARM | MBED_A25 | I2C EEPROM line read/write test | 12.41 | 15 |
+| OK | NUCLEO_F334R8 | uARM | MBED_A1 | Basic | 3.42 | 10 |
+| OK | NUCLEO_F334R8 | uARM | EXAMPLE_1 | /dev/null | 3.42 | 10 |
+| OK | NUCLEO_F334R8 | uARM | MBED_24 | Timeout Int us | 11.47 | 15 |
+| OK | NUCLEO_F334R8 | uARM | MBED_25 | Time us | 11.43 | 15 |
+| OK | NUCLEO_F334R8 | uARM | MBED_26 | Integer constant division | 3.37 | 10 |
+| OK | NUCLEO_F334R8 | uARM | MBED_23 | Ticker Int us | 12.43 | 15 |
+| OK | NUCLEO_F334R8 | uARM | MBED_A19 | I2C EEPROM read/write test | 11.42 | 15 |
+| OK | NUCLEO_F334R8 | uARM | MBED_11 | Ticker Int | 12.43 | 20 |
+| OK | NUCLEO_F334R8 | uARM | MBED_10 | Hello World | 2.42 | 10 |
+| OK | NUCLEO_F334R8 | uARM | MBED_12 | C++ | 3.42 | 10 |
+| OK | NUCLEO_F334R8 | uARM | MBED_16 | RTC | 4.76 | 15 |
+| UNDEF | NUCLEO_F334R8 | uARM | MBED_2 | stdio | 20.42 | 20 |
+| UNDEF | NUCLEO_F334R8 | uARM | MBED_A9 | Serial Echo at 115200 | 10.37 | 10 |
++--------+---------------+-----------+-----------+---------------------------------+--------------------+---------------+
+Result: 2 UNDEF / 12 OK
+
+Completed in 160 sec
+```
+
+If we want to get additional test summary with results in separate columns please use option ```-t```.
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -t
+...
+Test summary:
++---------------+-----------+---------------------------------+-------+
+| Target | Test ID | Test Description | uARM |
++---------------+-----------+---------------------------------+-------+
+| NUCLEO_F334R8 | EXAMPLE_1 | /dev/null | OK |
+| NUCLEO_F334R8 | MBED_10 | Hello World | OK |
+| NUCLEO_F334R8 | MBED_11 | Ticker Int | OK |
+| NUCLEO_F334R8 | MBED_12 | C++ | OK |
+| NUCLEO_F334R8 | MBED_16 | RTC | OK |
+| NUCLEO_F334R8 | MBED_2 | stdio | UNDEF |
+| NUCLEO_F334R8 | MBED_23 | Ticker Int us | OK |
+| NUCLEO_F334R8 | MBED_24 | Timeout Int us | OK |
+| NUCLEO_F334R8 | MBED_25 | Time us | OK |
+| NUCLEO_F334R8 | MBED_26 | Integer constant division | OK |
+| NUCLEO_F334R8 | MBED_A1 | Basic | OK |
+| NUCLEO_F334R8 | MBED_A19 | I2C EEPROM read/write test | OK |
+| NUCLEO_F334R8 | MBED_A25 | I2C EEPROM line read/write test | OK |
+| NUCLEO_F334R8 | MBED_A9 | Serial Echo at 115200 | UNDEF |
++---------------+-----------+---------------------------------+-------+
+```
+----
+Please do not forget you can combine few options together to get result you want. For example you want to repeat few tests multiple number of times, shuffle test ids execution order and select only tests which are critical for you at this point. You can do it using switch -n, --global-loops with --loops and --shuffle:
+
+Execute above command to:
+
+* Run only tests: ```RTOS_1```, ```RTOS_2```, ```RTOS_3```, ```MBED_10```, ```MBED_16```, ```MBED_11```.
+* Shuffle test execution order. Note tests in loops will not be shuffled.
+* Set global loop count to 3 - each test will repeated 3 times.
+* Overwrite global loop count (set above to 3) and:
+ * Force to loop test RTOS_1 to execute 3 times.
+ * Force to loop test RTOS_2 to execute 4 times.
+ * Force to loop test RTOS_3 to execute 5 times.
+ * Force to loop test MBED_11 to execute 5 times.
+
+```
+$ python singletest.py -i test_spec.json -M muts_all.json -n RTOS_1,RTOS_2,RTOS_3,MBED_10,MBED_16,MBED_11 --shuffle --global-loops 3 --loops RTOS_1=3,RTOS_2=4,RTOS_3=5,MBED_11=5
+```
+
+# CppUTest unit test library support
+## CppUTest in Mbed SDK testing introduction
+[CppUTest](http://cpputest.github.io/) is a C / C++ based unit xUnit test framework for unit testing and for test-driving your code. It is written in C++ but is used in C and C++ projects and frequently used in embedded systems but it works for any C / C++ project.
+
+Mbed SDK test suite supports writing tests using CppUTest. All you need to do it to provide CppUTest sources and includes with Mbed SDK port. This is already done for you so all you need to do it to get proper sources in your project directory.
+CppUTest’s core design principles are:
+* Simple in design and simple in use.
+* Portable to old and new platforms.
+* Build with Test-driven Development in mind.
+
+## From where you can get more help about CppUTest library and unit testing
+• You can read [CppUTest manual](http://cpputest.github.io/manual.html)
+* [CppUTest forum](https://groups.google.com/forum/?fromgroups#!forum/cpputest)
+* [CppUTest on GitHub](https://github.com/cpputest/cpputest)
+* Finally, if you think unit testing is new concept for you, you can have a grasp of it on Wikipedia pages about [unit testing](http://en.wikipedia.org/wiki/Unit_testing) and continue from there.
+
+## How to add CppUTest to your current Mbed SDK installation
+
+### Do I need CppUTest port for Mbed SDK?
+Yes, you do. If you want to use CppUTest with Mbed SDK you need to have CppUTest version with ARMCC compiler (only ARM flavor for now) port and Mbed SDK console port (if you want to have output on serial port). All is already prepared by Mbed engineers and you can get it for example here: http://mbed.org/users/rgrover1/code/CppUTest/
+
+### Prerequisites
+* Installed [git client](http://git-scm.com/downloads/).
+* Installed [Mercurial client](http://mercurial.selenic.com/).
+
+### How / where to install
+We want to create directory structure similar to one below:
+```
+\your_project_directory
+│
+├───cpputest
+│ ├───include
+│ └───src
+└───mbed
+ ├───libraries
+ ├───travis
+ └───workspace_tools
+```
+
+Please go to directory with your project. For example it could be c:\Projects\Project.
+```
+$ cd c:\Projects\Project
+```
+If your project directory already has your mbed SDK repository included just execute below command (Mercurial console client). It should download CppUTest with Mbed SDK port.
+```
+$ hg clone https://mbed.org/users/rgrover1/code/cpputest/
+```
+
+You should see something like this after you execute Mercurial clone command:
+```
+$ hg clone https://mbed.org/users/rgrover1/code/cpputest/
+destination directory: cpputest
+requesting all changes
+adding changesets
+adding manifests
+adding file changes
+added 3 changesets with 69 changes to 42 files
+updating to branch default
+41 files updated, 0 files merged, 0 files removed, 0 files unresolved
+```
+
+Confirm your project structure. It should look more or less like this:
+```
+$ ls
+cpputest mbed
+```
+From now on CppUTest is in correct path. Each time you want to compile unit tests for CppUTest build script will always look for CppUTest library in the same directory where mbed library is.
+
+## New off-line mbed SDK project with CppUTest support
+
+If you are creating new mbed SDK project and you want to use CppUTest with it you need to download both mbed SDK and CppUTest with mbed port to the same directory. You can do it like this:
+```
+$ cd c:\Projects\Project
+$ git clone https://github.com/mbedmicro/mbed.git
+$ hg clone https://mbed.org/users/rgrover1/code/cpputest/
+```
+
+After above three steps you should have proper directory structure. All you need to do now is to configure your ```private_settings.py``` in ```mbed/workspace_tools/``` directory. Please refer to mbed SDK build script documentation for details.
+
+## CppUTest with mbed port
+To make sure you actualy have CppUTest library with mbed SDK port you can go to CppUTest ```armcc``` platform directory:
+```
+$ cd c:/Projects/Project/cpputest/src/Platforms/armcc/
+```
+And open file ```UtestPlatform.cpp```.
+
+You should find part of code responsible for porting console on default serial port of the mbed device:
+```c++
+#include "Serial.h"
+using namespace mbed;
+
+int PlatformSpecificPutchar(int c)
+{
+ /* Please modify this block for test results to be reported as
+ * console output. The following is a sample implementation using a
+ * Serial object connected to the console. */
+#define NEED_TEST_REPORT_AS_CONSOLE_OUTPUT 1
+#if NEED_TEST_REPORT_AS_CONSOLE_OUTPUT
+ extern Serial console;
+
+ #define NEED_LINE_FEED_IN_ADDITION_TO_NEWLINE 1
+ #if NEED_LINE_FEED_IN_ADDITION_TO_NEWLINE
+ /* CppUTest emits \n line terminators in its reports; some terminals
+ * need the linefeed (\r) in addition. */
+ if (c == '\n') {
+ console.putc('\r');
+ }
+ #endif /* #if NEED_LINE_FEED_IN_ADDITION_TO_NEWLINE */
+
+ return (console.putc(c));
+#else /* NEED_TEST_REPORT_AS_CONSOLE_OUTPUT */
+ return (0);
+#endif /* NEED_TEST_REPORT_AS_CONSOLE_OUTPUT */
+}
+```
+
+You can find cpputest UT test runner main function in mbed sources: ```c:/Projects/Project/mbed/libraries/tests/utest/testrunner/testrunner.cpp```. Test runner code (in ```testrunner.cpp```) only defined console object and executes all unit tests:
+```c++
+#include "CommandLineTestRunner.h"
+#include <stdio.h>
+#include "mbed.h"
+#include "testrunner.h"
+#include "test_env.h"
+
+/**
+Object 'mbed_cpputest_console' is used to show prints on console.
+It is declared in \cpputest\src\Platforms\armcc\UtestPlatform.cpp
+*/
+Serial mbed_cpputest_console(STDIO_UART_TX, STDIO_UART_RX);
+
+int main(int ac, char** av) {
+ MBED_HOSTTEST_TIMEOUT(20);
+ MBED_HOSTTEST_SELECT(default_auto);
+ MBED_HOSTTEST_DESCRIPTION(Unit test);
+ MBED_HOSTTEST_START("UT");
+
+ unsigned failureCount = 0;
+ {
+ // Some compilers may not pass ac, av so we need to supply them ourselves
+ int ac = 2;
+ char* av[] = {__FILE__, "-v"};
+ failureCount = CommandLineTestRunner::RunAllTests(ac, av);
+ }
+
+ MBED_HOSTTEST_RESULT(failureCount == 0);
+ return failureCount;
+}
+```
+
+## Unit test location
+Unit tests source code is located in below directory: ```c:/Projects/Project/mbed/libraries/tests/utest/```
+
+Each sub directory except testrunner contains compilable unit test source files with test groups and test cases. You can see utest structure below. Please note this is just example and in the future this directory will contain many sub directories with unit tests.
+```
+$ c:\Projects\Project\mbed\libraries\tests\utest> tree
+utest
+├───basic
+├───semihost_fs
+└───testrunner
+```
+
+## Define unit tests in mbed SDK test suite structure
+All tests defined in test suite are described in ```mbed/workspace_tools/tests.py``` file. This file stores data structure ```TESTS``` which is a list of simple structures describing each test. Below you can find example of ```TESTS``` structure which is configuring one of the unit tests.
+```
+.
+.
+.
+ {
+ "id": "UT_2", "description": "Semihost file system",
+ "source_dir": join(TEST_DIR, "utest", "file"),
+ "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY],
+ "automated": False,
+ "mcu": ["LPC1768", "LPC2368", "LPC11U24"]
+ },
+.
+.
+.
+```
+Note: In dependency section we've added library ```CPPUTEST_LIBRARY``` which is pointing build script to CppUTest library with mbed port. This is a must for unit tests to be compiled with CppUTest library.
+
+### Tests are now divided into two types:
+#### 'Hello world' tests
+First type of test cases we call 'hello world' tests. They do not dependent on CppUTest library and are monolithic programs usually composed of one main function. Yo can find this tests in below example directories:
+
+* ```mbed/libraries/tests/mbed/```
+* ```mbed/libraries/tests/net/```
+* ```mbed/libraries/tests/rtos/```
+* ```mbed/libraries/tests/usb/```
+
+Usually ‘hello world’ test cases are using ```test_env.cpp``` and ```test_env.h``` files which implement simple test framework used to communicate with host test and help test framework instrument your tests.
+
+Below you can see listing of ```test_env.h``` file which contains simple macro definitions used to communicate (via serial port printouts) between test case (on hardware) and host test script (on host computer).
+Each use case should print on console basic information like:
+* Default test case timeout.
+* Which host test should be used to supervise test case execution.
+* Test description and test case ID (short identifier).
+
+```c++
+.
+.
+.
+// Test result related notification functions
+void notify_start();
+void notify_completion(bool success);
+bool notify_completion_str(bool success, char* buffer);
+void notify_performance_coefficient(const char* measurement_name, const int value);
+void notify_performance_coefficient(const char* measurement_name, const unsigned int value);
+void notify_performance_coefficient(const char* measurement_name, const double value);
+
+// Host test auto-detection API
+void notify_host_test_name(const char *host_test);
+void notify_timeout(int timeout);
+void notify_test_id(const char *test_id);
+void notify_test_description(const char *description);
+
+// Host test auto-detection API
+#define MBED_HOSTTEST_START(TESTID) notify_test_id(TESTID); notify_start()
+#define MBED_HOSTTEST_SELECT(NAME) notify_host_test_name(#NAME)
+#define MBED_HOSTTEST_TIMEOUT(SECONDS) notify_timeout(SECONDS)
+#define MBED_HOSTTEST_DESCRIPTION(DESC) notify_test_description(#DESC)
+#define MBED_HOSTTEST_RESULT(RESULT) notify_completion(RESULT)
+
+/**
+ Test auto-detection preamble example:
+ main() {
+ MBED_HOSTTEST_TIMEOUT(10);
+ MBED_HOSTTEST_SELECT( host_test );
+ MBED_HOSTTEST_DESCRIPTION(Hello World);
+ MBED_HOSTTEST_START("MBED_10");
+ // Proper 'host_test.py' should take over supervising of this test
+
+ // Test code
+ bool result = ...;
+
+ MBED_HOSTTEST_RESULT(result);
+ }
+*/
+.
+.
+.
+```
+
+Example of 'hello world' test:
+```c++
+#include "mbed.h"
+#include "test_env.h"
+
+#define CUSTOM_TIME 1256729737
+
+int main() {
+ MBED_HOSTTEST_TIMEOUT(20);
+ MBED_HOSTTEST_SELECT(rtc_auto);
+ MBED_HOSTTEST_DESCRIPTION(RTC);
+ MBED_HOSTTEST_START("MBED_16");
+
+ char buffer[32] = {0};
+ set_time(CUSTOM_TIME); // Set RTC time to Wed, 28 Oct 2009 11:35:37
+ while(1) {
+ time_t seconds = time(NULL);
+ strftime(buffer, 32, "%Y-%m-%d %H:%M:%S %p", localtime(&seconds));
+ printf("MBED: [%ld] [%s]\r\n", seconds, buffer);
+ wait(1);
+ }
+}
+```
+
+#### 'Unit test' test cases
+Second group of tests are unit tests. They are using CppUTest library and require you to write ```TEST_GROUP```s and ```TEST```s in your test files. Test suite will add test runner sources to your test automatically so you can concentrate on writing tests.
+
+Example of unit test:
+```c++
+#include "TestHarness.h"
+#include <utility>
+#include "mbed.h"
+
+TEST_GROUP(BusOut_mask)
+{
+};
+
+TEST(BusOut_mask, led_1_2_3)
+{
+ BusOut bus_data(LED1, LED2, LED3);
+ CHECK_EQUAL(0x07, bus_data.mask());
+}
+
+TEST(BusOut_mask, led_nc_nc_nc_nc)
+{
+ BusOut bus_data(NC, NC, NC, NC);
+ CHECK_EQUAL(0x00, bus_data.mask());
+}
+
+TEST(BusOut_mask, led_1_2_3_nc_nc)
+{
+ BusOut bus_data(LED1, LED2, LED3, NC, NC);
+ CHECK_EQUAL(0x07, bus_data.mask());
+}
+
+TEST(BusOut_mask, led_1_nc_2_nc_nc_3)
+{
+ BusOut bus_data(LED1, NC, LED2, NC, NC, LED3);
+ CHECK_EQUAL(0x25, bus_data.mask());
+}
+
+///////////////////////////////////////////////////////////////////////////////
+
+#ifdef MBED_OPERATORS
+TEST_GROUP(BusOut_digitalout_write)
+{
+};
+
+TEST(BusOut_digitalout_write, led_nc)
+{
+ BusOut bus_data(NC);
+ CHECK_EQUAL(false, bus_data[0].is_connected())
+}
+
+TEST(BusOut_digitalout_write, led_1_2_3)
+{
+ BusOut bus_data(LED1, LED2, LED3);
+ bus_data[0].write(1);
+ bus_data[1].write(1);
+ bus_data[2].write(1);
+ CHECK(bus_data[0].read());
+ CHECK(bus_data[1].read());
+ CHECK(bus_data[2].read());
+}
+
+TEST(BusOut_digitalout_write, led_1_2_3_nc_nc)
+{
+ BusOut bus_data(LED1, LED2, LED3, NC, NC);
+ bus_data[0].write(0);
+ bus_data[1].write(0);
+ bus_data[2].write(0);
+ CHECK(bus_data[0].read() == 0);
+ CHECK(bus_data[1].read() == 0);
+ CHECK(bus_data[2].read() == 0);
+}
+
+TEST(BusOut_digitalout_write, led_1_nc_2_nc_nc_3)
+{
+ BusOut bus_data(LED1, NC, LED2, NC, NC, LED3);
+ bus_data[0].write(1);
+ bus_data[2].write(0);
+ bus_data[5].write(0);
+ CHECK(bus_data[0].read());
+ CHECK(bus_data[2].read() == 0);
+ CHECK(bus_data[5].read() == 0);
+}
+#endif
+```
+
+## Example
+In below example we will run two example unit tests that are now available. tests ```UT_1``` and ```UT_2``` are unit tests used for now only to check if mbed SDK works with CppUTest library and if tests are being executed. In future number of unit tests will increase, nothing is also should stop you from writing and executing your own unit tests!
+
+### Example configuration
+By default unit tests ```UT_1``` and ```UT_2``` are not automated - simply test suite will ignore them. Also we do not want to create dependency to CppUTest library each time someone executes automation.
+
+Note: To compile ```UT_1``` and ```UT_2``` tests CppUTest library described above installation is needed and not all users wish to add UT libs to their project. Also new to mbed users may find it difficult. This is why unit testing is an extra feature active only after you deliberately install and enable needed components.
+
+Bellow snippet shows how to modify 'automated' flag so test suite will consider unit tests ```UT_1``` and ```UT_2``` as part of "automated test portfolio". Just change flag 'automated' from ```False``` to ```True```.
+
+```tests.py``` listing related to ```UT_1``` and ```UT_2```:
+```python
+.
+.
+.
+ # CPPUTEST Library provides Unit testing Framework
+ #
+ # To write TESTs and TEST_GROUPs please add CPPUTEST_LIBRARY to 'dependencies'
+ #
+ # This will also include:
+ # 1. test runner - main function with call to CommandLineTestRunner::RunAllTests(ac, av)
+ # 2. Serial console object to print test result on serial port console
+ #
+
+ # Unit testing with cpputest library
+ {
+ "id": "UT_1", "description": "Basic",
+ "source_dir": join(TEST_DIR, "utest", "basic"),
+ "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY],
+ "automated": True,
+ },
+ {
+ "id": "UT_2", "description": "Semihost file system",
+ "source_dir": join(TEST_DIR, "utest", "semihost_fs"),
+ "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY],
+ "automated": True,
+ "mcu": ["LPC1768", "LPC2368", "LPC11U24"]
+ },
+.
+.
+.
+```
+
+### Execute tests
+In my test I will use common [LPC1768](http://developer.mbed.org/platforms/mbed-LPC1768/) mbed-enabled board because unit test ```UT_2``` is checking semi-host functionality which is available on this board and handful of others.
+
+Configure your ```test_spec.json``` and ```muts_all.json``` files (refer to test suite build script and automation description) and set mbed disk and serial port.
+
+```
+$ singletest.py -i test_spec.json -M muts_all.json -n UT_1,UT_2 -V
+Building library CMSIS (LPC1768, ARM)
+Building library MBED (LPC1768, ARM)
+Building library CPPUTEST (LPC1768, ARM)
+Building project BASIC (LPC1768, ARM)
+Executing 'python host_test.py -p COM77 -d E:\ -t 10'
+Test::Output::Start
+Host test instrumentation on port: "COM77" and disk: "E:\"
+TEST(FirstTestGroup, FirstTest) - 0 ms
+
+OK (1 tests, 1 ran, 3 checks, 0 ignored, 0 filtered out, 3 ms)
+
+{{success}}
+{{end}}
+Test::Output::Finish
+TargetTest::LPC1768::ARM::UT_1::Basic [OK] in 2.43 of 10 sec
+Building library CPPUTEST (LPC1768, ARM)
+Building project SEMIHOST_FS (LPC1768, ARM)
+Executing 'python host_test.py -p COM77 -d E:\ -t 10'
+Test::Output::Start
+Host test instrumentation on port: "COM77" and disk: "E:\"
+TEST(FirstTestGroup, FirstTest) - 9 ms
+
+OK (1 tests, 1 ran, 10 checks, 0 ignored, 0 filtered out, 10 ms)
+
+{{success}}
+{{end}}
+Test::Output::Finish
+TargetTest::LPC1768::ARM::UT_2::Semihost file system [OK] in 2.43 of 10 sec
+Test summary:
++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+
+| Result | Target | Toolchain | Test ID | Test Description | Elapsed Time (sec) | Timeout (sec) | Loops |
++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+
+| OK | LPC1768 | ARM | UT_1 | Basic | 2.43 | 10 | 1/1 |
+| OK | LPC1768 | ARM | UT_2 | Semihost file system | 2.43 | 10 | 1/1 |
++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+
+Result: 2 OK
+
+Completed in 12.02 sec
+```
+
+You can compile unit tests using various number of supported compilers, below just few examples with working solutions:
+```
+Test summary:
++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+
+| Result | Target | Toolchain | Test ID | Test Description | Elapsed Time (sec) | Timeout (sec) | Loops |
++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+
+| OK | LPC1768 | ARM | UT_1 | Basic | 2.43 | 10 | 1/1 |
+| OK | LPC1768 | ARM | UT_2 | Semihost file system | 2.43 | 10 | 1/1 |
+| OK | LPC1768 | uARM | UT_1 | Basic | 2.43 | 10 | 1/1 |
+| OK | LPC1768 | uARM | UT_2 | Semihost file system | 2.43 | 10 | 1/1 |
+| OK | LPC1768 | GCC_ARM | UT_1 | Basic | 2.43 | 10 | 1/1 |
+| OK | LPC1768 | GCC_ARM | UT_2 | Semihost file system | 2.43 | 10 | 1/1 |
+| OK | LPC1768 | GCC_CR | UT_1 | Basic | 3.44 | 10 | 1/1 |
+| OK | LPC1768 | GCC_CR | UT_2 | Semihost file system | 3.43 | 10 | 1/1 |
++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+
+Result: 8 OK
+
+Completed in 55.85 sec
+```
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio.cpp
new file mode 100644
index 000000000..aab9e774e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio.cpp
@@ -0,0 +1,618 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBAudio.h"
+#include "USBAudio_Types.h"
+
+
+
+USBAudio::USBAudio(uint32_t frequency_in, uint8_t channel_nb_in, uint32_t frequency_out, uint8_t channel_nb_out, uint16_t vendor_id, uint16_t product_id, uint16_t product_release): USBDevice(vendor_id, product_id, product_release) {
+ mute = 0;
+ volCur = 0x0080;
+ volMin = 0x0000;
+ volMax = 0x0100;
+ volRes = 0x0004;
+ available = false;
+
+ FREQ_IN = frequency_in;
+ FREQ_OUT = frequency_out;
+
+ this->channel_nb_in = channel_nb_in;
+ this->channel_nb_out = channel_nb_out;
+
+ // stereo -> *2, mono -> *1
+ PACKET_SIZE_ISO_IN = (FREQ_IN / 500) * channel_nb_in;
+ PACKET_SIZE_ISO_OUT = (FREQ_OUT / 500) * channel_nb_out;
+
+ // STEREO -> left and right
+ channel_config_in = (channel_nb_in == 1) ? CHANNEL_M : CHANNEL_L + CHANNEL_R;
+ channel_config_out = (channel_nb_out == 1) ? CHANNEL_M : CHANNEL_L + CHANNEL_R;
+
+ SOF_handler = false;
+
+ buf_stream_out = NULL;
+ buf_stream_in = NULL;
+
+ interruptOUT = false;
+ writeIN = false;
+ interruptIN = false;
+ available = false;
+
+ volume = 0;
+
+ // connect the device
+ USBDevice::connect();
+}
+
+bool USBAudio::read(uint8_t * buf) {
+ buf_stream_in = buf;
+ SOF_handler = false;
+ while (!available || !SOF_handler);
+ available = false;
+ return true;
+}
+
+bool USBAudio::readNB(uint8_t * buf) {
+ buf_stream_in = buf;
+ SOF_handler = false;
+ while (!SOF_handler);
+ if (available) {
+ available = false;
+ buf_stream_in = NULL;
+ return true;
+ }
+ return false;
+}
+
+bool USBAudio::readWrite(uint8_t * buf_read, uint8_t * buf_write) {
+ buf_stream_in = buf_read;
+ SOF_handler = false;
+ writeIN = false;
+ if (interruptIN) {
+ USBDevice::writeNB(EP3IN, buf_write, PACKET_SIZE_ISO_OUT, PACKET_SIZE_ISO_OUT);
+ } else {
+ buf_stream_out = buf_write;
+ }
+ while (!available);
+ if (interruptIN) {
+ while (!writeIN);
+ }
+ while (!SOF_handler);
+ return true;
+}
+
+
+bool USBAudio::write(uint8_t * buf) {
+ writeIN = false;
+ SOF_handler = false;
+ if (interruptIN) {
+ USBDevice::writeNB(EP3IN, buf, PACKET_SIZE_ISO_OUT, PACKET_SIZE_ISO_OUT);
+ } else {
+ buf_stream_out = buf;
+ }
+ while (!SOF_handler);
+ if (interruptIN) {
+ while (!writeIN);
+ }
+ return true;
+}
+
+
+float USBAudio::getVolume() {
+ return (mute) ? 0.0 : volume;
+}
+
+
+bool USBAudio::EPISO_OUT_callback() {
+ uint32_t size = 0;
+ interruptOUT = true;
+ if (buf_stream_in != NULL) {
+ readEP(EP3OUT, (uint8_t *)buf_stream_in, &size, PACKET_SIZE_ISO_IN);
+ available = true;
+ buf_stream_in = NULL;
+ }
+ readStart(EP3OUT, PACKET_SIZE_ISO_IN);
+ return false;
+}
+
+
+bool USBAudio::EPISO_IN_callback() {
+ interruptIN = true;
+ writeIN = true;
+ return true;
+}
+
+
+
+// Called in ISR context on each start of frame
+void USBAudio::SOF(int frameNumber) {
+ uint32_t size = 0;
+
+ if (!interruptOUT) {
+ // read the isochronous endpoint
+ if (buf_stream_in != NULL) {
+ if (USBDevice::readEP_NB(EP3OUT, (uint8_t *)buf_stream_in, &size, PACKET_SIZE_ISO_IN)) {
+ if (size) {
+ available = true;
+ readStart(EP3OUT, PACKET_SIZE_ISO_IN);
+ buf_stream_in = NULL;
+ }
+ }
+ }
+ }
+
+ if (!interruptIN) {
+ // write if needed
+ if (buf_stream_out != NULL) {
+ USBDevice::writeNB(EP3IN, (uint8_t *)buf_stream_out, PACKET_SIZE_ISO_OUT, PACKET_SIZE_ISO_OUT);
+ buf_stream_out = NULL;
+ }
+ }
+
+ SOF_handler = true;
+}
+
+
+// Called in ISR context
+// Set configuration. Return false if the configuration is not supported.
+bool USBAudio::USBCallback_setConfiguration(uint8_t configuration) {
+ if (configuration != DEFAULT_CONFIGURATION) {
+ return false;
+ }
+
+ // Configure isochronous endpoint
+ realiseEndpoint(EP3OUT, PACKET_SIZE_ISO_IN, ISOCHRONOUS);
+ realiseEndpoint(EP3IN, PACKET_SIZE_ISO_OUT, ISOCHRONOUS);
+
+ // activate readings on this endpoint
+ readStart(EP3OUT, PACKET_SIZE_ISO_IN);
+ return true;
+}
+
+
+// Called in ISR context
+// Set alternate setting. Return false if the alternate setting is not supported
+bool USBAudio::USBCallback_setInterface(uint16_t interface, uint8_t alternate) {
+ if (interface == 0 && alternate == 0) {
+ return true;
+ }
+ if (interface == 1 && (alternate == 0 || alternate == 1)) {
+ return true;
+ }
+ if (interface == 2 && (alternate == 0 || alternate == 1)) {
+ return true;
+ }
+ return false;
+}
+
+
+
+// Called in ISR context
+// Called by USBDevice on Endpoint0 request
+// This is used to handle extensions to standard requests and class specific requests.
+// Return true if class handles this request
+bool USBAudio::USBCallback_request() {
+ bool success = false;
+ CONTROL_TRANSFER * transfer = getTransferPtr();
+
+ // Process class-specific requests
+ if (transfer->setup.bmRequestType.Type == CLASS_TYPE) {
+
+ // Feature Unit: Interface = 0, ID = 2
+ if (transfer->setup.wIndex == 0x0200) {
+
+ // Master Channel
+ if ((transfer->setup.wValue & 0xff) == 0) {
+
+ switch (transfer->setup.wValue >> 8) {
+ case MUTE_CONTROL:
+ switch (transfer->setup.bRequest) {
+ case REQUEST_GET_CUR:
+ transfer->remaining = 1;
+ transfer->ptr = &mute;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+
+ case REQUEST_SET_CUR:
+ transfer->remaining = 1;
+ transfer->notify = true;
+ transfer->direction = HOST_TO_DEVICE;
+ success = true;
+ break;
+ default:
+ break;
+ }
+ break;
+ case VOLUME_CONTROL:
+ switch (transfer->setup.bRequest) {
+ case REQUEST_GET_CUR:
+ transfer->remaining = 2;
+ transfer->ptr = (uint8_t *)&volCur;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case REQUEST_GET_MIN:
+ transfer->remaining = 2;
+ transfer->ptr = (uint8_t *)&volMin;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case REQUEST_GET_MAX:
+ transfer->remaining = 2;
+ transfer->ptr = (uint8_t *)&volMax;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case REQUEST_GET_RES:
+ transfer->remaining = 2;
+ transfer->ptr = (uint8_t *)&volRes;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+
+ case REQUEST_SET_CUR:
+ transfer->remaining = 2;
+ transfer->notify = true;
+ transfer->direction = HOST_TO_DEVICE;
+ success = true;
+ break;
+ case REQUEST_SET_MIN:
+ transfer->remaining = 2;
+ transfer->notify = true;
+ transfer->direction = HOST_TO_DEVICE;
+ success = true;
+ break;
+ case REQUEST_SET_MAX:
+ transfer->remaining = 2;
+ transfer->notify = true;
+ transfer->direction = HOST_TO_DEVICE;
+ success = true;
+ break;
+ case REQUEST_SET_RES:
+ transfer->remaining = 2;
+ transfer->notify = true;
+ transfer->direction = HOST_TO_DEVICE;
+ success = true;
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ }
+ }
+ return success;
+}
+
+
+// Called in ISR context when a data OUT stage has been performed
+void USBAudio::USBCallback_requestCompleted(uint8_t * buf, uint32_t length) {
+ if ((length == 1) || (length == 2)) {
+ uint16_t data = (length == 1) ? *buf : *((uint16_t *)buf);
+ CONTROL_TRANSFER * transfer = getTransferPtr();
+ switch (transfer->setup.wValue >> 8) {
+ case MUTE_CONTROL:
+ switch (transfer->setup.bRequest) {
+ case REQUEST_SET_CUR:
+ mute = data & 0xff;
+ updateVol.call();
+ break;
+ default:
+ break;
+ }
+ break;
+ case VOLUME_CONTROL:
+ switch (transfer->setup.bRequest) {
+ case REQUEST_SET_CUR:
+ volCur = data;
+ volume = (float)volCur/(float)volMax;
+ updateVol.call();
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+
+
+#define TOTAL_DESCRIPTOR_LENGTH ((1 * CONFIGURATION_DESCRIPTOR_LENGTH) \
+ + (5 * INTERFACE_DESCRIPTOR_LENGTH) \
+ + (1 * CONTROL_INTERFACE_DESCRIPTOR_LENGTH + 1) \
+ + (2 * INPUT_TERMINAL_DESCRIPTOR_LENGTH) \
+ + (1 * FEATURE_UNIT_DESCRIPTOR_LENGTH) \
+ + (2 * OUTPUT_TERMINAL_DESCRIPTOR_LENGTH) \
+ + (2 * STREAMING_INTERFACE_DESCRIPTOR_LENGTH) \
+ + (2 * FORMAT_TYPE_I_DESCRIPTOR_LENGTH) \
+ + (2 * (ENDPOINT_DESCRIPTOR_LENGTH + 2)) \
+ + (2 * STREAMING_ENDPOINT_DESCRIPTOR_LENGTH) )
+
+#define TOTAL_CONTROL_INTF_LENGTH (CONTROL_INTERFACE_DESCRIPTOR_LENGTH + 1 + \
+ 2*INPUT_TERMINAL_DESCRIPTOR_LENGTH + \
+ FEATURE_UNIT_DESCRIPTOR_LENGTH + \
+ 2*OUTPUT_TERMINAL_DESCRIPTOR_LENGTH)
+
+uint8_t * USBAudio::configurationDesc() {
+ static uint8_t configDescriptor[] = {
+ // Configuration 1
+ CONFIGURATION_DESCRIPTOR_LENGTH, // bLength
+ CONFIGURATION_DESCRIPTOR, // bDescriptorType
+ LSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (LSB)
+ MSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (MSB)
+ 0x03, // bNumInterfaces
+ DEFAULT_CONFIGURATION, // bConfigurationValue
+ 0x00, // iConfiguration
+ 0x80, // bmAttributes
+ 50, // bMaxPower
+
+ // Interface 0, Alternate Setting 0, Audio Control
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x00, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x00, // bNumEndpoints
+ AUDIO_CLASS, // bInterfaceClass
+ SUBCLASS_AUDIOCONTROL, // bInterfaceSubClass
+ 0x00, // bInterfaceProtocol
+ 0x00, // iInterface
+
+
+ // Audio Control Interface
+ CONTROL_INTERFACE_DESCRIPTOR_LENGTH + 1,// bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ CONTROL_HEADER, // bDescriptorSubtype
+ LSB(0x0100), // bcdADC (LSB)
+ MSB(0x0100), // bcdADC (MSB)
+ LSB(TOTAL_CONTROL_INTF_LENGTH), // wTotalLength
+ MSB(TOTAL_CONTROL_INTF_LENGTH), // wTotalLength
+ 0x02, // bInCollection
+ 0x01, // baInterfaceNr
+ 0x02, // baInterfaceNr
+
+ // Audio Input Terminal (Speaker)
+ INPUT_TERMINAL_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ CONTROL_INPUT_TERMINAL, // bDescriptorSubtype
+ 0x01, // bTerminalID
+ LSB(TERMINAL_USB_STREAMING), // wTerminalType
+ MSB(TERMINAL_USB_STREAMING), // wTerminalType
+ 0x00, // bAssocTerminal
+ channel_nb_in, // bNrChannels
+ (uint8_t)(LSB(channel_config_in)), // wChannelConfig
+ (uint8_t)(MSB(channel_config_in)), // wChannelConfig
+ 0x00, // iChannelNames
+ 0x00, // iTerminal
+
+ // Audio Feature Unit (Speaker)
+ FEATURE_UNIT_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ CONTROL_FEATURE_UNIT, // bDescriptorSubtype
+ 0x02, // bUnitID
+ 0x01, // bSourceID
+ 0x01, // bControlSize
+ CONTROL_MUTE |
+ CONTROL_VOLUME, // bmaControls(0)
+ 0x00, // bmaControls(1)
+ 0x00, // iTerminal
+
+ // Audio Output Terminal (Speaker)
+ OUTPUT_TERMINAL_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ CONTROL_OUTPUT_TERMINAL, // bDescriptorSubtype
+ 0x03, // bTerminalID
+ LSB(TERMINAL_SPEAKER), // wTerminalType
+ MSB(TERMINAL_SPEAKER), // wTerminalType
+ 0x00, // bAssocTerminal
+ 0x02, // bSourceID
+ 0x00, // iTerminal
+
+
+ // Audio Input Terminal (Microphone)
+ INPUT_TERMINAL_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ CONTROL_INPUT_TERMINAL, // bDescriptorSubtype
+ 0x04, // bTerminalID
+ LSB(TERMINAL_MICROPHONE), // wTerminalType
+ MSB(TERMINAL_MICROPHONE), // wTerminalType
+ 0x00, // bAssocTerminal
+ channel_nb_out, // bNrChannels
+ (uint8_t)(LSB(channel_config_out)), // wChannelConfig
+ (uint8_t)(MSB(channel_config_out)), // wChannelConfig
+ 0x00, // iChannelNames
+ 0x00, // iTerminal
+
+ // Audio Output Terminal (Microphone)
+ OUTPUT_TERMINAL_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ CONTROL_OUTPUT_TERMINAL, // bDescriptorSubtype
+ 0x05, // bTerminalID
+ LSB(TERMINAL_USB_STREAMING), // wTerminalType
+ MSB(TERMINAL_USB_STREAMING), // wTerminalType
+ 0x00, // bAssocTerminal
+ 0x04, // bSourceID
+ 0x00, // iTerminal
+
+
+
+
+
+
+ // Interface 1, Alternate Setting 0, Audio Streaming - Zero Bandwith
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x01, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x00, // bNumEndpoints
+ AUDIO_CLASS, // bInterfaceClass
+ SUBCLASS_AUDIOSTREAMING, // bInterfaceSubClass
+ 0x00, // bInterfaceProtocol
+ 0x00, // iInterface
+
+ // Interface 1, Alternate Setting 1, Audio Streaming - Operational
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x01, // bInterfaceNumber
+ 0x01, // bAlternateSetting
+ 0x01, // bNumEndpoints
+ AUDIO_CLASS, // bInterfaceClass
+ SUBCLASS_AUDIOSTREAMING, // bInterfaceSubClass
+ 0x00, // bInterfaceProtocol
+ 0x00, // iInterface
+
+ // Audio Streaming Interface
+ STREAMING_INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ STREAMING_GENERAL, // bDescriptorSubtype
+ 0x01, // bTerminalLink
+ 0x00, // bDelay
+ LSB(FORMAT_PCM), // wFormatTag
+ MSB(FORMAT_PCM), // wFormatTag
+
+ // Audio Type I Format
+ FORMAT_TYPE_I_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ STREAMING_FORMAT_TYPE, // bDescriptorSubtype
+ FORMAT_TYPE_I, // bFormatType
+ channel_nb_in, // bNrChannels
+ 0x02, // bSubFrameSize
+ 16, // bBitResolution
+ 0x01, // bSamFreqType
+ (uint8_t)(LSB(FREQ_IN)), // tSamFreq
+ (uint8_t)((FREQ_IN >> 8) & 0xff), // tSamFreq
+ (uint8_t)((FREQ_IN >> 16) & 0xff), // tSamFreq
+
+ // Endpoint - Standard Descriptor
+ ENDPOINT_DESCRIPTOR_LENGTH + 2, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPISO_OUT), // bEndpointAddress
+ E_ISOCHRONOUS, // bmAttributes
+ (uint8_t)(LSB(PACKET_SIZE_ISO_IN)), // wMaxPacketSize
+ (uint8_t)(MSB(PACKET_SIZE_ISO_IN)), // wMaxPacketSize
+ 0x01, // bInterval
+ 0x00, // bRefresh
+ 0x00, // bSynchAddress
+
+ // Endpoint - Audio Streaming
+ STREAMING_ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR_TYPE, // bDescriptorType
+ ENDPOINT_GENERAL, // bDescriptor
+ 0x00, // bmAttributes
+ 0x00, // bLockDelayUnits
+ LSB(0x0000), // wLockDelay
+ MSB(0x0000), // wLockDelay
+
+
+
+
+
+
+
+ // Interface 1, Alternate Setting 0, Audio Streaming - Zero Bandwith
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x02, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x00, // bNumEndpoints
+ AUDIO_CLASS, // bInterfaceClass
+ SUBCLASS_AUDIOSTREAMING, // bInterfaceSubClass
+ 0x00, // bInterfaceProtocol
+ 0x00, // iInterface
+
+ // Interface 1, Alternate Setting 1, Audio Streaming - Operational
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x02, // bInterfaceNumber
+ 0x01, // bAlternateSetting
+ 0x01, // bNumEndpoints
+ AUDIO_CLASS, // bInterfaceClass
+ SUBCLASS_AUDIOSTREAMING, // bInterfaceSubClass
+ 0x00, // bInterfaceProtocol
+ 0x00, // iInterface
+
+ // Audio Streaming Interface
+ STREAMING_INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ SUBCLASS_AUDIOCONTROL, // bDescriptorSubtype
+ 0x05, // bTerminalLink (output terminal microphone)
+ 0x01, // bDelay
+ 0x01, // wFormatTag
+ 0x00, // wFormatTag
+
+ // Audio Type I Format
+ FORMAT_TYPE_I_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR_TYPE, // bDescriptorType
+ SUBCLASS_AUDIOSTREAMING, // bDescriptorSubtype
+ FORMAT_TYPE_I, // bFormatType
+ channel_nb_out, // bNrChannels
+ 0x02, // bSubFrameSize
+ 0x10, // bBitResolution
+ 0x01, // bSamFreqType
+ (uint8_t)(LSB(FREQ_OUT)), // tSamFreq
+ (uint8_t)((FREQ_OUT >> 8) & 0xff), // tSamFreq
+ (uint8_t)((FREQ_OUT >> 16) & 0xff), // tSamFreq
+
+ // Endpoint - Standard Descriptor
+ ENDPOINT_DESCRIPTOR_LENGTH + 2, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPISO_IN), // bEndpointAddress
+ E_ISOCHRONOUS, // bmAttributes
+ (uint8_t)(LSB(PACKET_SIZE_ISO_OUT)), // wMaxPacketSize
+ (uint8_t)(MSB(PACKET_SIZE_ISO_OUT)), // wMaxPacketSize
+ 0x01, // bInterval
+ 0x00, // bRefresh
+ 0x00, // bSynchAddress
+
+ // Endpoint - Audio Streaming
+ STREAMING_ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR_TYPE, // bDescriptorType
+ ENDPOINT_GENERAL, // bDescriptor
+ 0x00, // bmAttributes
+ 0x00, // bLockDelayUnits
+ LSB(0x0000), // wLockDelay
+ MSB(0x0000), // wLockDelay
+
+ // Terminator
+ 0 // bLength
+ };
+ return configDescriptor;
+}
+
+uint8_t * USBAudio::stringIinterfaceDesc() {
+ static uint8_t stringIinterfaceDescriptor[] = {
+ 0x0c, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'A',0,'u',0,'d',0,'i',0,'o',0 //bString iInterface - Audio
+ };
+ return stringIinterfaceDescriptor;
+}
+
+uint8_t * USBAudio::stringIproductDesc() {
+ static uint8_t stringIproductDescriptor[] = {
+ 0x16, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'M',0,'b',0,'e',0,'d',0,' ',0,'A',0,'u',0,'d',0,'i',0,'o',0 //bString iProduct - Mbed Audio
+ };
+ return stringIproductDescriptor;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio.h
new file mode 100644
index 000000000..5038f053c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio.h
@@ -0,0 +1,287 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBAudio_H
+#define USBAudio_H
+
+/* These headers are included for child class. */
+#include "USBEndpoints.h"
+#include "USBDescriptor.h"
+#include "USBDevice_Types.h"
+
+#include "USBDevice.h"
+
+
+/**
+* USBAudio example
+*
+* @code
+* #include "mbed.h"
+* #include "USBAudio.h"
+*
+* Serial pc(USBTX, USBRX);
+*
+* // frequency: 48 kHz
+* #define FREQ 48000
+*
+* // 1 channel: mono
+* #define NB_CHA 1
+*
+* // length of an audio packet: each ms, we receive 48 * 16bits ->48 * 2 bytes. as there is one channel, the length will be 48 * 2 * 1
+* #define AUDIO_LENGTH_PACKET 48 * 2 * 1
+*
+* // USBAudio
+* USBAudio audio(FREQ, NB_CHA);
+*
+* int main() {
+* int16_t buf[AUDIO_LENGTH_PACKET/2];
+*
+* while (1) {
+* // read an audio packet
+* audio.read((uint8_t *)buf);
+*
+*
+* // print packet received
+* pc.printf("recv: ");
+* for(int i = 0; i < AUDIO_LENGTH_PACKET/2; i++) {
+* pc.printf("%d ", buf[i]);
+* }
+* pc.printf("\r\n");
+* }
+* }
+* @endcode
+*/
+class USBAudio: public USBDevice {
+public:
+
+ /**
+ * Constructor
+ *
+ * @param frequency_in frequency in Hz (default: 48000)
+ * @param channel_nb_in channel number (1 or 2) (default: 1)
+ * @param frequency_out frequency in Hz (default: 8000)
+ * @param channel_nb_out_in channel number (1 or 2) (default: 1)
+ * @param vendor_id Your vendor_id
+ * @param product_id Your product_id
+ * @param product_release Your preoduct_release
+ */
+ USBAudio(uint32_t frequency_in = 48000, uint8_t channel_nb_in = 1, uint32_t frequency_out = 8000, uint8_t channel_nb_out = 1, uint16_t vendor_id = 0x7bb8, uint16_t product_id = 0x1111, uint16_t product_release = 0x0100);
+
+ /**
+ * Get current volume between 0.0 and 1.0
+ *
+ * @returns volume
+ */
+ float getVolume();
+
+ /**
+ * Read an audio packet. During a frame, only a single reading (you can't write and read an audio packet during the same frame)can be done using this method. Warning: Blocking
+ *
+ * @param buf pointer on a buffer which will be filled with an audio packet
+ *
+ * @returns true if successfull
+ */
+ bool read(uint8_t * buf);
+
+ /**
+ * Try to read an audio packet. During a frame, only a single reading (you can't write and read an audio packet during the same frame)can be done using this method. Warning: Non Blocking
+ *
+ * @param buf pointer on a buffer which will be filled if an audio packet is available
+ *
+ * @returns true if successfull
+ */
+ bool readNB(uint8_t * buf);
+
+ /**
+ * Write an audio packet. During a frame, only a single writing (you can't write and read an audio packet during the same frame)can be done using this method.
+ *
+ * @param buf pointer on the audio packet which will be sent
+ * @returns true if successful
+ */
+ bool write(uint8_t * buf);
+
+ /**
+ * Write and read an audio packet at the same time (on the same frame)
+ *
+ * @param buf_read pointer on a buffer which will be filled with an audio packet
+ * @param buf_write pointer on the audio packet which will be sent
+ * @returns true if successful
+ */
+ bool readWrite(uint8_t * buf_read, uint8_t * buf_write);
+
+
+ /** attach a handler to update the volume
+ *
+ * @param function Function to attach
+ *
+ */
+ void attach(void(*fptr)(void)) {
+ updateVol.attach(fptr);
+ }
+
+ /** Attach a nonstatic void/void member function to update the volume
+ *
+ * @param tptr Object pointer
+ * @param mptr Member function pointer
+ *
+ */
+ template<typename T>
+ void attach(T *tptr, void(T::*mptr)(void)) {
+ updateVol.attach(tptr, mptr);
+ }
+
+
+protected:
+
+ /*
+ * Called by USBDevice layer. Set configuration of the device.
+ * For instance, you can add all endpoints that you need on this function.
+ *
+ * @param configuration Number of the configuration
+ * @returns true if class handles this request
+ */
+ virtual bool USBCallback_setConfiguration(uint8_t configuration);
+
+ /*
+ * Called by USBDevice on Endpoint0 request. Warning: Called in ISR context
+ * This is used to handle extensions to standard requests
+ * and class specific requests
+ *
+ * @returns true if class handles this request
+ */
+ virtual bool USBCallback_request();
+
+ /*
+ * Get string product descriptor
+ *
+ * @returns pointer to the string product descriptor
+ */
+ virtual uint8_t * stringIproductDesc();
+
+ /*
+ * Get string interface descriptor
+ *
+ * @returns pointer to the string interface descriptor
+ */
+ virtual uint8_t * stringIinterfaceDesc();
+
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc();
+
+ /*
+ * Called by USBDevice layer. Set interface/alternate of the device.
+ *
+ * @param interface Number of the interface to be configured
+ * @param alternate Number of the alternate to be configured
+ * @returns true if class handles this request
+ */
+ virtual bool USBCallback_setInterface(uint16_t interface, uint8_t alternate);
+
+ /*
+ * Called by USBDevice on Endpoint0 request completion
+ * if the 'notify' flag has been set to true. Warning: Called in ISR context
+ *
+ * In this case it is used to indicate that a HID report has
+ * been received from the host on endpoint 0
+ *
+ * @param buf buffer received on endpoint 0
+ * @param length length of this buffer
+ */
+ virtual void USBCallback_requestCompleted(uint8_t * buf, uint32_t length);
+
+ /*
+ * Callback called on each Start of Frame event
+ */
+ virtual void SOF(int frameNumber);
+
+ /*
+ * Callback called when a packet is received
+ */
+ virtual bool EPISO_OUT_callback();
+
+ /*
+ * Callback called when a packet has been sent
+ */
+ virtual bool EPISO_IN_callback();
+
+private:
+
+ // stream available ?
+ volatile bool available;
+
+ // interrupt OUT has been received
+ volatile bool interruptOUT;
+
+ // interrupt IN has been received
+ volatile bool interruptIN;
+
+ // audio packet has been written
+ volatile bool writeIN;
+
+ // FREQ
+ uint32_t FREQ_OUT;
+ uint32_t FREQ_IN;
+
+ // size of the maximum packet for the isochronous endpoint
+ uint32_t PACKET_SIZE_ISO_IN;
+ uint32_t PACKET_SIZE_ISO_OUT;
+
+ // mono, stereo,...
+ uint8_t channel_nb_in;
+ uint8_t channel_nb_out;
+
+ // channel config: master, left, right
+ uint8_t channel_config_in;
+ uint8_t channel_config_out;
+
+ // mute state
+ uint8_t mute;
+
+ // Volume Current Value
+ uint16_t volCur;
+
+ // Volume Minimum Value
+ uint16_t volMin;
+
+ // Volume Maximum Value
+ uint16_t volMax;
+
+ // Volume Resolution
+ uint16_t volRes;
+
+ // Buffer containing one audio packet (to be read)
+ volatile uint8_t * buf_stream_in;
+
+ // Buffer containing one audio packet (to be written)
+ volatile uint8_t * buf_stream_out;
+
+ // callback to update volume
+ FunctionPointer updateVol;
+
+ // boolean showing that the SOF handler has been called. Useful for readNB.
+ volatile bool SOF_handler;
+
+ volatile float volume;
+
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio_Types.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio_Types.h
new file mode 100644
index 000000000..1151a7200
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBAudio/USBAudio_Types.h
@@ -0,0 +1,97 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBAUDIO_TYPES_H
+#define USBAUDIO_TYPES_H
+
+
+#define DEFAULT_CONFIGURATION (1)
+
+// Audio Request Codes
+#define REQUEST_SET_CUR 0x01
+#define REQUEST_GET_CUR 0x81
+#define REQUEST_SET_MIN 0x02
+#define REQUEST_GET_MIN 0x82
+#define REQUEST_SET_MAX 0x03
+#define REQUEST_GET_MAX 0x83
+#define REQUEST_SET_RES 0x04
+#define REQUEST_GET_RES 0x84
+
+#define MUTE_CONTROL 0x01
+#define VOLUME_CONTROL 0x02
+
+
+// Audio Descriptor Sizes
+#define CONTROL_INTERFACE_DESCRIPTOR_LENGTH 0x09
+#define STREAMING_INTERFACE_DESCRIPTOR_LENGTH 0x07
+#define INPUT_TERMINAL_DESCRIPTOR_LENGTH 0x0C
+#define OUTPUT_TERMINAL_DESCRIPTOR_LENGTH 0x09
+#define FEATURE_UNIT_DESCRIPTOR_LENGTH 0x09
+#define STREAMING_ENDPOINT_DESCRIPTOR_LENGTH 0x07
+
+// Audio Format Type Descriptor Sizes
+#define FORMAT_TYPE_I_DESCRIPTOR_LENGTH 0x0b
+
+#define AUDIO_CLASS 0x01
+#define SUBCLASS_AUDIOCONTROL 0x01
+#define SUBCLASS_AUDIOSTREAMING 0x02
+
+// Audio Descriptor Types
+#define INTERFACE_DESCRIPTOR_TYPE 0x24
+#define ENDPOINT_DESCRIPTOR_TYPE 0x25
+
+// Audio Control Interface Descriptor Subtypes
+#define CONTROL_HEADER 0x01
+#define CONTROL_INPUT_TERMINAL 0x02
+#define CONTROL_OUTPUT_TERMINAL 0x03
+#define CONTROL_FEATURE_UNIT 0x06
+
+// USB Terminal Types
+#define TERMINAL_USB_STREAMING 0x0101
+
+// Predefined Audio Channel Configuration Bits
+// Mono
+#define CHANNEL_M 0x0000
+#define CHANNEL_L 0x0001 /* Left Front */
+#define CHANNEL_R 0x0002 /* Right Front */
+
+// Feature Unit Control Bits
+#define CONTROL_MUTE 0x0001
+#define CONTROL_VOLUME 0x0002
+
+// Input Terminal Types
+#define TERMINAL_MICROPHONE 0x0201
+
+// Output Terminal Types
+#define TERMINAL_SPEAKER 0x0301
+#define TERMINAL_HEADPHONES 0x0302
+
+// Audio Streaming Interface Descriptor Subtypes
+#define STREAMING_GENERAL 0x01
+#define STREAMING_FORMAT_TYPE 0x02
+
+// Audio Data Format Type I Codes
+#define FORMAT_PCM 0x0001
+
+// Audio Format Types
+#define FORMAT_TYPE_I 0x01
+
+// Audio Endpoint Descriptor Subtypes
+#define ENDPOINT_GENERAL 0x01
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_function_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_function_api.h
new file mode 100644
index 000000000..d319e60f3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_function_api.h
@@ -0,0 +1,365 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : devdrv_usb_function_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_FUNCTION_API_H
+#define USB_FUNCTION_API_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <MBRZA1H.h>
+#include "r_typedefs.h"
+#include "usb0_function_api.h"
+#include "usb1_function_api.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct
+{
+ uint32_t fifo;
+ uint32_t buffer;
+ uint32_t bytes;
+ uint32_t dir;
+ uint32_t size;
+} USB_FUNCTION_DMA_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define USBFCLOCK_X1_48MHZ (0x0000u) /* USB_X1_48MHz */
+#define USBFCLOCK_EXTAL_12MHZ (0x0004u) /* EXTAL_12MHz */
+
+#define DEVDRV_USBF_ON (1)
+#define DEVDRV_USBF_OFF (0)
+#define DEVDRV_USBF_YES (1)
+#define DEVDRV_USBF_NO (0)
+
+#define DEVDRV_USBF_STALL (-2)
+
+#define DEVDRV_USBF_WRITEEND (0)
+#define DEVDRV_USBF_WRITESHRT (1)
+#define DEVDRV_USBF_WRITING (2)
+#define DEVDRV_USBF_WRITEDMA (3)
+
+#define DEVDRV_USBF_FIFOERROR (0xffff)
+
+#define DEVDRV_USBF_PIPE_IDLE (0x00)
+#define DEVDRV_USBF_PIPE_WAIT (0x01)
+#define DEVDRV_USBF_PIPE_DONE (0x02)
+#define DEVDRV_USBF_PIPE_NORES (0x03)
+#define DEVDRV_USBF_PIPE_STALL (0x04)
+
+#define DEVDRV_USBF_PID_NAK (0x0000u)
+#define DEVDRV_USBF_PID_BUF (0x0001u)
+#define DEVDRV_USBF_PID_STALL (0x0002u)
+#define DEVDRV_USBF_PID_STALL2 (0x0003u)
+
+#define USB_FUNCTION_NON_SPEED (0)
+#define USB_FUNCTION_LOW_SPEED (1)
+#define USB_FUNCTION_FULL_SPEED (2)
+#define USB_FUNCTION_HIGH_SPEED (3)
+
+#define USB_FUNCTION_READEND (0)
+#define USB_FUNCTION_READSHRT (1)
+#define USB_FUNCTION_READING (2)
+#define USB_FUNCTION_READOVER (3)
+#define USB_FUNCTION_READZERO (4)
+
+#define USB_FUNCTION_MAX_PIPE_NO (15u)
+#define USB_FUNCTION_PIPE0 (0)
+#define USB_FUNCTION_PIPE1 (1)
+#define USB_FUNCTION_PIPE2 (2)
+#define USB_FUNCTION_PIPE3 (3)
+#define USB_FUNCTION_PIPE4 (4)
+#define USB_FUNCTION_PIPE5 (5)
+#define USB_FUNCTION_PIPE6 (6)
+#define USB_FUNCTION_PIPE7 (7)
+#define USB_FUNCTION_PIPE8 (8)
+#define USB_FUNCTION_PIPE9 (9)
+#define USB_FUNCTION_PIPEA (10)
+#define USB_FUNCTION_PIPEB (11)
+#define USB_FUNCTION_PIPEC (12)
+#define USB_FUNCTION_PIPED (13)
+#define USB_FUNCTION_PIPEE (14)
+#define USB_FUNCTION_PIPEF (15)
+
+#define USB_FUNCTION_ISO (0xc000u)
+#define USB_FUNCTION_INTERRUPT (0x8000u)
+#define USB_FUNCTION_BULK (0x4000u)
+
+#define USB_FUNCTION_NONE (0x0000u)
+#define USB_FUNCTON_BFREFIELD (0x0400u)
+#define USB_FUNCTION_BFREON (0x0400u)
+#define USB_FUNCTION_BFREOFF (0x0000u)
+#define USB_FUNCTION_DBLBFIELD (0x0200u)
+#define USB_FUNCTION_DBLBON (0x0200u)
+#define USB_FUNCTION_DBLBOFF (0x0000u)
+#define USB_FUNCTION_CNTMDFIELD (0x0100u)
+#define USB_FUNCTION_CNTMDON (0x0100u)
+#define USB_FUNCTION_CNTMDOFF (0x0000u)
+#define USB_FUNCTION_SHTNAKON (0x0080u)
+#define USB_FUNCTION_SHTNAKOFF (0x0000u)
+#define USB_FUNCTION_DIRFIELD (0x0010u)
+#define USB_FUNCTION_DIR_P_OUT (0x0000u)
+#define USB_FUNCTION_DIR_P_IN (0x0010u)
+#define USB_FUNCTION_EPNUMFIELD (0x000fu)
+#define USB_FUNCTION_MAX_EP_NO (15u)
+#define USB_FUNCTION_EP0 (0u)
+#define USB_FUNCTION_EP1 (1u)
+#define USB_FUNCTION_EP2 (2u)
+#define USB_FUNCTION_EP3 (3u)
+#define USB_FUNCTION_EP4 (4u)
+#define USB_FUNCTION_EP5 (5u)
+#define USB_FUNCTION_EP6 (6u)
+#define USB_FUNCTION_EP7 (7u)
+#define USB_FUNCTION_EP8 (8u)
+#define USB_FUNCTION_EP9 (9u)
+#define USB_FUNCTION_EP10 (10u)
+#define USB_FUNCTION_EP11 (11u)
+#define USB_FUNCTION_EP12 (12u)
+#define USB_FUNCTION_EP13 (13u)
+#define USB_FUNCTION_EP14 (14u)
+#define USB_FUNCTION_EP15 (15u)
+
+#define USB_FUNCTION_EPTABLE_LENGTH (5u)
+
+#define USB_FUNCTION_CUSE (0)
+#define USB_FUNCTION_D0USE (1)
+#define USB_FUNCTION_D0DMA (2)
+#define USB_FUNCTION_D1USE (3)
+#define USB_FUNCTION_D1DMA (4)
+
+#define USB_FUNCTION_CFIFO_USE (0x0000)
+#define USB_FUNCTION_D0FIFO_USE (0x1000)
+#define USB_FUNCTION_D1FIFO_USE (0x2000)
+#define USB_FUNCTION_D0FIFO_DMA (0x5000)
+#define USB_FUNCTION_D1FIFO_DMA (0x6000)
+
+#define USB_FUNCTION_BUF2FIFO (0)
+#define USB_FUNCTION_FIFO2BUF (1)
+
+#define USB_FUNCTION_DVST_POWERED (0x0001)
+#define USB_FUNCTION_DVST_DEFAULT (0x0002)
+#define USB_FUNCTION_DVST_ADDRESS (0x0003)
+#define USB_FUNCTION_DVST_CONFIGURED (0x0004)
+#define USB_FUNCTION_DVST_SUSPEND (0x0005)
+#define USB_FUNCTION_DVST_CONFIGURED_SUSPEND (0x0006)
+
+#define USB_FUNCTION_FUNCTION_TEST_SELECT (0xff00u)
+#define USB_FUNCTION_FUNCTION_TEST_J (0x0100u)
+#define USB_FUNCTION_FUNCTION_TEST_K (0x0200u)
+#define USB_FUNCTION_FUNCTION_TEST_SE0_NAK (0x0300u)
+#define USB_FUNCTION_FUNCTION_TEST_PACKET (0x0400u)
+#define USB_FUNCTION_FUNCTION_TEST_FORCE_ENABLE (0x0500u)
+#define USB_FUNCTION_FUNCTION_TEST_STSelectors (0x0600u)
+#define USB_FUNCTION_FUNCTION_TEST_Reserved (0x4000u)
+#define USB_FUNCTION_FUNCTION_TEST_VSTModes (0xc000u)
+
+#define USB_FUNCTION_DT_TYPE (0xff00u)
+#define USB_FUNCTION_DT_INDEX (0xff)
+#define USB_FUNCTION_DT_DEVICE (0x01)
+#define USB_FUNCTION_DT_CONFIGURATION (0x02)
+#define USB_FUNCTION_DT_STRING (0x03)
+#define USB_FUNCTION_DT_INTERFACE (0x04)
+#define USB_FUNCTION_DT_ENDPOINT (0x05)
+#define USB_FUNCTION_DT_DEVICE_QUALIFIER (0x06)
+#define USB_FUNCTION_DT_OTHER_SPEED_CONFIGURATION (0x07)
+#define USB_FUNCTION_DT_INTERFACE_POWER (0x08)
+
+#define USB_FUNCTION_CF_RESERVED (0x80)
+#define USB_FUNCTION_CF_SELF (0x40)
+#define USB_FUNCTION_CF_RWUP (0x20)
+#define USB_FUNCTION_CF_NORWUP (0x00)
+#define USB_FUNCTION_EP_ERROR (0xff)
+
+#define USB_FUNCTION_EP_OUT (0x00)
+#define USB_FUNCTION_EP_IN (0x80)
+#define USB_FUNCTION_EP_CNTRL (0x00)
+#define USB_FUNCTION_EP_ISO (0x01)
+#define USB_FUNCTION_EP_BULK (0x02)
+#define USB_FUNCTION_EP_INT (0x03)
+
+#define USB_FUNCTION_STANDARD_REQUEST (0x0000u)
+#define USB_FUNCTION_CLASS_REQUEST (0x0020u)
+#define USB_FUNCTION_VENDOR_REQUEST (0x0040u)
+#define USB_FUNCTION_DEVICE_REQUEST (0x0000u)
+#define USB_FUNCTION_INTERFACE_REQUEST (0x0001u)
+#define USB_FUNCTION_ENDPOINT_REQUEST (0x0002u)
+
+#define USB_FUNCTION_GETSTATUS_BUSPOWERD (0x0000u)
+#define USB_FUNCTION_GETSTATUS_SELFPOWERD (0x0001u)
+#define USB_FUNCTION_GETSTATUS_REMOTEWAKEUP (0x0002u)
+#define USB_FUNCTION_GETSTATUS_NOTHALT (0x0000u)
+#define USB_FUNCTION_GETSTATUS_HALT (0x0001u)
+
+#define USB_FUNCTION_FEATURE_ENDPOINT_HALT (0x0000u)
+#define USB_FUNCTION_FEATURE_REMOTE_WAKEUP (0x0001u)
+#define USB_FUNCTION_FEATURE_TEST_MODE (0x0002u)
+
+#define USB_FUNCTION_bRequest (0xff00u) /* b15-8:bRequest */
+#define USB_FUNCTION_bmRequestType (0x00ffu) /* b7-0: bmRequestType */
+#define USB_FUNCTION_bmRequestTypeDir (0x0080u) /* b7 : Data transfer direction */
+#define USB_FUNCTION_bmRequestTypeType (0x0060u) /* b6-5: Type */
+#define USB_FUNCTION_bmRequestTypeRecip (0x001fu) /* b4-0: Recipient */
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+#if 0
+void R_USB_api_function_init(uint16_t root, uint8_t int_level, uint16_t mode, uint16_t clockmode);
+uint16_t R_USB_api_function_IsConfigured(uint16_t root);
+uint16_t R_USB_api_function_CtrlReadStart(uint16_t root, uint32_t size, uint8_t *data);
+void R_USB_api_function_CtrlWriteStart(uint16_t root, uint32_t size, uint8_t *data);
+uint16_t R_USB_api_function_start_send_transfer(uint16_t root, uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t R_USB_api_function_check_pipe_status(uint16_t root, uint16_t pipe, uint32_t *size);
+void R_USB_api_function_clear_pipe_status(uint16_t root, uint16_t pipe);
+void R_USB_api_function_start_receive_transfer(uint16_t root, uint16_t pipe, uint32_t size, uint8_t *data);
+void R_USB_api_function_set_pid_buf(uint16_t root, uint16_t pipe);
+void R_USB_api_function_set_pid_nak(uint16_t root, uint16_t pipe);
+void R_USB_api_function_set_pid_stall(uint16_t root, uint16_t pipe);
+void R_USB_api_function_clear_pid_stall(uint16_t root, uint16_t pipe);
+uint16_t R_USB_api_function_get_pid(uint16_t root, uint16_t pipe);
+int32_t R_USB_api_function_check_stall(uint16_t root, uint16_t pipe);
+void R_USB_api_function_set_sqclr(uint16_t root, uint16_t pipe);
+void R_USB_api_function_set_sqset(uint16_t root, uint16_t pipe);
+void R_USB_api_function_set_csclr(uint16_t root, uint16_t pipe);
+void R_USB_api_function_set_curpipe(uint16_t root, uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void R_USB_api_function_clear_brdy_sts(uint16_t root, uint16_t pipe);
+void R_USB_api_function_clear_bemp_sts(uint16_t root, uint16_t pipe);
+void R_USB_api_function_clear_nrdy_sts(uint16_t root, uint16_t pipe);
+void R_USB_api_function_enable_brdy_int(uint16_t root, uint16_t pipe);
+void R_USB_api_function_disable_brdy_int(uint16_t root, uint16_t pipe);
+void R_USB_api_function_enable_bemp_int(uint16_t root, uint16_t pipe);
+void R_USB_api_function_disable_bemp_int(uint16_t root, uint16_t pipe);
+void R_USB_api_function_enable_nrdy_int(uint16_t root, uint16_t pipe);
+void R_USB_api_function_disable_nrdy_int(uint16_t root, uint16_t pipe);
+void R_USB_api_function_stop_transfer(uint16_t root, uint16_t pipe);
+#endif
+
+#ifdef USB0_FUNCTION_API_H
+void usb0_function_interrupt(uint32_t int_sense);
+void usb0_function_dma_interrupt_d0fifo(uint32_t int_sense);
+void usb0_function_dma_interrupt_d1fifo(uint32_t int_sense);
+
+void usb0_function_Class0(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Class1(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Class2(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Class3(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Class4(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Class5(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Vendor0(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Vendor1(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Vendor2(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Vendor3(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Vendor4(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Vendor5(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_ResetDescriptor(uint16_t mode);
+
+IRQn_Type Userdef_USB_usb0_function_d0fifo_dmaintid(void);
+IRQn_Type Userdef_USB_usb0_function_d1fifo_dmaintid(void);
+void Userdef_USB_usb0_function_attach(void);
+void Userdef_USB_usb0_function_detach(void);
+void Userdef_USB_usb0_function_delay_1ms(void);
+void Userdef_USB_usb0_function_delay_xms(uint32_t msec);
+void Userdef_USB_usb0_function_delay_10us(uint32_t usec);
+void Userdef_USB_usb0_function_delay_500ns(void);
+void Userdef_USB_usb0_function_start_dma(USB_FUNCTION_DMA_t *dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb0_function_stop_dma0(void);
+uint32_t Userdef_USB_usb0_function_stop_dma1(void);
+
+void usb0_function_stop_transfer(uint16_t pipe);
+void usb0_function_enable_brdy_int(uint16_t pipe);
+void usb0_function_disable_brdy_int(uint16_t pipe);
+void usb0_function_enable_bemp_int(uint16_t pipe);
+void usb0_function_disable_bemp_int(uint16_t pipe);
+void usb0_function_enable_nrdy_int(uint16_t pipe);
+void usb0_function_disable_nrdy_int(uint16_t pipe);
+#endif
+
+#ifdef USB1_FUNCTION_API_H
+void usb1_function_interrupt(uint32_t int_sense);
+void usb1_function_dma_interrupt_d0fifo(uint32_t int_sense);
+void usb1_function_dma_interrupt_d1fifo(uint32_t int_sense);
+
+void usb1_function_Class0(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Class1(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Class2(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Class3(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Class4(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Class5(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Vendor0(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Vendor1(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Vendor2(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Vendor3(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Vendor4(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Vendor5(uint16_t type, uint16_t req, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_ResetDescriptor(uint16_t mode);
+
+uint16_t Userdef_USB_usb1_function_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb1_function_d1fifo_dmaintid(void);
+void Userdef_USB_usb1_function_attach(void);
+void Userdef_USB_usb1_function_detach(void);
+void Userdef_USB_usb1_function_delay_1ms(void);
+void Userdef_USB_usb1_function_delay_xms(uint32_t msec);
+void Userdef_USB_usb1_function_delay_10us(uint32_t usec);
+void Userdef_USB_usb1_function_delay_500ns(void);
+void Userdef_USB_usb1_function_start_dma(USB_FUNCTION_DMA_t *dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb1_function_stop_dma0(void);
+uint32_t Userdef_USB_usb1_function_stop_dma1(void);
+
+void usb1_function_stop_transfer(uint16_t pipe);
+void usb1_function_enable_brdy_int(uint16_t pipe);
+void usb1_function_disable_brdy_int(uint16_t pipe);
+void usb1_function_enable_bemp_int(uint16_t pipe);
+void usb1_function_disable_bemp_int(uint16_t pipe);
+void usb1_function_enable_nrdy_int(uint16_t pipe);
+void usb1_function_disable_nrdy_int(uint16_t pipe);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* USB_FUNCTION_API_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_function.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_function.h
new file mode 100644
index 000000000..090e51c10
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_function.h
@@ -0,0 +1,143 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb_function.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_FUNCTION_H
+#define USB_FUNCTION_H
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define USB_FUNCTION_ALT_NO (255)
+#define USB_FUNCTION_ALT_SET (0xff)
+
+#define USB_FUNCTION_BITUPLLE (0x0002u)
+#define USB_FUNCTION_BITUCKSEL (0x0004u)
+#define USB_FUNCTION_BITBWAIT (0x003fu)
+
+#define USB_FUNCTION_BUSWAIT_02 (0x0000u)
+#define USB_FUNCTION_BUSWAIT_03 (0x0001u)
+#define USB_FUNCTION_BUSWAIT_04 (0x0002u)
+#define USB_FUNCTION_BUSWAIT_05 (0x0003u)
+#define USB_FUNCTION_BUSWAIT_06 (0x0004u)
+#define USB_FUNCTION_BUSWAIT_07 (0x0005u)
+#define USB_FUNCTION_BUSWAIT_08 (0x0006u)
+#define USB_FUNCTION_BUSWAIT_09 (0x0007u)
+#define USB_FUNCTION_BUSWAIT_10 (0x0008u)
+#define USB_FUNCTION_BUSWAIT_11 (0x0009u)
+#define USB_FUNCTION_BUSWAIT_12 (0x000au)
+#define USB_FUNCTION_BUSWAIT_13 (0x000bu)
+#define USB_FUNCTION_BUSWAIT_14 (0x000cu)
+#define USB_FUNCTION_BUSWAIT_15 (0x000du)
+#define USB_FUNCTION_BUSWAIT_16 (0x000eu)
+#define USB_FUNCTION_BUSWAIT_17 (0x000fu)
+
+#define USB_FUNCTION_BITRESUME (0x0020u)
+#define USB_FUNCTION_BITUACT (0x0010u)
+#define USB_FUNCTION_HSPROC (0x0004u)
+#define USB_FUNCTION_HSMODE (0x0003u)
+#define USB_FUNCTION_FSMODE (0x0002u)
+#define USB_FUNCTION_LSMODE (0x0001u)
+#define USB_FUNCTION_UNDECID (0x0000u)
+
+#define USB_FUNCTION_BITRCNT (0x8000u)
+#define USB_FUNCTION_BITDREQE (0x1000u)
+#define USB_FUNCTION_BITMBW (0x0c00u)
+#define USB_FUNCTION_BITMBW_8 (0x0000u)
+#define USB_FUNCTION_BITMBW_16 (0x0400u)
+#define USB_FUNCTION_BITMBW_32 (0x0800u)
+#define USB_FUNCTION_BITBYTE_LITTLE (0x0000u)
+#define USB_FUNCTION_BITBYTE_BIG (0x0100u)
+#define USB_FUNCTION_BITISEL (0x0020u)
+#define USB_FUNCTION_BITCURPIPE (0x000fu)
+
+#define USB_FUNCTION_CFIFO_READ (0x0000u)
+#define USB_FUNCTION_CFIFO_WRITE (0x0020u)
+
+#define USB_FUNCTION_BITBVAL (0x8000u)
+#define USB_FUNCTION_BITBCLR (0x4000u)
+#define USB_FUNCTION_BITFRDY (0x2000u)
+#define USB_FUNCTION_BITDTLN (0x0fffu)
+
+#define USB_FUNCTION_BITVBSE (0x8000u)
+#define USB_FUNCTION_BITRSME (0x4000u)
+#define USB_FUNCTION_BITSOFE (0x2000u)
+#define USB_FUNCTION_BITDVSE (0x1000u)
+#define USB_FUNCTION_BITCTRE (0x0800u)
+#define USB_FUNCTION_BITVBINT (0x8000u)
+#define USB_FUNCTION_BITRESM (0x4000u)
+#define USB_FUNCTION_BITSOFR (0x2000u)
+#define USB_FUNCTION_BITDVST (0x1000u)
+#define USB_FUNCTION_BITCTRT (0x0800u)
+
+#define USB_FUNCTION_BITBEMPE (0x0400u)
+#define USB_FUNCTION_BITNRDYE (0x0200u)
+#define USB_FUNCTION_BITBRDYE (0x0100u)
+#define USB_FUNCTION_BITBEMP (0x0400u)
+#define USB_FUNCTION_BITNRDY (0x0200u)
+#define USB_FUNCTION_BITBRDY (0x0100u)
+
+#define USB_FUNCTION_BITDVSQ (0x0070u)
+#define USB_FUNCTION_BITDVSQS (0x0030u)
+#define USB_FUNCTION_DS_SPD_CNFG (0x0070u)
+#define USB_FUNCTION_DS_SPD_ADDR (0x0060u)
+#define USB_FUNCTION_DS_SPD_DFLT (0x0050u)
+#define USB_FUNCTION_DS_SPD_POWR (0x0040u)
+#define USB_FUNCTION_DS_CNFG (0x0030u)
+#define USB_FUNCTION_DS_ADDS (0x0020u)
+#define USB_FUNCTION_DS_DFLT (0x0010u)
+#define USB_FUNCTION_DS_POWR (0x0000u)
+#define USB_FUNCTION_BITVALID (0x0008u)
+#define USB_FUNCTION_BITCTSQ (0x0007u)
+#define USB_FUNCTION_CS_SQER (0x0006u)
+#define USB_FUNCTION_CS_WRND (0x0005u)
+#define USB_FUNCTION_CS_WRSS (0x0004u)
+#define USB_FUNCTION_CS_WRDS (0x0003u)
+#define USB_FUNCTION_CS_RDSS (0x0002u)
+#define USB_FUNCTION_CS_RDDS (0x0001u)
+#define USB_FUNCTION_CS_IDST (0x0000u)
+
+#define USB_FUNCTION_PIPExBUF (64u)
+
+#define USB_FUNCTION_D0FIFO (0)
+#define USB_FUNCTION_D1FIFO (1)
+#define USB_FUNCTION_DMA_READY (0)
+#define USB_FUNCTION_DMA_BUSY (1)
+#define USB_FUNCTION_DMA_BUSYEND (2)
+
+#define USB_FUNCTION_FIFO_USE (0x7000)
+
+#endif /* USB_FUNCTION_FUNCTION_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_function_version.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_function_version.h
new file mode 100644
index 000000000..d26e3b083
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_function_version.h
@@ -0,0 +1,32 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb_function_version.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+
+#define USB_FUNCTION_LOCAL_Rev "VER080_140709"
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function.h
new file mode 100644
index 000000000..02855eb13
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function.h
@@ -0,0 +1,171 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_FUNCTION_H
+#define USB0_FUNCTION_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_function_api.h"
+#include "usb_function.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern const uint16_t g_usb0_function_bit_set[];
+extern uint32_t g_usb0_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint8_t *g_usb0_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+extern uint16_t g_usb0_function_PipeIgnore[];
+extern uint16_t g_usb0_function_PipeTbl[];
+extern uint16_t g_usb0_function_pipe_status[];
+extern uint32_t g_usb0_function_PipeDataSize[];
+
+extern USB_FUNCTION_DMA_t g_usb0_function_DmaInfo[];
+extern uint16_t g_usb0_function_DmaPipe[];
+extern uint16_t g_usb0_function_DmaBval[];
+extern uint16_t g_usb0_function_DmaStatus[];
+
+extern uint16_t g_usb0_function_CtrZeroLengthFlag;
+
+extern uint16_t g_usb0_function_ConfigNum;
+extern uint16_t g_usb0_function_Alternate[USB_FUNCTION_ALT_NO];
+extern uint16_t g_usb0_function_RemoteWakeupFlag;
+extern uint16_t g_usb0_function_TestModeFlag;
+extern uint16_t g_usb0_function_TestModeSelectors;
+
+extern uint16_t g_usb0_function_ReqType;
+extern uint16_t g_usb0_function_ReqTypeType;
+extern uint16_t g_usb0_function_ReqTypeRecip;
+extern uint16_t g_usb0_function_ReqRequest;
+extern uint16_t g_usb0_function_ReqValue;
+extern uint16_t g_usb0_function_ReqIndex;
+extern uint16_t g_usb0_function_ReqLength;
+
+extern uint16_t g_usb0_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1];
+
+extern uint16_t g_usb0_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint16_t g_usb0_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint16_t g_usb0_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint16_t g_usb0_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+/* ==== common ==== */
+void usb0_function_dma_stop_d0(uint16_t pipe, uint32_t remain);
+void usb0_function_dma_stop_d1(uint16_t pipe, uint32_t remain);
+uint16_t usb0_function_is_hispeed(void);
+uint16_t usb0_function_is_hispeed_enable(void);
+uint16_t usb0_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb0_function_write_buffer(uint16_t pipe);
+uint16_t usb0_function_write_buffer_c(uint16_t pipe);
+uint16_t usb0_function_write_buffer_d0(uint16_t pipe);
+uint16_t usb0_function_write_buffer_d1(uint16_t pipe);
+void usb0_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb0_function_read_buffer(uint16_t pipe);
+uint16_t usb0_function_read_buffer_c(uint16_t pipe);
+uint16_t usb0_function_read_buffer_d0(uint16_t pipe);
+uint16_t usb0_function_read_buffer_d1(uint16_t pipe);
+uint16_t usb0_function_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb0_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb0_function_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc);
+uint16_t usb0_function_get_mbw(uint32_t trncount, uint32_t dtptr);
+uint16_t usb0_function_read_dma(uint16_t pipe);
+void usb0_function_brdy_int(uint16_t status, uint16_t int_enb);
+void usb0_function_nrdy_int(uint16_t status, uint16_t int_enb);
+void usb0_function_bemp_int(uint16_t status, uint16_t int_enb);
+void usb0_function_setting_interrupt(uint8_t level);
+void usb0_function_reset_module(uint16_t clockmode);
+uint16_t usb0_function_get_buf_size(uint16_t pipe);
+uint16_t usb0_function_get_mxps(uint16_t pipe);
+void usb0_function_clear_brdy_sts(uint16_t pipe);
+void usb0_function_clear_bemp_sts(uint16_t pipe);
+void usb0_function_clear_nrdy_sts(uint16_t pipe);
+void usb0_function_set_pid_buf(uint16_t pipe);
+void usb0_function_set_pid_nak(uint16_t pipe);
+void usb0_function_set_pid_stall(uint16_t pipe);
+void usb0_function_clear_pid_stall(uint16_t pipe);
+uint16_t usb0_function_get_pid(uint16_t pipe);
+void usb0_function_set_sqclr(uint16_t pipe);
+void usb0_function_set_sqset(uint16_t pipe);
+void usb0_function_set_csclr(uint16_t pipe);
+void usb0_function_aclrm(uint16_t pipe);
+void usb0_function_set_aclrm(uint16_t pipe);
+void usb0_function_clr_aclrm(uint16_t pipe);
+uint16_t usb0_function_get_sqmon(uint16_t pipe);
+uint16_t usb0_function_get_inbuf(uint16_t pipe);
+
+/* ==== function ==== */
+void usb0_function_init_status(void);
+void usb0_function_InitModule(uint16_t mode);
+uint16_t usb0_function_CheckVBUStaus(void);
+void usb0_function_USB_FUNCTION_Attach(void);
+void usb0_function_USB_FUNCTION_Detach(void);
+void usb0_function_USB_FUNCTION_BusReset(void);
+void usb0_function_USB_FUNCTION_Resume(void);
+void usb0_function_USB_FUNCTION_Suspend(void);
+void usb0_function_USB_FUNCTION_TestMode(void);
+void usb0_function_ResetDCP(void);
+void usb0_function_ResetEP(uint16_t num);
+uint16_t usb0_function_EpToPipe(uint16_t ep);
+void usb0_function_InitEPTable(uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num);
+uint16_t usb0_function_GetConfigNum(void);
+uint16_t usb0_function_GetAltNum(uint16_t Con_Num, uint16_t Int_Num);
+uint16_t usb0_function_CheckRemoteWakeup(void);
+void usb0_function_clear_alt(void);
+void usb0_function_clear_pipe_tbl(void);
+void usb0_function_clear_ep_table_index(void);
+uint16_t usb0_function_GetInterfaceNum(uint16_t num);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* USB0_FUNCTION_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_api.h
new file mode 100644
index 000000000..c33b3e63e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_api.h
@@ -0,0 +1,104 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_FUNCTION_API_H
+#define USB0_FUNCTION_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void usb0_api_function_init(uint8_t int_level, uint16_t mode, uint16_t clockmode);
+uint16_t usb0_api_function_IsConfigured(void);
+uint16_t usb0_function_GetDeviceState(void);
+uint16_t usb0_api_function_CtrlReadStart(uint32_t size, uint8_t *data);
+void usb0_api_function_CtrlWriteStart(uint32_t size, uint8_t *data);
+uint16_t usb0_api_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb0_api_function_check_pipe_status(uint16_t pipe, uint32_t *size);
+void usb0_api_function_clear_pipe_status(uint16_t pipe);
+void usb0_api_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+void usb0_api_function_set_pid_buf(uint16_t pipe);
+void usb0_api_function_set_pid_nak(uint16_t pipe);
+void usb0_api_function_set_pid_stall(uint16_t pipe);
+void usb0_api_function_clear_pid_stall(uint16_t pipe);
+uint16_t usb0_api_function_get_pid(uint16_t pipe);
+int32_t usb0_api_function_check_stall(uint16_t pipe);
+void usb0_api_function_set_sqclr(uint16_t pipe);
+void usb0_api_function_set_sqset(uint16_t pipe);
+void usb0_api_function_set_csclr(uint16_t pipe);
+void usb0_api_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb0_api_function_clear_brdy_sts(uint16_t pipe);
+void usb0_api_function_clear_bemp_sts(uint16_t pipe);
+void usb0_api_function_clear_nrdy_sts(uint16_t pipe);
+
+void usb0_function_ClearFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_SetFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_SetAddress(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_SetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_SetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_SetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_SynchFrame(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_GetStatus(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_GetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_GetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_GetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Resrv_0(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Resrv_123(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Resrv_4(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb0_function_Resrv_5(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB0_FUNCTION_API_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_dmacdrv.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_dmacdrv.h
new file mode 100644
index 000000000..d74bac718
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_function_dmacdrv.h
@@ -0,0 +1,142 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_dmacdrv.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_FUNCTION_DMACDRV_H
+#define USB0_FUNCTION_DMACDRV_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct dmac_transinfo
+{
+ uint32_t src_addr; /* Transfer source address */
+ uint32_t dst_addr; /* Transfer destination address */
+ uint32_t count; /* Transfer byte count */
+ uint32_t src_size; /* Transfer source data size */
+ uint32_t dst_size; /* Transfer destination data size */
+ uint32_t saddr_dir; /* Transfer source address direction */
+ uint32_t daddr_dir; /* Transfer destination address direction */
+} dmac_transinfo_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+/* ==== Transfer specification of the sample program ==== */
+#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */
+#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */
+
+/* ==== DMA modes ==== */
+#define DMAC_MODE_REGISTER (0) /* Register mode */
+#define DMAC_MODE_LINK (1) /* Link mode */
+
+/* ==== Transfer requests ==== */
+#define DMAC_REQ_MODE_EXT (0) /* External request */
+#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */
+#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */
+
+/* ==== DMAC transfer sizes ==== */
+#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */
+#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */
+#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */
+#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */
+#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */
+#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */
+#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */
+#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */
+
+/* ==== Address increment for transferring ==== */
+#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */
+#define DMAC_TRANS_ADR_INC (0) /* Increment */
+
+/* ==== Method for detecting DMA request ==== */
+#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */
+#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */
+#define DMAC_REQ_DET_LOW (2) /* Low level detection */
+#define DMAC_REQ_DET_HIGH (3) /* High level detection */
+
+/* ==== Request Direction ==== */
+#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */
+#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */
+
+/* ==== Descriptors ==== */
+#define DMAC_DESC_HEADER (0) /* Header */
+#define DMAC_DESC_SRC_ADDR (1) /* Source Address */
+#define DMAC_DESC_DST_ADDR (2) /* Destination Address */
+#define DMAC_DESC_COUNT (3) /* Transaction Byte */
+#define DMAC_DESC_CHCFG (4) /* Channel Confg */
+#define DMAC_DESC_CHITVL (5) /* Channel Interval */
+#define DMAC_DESC_CHEXT (6) /* Channel Extension */
+#define DMAC_DESC_LINK_ADDR (7) /* Link Address */
+
+/* ==== On-chip peripheral module requests ===== */
+typedef enum dmac_request_factor
+{
+ DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */
+ DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */
+ DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */
+ DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */
+} dmac_request_factor_t;
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void usb0_function_DMAC1_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb0_function_DMAC1_Open(uint32_t req);
+void usb0_function_DMAC1_Close(uint32_t *remain);
+void usb0_function_DMAC1_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+void usb0_function_DMAC2_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb0_function_DMAC2_Open(uint32_t req);
+void usb0_function_DMAC2_Close(uint32_t *remain);
+void usb0_function_DMAC2_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB0_FUNCTION_DMACDRV_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dataio.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dataio.c
new file mode 100644
index 000000000..2f283c738
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dataio.c
@@ -0,0 +1,2933 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_dataio.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static uint16_t g_usb0_function_mbw[(USB_FUNCTION_MAX_PIPE_NO + 1)];
+
+static void usb0_function_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_function_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_function_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_function_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_function_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static uint16_t usb0_function_read_dma_d0(uint16_t pipe);
+static uint16_t usb0_function_read_dma_d1(uint16_t pipe);
+static uint16_t usb0_function_write_dma_d0(uint16_t pipe);
+static uint16_t usb0_function_write_dma_d1(uint16_t pipe);
+
+static void usb0_function_read_c_fifo(uint16_t pipe, uint16_t count);
+static void usb0_function_write_c_fifo(uint16_t Pipe, uint16_t count);
+static void usb0_function_read_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb0_function_write_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb0_function_read_d1_fifo(uint16_t pipe, uint16_t count);
+static void usb0_function_write_d1_fifo(uint16_t pipe, uint16_t count);
+
+static void usb0_function_clear_transaction_counter(uint16_t pipe);
+static void usb0_function_set_transaction_counter(uint16_t pipe, uint32_t count);
+
+static uint32_t usb0_function_com_get_dmasize(uint32_t trncount, uint32_t dtptr);
+
+static uint16_t usb0_function_set_dfacc_d0(uint16_t mbw, uint32_t count);
+static uint16_t usb0_function_set_dfacc_d1(uint16_t mbw, uint32_t count);
+
+
+/*******************************************************************************
+* Function Name: usb0_function_start_send_transfer
+* Description : Starts the USB data communication using pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+ uint16_t usefifo;
+ uint16_t mbw;
+
+ g_usb0_function_data_count[pipe] = size;
+ g_usb0_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ usb0_function_clear_bemp_sts(pipe);
+ usb0_function_clear_brdy_sts(pipe);
+ usb0_function_clear_nrdy_sts(pipe);
+
+ mbw = usb0_function_get_mbw(size, (uint32_t)data);
+
+ usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ case USB_FUNCTION_D0FIFO_DMA:
+ usefifo = USB_FUNCTION_D0USE;
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ case USB_FUNCTION_D1FIFO_DMA:
+ usefifo = USB_FUNCTION_D1USE;
+ break;
+
+ default:
+ usefifo = USB_FUNCTION_CUSE;
+ break;
+ };
+
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, usefifo, DEVDRV_USBF_NO, mbw);
+
+ usb0_function_clear_transaction_counter(pipe);
+
+ usb0_function_aclrm(pipe);
+
+ status = usb0_function_write_buffer(pipe);
+
+ if (status != DEVDRV_USBF_FIFOERROR)
+ {
+ usb0_function_set_pid_buf(pipe);
+ }
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_buffer
+* Description : Writes data in the buffer allocated in the pipe specified by
+* : the argument. The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_write_buffer (uint16_t pipe)
+{
+ uint16_t status;
+ uint16_t usefifo;
+
+ g_usb0_function_PipeIgnore[pipe] = 0;
+ usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ status = usb0_function_write_buffer_d0(pipe);
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ status = usb0_function_write_buffer_d1(pipe);
+ break;
+
+ case USB_FUNCTION_D0FIFO_DMA:
+ status = usb0_function_write_dma_d0(pipe);
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ status = usb0_function_write_dma_d1(pipe);
+ break;
+
+ default:
+ status = usb0_function_write_buffer_c(pipe);
+ break;
+ };
+
+ switch (status)
+ {
+ case DEVDRV_USBF_WRITING: /* Continue of data write */
+ usb0_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ usb0_function_enable_brdy_int(pipe); /* Enable Ready Interrupt */
+ break;
+
+ case DEVDRV_USBF_WRITEEND: /* End of data write */
+ case DEVDRV_USBF_WRITESHRT: /* End of data write */
+ usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ usb0_function_clear_nrdy_sts(pipe);
+ usb0_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ /* for last transfer */
+ usb0_function_enable_bemp_int(pipe); /* Enable Empty Interrupt */
+ break;
+
+ case DEVDRV_USBF_WRITEDMA: /* DMA write */
+ usb0_function_clear_nrdy_sts(pipe);
+ usb0_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ usb0_function_disable_bemp_int(pipe); /* Disable Empty Interrupt */
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_buffer_c
+* Description : Writes data in the buffer allocated in the pipe specified in
+* : the argument. Writes data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_write_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ if (g_usb0_function_CtrZeroLengthFlag == 1)
+ {
+ g_usb0_function_CtrZeroLengthFlag = 0; /* Zero Length Packet Flag CLR */
+ return DEVDRV_USBF_WRITEEND;
+ }
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ if (pipe == USB_FUNCTION_PIPE0)
+ {
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw);
+ }
+ else
+ {
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, DEVDRV_USBF_NO, mbw);
+ }
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] <= (uint32_t)size)
+ {
+ status = DEVDRV_USBF_WRITEEND; /* write continues */
+ count = g_usb0_function_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = DEVDRV_USBF_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_function_write_c_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_function_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_function_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB200.CFIFOCTR, USB_CFIFOCTR_BVAL_SHIFT, USB_CFIFOCTR_BVAL) == 0)
+ {
+ USB200.CFIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */
+ g_usb0_function_CtrZeroLengthFlag = 1; /* Zero Length Packet Flag */
+ }
+ }
+ else
+ {
+ g_usb0_function_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_buffer_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_write_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] <= (uint32_t)size)
+ {
+ status = DEVDRV_USBF_WRITEEND; /* write continues */
+ count = g_usb0_function_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = DEVDRV_USBF_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_function_write_d0_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_function_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_function_data_count[pipe] = 0;
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb0_function_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_buffer_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_write_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] <= (uint32_t)size)
+ {
+ status = DEVDRV_USBF_WRITEEND; /* write continues */
+ count = g_usb0_function_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = DEVDRV_USBF_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_function_write_d1_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_function_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_function_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb0_function_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D0FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb0_function_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND : Write end
+* : DEVDRV_USBF_WRITESHRT : short data
+* : DEVDRV_USBF_WRITING : Continue of data write
+* : DEVDRV_USBF_WRITEDMA : Write DMA
+* : DEVDRV_USBF_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb0_function_write_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb0_function_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb0_function_DmaPipe[USB_FUNCTION_D0FIFO] = pipe;
+
+ if ((count % size) != 0)
+ {
+ g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] = 1;
+ }
+ else
+ {
+ g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] = 0;
+ }
+
+ dfacc = usb0_function_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].fifo = USB_FUNCTION_D0FIFO_DMA;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].dir = USB_FUNCTION_BUF2FIFO;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe];
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].bytes = count;
+
+ Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO], dfacc);
+
+ usb0_function_set_curpipe2(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, 1, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+
+ g_usb0_function_data_count[pipe] = 0;
+ g_usb0_function_data_pointer[pipe] += count;
+ status = DEVDRV_USBF_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FIFOCTR, 1, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_dma_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D1FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb0_function_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND : Write end
+* : DEVDRV_USBF_WRITESHRT : short data
+* : DEVDRV_USBF_WRITING : Continue of data write
+* : DEVDRV_USBF_WRITEDMA : Write DMA
+* : DEVDRV_USBF_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb0_function_write_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc=0;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb0_function_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb0_function_DmaPipe[USB_FUNCTION_D1FIFO] = pipe;
+ if ((count % size) != 0)
+ {
+ g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] = 1;
+ }
+ else
+ {
+ g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] = 0;
+ }
+
+ dfacc = usb0_function_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].fifo = USB_FUNCTION_D1FIFO_DMA;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].dir = USB_FUNCTION_BUF2FIFO;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe];
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].bytes = count;
+
+ Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO], dfacc);
+
+ usb0_function_set_curpipe2(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, 1, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+
+ g_usb0_function_data_count[pipe] = 0;
+ g_usb0_function_data_pointer[pipe] += count;
+
+ status = DEVDRV_USBF_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FIFOCTR, 1, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_start_receive_transfer
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb0_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t usefifo;
+
+ usb0_function_clear_bemp_sts(pipe);
+ usb0_function_clear_brdy_sts(pipe);
+ usb0_function_clear_nrdy_sts(pipe);
+
+ usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ usb0_function_start_receive_trns_d0(pipe, size, data);
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ usb0_function_start_receive_trns_d1(pipe, size, data);
+ break;
+
+ case USB_FUNCTION_D0FIFO_DMA:
+ usb0_function_start_receive_dma_d0(pipe, size, data);
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ usb0_function_start_receive_dma_d1(pipe, size, data);
+ break;
+
+ default:
+ usb0_function_start_receive_trns_c(pipe, size, data);
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_start_receive_trns_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* : When storing data in the buffer allocated in the pipe specified in the
+* : argument, BRDY interrupt is generated to read data
+* : in the interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_function_set_pid_nak(pipe);
+ g_usb0_function_data_count[pipe] = size;
+ g_usb0_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_function_PipeIgnore[pipe] = 0;
+
+ g_usb0_function_PipeDataSize[pipe] = size;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb0_function_get_mbw(size, (uint32_t)data);
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_READ, mbw);
+ USB200.CFIFOCTR = USB_FUNCTION_BITBCLR;
+
+ usb0_function_set_transaction_counter(pipe, size);
+
+ usb0_function_aclrm(pipe);
+
+ usb0_function_enable_nrdy_int(pipe);
+ usb0_function_enable_brdy_int(pipe);
+
+ usb0_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_start_receive_trns_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data in the
+* : interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_function_set_pid_nak(pipe);
+ g_usb0_function_data_count[pipe] = size;
+ g_usb0_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_function_PipeIgnore[pipe] = 0;
+
+ g_usb0_function_PipeDataSize[pipe] = size;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb0_function_get_mbw(size, (uint32_t)data);
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+
+ usb0_function_set_transaction_counter(pipe, size);
+
+ usb0_function_aclrm(pipe);
+
+ usb0_function_enable_nrdy_int(pipe);
+ usb0_function_enable_brdy_int(pipe);
+
+ usb0_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_start_receive_trns_d1
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_function_set_pid_nak(pipe);
+ g_usb0_function_data_count[pipe] = size;
+ g_usb0_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_function_PipeIgnore[pipe] = 0;
+
+ g_usb0_function_PipeDataSize[pipe] = size;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb0_function_get_mbw(size, (uint32_t)data);
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ usb0_function_set_transaction_counter(pipe, size);
+
+ usb0_function_aclrm(pipe);
+
+ usb0_function_enable_nrdy_int(pipe);
+ usb0_function_enable_brdy_int(pipe);
+
+ usb0_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_start_receive_dma_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_function_set_pid_nak(pipe);
+ g_usb0_function_data_count[pipe] = size;
+ g_usb0_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_function_PipeIgnore[pipe] = 0;
+
+ g_usb0_function_PipeDataSize[pipe] = 0;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb0_function_get_mbw(size, (uint32_t)data);
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+
+ usb0_function_set_transaction_counter(pipe, size);
+
+ usb0_function_aclrm(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb0_function_read_dma(pipe);
+
+ usb0_function_enable_nrdy_int(pipe);
+ usb0_function_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb0_function_enable_nrdy_int(pipe);
+ usb0_function_enable_brdy_int(pipe);
+ }
+
+ usb0_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_start_receive_dma_d1
+* Description : Read data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_function_set_pid_nak(pipe);
+ g_usb0_function_data_count[pipe] = size;
+ g_usb0_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_function_PipeIgnore[pipe] = 0;
+
+ g_usb0_function_PipeDataSize[pipe] = 0;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb0_function_get_mbw(size, (uint32_t)data);
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ usb0_function_set_transaction_counter(pipe, size);
+
+ usb0_function_aclrm(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb0_function_read_dma(pipe);
+
+ usb0_function_enable_nrdy_int(pipe);
+ usb0_function_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb0_function_enable_nrdy_int(pipe);
+ usb0_function_enable_brdy_int(pipe);
+ }
+
+ usb0_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_buffer
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Uses FIF0 set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_read_buffer (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb0_function_PipeIgnore[pipe] = 0;
+
+ if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_USE)
+ {
+ status = usb0_function_read_buffer_d0(pipe);
+ }
+ else if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_USE)
+ {
+ status = usb0_function_read_buffer_d1(pipe);
+ }
+ else
+ {
+ status = usb0_function_read_buffer_c(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_FUNCTION_READING: /* Continue of data read */
+ break;
+
+ case USB_FUNCTION_READEND: /* End of data read */
+ case USB_FUNCTION_READSHRT: /* End of data read */
+ usb0_function_disable_brdy_int(pipe);
+ g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe];
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ break;
+
+ case USB_FUNCTION_READOVER: /* buffer over */
+ if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_USE)
+ {
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_USE)
+ {
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe];
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_buffer_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_read_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_function_data_count[pipe];
+ }
+ else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_function_read_c_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_function_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_buffer_d0
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_read_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_function_data_count[pipe];
+ }
+ else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_function_read_d0_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_function_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_buffer_d1
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_read_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_function_data_count[pipe];
+ }
+ else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb0_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_function_read_d1_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_function_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_dma
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO or D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_function_read_dma (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb0_function_PipeIgnore[pipe] = 0;
+ if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA)
+ {
+ status = usb0_function_read_dma_d0(pipe);
+ }
+ else
+ {
+ status = usb0_function_read_dma_d1(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_FUNCTION_READING: /* Continue of data read */
+ break;
+
+ case USB_FUNCTION_READZERO: /* End of data read */
+ usb0_function_disable_brdy_int(pipe);
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ break;
+
+ case USB_FUNCTION_READEND: /* End of data read */
+ case USB_FUNCTION_READSHRT: /* End of data read */
+ usb0_function_disable_brdy_int(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe];
+ }
+ break;
+
+ case USB_FUNCTION_READOVER: /* buffer over */
+ usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb0_function_PipeDataSize[pipe] -= g_usb0_function_data_count[pipe];
+ }
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READZERO ; zero data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb0_function_read_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb0_function_data_count[pipe];
+ status = USB_FUNCTION_READING;
+ }
+ else
+ {
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ count = g_usb0_function_data_count[pipe];
+ }
+ else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ status = USB_FUNCTION_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb0_function_set_curpipe(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb0_function_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_function_DmaPipe[USB_FUNCTION_D0FIFO] = pipe; /* not use in read operation */
+ g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] = 0; /* not use in read operation */
+
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].fifo = USB_FUNCTION_D0FIFO_DMA;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].dir = USB_FUNCTION_FIFO2BUF;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe];
+ g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].bytes = count;
+
+ if (status == USB_FUNCTION_READING)
+ {
+ g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_BUSY;
+ }
+ else
+ {
+ g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO], dfacc);
+
+ usb0_function_set_curpipe2(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb0_function_data_count[pipe] -= count;
+ g_usb0_function_data_pointer[pipe] += count;
+ g_usb0_function_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_dma_d1
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by DMA transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READZERO ; zero data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb0_function_read_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc=0;
+ uint16_t pipebuf_size;
+
+ g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[pipe], (uint32_t)g_usb0_function_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb0_function_data_count[pipe];
+ status = USB_FUNCTION_READING;
+ }
+ else
+ {
+ buffer = usb0_function_change_fifo_port(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw);
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ count = g_usb0_function_data_count[pipe];
+ }
+ else if (g_usb0_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb0_function_get_buf_size(pipe); /* Data buffer size */
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ status = USB_FUNCTION_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb0_function_set_curpipe(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb0_function_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_function_DmaPipe[USB_FUNCTION_D1FIFO] = pipe; /* not use in read operation */
+ g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] = 0; /* not use in read operation */
+
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].fifo = USB_FUNCTION_D1FIFO_DMA;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].dir = USB_FUNCTION_FIFO2BUF;
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].buffer = (uint32_t)g_usb0_function_data_pointer[pipe];
+ g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].bytes = count;
+
+ if (status == USB_FUNCTION_READING)
+ {
+ g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_BUSY;
+ }
+ else
+ {
+ g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb0_function_start_dma(&g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO], dfacc);
+
+ usb0_function_set_curpipe2(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb0_function_data_count[pipe] -= count;
+ g_usb0_function_data_pointer[pipe] += count;
+ g_usb0_function_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_change_fifo_port
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument. After allocating FIF0, waits in the software
+* : till the corresponding pipe becomes ready.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : DEVDRV_USBF_FIFOERROR ; Error
+* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value
+*******************************************************************************/
+uint16_t usb0_function_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ usb0_function_set_curpipe(pipe, fifosel, isel, mbw);
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ switch (fifosel)
+ {
+ case USB_FUNCTION_CUSE:
+ buffer = USB200.CFIFOCTR;
+ break;
+
+ case USB_FUNCTION_D0USE:
+ case USB_FUNCTION_D0DMA:
+ buffer = USB200.D0FIFOCTR;
+ break;
+
+ case USB_FUNCTION_D1USE:
+ case USB_FUNCTION_D1DMA:
+ buffer = USB200.D1FIFOCTR;
+ break;
+
+ default:
+ buffer = 0;
+ break;
+ }
+
+ if ((buffer & USB_FUNCTION_BITFRDY) == USB_FUNCTION_BITFRDY)
+ {
+ return buffer;
+ }
+
+ loop2 = 25;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ return DEVDRV_USBF_FIFOERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_curpipe
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ g_usb0_function_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_FUNCTION_CUSE:
+ buffer = USB200.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_FUNCTION_BITISEL);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D0DMA:
+ case USB_FUNCTION_D0USE:
+ buffer = USB200.D0FIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D1DMA:
+ case USB_FUNCTION_D1USE:
+ buffer = USB200.D1FIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_curpipe2
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* : uint16_t dfacc ; DFACC Access mode
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc)
+{
+ uint16_t buffer;
+ uint32_t loop;
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ uint32_t dummy;
+#endif
+ volatile uint32_t loop2;
+
+ g_usb0_function_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_FUNCTION_CUSE:
+ buffer = USB200.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_FUNCTION_BITISEL);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D0DMA:
+ case USB_FUNCTION_D0USE:
+ buffer = USB200.D0FIFOSEL;
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_FUNCTION_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+#endif
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB200.D0FIFO.UINT32;
+ }
+#endif
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D1DMA:
+ case USB_FUNCTION_D1USE:
+ buffer = USB200.D1FIFOSEL;
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_FUNCTION_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+#endif
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB200.D1FIFO.UINT32;
+ loop = dummy; // avoid warning.
+ }
+#endif
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_c_fifo
+* Description : Writes data in CFIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_write_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.CFIFO.UINT8[HH] = *g_usb0_function_data_pointer[pipe];
+ g_usb0_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.CFIFO.UINT16[H] = *((uint16_t *)g_usb0_function_data_pointer[pipe]);
+ g_usb0_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.CFIFO.UINT32 = *((uint32_t *)g_usb0_function_data_pointer[pipe]);
+ g_usb0_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_c_fifo
+* Description : Reads data from CFIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_read_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_function_data_pointer[pipe] = USB200.CFIFO.UINT8[HH];
+ g_usb0_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_function_data_pointer[pipe]) = USB200.CFIFO.UINT16[H];
+ g_usb0_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_function_data_pointer[pipe]) = USB200.CFIFO.UINT32;
+ g_usb0_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_d0_fifo
+* Description : Writes data in D0FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_write_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.D0FIFO.UINT8[HH] = *g_usb0_function_data_pointer[pipe];
+ g_usb0_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.D0FIFO.UINT16[H] = *((uint16_t *)g_usb0_function_data_pointer[pipe]);
+ g_usb0_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.D0FIFO.UINT32 = *((uint32_t *)g_usb0_function_data_pointer[pipe]);
+ g_usb0_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_d0_fifo
+* Description : Reads data from D0FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating DOFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_read_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_function_data_pointer[pipe] = USB200.D0FIFO.UINT8[HH];
+ g_usb0_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_function_data_pointer[pipe]) = USB200.D0FIFO.UINT16[H];
+ g_usb0_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_function_data_pointer[pipe]) = USB200.D0FIFO.UINT32;
+ g_usb0_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_write_d1_fifo
+* Description : Writes data in D1FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_write_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.D1FIFO.UINT8[HH] = *g_usb0_function_data_pointer[pipe];
+ g_usb0_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.D1FIFO.UINT16[H] = *((uint16_t *)g_usb0_function_data_pointer[pipe]);
+ g_usb0_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.D1FIFO.UINT32 = *((uint32_t *)g_usb0_function_data_pointer[pipe]);
+ g_usb0_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_read_d1_fifo
+* Description : Reads data from D1FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_read_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_function_data_pointer[pipe] = USB200.D1FIFO.UINT8[HH];
+ g_usb0_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_function_data_pointer[pipe]) = USB200.D1FIFO.UINT16[H];
+ g_usb0_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_function_data_pointer[pipe]) = USB200.D1FIFO.UINT32;
+ g_usb0_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_com_get_dmasize
+* Description : Calculates access width of DMA transfer by the argument to
+* : return as the Return Value.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : DMA transfer size : 0 8bit
+* : : 1 16bit
+* : : 2 32bit
+*******************************************************************************/
+static uint32_t usb0_function_com_get_dmasize (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+
+ if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0))
+ {
+ /* When transfer byte count is odd */
+ /* or transfer data area is 8-bit alignment */
+ size = 0; /* 8bit */
+ }
+ else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0))
+ {
+ /* When the transfer byte count is multiples of 2 */
+ /* or the transfer data area is 16-bit alignment */
+ size = 1; /* 16bit */
+ }
+ else
+ {
+ /* When the transfer byte count is multiples of 4 */
+ /* or the transfer data area is 32-bit alignment */
+ size = 2; /* 32bit */
+ }
+
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_get_mbw
+* Description : Calculates access width of DMA to return the value set in MBW.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : FIFO transfer size : USB_FUNCTION_BITMBW_8 8bit
+* : : USB_FUNCTION_BITMBW_16 16bit
+* : : USB_FUNCTION_BITMBW_32 32bit
+*******************************************************************************/
+uint16_t usb0_function_get_mbw (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+ uint16_t mbw;
+
+ size = usb0_function_com_get_dmasize(trncount, dtptr);
+
+ if (size == 0)
+ {
+ /* 8bit */
+ mbw = USB_FUNCTION_BITMBW_8;
+ }
+ else if (size == 1)
+ {
+ /* 16bit */
+ mbw = USB_FUNCTION_BITMBW_16;
+ }
+ else
+ {
+ /* 32bit */
+ mbw = USB_FUNCTION_BITMBW_32;
+ }
+
+ return mbw;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_transaction_counter
+* Description : Sets transaction counter by the argument(PIPEnTRN).
+* : Clears transaction before setting to enable transaction counter setting.
+* Arguments : uint16_t pipe ; Pipe number
+* : uint32_t bsize : Data transfer size
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_set_transaction_counter (uint16_t pipe, uint32_t bsize)
+{
+ uint16_t mxps;
+ uint16_t cnt;
+
+ if (bsize == 0)
+ {
+ return;
+ }
+
+ mxps = usb0_function_get_mxps(pipe); /* Max Packet Size */
+
+ if ((bsize % mxps) == 0)
+ {
+ cnt = (uint16_t)(bsize / mxps);
+ }
+ else
+ {
+ cnt = (uint16_t)((bsize / mxps) + 1);
+ }
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE1TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE2TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE3TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE4TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE5TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE9TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEATRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPEATRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPEATRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPEBTRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPEBTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPECTRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPECTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPEDTRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPEDTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEETRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPEETRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPEETRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPEFTRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPEFTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_transaction_counter
+* Description : Clears the transaction counter by the argument.
+* : After executing this function, the transaction counter is invalid.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_clear_transaction_counter (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEATRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPEATRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPEBTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPECTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPEDTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEETRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPEETRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPEFTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_stop_transfer
+* Description : Stops the USB transfer in the pipe specified by the argument.
+* : After stopping the USB transfer, clears the buffer allocated in
+* : the pipe.
+* : After executing this function, allocation in FIF0 becomes USB_FUNCTION_PIPE0;
+* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt
+* : in the corresponding pipe becomes invalid. Sequence bit is also
+* : cleared.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_stop_transfer (uint16_t pipe)
+{
+ uint16_t usefifo;
+ uint32_t remain;
+ uint16_t fifo;
+
+ usb0_function_set_pid_nak(pipe);
+
+ usefifo = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ usb0_function_clear_transaction_counter(pipe);
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D0USE;
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ usb0_function_clear_transaction_counter(pipe);
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D1USE;
+ break;
+
+ case USB_FUNCTION_D0FIFO_DMA:
+ remain = Userdef_USB_usb0_function_stop_dma0();
+ usb0_function_dma_stop_d0(pipe, remain);
+ usb0_function_clear_transaction_counter(pipe);
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D0DMA;
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ remain = Userdef_USB_usb0_function_stop_dma1();
+ usb0_function_dma_stop_d1(pipe, remain);
+ usb0_function_clear_transaction_counter(pipe);
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D1DMA;
+ break;
+
+ default:
+ usb0_function_clear_transaction_counter(pipe);
+ USB200.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_CUSE;
+ break;
+ }
+
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, fifo, DEVDRV_USBF_NO, USB_FUNCTION_BITMBW_16);
+
+ /* Interrupt of pipe set is disabled */
+ usb0_function_disable_brdy_int(pipe);
+ usb0_function_disable_nrdy_int(pipe);
+ usb0_function_disable_bemp_int(pipe);
+
+ usb0_function_aclrm(pipe);
+ usb0_function_set_csclr(pipe);
+
+ if ( g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT )
+ {
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES;
+ }
+
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_dfacc_d0
+* Description : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb0_function_set_dfacc_d0 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+ return dfacc;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_dfacc_d1
+* Description : Set the DFACC setting value in D1FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb0_function_set_dfacc_d1 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+
+ return dfacc;
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dma.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dma.c
new file mode 100644
index 000000000..cfc8d0f49
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_dma.c
@@ -0,0 +1,346 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_dma.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static void usb0_function_dmaint(uint16_t fifo);
+static void usb0_function_dmaint_buf2fifo(uint16_t pipe);
+static void usb0_function_dmaint_fifo2buf(uint16_t pipe);
+
+
+/*******************************************************************************
+* Function Name: usb0_function_dma_stop_d0
+* Description : D0FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb0_function_dma_stop_d0 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB200.D0FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC);
+
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb0_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
+ {
+ buffer = USB200.D0FIFOCTR;
+ dtln = (buffer & USB_FUNCTION_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb0_function_PipeDataSize[pipe] = (g_usb0_function_data_count[pipe] - remain);
+ g_usb0_function_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_dma_stop_d1
+* Description : D1FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb0_function_dma_stop_d1 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB200.D1FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC);
+
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb0_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
+ {
+ buffer = USB200.D1FIFOCTR;
+ dtln = (buffer & USB_FUNCTION_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb0_function_PipeDataSize[pipe] = (g_usb0_function_data_count[pipe] - remain);
+ g_usb0_function_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_dma_interrupt_d0fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb0_function_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D0FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_function_dma_interrupt_d0fifo (uint32_t int_sense)
+{
+ usb0_function_dmaint(USB_FUNCTION_D0FIFO);
+ g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_dma_interrupt_d1fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb0_function_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D1FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_function_dma_interrupt_d1fifo (uint32_t int_sense)
+{
+ usb0_function_dmaint(USB_FUNCTION_D1FIFO);
+ g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_dmaint
+* Description : This function is DMA transfer end interrupt
+* Arguments : uint16_t fifo ; fifo number
+* : ; USB_FUNCTION_D0FIFO
+* : ; USB_FUNCTION_D1FIFO
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_dmaint (uint16_t fifo)
+{
+ uint16_t pipe;
+
+ pipe = g_usb0_function_DmaPipe[fifo];
+
+ if (g_usb0_function_DmaInfo[fifo].dir == USB_FUNCTION_BUF2FIFO)
+ {
+ usb0_function_dmaint_buf2fifo(pipe);
+ }
+ else
+ {
+ usb0_function_dmaint_fifo2buf(pipe);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_dmaint_fifo2buf
+* Description : Executes read completion from FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_dmaint_fifo2buf (uint16_t pipe)
+{
+ uint32_t remain;
+ uint16_t useport;
+
+ if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
+ {
+ useport = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ if (useport == USB_FUNCTION_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb0_function_stop_dma0();
+ usb0_function_dma_stop_d0(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] == USB_FUNCTION_DMA_BUSYEND)
+ {
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ else
+ {
+ usb0_function_enable_brdy_int(pipe);
+ }
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb0_function_stop_dma1();
+ usb0_function_dma_stop_d1(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] == USB_FUNCTION_DMA_BUSYEND)
+ {
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ else
+ {
+ usb0_function_enable_brdy_int(pipe);
+ }
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_dmaint_buf2fifo
+* Description : Executes write completion in FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_dmaint_buf2fifo (uint16_t pipe)
+{
+ uint32_t remain;
+ uint16_t useport;
+
+ useport = (uint16_t)(g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ if (useport == USB_FUNCTION_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb0_function_stop_dma0();
+ usb0_function_dma_stop_d0(pipe, remain);
+
+ if (g_usb0_function_DmaBval[USB_FUNCTION_D0FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb0_function_stop_dma1();
+ usb0_function_dma_stop_d1(pipe, remain);
+
+ if (g_usb0_function_DmaBval[USB_FUNCTION_D1FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+
+ usb0_function_enable_bemp_int(pipe);
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_intrn.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_intrn.c
new file mode 100644
index 000000000..827efaed7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_intrn.c
@@ -0,0 +1,249 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_intrn.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_function_brdy_int
+* Description : Executes BRDY interrupt(USB_FUNCTION_PIPE1-9).
+* : According to the pipe that interrupt is generated in,
+* : reads/writes buffer allocated in the pipe.
+* : This function is executed in the BRDY interrupt handler.
+* : This function clears BRDY interrupt status and BEMP interrupt
+* : status.
+* Arguments : uint16_t Status ; BRDYSTS Register Value
+* : uint16_t Int_enbl ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb0_function_brdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint32_t int_sense = 0;
+ uint16_t pipe;
+ uint16_t pipebit;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ pipebit = g_usb0_function_bit_set[pipe];
+
+ if ((status & pipebit) && (int_enb & pipebit))
+ {
+ USB200.BRDYSTS = (uint16_t)~pipebit;
+ USB200.BEMPSTS = (uint16_t)~pipebit;
+ if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA)
+ {
+ if (g_usb0_function_DmaStatus[USB_FUNCTION_D0FIFO] != USB_FUNCTION_DMA_READY)
+ {
+ usb0_function_dma_interrupt_d0fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb0_function_read_dma(pipe);
+ usb0_function_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB200.D0FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ }
+ else if ((g_usb0_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA)
+ {
+ if (g_usb0_function_DmaStatus[USB_FUNCTION_D1FIFO] != USB_FUNCTION_DMA_READY)
+ {
+ usb0_function_dma_interrupt_d1fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb0_function_read_dma(pipe);
+ usb0_function_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB200.D1FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+ {
+ usb0_function_read_buffer(pipe);
+ }
+ else
+ {
+ usb0_function_write_buffer(pipe);
+ }
+ }
+ }
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_nrdy_int
+* Description : Executes NRDY interrupt(USB_FUNCTION_PIPE1-9).
+* : Checks NRDY interrupt cause by PID. When the cause if STALL,
+* : regards the pipe state as STALL and ends the processing.
+* : Then the cause is not STALL, increments the error count to
+* : communicate again. When the error count is 3, determines
+* : the pipe state as DEVDRV_USBF_PIPE_NORES and ends the processing.
+* : This function is executed in the NRDY interrupt handler.
+* : This function clears NRDY interrupt status.
+* Arguments : uint16_t status ; NRDYSTS Register Value
+* : uint16_t int_enb ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_function_nrdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB200.NRDYSTS = (uint16_t)~status;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb0_function_bit_set[pipe]) == g_usb0_function_bit_set[pipe])
+ {
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0, USB_SYSCFG_DCFM_SHIFT, USB_SYSCFG_DCFM) == 1)
+ {
+ if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT)
+ {
+ pid = usb0_function_get_pid(pipe);
+ if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2))
+ {
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL;
+ }
+ else
+ {
+ g_usb0_function_PipeIgnore[pipe]++;
+ if (g_usb0_function_PipeIgnore[pipe] == 3)
+ {
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES;
+ }
+ else
+ {
+ usb0_function_set_pid_buf(pipe);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* USB Function */
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_bemp_int
+* Description : Executes BEMP interrupt(USB_FUNCTION_PIPE1-9).
+* Arguments : uint16_t status ; BEMPSTS Register Value
+* : uint16_t int_enb ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_function_bemp_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+ uint16_t inbuf;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB200.BEMPSTS = (uint16_t)~status;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb0_function_bit_set[pipe]) == g_usb0_function_bit_set[pipe])
+ {
+ pid = usb0_function_get_pid(pipe);
+
+ if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2))
+ {
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL;
+ }
+ else
+ {
+ inbuf = usb0_function_get_inbuf(pipe);
+
+ if (inbuf == 0)
+ {
+ usb0_function_disable_bemp_int(pipe);
+ usb0_function_set_pid_nak(pipe);
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ }
+ }
+ }
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_lib.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_lib.c
new file mode 100644
index 000000000..e3d318b98
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_function_lib.c
@@ -0,0 +1,2026 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_lib.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_function_enable_brdy_int
+* Description : Enables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_enable_brdy_int (uint16_t pipe)
+{
+ /* enable brdy interrupt */
+ USB200.BRDYENB |= (uint16_t)g_usb0_function_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_disable_brdy_int
+* Description : Disables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_disable_brdy_int (uint16_t pipe)
+{
+ /* disable brdy interrupt */
+ USB200.BRDYENB &= (uint16_t)~(g_usb0_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_brdy_sts
+* Description : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_clear_brdy_sts (uint16_t pipe)
+{
+ /* clear brdy status */
+ USB200.BRDYSTS = (uint16_t)~(g_usb0_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_enable_bemp_int
+* Description : Enables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_enable_bemp_int (uint16_t pipe)
+{
+ /* enable bemp interrupt */
+ USB200.BEMPENB |= (uint16_t)g_usb0_function_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_disable_bemp_int
+* Description : Disables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_disable_bemp_int (uint16_t pipe)
+{
+ /* disable bemp interrupt */
+ USB200.BEMPENB &= (uint16_t)~(g_usb0_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_bemp_sts
+* Description : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_clear_bemp_sts (uint16_t pipe)
+{
+ /* clear bemp status */
+ USB200.BEMPSTS = (uint16_t)~(g_usb0_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_enable_nrdy_int
+* Description : Enables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : NRDY. Enables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_enable_nrdy_int (uint16_t pipe)
+{
+ /* enable nrdy interrupt */
+ USB200.NRDYENB |= (uint16_t)g_usb0_function_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_disable_nrdy_int
+* Description : Disables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : NRDY. Disables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_disable_nrdy_int (uint16_t pipe)
+{
+ /* disable nrdy interrupt */
+ USB200.NRDYENB &= (uint16_t)~(g_usb0_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_nrdy_sts
+* Description : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_clear_nrdy_sts (uint16_t pipe)
+{
+ /* clear nrdy status */
+ USB200.NRDYSTS = (uint16_t)~(g_usb0_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_is_hispeed
+* Description : Returns the result of USB reset hand shake (RHST) as
+* : return value.
+* Arguments : none
+* Return Value : USB_FUNCTION_HIGH_SPEED ; Hi-Speed
+* : USB_FUNCTION_FULL_SPEED ; Full-Speed
+* : LOW_SPEED ; Low-Speed
+* : USB_FUNCTION_NON_SPEED ; error
+*******************************************************************************/
+uint16_t usb0_function_is_hispeed (void)
+{
+ uint16_t rhst;
+ uint16_t speed;
+
+ rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0, USB_DVSTCTR0_RHST_SHIFT, USB_DVSTCTR0_RHST);
+
+ if (rhst == USB_FUNCTION_HSMODE)
+ {
+ speed = USB_FUNCTION_HIGH_SPEED;
+ }
+ else if (rhst == USB_FUNCTION_FSMODE)
+ {
+ speed = USB_FUNCTION_FULL_SPEED;
+ }
+ else if (rhst == USB_FUNCTION_LSMODE)
+ {
+ speed = USB_FUNCTION_LOW_SPEED;
+ }
+ else
+ {
+ speed = USB_FUNCTION_NON_SPEED;
+ }
+
+ return speed;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_is_hispeed_enable
+* Description : Returns the USB High-Speed connection enabled status as
+* : return value.
+* Arguments : none
+* Return Value : DEVDRV_USBF_YES : Hi-Speed Enable
+* : DEVDRV_USBF_NO : Hi-Speed Disable
+*******************************************************************************/
+uint16_t usb0_function_is_hispeed_enable (void)
+{
+ uint16_t ret;
+
+ ret = DEVDRV_USBF_NO;
+
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0, USB_SYSCFG_HSE_SHIFT, USB_SYSCFG_HSE) == 1)
+ {
+ ret = DEVDRV_USBF_YES;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_pid_buf
+* Description : Enables communicaqtion in the pipe specified by the argument
+* : (BUF).
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_pid_buf (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb0_function_get_pid(pipe);
+
+ if (pid == DEVDRV_USBF_PID_STALL2)
+ {
+ usb0_function_set_pid_nak(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_pid_nak
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* : When the pipe status was enabling communication (BUF) before
+* : executing before executing this function, waits in the software
+* : until the pipe becomes ready after setting disabled.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_pid_nak (uint16_t pipe)
+{
+ uint16_t pid;
+ uint16_t pbusy;
+ uint32_t loop;
+
+ pid = usb0_function_get_pid(pipe);
+
+ if (pid == DEVDRV_USBF_PID_STALL2)
+ {
+ usb0_function_set_pid_stall(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+
+ if (pid == DEVDRV_USBF_PID_BUF)
+ {
+ for (loop = 0; loop < 200; loop++)
+ {
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ pbusy = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_PBUSY_SHIFT,
+ USB_DCPCTR_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_PBUSY_SHIFT,
+ USB_PIPEnCTR_9_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPEACTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPEBCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPECCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPEDCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPEECTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPEFCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ default:
+ pbusy = 1;
+ break;
+ }
+
+ if (pbusy == 0)
+ {
+ break;
+ }
+ Userdef_USB_usb0_function_delay_500ns();
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_pid_stall
+* Description : Disables communication (STALL) in the pipe specified by the
+* : argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_pid_stall (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb0_function_get_pid(pipe);
+ if (pid == DEVDRV_USBF_PID_BUF)
+ {
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_pid_stall
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_clear_pid_stall (uint16_t pipe)
+{
+ usb0_function_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_get_pid
+* Description : Returns the pipe state specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb0_function_get_pid (uint16_t pipe)
+{
+ uint16_t pid;
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ pid = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ pid = RZA_IO_RegRead_16(&USB200.PIPEACTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ pid = RZA_IO_RegRead_16(&USB200.PIPEBCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ pid = RZA_IO_RegRead_16(&USB200.PIPECCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ pid = RZA_IO_RegRead_16(&USB200.PIPEDCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ pid = RZA_IO_RegRead_16(&USB200.PIPEECTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ pid = RZA_IO_RegRead_16(&USB200.PIPEFCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ pid = 0;
+ break;
+ }
+
+ return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_csclr
+* Description : CSPLIT status clear setting of sprit transaction in specified
+* : pipe is performed.
+* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+* : in DCPCTR register are continuously changed (when the sequence
+* : toggle bit of data PID is continuously changed over two or more pipes),
+* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+* : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+* : In addition, both bits should be operated after PID is set to NAK.
+* : However, when it is set to the isochronous transfer as the transfer type
+* : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_csclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_CSCLR_SHIFT,
+ USB_DCPCTR_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_CSCLR_SHIFT,
+ USB_PIPEnCTR_9_CSCLR);
+ break;
+
+ default:
+ /* PIPEA-F have not CSCLR */
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_sqclr
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA0.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_sqclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_SQCLR_SHIFT,
+ USB_DCPCTR_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQCLR_SHIFT,
+ USB_PIPEnCTR_9_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_sqset
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA1.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_sqset (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_SQSET_SHIFT,
+ USB_DCPCTR_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQSET_SHIFT,
+ USB_PIPEnCTR_9_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_get_sqmon
+* Description : Toggle bit of specified pipe is obtained
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : sqmon
+*******************************************************************************/
+uint16_t usb0_function_get_sqmon (uint16_t pipe)
+{
+ uint16_t sqmon;
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ sqmon = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_SQMON_SHIFT,
+ USB_DCPCTR_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_SQMON_SHIFT,
+ USB_PIPEnCTR_9_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPEACTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPEBCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPECCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPEDCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPEECTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPEFCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ default:
+ sqmon = 0;
+ break;
+ }
+
+ return sqmon;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_aclrm
+* Description : The buffer of specified pipe is initialized
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_function_aclrm (uint16_t pipe)
+{
+ usb0_function_set_aclrm(pipe);
+ usb0_function_clr_aclrm(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_set_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_function_set_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_clr_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_function_clr_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 0,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB200.PIPEACTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB200.PIPEBCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB200.PIPECCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB200.PIPEDCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB200.PIPEECTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB200.PIPEFCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_get_inbuf
+* Description : Returns INBUFM of the pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : inbuf
+*******************************************************************************/
+uint16_t usb0_function_get_inbuf (uint16_t pipe)
+{
+ uint16_t inbuf;
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_INBUFM_SHIFT,
+ USB_PIPEnCTR_9_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPEACTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPEBCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPECCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPEDCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPEECTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPEFCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ default:
+ inbuf = 0;
+ break;
+ }
+
+ return inbuf;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_setting_interrupt
+* Description : Sets the USB module interrupt level.
+* Arguments : uint8_t level ;interrupt level
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb0_function_setting_interrupt (uint8_t level)
+{
+ uint16_t d0fifo_dmaintid;
+ uint16_t d1fifo_dmaintid;
+
+ R_INTC_RegistIntFunc(INTC_ID_USBI0, usb0_function_interrupt);
+ R_INTC_SetPriority(INTC_ID_USBI0, level);
+ R_INTC_Enable(INTC_ID_USBI0);
+
+ d0fifo_dmaintid = Userdef_USB_usb0_function_d0fifo_dmaintid();
+
+ if (d0fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d0fifo_dmaintid, usb0_function_dma_interrupt_d0fifo);
+ R_INTC_SetPriority(d0fifo_dmaintid, level);
+ R_INTC_Enable(d0fifo_dmaintid);
+ }
+
+ d1fifo_dmaintid = Userdef_USB_usb0_function_d1fifo_dmaintid();
+
+ if (d1fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d1fifo_dmaintid, usb0_function_dma_interrupt_d1fifo);
+ R_INTC_SetPriority(d1fifo_dmaintid, level);
+ R_INTC_Enable(d1fifo_dmaintid);
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_reset_module
+* Description : Initializes the USB module.
+* : Enables providing clock to the USB module.
+* : Sets USB bus wait register.
+* Arguments : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ
+* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+void usb0_function_reset_module (uint16_t clockmode)
+{
+ /* UPLLE bit is only USB0 */
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_UPLLE_SHIFT,
+ USB_SYSCFG_UPLLE) == 1)
+ {
+ if ((USB200.SYSCFG0 & USB_FUNCTION_BITUCKSEL) != clockmode)
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_FUNCTION_BITUPLLE | clockmode);
+ Userdef_USB_usb0_function_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ Userdef_USB_usb0_function_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_FUNCTION_BITUPLLE | clockmode);
+ Userdef_USB_usb0_function_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+
+ USB200.BUSWAIT = (uint16_t)(USB_FUNCTION_BUSWAIT_05 & USB_FUNCTION_BITBWAIT);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_get_buf_size
+* Description : Obtains pipe buffer size specified by the argument and
+* : maximum packet size of the USB device in use.
+* : When USB_FUNCTION_PIPE0 is specified by the argument, obtains the maximum
+* : packet size of the USB device using the corresponding pipe.
+* : For the case that USB_FUNCTION_PIPE0 is not assigned by the argument, when the
+* : corresponding pipe is in continuous transfer mode,
+* : obtains the buffer size allocated in the corresponcing pipe,
+* : when incontinuous transfer, obtains maximum packet size.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : Maximum packet size or buffer size
+*******************************************************************************/
+uint16_t usb0_function_get_buf_size (uint16_t pipe)
+{
+ uint16_t size;
+ uint16_t bufsize;
+
+ if (pipe == USB_FUNCTION_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_function_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1)
+ {
+ bufsize = RZA_IO_RegRead_16(&g_usb0_function_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE);
+ size = (uint16_t)((bufsize + 1) * USB_FUNCTION_PIPExBUF);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb0_function_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+ }
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_get_mxps
+* Description : Obtains maximum packet size of the USB device using the pipe
+* : specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : Max Packet Size
+*******************************************************************************/
+uint16_t usb0_function_get_mxps (uint16_t pipe)
+{
+ uint16_t size;
+
+ if (pipe == USB_FUNCTION_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb0_function_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+ return size;
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_api.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_api.c
new file mode 100644
index 000000000..369b2bea6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_api.c
@@ -0,0 +1,441 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_api.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_api_function_init
+* Description : Initializes the USB module in the USB function mode.
+* Arguments : uint8_t int_level ; interruput level
+* : uint16_t mode : Speed modes
+* : : USB_FUCNTION_HIGH_SPEED: High-speed device
+* : : USB_FUCNTION_FULL_SPEED: Full-speed device
+* : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ
+* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb0_api_function_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
+{
+ volatile uint8_t dummy_buf;
+
+ CPG.STBCR7 &= 0xfd; /* The clock of USB0 modules is permitted */
+ dummy_buf = CPG.STBCR7; /* (Dummy read) */
+
+ usb0_function_setting_interrupt(int_level);
+
+ usb0_function_reset_module(clockmode); /* reset USB module with setting tranciever */
+ /* and HSE=1 */
+
+ usb0_function_init_status(); /* clear variables */
+
+ usb0_function_InitModule(mode); /* select USB Function and Interrupt Enable */
+ /* Detect USB Device to attach or detach */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_api_function_IsConfigured
+* Description : Checks if the USB device is configured to return the result as
+* : the return value.
+* Arguments : none
+* Return Value : DEVDRV_USBF_YES : Configured & Configured Suspend
+* : DEVDRV_USBF_NO : not Configured
+*******************************************************************************/
+uint16_t usb0_api_function_IsConfigured (void)
+{
+ uint16_t dvst;
+
+ dvst = usb0_function_GetDeviceState();
+
+ if ((dvst == USB_FUNCTION_DVST_CONFIGURED) ||
+ (dvst == USB_FUNCTION_DVST_CONFIGURED_SUSPEND))
+ {
+ return DEVDRV_USBF_YES;
+ }
+
+ return DEVDRV_USBF_NO;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_GetDeviceState
+* Description : Returns the state of USB device.
+* Arguments : none
+* Return Value : Device States
+*******************************************************************************/
+uint16_t usb0_function_GetDeviceState (void)
+{
+ uint16_t dvsq;
+ uint16_t dvst;
+
+ dvsq = USB200.INTSTS0;
+ switch(dvsq & USB_FUNCTION_BITDVSQ)
+ {
+ case USB_FUNCTION_DS_POWR: /* Power state *//* power-on */
+ dvst = USB_FUNCTION_DVST_POWERED;
+ break;
+
+ case USB_FUNCTION_DS_DFLT: /* Default state *//* bus-reset */
+ dvst = USB_FUNCTION_DVST_DEFAULT;
+ break;
+
+ case USB_FUNCTION_DS_ADDS: /* Address state */
+ dvst = USB_FUNCTION_DVST_ADDRESS;
+ break;
+
+ case USB_FUNCTION_DS_CNFG: /* Configured state */
+ dvst = USB_FUNCTION_DVST_CONFIGURED;
+ break;
+
+ case USB_FUNCTION_DS_SPD_CNFG: /* Configured Suspend state */
+ dvst = USB_FUNCTION_DVST_CONFIGURED_SUSPEND;
+ break;
+
+ case USB_FUNCTION_DS_SPD_POWR: /* Power Suspend state */
+ case USB_FUNCTION_DS_SPD_DFLT: /* Default Suspend state */
+ case USB_FUNCTION_DS_SPD_ADDR: /* Address Suspend state */
+ dvst = USB_FUNCTION_DVST_SUSPEND;
+ break;
+
+ default: /* error */
+ dvst = USB_FUNCTION_DVST_SUSPEND;
+ break;
+ }
+
+ return dvst;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_start_receive_transfer
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data data Address
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ usb0_function_start_receive_transfer(pipe, size, data);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_start_send_transfer
+* Description : Starts the USB data communication using pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data data Address
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_api_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+
+ status = usb0_function_start_send_transfer(pipe, size, data);
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_check_pipe_status
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t *size ; Data Size
+* Return Value : Pipe Status
+*******************************************************************************/
+uint16_t usb0_api_function_check_pipe_status (uint16_t pipe, uint32_t * size)
+{
+ if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_DONE)
+ {
+ *size = g_usb0_function_PipeDataSize[pipe];
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_PIPE_DONE;
+ }
+ else if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_NORES)
+ {
+ *size = 0;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_PIPE_NORES;
+ }
+ else if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_STALL)
+ {
+ *size = 0;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_PIPE_STALL;
+ }
+ else if (g_usb0_function_pipe_status[pipe] == DEVDRV_USBF_FIFOERROR)
+ {
+ *size = 0;
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_FIFOERROR;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ return g_usb0_function_pipe_status[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_clear_pipe_status
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : Pipe Status
+*******************************************************************************/
+void usb0_api_function_clear_pipe_status (uint16_t pipe)
+{
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+ g_usb0_function_PipeDataSize[pipe] = 0;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_set_pid_buf
+* Description : Enables communicaqtion in the pipe specified by the argument
+* : (BUF).
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_set_pid_buf (uint16_t pipe)
+{
+ usb0_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_set_pid_nak
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* : When the pipe status was enabling communication (BUF) before
+* : executing before executing this function, waits in the software
+* : until the pipe becomes ready after setting disabled.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_set_pid_nak (uint16_t pipe)
+{
+ usb0_function_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_set_pid_stall
+* Description : Disables communication (STALL) in the pipe specified by the
+* : argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_set_pid_stall (uint16_t pipe)
+{
+ usb0_function_set_pid_stall(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_clear_pid_stall
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_clear_pid_stall (uint16_t pipe)
+{
+ usb0_function_clear_pid_stall(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_get_pid
+* Description : Returns the pipe state specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb0_api_function_get_pid (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb0_function_get_pid(pipe);
+
+ return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_check_stall
+* Description :
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+int32_t usb0_api_function_check_stall (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb0_function_get_pid(pipe);
+
+ if ((pid & DEVDRV_USBF_PID_STALL) == DEVDRV_USBF_PID_STALL)
+ {
+ return DEVDRV_USBF_STALL;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_set_sqclr
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA0.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_set_sqclr (uint16_t pipe)
+{
+ usb0_function_set_sqclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_set_sqset
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA1.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_set_sqset (uint16_t pipe)
+{
+ usb0_function_set_sqset(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_set_csclr
+* Description : CSPLIT status clear setting of sprit transaction in specified
+* : pipe is performed.
+* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+* : in DCPCTR register are continuously changed (when the sequence
+* : toggle bit of data PID is continuously changed over two or more pipes),
+* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+* : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+* : In addition, both bits should be operated after PID is set to NAK.
+* : However, when it is set to the isochronous transfer as the transfer type
+* : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_set_csclr (uint16_t pipe)
+{
+ usb0_function_set_csclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_set_curpipe
+* Description : Allocates FIF0 specifed by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ usb0_function_set_curpipe(pipe, fifosel, isel, mbw);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_clear_brdy_sts
+* Description : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_clear_brdy_sts (uint16_t pipe)
+{
+ usb0_function_clear_brdy_sts(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_clear_bemp_sts
+* Description : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_clear_bemp_sts (uint16_t pipe)
+{
+ usb0_function_clear_bemp_sts(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_clear_nrdy_sts
+* Description : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_clear_nrdy_sts (uint16_t pipe)
+{
+ usb0_function_clear_nrdy_sts(pipe);
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_controlrw.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_controlrw.c
new file mode 100644
index 000000000..0a9121ab8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_controlrw.c
@@ -0,0 +1,142 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_controlrw.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_api_function_CtrlReadStart
+* Description : Executes the USB control read transfer.
+* : USB host controller <- USB device
+* Arguments : uint16_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : DEVDRV_USBF_WRITEEND ; End of data write
+* : DEVDRV_USBF_WRITESHRT ; End of short data write
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_FIFOERROR ; FIFO access error
+*******************************************************************************/
+uint16_t usb0_api_function_CtrlReadStart (uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+ uint16_t mbw;
+
+ usb0_function_set_pid_nak(USB_FUNCTION_PIPE0);
+
+ g_usb0_function_data_count[USB_FUNCTION_PIPE0] = size;
+ g_usb0_function_data_pointer[USB_FUNCTION_PIPE0] = data;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[USB_FUNCTION_PIPE0],
+ (uint32_t)g_usb0_function_data_pointer[USB_FUNCTION_PIPE0]);
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw);
+ USB200.CFIFOCTR = USB_FUNCTION_BITBCLR;
+
+ status = usb0_function_write_buffer_c(USB_FUNCTION_PIPE0);
+
+ /* Peripheral Control sequence */
+ switch (status)
+ {
+ case DEVDRV_USBF_WRITESHRT: /* End of data write */
+ case DEVDRV_USBF_WRITEEND: /* End of data write (not null) */
+ case DEVDRV_USBF_WRITING: /* Continue of data write */
+ usb0_function_enable_bemp_int(USB_FUNCTION_PIPE0); /* Enable Empty Interrupt */
+ usb0_function_set_pid_buf(USB_FUNCTION_PIPE0); /* Set BUF */
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access error */
+ break;
+
+ default:
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_function_CtrlWriteStart
+* Description : Executes the USB control write transfer.
+* : USB host controller -> USB device
+* Arguments : uint16_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb0_api_function_CtrlWriteStart (uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_function_set_pid_nak(USB_FUNCTION_PIPE0);
+
+ g_usb0_function_data_count[USB_FUNCTION_PIPE0] = size;
+ g_usb0_function_data_pointer[USB_FUNCTION_PIPE0] = data;
+
+ mbw = usb0_function_get_mbw(g_usb0_function_data_count[USB_FUNCTION_PIPE0],
+ (uint32_t)g_usb0_function_data_pointer[USB_FUNCTION_PIPE0]);
+ usb0_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw);
+ USB200.CFIFOCTR = USB_FUNCTION_BITBCLR;
+
+ usb0_function_enable_brdy_int(USB_FUNCTION_PIPE0);
+ usb0_function_set_pid_buf(USB_FUNCTION_PIPE0);
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_global.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_global.c
new file mode 100644
index 000000000..5f1ff018f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_global.c
@@ -0,0 +1,144 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_global.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+const uint16_t g_usb0_function_bit_set[16] =
+{
+ 0x0001, 0x0002, 0x0004, 0x0008,
+ 0x0010, 0x0020, 0x0040, 0x0080,
+ 0x0100, 0x0200, 0x0400, 0x0800,
+ 0x1000, 0x2000, 0x4000, 0x8000
+};
+
+uint32_t g_usb0_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint8_t * g_usb0_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+uint16_t g_usb0_function_PipeIgnore[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb0_function_PipeTbl[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb0_function_pipe_status[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint32_t g_usb0_function_PipeDataSize[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+USB_FUNCTION_DMA_t g_usb0_function_DmaInfo[2];
+uint16_t g_usb0_function_DmaPipe[2];
+uint16_t g_usb0_function_DmaBval[2];
+uint16_t g_usb0_function_DmaStatus[2];
+
+uint16_t g_usb0_function_CtrZeroLengthFlag;
+
+//uint16_t g_usb0_function_ConfigNum;
+//uint16_t g_usb0_function_Alternate[USB_FUNCTION_ALT_NO];
+//uint16_t g_usb0_function_RemoteWakeupFlag;
+uint16_t g_usb0_function_TestModeFlag;
+uint16_t g_usb0_function_TestModeSelectors;
+
+//uint16_t g_usb0_function_ReqType;
+//uint16_t g_usb0_function_ReqTypeType;
+//uint16_t g_usb0_function_ReqTypeRecip;
+//uint16_t g_usb0_function_ReqRequest;
+//uint16_t g_usb0_function_ReqValue;
+//uint16_t g_usb0_function_ReqIndex;
+//uint16_t g_usb0_function_ReqLength;
+
+//uint16_t g_usb0_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1];
+
+uint16_t g_usb0_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb0_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb0_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb0_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+* Function Name: usb0_function_init_status
+* Description : Initialization USB Sample Driver Variable.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_function_init_status (void)
+{
+ uint16_t pipe;
+
+ //g_usb0_function_ConfigNum = 0;
+ //g_usb0_function_RemoteWakeupFlag = DEVDRV_USBF_OFF;
+ g_usb0_function_TestModeFlag = DEVDRV_USBF_OFF;
+ g_usb0_function_CtrZeroLengthFlag = 0;
+
+#if 0
+ usb0_function_clear_alt();
+#endif
+
+ for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
+ {
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+ g_usb0_function_PipeDataSize[pipe] = 0;
+ g_usb0_function_data_count[pipe] = 0;
+
+ /* pipe configuration in usb0_function_ResetEP() */
+ g_usb0_function_pipecfg[pipe] = 0;
+ g_usb0_function_pipebuf[pipe] = 0;
+ g_usb0_function_pipemaxp[pipe] = 0;
+ g_usb0_function_pipeperi[pipe] = 0;
+ }
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sig.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sig.c
new file mode 100644
index 000000000..66949dee6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sig.c
@@ -0,0 +1,330 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_sig.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_function_EnableINTModule(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_function_InitModule
+* Description : Initializes the USB module in the USB function mode.
+* Arguments : uint16_t mode ; USB_FUNCTION_HIGH_SPEED ; Hi-Speed Mode
+* : ; other ; Full-speed Mode
+* Return Value : none
+*******************************************************************************/
+void usb0_function_InitModule (uint16_t mode)
+{
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM); /* USB function */
+
+ /* USB module operation enabled */
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE);
+
+ if (mode == USB_FUNCTION_HIGH_SPEED)
+ {
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE); /* Hi-Speed Mode */
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ }
+
+ /* for power-on */
+ if (usb0_function_CheckVBUStaus() == DEVDRV_USBF_ON)
+ {
+ usb0_function_EnableINTModule(); /* Interrupt Enable */
+ usb0_function_USB_FUNCTION_Attach(); /* pull-up D+ and open D- */
+ }
+ else
+ {
+ usb0_function_USB_FUNCTION_Detach(); /* USB Detach */
+ /* with Interrupt Enable */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_CheckVBUStaus
+* Description : Checks the USB-VBUS state to returns the connection state to
+* : the USB host.
+* Arguments : none
+* Return Value : DEVDRV_USBF_ON : VBUS ON
+* : DEVDRV_USBF_OFF : VBUS OFF
+*******************************************************************************/
+uint16_t usb0_function_CheckVBUStaus (void)
+{
+ uint16_t buf1;
+ uint16_t buf2;
+ uint16_t buf3;
+
+ /* monitor VBUS pins */
+ do
+ {
+ buf1 = RZA_IO_RegRead_16(&USB200.INTSTS0,
+ USB_INTSTS0_VBSTS_SHIFT,
+ USB_INTSTS0_VBSTS);
+ Userdef_USB_usb0_function_delay_10us(1);
+ buf2 = RZA_IO_RegRead_16(&USB200.INTSTS0,
+ USB_INTSTS0_VBSTS_SHIFT,
+ USB_INTSTS0_VBSTS);
+ Userdef_USB_usb0_function_delay_10us(1);
+ buf3 = RZA_IO_RegRead_16(&USB200.INTSTS0,
+ USB_INTSTS0_VBSTS_SHIFT,
+ USB_INTSTS0_VBSTS);
+ } while ((buf1 != buf2) || (buf2 != buf3));
+
+ if (buf1 == DEVDRV_USBF_OFF)
+ {
+ return DEVDRV_USBF_OFF; /* detach */
+ }
+
+ return DEVDRV_USBF_ON; /* attach */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_USB_FUNCTION_Attach
+* Description : Connects to the USB host controller.
+* : This function pulls up D+.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_function_USB_FUNCTION_Attach (void)
+{
+ Userdef_USB_usb0_function_attach();
+
+ Userdef_USB_usb0_function_delay_xms(10);
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_DPRPU_SHIFT,
+ USB_SYSCFG_DPRPU); /* Pull-up D+ and open D- */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_USB_FUNCTION_Detach
+* Description : Disconnects from the USB host controller.
+* : This function opens D+/D-.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_function_USB_FUNCTION_Detach (void)
+{
+ uint16_t pipe;
+
+ Userdef_USB_usb0_function_detach();
+
+ for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
+ {
+ if (g_usb0_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_IDLE)
+ {
+ usb0_function_stop_transfer(pipe);
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_DPRPU_SHIFT,
+ USB_SYSCFG_DPRPU); /* open D+ and D- */
+
+ /* Detach Recovery */
+ Userdef_USB_usb0_function_delay_500ns(); /* need 1us=500ns * 2 wait */
+ Userdef_USB_usb0_function_delay_500ns();
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM);
+ Userdef_USB_usb0_function_delay_500ns(); /* need 100ns wait but 500ns S/W wait */
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM);
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE); /* soft reset module */
+ Userdef_USB_usb0_function_delay_500ns();
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE);
+
+ usb0_function_EnableINTModule(); /* Interrupt Enable */
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_USB_FUNCTION_BusReset
+* Description : This function is executed when the USB device is transitioned
+* : to POWERD_STATE. Sets the device descriptor according to the
+* : connection speed determined by the USB reset hand shake.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0 /*The USBHAL in mbed does not need this function*/
+void usb0_function_USB_FUNCTION_BusReset (void)
+{
+ usb0_function_init_status(); /* memory clear */
+
+ if (usb0_function_is_hispeed() == USB_FUNCTION_HIGH_SPEED)
+ {
+ usb0_function_ResetDescriptor(USB_FUNCTION_HIGH_SPEED); /* Device Descriptor reset */
+ }
+ else
+ {
+ usb0_function_ResetDescriptor(USB_FUNCTION_FULL_SPEED); /* Device Descriptor reset */
+ }
+
+ usb0_function_ResetDCP(); /* Default Control PIPE reset */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_USB_FUNCTION_Resume
+* Description : This function is executed when the USB device detects a resume
+* : signal.
+* : The USB sample driver does not operate for this function.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0 /*The USBHAL in mbed does not need this function*/
+void usb0_function_USB_FUNCTION_Resume (void)
+{
+ /* NOP */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_USB_FUNCTION_Suspend
+* Description : This function is executed when the USB device detects a suspend
+* : signal.
+* : The USB sample driver does not operate for this function.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0 /*The USBHAL in mbed does not need this function*/
+void usb0_function_USB_FUNCTION_Suspend (void)
+{
+ /* NOP */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_USB_FUNCTION_TestMode
+* Description : This function is executed when the USB device is transitioned U
+* : to TEST_MODE by the USB standard request.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_function_USB_FUNCTION_TestMode (void)
+{
+ switch (g_usb0_function_TestModeSelectors & USB_FUNCTION_FUNCTION_TEST_SELECT)
+ {
+ case USB_FUNCTION_FUNCTION_TEST_J:
+ case USB_FUNCTION_FUNCTION_TEST_K:
+ case USB_FUNCTION_FUNCTION_TEST_SE0_NAK:
+ case USB_FUNCTION_FUNCTION_TEST_PACKET:
+ RZA_IO_RegWrite_16(&USB200.TESTMODE,
+ (g_usb0_function_TestModeSelectors >> 8),
+ USB_TESTMODE_UTST_SHIFT,
+ USB_TESTMODE_UTST);
+ break;
+
+ case USB_FUNCTION_FUNCTION_TEST_FORCE_ENABLE:
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_EnableINTModule
+* Description : Enables USB interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_EnableINTModule (void)
+{
+ uint16_t buf;
+
+ buf = USB200.INTENB0;
+ buf |= (USB_FUNCTION_BITVBSE | USB_FUNCTION_BITDVSE | USB_FUNCTION_BITCTRE |
+ USB_FUNCTION_BITBEMPE | USB_FUNCTION_BITNRDYE | USB_FUNCTION_BITBRDYE);
+ USB200.INTENB0 = buf;
+
+ usb0_function_enable_bemp_int(USB_FUNCTION_PIPE0);
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sub.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sub.c
new file mode 100644
index 000000000..df7fbf5bb
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/function/usb0_function_sub.c
@@ -0,0 +1,453 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_sub.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+#if 0
+extern const uint16_t *g_usb0_function_EndPntPtr[];
+extern uint8_t g_usb0_function_DeviceDescriptor[];
+extern uint8_t *g_usb0_function_ConfigurationPtr[];
+#endif
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_function_ResetDCP
+* Description : Initializes the default control pipe(DCP).
+* Outline : Reset default control pipe
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_function_ResetDCP (void)
+{
+ USB200.DCPCFG = 0;
+#if 0
+ USB200.DCPMAXP = g_usb0_function_DeviceDescriptor[7];
+#else
+ USB200.DCPMAXP = 64;
+#endif
+
+ USB200.CFIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+ USB200.D0FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+ USB200.D1FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_ResetEP
+* Description : Initializes the end point.
+* Arguments : uint16_t num ; Configuration Number
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb0_function_ResetEP (uint16_t num)
+{
+ uint16_t pipe;
+ uint16_t ep;
+ uint16_t index;
+ uint16_t buf;
+ uint16_t * tbl;
+
+ tbl = (uint16_t *)(g_usb0_function_EndPntPtr[num - 1]);
+
+ for (ep = 1; ep <= USB_FUNCTION_MAX_EP_NO; ++ep)
+ {
+ if (g_usb0_function_EPTableIndex[ep] != USB_FUNCTION_EP_ERROR)
+ {
+ index = (uint16_t)(USB_FUNCTION_EPTABLE_LENGTH * g_usb0_function_EPTableIndex[ep]);
+ pipe = (uint16_t)(tbl[index + 0] & USB_FUNCTION_BITCURPIPE);
+
+ g_usb0_function_PipeTbl[pipe] = (uint16_t)( ((tbl[index + 1] & USB_FUNCTION_DIRFIELD) << 3) |
+ ep |
+ (tbl[index + 0] & USB_FUNCTION_FIFO_USE) );
+
+ if ((tbl[index + 1] & USB_FUNCTION_DIRFIELD) == USB_FUNCTION_DIR_P_OUT)
+ {
+ tbl[index + 1] |= USB_FUNCTION_SHTNAKON;
+#ifdef __USB_DMA_BFRE_ENABLE__
+ /* this routine cannnot be perfomred if read operation is executed in buffer size */
+ if (((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA) ||
+ ((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA))
+ {
+ tbl[index + 1] |= USB_FUNCTION_BFREON;
+ }
+#endif
+ }
+
+ /* Interrupt Disable */
+ buf = USB200.BRDYENB;
+ buf &= (uint16_t)~g_usb0_function_bit_set[pipe];
+ USB200.BRDYENB = buf;
+ buf = USB200.NRDYENB;
+ buf &= (uint16_t)~g_usb0_function_bit_set[pipe];
+ USB200.NRDYENB = buf;
+ buf = USB200.BEMPENB;
+ buf &= (uint16_t)~g_usb0_function_bit_set[pipe];
+ USB200.BEMPENB = buf;
+
+ usb0_function_set_pid_nak(pipe);
+
+ /* CurrentPIPE Clear */
+ if (RZA_IO_RegRead_16(&USB200.CFIFOSEL,
+ USB_CFIFOSEL_CURPIPE_SHIFT,
+ USB_CFIFOSEL_CURPIPE) == pipe)
+ {
+ RZA_IO_RegWrite_16(&USB200.CFIFOSEL,
+ 0,
+ USB_CFIFOSEL_CURPIPE_SHIFT,
+ USB_CFIFOSEL_CURPIPE);
+ }
+
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE);
+ }
+
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE);
+ }
+
+ /* PIPE Configuration */
+ USB200.PIPESEL = pipe;
+ USB200.PIPECFG = tbl[index + 1];
+ USB200.PIPEBUF = tbl[index + 2];
+ USB200.PIPEMAXP = tbl[index + 3];
+ USB200.PIPEPERI = tbl[index + 4];
+
+ g_usb0_function_pipecfg[pipe] = tbl[index + 1];
+ g_usb0_function_pipebuf[pipe] = tbl[index + 2];
+ g_usb0_function_pipemaxp[pipe] = tbl[index + 3];
+ g_usb0_function_pipeperi[pipe] = tbl[index + 4];
+
+ /* Buffer Clear */
+ usb0_function_set_sqclr(pipe);
+ usb0_function_aclrm(pipe);
+
+ /* init Global */
+ g_usb0_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+ g_usb0_function_PipeDataSize[pipe] = 0;
+ }
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_EpToPipe
+* Description : Returns the pipe which end point specified by the argument is
+* : allocated to.
+* Arguments : uint16_t ep ; Direction + Endpoint Number
+* Return Value : USB_FUNCTION_EP_ERROR : Error
+* : Others : Pipe Number
+*******************************************************************************/
+uint16_t usb0_function_EpToPipe (uint16_t ep)
+{
+ uint16_t pipe;
+
+ for (pipe = 1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ if ((g_usb0_function_PipeTbl[pipe] & 0x00ff) == ep)
+ {
+ return pipe;
+ }
+ }
+
+ return USB_FUNCTION_EP_ERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_InitEPTable
+* Description : Sets the end point by the Alternate setting value of the
+* : configuration number and the interface number specified by the
+* : argument.
+* Arguments : uint16_t Con_Num ; Configuration Number
+* : uint16_t Int_Num ; Interface Number
+* : uint16_t Alt_Num ; Alternate Setting
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb0_function_InitEPTable (uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num)
+{
+ uint8_t * ptr;
+ uint16_t point_interface;
+ uint16_t point_endpoint;
+ uint16_t length;
+ uint16_t start;
+ uint16_t numbers;
+ uint16_t endpoint;
+
+ ptr = (uint8_t *)g_usb0_function_ConfigurationPtr[Con_Num - 1];
+ point_interface = *ptr;
+ length = (uint16_t)((uint16_t)*(ptr + 3) << 8 | (uint16_t)*(ptr + 2));
+ ptr += *ptr;
+ start = 0;
+ numbers = 0;
+ point_endpoint = 0;
+
+ for (; point_interface < length;)
+ {
+ switch (*(ptr + 1)) /* Descriptor Type ? */
+ {
+ case USB_FUNCTION_DT_INTERFACE: /* Interface */
+ if ((*(ptr + 2) == Int_Num) && (*(ptr + 3) == Alt_Num))
+ {
+ numbers = *(ptr + 4);
+ }
+ else
+ {
+ start += *(ptr + 4);
+ }
+ point_interface += *ptr;
+ ptr += *ptr;
+ break;
+
+ case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */
+ if (point_endpoint < numbers)
+ {
+ endpoint = (uint16_t)(*(ptr + 2) & 0x0f);
+ g_usb0_function_EPTableIndex[endpoint] = (uint16_t)(start + point_endpoint);
+ ++point_endpoint;
+ }
+ point_interface += *ptr;
+ ptr += *ptr;
+ break;
+
+ case USB_FUNCTION_DT_DEVICE: /* Device */
+ case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */
+ case USB_FUNCTION_DT_STRING: /* String */
+ default: /* Class, Vendor, else */
+ point_interface += *ptr;
+ ptr += *ptr;
+ break;
+ }
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_GetConfigNum
+* Description : Returns the number of configuration referring to the number of
+* : configuration described in the device descriptor.
+* Arguments : none
+* Return Value : Number of possible configurations (bNumConfigurations).
+*******************************************************************************/
+#if 0
+uint16_t usb0_function_GetConfigNum (void)
+{
+ return (uint16_t)g_usb0_function_DeviceDescriptor[17];
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_GetInterfaceNum
+* Description : Returns the number of interface referring to the number of
+* : interface described in the configuration descriptor.
+* Arguments : uint16_t num ; Configuration Number
+* Return Value : Number of this interface (bNumInterfaces).
+*******************************************************************************/
+#if 0
+uint16_t usb0_function_GetInterfaceNum (uint16_t num)
+{
+ return (uint16_t)(*(g_usb0_function_ConfigurationPtr[num - 1] + 4));
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_GetAltNum
+* Description : Returns the Alternate setting value of the configuration number
+* : and the interface number specified by the argument.
+* Arguments : uint16_t Con_Num ; Configuration Number
+* : uint16_t Int_Num ; Interface Number
+* Return Value : Value used to select this alternate setting(bAlternateSetting).
+*******************************************************************************/
+#if 0
+uint16_t usb0_function_GetAltNum (uint16_t Con_Num, uint16_t Int_Num)
+{
+ uint8_t * ptr;
+ uint16_t point;
+ uint16_t alt_num = 0;
+ uint16_t length;
+
+ ptr = (uint8_t *)(g_usb0_function_ConfigurationPtr[Con_Num - 1]);
+ point = ptr[0];
+ ptr += ptr[0]; /* InterfaceDescriptor[0] */
+ length = (uint16_t)(*(g_usb0_function_ConfigurationPtr[Con_Num - 1] + 2));
+ length |= (uint16_t)((uint16_t)(*(g_usb0_function_ConfigurationPtr[Con_Num - 1] + 3)) << 8);
+
+ for (; point < length;) /* Search Descriptor Table size */
+ {
+ switch (ptr[1]) /* Descriptor Type ? */
+ {
+ case USB_FUNCTION_DT_INTERFACE: /* Interface */
+ if (Int_Num == ptr[2])
+ {
+ alt_num = (uint16_t)ptr[3]; /* Alternate Number count */
+ }
+ point += ptr[0];
+ ptr += ptr[0];
+ break;
+
+ case USB_FUNCTION_DT_DEVICE: /* Device */
+ case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */
+ case USB_FUNCTION_DT_STRING: /* String */
+ case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */
+ default: /* Class, Vendor, else */
+ point += ptr[0];
+ ptr += ptr[0];
+ break;
+ }
+ }
+ return alt_num;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_CheckRemoteWakeup
+* Description : Returns the result of the remote wake up function is supported
+* : or not referring to the configuration descriptor.
+* Arguments : none
+* Return Value : DEVDRV_USBF_ON : Support Remote Wakeup
+* : DEVDRV_USBF_OFF : not Support Remote Wakeup
+*******************************************************************************/
+#if 0
+uint16_t usb0_function_CheckRemoteWakeup (void)
+{
+ uint8_t atr;
+
+ if (g_usb0_function_ConfigNum == 0)
+ {
+ return DEVDRV_USBF_OFF;
+ }
+
+ atr = *(g_usb0_function_ConfigurationPtr[g_usb0_function_ConfigNum - 1] + 7);
+
+ if (atr & USB_FUNCTION_CF_RWUP)
+ {
+ return DEVDRV_USBF_ON;
+ }
+
+ return DEVDRV_USBF_OFF;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_alt
+* Description : Initializes the Alternate setting area.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb0_function_clear_alt (void)
+{
+ int i;
+
+ for (i = 0; i < USB_FUNCTION_ALT_NO; ++i)
+ {
+ g_usb0_function_Alternate[i] = 0; /* Alternate */
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_pipe_tbl
+* Description : Initializes pipe definition table.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_function_clear_pipe_tbl (void)
+{
+ int pipe;
+
+ for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
+ {
+ g_usb0_function_PipeTbl[pipe] = 0;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_clear_ep_table_index
+* Description : Initializes the end point table index.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb0_function_clear_ep_table_index (void)
+{
+ int ep;
+
+ for (ep = 0; ep <= USB_FUNCTION_MAX_EP_NO; ++ep)
+ {
+ g_usb0_function_EPTableIndex[ep] = USB_FUNCTION_EP_ERROR;
+ }
+}
+#endif
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_dmacdrv.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_dmacdrv.c
new file mode 100644
index 000000000..5b46b68ee
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_dmacdrv.c
@@ -0,0 +1,698 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_dmacdrv.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+#include "usb0_function_dmacdrv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
+
+/* ==== Request setting information for on-chip peripheral module ==== */
+typedef enum dmac_peri_req_reg_type
+{
+ DMAC_REQ_MID,
+ DMAC_REQ_RID,
+ DMAC_REQ_AM,
+ DMAC_REQ_LVL,
+ DMAC_REQ_REQD
+} dmac_peri_req_reg_type_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+/* ==== Prototype declaration ==== */
+
+/* ==== Global variable ==== */
+/* On-chip peripheral module request setting table */
+static const uint8_t usb0_function_dmac_peri_req_init_table[8][5] =
+{
+ /* MID,RID,AM,LVL,REQD */
+ {32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
+ {32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
+ {33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
+ {33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
+ {34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
+ {34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
+ {35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
+ {35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
+};
+
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC1_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 1.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 1 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t *trans_info : Setting information to DMAC register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction: Setting value of CHCFG_n register REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb0_function_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info,
+ uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC1_CHCFG_n_DAD_SHIFT,
+ DMAC1_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC1_CHCFG_n_SAD_SHIFT,
+ DMAC1_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->dst_size,
+ DMAC1_CHCFG_n_DDS_SHIFT,
+ DMAC1_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->src_size,
+ DMAC1_CHCFG_n_SDS_SHIFT,
+ DMAC1_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_DMS_SHIFT,
+ DMAC1_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_RSEL_SHIFT,
+ DMAC1_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_SBE_SHIFT,
+ DMAC1_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_DEM_SHIFT,
+ DMAC1_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_REN_SHIFT,
+ DMAC1_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_RSW_SHIFT,
+ DMAC1_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_REN_SHIFT,
+ DMAC1_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_RSW_SHIFT,
+ DMAC1_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_TM_SHIFT,
+ DMAC1_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_SEL_SHIFT,
+ DMAC1_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_HIEN_SHIFT,
+ DMAC1_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_LOEN_SHIFT,
+ DMAC1_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC1_CHCFG_n_AM_SHIFT,
+ DMAC1_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC1_CHCFG_n_LVL_SHIFT,
+ DMAC1_CHCFG_n_LVL);
+
+ if (usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC1_CHCFG_n_REQD_SHIFT,
+ DMAC1_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ req_direction,
+ DMAC1_CHCFG_n_REQD_SHIFT,
+ DMAC1_CHCFG_n_REQD);
+ }
+
+ RZA_IO_RegWrite_32(&DMAC01.DMARS,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC01_DMARS_CH1_RID_SHIFT,
+ DMAC01_DMARS_CH1_RID);
+ RZA_IO_RegWrite_32(&DMAC01.DMARS,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC01_DMARS_CH1_MID_SHIFT,
+ DMAC01_DMARS_CH1_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC1_Open
+* Description : Enables DMAC channel 1 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb0_function_DMAC1_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_EN_SHIFT,
+ DMAC1_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_TACT_SHIFT,
+ DMAC1_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_SWRST_SHIFT,
+ DMAC1_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
+ DMAC1_CHCTRL_n_SWRST_SHIFT,
+ DMAC1_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_SETEN_SHIFT,
+ DMAC1_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_STG_SHIFT,
+ DMAC1_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC1_Close
+* Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb0_function_DMAC1_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_CLREN_SHIFT,
+ DMAC1_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_TACT_SHIFT,
+ DMAC1_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_EN_SHIFT,
+ DMAC1_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC1.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC1_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 1 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 1 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb0_function_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_SR_SHIFT,
+ DMAC1_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC1.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC1.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC1.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC1.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC2_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 2.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 2 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
+* : : register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous
+* : : transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module
+* : : request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction : Setting value of CHCFG_n register
+* : : REQD bit
+*******************************************************************************/
+void usb0_function_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info,
+ uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC2_CHCFG_n_DAD_SHIFT,
+ DMAC2_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC2_CHCFG_n_SAD_SHIFT,
+ DMAC2_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->dst_size,
+ DMAC2_CHCFG_n_DDS_SHIFT,
+ DMAC2_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->src_size,
+ DMAC2_CHCFG_n_SDS_SHIFT,
+ DMAC2_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_DMS_SHIFT,
+ DMAC2_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_RSEL_SHIFT,
+ DMAC2_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_SBE_SHIFT,
+ DMAC2_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_DEM_SHIFT,
+ DMAC2_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_REN_SHIFT,
+ DMAC2_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_RSW_SHIFT,
+ DMAC2_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_REN_SHIFT,
+ DMAC2_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_RSW_SHIFT,
+ DMAC2_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_TM_SHIFT,
+ DMAC2_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 2,
+ DMAC2_CHCFG_n_SEL_SHIFT,
+ DMAC2_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_HIEN_SHIFT,
+ DMAC2_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_LOEN_SHIFT,
+ DMAC2_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC2_CHCFG_n_AM_SHIFT,
+ DMAC2_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC2_CHCFG_n_LVL_SHIFT,
+ DMAC2_CHCFG_n_LVL);
+ if (usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC2_CHCFG_n_REQD_SHIFT,
+ DMAC2_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ req_direction,
+ DMAC2_CHCFG_n_REQD_SHIFT,
+ DMAC2_CHCFG_n_REQD);
+ }
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC23_DMARS_CH2_RID_SHIFT,
+ DMAC23_DMARS_CH2_RID);
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb0_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC23_DMARS_CH2_MID_SHIFT,
+ DMAC23_DMARS_CH2_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC2_Open
+* Description : Enables DMAC channel 2 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb0_function_DMAC2_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC.CHSTAT_2,
+ DMAC2_CHSTAT_n_EN_SHIFT,
+ DMAC2_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC.CHSTAT_2,
+ DMAC2_CHSTAT_n_TACT_SHIFT,
+ DMAC2_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_SWRST_SHIFT,
+ DMAC2_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
+ DMAC2_CHCTRL_n_SWRST_SHIFT,
+ DMAC2_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_SETEN_SHIFT,
+ DMAC2_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_STG_SHIFT,
+ DMAC2_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC2_Close
+* Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb0_function_DMAC2_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_CLREN_SHIFT,
+ DMAC2_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_TACT_SHIFT,
+ DMAC2_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_EN_SHIFT,
+ DMAC2_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC2.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_DMAC2_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 2 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 2 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb0_function_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_SR_SHIFT,
+ DMAC2_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC2.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC2.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC2.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC2.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_userdef.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_userdef.c
new file mode 100644
index 000000000..5449f60c7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_function_userdef.c
@@ -0,0 +1,762 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_function_userdef.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "devdrv_usb_function_api.h"
+#include "usb0_function_dmacdrv.h" /* common DMAC driver for USB */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DUMMY_ACCESS OSTM0CNT
+
+/* #define CACHE_WRITEBACK */
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern int32_t io_cwb(unsigned long start, unsigned long end);
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_function_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void usb0_function_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void Userdef_USB_usb0_function_delay_10us_2(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_d0fifo_dmaintid
+* Description : get D0FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D0FIFO DMA Interrupt ID
+*******************************************************************************/
+IRQn_Type Userdef_USB_usb0_function_d0fifo_dmaintid (void)
+{
+#if 0
+ return DMAINT1_IRQn;
+#else
+ return 0xFFFF;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_d1fifo_dmaintid
+* Description : get D1FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D1FIFO DMA Interrupt ID
+*******************************************************************************/
+IRQn_Type Userdef_USB_usb0_function_d1fifo_dmaintid (void)
+{
+#if 0
+ return DMAINT1_IRQn;
+#else
+ return 0xFFFF;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_attach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_function_attach (void)
+{
+ printf("\n");
+ printf("channel 0 attach device\n");
+ printf("\n");
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_detach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_function_detach (void)
+{
+ printf("\n");
+ printf("channel 0 detach device\n");
+ printf("\n");
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_delay_1ms
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_function_delay_1ms (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /*
+ * Wait 1ms (Please change for your MCU).
+ */
+ for (i = 0; i < 1440; ++i)
+ {
+ tmp = DUMMY_ACCESS;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_delay_xms
+* Description : Wait for the software in the period of time specified by the
+* : argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t msec ; Wait Time (msec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_function_delay_xms (uint32_t msec)
+{
+ volatile unsigned short i;
+
+ for (i = 0; i < msec; ++i)
+ {
+ Userdef_USB_usb0_function_delay_1ms();
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_delay_10us
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t usec ; Wait Time(x 10usec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_function_delay_10us (uint32_t usec)
+{
+ volatile int i;
+
+ /* Wait 10us (Please change for your MCU) */
+ for (i = 0; i < usec; ++i)
+ {
+ Userdef_USB_usb0_function_delay_10us_2();
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_delay_10us_2
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+static void Userdef_USB_usb0_function_delay_10us_2 (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 1us (Please change for your MCU) */
+ for (i = 0; i < 14; ++i)
+ {
+ tmp = DUMMY_ACCESS;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_delay_500ns
+* Description : Wait for software for 500ns.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_function_delay_500ns (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 500ns (Please change for your MCU) */
+ /* Wait 500ns I clock 266MHz */
+ tmp = DUMMY_ACCESS;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_start_dma
+* Description : Enables DMA transfer on the information specified by the argument.
+* : Set DMAC register by this function to enable DMA transfer.
+* : After executing this function, USB module is set to start DMA
+* : transfer. DMA transfer should not wait for DMA transfer complete.
+* Arguments : USB_FUNCTION_DMA_t *dma : DMA parameter
+* : typedef struct{
+* : uint32_t fifo; FIFO for using
+* : uint32_t buffer; Start address of transfer source/destination
+* : uint32_t bytes; Transfer size(Byte)
+* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
+* : uint32_t size; DMA transfer size
+* : } USB_FUNCTION_DMA_t;
+* : uint16_t dfacc ; 0 : cycle steal mode
+* : 1 : 16byte continuous mode
+* : 2 : 32byte continuous mode
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_function_start_dma (USB_FUNCTION_DMA_t * dma, uint16_t dfacc)
+{
+ uint32_t trncount;
+ uint32_t src;
+ uint32_t dst;
+ uint32_t size;
+ uint32_t dir;
+#ifdef CACHE_WRITEBACK
+ uint32_t ptr;
+#endif
+
+ trncount = dma->bytes;
+ dir = dma->dir;
+
+ if (dir == USB_FUNCTION_FIFO2BUF)
+ {
+ /* DxFIFO determination */
+ dst = dma->buffer;
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ src += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ src += 3; /* byte access */
+ }
+#endif
+ }
+ else
+ {
+ /* DxFIFO determination */
+ src = dma->buffer;
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ dst += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ dst += 3; /* byte access */
+ }
+#endif
+ }
+
+#ifdef CACHE_WRITEBACK
+ ptr = (uint32_t)dma->buffer;
+
+ if ((ptr & 0x20000000ul) == 0)
+ {
+ io_cwb((uint32_t)ptr, (uint32_t)(ptr) + trncount);
+ }
+#endif
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ usb0_function_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+ else
+ {
+ usb0_function_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_enable_dmac0
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_FUNCTION_FIFO2BUF)
+ {
+ request_factor =DMAC_REQ_USB0_DMA0_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_FUNCTION_BUF2FIFO)
+ {
+ request_factor =DMAC_REQ_USB0_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb0_function_DMAC1_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in
+ usb0_function_DMAC1_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb0_function_DMAC1_Open(DMAC_REQ_MODE_PERI);
+ if (ret != 0)
+ {
+ printf("DMAC1 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: usb0_function_enable_dmac1
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb0_function_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_FUNCTION_FIFO2BUF)
+ {
+ request_factor =DMAC_REQ_USB0_DMA1_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_FUNCTION_BUF2FIFO)
+ {
+ request_factor =DMAC_REQ_USB0_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb0_function_DMAC2_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in
+ usb0_function_DMAC1_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb0_function_DMAC2_Open(DMAC_REQ_MODE_PERI);
+ if (ret != 0)
+ {
+ printf("DMAC2 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_stop_dma0
+* Description : Disables DMA transfer.
+* : This function should be executed to DMAC executed at the time
+* : of specification of D0_FIF0_DMA in dma->fifo.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb0_function_stop_dma0 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb0_function_DMAC1_Close(&remain);
+
+ return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_function_stop_dma1
+* Description : Disables DMA transfer.
+* : This function should be executed to DMAC executed at the time
+* : of specification of D1_FIF0_DMA in dma->fifo.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb0_function_stop_dma1 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb0_function_DMAC2_Close(&remain);
+
+ return remain;
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function.h
new file mode 100644
index 000000000..de51053c0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function.h
@@ -0,0 +1,171 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_FUNCTION_H
+#define USB1_FUNCTION_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_function_api.h"
+#include "usb_function.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern const uint16_t g_usb1_function_bit_set[];
+extern uint32_t g_usb1_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint8_t *g_usb1_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+extern uint16_t g_usb1_function_PipeIgnore[];
+extern uint16_t g_usb1_function_PipeTbl[];
+extern uint16_t g_usb1_function_pipe_status[];
+extern uint32_t g_usb1_function_PipeDataSize[];
+
+extern USB_FUNCTION_DMA_t g_usb1_function_DmaInfo[];
+extern uint16_t g_usb1_function_DmaPipe[];
+extern uint16_t g_usb1_function_DmaBval[];
+extern uint16_t g_usb1_function_DmaStatus[];
+
+extern uint16_t g_usb1_function_CtrZeroLengthFlag;
+
+extern uint16_t g_usb1_function_ConfigNum;
+extern uint16_t g_usb1_function_Alternate[USB_FUNCTION_ALT_NO];
+extern uint16_t g_usb1_function_RemoteWakeupFlag;
+extern uint16_t g_usb1_function_TestModeFlag;
+extern uint16_t g_usb1_function_TestModeSelectors;
+
+extern uint16_t g_usb1_function_ReqType;
+extern uint16_t g_usb1_function_ReqTypeType;
+extern uint16_t g_usb1_function_ReqTypeRecip;
+extern uint16_t g_usb1_function_ReqRequest;
+extern uint16_t g_usb1_function_ReqValue;
+extern uint16_t g_usb1_function_ReqIndex;
+extern uint16_t g_usb1_function_ReqLength;
+
+extern uint16_t g_usb1_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1];
+
+extern uint16_t g_usb1_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint16_t g_usb1_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint16_t g_usb1_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1];
+extern uint16_t g_usb1_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+/* ==== common ==== */
+void usb1_function_dma_stop_d0(uint16_t pipe, uint32_t remain);
+void usb1_function_dma_stop_d1(uint16_t pipe, uint32_t remain);
+uint16_t usb1_function_is_hispeed(void);
+uint16_t usb1_function_is_hispeed_enable(void);
+uint16_t usb1_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb1_function_write_buffer(uint16_t pipe);
+uint16_t usb1_function_write_buffer_c(uint16_t pipe);
+uint16_t usb1_function_write_buffer_d0(uint16_t pipe);
+uint16_t usb1_function_write_buffer_d1(uint16_t pipe);
+void usb1_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb1_function_read_buffer(uint16_t pipe);
+uint16_t usb1_function_read_buffer_c(uint16_t pipe);
+uint16_t usb1_function_read_buffer_d0(uint16_t pipe);
+uint16_t usb1_function_read_buffer_d1(uint16_t pipe);
+uint16_t usb1_function_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb1_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb1_function_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc);
+uint16_t usb1_function_get_mbw(uint32_t trncount, uint32_t dtptr);
+uint16_t usb1_function_read_dma(uint16_t pipe);
+void usb1_function_brdy_int(uint16_t status, uint16_t int_enb);
+void usb1_function_nrdy_int(uint16_t status, uint16_t int_enb);
+void usb1_function_bemp_int(uint16_t status, uint16_t int_enb);
+void usb1_function_setting_interrupt(uint8_t level);
+void usb1_function_reset_module(uint16_t clockmode);
+uint16_t usb1_function_get_buf_size(uint16_t pipe);
+uint16_t usb1_function_get_mxps(uint16_t pipe);
+void usb1_function_clear_brdy_sts(uint16_t pipe);
+void usb1_function_clear_bemp_sts(uint16_t pipe);
+void usb1_function_clear_nrdy_sts(uint16_t pipe);
+void usb1_function_set_pid_buf(uint16_t pipe);
+void usb1_function_set_pid_nak(uint16_t pipe);
+void usb1_function_set_pid_stall(uint16_t pipe);
+void usb1_function_clear_pid_stall(uint16_t pipe);
+uint16_t usb1_function_get_pid(uint16_t pipe);
+void usb1_function_set_sqclr(uint16_t pipe);
+void usb1_function_set_sqset(uint16_t pipe);
+void usb1_function_set_csclr(uint16_t pipe);
+void usb1_function_aclrm(uint16_t pipe);
+void usb1_function_set_aclrm(uint16_t pipe);
+void usb1_function_clr_aclrm(uint16_t pipe);
+uint16_t usb1_function_get_sqmon(uint16_t pipe);
+uint16_t usb1_function_get_inbuf(uint16_t pipe);
+
+/* ==== function ==== */
+void usb1_function_init_status(void);
+void usb1_function_InitModule(uint16_t mode);
+uint16_t usb1_function_CheckVBUStaus(void);
+void usb1_function_USB_FUNCTION_Attach(void);
+void usb1_function_USB_FUNCTION_Detach(void);
+void usb1_function_USB_FUNCTION_BusReset(void);
+void usb1_function_USB_FUNCTION_Resume(void);
+void usb1_function_USB_FUNCTION_Suspend(void);
+void usb1_function_USB_FUNCTION_TestMode(void);
+void usb1_function_ResetDCP(void);
+void usb1_function_ResetEP(uint16_t num);
+uint16_t usb1_function_EpToPipe(uint16_t ep);
+void usb1_function_InitEPTable(uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num);
+uint16_t usb1_function_GetConfigNum(void);
+uint16_t usb1_function_GetAltNum(uint16_t Con_Num, uint16_t Int_Num);
+uint16_t usb1_function_CheckRemoteWakeup(void);
+void usb1_function_clear_alt(void);
+void usb1_function_clear_pipe_tbl(void);
+void usb1_function_clear_ep_table_index(void);
+uint16_t usb1_function_GetInterfaceNum(uint16_t num);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* USB1_FUNCTION_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_api.h
new file mode 100644
index 000000000..7e78076d9
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_api.h
@@ -0,0 +1,104 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_FUNCTION_API_H
+#define USB1_FUNCTION_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void usb1_api_function_init(uint8_t int_level, uint16_t mode, uint16_t clockmode);
+uint16_t usb1_api_function_IsConfigured(void);
+uint16_t usb1_function_GetDeviceState(void);
+uint16_t usb1_api_function_CtrlReadStart(uint32_t size, uint8_t *data);
+void usb1_api_function_CtrlWriteStart(uint32_t size, uint8_t *data);
+uint16_t usb1_api_function_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb1_api_function_check_pipe_status(uint16_t pipe, uint32_t *size);
+void usb1_api_function_clear_pipe_status(uint16_t pipe);
+void usb1_api_function_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+void usb1_api_function_set_pid_buf(uint16_t pipe);
+void usb1_api_function_set_pid_nak(uint16_t pipe);
+void usb1_api_function_set_pid_stall(uint16_t pipe);
+void usb1_api_function_clear_pid_stall(uint16_t pipe);
+uint16_t usb1_api_function_get_pid(uint16_t pipe);
+int32_t usb1_api_function_check_stall(uint16_t pipe);
+void usb1_api_function_set_sqclr(uint16_t pipe);
+void usb1_api_function_set_sqset(uint16_t pipe);
+void usb1_api_function_set_csclr(uint16_t pipe);
+void usb1_api_function_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb1_api_function_clear_brdy_sts(uint16_t pipe);
+void usb1_api_function_clear_bemp_sts(uint16_t pipe);
+void usb1_api_function_clear_nrdy_sts(uint16_t pipe);
+
+void usb1_function_ClearFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_SetFeature(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_SetAddress(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_SetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_SetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_SetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_SynchFrame(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_GetStatus(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_GetDescriptor(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_GetConfiguration(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_GetInterface(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Resrv_0(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Resrv_123(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Resrv_4(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+void usb1_function_Resrv_5(uint16_t type, uint16_t value, uint16_t index, uint16_t length);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB1_FUNCTION_API_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_dmacdrv.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_dmacdrv.h
new file mode 100644
index 000000000..a4882f8fa
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_function_dmacdrv.h
@@ -0,0 +1,142 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_dmacdrv.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_FUNCTION_DMACDRV_H
+#define USB1_FUNCTION_DMACDRV_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct dmac_transinfo
+{
+ uint32_t src_addr; /* Transfer source address */
+ uint32_t dst_addr; /* Transfer destination address */
+ uint32_t count; /* Transfer byte count */
+ uint32_t src_size; /* Transfer source data size */
+ uint32_t dst_size; /* Transfer destination data size */
+ uint32_t saddr_dir; /* Transfer source address direction */
+ uint32_t daddr_dir; /* Transfer destination address direction */
+} dmac_transinfo_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+/* ==== Transfer specification of the sample program ==== */
+#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */
+#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */
+
+/* ==== DMA modes ==== */
+#define DMAC_MODE_REGISTER (0) /* Register mode */
+#define DMAC_MODE_LINK (1) /* Link mode */
+
+/* ==== Transfer requests ==== */
+#define DMAC_REQ_MODE_EXT (0) /* External request */
+#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */
+#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */
+
+/* ==== DMAC transfer sizes ==== */
+#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */
+#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */
+#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */
+#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */
+#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */
+#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */
+#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */
+#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */
+
+/* ==== Address increment for transferring ==== */
+#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */
+#define DMAC_TRANS_ADR_INC (0) /* Increment */
+
+/* ==== Method for detecting DMA request ==== */
+#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */
+#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */
+#define DMAC_REQ_DET_LOW (2) /* Low level detection */
+#define DMAC_REQ_DET_HIGH (3) /* High level detection */
+
+/* ==== Request Direction ==== */
+#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */
+#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */
+
+/* ==== Descriptors ==== */
+#define DMAC_DESC_HEADER (0) /* Header */
+#define DMAC_DESC_SRC_ADDR (1) /* Source Address */
+#define DMAC_DESC_DST_ADDR (2) /* Destination Address */
+#define DMAC_DESC_COUNT (3) /* Transaction Byte */
+#define DMAC_DESC_CHCFG (4) /* Channel Confg */
+#define DMAC_DESC_CHITVL (5) /* Channel Interval */
+#define DMAC_DESC_CHEXT (6) /* Channel Extension */
+#define DMAC_DESC_LINK_ADDR (7) /* Link Address */
+
+/* ==== On-chip peripheral module requests ===== */
+typedef enum dmac_request_factor
+{
+ DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */
+ DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */
+ DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */
+ DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */
+} dmac_request_factor_t;
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+void usb1_function_DMAC3_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb1_function_DMAC3_Open(uint32_t req);
+void usb1_function_DMAC3_Close(uint32_t *remain);
+void usb1_function_DMAC3_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+void usb1_function_DMAC4_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb1_function_DMAC4_Open(uint32_t req);
+void usb1_function_DMAC4_Close(uint32_t *remain);
+void usb1_function_DMAC4_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB1_FUNCTION_DMACDRV_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dataio.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dataio.c
new file mode 100644
index 000000000..cf088b60f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dataio.c
@@ -0,0 +1,2932 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_dataio.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static uint16_t g_usb1_function_mbw[(USB_FUNCTION_MAX_PIPE_NO + 1)];
+
+static void usb1_function_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_function_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_function_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_function_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_function_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static uint16_t usb1_function_read_dma_d0(uint16_t pipe);
+static uint16_t usb1_function_read_dma_d1(uint16_t pipe);
+static uint16_t usb1_function_write_dma_d0(uint16_t pipe);
+static uint16_t usb1_function_write_dma_d1(uint16_t pipe);
+
+static void usb1_function_read_c_fifo(uint16_t pipe, uint16_t count);
+static void usb1_function_write_c_fifo(uint16_t Pipe, uint16_t count);
+static void usb1_function_read_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb1_function_write_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb1_function_read_d1_fifo(uint16_t pipe, uint16_t count);
+static void usb1_function_write_d1_fifo(uint16_t pipe, uint16_t count);
+
+static void usb1_function_clear_transaction_counter(uint16_t pipe);
+static void usb1_function_set_transaction_counter(uint16_t pipe, uint32_t count);
+
+static uint32_t usb1_function_com_get_dmasize(uint32_t trncount, uint32_t dtptr);
+
+static uint16_t usb1_function_set_dfacc_d0(uint16_t mbw, uint32_t count);
+static uint16_t usb1_function_set_dfacc_d1(uint16_t mbw, uint32_t count);
+
+
+/*******************************************************************************
+* Function Name: usb1_function_start_send_transfer
+* Description : Starts the USB data communication using pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+ uint16_t usefifo;
+ uint16_t mbw;
+
+ g_usb1_function_data_count[pipe] = size;
+ g_usb1_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ usb1_function_clear_bemp_sts(pipe);
+ usb1_function_clear_brdy_sts(pipe);
+ usb1_function_clear_nrdy_sts(pipe);
+
+ mbw = usb1_function_get_mbw(size, (uint32_t)data);
+
+ usefifo = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ case USB_FUNCTION_D0FIFO_DMA:
+ usefifo = USB_FUNCTION_D0USE;
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ case USB_FUNCTION_D1FIFO_DMA:
+ usefifo = USB_FUNCTION_D1USE;
+ break;
+
+ default:
+ usefifo = USB_FUNCTION_CUSE;
+ break;
+ };
+
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, usefifo, DEVDRV_USBF_NO, mbw);
+
+ usb1_function_clear_transaction_counter(pipe);
+
+ usb1_function_aclrm(pipe);
+
+ status = usb1_function_write_buffer(pipe);
+
+ if (status != DEVDRV_USBF_FIFOERROR)
+ {
+ usb1_function_set_pid_buf(pipe);
+ }
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_buffer
+* Description : Writes data in the buffer allocated in the pipe specified by
+* : the argument. The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_write_buffer (uint16_t pipe)
+{
+ uint16_t status;
+ uint16_t usefifo;
+
+ g_usb1_function_PipeIgnore[pipe] = 0;
+ usefifo = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ status = usb1_function_write_buffer_d0(pipe);
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ status = usb1_function_write_buffer_d1(pipe);
+ break;
+
+ case USB_FUNCTION_D0FIFO_DMA:
+ status = usb1_function_write_dma_d0(pipe);
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ status = usb1_function_write_dma_d1(pipe);
+ break;
+
+ default:
+ status = usb1_function_write_buffer_c(pipe);
+ break;
+ };
+
+ switch (status)
+ {
+ case DEVDRV_USBF_WRITING: /* Continue of data write */
+ usb1_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ usb1_function_enable_brdy_int(pipe); /* Enable Ready Interrupt */
+ break;
+
+ case DEVDRV_USBF_WRITEEND: /* End of data write */
+ case DEVDRV_USBF_WRITESHRT: /* End of data write */
+ usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ usb1_function_clear_nrdy_sts(pipe);
+ usb1_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ /* for last transfer */
+ usb1_function_enable_bemp_int(pipe); /* Enable Empty Interrupt */
+ break;
+
+ case DEVDRV_USBF_WRITEDMA: /* DMA write */
+ usb1_function_clear_nrdy_sts(pipe);
+ usb1_function_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access status */
+ default:
+ usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ usb1_function_disable_bemp_int(pipe); /* Disable Empty Interrupt */
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_buffer_c
+* Description : Writes data in the buffer allocated in the pipe specified in
+* : the argument. Writes data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_write_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ if (g_usb1_function_CtrZeroLengthFlag == 1)
+ {
+ g_usb1_function_CtrZeroLengthFlag = 0; /* Zero Length Packet Flag CLR */
+ return DEVDRV_USBF_WRITEEND;
+ }
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ if (pipe == USB_FUNCTION_PIPE0)
+ {
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw);
+ }
+ else
+ {
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, DEVDRV_USBF_NO, mbw);
+ }
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] <= (uint32_t)size)
+ {
+ status = DEVDRV_USBF_WRITEEND; /* write continues */
+ count = g_usb1_function_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = DEVDRV_USBF_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb1_function_write_c_fifo(pipe, (uint16_t)count);
+
+ if (g_usb1_function_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb1_function_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB201.CFIFOCTR, USB_CFIFOCTR_BVAL_SHIFT, USB_CFIFOCTR_BVAL) == 0)
+ {
+ USB201.CFIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */
+ g_usb1_function_CtrZeroLengthFlag = 1; /* Zero Length Packet Flag */
+ }
+ }
+ else
+ {
+ g_usb1_function_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_buffer_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_write_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] <= (uint32_t)size)
+ {
+ status = DEVDRV_USBF_WRITEEND; /* write continues */
+ count = g_usb1_function_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = DEVDRV_USBF_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb1_function_write_d0_fifo(pipe, (uint16_t)count);
+
+ if (g_usb1_function_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb1_function_data_count[pipe] = 0;
+ if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb1_function_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_buffer_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_write_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] <= (uint32_t)size)
+ {
+ status = DEVDRV_USBF_WRITEEND; /* write continues */
+ count = g_usb1_function_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = DEVDRV_USBF_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb1_function_write_d1_fifo(pipe, (uint16_t)count);
+
+ if (g_usb1_function_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb1_function_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb1_function_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D0FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb1_function_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND : Write end
+* : DEVDRV_USBF_WRITESHRT : short data
+* : DEVDRV_USBF_WRITING : Continue of data write
+* : DEVDRV_USBF_WRITEDMA : Write DMA
+* : DEVDRV_USBF_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb1_function_write_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb1_function_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb1_function_DmaPipe[USB_FUNCTION_D0FIFO] = pipe;
+
+ if ((count % size) != 0)
+ {
+ g_usb1_function_DmaBval[USB_FUNCTION_D0FIFO] = 1;
+ }
+ else
+ {
+ g_usb1_function_DmaBval[USB_FUNCTION_D0FIFO] = 0;
+ }
+
+ dfacc = usb1_function_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].fifo = USB_FUNCTION_D0FIFO_DMA;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].dir = USB_FUNCTION_BUF2FIFO;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].buffer = (uint32_t)g_usb1_function_data_pointer[pipe];
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].bytes = count;
+
+ Userdef_USB_usb1_function_start_dma(&g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO], dfacc);
+
+ usb1_function_set_curpipe2(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D0FIFOSEL, 1, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+
+ g_usb1_function_data_count[pipe] = 0;
+ g_usb1_function_data_pointer[pipe] += count;
+ status = DEVDRV_USBF_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FIFOCTR, 1, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_dma_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D1FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb1_function_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : DEVDRV_USBF_WRITEEND : Write end
+* : DEVDRV_USBF_WRITESHRT : short data
+* : DEVDRV_USBF_WRITING : Continue of data write
+* : DEVDRV_USBF_WRITEDMA : Write DMA
+* : DEVDRV_USBF_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb1_function_write_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc=0;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb1_function_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb1_function_DmaPipe[USB_FUNCTION_D1FIFO] = pipe;
+ if ((count % size) != 0)
+ {
+ g_usb1_function_DmaBval[USB_FUNCTION_D1FIFO] = 1;
+ }
+ else
+ {
+ g_usb1_function_DmaBval[USB_FUNCTION_D1FIFO] = 0;
+ }
+
+ dfacc = usb1_function_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].fifo = USB_FUNCTION_D1FIFO_DMA;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].dir = USB_FUNCTION_BUF2FIFO;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].buffer = (uint32_t)g_usb1_function_data_pointer[pipe];
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].bytes = count;
+
+ Userdef_USB_usb1_function_start_dma(&g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO], dfacc);
+
+ usb1_function_set_curpipe2(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D1FIFOSEL, 1, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+
+ g_usb1_function_data_count[pipe] = 0;
+ g_usb1_function_data_pointer[pipe] += count;
+
+ status = DEVDRV_USBF_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FIFOCTR, 1, USB_DnFIFOCTR_BVAL_SHIFT, USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = DEVDRV_USBF_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_start_receive_transfer
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb1_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t usefifo;
+
+ usb1_function_clear_bemp_sts(pipe);
+ usb1_function_clear_brdy_sts(pipe);
+ usb1_function_clear_nrdy_sts(pipe);
+
+ usefifo = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ usb1_function_start_receive_trns_d0(pipe, size, data);
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ usb1_function_start_receive_trns_d1(pipe, size, data);
+ break;
+
+ case USB_FUNCTION_D0FIFO_DMA:
+ usb1_function_start_receive_dma_d0(pipe, size, data);
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ usb1_function_start_receive_dma_d1(pipe, size, data);
+ break;
+
+ default:
+ usb1_function_start_receive_trns_c(pipe, size, data);
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_start_receive_trns_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* : When storing data in the buffer allocated in the pipe specified in the
+* : argument, BRDY interrupt is generated to read data
+* : in the interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_function_set_pid_nak(pipe);
+ g_usb1_function_data_count[pipe] = size;
+ g_usb1_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_function_PipeIgnore[pipe] = 0;
+
+ g_usb1_function_PipeDataSize[pipe] = size;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb1_function_get_mbw(size, (uint32_t)data);
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_READ, mbw);
+ USB201.CFIFOCTR = USB_FUNCTION_BITBCLR;
+
+ usb1_function_set_transaction_counter(pipe, size);
+
+ usb1_function_aclrm(pipe);
+
+ usb1_function_enable_nrdy_int(pipe);
+ usb1_function_enable_brdy_int(pipe);
+
+ usb1_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_start_receive_trns_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data in the
+* : interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_function_set_pid_nak(pipe);
+ g_usb1_function_data_count[pipe] = size;
+ g_usb1_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_function_PipeIgnore[pipe] = 0;
+
+ g_usb1_function_PipeDataSize[pipe] = size;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb1_function_get_mbw(size, (uint32_t)data);
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+
+ usb1_function_set_transaction_counter(pipe, size);
+
+ usb1_function_aclrm(pipe);
+
+ usb1_function_enable_nrdy_int(pipe);
+ usb1_function_enable_brdy_int(pipe);
+
+ usb1_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_start_receive_trns_d1
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_function_set_pid_nak(pipe);
+ g_usb1_function_data_count[pipe] = size;
+ g_usb1_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_function_PipeIgnore[pipe] = 0;
+
+ g_usb1_function_PipeDataSize[pipe] = size;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb1_function_get_mbw(size, (uint32_t)data);
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ usb1_function_set_transaction_counter(pipe, size);
+
+ usb1_function_aclrm(pipe);
+
+ usb1_function_enable_nrdy_int(pipe);
+ usb1_function_enable_brdy_int(pipe);
+
+ usb1_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_start_receive_dma_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_function_set_pid_nak(pipe);
+ g_usb1_function_data_count[pipe] = size;
+ g_usb1_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_function_PipeIgnore[pipe] = 0;
+
+ g_usb1_function_PipeDataSize[pipe] = 0;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb1_function_get_mbw(size, (uint32_t)data);
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+
+ usb1_function_set_transaction_counter(pipe, size);
+
+ usb1_function_aclrm(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb1_function_read_dma(pipe);
+
+ usb1_function_enable_nrdy_int(pipe);
+ usb1_function_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb1_function_enable_nrdy_int(pipe);
+ usb1_function_enable_brdy_int(pipe);
+ }
+
+ usb1_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_start_receive_dma_d1
+* Description : Read data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_function_set_pid_nak(pipe);
+ g_usb1_function_data_count[pipe] = size;
+ g_usb1_function_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_function_PipeIgnore[pipe] = 0;
+
+ g_usb1_function_PipeDataSize[pipe] = 0;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_WAIT;
+
+ mbw = usb1_function_get_mbw(size, (uint32_t)data);
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ usb1_function_set_transaction_counter(pipe, size);
+
+ usb1_function_aclrm(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb1_function_read_dma(pipe);
+
+ usb1_function_enable_nrdy_int(pipe);
+ usb1_function_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb1_function_enable_nrdy_int(pipe);
+ usb1_function_enable_brdy_int(pipe);
+ }
+
+ usb1_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_buffer
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Uses FIF0 set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_read_buffer (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb1_function_PipeIgnore[pipe] = 0;
+
+ if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_USE)
+ {
+ status = usb1_function_read_buffer_d0(pipe);
+ }
+ else if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_USE)
+ {
+ status = usb1_function_read_buffer_d1(pipe);
+ }
+ else
+ {
+ status = usb1_function_read_buffer_c(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_FUNCTION_READING: /* Continue of data read */
+ break;
+
+ case USB_FUNCTION_READEND: /* End of data read */
+ case USB_FUNCTION_READSHRT: /* End of data read */
+ usb1_function_disable_brdy_int(pipe);
+ g_usb1_function_PipeDataSize[pipe] -= g_usb1_function_data_count[pipe];
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ break;
+
+ case USB_FUNCTION_READOVER: /* buffer over */
+ if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_USE)
+ {
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_USE)
+ {
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ USB201.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb1_function_PipeDataSize[pipe] -= g_usb1_function_data_count[pipe];
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access status */
+ default:
+ usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_buffer_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_read_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_CUSE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb1_function_data_count[pipe];
+ }
+ else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB201.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb1_function_read_c_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb1_function_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_buffer_d0
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_read_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb1_function_data_count[pipe];
+ }
+ else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb1_function_read_d0_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb1_function_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_buffer_d1
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_read_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb1_function_data_count[pipe];
+ }
+ else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ usb1_function_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb1_function_read_d1_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb1_function_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_dma
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO or D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_function_read_dma (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb1_function_PipeIgnore[pipe] = 0;
+ if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA)
+ {
+ status = usb1_function_read_dma_d0(pipe);
+ }
+ else
+ {
+ status = usb1_function_read_dma_d1(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_FUNCTION_READING: /* Continue of data read */
+ break;
+
+ case USB_FUNCTION_READZERO: /* End of data read */
+ usb1_function_disable_brdy_int(pipe);
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ break;
+
+ case USB_FUNCTION_READEND: /* End of data read */
+ case USB_FUNCTION_READSHRT: /* End of data read */
+ usb1_function_disable_brdy_int(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb1_function_PipeDataSize[pipe] -= g_usb1_function_data_count[pipe];
+ }
+ break;
+
+ case USB_FUNCTION_READOVER: /* buffer over */
+ usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb1_function_PipeDataSize[pipe] -= g_usb1_function_data_count[pipe];
+ }
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access status */
+ default:
+ usb1_function_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_FIFOERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READZERO ; zero data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb1_function_read_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb1_function_data_count[pipe];
+ status = USB_FUNCTION_READING;
+ }
+ else
+ {
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw);
+
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ count = g_usb1_function_data_count[pipe];
+ }
+ else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ status = USB_FUNCTION_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb1_function_set_curpipe(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb1_function_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_function_DmaPipe[USB_FUNCTION_D0FIFO] = pipe; /* not use in read operation */
+ g_usb1_function_DmaBval[USB_FUNCTION_D0FIFO] = 0; /* not use in read operation */
+
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].fifo = USB_FUNCTION_D0FIFO_DMA;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].dir = USB_FUNCTION_FIFO2BUF;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].buffer = (uint32_t)g_usb1_function_data_pointer[pipe];
+ g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].bytes = count;
+
+ if (status == USB_FUNCTION_READING)
+ {
+ g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_BUSY;
+ }
+ else
+ {
+ g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb1_function_start_dma(&g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO], dfacc);
+
+ usb1_function_set_curpipe2(pipe, USB_FUNCTION_D0DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb1_function_data_count[pipe] -= count;
+ g_usb1_function_data_pointer[pipe] += count;
+ g_usb1_function_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_dma_d1
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by DMA transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_FUNCTION_READEND ; Read end
+* : USB_FUNCTION_READSHRT ; short data
+* : USB_FUNCTION_READZERO ; zero data
+* : USB_FUNCTION_READING ; Continue of data read
+* : USB_FUNCTION_READOVER ; buffer over
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb1_function_read_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[pipe], (uint32_t)g_usb1_function_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb1_function_data_count[pipe];
+ status = USB_FUNCTION_READING;
+ }
+ else
+ {
+ buffer = usb1_function_change_fifo_port(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw);
+ if (buffer == DEVDRV_USBF_FIFOERROR) /* FIFO access status */
+ {
+ return DEVDRV_USBF_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_FUNCTION_BITDTLN);
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_function_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_FUNCTION_READOVER;
+ count = g_usb1_function_data_count[pipe];
+ }
+ else if (g_usb1_function_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_FUNCTION_READEND;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_FUNCTION_READING;
+ count = dtln;
+ if (count == 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb1_function_get_buf_size(pipe); /* Data buffer size */
+ if (count != pipebuf_size)
+ {
+ status = USB_FUNCTION_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Clear BCLR */
+ status = USB_FUNCTION_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb1_function_set_curpipe(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb1_function_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_function_DmaPipe[USB_FUNCTION_D1FIFO] = pipe; /* not use in read operation */
+ g_usb1_function_DmaBval[USB_FUNCTION_D1FIFO] = 0; /* not use in read operation */
+
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].fifo = USB_FUNCTION_D1FIFO_DMA;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].dir = USB_FUNCTION_FIFO2BUF;
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].buffer = (uint32_t)g_usb1_function_data_pointer[pipe];
+ g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].bytes = count;
+
+ if (status == USB_FUNCTION_READING)
+ {
+ g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_BUSY;
+ }
+ else
+ {
+ g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb1_function_start_dma(&g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO], dfacc);
+
+ usb1_function_set_curpipe2(pipe, USB_FUNCTION_D1DMA, DEVDRV_USBF_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb1_function_data_count[pipe] -= count;
+ g_usb1_function_data_pointer[pipe] += count;
+ g_usb1_function_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_change_fifo_port
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument. After allocating FIF0, waits in the software
+* : till the corresponding pipe becomes ready.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : DEVDRV_USBF_FIFOERROR ; Error
+* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value
+*******************************************************************************/
+uint16_t usb1_function_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ usb1_function_set_curpipe(pipe, fifosel, isel, mbw);
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ switch (fifosel)
+ {
+ case USB_FUNCTION_CUSE:
+ buffer = USB201.CFIFOCTR;
+ break;
+
+ case USB_FUNCTION_D0USE:
+ case USB_FUNCTION_D0DMA:
+ buffer = USB201.D0FIFOCTR;
+ break;
+
+ case USB_FUNCTION_D1USE:
+ case USB_FUNCTION_D1DMA:
+ buffer = USB201.D1FIFOCTR;
+ break;
+
+ default:
+ buffer = 0;
+ break;
+ }
+
+ if ((buffer & USB_FUNCTION_BITFRDY) == USB_FUNCTION_BITFRDY)
+ {
+ return buffer;
+ }
+
+ loop2 = 25;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ return DEVDRV_USBF_FIFOERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_curpipe
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ g_usb1_function_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_FUNCTION_CUSE:
+ buffer = USB201.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_FUNCTION_BITISEL);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D0DMA:
+ case USB_FUNCTION_D0USE:
+ buffer = USB201.D0FIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D1DMA:
+ case USB_FUNCTION_D1USE:
+ buffer = USB201.D1FIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) ==
+ (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_curpipe2
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* : uint16_t dfacc ; DFACC Access mode
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc)
+{
+ uint16_t buffer;
+ uint32_t loop;
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ uint32_t dummy;
+#endif
+ volatile uint32_t loop2;
+
+ g_usb1_function_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_FUNCTION_CUSE:
+ buffer = USB201.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_FUNCTION_BITISEL);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)) ==
+ (buffer & (USB_FUNCTION_BITISEL | USB_FUNCTION_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D0DMA:
+ case USB_FUNCTION_D0USE:
+ buffer = USB201.D0FIFOSEL;
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_FUNCTION_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+#endif
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB201.D0FIFO.UINT32;
+ }
+#endif
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_FUNCTION_D1DMA:
+ case USB_FUNCTION_D1USE:
+ buffer = USB201.D1FIFOSEL;
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_FUNCTION_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE);
+#endif
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+#ifdef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB201.D1FIFO.UINT32;
+ loop = dummy; // avoid warning.
+ }
+#endif
+ buffer &= (uint16_t)~(USB_FUNCTION_BITCURPIPE | USB_FUNCTION_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_FUNCTION_BITCURPIPE) == (buffer & USB_FUNCTION_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_c_fifo
+* Description : Writes data in CFIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_write_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB201.CFIFO.UINT8[HH] = *g_usb1_function_data_pointer[pipe];
+ g_usb1_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB201.CFIFO.UINT16[H] = *((uint16_t *)g_usb1_function_data_pointer[pipe]);
+ g_usb1_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB201.CFIFO.UINT32 = *((uint32_t *)g_usb1_function_data_pointer[pipe]);
+ g_usb1_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_c_fifo
+* Description : Reads data from CFIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_read_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb1_function_data_pointer[pipe] = USB201.CFIFO.UINT8[HH];
+ g_usb1_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb1_function_data_pointer[pipe]) = USB201.CFIFO.UINT16[H];
+ g_usb1_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb1_function_data_pointer[pipe]) = USB201.CFIFO.UINT32;
+ g_usb1_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_d0_fifo
+* Description : Writes data in D0FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_write_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB201.D0FIFO.UINT8[HH] = *g_usb1_function_data_pointer[pipe];
+ g_usb1_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB201.D0FIFO.UINT16[H] = *((uint16_t *)g_usb1_function_data_pointer[pipe]);
+ g_usb1_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB201.D0FIFO.UINT32 = *((uint32_t *)g_usb1_function_data_pointer[pipe]);
+ g_usb1_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_d0_fifo
+* Description : Reads data from D0FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating DOFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_read_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb1_function_data_pointer[pipe] = USB201.D0FIFO.UINT8[HH];
+ g_usb1_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb1_function_data_pointer[pipe]) = USB201.D0FIFO.UINT16[H];
+ g_usb1_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb1_function_data_pointer[pipe]) = USB201.D0FIFO.UINT32;
+ g_usb1_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_write_d1_fifo
+* Description : Writes data in D1FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_write_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB201.D1FIFO.UINT8[HH] = *g_usb1_function_data_pointer[pipe];
+ g_usb1_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB201.D1FIFO.UINT16[H] = *((uint16_t *)g_usb1_function_data_pointer[pipe]);
+ g_usb1_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB201.D1FIFO.UINT32 = *((uint32_t *)g_usb1_function_data_pointer[pipe]);
+ g_usb1_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_read_d1_fifo
+* Description : Reads data from D1FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_function_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_read_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb1_function_data_pointer[pipe] = USB201.D1FIFO.UINT8[HH];
+ g_usb1_function_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_function_mbw[pipe] == USB_FUNCTION_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb1_function_data_pointer[pipe]) = USB201.D1FIFO.UINT16[H];
+ g_usb1_function_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb1_function_data_pointer[pipe]) = USB201.D1FIFO.UINT32;
+ g_usb1_function_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_com_get_dmasize
+* Description : Calculates access width of DMA transfer by the argument to
+* : return as the Return Value.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : DMA transfer size : 0 8bit
+* : : 1 16bit
+* : : 2 32bit
+*******************************************************************************/
+static uint32_t usb1_function_com_get_dmasize (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+
+ if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0))
+ {
+ /* When transfer byte count is odd */
+ /* or transfer data area is 8-bit alignment */
+ size = 0; /* 8bit */
+ }
+ else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0))
+ {
+ /* When the transfer byte count is multiples of 2 */
+ /* or the transfer data area is 16-bit alignment */
+ size = 1; /* 16bit */
+ }
+ else
+ {
+ /* When the transfer byte count is multiples of 4 */
+ /* or the transfer data area is 32-bit alignment */
+ size = 2; /* 32bit */
+ }
+
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_get_mbw
+* Description : Calculates access width of DMA to return the value set in MBW.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : FIFO transfer size : USB_FUNCTION_BITMBW_8 8bit
+* : : USB_FUNCTION_BITMBW_16 16bit
+* : : USB_FUNCTION_BITMBW_32 32bit
+*******************************************************************************/
+uint16_t usb1_function_get_mbw (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+ uint16_t mbw;
+
+ size = usb1_function_com_get_dmasize(trncount, dtptr);
+
+ if (size == 0)
+ {
+ /* 8bit */
+ mbw = USB_FUNCTION_BITMBW_8;
+ }
+ else if (size == 1)
+ {
+ /* 16bit */
+ mbw = USB_FUNCTION_BITMBW_16;
+ }
+ else
+ {
+ /* 32bit */
+ mbw = USB_FUNCTION_BITMBW_32;
+ }
+
+ return mbw;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_transaction_counter
+* Description : Sets transaction counter by the argument(PIPEnTRN).
+* : Clears transaction before setting to enable transaction counter setting.
+* Arguments : uint16_t pipe ; Pipe number
+* : uint32_t bsize : Data transfer size
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_set_transaction_counter (uint16_t pipe, uint32_t bsize)
+{
+ uint16_t mxps;
+ uint16_t cnt;
+
+ if (bsize == 0)
+ {
+ return;
+ }
+
+ mxps = usb1_function_get_mxps(pipe); /* Max Packet Size */
+
+ if ((bsize % mxps) == 0)
+ {
+ cnt = (uint16_t)(bsize / mxps);
+ }
+ else
+ {
+ cnt = (uint16_t)((bsize / mxps) + 1);
+ }
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE1TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE2TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE3TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE4TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE5TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE9TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEATRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPEATRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPEATRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPEBTRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPEBTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPECTRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPECTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPEDTRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPEDTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEETRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPEETRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPEETRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPEFTRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPEFTRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_transaction_counter
+* Description : Clears the transaction counter by the argument.
+* : After executing this function, the transaction counter is invalid.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_clear_transaction_counter (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEATRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPEATRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPEBTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPECTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPEDTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEETRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPEETRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFTRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPEFTRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_stop_transfer
+* Description : Stops the USB transfer in the pipe specified by the argument.
+* : After stopping the USB transfer, clears the buffer allocated in
+* : the pipe.
+* : After executing this function, allocation in FIF0 becomes USB_FUNCTION_PIPE0;
+* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt
+* : in the corresponding pipe becomes invalid. Sequence bit is also
+* : cleared.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_stop_transfer (uint16_t pipe)
+{
+ uint16_t usefifo;
+ uint32_t remain;
+ uint16_t fifo;
+
+ usb1_function_set_pid_nak(pipe);
+
+ usefifo = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+ switch (usefifo)
+ {
+ case USB_FUNCTION_D0FIFO_USE:
+ usb1_function_clear_transaction_counter(pipe);
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D0USE;
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ usb1_function_clear_transaction_counter(pipe);
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D1USE;
+ break;
+
+ case USB_FUNCTION_D0FIFO_DMA:
+ remain = Userdef_USB_usb1_function_stop_dma0();
+ usb1_function_dma_stop_d0(pipe, remain);
+ usb1_function_clear_transaction_counter(pipe);
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D0DMA;
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ remain = Userdef_USB_usb1_function_stop_dma1();
+ usb1_function_dma_stop_d1(pipe, remain);
+ usb1_function_clear_transaction_counter(pipe);
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_D1DMA;
+ break;
+
+ default:
+ usb1_function_clear_transaction_counter(pipe);
+ USB201.CFIFOCTR = USB_FUNCTION_BITBCLR; /* Buffer Clear */
+ fifo = USB_FUNCTION_CUSE;
+ break;
+ }
+
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, fifo, DEVDRV_USBF_NO, USB_FUNCTION_BITMBW_16);
+
+ /* Interrupt of pipe set is disabled */
+ usb1_function_disable_brdy_int(pipe);
+ usb1_function_disable_nrdy_int(pipe);
+ usb1_function_disable_bemp_int(pipe);
+
+ usb1_function_aclrm(pipe);
+ usb1_function_set_csclr(pipe);
+
+ if ( g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT )
+ {
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_dfacc_d0
+* Description : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb1_function_set_dfacc_d0 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+ return dfacc;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_dfacc_d1
+* Description : Set the DFACC setting value in D1FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb1_function_set_dfacc_d1 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_FUNCTION_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_FUNCTION_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+
+ return dfacc;
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dma.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dma.c
new file mode 100644
index 000000000..c6f3f1472
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_dma.c
@@ -0,0 +1,346 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_dma.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static void usb1_function_dmaint(uint16_t fifo);
+static void usb1_function_dmaint_buf2fifo(uint16_t pipe);
+static void usb1_function_dmaint_fifo2buf(uint16_t pipe);
+
+
+/*******************************************************************************
+* Function Name: usb1_function_dma_stop_d0
+* Description : D0FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb1_function_dma_stop_d0 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB201.D0FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC);
+
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb1_function_DmaInfo[USB_FUNCTION_D0FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
+ {
+ buffer = USB201.D0FIFOCTR;
+ dtln = (buffer & USB_FUNCTION_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb1_function_PipeDataSize[pipe] = (g_usb1_function_data_count[pipe] - remain);
+ g_usb1_function_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB201.D0FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_dma_stop_d1
+* Description : D1FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb1_function_dma_stop_d1 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB201.D1FBCFG, USB_DnFBCFG_DFACC_SHIFT, USB_DnFBCFG_DFACC);
+
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb1_function_DmaInfo[USB_FUNCTION_D1FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
+ {
+ buffer = USB201.D1FIFOCTR;
+ dtln = (buffer & USB_FUNCTION_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb1_function_PipeDataSize[pipe] = (g_usb1_function_data_count[pipe] - remain);
+ g_usb1_function_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB201.D1FIFOSEL, 0, USB_DnFIFOSEL_DREQE_SHIFT, USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_dma_interrupt_d0fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb1_function_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D0FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_function_dma_interrupt_d0fifo (uint32_t int_sense)
+{
+ usb1_function_dmaint(USB_FUNCTION_D0FIFO);
+ g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] = USB_FUNCTION_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_dma_interrupt_d1fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb1_function_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_FUNCTION_D1FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_function_dma_interrupt_d1fifo (uint32_t int_sense)
+{
+ usb1_function_dmaint(USB_FUNCTION_D1FIFO);
+ g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] = USB_FUNCTION_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_dmaint
+* Description : This function is DMA transfer end interrupt
+* Arguments : uint16_t fifo ; fifo number
+* : ; USB_FUNCTION_D0FIFO
+* : ; USB_FUNCTION_D1FIFO
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_dmaint (uint16_t fifo)
+{
+ uint16_t pipe;
+
+ pipe = g_usb1_function_DmaPipe[fifo];
+
+ if (g_usb1_function_DmaInfo[fifo].dir == USB_FUNCTION_BUF2FIFO)
+ {
+ usb1_function_dmaint_buf2fifo(pipe);
+ }
+ else
+ {
+ usb1_function_dmaint_fifo2buf(pipe);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_dmaint_fifo2buf
+* Description : Executes read completion from FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_dmaint_fifo2buf (uint16_t pipe)
+{
+ uint32_t remain;
+ uint16_t useport;
+
+ if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_DONE)
+ {
+ useport = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ if (useport == USB_FUNCTION_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb1_function_stop_dma0();
+ usb1_function_dma_stop_d0(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] == USB_FUNCTION_DMA_BUSYEND)
+ {
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ else
+ {
+ usb1_function_enable_brdy_int(pipe);
+ }
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb1_function_stop_dma1();
+ usb1_function_dma_stop_d1(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] == USB_FUNCTION_DMA_BUSYEND)
+ {
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ else
+ {
+ usb1_function_enable_brdy_int(pipe);
+ }
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_dmaint_buf2fifo
+* Description : Executes write completion in FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_dmaint_buf2fifo (uint16_t pipe)
+{
+ uint32_t remain;
+ uint16_t useport;
+
+ useport = (uint16_t)(g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+
+ if (useport == USB_FUNCTION_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb1_function_stop_dma0();
+ usb1_function_dma_stop_d0(pipe, remain);
+
+ if (g_usb1_function_DmaBval[USB_FUNCTION_D0FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb1_function_stop_dma1();
+ usb1_function_dma_stop_d1(pipe, remain);
+
+ if (g_usb1_function_DmaBval[USB_FUNCTION_D1FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+
+ usb1_function_enable_bemp_int(pipe);
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_intrn.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_intrn.c
new file mode 100644
index 000000000..bdcc9a8f7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_intrn.c
@@ -0,0 +1,249 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_intrn.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_function_brdy_int
+* Description : Executes BRDY interrupt(USB_FUNCTION_PIPE1-9).
+* : According to the pipe that interrupt is generated in,
+* : reads/writes buffer allocated in the pipe.
+* : This function is executed in the BRDY interrupt handler.
+* : This function clears BRDY interrupt status and BEMP interrupt
+* : status.
+* Arguments : uint16_t Status ; BRDYSTS Register Value
+* : uint16_t Int_enbl ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb1_function_brdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint32_t int_sense = 0;
+ uint16_t pipe;
+ uint16_t pipebit;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ pipebit = g_usb1_function_bit_set[pipe];
+
+ if ((status & pipebit) && (int_enb & pipebit))
+ {
+ USB201.BRDYSTS = (uint16_t)~pipebit;
+ USB201.BEMPSTS = (uint16_t)~pipebit;
+ if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA)
+ {
+ if (g_usb1_function_DmaStatus[USB_FUNCTION_D0FIFO] != USB_FUNCTION_DMA_READY)
+ {
+ usb1_function_dma_interrupt_d0fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb1_function_read_dma(pipe);
+ usb1_function_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB201.D0FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ }
+ else if ((g_usb1_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA)
+ {
+ if (g_usb1_function_DmaStatus[USB_FUNCTION_D1FIFO] != USB_FUNCTION_DMA_READY)
+ {
+ usb1_function_dma_interrupt_d1fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb1_function_read_dma(pipe);
+ usb1_function_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB201.D1FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+ {
+ usb1_function_read_buffer(pipe);
+ }
+ else
+ {
+ usb1_function_write_buffer(pipe);
+ }
+ }
+ }
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_nrdy_int
+* Description : Executes NRDY interrupt(USB_FUNCTION_PIPE1-9).
+* : Checks NRDY interrupt cause by PID. When the cause if STALL,
+* : regards the pipe state as STALL and ends the processing.
+* : Then the cause is not STALL, increments the error count to
+* : communicate again. When the error count is 3, determines
+* : the pipe state as DEVDRV_USBF_PIPE_NORES and ends the processing.
+* : This function is executed in the NRDY interrupt handler.
+* : This function clears NRDY interrupt status.
+* Arguments : uint16_t status ; NRDYSTS Register Value
+* : uint16_t int_enb ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_function_nrdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB201.NRDYSTS = (uint16_t)~status;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb1_function_bit_set[pipe]) == g_usb1_function_bit_set[pipe])
+ {
+ if (RZA_IO_RegRead_16(&USB201.SYSCFG0, USB_SYSCFG_DCFM_SHIFT, USB_SYSCFG_DCFM) == 1)
+ {
+ if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_WAIT)
+ {
+ pid = usb1_function_get_pid(pipe);
+ if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2))
+ {
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL;
+ }
+ else
+ {
+ g_usb1_function_PipeIgnore[pipe]++;
+ if (g_usb1_function_PipeIgnore[pipe] == 3)
+ {
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_NORES;
+ }
+ else
+ {
+ usb1_function_set_pid_buf(pipe);
+ }
+ }
+ }
+ }
+ else
+ {
+ /* USB Function */
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_bemp_int
+* Description : Executes BEMP interrupt(USB_FUNCTION_PIPE1-9).
+* Arguments : uint16_t status ; BEMPSTS Register Value
+* : uint16_t int_enb ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_function_bemp_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+ uint16_t inbuf;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB201.BEMPSTS = (uint16_t)~status;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb1_function_bit_set[pipe]) == g_usb1_function_bit_set[pipe])
+ {
+ pid = usb1_function_get_pid(pipe);
+
+ if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2))
+ {
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL;
+ }
+ else
+ {
+ inbuf = usb1_function_get_inbuf(pipe);
+
+ if (inbuf == 0)
+ {
+ usb1_function_disable_bemp_int(pipe);
+ usb1_function_set_pid_nak(pipe);
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ }
+ }
+ }
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_lib.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_lib.c
new file mode 100644
index 000000000..d448dc599
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_function_lib.c
@@ -0,0 +1,2044 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_lib.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_function_enable_brdy_int
+* Description : Enables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_enable_brdy_int (uint16_t pipe)
+{
+ /* enable brdy interrupt */
+ USB201.BRDYENB |= (uint16_t)g_usb1_function_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_disable_brdy_int
+* Description : Disables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_disable_brdy_int (uint16_t pipe)
+{
+ /* disable brdy interrupt */
+ USB201.BRDYENB &= (uint16_t)~(g_usb1_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_brdy_sts
+* Description : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_clear_brdy_sts (uint16_t pipe)
+{
+ /* clear brdy status */
+ USB201.BRDYSTS = (uint16_t)~(g_usb1_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_enable_bemp_int
+* Description : Enables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_enable_bemp_int (uint16_t pipe)
+{
+ /* enable bemp interrupt */
+ USB201.BEMPENB |= (uint16_t)g_usb1_function_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_disable_bemp_int
+* Description : Disables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_disable_bemp_int (uint16_t pipe)
+{
+ /* disable bemp interrupt */
+ USB201.BEMPENB &= (uint16_t)~(g_usb1_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_bemp_sts
+* Description : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_clear_bemp_sts (uint16_t pipe)
+{
+ /* clear bemp status */
+ USB201.BEMPSTS = (uint16_t)~(g_usb1_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_enable_nrdy_int
+* Description : Enables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : NRDY. Enables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_enable_nrdy_int (uint16_t pipe)
+{
+ /* enable nrdy interrupt */
+ USB201.NRDYENB |= (uint16_t)g_usb1_function_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_disable_nrdy_int
+* Description : Disables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : NRDY. Disables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_disable_nrdy_int (uint16_t pipe)
+{
+ /* disable nrdy interrupt */
+ USB201.NRDYENB &= (uint16_t)~(g_usb1_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_nrdy_sts
+* Description : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_clear_nrdy_sts (uint16_t pipe)
+{
+ /* clear nrdy status */
+ USB201.NRDYSTS = (uint16_t)~(g_usb1_function_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_is_hispeed
+* Description : Returns the result of USB reset hand shake (RHST) as
+* : return value.
+* Arguments : none
+* Return Value : USB_FUNCTION_HIGH_SPEED ; Hi-Speed
+* : USB_FUNCTION_FULL_SPEED ; Full-Speed
+* : LOW_SPEED ; Low-Speed
+* : USB_FUNCTION_NON_SPEED ; error
+*******************************************************************************/
+uint16_t usb1_function_is_hispeed (void)
+{
+ uint16_t rhst;
+ uint16_t speed;
+
+ rhst = RZA_IO_RegRead_16(&USB201.DVSTCTR0, USB_DVSTCTR0_RHST_SHIFT, USB_DVSTCTR0_RHST);
+
+ if (rhst == USB_FUNCTION_HSMODE)
+ {
+ speed = USB_FUNCTION_HIGH_SPEED;
+ }
+ else if (rhst == USB_FUNCTION_FSMODE)
+ {
+ speed = USB_FUNCTION_FULL_SPEED;
+ }
+ else if (rhst == USB_FUNCTION_LSMODE)
+ {
+ speed = USB_FUNCTION_LOW_SPEED;
+ }
+ else
+ {
+ speed = USB_FUNCTION_NON_SPEED;
+ }
+
+ return speed;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_is_hispeed_enable
+* Description : Returns the USB High-Speed connection enabled status as
+* : return value.
+* Arguments : none
+* Return Value : DEVDRV_USBF_YES : Hi-Speed Enable
+* : DEVDRV_USBF_NO : Hi-Speed Disable
+*******************************************************************************/
+uint16_t usb1_function_is_hispeed_enable (void)
+{
+ uint16_t ret;
+
+ ret = DEVDRV_USBF_NO;
+
+ if (RZA_IO_RegRead_16(&USB201.SYSCFG0, USB_SYSCFG_HSE_SHIFT, USB_SYSCFG_HSE) == 1)
+ {
+ ret = DEVDRV_USBF_YES;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_pid_buf
+* Description : Enables communicaqtion in the pipe specified by the argument
+* : (BUF).
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_pid_buf (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb1_function_get_pid(pipe);
+
+ if (pid == DEVDRV_USBF_PID_STALL2)
+ {
+ usb1_function_set_pid_nak(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ DEVDRV_USBF_PID_BUF,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_pid_nak
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* : When the pipe status was enabling communication (BUF) before
+* : executing before executing this function, waits in the software
+* : until the pipe becomes ready after setting disabled.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_pid_nak (uint16_t pipe)
+{
+ uint16_t pid;
+ uint16_t pbusy;
+ uint32_t loop;
+
+ pid = usb1_function_get_pid(pipe);
+
+ if (pid == DEVDRV_USBF_PID_STALL2)
+ {
+ usb1_function_set_pid_stall(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ DEVDRV_USBF_PID_NAK,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+
+ if (pid == DEVDRV_USBF_PID_BUF)
+ {
+ for (loop = 0; loop < 200; loop++)
+ {
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ pbusy = RZA_IO_RegRead_16(&USB201.DCPCTR,
+ USB_DCPCTR_PBUSY_SHIFT,
+ USB_DCPCTR_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_PBUSY_SHIFT,
+ USB_PIPEnCTR_9_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPEACTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPEBCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPECCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPEDCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPEECTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPEFCTR,
+ USB_PIPEnCTR_A_F_PBUSY_SHIFT,
+ USB_PIPEnCTR_A_F_PBUSY);
+ break;
+
+ default:
+ pbusy = 1;
+ break;
+ }
+
+ if (pbusy == 0)
+ {
+ break;
+ }
+ Userdef_USB_usb1_function_delay_500ns();
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_pid_stall
+* Description : Disables communication (STALL) in the pipe specified by the
+* : argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_pid_stall (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb1_function_get_pid(pipe);
+ if (pid == DEVDRV_USBF_PID_BUF)
+ {
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ DEVDRV_USBF_PID_STALL2,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ DEVDRV_USBF_PID_STALL,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_pid_stall
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_clear_pid_stall (uint16_t pipe)
+{
+ usb1_function_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_get_pid
+* Description : Returns the pipe state specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb1_function_get_pid (uint16_t pipe)
+{
+ uint16_t pid;
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ pid = RZA_IO_RegRead_16(&USB201.DCPCTR,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ pid = RZA_IO_RegRead_16(&USB201.PIPEACTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ pid = RZA_IO_RegRead_16(&USB201.PIPEBCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ pid = RZA_IO_RegRead_16(&USB201.PIPECCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ pid = RZA_IO_RegRead_16(&USB201.PIPEDCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ pid = RZA_IO_RegRead_16(&USB201.PIPEECTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ pid = RZA_IO_RegRead_16(&USB201.PIPEFCTR,
+ USB_PIPEnCTR_A_F_PID_SHIFT,
+ USB_PIPEnCTR_A_F_PID);
+ break;
+
+ default:
+ pid = 0;
+ break;
+ }
+
+ return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_csclr
+* Description : CSPLIT status clear setting of sprit transaction in specified
+* : pipe is performed.
+* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+* : in DCPCTR register are continuously changed (when the sequence
+* : toggle bit of data PID is continuously changed over two or more pipes),
+* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+* : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+* : In addition, both bits should be operated after PID is set to NAK.
+* : However, when it is set to the isochronous transfer as the transfer type
+* : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_csclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ 1,
+ USB_DCPCTR_CSCLR_SHIFT,
+ USB_DCPCTR_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_CSCLR_SHIFT,
+ USB_PIPEnCTR_9_CSCLR);
+ break;
+
+ default:
+ /* PIPEA-F have not CSCLR */
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_sqclr
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA0.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_sqclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ 1,
+ USB_DCPCTR_SQCLR_SHIFT,
+ USB_DCPCTR_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQCLR_SHIFT,
+ USB_PIPEnCTR_9_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQCLR_SHIFT,
+ USB_PIPEnCTR_A_F_SQCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_sqset
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA1.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_sqset (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ 1,
+ USB_DCPCTR_SQSET_SHIFT,
+ USB_DCPCTR_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQSET_SHIFT,
+ USB_PIPEnCTR_9_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ 1,
+ USB_PIPEnCTR_A_F_SQSET_SHIFT,
+ USB_PIPEnCTR_A_F_SQSET);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_get_sqmon
+* Description : Toggle bit of specified pipe is obtained
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : sqmon
+*******************************************************************************/
+uint16_t usb1_function_get_sqmon (uint16_t pipe)
+{
+ uint16_t sqmon;
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ sqmon = RZA_IO_RegRead_16(&USB201.DCPCTR,
+ USB_DCPCTR_SQMON_SHIFT,
+ USB_DCPCTR_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_SQMON_SHIFT,
+ USB_PIPEnCTR_9_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPEACTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPEBCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPECCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPEDCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPEECTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPEFCTR,
+ USB_PIPEnCTR_A_F_SQMON_SHIFT,
+ USB_PIPEnCTR_A_F_SQMON);
+ break;
+
+ default:
+ sqmon = 0;
+ break;
+ }
+
+ return sqmon;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_aclrm
+* Description : The buffer of specified pipe is initialized
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_function_aclrm (uint16_t pipe)
+{
+ usb1_function_set_aclrm(pipe);
+ usb1_function_clr_aclrm(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_set_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_function_set_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ 1,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_clr_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_function_clr_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 0,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ RZA_IO_RegWrite_16(&USB201.PIPEACTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ RZA_IO_RegWrite_16(&USB201.PIPEBCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ RZA_IO_RegWrite_16(&USB201.PIPECCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ RZA_IO_RegWrite_16(&USB201.PIPEDCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ RZA_IO_RegWrite_16(&USB201.PIPEECTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ RZA_IO_RegWrite_16(&USB201.PIPEFCTR,
+ 0,
+ USB_PIPEnCTR_A_F_ACLRM_SHIFT,
+ USB_PIPEnCTR_A_F_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_get_inbuf
+* Description : Returns INBUFM of the pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : inbuf
+*******************************************************************************/
+uint16_t usb1_function_get_inbuf (uint16_t pipe)
+{
+ uint16_t inbuf;
+
+ switch (pipe)
+ {
+ case USB_FUNCTION_PIPE0:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE1:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE2:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE3:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE4:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE5:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPE6:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE7:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE8:
+ inbuf = 0;
+ break;
+
+ case USB_FUNCTION_PIPE9:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_INBUFM_SHIFT,
+ USB_PIPEnCTR_9_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEA:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPEACTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEB:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPEBCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEC:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPECCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPED:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPEDCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEE:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPEECTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ case USB_FUNCTION_PIPEF:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPEFCTR,
+ USB_PIPEnCTR_A_F_INBUFM_SHIFT,
+ USB_PIPEnCTR_A_F_INBUFM);
+ break;
+
+ default:
+ inbuf = 0;
+ break;
+ }
+
+ return inbuf;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_setting_interrupt
+* Description : Sets the USB module interrupt level.
+* Arguments : uint8_t level
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb1_function_setting_interrupt (uint8_t level)
+{
+ uint16_t d0fifo_dmaintid;
+ uint16_t d1fifo_dmaintid;
+
+ R_INTC_RegistIntFunc(INTC_ID_USBI1, usb1_function_interrupt);
+ R_INTC_SetPriority(INTC_ID_USBI1, level);
+ R_INTC_Enable(INTC_ID_USBI1);
+
+ d0fifo_dmaintid = Userdef_USB_usb1_function_d0fifo_dmaintid();
+
+ if (d0fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d0fifo_dmaintid, usb1_function_dma_interrupt_d0fifo);
+ R_INTC_SetPriority(d0fifo_dmaintid, level);
+ R_INTC_Enable(d0fifo_dmaintid);
+ }
+
+ d1fifo_dmaintid = Userdef_USB_usb1_function_d1fifo_dmaintid();
+
+ if (d1fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d1fifo_dmaintid, usb1_function_dma_interrupt_d1fifo);
+ R_INTC_SetPriority(d1fifo_dmaintid, level);
+ R_INTC_Enable(d1fifo_dmaintid);
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_reset_module
+* Description : Initializes the USB module.
+* : Enables providing clock to the USB module.
+* : Sets USB bus wait register.
+* Arguments : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ
+* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+void usb1_function_reset_module (uint16_t clockmode)
+{
+ /* UPLLE bit is only USB0 */
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_UPLLE_SHIFT,
+ USB_SYSCFG_UPLLE) == 1)
+ {
+ if ((USB200.SYSCFG0 & USB_FUNCTION_BITUCKSEL) != clockmode)
+ {
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB201.SYSCFG0 = 0;
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_FUNCTION_BITUPLLE | clockmode);
+ Userdef_USB_usb1_function_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ Userdef_USB_usb1_function_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB201.SYSCFG0 = 0;
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_FUNCTION_BITUPLLE | clockmode);
+ Userdef_USB_usb1_function_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+
+ USB201.BUSWAIT = (uint16_t)(USB_FUNCTION_BUSWAIT_05 & USB_FUNCTION_BITBWAIT);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_get_buf_size
+* Description : Obtains pipe buffer size specified by the argument and
+* : maximum packet size of the USB device in use.
+* : When USB_FUNCTION_PIPE0 is specified by the argument, obtains the maximum
+* : packet size of the USB device using the corresponding pipe.
+* : For the case that USB_FUNCTION_PIPE0 is not assigned by the argument, when the
+* : corresponding pipe is in continuous transfer mode,
+* : obtains the buffer size allocated in the corresponcing pipe,
+* : when incontinuous transfer, obtains maximum packet size.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : Maximum packet size or buffer size
+*******************************************************************************/
+uint16_t usb1_function_get_buf_size (uint16_t pipe)
+{
+ uint16_t size;
+ uint16_t bufsize;
+
+ if (pipe == USB_FUNCTION_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_function_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1)
+ {
+ bufsize = RZA_IO_RegRead_16(&g_usb1_function_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE);
+ size = (uint16_t)((bufsize + 1) * USB_FUNCTION_PIPExBUF);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb1_function_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+ }
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_get_mxps
+* Description : Obtains maximum packet size of the USB device using the pipe
+* : specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : Max Packet Size
+*******************************************************************************/
+uint16_t usb1_function_get_mxps (uint16_t pipe)
+{
+ uint16_t size;
+
+ if (pipe == USB_FUNCTION_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb1_function_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+ return size;
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_api.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_api.c
new file mode 100644
index 000000000..6edb9d2bf
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_api.c
@@ -0,0 +1,441 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_api.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_api_function_init
+* Description : Initializes the USB module in the USB function mode.
+* Arguments : uint8_t int_level ; interruput level
+* : uint16_t mode : Speed modes
+* : : USB_FUCNTION_HIGH_SPEED: High-speed device
+* : : USB_FUCNTION_FULL_SPEED: Full-speed device
+* : uint16_t clockmode ; 48MHz ; USBFCLOCK_X1_48MHZ
+* : ; 12MHz ; USBFCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb1_api_function_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
+{
+ volatile uint8_t dummy_buf;
+
+ CPG.STBCR7 &= 0xfc; /*The clock of USB0/1 modules is permitted */
+ dummy_buf = CPG.STBCR7; /* (Dummy read) */
+
+ usb1_function_setting_interrupt(int_level);
+
+ usb1_function_reset_module(clockmode); /* reset USB module with setting tranciever */
+ /* and HSE=1 */
+
+ usb1_function_init_status(); /* clear variables */
+
+ usb1_function_InitModule(mode); /* select USB Function and Interrupt Enable */
+ /* Detect USB Device to attach or detach */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_api_function_IsConfigured
+* Description : Checks if the USB device is configured to return the result as
+* : the return value.
+* Arguments : none
+* Return Value : DEVDRV_USBF_YES : Configured & Configured Suspend
+* : DEVDRV_USBF_NO : not Configured
+*******************************************************************************/
+uint16_t usb1_api_function_IsConfigured (void)
+{
+ uint16_t dvst;
+
+ dvst = usb1_function_GetDeviceState();
+
+ if ((dvst == USB_FUNCTION_DVST_CONFIGURED) ||
+ (dvst == USB_FUNCTION_DVST_CONFIGURED_SUSPEND))
+ {
+ return DEVDRV_USBF_YES;
+ }
+
+ return DEVDRV_USBF_NO;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_GetDeviceState
+* Description : Returns the state of USB device.
+* Arguments : none
+* Return Value : Device States
+*******************************************************************************/
+uint16_t usb1_function_GetDeviceState (void)
+{
+ uint16_t dvsq;
+ uint16_t dvst;
+
+ dvsq = USB201.INTSTS0;
+ switch (dvsq & USB_FUNCTION_BITDVSQ)
+ {
+ case USB_FUNCTION_DS_POWR: /* Power state *//* power-on */
+ dvst = USB_FUNCTION_DVST_POWERED;
+ break;
+
+ case USB_FUNCTION_DS_DFLT: /* Default state *//* bus-reset */
+ dvst = USB_FUNCTION_DVST_DEFAULT;
+ break;
+
+ case USB_FUNCTION_DS_ADDS: /* Address state */
+ dvst = USB_FUNCTION_DVST_ADDRESS;
+ break;
+
+ case USB_FUNCTION_DS_CNFG: /* Configured state */
+ dvst = USB_FUNCTION_DVST_CONFIGURED;
+ break;
+
+ case USB_FUNCTION_DS_SPD_CNFG: /* Configured Suspend state */
+ dvst = USB_FUNCTION_DVST_CONFIGURED_SUSPEND;
+ break;
+
+ case USB_FUNCTION_DS_SPD_POWR: /* Power Suspend state */
+ case USB_FUNCTION_DS_SPD_DFLT: /* Default Suspend state */
+ case USB_FUNCTION_DS_SPD_ADDR: /* Address Suspend state */
+ dvst = USB_FUNCTION_DVST_SUSPEND;
+ break;
+
+ default: /* error */
+ dvst = USB_FUNCTION_DVST_SUSPEND;
+ break;
+ }
+
+ return dvst;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_start_receive_transfer
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data data Address
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ usb1_function_start_receive_transfer(pipe, size, data);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_start_send_transfer
+* Description : Starts the USB data communication using pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data data Address
+* Return Value : DEVDRV_USBF_WRITEEND ; Write end
+* : DEVDRV_USBF_WRITESHRT ; short data
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_WRITEDMA ; Write DMA
+* : DEVDRV_USBF_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_api_function_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+
+ status = usb1_function_start_send_transfer(pipe, size, data);
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_check_pipe_status
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t *size ; Data Size
+* Return Value : Pipe Status
+*******************************************************************************/
+uint16_t usb1_api_function_check_pipe_status (uint16_t pipe, uint32_t * size)
+{
+ if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_DONE)
+ {
+ *size = g_usb1_function_PipeDataSize[pipe];
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_PIPE_DONE;
+ }
+ else if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_NORES)
+ {
+ *size = 0;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_PIPE_NORES;
+ }
+ else if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_PIPE_STALL)
+ {
+ *size = 0;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_PIPE_STALL;
+ }
+ else if (g_usb1_function_pipe_status[pipe] == DEVDRV_USBF_FIFOERROR)
+ {
+ *size = 0;
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+
+ return DEVDRV_USBF_FIFOERROR;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ return g_usb1_function_pipe_status[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_clear_pipe_status
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : Pipe Status
+*******************************************************************************/
+void usb1_api_function_clear_pipe_status (uint16_t pipe)
+{
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+ g_usb1_function_PipeDataSize[pipe] = 0;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_set_pid_buf
+* Description : Enables communicaqtion in the pipe specified by the argument
+* : (BUF).
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_set_pid_buf (uint16_t pipe)
+{
+ usb1_function_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_set_pid_nak
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* : When the pipe status was enabling communication (BUF) before
+* : executing before executing this function, waits in the software
+* : until the pipe becomes ready after setting disabled.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_set_pid_nak (uint16_t pipe)
+{
+ usb1_function_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_set_pid_stall
+* Description : Disables communication (STALL) in the pipe specified by the
+* : argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_set_pid_stall (uint16_t pipe)
+{
+ usb1_function_set_pid_stall(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_clear_pid_stall
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_clear_pid_stall (uint16_t pipe)
+{
+ usb1_function_clear_pid_stall(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_get_pid
+* Description : Returns the pipe state specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb1_api_function_get_pid (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb1_function_get_pid(pipe);
+
+ return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_check_stall
+* Description :
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+int32_t usb1_api_function_check_stall (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb1_function_get_pid(pipe);
+
+ if ((pid & DEVDRV_USBF_PID_STALL) == DEVDRV_USBF_PID_STALL)
+ {
+ return DEVDRV_USBF_STALL;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_set_sqclr
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA0.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_set_sqclr (uint16_t pipe)
+{
+ usb1_function_set_sqclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_set_sqset
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA1.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_set_sqset (uint16_t pipe)
+{
+ usb1_function_set_sqset(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_set_csclr
+* Description : CSPLIT status clear setting of sprit transaction in specified
+* : pipe is performed.
+* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+* : in DCPCTR register are continuously changed (when the sequence
+* : toggle bit of data PID is continuously changed over two or more pipes),
+* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+* : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+* : In addition, both bits should be operated after PID is set to NAK.
+* : However, when it is set to the isochronous transfer as the transfer type
+* : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_set_csclr (uint16_t pipe)
+{
+ usb1_function_set_csclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_set_curpipe
+* Description : Allocates FIF0 specifed by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ usb1_function_set_curpipe(pipe, fifosel, isel, mbw);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_clear_brdy_sts
+* Description : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_clear_brdy_sts (uint16_t pipe)
+{
+ usb1_function_clear_brdy_sts(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_clear_bemp_sts
+* Description : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_clear_bemp_sts (uint16_t pipe)
+{
+ usb1_function_clear_bemp_sts(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_clear_nrdy_sts
+* Description : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_clear_nrdy_sts (uint16_t pipe)
+{
+ usb1_function_clear_nrdy_sts(pipe);
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_controlrw.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_controlrw.c
new file mode 100644
index 000000000..45f8fa485
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_controlrw.c
@@ -0,0 +1,142 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_controlrw.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_api_function_CtrlReadStart
+* Description : Executes the USB control read transfer.
+* : USB host controller <- USB device
+* Arguments : uint16_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : DEVDRV_USBF_WRITEEND ; End of data write
+* : DEVDRV_USBF_WRITESHRT ; End of short data write
+* : DEVDRV_USBF_WRITING ; Continue of data write
+* : DEVDRV_USBF_FIFOERROR ; FIFO access error
+*******************************************************************************/
+uint16_t usb1_api_function_CtrlReadStart (uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+ uint16_t mbw;
+
+ usb1_function_set_pid_nak(USB_FUNCTION_PIPE0);
+
+ g_usb1_function_data_count[USB_FUNCTION_PIPE0] = size;
+ g_usb1_function_data_pointer[USB_FUNCTION_PIPE0] = data;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[USB_FUNCTION_PIPE0],
+ (uint32_t)g_usb1_function_data_pointer[USB_FUNCTION_PIPE0]);
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw);
+ USB201.CFIFOCTR = USB_FUNCTION_BITBCLR;
+
+ status = usb1_function_write_buffer_c(USB_FUNCTION_PIPE0);
+
+ /* Peripheral Control sequence */
+ switch (status)
+ {
+ case DEVDRV_USBF_WRITESHRT: /* End of data write */
+ case DEVDRV_USBF_WRITEEND: /* End of data write (not null) */
+ case DEVDRV_USBF_WRITING: /* Continue of data write */
+ usb1_function_enable_bemp_int(USB_FUNCTION_PIPE0); /* Enable Empty Interrupt */
+ usb1_function_set_pid_buf(USB_FUNCTION_PIPE0); /* Set BUF */
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access error */
+ break;
+
+ default:
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_function_CtrlWriteStart
+* Description : Executes the USB control write transfer.
+* : USB host controller -> USB device
+* Arguments : uint16_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb1_api_function_CtrlWriteStart (uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_function_set_pid_nak(USB_FUNCTION_PIPE0);
+
+ g_usb1_function_data_count[USB_FUNCTION_PIPE0] = size;
+ g_usb1_function_data_pointer[USB_FUNCTION_PIPE0] = data;
+
+ mbw = usb1_function_get_mbw(g_usb1_function_data_count[USB_FUNCTION_PIPE0],
+ (uint32_t)g_usb1_function_data_pointer[USB_FUNCTION_PIPE0]);
+ usb1_function_set_curpipe(USB_FUNCTION_PIPE0, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_WRITE, mbw);
+ USB201.CFIFOCTR = USB_FUNCTION_BITBCLR;
+
+ usb1_function_enable_brdy_int(USB_FUNCTION_PIPE0);
+ usb1_function_set_pid_buf(USB_FUNCTION_PIPE0);
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_global.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_global.c
new file mode 100644
index 000000000..2ca4dac59
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_global.c
@@ -0,0 +1,144 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_global.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+const uint16_t g_usb1_function_bit_set[16] =
+{
+ 0x0001, 0x0002, 0x0004, 0x0008,
+ 0x0010, 0x0020, 0x0040, 0x0080,
+ 0x0100, 0x0200, 0x0400, 0x0800,
+ 0x1000, 0x2000, 0x4000, 0x8000
+};
+
+uint32_t g_usb1_function_data_count[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint8_t * g_usb1_function_data_pointer[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+uint16_t g_usb1_function_PipeIgnore[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb1_function_PipeTbl[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb1_function_pipe_status[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint32_t g_usb1_function_PipeDataSize[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+USB_FUNCTION_DMA_t g_usb1_function_DmaInfo[2];
+uint16_t g_usb1_function_DmaPipe[2];
+uint16_t g_usb1_function_DmaBval[2];
+uint16_t g_usb1_function_DmaStatus[2];
+
+uint16_t g_usb1_function_CtrZeroLengthFlag;
+
+//uint16_t g_usb1_function_ConfigNum;
+//uint16_t g_usb1_function_Alternate[USB_FUNCTION_ALT_NO];
+//uint16_t g_usb1_function_RemoteWakeupFlag;
+uint16_t g_usb1_function_TestModeFlag;
+uint16_t g_usb1_function_TestModeSelectors;
+
+//uint16_t g_usb1_function_ReqType;
+//uint16_t g_usb1_function_ReqTypeType;
+//uint16_t g_usb1_function_ReqTypeRecip;
+//uint16_t g_usb1_function_ReqRequest;
+//uint16_t g_usb1_function_ReqValue;
+//uint16_t g_usb1_function_ReqIndex;
+//uint16_t g_usb1_function_ReqLength;
+
+//uint16_t g_usb1_function_EPTableIndex[USB_FUNCTION_MAX_EP_NO + 1];
+
+uint16_t g_usb1_function_pipecfg[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb1_function_pipebuf[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb1_function_pipemaxp[USB_FUNCTION_MAX_PIPE_NO + 1];
+uint16_t g_usb1_function_pipeperi[USB_FUNCTION_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+* Function Name: usb1_function_init_status
+* Description : Initialization USB Sample Driver Variable.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_function_init_status (void)
+{
+ uint16_t pipe;
+
+ //g_usb1_function_ConfigNum = 0;
+ //g_usb1_function_RemoteWakeupFlag = DEVDRV_USBF_OFF;
+ g_usb1_function_TestModeFlag = DEVDRV_USBF_OFF;
+ g_usb1_function_CtrZeroLengthFlag = 0;
+
+#if 0
+ usb1_function_clear_alt();
+#endif
+
+ for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
+ {
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+ g_usb1_function_PipeDataSize[pipe] = 0;
+ g_usb1_function_data_count[pipe] = 0;
+
+ /* pipe configuration in usb1_function_ResetEP() */
+ g_usb1_function_pipecfg[pipe] = 0;
+ g_usb1_function_pipebuf[pipe] = 0;
+ g_usb1_function_pipemaxp[pipe] = 0;
+ g_usb1_function_pipeperi[pipe] = 0;
+ }
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sig.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sig.c
new file mode 100644
index 000000000..9c0b4af89
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sig.c
@@ -0,0 +1,330 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_sig.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_function_EnableINTModule(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_function_InitModule
+* Description : Initializes the USB module in the USB function mode.
+* Arguments : uint16_t mode ; USB_FUNCTION_HIGH_SPEED ; Hi-Speed Mode
+* : ; other ; Full-speed Mode
+* Return Value : none
+*******************************************************************************/
+void usb1_function_InitModule (uint16_t mode)
+{
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 0,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM); /* USB function */
+
+ /* USB module operation enabled */
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE);
+
+ if (mode == USB_FUNCTION_HIGH_SPEED)
+ {
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE); /* Hi-Speed Mode */
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ }
+
+ /* for power-on */
+ if (usb1_function_CheckVBUStaus() == DEVDRV_USBF_ON)
+ {
+ usb1_function_EnableINTModule(); /* Interrupt Enable */
+ usb1_function_USB_FUNCTION_Attach(); /* pull-up D+ and open D- */
+ }
+ else
+ {
+ usb1_function_USB_FUNCTION_Detach(); /* USB Detach */
+ /* with Interrupt Enable */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_CheckVBUStaus
+* Description : Checks the USB-VBUS state to returns the connection state to
+* : the USB host.
+* Arguments : none
+* Return Value : DEVDRV_USBF_ON : VBUS ON
+* : DEVDRV_USBF_OFF : VBUS OFF
+*******************************************************************************/
+uint16_t usb1_function_CheckVBUStaus (void)
+{
+ uint16_t buf1;
+ uint16_t buf2;
+ uint16_t buf3;
+
+ /* monitor VBUS pins */
+ do
+ {
+ buf1 = RZA_IO_RegRead_16(&USB201.INTSTS0,
+ USB_INTSTS0_VBSTS_SHIFT,
+ USB_INTSTS0_VBSTS);
+ Userdef_USB_usb1_function_delay_10us(1);
+ buf2 = RZA_IO_RegRead_16(&USB201.INTSTS0,
+ USB_INTSTS0_VBSTS_SHIFT,
+ USB_INTSTS0_VBSTS);
+ Userdef_USB_usb1_function_delay_10us(1);
+ buf3 = RZA_IO_RegRead_16(&USB201.INTSTS0,
+ USB_INTSTS0_VBSTS_SHIFT,
+ USB_INTSTS0_VBSTS);
+ } while ((buf1 != buf2) || (buf2 != buf3));
+
+ if (buf1 == DEVDRV_USBF_OFF)
+ {
+ return DEVDRV_USBF_OFF; /* detach */
+ }
+
+ return DEVDRV_USBF_ON; /* attach */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_USB_FUNCTION_Attach
+* Description : Connects to the USB host controller.
+* : This function pulls up D+.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_function_USB_FUNCTION_Attach (void)
+{
+ Userdef_USB_usb1_function_attach();
+
+ Userdef_USB_usb1_function_delay_xms(10);
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_DPRPU_SHIFT,
+ USB_SYSCFG_DPRPU); /* Pull-up D+ and open D- */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_USB_FUNCTION_Detach
+* Description : Disconnects from the USB host controller.
+* : This function opens D+/D-.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_function_USB_FUNCTION_Detach (void)
+{
+ uint16_t pipe;
+
+ Userdef_USB_usb1_function_detach();
+
+ for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
+ {
+ if (g_usb1_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_IDLE)
+ {
+ usb1_function_stop_transfer(pipe);
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 0,
+ USB_SYSCFG_DPRPU_SHIFT,
+ USB_SYSCFG_DPRPU); /* open D+ and D- */
+
+ /* Detach Recovery */
+ Userdef_USB_usb1_function_delay_500ns(); /* need 1us=500ns * 2 wait */
+ Userdef_USB_usb1_function_delay_500ns();
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM);
+ Userdef_USB_usb1_function_delay_500ns(); /* need 100ns wait but 500ns S/W wait */
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 0,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM);
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 0,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE); /* soft reset module */
+ Userdef_USB_usb1_function_delay_500ns();
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE);
+
+ usb1_function_EnableINTModule(); /* Interrupt Enable */
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_USB_FUNCTION_BusReset
+* Description : This function is executed when the USB device is transitioned
+* : to POWERD_STATE. Sets the device descriptor according to the
+* : connection speed determined by the USB reset hand shake.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0 /*The USBHAL in mbed does not need this function*/
+void usb1_function_USB_FUNCTION_BusReset (void)
+{
+ usb1_function_init_status(); /* memory clear */
+
+ if (usb1_function_is_hispeed() == USB_FUNCTION_HIGH_SPEED)
+ {
+ usb1_function_ResetDescriptor(USB_FUNCTION_HIGH_SPEED); /* Device Descriptor reset */
+ }
+ else
+ {
+ usb1_function_ResetDescriptor(USB_FUNCTION_FULL_SPEED); /* Device Descriptor reset */
+ }
+
+ usb1_function_ResetDCP(); /* Default Control PIPE reset */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_USB_FUNCTION_Resume
+* Description : This function is executed when the USB device detects a resume
+* : signal.
+* : The USB sample driver does not operate for this function.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0 /*The USBHAL in mbed does not need this function*/
+void usb1_function_USB_FUNCTION_Resume (void)
+{
+ /* NOP */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_USB_FUNCTION_Suspend
+* Description : This function is executed when the USB device detects a suspend
+* : signal.
+* : The USB sample driver does not operate for this function.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0 /*The USBHAL in mbed does not need this function*/
+void usb1_function_USB_FUNCTION_Suspend (void)
+{
+ /* NOP */
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_USB_FUNCTION_TestMode
+* Description : This function is executed when the USB device is transitioned U
+* : to TEST_MODE by the USB standard request.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_function_USB_FUNCTION_TestMode (void)
+{
+ switch (g_usb1_function_TestModeSelectors & USB_FUNCTION_FUNCTION_TEST_SELECT)
+ {
+ case USB_FUNCTION_FUNCTION_TEST_J:
+ case USB_FUNCTION_FUNCTION_TEST_K:
+ case USB_FUNCTION_FUNCTION_TEST_SE0_NAK:
+ case USB_FUNCTION_FUNCTION_TEST_PACKET:
+ RZA_IO_RegWrite_16(&USB201.TESTMODE,
+ (g_usb1_function_TestModeSelectors >> 8),
+ USB_TESTMODE_UTST_SHIFT,
+ USB_TESTMODE_UTST);
+ break;
+
+ case USB_FUNCTION_FUNCTION_TEST_FORCE_ENABLE:
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_EnableINTModule
+* Description : Enables USB interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_EnableINTModule (void)
+{
+ uint16_t buf;
+
+ buf = USB201.INTENB0;
+ buf |= (USB_FUNCTION_BITVBSE | USB_FUNCTION_BITDVSE | USB_FUNCTION_BITCTRE |
+ USB_FUNCTION_BITBEMPE | USB_FUNCTION_BITNRDYE | USB_FUNCTION_BITBRDYE);
+ USB201.INTENB0 = buf;
+
+ usb1_function_enable_bemp_int(USB_FUNCTION_PIPE0);
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sub.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sub.c
new file mode 100644
index 000000000..bdb548a5f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/function/usb1_function_sub.c
@@ -0,0 +1,453 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_sub.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_function.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+#if 0
+extern const uint16_t *g_usb1_function_EndPntPtr[];
+extern uint8_t g_usb1_function_DeviceDescriptor[];
+extern uint8_t *g_usb1_function_ConfigurationPtr[];
+#endif
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_function_ResetDCP
+* Description : Initializes the default control pipe(DCP).
+* Outline : Reset default control pipe
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_function_ResetDCP (void)
+{
+ USB201.DCPCFG = 0;
+#if 0
+ USB201.DCPMAXP = g_usb1_function_DeviceDescriptor[7];
+#else
+ USB201.DCPMAXP = 64;
+#endif
+
+ USB201.CFIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+ USB201.D0FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+ USB201.D1FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_ResetEP
+* Description : Initializes the end point.
+* Arguments : uint16_t num ; Configuration Number
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb1_function_ResetEP (uint16_t num)
+{
+ uint16_t pipe;
+ uint16_t ep;
+ uint16_t index;
+ uint16_t buf;
+ uint16_t * tbl;
+
+ tbl = (uint16_t *)(g_usb1_function_EndPntPtr[num - 1]);
+
+ for (ep = 1; ep <= USB_FUNCTION_MAX_EP_NO; ++ep)
+ {
+ if (g_usb1_function_EPTableIndex[ep] != USB_FUNCTION_EP_ERROR)
+ {
+ index = (uint16_t)(USB_FUNCTION_EPTABLE_LENGTH * g_usb1_function_EPTableIndex[ep]);
+ pipe = (uint16_t)(tbl[index + 0] & USB_FUNCTION_BITCURPIPE);
+
+ g_usb1_function_PipeTbl[pipe] = (uint16_t)(((tbl[index + 1] & USB_FUNCTION_DIRFIELD) << 3) |
+ ep |
+ (tbl[index + 0] & USB_FUNCTION_FIFO_USE));
+
+ if ((tbl[index + 1] & USB_FUNCTION_DIRFIELD) == USB_FUNCTION_DIR_P_OUT)
+ {
+ tbl[index + 1] |= USB_FUNCTION_SHTNAKON;
+#ifdef __USB_DMA_BFRE_ENABLE__
+ /* this routine cannnot be perfomred if read operation is executed in buffer size */
+ if (((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D0FIFO_DMA) ||
+ ((tbl[index + 0] & USB_FUNCTION_FIFO_USE) == USB_FUNCTION_D1FIFO_DMA))
+ {
+ tbl[index + 1] |= USB_FUNCTION_BFREON;
+ }
+#endif
+ }
+
+ /* Interrupt Disable */
+ buf = USB201.BRDYENB;
+ buf &= (uint16_t)~g_usb1_function_bit_set[pipe];
+ USB201.BRDYENB = buf;
+ buf = USB201.NRDYENB;
+ buf &= (uint16_t)~g_usb1_function_bit_set[pipe];
+ USB201.NRDYENB = buf;
+ buf = USB201.BEMPENB;
+ buf &= (uint16_t)~g_usb1_function_bit_set[pipe];
+ USB201.BEMPENB = buf;
+
+ usb1_function_set_pid_nak(pipe);
+
+ /* CurrentPIPE Clear */
+ if (RZA_IO_RegRead_16(&USB201.CFIFOSEL,
+ USB_CFIFOSEL_CURPIPE_SHIFT,
+ USB_CFIFOSEL_CURPIPE) == pipe)
+ {
+ RZA_IO_RegWrite_16(&USB201.CFIFOSEL,
+ 0,
+ USB_CFIFOSEL_CURPIPE_SHIFT,
+ USB_CFIFOSEL_CURPIPE);
+ }
+
+ if (RZA_IO_RegRead_16(&USB201.D0FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE);
+ }
+
+ if (RZA_IO_RegRead_16(&USB201.D1FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE);
+ }
+
+ /* PIPE Configuration */
+ USB201.PIPESEL = pipe;
+ USB201.PIPECFG = tbl[index + 1];
+ USB201.PIPEBUF = tbl[index + 2];
+ USB201.PIPEMAXP = tbl[index + 3];
+ USB201.PIPEPERI = tbl[index + 4];
+
+ g_usb1_function_pipecfg[pipe] = tbl[index + 1];
+ g_usb1_function_pipebuf[pipe] = tbl[index + 2];
+ g_usb1_function_pipemaxp[pipe] = tbl[index + 3];
+ g_usb1_function_pipeperi[pipe] = tbl[index + 4];
+
+ /* Buffer Clear */
+ usb1_function_set_sqclr(pipe);
+ usb1_function_aclrm(pipe);
+
+ /* init Global */
+ g_usb1_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+ g_usb1_function_PipeDataSize[pipe] = 0;
+ }
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_EpToPipe
+* Description : Returns the pipe which end point specified by the argument is
+* : allocated to.
+* Arguments : uint16_t ep ; Direction + Endpoint Number
+* Return Value : USB_FUNCTION_EP_ERROR : Error
+* : Others : Pipe Number
+*******************************************************************************/
+uint16_t usb1_function_EpToPipe (uint16_t ep)
+{
+ uint16_t pipe;
+
+ for (pipe = 1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++)
+ {
+ if ((g_usb1_function_PipeTbl[pipe] & 0x00ff) == ep)
+ {
+ return pipe;
+ }
+ }
+
+ return USB_FUNCTION_EP_ERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_InitEPTable
+* Description : Sets the end point by the Alternate setting value of the
+* : configuration number and the interface number specified by the
+* : argument.
+* Arguments : uint16_t Con_Num ; Configuration Number
+* : uint16_t Int_Num ; Interface Number
+* : uint16_t Alt_Num ; Alternate Setting
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb1_function_InitEPTable (uint16_t Con_Num, uint16_t Int_Num, uint16_t Alt_Num)
+{
+ uint8_t * ptr;
+ uint16_t point_interface;
+ uint16_t point_endpoint;
+ uint16_t length;
+ uint16_t start;
+ uint16_t numbers;
+ uint16_t endpoint;
+
+ ptr = (uint8_t *)g_usb1_function_ConfigurationPtr[Con_Num - 1];
+ point_interface = *ptr;
+ length = (uint16_t)((uint16_t)*(ptr + 3) << 8 | (uint16_t)*(ptr + 2));
+ ptr += *ptr;
+ start = 0;
+ numbers = 0;
+ point_endpoint = 0;
+
+ for (; point_interface < length;)
+ {
+ switch (*(ptr + 1)) /* Descriptor Type ? */
+ {
+ case USB_FUNCTION_DT_INTERFACE: /* Interface */
+ if ((*(ptr + 2) == Int_Num) && (*(ptr + 3) == Alt_Num))
+ {
+ numbers = *(ptr + 4);
+ }
+ else
+ {
+ start += *(ptr + 4);
+ }
+ point_interface += *ptr;
+ ptr += *ptr;
+ break;
+
+ case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */
+ if (point_endpoint < numbers)
+ {
+ endpoint = (uint16_t)(*(ptr + 2) & 0x0f);
+ g_usb1_function_EPTableIndex[endpoint] = (uint16_t)(start + point_endpoint);
+ ++point_endpoint;
+ }
+ point_interface += *ptr;
+ ptr += *ptr;
+ break;
+
+ case USB_FUNCTION_DT_DEVICE: /* Device */
+ case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */
+ case USB_FUNCTION_DT_STRING: /* String */
+ default: /* Class, Vendor, else */
+ point_interface += *ptr;
+ ptr += *ptr;
+ break;
+ }
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_GetConfigNum
+* Description : Returns the number of configuration referring to the number of
+* : configuration described in the device descriptor.
+* Arguments : none
+* Return Value : Number of possible configurations (bNumConfigurations).
+*******************************************************************************/
+#if 0
+uint16_t usb1_function_GetConfigNum (void)
+{
+ return (uint16_t)g_usb1_function_DeviceDescriptor[17];
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_GetInterfaceNum
+* Description : Returns the number of interface referring to the number of
+* : interface described in the configuration descriptor.
+* Arguments : uint16_t num ; Configuration Number
+* Return Value : Number of this interface (bNumInterfaces).
+*******************************************************************************/
+#if 0
+uint16_t usb1_function_GetInterfaceNum (uint16_t num)
+{
+ return (uint16_t)(*(g_usb1_function_ConfigurationPtr[num - 1] + 4));
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_GetAltNum
+* Description : Returns the Alternate setting value of the configuration number
+* : and the interface number specified by the argument.
+* Arguments : uint16_t Con_Num ; Configuration Number
+* : uint16_t Int_Num ; Interface Number
+* Return Value : Value used to select this alternate setting(bAlternateSetting).
+*******************************************************************************/
+#if 0
+uint16_t usb1_function_GetAltNum (uint16_t Con_Num, uint16_t Int_Num)
+{
+ uint8_t * ptr;
+ uint16_t point;
+ uint16_t alt_num = 0;
+ uint16_t length;
+
+ ptr = (uint8_t *)(g_usb1_function_ConfigurationPtr[Con_Num - 1]);
+ point = ptr[0];
+ ptr += ptr[0]; /* InterfaceDescriptor[0] */
+ length = (uint16_t)(*(g_usb1_function_ConfigurationPtr[Con_Num - 1] + 2));
+ length |= (uint16_t)((uint16_t)(*(g_usb1_function_ConfigurationPtr[Con_Num - 1] + 3)) << 8);
+
+ for (; point < length;) /* Search Descriptor Table size */
+ {
+ switch (ptr[1]) /* Descriptor Type ? */
+ {
+ case USB_FUNCTION_DT_INTERFACE: /* Interface */
+ if (Int_Num == ptr[2])
+ {
+ alt_num = (uint16_t)ptr[3]; /* Alternate Number count */
+ }
+ point += ptr[0];
+ ptr += ptr[0];
+ break;
+
+ case USB_FUNCTION_DT_DEVICE: /* Device */
+ case USB_FUNCTION_DT_CONFIGURATION: /* Configuration */
+ case USB_FUNCTION_DT_STRING: /* String */
+ case USB_FUNCTION_DT_ENDPOINT: /* Endpoint */
+ default: /* Class, Vendor, else */
+ point += ptr[0];
+ ptr += ptr[0];
+ break;
+ }
+ }
+ return alt_num;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_CheckRemoteWakeup
+* Description : Returns the result of the remote wake up function is supported
+* : or not referring to the configuration descriptor.
+* Arguments : none
+* Return Value : DEVDRV_USBF_ON : Support Remote Wakeup
+* : DEVDRV_USBF_OFF : not Support Remote Wakeup
+*******************************************************************************/
+#if 0
+uint16_t usb1_function_CheckRemoteWakeup (void)
+{
+ uint8_t atr;
+
+ if (g_usb1_function_ConfigNum == 0)
+ {
+ return DEVDRV_USBF_OFF;
+ }
+
+ atr = *(g_usb1_function_ConfigurationPtr[g_usb1_function_ConfigNum - 1] + 7);
+
+ if (atr & USB_FUNCTION_CF_RWUP)
+ {
+ return DEVDRV_USBF_ON;
+ }
+
+ return DEVDRV_USBF_OFF;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_alt
+* Description : Initializes the Alternate setting area.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb1_function_clear_alt (void)
+{
+ int i;
+
+ for (i = 0; i < USB_FUNCTION_ALT_NO; ++i)
+ {
+ g_usb1_function_Alternate[i] = 0; /* Alternate */
+ }
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_pipe_tbl
+* Description : Initializes pipe definition table.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_function_clear_pipe_tbl (void)
+{
+ int pipe;
+
+ for (pipe = 0; pipe < (USB_FUNCTION_MAX_PIPE_NO + 1); ++pipe)
+ {
+ g_usb1_function_PipeTbl[pipe] = 0;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_clear_ep_table_index
+* Description : Initializes the end point table index.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+#if 0
+void usb1_function_clear_ep_table_index (void)
+{
+ int ep;
+
+ for (ep = 0; ep <= USB_FUNCTION_MAX_EP_NO; ++ep)
+ {
+ g_usb1_function_EPTableIndex[ep] = USB_FUNCTION_EP_ERROR;
+ }
+}
+#endif
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_dmacdrv.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_dmacdrv.c
new file mode 100644
index 000000000..809f682a0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_dmacdrv.c
@@ -0,0 +1,698 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_dmacdrv.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+#include "usb1_function_dmacdrv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
+
+/* ==== Request setting information for on-chip peripheral module ==== */
+typedef enum dmac_peri_req_reg_type
+{
+ DMAC_REQ_MID,
+ DMAC_REQ_RID,
+ DMAC_REQ_AM,
+ DMAC_REQ_LVL,
+ DMAC_REQ_REQD
+} dmac_peri_req_reg_type_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+/* ==== Prototype declaration ==== */
+
+/* ==== Global variable ==== */
+/* On-chip peripheral module request setting table */
+static const uint8_t usb1_function_dmac_peri_req_init_table[8][5] =
+{
+ /* MID,RID,AM,LVL,REQD */
+ {32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
+ {32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
+ {33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
+ {33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
+ {34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
+ {34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
+ {35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
+ {35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
+};
+
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC3_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 1.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 1 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t *trans_info : Setting information to DMAC register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction: Setting value of CHCFG_n register REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb1_function_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info,
+ uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC3.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC3.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC3.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC3_CHCFG_n_DAD_SHIFT,
+ DMAC3_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC3_CHCFG_n_SAD_SHIFT,
+ DMAC3_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->dst_size,
+ DMAC3_CHCFG_n_DDS_SHIFT,
+ DMAC3_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->src_size,
+ DMAC3_CHCFG_n_SDS_SHIFT,
+ DMAC3_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_DMS_SHIFT,
+ DMAC3_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_RSEL_SHIFT,
+ DMAC3_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_SBE_SHIFT,
+ DMAC3_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_DEM_SHIFT,
+ DMAC3_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 1,
+ DMAC3_CHCFG_n_REN_SHIFT,
+ DMAC3_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 1,
+ DMAC3_CHCFG_n_RSW_SHIFT,
+ DMAC3_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_REN_SHIFT,
+ DMAC3_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_RSW_SHIFT,
+ DMAC3_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_TM_SHIFT,
+ DMAC3_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 3,
+ DMAC3_CHCFG_n_SEL_SHIFT,
+ DMAC3_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 1,
+ DMAC3_CHCFG_n_HIEN_SHIFT,
+ DMAC3_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_LOEN_SHIFT,
+ DMAC3_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC3_CHCFG_n_AM_SHIFT,
+ DMAC3_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC3_CHCFG_n_LVL_SHIFT,
+ DMAC3_CHCFG_n_LVL);
+
+ if (usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC3_CHCFG_n_REQD_SHIFT,
+ DMAC3_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ req_direction,
+ DMAC3_CHCFG_n_REQD_SHIFT,
+ DMAC3_CHCFG_n_REQD);
+ }
+
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC23_DMARS_CH3_RID_SHIFT,
+ DMAC23_DMARS_CH3_RID);
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC23_DMARS_CH3_MID_SHIFT,
+ DMAC23_DMARS_CH3_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC3_Open
+* Description : Enables DMAC channel 3 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb1_function_DMAC3_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_EN_SHIFT,
+ DMAC3_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_TACT_SHIFT,
+ DMAC3_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_SWRST_SHIFT,
+ DMAC3_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n,
+ DMAC3_CHCTRL_n_SWRST_SHIFT,
+ DMAC3_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_SETEN_SHIFT,
+ DMAC3_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_STG_SHIFT,
+ DMAC3_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC3_Close
+* Description : Aborts DMAC channel 3 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb1_function_DMAC3_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_CLREN_SHIFT,
+ DMAC3_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_TACT_SHIFT,
+ DMAC3_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_EN_SHIFT,
+ DMAC3_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC3.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC3_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 3 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 3 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb1_function_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_SR_SHIFT,
+ DMAC3_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC3.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC3.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC3.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC3.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC3.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC3.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC4_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 2.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 2 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
+* : : register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous
+* : : transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module
+* : : request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction : Setting value of CHCFG_n register
+* : : REQD bit
+*******************************************************************************/
+void usb1_function_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info,
+ uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC4.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC4.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC4.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC4_CHCFG_n_DAD_SHIFT,
+ DMAC4_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC4_CHCFG_n_SAD_SHIFT,
+ DMAC4_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->dst_size,
+ DMAC4_CHCFG_n_DDS_SHIFT,
+ DMAC4_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->src_size,
+ DMAC4_CHCFG_n_SDS_SHIFT,
+ DMAC4_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_DMS_SHIFT,
+ DMAC4_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_RSEL_SHIFT,
+ DMAC4_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_SBE_SHIFT,
+ DMAC4_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_DEM_SHIFT,
+ DMAC4_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 1,
+ DMAC4_CHCFG_n_REN_SHIFT,
+ DMAC4_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 1,
+ DMAC4_CHCFG_n_RSW_SHIFT,
+ DMAC4_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_REN_SHIFT,
+ DMAC4_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_RSW_SHIFT,
+ DMAC4_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_TM_SHIFT,
+ DMAC4_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 4,
+ DMAC4_CHCFG_n_SEL_SHIFT,
+ DMAC4_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 1,
+ DMAC4_CHCFG_n_HIEN_SHIFT,
+ DMAC4_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_LOEN_SHIFT,
+ DMAC4_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC4_CHCFG_n_AM_SHIFT,
+ DMAC4_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC4_CHCFG_n_LVL_SHIFT,
+ DMAC4_CHCFG_n_LVL);
+ if (usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC4_CHCFG_n_REQD_SHIFT,
+ DMAC4_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ req_direction,
+ DMAC4_CHCFG_n_REQD_SHIFT,
+ DMAC4_CHCFG_n_REQD);
+ }
+ RZA_IO_RegWrite_32(&DMAC45.DMARS,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC45_DMARS_CH4_RID_SHIFT,
+ DMAC45_DMARS_CH4_RID);
+ RZA_IO_RegWrite_32(&DMAC45.DMARS,
+ usb1_function_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC45_DMARS_CH4_MID_SHIFT,
+ DMAC45_DMARS_CH4_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC4_Open
+* Description : Enables DMAC channel 4 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb1_function_DMAC4_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_EN_SHIFT,
+ DMAC4_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_TACT_SHIFT,
+ DMAC4_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_SWRST_SHIFT,
+ DMAC4_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n,
+ DMAC4_CHCTRL_n_SWRST_SHIFT,
+ DMAC4_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_SETEN_SHIFT,
+ DMAC4_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_STG_SHIFT,
+ DMAC4_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC4_Close
+* Description : Aborts DMAC channel 4 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb1_function_DMAC4_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_CLREN_SHIFT,
+ DMAC4_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_TACT_SHIFT,
+ DMAC4_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_EN_SHIFT,
+ DMAC4_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC4.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_DMAC4_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 4 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 4 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb1_function_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_SR_SHIFT,
+ DMAC4_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC4.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC4.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC4.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC4.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC4.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC4.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_userdef.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_userdef.c
new file mode 100644
index 000000000..77c62132d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_function_userdef.c
@@ -0,0 +1,762 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_function_userdef.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "devdrv_usb_function_api.h"
+#include "usb1_function_dmacdrv.h" /* common DMAC driver for USB */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DUMMY_ACCESS OSTM0CNT
+
+/* #define CACHE_WRITEBACK */
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern int32_t io_cwb(unsigned long start, unsigned long end);
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_function_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void usb1_function_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void Userdef_USB_usb1_function_delay_10us_2(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_d0fifo_dmaintid
+* Description : get D0FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D0FIFO DMA Interrupt ID
+*******************************************************************************/
+IRQn_Type Userdef_USB_usb1_function_d0fifo_dmaintid (void)
+{
+#if 0
+ return DMAINT1_IRQn;
+#else
+ return 0xFFFF;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_d1fifo_dmaintid
+* Description : get D1FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D1FIFO DMA Interrupt ID
+*******************************************************************************/
+IRQn_Type Userdef_USB_usb1_function_d1fifo_dmaintid (void)
+{
+#if 0
+ return DMAINT1_IRQn;
+#else
+ return 0xFFFF;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_attach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_function_attach (void)
+{
+ printf("\n");
+ printf("channel 1 attach device\n");
+ printf("\n");
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_detach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_function_detach (void)
+{
+ printf("\n");
+ printf("channel 1 detach device\n");
+ printf("\n");
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_delay_1ms
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_function_delay_1ms (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /*
+ * Wait 1ms (Please change for your MCU).
+ */
+ for (i = 0; i < 1440; ++i)
+ {
+ tmp = DUMMY_ACCESS;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_delay_xms
+* Description : Wait for the software in the period of time specified by the
+* : argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t msec ; Wait Time (msec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_function_delay_xms (uint32_t msec)
+{
+ volatile unsigned short i;
+
+ for (i = 0; i < msec; ++i)
+ {
+ Userdef_USB_usb1_function_delay_1ms();
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_delay_10us
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t usec ; Wait Time(x 10usec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_function_delay_10us (uint32_t usec)
+{
+ volatile int i;
+
+ /* Wait 10us (Please change for your MCU) */
+ for (i = 0; i < usec; ++i)
+ {
+ Userdef_USB_usb1_function_delay_10us_2();
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_delay_10us_2
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+static void Userdef_USB_usb1_function_delay_10us_2 (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 1us (Please change for your MCU) */
+ for (i = 0; i < 14; ++i)
+ {
+ tmp = DUMMY_ACCESS;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_delay_500ns
+* Description : Wait for software for 500ns.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_function_delay_500ns (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 500ns (Please change for your MCU) */
+ /* Wait 500ns I clock 266MHz */
+ tmp = DUMMY_ACCESS;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_start_dma
+* Description : Enables DMA transfer on the information specified by the argument.
+* : Set DMAC register by this function to enable DMA transfer.
+* : After executing this function, USB module is set to start DMA
+* : transfer. DMA transfer should not wait for DMA transfer complete.
+* Arguments : USB_FUNCTION_DMA_t *dma : DMA parameter
+* : typedef struct{
+* : uint32_t fifo; FIFO for using
+* : uint32_t buffer; Start address of transfer source/destination
+* : uint32_t bytes; Transfer size(Byte)
+* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
+* : uint32_t size; DMA transfer size
+* : } USB_FUNCTION_DMA_t;
+* : uint16_t dfacc ; 0 : cycle steal mode
+* : 1 : 16byte continuous mode
+* : 2 : 32byte continuous mode
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_function_start_dma (USB_FUNCTION_DMA_t * dma, uint16_t dfacc)
+{
+ uint32_t trncount;
+ uint32_t src;
+ uint32_t dst;
+ uint32_t size;
+ uint32_t dir;
+#ifdef CACHE_WRITEBACK
+ uint32_t ptr;
+#endif
+
+ trncount = dma->bytes;
+ dir = dma->dir;
+
+ if (dir == USB_FUNCTION_FIFO2BUF)
+ {
+ /* DxFIFO determination */
+ dst = dma->buffer;
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ src += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ src += 3; /* byte access */
+ }
+#endif
+ }
+ else
+ {
+ /* DxFIFO determination */
+ src = dma->buffer;
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ dst += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ dst += 3; /* byte access */
+ }
+#endif
+ }
+
+#ifdef CACHE_WRITEBACK
+ ptr = (uint32_t)dma->buffer;
+
+ if ((ptr & 0x20000000ul) == 0)
+ {
+ io_cwb((uint32_t)ptr, (uint32_t)(ptr) + trncount);
+ }
+#endif
+
+ if (dma->fifo == USB_FUNCTION_D0FIFO_DMA)
+ {
+ usb1_function_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+ else
+ {
+ usb1_function_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_enable_dmac0
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_FUNCTION_FIFO2BUF)
+ {
+ request_factor =DMAC_REQ_USB1_DMA0_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_FUNCTION_BUF2FIFO)
+ {
+ request_factor =DMAC_REQ_USB1_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb1_function_DMAC3_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in
+ usb1_function_DMAC3_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb1_function_DMAC3_Open(DMAC_REQ_MODE_PERI);
+ if (ret != 0)
+ {
+ printf("DMAC3 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: usb1_function_enable_dmac1
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb1_function_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_FUNCTION_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+ printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_FUNCTION_FIFO2BUF)
+ {
+ request_factor =DMAC_REQ_USB1_DMA1_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_FUNCTION_BUF2FIFO)
+ {
+ request_factor =DMAC_REQ_USB1_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb1_function_DMAC4_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in
+ usb1_function_DMAC4_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb1_function_DMAC4_Open(DMAC_REQ_MODE_PERI);
+ if (ret != 0)
+ {
+ printf("DMAC4 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_stop_dma0
+* Description : Disables DMA transfer.
+* : This function should be executed to DMAC executed at the time
+* : of specification of D0_FIF0_DMA in dma->fifo.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb1_function_stop_dma0 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb1_function_DMAC3_Close(&remain);
+
+ return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_function_stop_dma1
+* Description : Disables DMA transfer.
+* : This function should be executed to DMAC executed at the time
+* : of specification of D1_FIF0_DMA in dma->fifo.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb1_function_stop_dma1 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb1_function_DMAC4_Close(&remain);
+
+ return remain;
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb_function_setting.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb_function_setting.h
new file mode 100644
index 000000000..fc940c477
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/TARGET_RENESAS/TARGET_RZ_A1H/usb_function_setting.h
@@ -0,0 +1,173 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#ifndef USB_FUNCTION_SETTING_H
+#define USB_FUNCTION_SETTING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USB_FUNCTION_CH 0
+#define USB_FUNCTION_HISPEED 1
+
+#if (USB_FUNCTION_CH == 0)
+#include "usb0_function.h"
+#define USB20X USB200
+#define USBIX_IRQn USBI0_IRQn
+#define g_usbx_function_bit_set g_usb0_function_bit_set
+#define g_usbx_function_PipeDataSize g_usb0_function_PipeDataSize
+#define g_usbx_function_data_count g_usb0_function_data_count
+#define g_usbx_function_PipeTbl g_usb0_function_PipeTbl
+#define g_usbx_function_DmaStatus g_usb0_function_DmaStatus
+#define g_usbx_function_pipecfg g_usb0_function_pipecfg
+#define g_usbx_function_pipe_status g_usb0_function_pipe_status
+#define g_usbx_function_data_pointer g_usb0_function_data_pointer
+#define g_usbx_function_pipebuf g_usb0_function_pipebuf
+#define g_usbx_function_pipemaxp g_usb0_function_pipemaxp
+#define g_usbx_function_pipeperi g_usb0_function_pipeperi
+#define g_usbx_function_TestModeFlag g_usb0_function_TestModeFlag
+#define usbx_function_BRDYInterruptPIPE0 usb0_function_BRDYInterruptPIPE0
+#define usbx_function_BRDYInterrupt usb0_function_BRDYInterrupt
+#define usbx_function_NRDYInterruptPIPE0 usb0_function_NRDYInterruptPIPE0
+#define usbx_function_NRDYInterrupt usb0_function_NRDYInterrupt
+#define usbx_function_BEMPInterruptPIPE0 usb0_function_BEMPInterruptPIPE0
+#define usbx_function_BEMPInterrupt usb0_function_BEMPInterrupt
+#define usbx_function_read_buffer_c usb0_function_read_buffer_c
+#define usbx_function_set_pid_buf usb0_function_set_pid_buf
+#define usbx_function_disable_brdy_int usb0_function_disable_brdy_int
+#define usbx_function_set_pid_stall usb0_function_set_pid_stall
+#define usbx_function_dma_interrupt_d0fifo usb0_function_dma_interrupt_d0fifo
+#define usbx_function_read_dma usb0_function_read_dma
+#define usbx_function_dma_interrupt_d1fifo usb0_function_dma_interrupt_d1fifo
+#define usbx_function_write_buffer usb0_function_write_buffer
+#define usbx_function_set_pid_nak usb0_function_set_pid_nak
+#define usbx_function_get_mbw usb0_function_get_mbw
+#define usbx_function_set_curpipe usb0_function_set_curpipe
+#define usbx_function_aclrm usb0_function_aclrm
+#define usbx_function_enable_nrdy_int usb0_function_enable_nrdy_int
+#define usbx_function_enable_brdy_int usb0_function_enable_brdy_int
+#define usbx_function_get_pid usb0_function_get_pid
+#define usbx_function_get_inbuf usb0_function_get_inbuf
+#define usbx_function_disable_bemp_int usb0_function_disable_bemp_int
+#define usbx_function_EpToPipe usb0_function_EpToPipe
+#define usbx_function_clear_pipe_tbl usb0_function_clear_pipe_tbl
+#define Userdef_USB_usbx_function_d0fifo_dmaintid Userdef_USB_usb0_function_d0fifo_dmaintid
+#define Userdef_USB_usbx_function_d1fifo_dmaintid Userdef_USB_usb0_function_d1fifo_dmaintid
+#define usbx_function_reset_module usb0_function_reset_module
+#define usbx_function_init_status usb0_function_init_status
+#define usbx_function_InitModule usb0_function_InitModule
+#define usbx_function_clear_alt usb0_function_clear_alt
+#define usbx_function_set_sqclr usb0_function_set_sqclr
+#define usbx_api_function_CtrlWriteStart usb0_api_function_CtrlWriteStart
+#define usbx_api_function_CtrlReadStart usb0_api_function_CtrlReadStart
+#define usbx_function_write_buffer_c usb0_function_write_buffer_c
+#define usbx_api_function_check_pipe_status usb0_api_function_check_pipe_status
+#define usbx_api_function_set_pid_nak usb0_api_function_set_pid_nak
+#define usbx_api_function_clear_pipe_status usb0_api_function_clear_pipe_status
+#define usbx_api_function_start_receive_transfer usb0_api_function_start_receive_transfer
+#define usbx_function_read_buffer usb0_function_read_buffer
+#define usbx_api_function_start_send_transfer usb0_api_function_start_send_transfer
+#define usbx_function_stop_transfer usb0_function_stop_transfer
+#define usbx_function_clear_pid_stall usb0_function_clear_pid_stall
+#define usbx_function_CheckVBUStaus usb0_function_CheckVBUStaus
+#define usbx_function_USB_FUNCTION_Attach usb0_function_USB_FUNCTION_Attach
+#define usbx_function_USB_FUNCTION_Detach usb0_function_USB_FUNCTION_Detach
+#define usbx_function_is_hispeed usb0_function_is_hispeed
+#define usbx_function_ResetDescriptor usb0_function_ResetDescriptor
+#define usbx_function_USB_FUNCTION_Suspend usb0_function_USB_FUNCTION_Suspend
+#define usbx_function_USB_FUNCTION_TestMode usb0_function_USB_FUNCTION_TestMode
+#else
+#include "usb1_function.h"
+#define USB20X USB201
+#define USBIX_IRQn USBI1_IRQn
+#define g_usbx_function_bit_set g_usb1_function_bit_set
+#define g_usbx_function_PipeDataSize g_usb1_function_PipeDataSize
+#define g_usbx_function_data_count g_usb1_function_data_count
+#define g_usbx_function_PipeTbl g_usb1_function_PipeTbl
+#define g_usbx_function_DmaStatus g_usb1_function_DmaStatus
+#define g_usbx_function_pipecfg g_usb1_function_pipecfg
+#define g_usbx_function_pipe_status g_usb1_function_pipe_status
+#define g_usbx_function_data_pointer g_usb1_function_data_pointer
+#define g_usbx_function_pipebuf g_usb1_function_pipebuf
+#define g_usbx_function_pipemaxp g_usb1_function_pipemaxp
+#define g_usbx_function_pipeperi g_usb1_function_pipeperi
+#define g_usbx_function_TestModeFlag g_usb1_function_TestModeFlag
+#define usbx_function_BRDYInterruptPIPE0 usb1_function_BRDYInterruptPIPE0
+#define usbx_function_BRDYInterrupt usb1_function_BRDYInterrupt
+#define usbx_function_NRDYInterruptPIPE0 usb1_function_NRDYInterruptPIPE0
+#define usbx_function_NRDYInterrupt usb1_function_NRDYInterrupt
+#define usbx_function_BEMPInterruptPIPE0 usb1_function_BEMPInterruptPIPE0
+#define usbx_function_BEMPInterrupt usb1_function_BEMPInterrupt
+#define usbx_function_read_buffer_c usb1_function_read_buffer_c
+#define usbx_function_set_pid_buf usb1_function_set_pid_buf
+#define usbx_function_disable_brdy_int usb1_function_disable_brdy_int
+#define usbx_function_set_pid_stall usb1_function_set_pid_stall
+#define usbx_function_dma_interrupt_d0fifo usb1_function_dma_interrupt_d0fifo
+#define usbx_function_read_dma usb1_function_read_dma
+#define usbx_function_dma_interrupt_d1fifo usb1_function_dma_interrupt_d1fifo
+#define usbx_function_write_buffer usb1_function_write_buffer
+#define usbx_function_set_pid_nak usb1_function_set_pid_nak
+#define usbx_function_get_mbw usb1_function_get_mbw
+#define usbx_function_set_curpipe usb1_function_set_curpipe
+#define usbx_function_aclrm usb1_function_aclrm
+#define usbx_function_enable_nrdy_int usb1_function_enable_nrdy_int
+#define usbx_function_enable_brdy_int usb1_function_enable_brdy_int
+#define usbx_function_get_pid usb1_function_get_pid
+#define usbx_function_get_inbuf usb1_function_get_inbuf
+#define usbx_function_disable_bemp_int usb1_function_disable_bemp_int
+#define usbx_function_EpToPipe usb1_function_EpToPipe
+#define usbx_function_clear_pipe_tbl usb1_function_clear_pipe_tbl
+#define Userdef_USB_usbx_function_d0fifo_dmaintid Userdef_USB_usb1_function_d0fifo_dmaintid
+#define Userdef_USB_usbx_function_d1fifo_dmaintid Userdef_USB_usb1_function_d1fifo_dmaintid
+#define usbx_function_reset_module usb1_function_reset_module
+#define usbx_function_init_status usb1_function_init_status
+#define usbx_function_InitModule usb1_function_InitModule
+#define usbx_function_clear_alt usb1_function_clear_alt
+#define usbx_function_set_sqclr usb1_function_set_sqclr
+#define usbx_api_function_CtrlWriteStart usb1_api_function_CtrlWriteStart
+#define usbx_api_function_CtrlReadStart usb1_api_function_CtrlReadStart
+#define usbx_function_write_buffer_c usb1_function_write_buffer_c
+#define usbx_api_function_check_pipe_status usb1_api_function_check_pipe_status
+#define usbx_api_function_set_pid_nak usb1_api_function_set_pid_nak
+#define usbx_api_function_clear_pipe_status usb1_api_function_clear_pipe_status
+#define usbx_api_function_start_receive_transfer usb1_api_function_start_receive_transfer
+#define usbx_function_read_buffer usb1_function_read_buffer
+#define usbx_api_function_start_send_transfer usb1_api_function_start_send_transfer
+#define usbx_function_stop_transfer usb1_function_stop_transfer
+#define usbx_function_clear_pid_stall usb1_function_clear_pid_stall
+#define usbx_function_CheckVBUStaus usb1_function_CheckVBUStaus
+#define usbx_function_USB_FUNCTION_Attach usb1_function_USB_FUNCTION_Attach
+#define usbx_function_USB_FUNCTION_Detach usb1_function_USB_FUNCTION_Detach
+#define usbx_function_is_hispeed usb1_function_is_hispeed
+#define usbx_function_ResetDescriptor usb1_function_ResetDescriptor
+#define usbx_function_USB_FUNCTION_Suspend usb1_function_USB_FUNCTION_Suspend
+#define usbx_function_USB_FUNCTION_TestMode usb1_function_USB_FUNCTION_TestMode
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB_FUNCTION_SETTING_H */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDescriptor.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDescriptor.h
new file mode 100644
index 000000000..9d4ce849f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDescriptor.h
@@ -0,0 +1,74 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+/* Standard descriptor types */
+#define DEVICE_DESCRIPTOR (1)
+#define CONFIGURATION_DESCRIPTOR (2)
+#define STRING_DESCRIPTOR (3)
+#define INTERFACE_DESCRIPTOR (4)
+#define ENDPOINT_DESCRIPTOR (5)
+#define QUALIFIER_DESCRIPTOR (6)
+
+/* Standard descriptor lengths */
+#define DEVICE_DESCRIPTOR_LENGTH (0x12)
+#define CONFIGURATION_DESCRIPTOR_LENGTH (0x09)
+#define INTERFACE_DESCRIPTOR_LENGTH (0x09)
+#define ENDPOINT_DESCRIPTOR_LENGTH (0x07)
+
+
+/*string offset*/
+#define STRING_OFFSET_LANGID (0)
+#define STRING_OFFSET_IMANUFACTURER (1)
+#define STRING_OFFSET_IPRODUCT (2)
+#define STRING_OFFSET_ISERIAL (3)
+#define STRING_OFFSET_ICONFIGURATION (4)
+#define STRING_OFFSET_IINTERFACE (5)
+
+/* USB Specification Release Number */
+#define USB_VERSION_2_0 (0x0200)
+
+/* Least/Most significant byte of short integer */
+#define LSB(n) ((n)&0xff)
+#define MSB(n) (((n)&0xff00)>>8)
+
+/* Convert physical endpoint number to descriptor endpoint number */
+#define PHY_TO_DESC(endpoint) (((endpoint)>>1) | (((endpoint) & 1) ? 0x80:0))
+
+/* bmAttributes in configuration descriptor */
+/* C_RESERVED must always be set */
+#define C_RESERVED (1U<<7)
+#define C_SELF_POWERED (1U<<6)
+#define C_REMOTE_WAKEUP (1U<<5)
+
+/* bMaxPower in configuration descriptor */
+#define C_POWER(mA) ((mA)/2)
+
+/* bmAttributes in endpoint descriptor */
+#define E_CONTROL (0x00)
+#define E_ISOCHRONOUS (0x01)
+#define E_BULK (0x02)
+#define E_INTERRUPT (0x03)
+
+/* For isochronous endpoints only: */
+#define E_NO_SYNCHRONIZATION (0x00)
+#define E_ASYNCHRONOUS (0x04)
+#define E_ADAPTIVE (0x08)
+#define E_SYNCHRONOUS (0x0C)
+#define E_DATA (0x00)
+#define E_FEEDBACK (0x10)
+#define E_IMPLICIT_FEEDBACK (0x20)
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice.cpp
new file mode 100644
index 000000000..dc3efc96f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice.cpp
@@ -0,0 +1,1005 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+
+#include "USBEndpoints.h"
+#include "USBDevice.h"
+#include "USBDescriptor.h"
+
+//#define DEBUG
+
+/* Device status */
+#define DEVICE_STATUS_SELF_POWERED (1U<<0)
+#define DEVICE_STATUS_REMOTE_WAKEUP (1U<<1)
+
+/* Endpoint status */
+#define ENDPOINT_STATUS_HALT (1U<<0)
+
+/* Standard feature selectors */
+#define DEVICE_REMOTE_WAKEUP (1)
+#define ENDPOINT_HALT (0)
+
+/* Macro to convert wIndex endpoint number to physical endpoint number */
+#define WINDEX_TO_PHYSICAL(endpoint) (((endpoint & 0x0f) << 1) + \
+ ((endpoint & 0x80) ? 1 : 0))
+
+
+bool USBDevice::requestGetDescriptor(void)
+{
+ bool success = false;
+#ifdef DEBUG
+ printf("get descr: type: %d\r\n", DESCRIPTOR_TYPE(transfer.setup.wValue));
+#endif
+ switch (DESCRIPTOR_TYPE(transfer.setup.wValue))
+ {
+ case DEVICE_DESCRIPTOR:
+ if (deviceDesc() != NULL)
+ {
+ if ((deviceDesc()[0] == DEVICE_DESCRIPTOR_LENGTH) \
+ && (deviceDesc()[1] == DEVICE_DESCRIPTOR))
+ {
+#ifdef DEBUG
+ printf("device descr\r\n");
+#endif
+ transfer.remaining = DEVICE_DESCRIPTOR_LENGTH;
+ transfer.ptr = deviceDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ }
+ }
+ break;
+ case CONFIGURATION_DESCRIPTOR:
+ if (configurationDesc() != NULL)
+ {
+ if ((configurationDesc()[0] == CONFIGURATION_DESCRIPTOR_LENGTH) \
+ && (configurationDesc()[1] == CONFIGURATION_DESCRIPTOR))
+ {
+#ifdef DEBUG
+ printf("conf descr request\r\n");
+#endif
+ /* Get wTotalLength */
+ transfer.remaining = configurationDesc()[2] \
+ | (configurationDesc()[3] << 8);
+
+ transfer.ptr = configurationDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ }
+ }
+ break;
+ case STRING_DESCRIPTOR:
+#ifdef DEBUG
+ printf("str descriptor\r\n");
+#endif
+ switch (DESCRIPTOR_INDEX(transfer.setup.wValue))
+ {
+ case STRING_OFFSET_LANGID:
+#ifdef DEBUG
+ printf("1\r\n");
+#endif
+ transfer.remaining = stringLangidDesc()[0];
+ transfer.ptr = stringLangidDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case STRING_OFFSET_IMANUFACTURER:
+#ifdef DEBUG
+ printf("2\r\n");
+#endif
+ transfer.remaining = stringImanufacturerDesc()[0];
+ transfer.ptr = stringImanufacturerDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case STRING_OFFSET_IPRODUCT:
+#ifdef DEBUG
+ printf("3\r\n");
+#endif
+ transfer.remaining = stringIproductDesc()[0];
+ transfer.ptr = stringIproductDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case STRING_OFFSET_ISERIAL:
+#ifdef DEBUG
+ printf("4\r\n");
+#endif
+ transfer.remaining = stringIserialDesc()[0];
+ transfer.ptr = stringIserialDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case STRING_OFFSET_ICONFIGURATION:
+#ifdef DEBUG
+ printf("5\r\n");
+#endif
+ transfer.remaining = stringIConfigurationDesc()[0];
+ transfer.ptr = stringIConfigurationDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case STRING_OFFSET_IINTERFACE:
+#ifdef DEBUG
+ printf("6\r\n");
+#endif
+ transfer.remaining = stringIinterfaceDesc()[0];
+ transfer.ptr = stringIinterfaceDesc();
+ transfer.direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ }
+ break;
+ case INTERFACE_DESCRIPTOR:
+#ifdef DEBUG
+ printf("interface descr\r\n");
+#endif
+ case ENDPOINT_DESCRIPTOR:
+#ifdef DEBUG
+ printf("endpoint descr\r\n");
+#endif
+ /* TODO: Support is optional, not implemented here */
+ break;
+ default:
+#ifdef DEBUG
+ printf("ERROR\r\n");
+#endif
+ break;
+ }
+
+ return success;
+}
+
+void USBDevice::decodeSetupPacket(uint8_t *data, SETUP_PACKET *packet)
+{
+ /* Fill in the elements of a SETUP_PACKET structure from raw data */
+ packet->bmRequestType.dataTransferDirection = (data[0] & 0x80) >> 7;
+ packet->bmRequestType.Type = (data[0] & 0x60) >> 5;
+ packet->bmRequestType.Recipient = data[0] & 0x1f;
+ packet->bRequest = data[1];
+ packet->wValue = (data[2] | (uint16_t)data[3] << 8);
+ packet->wIndex = (data[4] | (uint16_t)data[5] << 8);
+ packet->wLength = (data[6] | (uint16_t)data[7] << 8);
+}
+
+
+bool USBDevice::controlOut(void)
+{
+ /* Control transfer data OUT stage */
+ uint8_t buffer[MAX_PACKET_SIZE_EP0];
+ uint32_t packetSize;
+
+ /* Check we should be transferring data OUT */
+ if (transfer.direction != HOST_TO_DEVICE)
+ {
+#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1)
+ /*
+ * We seem to have a pending device-to-host transfer. The host must have
+ * sent a new control request without waiting for us to finish processing
+ * the previous one. This appears to happen when we're connected to certain
+ * USB 3.0 host chip set. Do a zeor-length send to tell the host we're not
+ * ready for the new request - that'll make it resend - and then just
+ * pretend we were successful here so that the pending transfer can finish.
+ */
+ uint8_t buf[1] = { 0 };
+ EP0write(buf, 0);
+
+ /* execute our pending ttransfer */
+ controlIn();
+
+ /* indicate success */
+ return true;
+ #else
+ /* for other platforms, count on the HAL to handle this case */
+ return false;
+ #endif
+ }
+
+ /* Read from endpoint */
+ packetSize = EP0getReadResult(buffer);
+
+ /* Check if transfer size is valid */
+ if (packetSize > transfer.remaining)
+ {
+ /* Too big */
+ return false;
+ }
+
+ /* Update transfer */
+ transfer.ptr += packetSize;
+ transfer.remaining -= packetSize;
+
+ /* Check if transfer has completed */
+ if (transfer.remaining == 0)
+ {
+ /* Transfer completed */
+ if (transfer.notify)
+ {
+ /* Notify class layer. */
+ USBCallback_requestCompleted(buffer, packetSize);
+ transfer.notify = false;
+ }
+ /* Status stage */
+ EP0write(NULL, 0);
+ }
+ else
+ {
+ EP0read();
+ }
+
+ return true;
+}
+
+bool USBDevice::controlIn(void)
+{
+ /* Control transfer data IN stage */
+ uint32_t packetSize;
+
+ /* Check if transfer has completed (status stage transactions */
+ /* also have transfer.remaining == 0) */
+ if (transfer.remaining == 0)
+ {
+ if (transfer.zlp)
+ {
+ /* Send zero length packet */
+ EP0write(NULL, 0);
+ transfer.zlp = false;
+ }
+
+ /* Transfer completed */
+ if (transfer.notify)
+ {
+ /* Notify class layer. */
+ USBCallback_requestCompleted(NULL, 0);
+ transfer.notify = false;
+ }
+
+ EP0read();
+ EP0readStage();
+
+ /* Completed */
+ return true;
+ }
+
+ /* Check we should be transferring data IN */
+ if (transfer.direction != DEVICE_TO_HOST)
+ {
+ return false;
+ }
+
+ packetSize = transfer.remaining;
+
+ if (packetSize > MAX_PACKET_SIZE_EP0)
+ {
+ packetSize = MAX_PACKET_SIZE_EP0;
+ }
+
+ /* Write to endpoint */
+ EP0write(transfer.ptr, packetSize);
+
+ /* Update transfer */
+ transfer.ptr += packetSize;
+ transfer.remaining -= packetSize;
+
+ return true;
+}
+
+bool USBDevice::requestSetAddress(void)
+{
+ /* Set the device address */
+ setAddress(transfer.setup.wValue);
+
+ if (transfer.setup.wValue == 0)
+ {
+ device.state = DEFAULT;
+ }
+ else
+ {
+ device.state = ADDRESS;
+ }
+
+ return true;
+}
+
+bool USBDevice::requestSetConfiguration(void)
+{
+
+ device.configuration = transfer.setup.wValue;
+ /* Set the device configuration */
+ if (device.configuration == 0)
+ {
+ /* Not configured */
+ unconfigureDevice();
+ device.state = ADDRESS;
+ }
+ else
+ {
+ if (USBCallback_setConfiguration(device.configuration))
+ {
+ /* Valid configuration */
+ configureDevice();
+ device.state = CONFIGURED;
+ }
+ else
+ {
+ return false;
+ }
+ }
+
+ return true;
+}
+
+bool USBDevice::requestGetConfiguration(void)
+{
+ /* Send the device configuration */
+ transfer.ptr = &device.configuration;
+ transfer.remaining = sizeof(device.configuration);
+ transfer.direction = DEVICE_TO_HOST;
+ return true;
+}
+
+bool USBDevice::requestGetInterface(void)
+{
+ /* Return the selected alternate setting for an interface */
+
+ if (device.state != CONFIGURED)
+ {
+ return false;
+ }
+
+ /* Send the alternate setting */
+ transfer.setup.wIndex = currentInterface;
+ transfer.ptr = &currentAlternate;
+ transfer.remaining = sizeof(currentAlternate);
+ transfer.direction = DEVICE_TO_HOST;
+ return true;
+}
+
+bool USBDevice::requestSetInterface(void)
+{
+ bool success = false;
+ if(USBCallback_setInterface(transfer.setup.wIndex, transfer.setup.wValue))
+ {
+ success = true;
+ currentInterface = transfer.setup.wIndex;
+ currentAlternate = transfer.setup.wValue;
+ }
+ return success;
+}
+
+bool USBDevice::requestSetFeature()
+{
+ bool success = false;
+
+ if (device.state != CONFIGURED)
+ {
+ /* Endpoint or interface must be zero */
+ if (transfer.setup.wIndex != 0)
+ {
+ return false;
+ }
+ }
+
+ switch (transfer.setup.bmRequestType.Recipient)
+ {
+ case DEVICE_RECIPIENT:
+ /* TODO: Remote wakeup feature not supported */
+ break;
+ case ENDPOINT_RECIPIENT:
+ if (transfer.setup.wValue == ENDPOINT_HALT)
+ {
+ /* TODO: We should check that the endpoint number is valid */
+ stallEndpoint(
+ WINDEX_TO_PHYSICAL(transfer.setup.wIndex));
+ success = true;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return success;
+}
+
+bool USBDevice::requestClearFeature()
+{
+ bool success = false;
+
+ if (device.state != CONFIGURED)
+ {
+ /* Endpoint or interface must be zero */
+ if (transfer.setup.wIndex != 0)
+ {
+ return false;
+ }
+ }
+
+ switch (transfer.setup.bmRequestType.Recipient)
+ {
+ case DEVICE_RECIPIENT:
+ /* TODO: Remote wakeup feature not supported */
+ break;
+ case ENDPOINT_RECIPIENT:
+ /* TODO: We should check that the endpoint number is valid */
+ if (transfer.setup.wValue == ENDPOINT_HALT)
+ {
+ unstallEndpoint( WINDEX_TO_PHYSICAL(transfer.setup.wIndex));
+ success = true;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return success;
+}
+
+bool USBDevice::requestGetStatus(void)
+{
+ static uint16_t status;
+ bool success = false;
+
+ if (device.state != CONFIGURED)
+ {
+ /* Endpoint or interface must be zero */
+ if (transfer.setup.wIndex != 0)
+ {
+ return false;
+ }
+ }
+
+ switch (transfer.setup.bmRequestType.Recipient)
+ {
+ case DEVICE_RECIPIENT:
+ /* TODO: Currently only supports self powered devices */
+ status = DEVICE_STATUS_SELF_POWERED;
+ success = true;
+ break;
+ case INTERFACE_RECIPIENT:
+ status = 0;
+ success = true;
+ break;
+ case ENDPOINT_RECIPIENT:
+ /* TODO: We should check that the endpoint number is valid */
+ if (getEndpointStallState(
+ WINDEX_TO_PHYSICAL(transfer.setup.wIndex)))
+ {
+ status = ENDPOINT_STATUS_HALT;
+ }
+ else
+ {
+ status = 0;
+ }
+ success = true;
+ break;
+ default:
+ break;
+ }
+
+ if (success)
+ {
+ /* Send the status */
+ transfer.ptr = (uint8_t *)&status; /* Assumes little endian */
+ transfer.remaining = sizeof(status);
+ transfer.direction = DEVICE_TO_HOST;
+ }
+
+ return success;
+}
+
+bool USBDevice::requestSetup(void)
+{
+ bool success = false;
+
+ /* Process standard requests */
+ if ((transfer.setup.bmRequestType.Type == STANDARD_TYPE))
+ {
+ switch (transfer.setup.bRequest)
+ {
+ case GET_STATUS:
+ success = requestGetStatus();
+ break;
+ case CLEAR_FEATURE:
+ success = requestClearFeature();
+ break;
+ case SET_FEATURE:
+ success = requestSetFeature();
+ break;
+ case SET_ADDRESS:
+ success = requestSetAddress();
+ break;
+ case GET_DESCRIPTOR:
+ success = requestGetDescriptor();
+ break;
+ case SET_DESCRIPTOR:
+ /* TODO: Support is optional, not implemented here */
+ success = false;
+ break;
+ case GET_CONFIGURATION:
+ success = requestGetConfiguration();
+ break;
+ case SET_CONFIGURATION:
+ success = requestSetConfiguration();
+ break;
+ case GET_INTERFACE:
+ success = requestGetInterface();
+ break;
+ case SET_INTERFACE:
+ success = requestSetInterface();
+ break;
+ default:
+ break;
+ }
+ }
+
+ return success;
+}
+
+bool USBDevice::controlSetup(void)
+{
+ bool success = false;
+
+ /* Control transfer setup stage */
+ uint8_t buffer[MAX_PACKET_SIZE_EP0];
+
+ EP0setup(buffer);
+
+ /* Initialise control transfer state */
+ decodeSetupPacket(buffer, &transfer.setup);
+ transfer.ptr = NULL;
+ transfer.remaining = 0;
+ transfer.direction = 0;
+ transfer.zlp = false;
+ transfer.notify = false;
+
+#ifdef DEBUG
+ printf("dataTransferDirection: %d\r\nType: %d\r\nRecipient: %d\r\nbRequest: %d\r\nwValue: %d\r\nwIndex: %d\r\nwLength: %d\r\n",transfer.setup.bmRequestType.dataTransferDirection,
+ transfer.setup.bmRequestType.Type,
+ transfer.setup.bmRequestType.Recipient,
+ transfer.setup.bRequest,
+ transfer.setup.wValue,
+ transfer.setup.wIndex,
+ transfer.setup.wLength);
+#endif
+
+ /* Class / vendor specific */
+ success = USBCallback_request();
+
+ if (!success)
+ {
+ /* Standard requests */
+ if (!requestSetup())
+ {
+#ifdef DEBUG
+ printf("fail!!!!\r\n");
+#endif
+ return false;
+ }
+ }
+
+ /* Check transfer size and direction */
+ if (transfer.setup.wLength>0)
+ {
+ if (transfer.setup.bmRequestType.dataTransferDirection \
+ == DEVICE_TO_HOST)
+ {
+ /* IN data stage is required */
+ if (transfer.direction != DEVICE_TO_HOST)
+ {
+ return false;
+ }
+
+ /* Transfer must be less than or equal to the size */
+ /* requested by the host */
+ if (transfer.remaining > transfer.setup.wLength)
+ {
+ transfer.remaining = transfer.setup.wLength;
+ }
+ }
+ else
+ {
+
+ /* OUT data stage is required */
+ if (transfer.direction != HOST_TO_DEVICE)
+ {
+ return false;
+ }
+
+ /* Transfer must be equal to the size requested by the host */
+ if (transfer.remaining != transfer.setup.wLength)
+ {
+ return false;
+ }
+ }
+ }
+ else
+ {
+ /* No data stage; transfer size must be zero */
+ if (transfer.remaining != 0)
+ {
+ return false;
+ }
+ }
+
+ /* Data or status stage if applicable */
+ if (transfer.setup.wLength>0)
+ {
+ if (transfer.setup.bmRequestType.dataTransferDirection \
+ == DEVICE_TO_HOST)
+ {
+ /* Check if we'll need to send a zero length packet at */
+ /* the end of this transfer */
+ if (transfer.setup.wLength > transfer.remaining)
+ {
+ /* Device wishes to transfer less than host requested */
+ if ((transfer.remaining % MAX_PACKET_SIZE_EP0) == 0)
+ {
+ /* Transfer is a multiple of EP0 max packet size */
+ transfer.zlp = true;
+ }
+ }
+
+ /* IN stage */
+ controlIn();
+ }
+ else
+ {
+ /* OUT stage */
+ EP0read();
+ }
+ }
+ else
+ {
+ /* Status stage */
+ EP0write(NULL, 0);
+ }
+
+ return true;
+}
+
+void USBDevice::busReset(void)
+{
+ device.state = DEFAULT;
+ device.configuration = 0;
+ device.suspended = false;
+
+ /* Call class / vendor specific busReset function */
+ USBCallback_busReset();
+}
+
+void USBDevice::EP0setupCallback(void)
+{
+ /* Endpoint 0 setup event */
+ if (!controlSetup())
+ {
+ /* Protocol stall */
+ EP0stall();
+ }
+
+ /* Return true if an OUT data stage is expected */
+}
+
+void USBDevice::EP0out(void)
+{
+ /* Endpoint 0 OUT data event */
+ if (!controlOut())
+ {
+ /* Protocol stall; this will stall both endpoints */
+ EP0stall();
+ }
+}
+
+void USBDevice::EP0in(void)
+{
+#ifdef DEBUG
+ printf("EP0IN\r\n");
+#endif
+ /* Endpoint 0 IN data event */
+ if (!controlIn())
+ {
+ /* Protocol stall; this will stall both endpoints */
+ EP0stall();
+ }
+}
+
+bool USBDevice::configured(void)
+{
+ /* Returns true if device is in the CONFIGURED state */
+ return (device.state == CONFIGURED);
+}
+
+void USBDevice::connect(bool blocking)
+{
+ /* Connect device */
+ USBHAL::connect();
+
+ if (blocking) {
+ /* Block if not configured */
+ while (!configured());
+ }
+}
+
+void USBDevice::disconnect(void)
+{
+ /* Disconnect device */
+ USBHAL::disconnect();
+
+ /* Set initial device state */
+ device.state = POWERED;
+ device.configuration = 0;
+ device.suspended = false;
+}
+
+CONTROL_TRANSFER * USBDevice::getTransferPtr(void)
+{
+ return &transfer;
+}
+
+bool USBDevice::addEndpoint(uint8_t endpoint, uint32_t maxPacket)
+{
+ return realiseEndpoint(endpoint, maxPacket, 0);
+}
+
+bool USBDevice::addRateFeedbackEndpoint(uint8_t endpoint, uint32_t maxPacket)
+{
+ /* For interrupt endpoints only */
+ return realiseEndpoint(endpoint, maxPacket, RATE_FEEDBACK_MODE);
+}
+
+uint8_t * USBDevice::findDescriptor(uint8_t descriptorType)
+{
+ /* Find a descriptor within the list of descriptors */
+ /* following a configuration descriptor. */
+ uint16_t wTotalLength;
+ uint8_t *ptr;
+
+ if (configurationDesc() == NULL)
+ {
+ return NULL;
+ }
+
+ /* Check this is a configuration descriptor */
+ if ((configurationDesc()[0] != CONFIGURATION_DESCRIPTOR_LENGTH) \
+ || (configurationDesc()[1] != CONFIGURATION_DESCRIPTOR))
+ {
+ return NULL;
+ }
+
+ wTotalLength = configurationDesc()[2] | (configurationDesc()[3] << 8);
+
+ /* Check there are some more descriptors to follow */
+ if (wTotalLength <= (CONFIGURATION_DESCRIPTOR_LENGTH+2))
+ /* +2 is for bLength and bDescriptorType of next descriptor */
+ {
+ return NULL;
+ }
+
+ /* Start at first descriptor after the configuration descriptor */
+ ptr = &(configurationDesc()[CONFIGURATION_DESCRIPTOR_LENGTH]);
+
+ do {
+ if (ptr[1] /* bDescriptorType */ == descriptorType)
+ {
+ /* Found */
+ return ptr;
+ }
+
+ /* Skip to next descriptor */
+ ptr += ptr[0]; /* bLength */
+ } while (ptr < (configurationDesc() + wTotalLength));
+
+ /* Reached end of the descriptors - not found */
+ return NULL;
+}
+
+
+void USBDevice::connectStateChanged(unsigned int connected)
+{
+}
+
+void USBDevice::suspendStateChanged(unsigned int suspended)
+{
+}
+
+
+USBDevice::USBDevice(uint16_t vendor_id, uint16_t product_id, uint16_t product_release){
+ VENDOR_ID = vendor_id;
+ PRODUCT_ID = product_id;
+ PRODUCT_RELEASE = product_release;
+
+ /* Set initial device state */
+ device.state = POWERED;
+ device.configuration = 0;
+ device.suspended = false;
+};
+
+
+bool USBDevice::readStart(uint8_t endpoint, uint32_t maxSize)
+{
+ return endpointRead(endpoint, maxSize) == EP_PENDING;
+}
+
+
+bool USBDevice::write(uint8_t endpoint, uint8_t * buffer, uint32_t size, uint32_t maxSize)
+{
+ EP_STATUS result;
+
+ if (size > maxSize)
+ {
+ return false;
+ }
+
+
+ if(!configured()) {
+ return false;
+ }
+
+ /* Send report */
+ result = endpointWrite(endpoint, buffer, size);
+
+ if (result != EP_PENDING)
+ {
+ return false;
+ }
+
+ /* Wait for completion */
+ do {
+ result = endpointWriteResult(endpoint);
+ } while ((result == EP_PENDING) && configured());
+
+ return (result == EP_COMPLETED);
+}
+
+
+bool USBDevice::writeNB(uint8_t endpoint, uint8_t * buffer, uint32_t size, uint32_t maxSize)
+{
+ EP_STATUS result;
+
+ if (size > maxSize)
+ {
+ return false;
+ }
+
+ if(!configured()) {
+ return false;
+ }
+
+ /* Send report */
+ result = endpointWrite(endpoint, buffer, size);
+
+ if (result != EP_PENDING)
+ {
+ return false;
+ }
+
+ result = endpointWriteResult(endpoint);
+
+ return (result == EP_COMPLETED);
+}
+
+
+
+bool USBDevice::readEP(uint8_t endpoint, uint8_t * buffer, uint32_t * size, uint32_t maxSize)
+{
+ EP_STATUS result;
+
+ if(!configured()) {
+ return false;
+ }
+
+ /* Wait for completion */
+ do {
+ result = endpointReadResult(endpoint, buffer, size);
+ } while ((result == EP_PENDING) && configured());
+
+ return (result == EP_COMPLETED);
+}
+
+
+bool USBDevice::readEP_NB(uint8_t endpoint, uint8_t * buffer, uint32_t * size, uint32_t maxSize)
+{
+ EP_STATUS result;
+
+ if(!configured()) {
+ return false;
+ }
+
+ result = endpointReadResult(endpoint, buffer, size);
+
+ return (result == EP_COMPLETED);
+}
+
+
+
+uint8_t * USBDevice::deviceDesc() {
+ static uint8_t deviceDescriptor[] = {
+ DEVICE_DESCRIPTOR_LENGTH, /* bLength */
+ DEVICE_DESCRIPTOR, /* bDescriptorType */
+ LSB(USB_VERSION_2_0), /* bcdUSB (LSB) */
+ MSB(USB_VERSION_2_0), /* bcdUSB (MSB) */
+ 0x00, /* bDeviceClass */
+ 0x00, /* bDeviceSubClass */
+ 0x00, /* bDeviceprotocol */
+ MAX_PACKET_SIZE_EP0, /* bMaxPacketSize0 */
+ (uint8_t)(LSB(VENDOR_ID)), /* idVendor (LSB) */
+ (uint8_t)(MSB(VENDOR_ID)), /* idVendor (MSB) */
+ (uint8_t)(LSB(PRODUCT_ID)), /* idProduct (LSB) */
+ (uint8_t)(MSB(PRODUCT_ID)), /* idProduct (MSB) */
+ (uint8_t)(LSB(PRODUCT_RELEASE)), /* bcdDevice (LSB) */
+ (uint8_t)(MSB(PRODUCT_RELEASE)), /* bcdDevice (MSB) */
+ STRING_OFFSET_IMANUFACTURER, /* iManufacturer */
+ STRING_OFFSET_IPRODUCT, /* iProduct */
+ STRING_OFFSET_ISERIAL, /* iSerialNumber */
+ 0x01 /* bNumConfigurations */
+ };
+ return deviceDescriptor;
+}
+
+uint8_t * USBDevice::stringLangidDesc() {
+ static uint8_t stringLangidDescriptor[] = {
+ 0x04, /*bLength*/
+ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/
+ 0x09,0x04, /*bString Lang ID - 0x0409 - English*/
+ };
+ return stringLangidDescriptor;
+}
+
+uint8_t * USBDevice::stringImanufacturerDesc() {
+ static uint8_t stringImanufacturerDescriptor[] = {
+ 0x12, /*bLength*/
+ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/
+ 'm',0,'b',0,'e',0,'d',0,'.',0,'o',0,'r',0,'g',0, /*bString iManufacturer - mbed.org*/
+ };
+ return stringImanufacturerDescriptor;
+}
+
+uint8_t * USBDevice::stringIserialDesc() {
+ static uint8_t stringIserialDescriptor[] = {
+ 0x16, /*bLength*/
+ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/
+ '0',0,'1',0,'2',0,'3',0,'4',0,'5',0,'6',0,'7',0,'8',0,'9',0, /*bString iSerial - 0123456789*/
+ };
+ return stringIserialDescriptor;
+}
+
+uint8_t * USBDevice::stringIConfigurationDesc() {
+ static uint8_t stringIconfigurationDescriptor[] = {
+ 0x06, /*bLength*/
+ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/
+ '0',0,'1',0, /*bString iConfiguration - 01*/
+ };
+ return stringIconfigurationDescriptor;
+}
+
+uint8_t * USBDevice::stringIinterfaceDesc() {
+ static uint8_t stringIinterfaceDescriptor[] = {
+ 0x08, /*bLength*/
+ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/
+ 'U',0,'S',0,'B',0, /*bString iInterface - USB*/
+ };
+ return stringIinterfaceDescriptor;
+}
+
+uint8_t * USBDevice::stringIproductDesc() {
+ static uint8_t stringIproductDescriptor[] = {
+ 0x16, /*bLength*/
+ STRING_DESCRIPTOR, /*bDescriptorType 0x03*/
+ 'U',0,'S',0,'B',0,' ',0,'D',0,'E',0,'V',0,'I',0,'C',0,'E',0 /*bString iProduct - USB DEVICE*/
+ };
+ return stringIproductDescriptor;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice.h
new file mode 100644
index 000000000..a25ca1adf
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice.h
@@ -0,0 +1,271 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBDEVICE_H
+#define USBDEVICE_H
+
+#include "mbed.h"
+#include "USBDevice_Types.h"
+#include "USBHAL.h"
+
+class USBDevice: public USBHAL
+{
+public:
+ USBDevice(uint16_t vendor_id, uint16_t product_id, uint16_t product_release);
+
+ /*
+ * Check if the device is configured
+ *
+ * @returns true if configured, false otherwise
+ */
+ bool configured(void);
+
+ /*
+ * Connect a device
+ *
+ * @param blocking: block if not configured
+ */
+ void connect(bool blocking = true);
+
+ /*
+ * Disconnect a device
+ */
+ void disconnect(void);
+
+ /*
+ * Add an endpoint
+ *
+ * @param endpoint endpoint which will be added
+ * @param maxPacket Maximum size of a packet which can be sent for this endpoint
+ * @returns true if successful, false otherwise
+ */
+ bool addEndpoint(uint8_t endpoint, uint32_t maxPacket);
+
+ /*
+ * Start a reading on a certain endpoint.
+ * You can access the result of the reading by USBDevice_read
+ *
+ * @param endpoint endpoint which will be read
+ * @param maxSize the maximum length that can be read
+ * @return true if successful
+ */
+ bool readStart(uint8_t endpoint, uint32_t maxSize);
+
+ /*
+ * Read a certain endpoint. Before calling this function, USBUSBDevice_readStart
+ * must be called.
+ *
+ * Warning: blocking
+ *
+ * @param endpoint endpoint which will be read
+ * @param buffer buffer will be filled with the data received
+ * @param size the number of bytes read will be stored in *size
+ * @param maxSize the maximum length that can be read
+ * @returns true if successful
+ */
+ bool readEP(uint8_t endpoint, uint8_t * buffer, uint32_t * size, uint32_t maxSize);
+
+ /*
+ * Read a certain endpoint.
+ *
+ * Warning: non blocking
+ *
+ * @param endpoint endpoint which will be read
+ * @param buffer buffer will be filled with the data received (if data are available)
+ * @param size the number of bytes read will be stored in *size
+ * @param maxSize the maximum length that can be read
+ * @returns true if successful
+ */
+ bool readEP_NB(uint8_t endpoint, uint8_t * buffer, uint32_t * size, uint32_t maxSize);
+
+ /*
+ * Write a certain endpoint.
+ *
+ * Warning: blocking
+ *
+ * @param endpoint endpoint to write
+ * @param buffer data contained in buffer will be write
+ * @param size the number of bytes to write
+ * @param maxSize the maximum length that can be written on this endpoint
+ */
+ bool write(uint8_t endpoint, uint8_t * buffer, uint32_t size, uint32_t maxSize);
+
+
+ /*
+ * Write a certain endpoint.
+ *
+ * Warning: non blocking
+ *
+ * @param endpoint endpoint to write
+ * @param buffer data contained in buffer will be write
+ * @param size the number of bytes to write
+ * @param maxSize the maximum length that can be written on this endpoint
+ */
+ bool writeNB(uint8_t endpoint, uint8_t * buffer, uint32_t size, uint32_t maxSize);
+
+
+ /*
+ * Called by USBDevice layer on bus reset. Warning: Called in ISR context
+ *
+ * May be used to reset state
+ */
+ virtual void USBCallback_busReset(void) {};
+
+ /*
+ * Called by USBDevice on Endpoint0 request. Warning: Called in ISR context
+ * This is used to handle extensions to standard requests
+ * and class specific requests
+ *
+ * @returns true if class handles this request
+ */
+ virtual bool USBCallback_request() { return false; };
+
+ /*
+ * Called by USBDevice on Endpoint0 request completion
+ * if the 'notify' flag has been set to true. Warning: Called in ISR context
+ *
+ * In this case it is used to indicate that a HID report has
+ * been received from the host on endpoint 0
+ *
+ * @param buf buffer received on endpoint 0
+ * @param length length of this buffer
+ */
+ virtual void USBCallback_requestCompleted(uint8_t * buf, uint32_t length) {};
+
+ /*
+ * Called by USBDevice layer. Set configuration of the device.
+ * For instance, you can add all endpoints that you need on this function.
+ *
+ * @param configuration Number of the configuration
+ */
+ virtual bool USBCallback_setConfiguration(uint8_t configuration) { return false; };
+
+ /*
+ * Called by USBDevice layer. Set interface/alternate of the device.
+ *
+ * @param interface Number of the interface to be configured
+ * @param alternate Number of the alternate to be configured
+ * @returns true if class handles this request
+ */
+ virtual bool USBCallback_setInterface(uint16_t interface, uint8_t alternate) { return false; };
+
+ /*
+ * Get device descriptor. Warning: this method has to store the length of the report descriptor in reportLength.
+ *
+ * @returns pointer to the device descriptor
+ */
+ virtual uint8_t * deviceDesc();
+
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc(){return NULL;};
+
+ /*
+ * Get string lang id descriptor
+ *
+ * @return pointer to the string lang id descriptor
+ */
+ virtual uint8_t * stringLangidDesc();
+
+ /*
+ * Get string manufacturer descriptor
+ *
+ * @returns pointer to the string manufacturer descriptor
+ */
+ virtual uint8_t * stringImanufacturerDesc();
+
+ /*
+ * Get string product descriptor
+ *
+ * @returns pointer to the string product descriptor
+ */
+ virtual uint8_t * stringIproductDesc();
+
+ /*
+ * Get string serial descriptor
+ *
+ * @returns pointer to the string serial descriptor
+ */
+ virtual uint8_t * stringIserialDesc();
+
+ /*
+ * Get string configuration descriptor
+ *
+ * @returns pointer to the string configuration descriptor
+ */
+ virtual uint8_t * stringIConfigurationDesc();
+
+ /*
+ * Get string interface descriptor
+ *
+ * @returns pointer to the string interface descriptor
+ */
+ virtual uint8_t * stringIinterfaceDesc();
+
+ /*
+ * Get the length of the report descriptor
+ *
+ * @returns length of the report descriptor
+ */
+ virtual uint16_t reportDescLength() { return 0; };
+
+
+
+protected:
+ virtual void busReset(void);
+ virtual void EP0setupCallback(void);
+ virtual void EP0out(void);
+ virtual void EP0in(void);
+ virtual void connectStateChanged(unsigned int connected);
+ virtual void suspendStateChanged(unsigned int suspended);
+ uint8_t * findDescriptor(uint8_t descriptorType);
+ CONTROL_TRANSFER * getTransferPtr(void);
+
+ uint16_t VENDOR_ID;
+ uint16_t PRODUCT_ID;
+ uint16_t PRODUCT_RELEASE;
+
+private:
+ bool addRateFeedbackEndpoint(uint8_t endpoint, uint32_t maxPacket);
+ bool requestGetDescriptor(void);
+ bool controlOut(void);
+ bool controlIn(void);
+ bool requestSetAddress(void);
+ bool requestSetConfiguration(void);
+ bool requestSetFeature(void);
+ bool requestClearFeature(void);
+ bool requestGetStatus(void);
+ bool requestSetup(void);
+ bool controlSetup(void);
+ void decodeSetupPacket(uint8_t *data, SETUP_PACKET *packet);
+ bool requestGetConfiguration(void);
+ bool requestGetInterface(void);
+ bool requestSetInterface(void);
+
+ CONTROL_TRANSFER transfer;
+ USB_DEVICE device;
+
+ uint16_t currentInterface;
+ uint8_t currentAlternate;
+};
+
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice_Types.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice_Types.h
new file mode 100644
index 000000000..19bc1c2f3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBDevice_Types.h
@@ -0,0 +1,83 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBDEVICE_TYPES_H
+#define USBDEVICE_TYPES_H
+
+/* Standard requests */
+#define GET_STATUS (0)
+#define CLEAR_FEATURE (1)
+#define SET_FEATURE (3)
+#define SET_ADDRESS (5)
+#define GET_DESCRIPTOR (6)
+#define SET_DESCRIPTOR (7)
+#define GET_CONFIGURATION (8)
+#define SET_CONFIGURATION (9)
+#define GET_INTERFACE (10)
+#define SET_INTERFACE (11)
+
+/* bmRequestType.dataTransferDirection */
+#define HOST_TO_DEVICE (0)
+#define DEVICE_TO_HOST (1)
+
+/* bmRequestType.Type*/
+#define STANDARD_TYPE (0)
+#define CLASS_TYPE (1)
+#define VENDOR_TYPE (2)
+#define RESERVED_TYPE (3)
+
+/* bmRequestType.Recipient */
+#define DEVICE_RECIPIENT (0)
+#define INTERFACE_RECIPIENT (1)
+#define ENDPOINT_RECIPIENT (2)
+#define OTHER_RECIPIENT (3)
+
+/* Descriptors */
+#define DESCRIPTOR_TYPE(wValue) (wValue >> 8)
+#define DESCRIPTOR_INDEX(wValue) (wValue & 0xff)
+
+typedef struct {
+ struct {
+ uint8_t dataTransferDirection;
+ uint8_t Type;
+ uint8_t Recipient;
+ } bmRequestType;
+ uint8_t bRequest;
+ uint16_t wValue;
+ uint16_t wIndex;
+ uint16_t wLength;
+} SETUP_PACKET;
+
+typedef struct {
+ SETUP_PACKET setup;
+ uint8_t *ptr;
+ uint32_t remaining;
+ uint8_t direction;
+ bool zlp;
+ bool notify;
+} CONTROL_TRANSFER;
+
+typedef enum {ATTACHED, POWERED, DEFAULT, ADDRESS, CONFIGURED} DEVICE_STATE;
+
+typedef struct {
+ volatile DEVICE_STATE state;
+ uint8_t configuration;
+ bool suspended;
+} USB_DEVICE;
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints.h
new file mode 100644
index 000000000..48950986a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints.h
@@ -0,0 +1,56 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBENDPOINTS_H
+#define USBENDPOINTS_H
+
+/* SETUP packet size */
+#define SETUP_PACKET_SIZE (8)
+
+/* Options flags for configuring endpoints */
+#define DEFAULT_OPTIONS (0)
+#define SINGLE_BUFFERED (1U << 0)
+#define ISOCHRONOUS (1U << 1)
+#define RATE_FEEDBACK_MODE (1U << 2) /* Interrupt endpoints only */
+
+/* Endpoint transfer status, for endpoints > 0 */
+typedef enum {
+ EP_COMPLETED, /* Transfer completed */
+ EP_PENDING, /* Transfer in progress */
+ EP_INVALID, /* Invalid parameter */
+ EP_STALLED, /* Endpoint stalled */
+} EP_STATUS;
+
+/* Include configuration for specific target */
+#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368) || defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
+#include "USBEndpoints_LPC17_LPC23.h"
+#elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X) || defined (TARGET_LPC1549)
+#include "USBEndpoints_LPC11U.h"
+#elif defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1)
+#include "USBEndpoints_KL25Z.h"
+#elif defined (TARGET_STM32F4)
+#include "USBEndpoints_STM32F4.h"
+#elif defined (TARGET_RZ_A1H)
+#include "USBEndpoints_RZ_A1H.h"
+#elif defined(TARGET_Maxim)
+#include "USBEndpoints_Maxim.h"
+#else
+#error "Unknown target type"
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h
new file mode 100644
index 000000000..87721a21c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_KL25Z.h
@@ -0,0 +1,99 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#define NUMBER_OF_LOGICAL_ENDPOINTS (16)
+#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
+
+/* Define physical endpoint numbers */
+
+/* Endpoint No. */
+/* ---------------- */
+#define EP0OUT (0)
+#define EP0IN (1)
+#define EP1OUT (2)
+#define EP1IN (3)
+#define EP2OUT (4)
+#define EP2IN (5)
+#define EP3OUT (6)
+#define EP3IN (7)
+#define EP4OUT (8)
+#define EP4IN (9)
+#define EP5OUT (10)
+#define EP5IN (11)
+#define EP6OUT (12)
+#define EP6IN (13)
+#define EP7OUT (14)
+#define EP7IN (15)
+#define EP8OUT (16)
+#define EP8IN (17)
+#define EP9OUT (18)
+#define EP9IN (19)
+#define EP10OUT (20)
+#define EP10IN (21)
+#define EP11OUT (22)
+#define EP11IN (23)
+#define EP12OUT (24)
+#define EP12IN (25)
+#define EP13OUT (26)
+#define EP13IN (27)
+#define EP14OUT (28)
+#define EP14IN (29)
+#define EP15OUT (30)
+#define EP15IN (31)
+
+/* Maximum Packet sizes */
+
+#define MAX_PACKET_SIZE_EP0 (64)
+#define MAX_PACKET_SIZE_EP1 (64)
+#define MAX_PACKET_SIZE_EP2 (64)
+#define MAX_PACKET_SIZE_EP3 (1023)
+#define MAX_PACKET_SIZE_EP4 (64)
+#define MAX_PACKET_SIZE_EP5 (64)
+#define MAX_PACKET_SIZE_EP6 (64)
+#define MAX_PACKET_SIZE_EP7 (64)
+#define MAX_PACKET_SIZE_EP8 (64)
+#define MAX_PACKET_SIZE_EP9 (64)
+#define MAX_PACKET_SIZE_EP10 (64)
+#define MAX_PACKET_SIZE_EP11 (64)
+#define MAX_PACKET_SIZE_EP12 (64)
+#define MAX_PACKET_SIZE_EP13 (64)
+#define MAX_PACKET_SIZE_EP14 (64)
+#define MAX_PACKET_SIZE_EP15 (64)
+
+/* Generic endpoints - intended to be portable accross devices */
+/* and be suitable for simple USB devices. */
+
+/* Bulk endpoints */
+#define EPBULK_OUT (EP2OUT)
+#define EPBULK_IN (EP2IN)
+#define EPBULK_OUT_callback EP2_OUT_callback
+#define EPBULK_IN_callback EP2_IN_callback
+/* Interrupt endpoints */
+#define EPINT_OUT (EP1OUT)
+#define EPINT_IN (EP1IN)
+#define EPINT_OUT_callback EP1_OUT_callback
+#define EPINT_IN_callback EP1_IN_callback
+/* Isochronous endpoints */
+#define EPISO_OUT (EP3OUT)
+#define EPISO_IN (EP3IN)
+#define EPISO_OUT_callback EP3_OUT_callback
+#define EPISO_IN_callback EP3_IN_callback
+
+#define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2)
+#define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1)
+#define MAX_PACKET_SIZE_EPISO (MAX_PACKET_SIZE_EP3)
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h
new file mode 100644
index 000000000..b4ddaa514
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_LPC11U.h
@@ -0,0 +1,71 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#define NUMBER_OF_LOGICAL_ENDPOINTS (5)
+#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
+
+/* Define physical endpoint numbers */
+
+/* Endpoint No. Type(s) MaxPacket DoubleBuffer */
+/* ---------------- ------------ ---------- --- */
+#define EP0OUT (0) /* Control 64 No */
+#define EP0IN (1) /* Control 64 No */
+#define EP1OUT (2) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP1IN (3) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP2OUT (4) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP2IN (5) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP3OUT (6) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP3IN (7) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP4OUT (8) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP4IN (9) /* Int/Bulk/Iso 64/64/1023 Yes */
+
+/* Maximum Packet sizes */
+
+#define MAX_PACKET_SIZE_EP0 (64)
+#define MAX_PACKET_SIZE_EP1 (64) /* Int/Bulk */
+#define MAX_PACKET_SIZE_EP2 (64) /* Int/Bulk */
+#define MAX_PACKET_SIZE_EP3 (64) /* Int/Bulk */
+#define MAX_PACKET_SIZE_EP4 (64) /* Int/Bulk */
+
+#define MAX_PACKET_SIZE_EP1_ISO (1023) /* Isochronous */
+#define MAX_PACKET_SIZE_EP2_ISO (1023) /* Isochronous */
+#define MAX_PACKET_SIZE_EP3_ISO (1023) /* Isochronous */
+#define MAX_PACKET_SIZE_EP4_ISO (1023) /* Isochronous */
+
+/* Generic endpoints - intended to be portable accross devices */
+/* and be suitable for simple USB devices. */
+
+/* Bulk endpoint */
+#define EPBULK_OUT (EP2OUT)
+#define EPBULK_IN (EP2IN)
+#define EPBULK_OUT_callback EP2_OUT_callback
+#define EPBULK_IN_callback EP2_IN_callback
+/* Interrupt endpoint */
+#define EPINT_OUT (EP1OUT)
+#define EPINT_IN (EP1IN)
+#define EPINT_OUT_callback EP1_OUT_callback
+#define EPINT_IN_callback EP1_IN_callback
+/* Isochronous endpoint */
+#define EPISO_OUT (EP3OUT)
+#define EPISO_IN (EP3IN)
+#define EPISO_OUT_callback EP3_OUT_callback
+#define EPISO_IN_callback EP3_IN_callback
+
+#define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2)
+#define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1)
+#define MAX_PACKET_SIZE_EPISO (MAX_PACKET_SIZE_EP3_ISO)
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h
new file mode 100644
index 000000000..383b7e36f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_LPC17_LPC23.h
@@ -0,0 +1,99 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#define NUMBER_OF_LOGICAL_ENDPOINTS (16)
+#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
+
+/* Define physical endpoint numbers */
+
+/* Endpoint No. Type(s) MaxPacket DoubleBuffer */
+/* ---------------- ------------ ---------- --- */
+#define EP0OUT (0) /* Control 64 No */
+#define EP0IN (1) /* Control 64 No */
+#define EP1OUT (2) /* Interrupt 64 No */
+#define EP1IN (3) /* Interrupt 64 No */
+#define EP2OUT (4) /* Bulk 64 Yes */
+#define EP2IN (5) /* Bulk 64 Yes */
+#define EP3OUT (6) /* Isochronous 1023 Yes */
+#define EP3IN (7) /* Isochronous 1023 Yes */
+#define EP4OUT (8) /* Interrupt 64 No */
+#define EP4IN (9) /* Interrupt 64 No */
+#define EP5OUT (10) /* Bulk 64 Yes */
+#define EP5IN (11) /* Bulk 64 Yes */
+#define EP6OUT (12) /* Isochronous 1023 Yes */
+#define EP6IN (13) /* Isochronous 1023 Yes */
+#define EP7OUT (14) /* Interrupt 64 No */
+#define EP7IN (15) /* Interrupt 64 No */
+#define EP8OUT (16) /* Bulk 64 Yes */
+#define EP8IN (17) /* Bulk 64 Yes */
+#define EP9OUT (18) /* Isochronous 1023 Yes */
+#define EP9IN (19) /* Isochronous 1023 Yes */
+#define EP10OUT (20) /* Interrupt 64 No */
+#define EP10IN (21) /* Interrupt 64 No */
+#define EP11OUT (22) /* Bulk 64 Yes */
+#define EP11IN (23) /* Bulk 64 Yes */
+#define EP12OUT (24) /* Isochronous 1023 Yes */
+#define EP12IN (25) /* Isochronous 1023 Yes */
+#define EP13OUT (26) /* Interrupt 64 No */
+#define EP13IN (27) /* Interrupt 64 No */
+#define EP14OUT (28) /* Bulk 64 Yes */
+#define EP14IN (29) /* Bulk 64 Yes */
+#define EP15OUT (30) /* Bulk 64 Yes */
+#define EP15IN (31) /* Bulk 64 Yes */
+
+/* Maximum Packet sizes */
+
+#define MAX_PACKET_SIZE_EP0 (64)
+#define MAX_PACKET_SIZE_EP1 (64)
+#define MAX_PACKET_SIZE_EP2 (64)
+#define MAX_PACKET_SIZE_EP3 (1023)
+#define MAX_PACKET_SIZE_EP4 (64)
+#define MAX_PACKET_SIZE_EP5 (64)
+#define MAX_PACKET_SIZE_EP6 (1023)
+#define MAX_PACKET_SIZE_EP7 (64)
+#define MAX_PACKET_SIZE_EP8 (64)
+#define MAX_PACKET_SIZE_EP9 (1023)
+#define MAX_PACKET_SIZE_EP10 (64)
+#define MAX_PACKET_SIZE_EP11 (64)
+#define MAX_PACKET_SIZE_EP12 (1023)
+#define MAX_PACKET_SIZE_EP13 (64)
+#define MAX_PACKET_SIZE_EP14 (64)
+#define MAX_PACKET_SIZE_EP15 (64)
+
+/* Generic endpoints - intended to be portable accross devices */
+/* and be suitable for simple USB devices. */
+
+/* Bulk endpoints */
+#define EPBULK_OUT (EP2OUT)
+#define EPBULK_IN (EP2IN)
+#define EPBULK_OUT_callback EP2_OUT_callback
+#define EPBULK_IN_callback EP2_IN_callback
+/* Interrupt endpoints */
+#define EPINT_OUT (EP1OUT)
+#define EPINT_IN (EP1IN)
+#define EPINT_OUT_callback EP1_OUT_callback
+#define EPINT_IN_callback EP1_IN_callback
+/* Isochronous endpoints */
+#define EPISO_OUT (EP3OUT)
+#define EPISO_IN (EP3IN)
+#define EPISO_OUT_callback EP3_OUT_callback
+#define EPISO_IN_callback EP3_IN_callback
+
+#define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2)
+#define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1)
+#define MAX_PACKET_SIZE_EPISO (MAX_PACKET_SIZE_EP3)
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_Maxim.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_Maxim.h
new file mode 100644
index 000000000..5cd3905c9
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_Maxim.h
@@ -0,0 +1,90 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#define NUMBER_OF_LOGICAL_ENDPOINTS (8)
+#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
+
+#define DIR_OUT 0x00
+#define DIR_IN 0x01
+#define EP_NUM(ep) (ep >> 1)
+#define IN_EP(ep) (ep & DIR_IN)
+#define OUT_EP(ep) (!(ep & DIR_IN))
+
+/* Define physical endpoint numbers */
+
+/* Endpoint No. */
+/* ---------------- */
+#define EP0OUT ((0 << 1) | DIR_OUT)
+#define EP0IN ((0 << 1) | DIR_IN)
+#define EP1OUT ((1 << 1) | DIR_OUT)
+#define EP1IN ((1 << 1) | DIR_IN)
+#define EP2OUT ((2 << 1) | DIR_OUT)
+#define EP2IN ((2 << 1) | DIR_IN)
+#define EP3OUT ((3 << 1) | DIR_OUT)
+#define EP3IN ((3 << 1) | DIR_IN)
+#define EP4OUT ((4 << 1) | DIR_OUT)
+#define EP4IN ((4 << 1) | DIR_IN)
+#define EP5OUT ((5 << 1) | DIR_OUT)
+#define EP5IN ((5 << 1) | DIR_IN)
+#define EP6OUT ((6 << 1) | DIR_OUT)
+#define EP6IN ((6 << 1) | DIR_IN)
+#define EP7OUT ((7 << 1) | DIR_OUT)
+#define EP7IN ((7 << 1) | DIR_IN)
+
+/* Maximum Packet sizes */
+
+#define MAX_PACKET_SIZE_EP0 (64)
+#define MAX_PACKET_SIZE_EP1 (64)
+#define MAX_PACKET_SIZE_EP2 (64)
+#define MAX_PACKET_SIZE_EP3 (64)
+#define MAX_PACKET_SIZE_EP4 (64)
+#define MAX_PACKET_SIZE_EP5 (64)
+#define MAX_PACKET_SIZE_EP6 (64)
+#define MAX_PACKET_SIZE_EP7 (64)
+
+/* Generic endpoints - intended to be portable accross devices */
+/* and be suitable for simple USB devices. */
+
+/* Bulk endpoints */
+#define EPBULK_OUT (EP1OUT)
+#define EPBULK_IN (EP2IN)
+#define EPBULK_OUT_callback EP1_OUT_callback
+#define EPBULK_IN_callback EP2_IN_callback
+/* Interrupt endpoints */
+#define EPINT_OUT (EP3OUT)
+#define EPINT_IN (EP4IN)
+#define EPINT_OUT_callback EP3_OUT_callback
+#define EPINT_IN_callback EP4_IN_callback
+
+#define MAX_PACKET_SIZE_EPBULK (64)
+#define MAX_PACKET_SIZE_EPINT (64)
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h
new file mode 100644
index 000000000..f25a3d862
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_RZ_A1H.h
@@ -0,0 +1,85 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#define NUMBER_OF_LOGICAL_ENDPOINTS (16)
+#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
+
+/* Define physical endpoint numbers */
+
+/* Endpoint No. Type(s) MaxSiz DoubleBuf pipe */
+/* ---------------- --------- ------ --------- ---- */
+#define EP0OUT (0) /* Control 256 No 0 */
+#define EP0IN (1) /* Control 256 No 0 */
+#define EP1OUT (2) /* Int 64 No 6 */
+#define EP1IN (3) /* Int 64 No 7 */
+#define EP2OUT (4) /* Bulk 2048 Yes 3 */
+#define EP2IN (5) /* Bulk 2048 Yes 4 */
+#define EP3OUT (6) /* Bulk/Iso 2048 Yes 1 */
+#define EP3IN (7) /* Bulk/Iso 2048 Yes 2 */
+/*following EP is not configured in sample program*/
+#define EP6IN (8) /* Bulk 2048 Yes 5 */
+#define EP8IN (9) /* Int 64 No 8 */
+#define EP9IN (10) /* Bulk 512 Bulk 9 */
+#define EP10IN (11) /* Int/Bulk 2048 Bulk 10 */
+#define EP11IN (12) /* Bulk 2048 Yes 11 */
+#define EP12IN (13) /* Bulk 2048 Yes 12 */
+#define EP13IN (14) /* Bulk 2048 Yes 13 */
+#define EP14IN (15) /* Bulk 2048 Yes 14 */
+#define EP15IN (16) /* Bulk 2048 Yes 15 */
+
+/* Maximum Packet sizes */
+#define MAX_PACKET_SIZE_EP0 (64) /*pipe0/pipe0: control */
+#define MAX_PACKET_SIZE_EP1 (64) /*pipe6/pipe7: interrupt */
+#define MAX_PACKET_SIZE_EP2 (512) /*pipe3/pipe4: bulk */
+#define MAX_PACKET_SIZE_EP3 (512) /*pipe1/pipe2: isochronous */
+#define MAX_PACKET_SIZE_EP6 (64) /*pipe5: Note *1 */
+#define MAX_PACKET_SIZE_EP8 (64) /*pipe7: Note *1 */
+#define MAX_PACKET_SIZE_EP9 (512) /*pipe8: Note *1 */
+#define MAX_PACKET_SIZE_EP10 (512) /*pipe9: Note *1 */
+#define MAX_PACKET_SIZE_EP11 (512) /*pipe10: Note *1 */
+#define MAX_PACKET_SIZE_EP12 (512) /*pipe11: Note *1 */
+#define MAX_PACKET_SIZE_EP13 (512) /*pipe12: Note *1 */
+#define MAX_PACKET_SIZE_EP14 (512) /*pipe13: Note *1 */
+#define MAX_PACKET_SIZE_EP15 (512) /*pipe14: Note *1 */
+/* Note *1: This pipe is not configure in sample program */
+
+
+/* Generic endpoints - intended to be portable accross devices */
+/* and be suitable for simple USB devices. */
+
+/* Bulk endpoints */
+#define EPBULK_OUT (EP2OUT)
+#define EPBULK_IN (EP2IN)
+#define EPBULK_OUT_callback EP2_OUT_callback
+#define EPBULK_IN_callback EP2_IN_callback
+/* Interrupt endpoints */
+#define EPINT_OUT (EP1OUT)
+#define EPINT_IN (EP1IN)
+#define EPINT_OUT_callback EP1_OUT_callback
+#define EPINT_IN_callback EP1_IN_callback
+/* Isochronous endpoints */
+#define EPISO_OUT (EP3OUT)
+#define EPISO_IN (EP3IN)
+#define EPISO_OUT_callback EP3_OUT_callback
+#define EPISO_IN_callback EP3_IN_callback
+
+#define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2)
+#define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1)
+#define MAX_PACKET_SIZE_EPISO (MAX_PACKET_SIZE_EP3)
+
+/*EOF*/
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h
new file mode 100644
index 000000000..1d520d11c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h
@@ -0,0 +1,67 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#define NUMBER_OF_LOGICAL_ENDPOINTS (4)
+#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
+
+/* Define physical endpoint numbers */
+
+/* Endpoint No. Type(s) MaxPacket DoubleBuffer */
+/* ---------------- ------------ ---------- --- */
+#define EP0OUT (0) /* Control 64 No */
+#define EP0IN (1) /* Control 64 No */
+#define EP1OUT (2) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP1IN (3) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP2OUT (4) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP2IN (5) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP3OUT (6) /* Int/Bulk/Iso 64/64/1023 Yes */
+#define EP3IN (7) /* Int/Bulk/Iso 64/64/1023 Yes */
+
+/* Maximum Packet sizes */
+
+#define MAX_PACKET_SIZE_EP0 (64)
+#define MAX_PACKET_SIZE_EP1 (64) /* Int/Bulk */
+#define MAX_PACKET_SIZE_EP2 (64) /* Int/Bulk */
+#define MAX_PACKET_SIZE_EP3 (64) /* Int/Bulk */
+
+#define MAX_PACKET_SIZE_EP1_ISO (1023) /* Isochronous */
+#define MAX_PACKET_SIZE_EP2_ISO (1023) /* Isochronous */
+#define MAX_PACKET_SIZE_EP3_ISO (1023) /* Isochronous */
+
+/* Generic endpoints - intended to be portable accross devices */
+/* and be suitable for simple USB devices. */
+
+/* Bulk endpoint */
+#define EPBULK_OUT (EP2OUT)
+#define EPBULK_IN (EP2IN)
+#define EPBULK_OUT_callback EP2_OUT_callback
+#define EPBULK_IN_callback EP2_IN_callback
+/* Interrupt endpoint */
+#define EPINT_OUT (EP1OUT)
+#define EPINT_IN (EP1IN)
+#define EPINT_OUT_callback EP1_OUT_callback
+#define EPINT_IN_callback EP1_IN_callback
+/* Isochronous endpoint */
+#define EPISO_OUT (EP3OUT)
+#define EPISO_IN (EP3IN)
+#define EPISO_OUT_callback EP3_OUT_callback
+#define EPISO_IN_callback EP3_IN_callback
+
+#define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2)
+#define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1)
+#define MAX_PACKET_SIZE_EPISO (MAX_PACKET_SIZE_EP3_ISO)
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL.h
new file mode 100644
index 000000000..faf22e8d5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL.h
@@ -0,0 +1,121 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBBUSINTERFACE_H
+#define USBBUSINTERFACE_H
+
+#include "mbed.h"
+#include "USBEndpoints.h"
+#include "toolchain.h"
+
+//#ifdef __GNUC__
+//#define __packed __attribute__ ((__packed__))
+//#endif
+
+class USBHAL {
+public:
+ /* Configuration */
+ USBHAL();
+ ~USBHAL();
+ void connect(void);
+ void disconnect(void);
+ void configureDevice(void);
+ void unconfigureDevice(void);
+ void setAddress(uint8_t address);
+ void remoteWakeup(void);
+
+ /* Endpoint 0 */
+ void EP0setup(uint8_t *buffer);
+ void EP0read(void);
+ void EP0readStage(void);
+ uint32_t EP0getReadResult(uint8_t *buffer);
+ void EP0write(uint8_t *buffer, uint32_t size);
+ void EP0getWriteResult(void);
+ void EP0stall(void);
+
+ /* Other endpoints */
+ EP_STATUS endpointRead(uint8_t endpoint, uint32_t maximumSize);
+ EP_STATUS endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead);
+ EP_STATUS endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size);
+ EP_STATUS endpointWriteResult(uint8_t endpoint);
+ void stallEndpoint(uint8_t endpoint);
+ void unstallEndpoint(uint8_t endpoint);
+ bool realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options);
+ bool getEndpointStallState(unsigned char endpoint);
+ uint32_t endpointReadcore(uint8_t endpoint, uint8_t *buffer);
+
+protected:
+ virtual void busReset(void){};
+ virtual void EP0setupCallback(void){};
+ virtual void EP0out(void){};
+ virtual void EP0in(void){};
+ virtual void connectStateChanged(unsigned int connected){};
+ virtual void suspendStateChanged(unsigned int suspended){};
+ virtual void SOF(int frameNumber){};
+
+ virtual bool EP1_OUT_callback(){return false;};
+ virtual bool EP1_IN_callback(){return false;};
+ virtual bool EP2_OUT_callback(){return false;};
+ virtual bool EP2_IN_callback(){return false;};
+ virtual bool EP3_OUT_callback(){return false;};
+ virtual bool EP3_IN_callback(){return false;};
+#if !defined(TARGET_STM32F4)
+ virtual bool EP4_OUT_callback(){return false;};
+ virtual bool EP4_IN_callback(){return false;};
+#if !(defined(TARGET_LPC11UXX) || defined(TARGET_LPC11U6X) || defined(TARGET_LPC1347) || defined(TARGET_LPC1549))
+ virtual bool EP5_OUT_callback(){return false;};
+ virtual bool EP5_IN_callback(){return false;};
+ virtual bool EP6_OUT_callback(){return false;};
+ virtual bool EP6_IN_callback(){return false;};
+ virtual bool EP7_OUT_callback(){return false;};
+ virtual bool EP7_IN_callback(){return false;};
+ virtual bool EP8_OUT_callback(){return false;};
+ virtual bool EP8_IN_callback(){return false;};
+ virtual bool EP9_OUT_callback(){return false;};
+ virtual bool EP9_IN_callback(){return false;};
+ virtual bool EP10_OUT_callback(){return false;};
+ virtual bool EP10_IN_callback(){return false;};
+ virtual bool EP11_OUT_callback(){return false;};
+ virtual bool EP11_IN_callback(){return false;};
+ virtual bool EP12_OUT_callback(){return false;};
+ virtual bool EP12_IN_callback(){return false;};
+ virtual bool EP13_OUT_callback(){return false;};
+ virtual bool EP13_IN_callback(){return false;};
+ virtual bool EP14_OUT_callback(){return false;};
+ virtual bool EP14_IN_callback(){return false;};
+ virtual bool EP15_OUT_callback(){return false;};
+ virtual bool EP15_IN_callback(){return false;};
+#endif
+#endif
+
+private:
+ void usbisr(void);
+ static void _usbisr(void);
+ static USBHAL * instance;
+
+#if defined(TARGET_LPC11UXX) || defined(TARGET_LPC11U6X) || defined(TARGET_LPC1347) || defined(TARGET_LPC1549)
+ bool (USBHAL::*epCallback[10 - 2])(void);
+#elif defined(TARGET_STM32F4)
+ bool (USBHAL::*epCallback[8 - 2])(void);
+#else
+ bool (USBHAL::*epCallback[32 - 2])(void);
+#endif
+
+
+};
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp
new file mode 100644
index 000000000..f92a99979
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp
@@ -0,0 +1,551 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1)
+
+#include "USBHAL.h"
+
+USBHAL * USBHAL::instance;
+
+static volatile int epComplete = 0;
+
+// Convert physical endpoint number to register bit
+#define EP(endpoint) (1<<(endpoint))
+
+// Convert physical to logical
+#define PHY_TO_LOG(endpoint) ((endpoint)>>1)
+
+// Get endpoint direction
+#define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
+#define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
+
+#define BD_OWN_MASK (1<<7)
+#define BD_DATA01_MASK (1<<6)
+#define BD_KEEP_MASK (1<<5)
+#define BD_NINC_MASK (1<<4)
+#define BD_DTS_MASK (1<<3)
+#define BD_STALL_MASK (1<<2)
+
+#define TX 1
+#define RX 0
+#define ODD 0
+#define EVEN 1
+// this macro waits a physical endpoint number
+#define EP_BDT_IDX(ep, dir, odd) (((ep * 4) + (2 * dir) + (1 * odd)))
+
+#define SETUP_TOKEN 0x0D
+#define IN_TOKEN 0x09
+#define OUT_TOKEN 0x01
+#define TOK_PID(idx) ((bdt[idx].info >> 2) & 0x0F)
+
+// for each endpt: 8 bytes
+typedef struct BDT {
+ uint8_t info; // BD[0:7]
+ uint8_t dummy; // RSVD: BD[8:15]
+ uint16_t byte_count; // BD[16:32]
+ uint32_t address; // Addr
+} BDT;
+
+
+// there are:
+// * 16 bidirectionnal endpt -> 32 physical endpt
+// * as there are ODD and EVEN buffer -> 32*2 bdt
+__attribute__((__aligned__(512))) BDT bdt[NUMBER_OF_PHYSICAL_ENDPOINTS * 2];
+uint8_t * endpoint_buffer[(NUMBER_OF_PHYSICAL_ENDPOINTS - 2) * 2];
+uint8_t * endpoint_buffer_iso[2*2];
+
+static uint8_t set_addr = 0;
+static uint8_t addr = 0;
+
+static uint32_t Data1 = 0x55555555;
+
+static uint32_t frameNumber() {
+ return((USB0->FRMNUML | (USB0->FRMNUMH << 8)) & 0x07FF);
+}
+
+uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
+ return 0;
+}
+
+USBHAL::USBHAL(void) {
+ // Disable IRQ
+ NVIC_DisableIRQ(USB0_IRQn);
+
+#if defined(TARGET_K64F)
+ MPU->CESR=0;
+#endif
+ // fill in callback array
+ epCallback[0] = &USBHAL::EP1_OUT_callback;
+ epCallback[1] = &USBHAL::EP1_IN_callback;
+ epCallback[2] = &USBHAL::EP2_OUT_callback;
+ epCallback[3] = &USBHAL::EP2_IN_callback;
+ epCallback[4] = &USBHAL::EP3_OUT_callback;
+ epCallback[5] = &USBHAL::EP3_IN_callback;
+ epCallback[6] = &USBHAL::EP4_OUT_callback;
+ epCallback[7] = &USBHAL::EP4_IN_callback;
+ epCallback[8] = &USBHAL::EP5_OUT_callback;
+ epCallback[9] = &USBHAL::EP5_IN_callback;
+ epCallback[10] = &USBHAL::EP6_OUT_callback;
+ epCallback[11] = &USBHAL::EP6_IN_callback;
+ epCallback[12] = &USBHAL::EP7_OUT_callback;
+ epCallback[13] = &USBHAL::EP7_IN_callback;
+ epCallback[14] = &USBHAL::EP8_OUT_callback;
+ epCallback[15] = &USBHAL::EP8_IN_callback;
+ epCallback[16] = &USBHAL::EP9_OUT_callback;
+ epCallback[17] = &USBHAL::EP9_IN_callback;
+ epCallback[18] = &USBHAL::EP10_OUT_callback;
+ epCallback[19] = &USBHAL::EP10_IN_callback;
+ epCallback[20] = &USBHAL::EP11_OUT_callback;
+ epCallback[21] = &USBHAL::EP11_IN_callback;
+ epCallback[22] = &USBHAL::EP12_OUT_callback;
+ epCallback[23] = &USBHAL::EP12_IN_callback;
+ epCallback[24] = &USBHAL::EP13_OUT_callback;
+ epCallback[25] = &USBHAL::EP13_IN_callback;
+ epCallback[26] = &USBHAL::EP14_OUT_callback;
+ epCallback[27] = &USBHAL::EP14_IN_callback;
+ epCallback[28] = &USBHAL::EP15_OUT_callback;
+ epCallback[29] = &USBHAL::EP15_IN_callback;
+
+#if defined(TARGET_KL43Z)
+ // enable USBFS clock
+ SIM->SCGC4 |= SIM_SCGC4_USBFS_MASK;
+
+ // enable the IRC48M clock
+ USB0->CLK_RECOVER_IRC_EN |= USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK;
+
+ // enable the USB clock recovery tuning
+ USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
+
+ // choose usb src clock
+ SIM->SOPT2 |= SIM_SOPT2_USBSRC_MASK;
+#else
+ // choose usb src as PLL
+ SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK;
+ SIM->SOPT2 |= (SIM_SOPT2_USBSRC_MASK | (1 << SIM_SOPT2_PLLFLLSEL_SHIFT));
+
+ // enable OTG clock
+ SIM->SCGC4 |= SIM_SCGC4_USBOTG_MASK;
+#endif
+
+ // Attach IRQ
+ instance = this;
+ NVIC_SetVector(USB0_IRQn, (uint32_t)&_usbisr);
+ NVIC_EnableIRQ(USB0_IRQn);
+
+ // USB Module Configuration
+ // Reset USB Module
+ USB0->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
+ while(USB0->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
+
+ // Set BDT Base Register
+ USB0->BDTPAGE1 = (uint8_t)((uint32_t)bdt>>8);
+ USB0->BDTPAGE2 = (uint8_t)((uint32_t)bdt>>16);
+ USB0->BDTPAGE3 = (uint8_t)((uint32_t)bdt>>24);
+
+ // Clear interrupt flag
+ USB0->ISTAT = 0xff;
+
+ // USB Interrupt Enablers
+ USB0->INTEN |= USB_INTEN_TOKDNEEN_MASK |
+ USB_INTEN_SOFTOKEN_MASK |
+ USB_INTEN_ERROREN_MASK |
+ USB_INTEN_USBRSTEN_MASK;
+
+ // Disable weak pull downs
+ USB0->USBCTRL &= ~(USB_USBCTRL_PDE_MASK | USB_USBCTRL_SUSP_MASK);
+
+ USB0->USBTRC0 |= 0x40;
+}
+
+USBHAL::~USBHAL(void) { }
+
+void USBHAL::connect(void) {
+ // enable USB
+ USB0->CTL |= USB_CTL_USBENSOFEN_MASK;
+ // Pull up enable
+ USB0->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK;
+}
+
+void USBHAL::disconnect(void) {
+ // disable USB
+ USB0->CTL &= ~USB_CTL_USBENSOFEN_MASK;
+ // Pull up disable
+ USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
+
+ //Free buffers if required:
+ for (int i = 0; i<(NUMBER_OF_PHYSICAL_ENDPOINTS - 2) * 2; i++) {
+ free(endpoint_buffer[i]);
+ endpoint_buffer[i] = NULL;
+ }
+ free(endpoint_buffer_iso[2]);
+ endpoint_buffer_iso[2] = NULL;
+ free(endpoint_buffer_iso[0]);
+ endpoint_buffer_iso[0] = NULL;
+}
+
+void USBHAL::configureDevice(void) {
+ // not needed
+}
+
+void USBHAL::unconfigureDevice(void) {
+ // not needed
+}
+
+void USBHAL::setAddress(uint8_t address) {
+ // we don't set the address now otherwise the usb controller does not ack
+ // we set a flag instead
+ // see usbisr when an IN token is received
+ set_addr = 1;
+ addr = address;
+}
+
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
+ uint32_t handshake_flag = 0;
+ uint8_t * buf;
+
+ if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
+ return false;
+ }
+
+ uint32_t log_endpoint = PHY_TO_LOG(endpoint);
+
+ if ((flags & ISOCHRONOUS) == 0) {
+ handshake_flag = USB_ENDPT_EPHSHK_MASK;
+ if (IN_EP(endpoint)) {
+ if (endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)] == NULL)
+ endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)] = (uint8_t *) malloc (64*2);
+ buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)][0];
+ } else {
+ if (endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)] == NULL)
+ endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)] = (uint8_t *) malloc (64*2);
+ buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)][0];
+ }
+ } else {
+ if (IN_EP(endpoint)) {
+ if (endpoint_buffer_iso[2] == NULL)
+ endpoint_buffer_iso[2] = (uint8_t *) malloc (1023*2);
+ buf = &endpoint_buffer_iso[2][0];
+ } else {
+ if (endpoint_buffer_iso[0] == NULL)
+ endpoint_buffer_iso[0] = (uint8_t *) malloc (1023*2);
+ buf = &endpoint_buffer_iso[0][0];
+ }
+ }
+
+ // IN endpt -> device to host (TX)
+ if (IN_EP(endpoint)) {
+ USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
+ USB_ENDPT_EPTXEN_MASK; // en TX (IN) tran
+ bdt[EP_BDT_IDX(log_endpoint, TX, ODD )].address = (uint32_t) buf;
+ bdt[EP_BDT_IDX(log_endpoint, TX, EVEN)].address = 0;
+ }
+ // OUT endpt -> host to device (RX)
+ else {
+ USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
+ USB_ENDPT_EPRXEN_MASK; // en RX (OUT) tran.
+ bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].byte_count = maxPacket;
+ bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].address = (uint32_t) buf;
+ bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info = BD_OWN_MASK | BD_DTS_MASK;
+ bdt[EP_BDT_IDX(log_endpoint, RX, EVEN)].info = 0;
+ }
+
+ Data1 |= (1 << endpoint);
+
+ return true;
+}
+
+// read setup packet
+void USBHAL::EP0setup(uint8_t *buffer) {
+ uint32_t sz;
+ endpointReadResult(EP0OUT, buffer, &sz);
+}
+
+void USBHAL::EP0readStage(void) {
+ Data1 &= ~1UL; // set DATA0
+ bdt[0].info = (BD_DTS_MASK | BD_OWN_MASK);
+}
+
+void USBHAL::EP0read(void) {
+ uint32_t idx = EP_BDT_IDX(PHY_TO_LOG(EP0OUT), RX, 0);
+ bdt[idx].byte_count = MAX_PACKET_SIZE_EP0;
+}
+
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
+ uint32_t sz;
+ endpointReadResult(EP0OUT, buffer, &sz);
+ return sz;
+}
+
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
+ endpointWrite(EP0IN, buffer, size);
+}
+
+void USBHAL::EP0getWriteResult(void) {
+}
+
+void USBHAL::EP0stall(void) {
+ stallEndpoint(EP0OUT);
+}
+
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
+ endpoint = PHY_TO_LOG(endpoint);
+ uint32_t idx = EP_BDT_IDX(endpoint, RX, 0);
+ bdt[idx].byte_count = maximumSize;
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
+ uint32_t n, sz, idx, setup = 0;
+ uint8_t not_iso;
+ uint8_t * ep_buf;
+
+ uint32_t log_endpoint = PHY_TO_LOG(endpoint);
+
+ if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
+ return EP_INVALID;
+ }
+
+ // if read on a IN endpoint -> error
+ if (IN_EP(endpoint)) {
+ return EP_INVALID;
+ }
+
+ idx = EP_BDT_IDX(log_endpoint, RX, 0);
+ sz = bdt[idx].byte_count;
+ not_iso = USB0->ENDPOINT[log_endpoint].ENDPT & USB_ENDPT_EPHSHK_MASK;
+
+ //for isochronous endpoint, we don't wait an interrupt
+ if ((log_endpoint != 0) && not_iso && !(epComplete & EP(endpoint))) {
+ return EP_PENDING;
+ }
+
+ if ((log_endpoint == 0) && (TOK_PID(idx) == SETUP_TOKEN)) {
+ setup = 1;
+ }
+
+ // non iso endpoint
+ if (not_iso) {
+ ep_buf = endpoint_buffer[idx];
+ } else {
+ ep_buf = endpoint_buffer_iso[0];
+ }
+
+ for (n = 0; n < sz; n++) {
+ buffer[n] = ep_buf[n];
+ }
+
+ if (((Data1 >> endpoint) & 1) == ((bdt[idx].info >> 6) & 1)) {
+ if (setup && (buffer[6] == 0)) // if no setup data stage,
+ Data1 &= ~1UL; // set DATA0
+ else
+ Data1 ^= (1 << endpoint);
+ }
+
+ if (((Data1 >> endpoint) & 1)) {
+ bdt[idx].info = BD_DTS_MASK | BD_DATA01_MASK | BD_OWN_MASK;
+ }
+ else {
+ bdt[idx].info = BD_DTS_MASK | BD_OWN_MASK;
+ }
+
+ USB0->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
+ *bytesRead = sz;
+
+ epComplete &= ~EP(endpoint);
+ return EP_COMPLETED;
+}
+
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
+ uint32_t idx, n;
+ uint8_t * ep_buf;
+
+ if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
+ return EP_INVALID;
+ }
+
+ // if write on a OUT endpoint -> error
+ if (OUT_EP(endpoint)) {
+ return EP_INVALID;
+ }
+
+ idx = EP_BDT_IDX(PHY_TO_LOG(endpoint), TX, 0);
+ bdt[idx].byte_count = size;
+
+
+ // non iso endpoint
+ if (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPHSHK_MASK) {
+ ep_buf = endpoint_buffer[idx];
+ } else {
+ ep_buf = endpoint_buffer_iso[2];
+ }
+
+ for (n = 0; n < size; n++) {
+ ep_buf[n] = data[n];
+ }
+
+ if ((Data1 >> endpoint) & 1) {
+ bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK;
+ } else {
+ bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK;
+ }
+
+ Data1 ^= (1 << endpoint);
+
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
+ if (epComplete & EP(endpoint)) {
+ epComplete &= ~EP(endpoint);
+ return EP_COMPLETED;
+ }
+
+ return EP_PENDING;
+}
+
+void USBHAL::stallEndpoint(uint8_t endpoint) {
+ USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT |= USB_ENDPT_EPSTALL_MASK;
+}
+
+void USBHAL::unstallEndpoint(uint8_t endpoint) {
+ USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
+}
+
+bool USBHAL::getEndpointStallState(uint8_t endpoint) {
+ uint8_t stall = (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPSTALL_MASK);
+ return (stall) ? true : false;
+}
+
+void USBHAL::remoteWakeup(void) {
+ // [TODO]
+}
+
+
+void USBHAL::_usbisr(void) {
+ instance->usbisr();
+}
+
+
+void USBHAL::usbisr(void) {
+ uint8_t i;
+ uint8_t istat = USB0->ISTAT;
+
+ // reset interrupt
+ if (istat & USB_ISTAT_USBRST_MASK) {
+ // disable all endpt
+ for(i = 0; i < 16; i++) {
+ USB0->ENDPOINT[i].ENDPT = 0x00;
+ }
+
+ // enable control endpoint
+ realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
+ realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
+
+ Data1 = 0x55555555;
+ USB0->CTL |= USB_CTL_ODDRST_MASK;
+
+ USB0->ISTAT = 0xFF; // clear all interrupt status flags
+ USB0->ERRSTAT = 0xFF; // clear all error flags
+ USB0->ERREN = 0xFF; // enable error interrupt sources
+ USB0->ADDR = 0x00; // set default address
+
+ return;
+ }
+
+ // resume interrupt
+ if (istat & USB_ISTAT_RESUME_MASK) {
+ USB0->ISTAT = USB_ISTAT_RESUME_MASK;
+ }
+
+ // SOF interrupt
+ if (istat & USB_ISTAT_SOFTOK_MASK) {
+ USB0->ISTAT = USB_ISTAT_SOFTOK_MASK;
+ // SOF event, read frame number
+ SOF(frameNumber());
+ }
+
+ // stall interrupt
+ if (istat & 1<<7) {
+ if (USB0->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK)
+ USB0->ENDPOINT[0].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
+ USB0->ISTAT |= USB_ISTAT_STALL_MASK;
+ }
+
+ // token interrupt
+ if (istat & 1<<3) {
+ uint32_t num = (USB0->STAT >> 4) & 0x0F;
+ uint32_t dir = (USB0->STAT >> 3) & 0x01;
+ uint32_t ev_odd = (USB0->STAT >> 2) & 0x01;
+
+ // setup packet
+ if ((num == 0) && (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == SETUP_TOKEN)) {
+ Data1 &= ~0x02;
+ bdt[EP_BDT_IDX(0, TX, EVEN)].info &= ~BD_OWN_MASK;
+ bdt[EP_BDT_IDX(0, TX, ODD)].info &= ~BD_OWN_MASK;
+
+ // EP0 SETUP event (SETUP data received)
+ EP0setupCallback();
+
+ } else {
+ // OUT packet
+ if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == OUT_TOKEN) {
+ if (num == 0)
+ EP0out();
+ else {
+ epComplete |= (1 << EP(num));
+ if ((instance->*(epCallback[EP(num) - 2]))()) {
+ epComplete &= ~(1 << EP(num));
+ }
+ }
+ }
+
+ // IN packet
+ if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == IN_TOKEN) {
+ if (num == 0) {
+ EP0in();
+ if (set_addr == 1) {
+ USB0->ADDR = addr & 0x7F;
+ set_addr = 0;
+ }
+ }
+ else {
+ epComplete |= (1 << (EP(num) + 1));
+ if ((instance->*(epCallback[EP(num) + 1 - 2]))()) {
+ epComplete &= ~(1 << (EP(num) + 1));
+ }
+ }
+ }
+ }
+
+ USB0->ISTAT = USB_ISTAT_TOKDNE_MASK;
+ }
+
+ // sleep interrupt
+ if (istat & 1<<4) {
+ USB0->ISTAT |= USB_ISTAT_SLEEP_MASK;
+ }
+
+ // error interrupt
+ if (istat & USB_ISTAT_ERROR_MASK) {
+ USB0->ERRSTAT = 0xFF;
+ USB0->ISTAT |= USB_ISTAT_ERROR_MASK;
+ }
+}
+
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC11U.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC11U.cpp
new file mode 100644
index 000000000..1a5fa8c0f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC11U.cpp
@@ -0,0 +1,738 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined(TARGET_LPC11UXX) || defined(TARGET_LPC11U6X) || defined(TARGET_LPC1347) || defined(TARGET_LPC1549)
+
+#if defined(TARGET_LPC1347) || defined(TARGET_LPC1549)
+#define USB_IRQ USB_IRQ_IRQn
+#else
+#define USB_IRQ USB_IRQn
+#endif
+
+#include "USBHAL.h"
+
+USBHAL * USBHAL::instance;
+#if defined(TARGET_LPC1549)
+static uint8_t usbmem[2048] __attribute__((aligned(2048)));
+#endif
+
+// Valid physical endpoint numbers are 0 to (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
+#define LAST_PHYSICAL_ENDPOINT (NUMBER_OF_PHYSICAL_ENDPOINTS-1)
+
+// Convert physical endpoint number to register bit
+#define EP(endpoint) (1UL<<endpoint)
+
+// Convert physical to logical
+#define PHY_TO_LOG(endpoint) ((endpoint)>>1)
+
+// Get endpoint direction
+#define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
+#define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
+
+// USB RAM
+#if defined(TARGET_LPC1549)
+#define USB_RAM_START ((uint32_t)usbmem)
+#define USB_RAM_SIZE sizeof(usbmem)
+#else
+#define USB_RAM_START (0x20004000)
+#define USB_RAM_SIZE (0x00000800)
+#endif
+
+// SYSAHBCLKCTRL
+#if defined(TARGET_LPC1549)
+#define CLK_USB (1UL<<23)
+#else
+#define CLK_USB (1UL<<14)
+#define CLK_USBRAM (1UL<<27)
+#endif
+
+// USB Information register
+#define FRAME_NR(a) ((a) & 0x7ff) // Frame number
+
+// USB Device Command/Status register
+#define DEV_ADDR_MASK (0x7f) // Device address
+#define DEV_ADDR(a) ((a) & DEV_ADDR_MASK)
+#define DEV_EN (1UL<<7) // Device enable
+#define SETUP (1UL<<8) // SETUP token received
+#define PLL_ON (1UL<<9) // PLL enabled in suspend
+#define DCON (1UL<<16) // Device status - connect
+#define DSUS (1UL<<17) // Device status - suspend
+#define DCON_C (1UL<<24) // Connect change
+#define DSUS_C (1UL<<25) // Suspend change
+#define DRES_C (1UL<<26) // Reset change
+#define VBUSDEBOUNCED (1UL<<28) // Vbus detected
+
+// Endpoint Command/Status list
+#define CMDSTS_A (1UL<<31) // Active
+#define CMDSTS_D (1UL<<30) // Disable
+#define CMDSTS_S (1UL<<29) // Stall
+#define CMDSTS_TR (1UL<<28) // Toggle Reset
+#define CMDSTS_RF (1UL<<27) // Rate Feedback mode
+#define CMDSTS_TV (1UL<<27) // Toggle Value
+#define CMDSTS_T (1UL<<26) // Endpoint Type
+#define CMDSTS_NBYTES(n) (((n)&0x3ff)<<16) // Number of bytes
+#define CMDSTS_ADDRESS_OFFSET(a) (((a)>>6)&0xffff) // Buffer start address
+
+#define BYTES_REMAINING(s) (((s)>>16)&0x3ff) // Bytes remaining after transfer
+
+// USB Non-endpoint interrupt sources
+#define FRAME_INT (1UL<<30)
+#define DEV_INT (1UL<<31)
+
+static volatile int epComplete = 0;
+
+// One entry for a double-buffered logical endpoint in the endpoint
+// command/status list. Endpoint 0 is single buffered, out[1] is used
+// for the SETUP packet and in[1] is not used
+typedef struct {
+ uint32_t out[2];
+ uint32_t in[2];
+} PACKED EP_COMMAND_STATUS;
+
+typedef struct {
+ uint8_t out[MAX_PACKET_SIZE_EP0];
+ uint8_t in[MAX_PACKET_SIZE_EP0];
+ uint8_t setup[SETUP_PACKET_SIZE];
+} PACKED CONTROL_TRANSFER;
+
+typedef struct {
+ uint32_t maxPacket;
+ uint32_t buffer[2];
+ uint32_t options;
+} PACKED EP_STATE;
+
+static volatile EP_STATE endpointState[NUMBER_OF_PHYSICAL_ENDPOINTS];
+
+// Pointer to the endpoint command/status list
+static EP_COMMAND_STATUS *ep = NULL;
+
+// Pointer to endpoint 0 data (IN/OUT and SETUP)
+static CONTROL_TRANSFER *ct = NULL;
+
+// Shadow DEVCMDSTAT register to avoid accidentally clearing flags or
+// initiating a remote wakeup event.
+static volatile uint32_t devCmdStat;
+
+// Pointers used to allocate USB RAM
+static uint32_t usbRamPtr = USB_RAM_START;
+static uint32_t epRamPtr = 0; // Buffers for endpoints > 0 start here
+
+#define ROUND_UP_TO_MULTIPLE(x, m) ((((x)+((m)-1))/(m))*(m))
+
+void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size);
+void USBMemCopy(uint8_t *dst, uint8_t *src, uint32_t size) {
+ if (size > 0) {
+ do {
+ *dst++ = *src++;
+ } while (--size > 0);
+ }
+}
+
+
+USBHAL::USBHAL(void) {
+ NVIC_DisableIRQ(USB_IRQ);
+
+ // fill in callback array
+ epCallback[0] = &USBHAL::EP1_OUT_callback;
+ epCallback[1] = &USBHAL::EP1_IN_callback;
+ epCallback[2] = &USBHAL::EP2_OUT_callback;
+ epCallback[3] = &USBHAL::EP2_IN_callback;
+ epCallback[4] = &USBHAL::EP3_OUT_callback;
+ epCallback[5] = &USBHAL::EP3_IN_callback;
+ epCallback[6] = &USBHAL::EP4_OUT_callback;
+ epCallback[7] = &USBHAL::EP4_IN_callback;
+
+#if defined(TARGET_LPC1549)
+ /* Set USB PLL input to system oscillator */
+ LPC_SYSCON->USBPLLCLKSEL = 0x01;
+
+ /* Setup USB PLL (FCLKIN = 12MHz) * 4 = 48MHz
+ MSEL = 3 (this is pre-decremented), PSEL = 1 (for P = 2)
+ FCLKOUT = FCLKIN * (MSEL + 1) = 12MHz * 4 = 48MHz
+ FCCO = FCLKOUT * 2 * P = 48MHz * 2 * 2 = 192MHz (within FCCO range) */
+ LPC_SYSCON->USBPLLCTRL = (0x3 | (1UL << 6));
+
+ /* Powerup USB PLL */
+ LPC_SYSCON->PDRUNCFG &= ~(CLK_USB);
+
+ /* Wait for PLL to lock */
+ while(!(LPC_SYSCON->USBPLLSTAT & 0x01));
+
+ /* enable USB main clock */
+ LPC_SYSCON->USBCLKSEL = 0x02;
+ LPC_SYSCON->USBCLKDIV = 1;
+
+ /* Enable AHB clock to the USB block. */
+ LPC_SYSCON->SYSAHBCLKCTRL1 |= CLK_USB;
+
+ /* power UP USB Phy */
+ LPC_SYSCON->PDRUNCFG &= ~(1UL << 9);
+
+ /* Reset USB block */
+ LPC_SYSCON->PRESETCTRL1 |= (CLK_USB);
+ LPC_SYSCON->PRESETCTRL1 &= ~(CLK_USB);
+
+#else
+ #if defined(TARGET_LPC11U35_401) || defined(TARGET_LPC11U35_501)
+ // USB_VBUS input with pull-down
+ LPC_IOCON->PIO0_3 = 0x00000009;
+ #endif
+
+ // nUSB_CONNECT output
+ LPC_IOCON->PIO0_6 = 0x00000001;
+
+ // Enable clocks (USB registers, USB RAM)
+ LPC_SYSCON->SYSAHBCLKCTRL |= CLK_USB | CLK_USBRAM;
+
+ // Ensure device disconnected (DCON not set)
+ LPC_USB->DEVCMDSTAT = 0;
+#endif
+ // to ensure that the USB host sees the device as
+ // disconnected if the target CPU is reset.
+ wait(0.3);
+
+ // Reserve space in USB RAM for endpoint command/status list
+ // Must be 256 byte aligned
+ usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 256);
+ ep = (EP_COMMAND_STATUS *)usbRamPtr;
+ usbRamPtr += (sizeof(EP_COMMAND_STATUS) * NUMBER_OF_LOGICAL_ENDPOINTS);
+ LPC_USB->EPLISTSTART = (uint32_t)(ep) & 0xffffff00;
+
+ // Reserve space in USB RAM for Endpoint 0
+ // Must be 64 byte aligned
+ usbRamPtr = ROUND_UP_TO_MULTIPLE(usbRamPtr, 64);
+ ct = (CONTROL_TRANSFER *)usbRamPtr;
+ usbRamPtr += sizeof(CONTROL_TRANSFER);
+ LPC_USB->DATABUFSTART =(uint32_t)(ct) & 0xffc00000;
+
+ // Setup command/status list for EP0
+ ep[0].out[0] = 0;
+ ep[0].in[0] = 0;
+ ep[0].out[1] = CMDSTS_ADDRESS_OFFSET((uint32_t)ct->setup);
+
+ // Route all interrupts to IRQ, some can be routed to
+ // USB_FIQ if you wish.
+ LPC_USB->INTROUTING = 0;
+
+ // Set device address 0, enable USB device, no remote wakeup
+ devCmdStat = DEV_ADDR(0) | DEV_EN | DSUS;
+ LPC_USB->DEVCMDSTAT = devCmdStat;
+
+ // Enable interrupts for device events and EP0
+ LPC_USB->INTEN = DEV_INT | EP(EP0IN) | EP(EP0OUT) | FRAME_INT;
+ instance = this;
+
+ //attach IRQ handler and enable interrupts
+ NVIC_SetVector(USB_IRQ, (uint32_t)&_usbisr);
+}
+
+USBHAL::~USBHAL(void) {
+ // Ensure device disconnected (DCON not set)
+ LPC_USB->DEVCMDSTAT = 0;
+ // Disable USB interrupts
+ NVIC_DisableIRQ(USB_IRQ);
+}
+
+void USBHAL::connect(void) {
+ NVIC_EnableIRQ(USB_IRQ);
+ devCmdStat |= DCON;
+ LPC_USB->DEVCMDSTAT = devCmdStat;
+}
+
+void USBHAL::disconnect(void) {
+ NVIC_DisableIRQ(USB_IRQ);
+ devCmdStat &= ~DCON;
+ LPC_USB->DEVCMDSTAT = devCmdStat;
+}
+
+void USBHAL::configureDevice(void) {
+ // Not required
+}
+
+void USBHAL::unconfigureDevice(void) {
+ // Not required
+}
+
+void USBHAL::EP0setup(uint8_t *buffer) {
+ // Copy setup packet data
+ USBMemCopy(buffer, ct->setup, SETUP_PACKET_SIZE);
+}
+
+void USBHAL::EP0read(void) {
+ // Start an endpoint 0 read
+
+ // The USB ISR will call USBDevice_EP0out() when a packet has been read,
+ // the USBDevice layer then calls USBBusInterface_EP0getReadResult() to
+ // read the data.
+
+ ep[0].out[0] = CMDSTS_A |CMDSTS_NBYTES(MAX_PACKET_SIZE_EP0) \
+ | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out);
+}
+
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
+ // Complete an endpoint 0 read
+ uint32_t bytesRead;
+
+ // Find how many bytes were read
+ bytesRead = MAX_PACKET_SIZE_EP0 - BYTES_REMAINING(ep[0].out[0]);
+
+ // Copy data
+ USBMemCopy(buffer, ct->out, bytesRead);
+ return bytesRead;
+}
+
+
+void USBHAL::EP0readStage(void) {
+ // Not required
+}
+
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
+ // Start and endpoint 0 write
+
+ // The USB ISR will call USBDevice_EP0in() when the data has
+ // been written, the USBDevice layer then calls
+ // USBBusInterface_EP0getWriteResult() to complete the transaction.
+
+ // Copy data
+ USBMemCopy(ct->in, buffer, size);
+
+ // Start transfer
+ ep[0].in[0] = CMDSTS_A | CMDSTS_NBYTES(size) \
+ | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->in);
+}
+
+
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
+ uint8_t bf = 0;
+ uint32_t flags = 0;
+
+ //check which buffer must be filled
+ if (LPC_USB->EPBUFCFG & EP(endpoint)) {
+ // Double buffered
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ bf = 1;
+ } else {
+ bf = 0;
+ }
+ }
+
+ // if isochronous endpoint, T = 1
+ if(endpointState[endpoint].options & ISOCHRONOUS)
+ {
+ flags |= CMDSTS_T;
+ }
+
+ //Active the endpoint for reading
+ ep[PHY_TO_LOG(endpoint)].out[bf] = CMDSTS_A | CMDSTS_NBYTES(maximumSize) \
+ | CMDSTS_ADDRESS_OFFSET((uint32_t)ct->out) | flags;
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead) {
+
+ uint8_t bf = 0;
+
+ if (!(epComplete & EP(endpoint)))
+ return EP_PENDING;
+ else {
+ epComplete &= ~EP(endpoint);
+
+ //check which buffer has been filled
+ if (LPC_USB->EPBUFCFG & EP(endpoint)) {
+ // Double buffered (here we read the previous buffer which was used)
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ bf = 0;
+ } else {
+ bf = 1;
+ }
+ }
+
+ // Find how many bytes were read
+ *bytesRead = (uint32_t) (endpointState[endpoint].maxPacket - BYTES_REMAINING(ep[PHY_TO_LOG(endpoint)].out[bf]));
+
+ // Copy data
+ USBMemCopy(data, ct->out, *bytesRead);
+ return EP_COMPLETED;
+ }
+}
+
+void USBHAL::EP0getWriteResult(void) {
+ // Not required
+}
+
+void USBHAL::EP0stall(void) {
+ ep[0].in[0] = CMDSTS_S;
+ ep[0].out[0] = CMDSTS_S;
+}
+
+void USBHAL::setAddress(uint8_t address) {
+ devCmdStat &= ~DEV_ADDR_MASK;
+ devCmdStat |= DEV_ADDR(address);
+ LPC_USB->DEVCMDSTAT = devCmdStat;
+}
+
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
+ uint32_t flags = 0;
+ uint32_t bf;
+
+ // Validate parameters
+ if (data == NULL) {
+ return EP_INVALID;
+ }
+
+ if (endpoint > LAST_PHYSICAL_ENDPOINT) {
+ return EP_INVALID;
+ }
+
+ if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
+ return EP_INVALID;
+ }
+
+ if (size > endpointState[endpoint].maxPacket) {
+ return EP_INVALID;
+ }
+
+ if (LPC_USB->EPBUFCFG & EP(endpoint)) {
+ // Double buffered
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ bf = 1;
+ } else {
+ bf = 0;
+ }
+ } else {
+ // Single buffered
+ bf = 0;
+ }
+
+ // Check if already active
+ if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
+ return EP_INVALID;
+ }
+
+ // Check if stalled
+ if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
+ return EP_STALLED;
+ }
+
+ // Copy data to USB RAM
+ USBMemCopy((uint8_t *)endpointState[endpoint].buffer[bf], data, size);
+
+ // Add options
+ if (endpointState[endpoint].options & RATE_FEEDBACK_MODE) {
+ flags |= CMDSTS_RF;
+ }
+
+ if (endpointState[endpoint].options & ISOCHRONOUS) {
+ flags |= CMDSTS_T;
+ }
+
+ // Add transfer
+ ep[PHY_TO_LOG(endpoint)].in[bf] = CMDSTS_ADDRESS_OFFSET( \
+ endpointState[endpoint].buffer[bf]) \
+ | CMDSTS_NBYTES(size) | CMDSTS_A | flags;
+
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
+ uint32_t bf;
+
+ // Validate parameters
+ if (endpoint > LAST_PHYSICAL_ENDPOINT) {
+ return EP_INVALID;
+ }
+
+ if (OUT_EP(endpoint)) {
+ return EP_INVALID;
+ }
+
+ if (LPC_USB->EPBUFCFG & EP(endpoint)) {
+ // Double buffered // TODO: FIX THIS
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ bf = 1;
+ } else {
+ bf = 0;
+ }
+ } else {
+ // Single buffered
+ bf = 0;
+ }
+
+ // Check if endpoint still active
+ if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_A) {
+ return EP_PENDING;
+ }
+
+ // Check if stalled
+ if (ep[PHY_TO_LOG(endpoint)].in[bf] & CMDSTS_S) {
+ return EP_STALLED;
+ }
+
+ return EP_COMPLETED;
+}
+
+void USBHAL::stallEndpoint(uint8_t endpoint) {
+
+ // FIX: should this clear active bit?
+ if (IN_EP(endpoint)) {
+ ep[PHY_TO_LOG(endpoint)].in[0] |= CMDSTS_S;
+ ep[PHY_TO_LOG(endpoint)].in[1] |= CMDSTS_S;
+ } else {
+ ep[PHY_TO_LOG(endpoint)].out[0] |= CMDSTS_S;
+ ep[PHY_TO_LOG(endpoint)].out[1] |= CMDSTS_S;
+ }
+}
+
+void USBHAL::unstallEndpoint(uint8_t endpoint) {
+ if (LPC_USB->EPBUFCFG & EP(endpoint)) {
+ // Double buffered
+ if (IN_EP(endpoint)) {
+ ep[PHY_TO_LOG(endpoint)].in[0] = 0; // S = 0
+ ep[PHY_TO_LOG(endpoint)].in[1] = 0; // S = 0
+
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ ep[PHY_TO_LOG(endpoint)].in[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
+ } else {
+ ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
+ }
+ } else {
+ ep[PHY_TO_LOG(endpoint)].out[0] = 0; // S = 0
+ ep[PHY_TO_LOG(endpoint)].out[1] = 0; // S = 0
+
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ ep[PHY_TO_LOG(endpoint)].out[1] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
+ } else {
+ ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
+ }
+ }
+ } else {
+ // Single buffered
+ if (IN_EP(endpoint)) {
+ ep[PHY_TO_LOG(endpoint)].in[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
+ } else {
+ ep[PHY_TO_LOG(endpoint)].out[0] = CMDSTS_TR; // S = 0, TR = 1, TV = 0
+ }
+ }
+}
+
+bool USBHAL::getEndpointStallState(unsigned char endpoint) {
+ if (IN_EP(endpoint)) {
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ if (ep[PHY_TO_LOG(endpoint)].in[1] & CMDSTS_S) {
+ return true;
+ }
+ } else {
+ if (ep[PHY_TO_LOG(endpoint)].in[0] & CMDSTS_S) {
+ return true;
+ }
+ }
+ } else {
+ if (LPC_USB->EPINUSE & EP(endpoint)) {
+ if (ep[PHY_TO_LOG(endpoint)].out[1] & CMDSTS_S) {
+ return true;
+ }
+ } else {
+ if (ep[PHY_TO_LOG(endpoint)].out[0] & CMDSTS_S) {
+ return true;
+ }
+ }
+ }
+
+ return false;
+}
+
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options) {
+ uint32_t tmpEpRamPtr;
+
+ if (endpoint > LAST_PHYSICAL_ENDPOINT) {
+ return false;
+ }
+
+ // Not applicable to the control endpoints
+ if ((endpoint==EP0IN) || (endpoint==EP0OUT)) {
+ return false;
+ }
+
+ // Allocate buffers in USB RAM
+ tmpEpRamPtr = epRamPtr;
+
+ // Must be 64 byte aligned
+ tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
+
+ if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
+ // Out of memory
+ return false;
+ }
+
+ // Allocate first buffer
+ endpointState[endpoint].buffer[0] = tmpEpRamPtr;
+ tmpEpRamPtr += maxPacket;
+
+ if (!(options & SINGLE_BUFFERED)) {
+ // Must be 64 byte aligned
+ tmpEpRamPtr = ROUND_UP_TO_MULTIPLE(tmpEpRamPtr, 64);
+
+ if ((tmpEpRamPtr + maxPacket) > (USB_RAM_START + USB_RAM_SIZE)) {
+ // Out of memory
+ return false;
+ }
+
+ // Allocate second buffer
+ endpointState[endpoint].buffer[1] = tmpEpRamPtr;
+ tmpEpRamPtr += maxPacket;
+ }
+
+ // Commit to this USB RAM allocation
+ epRamPtr = tmpEpRamPtr;
+
+ // Remaining endpoint state values
+ endpointState[endpoint].maxPacket = maxPacket;
+ endpointState[endpoint].options = options;
+
+ // Enable double buffering if required
+ if (options & SINGLE_BUFFERED) {
+ LPC_USB->EPBUFCFG &= ~EP(endpoint);
+ } else {
+ // Double buffered
+ LPC_USB->EPBUFCFG |= EP(endpoint);
+ }
+
+ // Enable interrupt
+ LPC_USB->INTEN |= EP(endpoint);
+
+ // Enable endpoint
+ unstallEndpoint(endpoint);
+ return true;
+}
+
+void USBHAL::remoteWakeup(void) {
+ // Clearing DSUS bit initiates a remote wakeup if the
+ // device is currently enabled and suspended - otherwise
+ // it has no effect.
+ LPC_USB->DEVCMDSTAT = devCmdStat & ~DSUS;
+}
+
+
+static void disableEndpoints(void) {
+ uint32_t logEp;
+
+ // Ref. Table 158 "When a bus reset is received, software
+ // must set the disable bit of all endpoints to 1".
+
+ for (logEp = 1; logEp < NUMBER_OF_LOGICAL_ENDPOINTS; logEp++) {
+ ep[logEp].out[0] = CMDSTS_D;
+ ep[logEp].out[1] = CMDSTS_D;
+ ep[logEp].in[0] = CMDSTS_D;
+ ep[logEp].in[1] = CMDSTS_D;
+ }
+
+ // Start of USB RAM for endpoints > 0
+ epRamPtr = usbRamPtr;
+}
+
+
+
+void USBHAL::_usbisr(void) {
+ instance->usbisr();
+}
+
+void USBHAL::usbisr(void) {
+ // Start of frame
+ if (LPC_USB->INTSTAT & FRAME_INT) {
+ // Clear SOF interrupt
+ LPC_USB->INTSTAT = FRAME_INT;
+
+ // SOF event, read frame number
+ SOF(FRAME_NR(LPC_USB->INFO));
+ }
+
+ // Device state
+ if (LPC_USB->INTSTAT & DEV_INT) {
+ LPC_USB->INTSTAT = DEV_INT;
+
+ if (LPC_USB->DEVCMDSTAT & DSUS_C) {
+ // Suspend status changed
+ LPC_USB->DEVCMDSTAT = devCmdStat | DSUS_C;
+ if((LPC_USB->DEVCMDSTAT & DSUS) != 0) {
+ suspendStateChanged(1);
+ }
+ }
+
+ if (LPC_USB->DEVCMDSTAT & DRES_C) {
+ // Bus reset
+ LPC_USB->DEVCMDSTAT = devCmdStat | DRES_C;
+
+ suspendStateChanged(0);
+
+ // Disable endpoints > 0
+ disableEndpoints();
+
+ // Bus reset event
+ busReset();
+ }
+ }
+
+ // Endpoint 0
+ if (LPC_USB->INTSTAT & EP(EP0OUT)) {
+ // Clear EP0OUT/SETUP interrupt
+ LPC_USB->INTSTAT = EP(EP0OUT);
+
+ // Check if SETUP
+ if (LPC_USB->DEVCMDSTAT & SETUP) {
+ // Clear Active and Stall bits for EP0
+ // Documentation does not make it clear if we must use the
+ // EPSKIP register to achieve this, Fig. 16 and NXP reference
+ // code suggests we can just clear the Active bits - check with
+ // NXP to be sure.
+ ep[0].in[0] = 0;
+ ep[0].out[0] = 0;
+
+ // Clear EP0IN interrupt
+ LPC_USB->INTSTAT = EP(EP0IN);
+
+ // Clear SETUP (and INTONNAK_CI/O) in device status register
+ LPC_USB->DEVCMDSTAT = devCmdStat | SETUP;
+
+ // EP0 SETUP event (SETUP data received)
+ EP0setupCallback();
+ } else {
+ // EP0OUT ACK event (OUT data received)
+ EP0out();
+ }
+ }
+
+ if (LPC_USB->INTSTAT & EP(EP0IN)) {
+ // Clear EP0IN interrupt
+ LPC_USB->INTSTAT = EP(EP0IN);
+
+ // EP0IN ACK event (IN data sent)
+ EP0in();
+ }
+
+ for (uint8_t num = 2; num < 5*2; num++) {
+ if (LPC_USB->INTSTAT & EP(num)) {
+ LPC_USB->INTSTAT = EP(num);
+ epComplete |= EP(num);
+ if ((instance->*(epCallback[num - 2]))()) {
+ epComplete &= ~EP(num);
+ }
+ }
+ }
+}
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp
new file mode 100644
index 000000000..8bffe10ac
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC17.cpp
@@ -0,0 +1,623 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined(TARGET_LPC1768) || defined(TARGET_LPC2368)
+
+#include "USBHAL.h"
+
+
+// Get endpoint direction
+#define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
+#define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
+
+// Convert physical endpoint number to register bit
+#define EP(endpoint) (1UL<<endpoint)
+
+// Power Control for Peripherals register
+#define PCUSB (1UL<<31)
+
+// USB Clock Control register
+#define DEV_CLK_EN (1UL<<1)
+#define AHB_CLK_EN (1UL<<4)
+
+// USB Clock Status register
+#define DEV_CLK_ON (1UL<<1)
+#define AHB_CLK_ON (1UL<<4)
+
+// USB Device Interupt registers
+#define FRAME (1UL<<0)
+#define EP_FAST (1UL<<1)
+#define EP_SLOW (1UL<<2)
+#define DEV_STAT (1UL<<3)
+#define CCEMPTY (1UL<<4)
+#define CDFULL (1UL<<5)
+#define RxENDPKT (1UL<<6)
+#define TxENDPKT (1UL<<7)
+#define EP_RLZED (1UL<<8)
+#define ERR_INT (1UL<<9)
+
+// USB Control register
+#define RD_EN (1<<0)
+#define WR_EN (1<<1)
+#define LOG_ENDPOINT(endpoint) ((endpoint>>1)<<2)
+
+// USB Receive Packet Length register
+#define DV (1UL<<10)
+#define PKT_RDY (1UL<<11)
+#define PKT_LNGTH_MASK (0x3ff)
+
+// Serial Interface Engine (SIE)
+#define SIE_WRITE (0x01)
+#define SIE_READ (0x02)
+#define SIE_COMMAND (0x05)
+#define SIE_CMD_CODE(phase, data) ((phase<<8)|(data<<16))
+
+// SIE Command codes
+#define SIE_CMD_SET_ADDRESS (0xD0)
+#define SIE_CMD_CONFIGURE_DEVICE (0xD8)
+#define SIE_CMD_SET_MODE (0xF3)
+#define SIE_CMD_READ_FRAME_NUMBER (0xF5)
+#define SIE_CMD_READ_TEST_REGISTER (0xFD)
+#define SIE_CMD_SET_DEVICE_STATUS (0xFE)
+#define SIE_CMD_GET_DEVICE_STATUS (0xFE)
+#define SIE_CMD_GET_ERROR_CODE (0xFF)
+#define SIE_CMD_READ_ERROR_STATUS (0xFB)
+
+#define SIE_CMD_SELECT_ENDPOINT(endpoint) (0x00+endpoint)
+#define SIE_CMD_SELECT_ENDPOINT_CLEAR_INTERRUPT(endpoint) (0x40+endpoint)
+#define SIE_CMD_SET_ENDPOINT_STATUS(endpoint) (0x40+endpoint)
+
+#define SIE_CMD_CLEAR_BUFFER (0xF2)
+#define SIE_CMD_VALIDATE_BUFFER (0xFA)
+
+// SIE Device Status register
+#define SIE_DS_CON (1<<0)
+#define SIE_DS_CON_CH (1<<1)
+#define SIE_DS_SUS (1<<2)
+#define SIE_DS_SUS_CH (1<<3)
+#define SIE_DS_RST (1<<4)
+
+// SIE Device Set Address register
+#define SIE_DSA_DEV_EN (1<<7)
+
+// SIE Configue Device register
+#define SIE_CONF_DEVICE (1<<0)
+
+// Select Endpoint register
+#define SIE_SE_FE (1<<0)
+#define SIE_SE_ST (1<<1)
+#define SIE_SE_STP (1<<2)
+#define SIE_SE_PO (1<<3)
+#define SIE_SE_EPN (1<<4)
+#define SIE_SE_B_1_FULL (1<<5)
+#define SIE_SE_B_2_FULL (1<<6)
+
+// Set Endpoint Status command
+#define SIE_SES_ST (1<<0)
+#define SIE_SES_DA (1<<5)
+#define SIE_SES_RF_MO (1<<6)
+#define SIE_SES_CND_ST (1<<7)
+
+
+USBHAL * USBHAL::instance;
+
+static volatile int epComplete;
+static uint32_t endpointStallState;
+
+static void SIECommand(uint32_t command) {
+ // The command phase of a SIE transaction
+ LPC_USB->USBDevIntClr = CCEMPTY;
+ LPC_USB->USBCmdCode = SIE_CMD_CODE(SIE_COMMAND, command);
+ while (!(LPC_USB->USBDevIntSt & CCEMPTY));
+}
+
+static void SIEWriteData(uint8_t data) {
+ // The data write phase of a SIE transaction
+ LPC_USB->USBDevIntClr = CCEMPTY;
+ LPC_USB->USBCmdCode = SIE_CMD_CODE(SIE_WRITE, data);
+ while (!(LPC_USB->USBDevIntSt & CCEMPTY));
+}
+
+static uint8_t SIEReadData(uint32_t command) {
+ // The data read phase of a SIE transaction
+ LPC_USB->USBDevIntClr = CDFULL;
+ LPC_USB->USBCmdCode = SIE_CMD_CODE(SIE_READ, command);
+ while (!(LPC_USB->USBDevIntSt & CDFULL));
+ return (uint8_t)LPC_USB->USBCmdData;
+}
+
+static void SIEsetDeviceStatus(uint8_t status) {
+ // Write SIE device status register
+ SIECommand(SIE_CMD_SET_DEVICE_STATUS);
+ SIEWriteData(status);
+}
+
+static uint8_t SIEgetDeviceStatus(void) {
+ // Read SIE device status register
+ SIECommand(SIE_CMD_GET_DEVICE_STATUS);
+ return SIEReadData(SIE_CMD_GET_DEVICE_STATUS);
+}
+
+void SIEsetAddress(uint8_t address) {
+ // Write SIE device address register
+ SIECommand(SIE_CMD_SET_ADDRESS);
+ SIEWriteData((address & 0x7f) | SIE_DSA_DEV_EN);
+}
+
+static uint8_t SIEselectEndpoint(uint8_t endpoint) {
+ // SIE select endpoint command
+ SIECommand(SIE_CMD_SELECT_ENDPOINT(endpoint));
+ return SIEReadData(SIE_CMD_SELECT_ENDPOINT(endpoint));
+}
+
+static uint8_t SIEclearBuffer(void) {
+ // SIE clear buffer command
+ SIECommand(SIE_CMD_CLEAR_BUFFER);
+ return SIEReadData(SIE_CMD_CLEAR_BUFFER);
+}
+
+static void SIEvalidateBuffer(void) {
+ // SIE validate buffer command
+ SIECommand(SIE_CMD_VALIDATE_BUFFER);
+}
+
+static void SIEsetEndpointStatus(uint8_t endpoint, uint8_t status) {
+ // SIE set endpoint status command
+ SIECommand(SIE_CMD_SET_ENDPOINT_STATUS(endpoint));
+ SIEWriteData(status);
+}
+
+static uint16_t SIEgetFrameNumber(void) __attribute__ ((unused));
+static uint16_t SIEgetFrameNumber(void) {
+ // Read current frame number
+ uint16_t lowByte;
+ uint16_t highByte;
+
+ SIECommand(SIE_CMD_READ_FRAME_NUMBER);
+ lowByte = SIEReadData(SIE_CMD_READ_FRAME_NUMBER);
+ highByte = SIEReadData(SIE_CMD_READ_FRAME_NUMBER);
+
+ return (highByte << 8) | lowByte;
+}
+
+static void SIEconfigureDevice(void) {
+ // SIE Configure device command
+ SIECommand(SIE_CMD_CONFIGURE_DEVICE);
+ SIEWriteData(SIE_CONF_DEVICE);
+}
+
+static void SIEunconfigureDevice(void) {
+ // SIE Configure device command
+ SIECommand(SIE_CMD_CONFIGURE_DEVICE);
+ SIEWriteData(0);
+}
+
+static void SIEconnect(void) {
+ // Connect USB device
+ uint8_t status = SIEgetDeviceStatus();
+ SIEsetDeviceStatus(status | SIE_DS_CON);
+}
+
+
+static void SIEdisconnect(void) {
+ // Disconnect USB device
+ uint8_t status = SIEgetDeviceStatus();
+ SIEsetDeviceStatus(status & ~SIE_DS_CON);
+}
+
+
+static uint8_t selectEndpointClearInterrupt(uint8_t endpoint) {
+ // Implemented using using EP_INT_CLR.
+ LPC_USB->USBEpIntClr = EP(endpoint);
+ while (!(LPC_USB->USBDevIntSt & CDFULL));
+ return (uint8_t)LPC_USB->USBCmdData;
+}
+
+
+static void enableEndpointEvent(uint8_t endpoint) {
+ // Enable an endpoint interrupt
+ LPC_USB->USBEpIntEn |= EP(endpoint);
+}
+
+static void disableEndpointEvent(uint8_t endpoint) __attribute__ ((unused));
+static void disableEndpointEvent(uint8_t endpoint) {
+ // Disable an endpoint interrupt
+ LPC_USB->USBEpIntEn &= ~EP(endpoint);
+}
+
+static volatile uint32_t __attribute__((used)) dummyRead;
+uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
+ // Read from an OUT endpoint
+ uint32_t size;
+ uint32_t i;
+ uint32_t data = 0;
+ uint8_t offset;
+
+ LPC_USB->USBCtrl = LOG_ENDPOINT(endpoint) | RD_EN;
+ while (!(LPC_USB->USBRxPLen & PKT_RDY));
+
+ size = LPC_USB->USBRxPLen & PKT_LNGTH_MASK;
+
+ offset = 0;
+
+ if (size > 0) {
+ for (i=0; i<size; i++) {
+ if (offset==0) {
+ // Fetch up to four bytes of data as a word
+ data = LPC_USB->USBRxData;
+ }
+
+ // extract a byte
+ *buffer = (data>>offset) & 0xff;
+ buffer++;
+
+ // move on to the next byte
+ offset = (offset + 8) % 32;
+ }
+ } else {
+ dummyRead = LPC_USB->USBRxData;
+ }
+
+ LPC_USB->USBCtrl = 0;
+
+ if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) {
+ SIEselectEndpoint(endpoint);
+ SIEclearBuffer();
+ }
+
+ return size;
+}
+
+static void endpointWritecore(uint8_t endpoint, uint8_t *buffer, uint32_t size) {
+ // Write to an IN endpoint
+ uint32_t temp, data;
+ uint8_t offset;
+
+ LPC_USB->USBCtrl = LOG_ENDPOINT(endpoint) | WR_EN;
+
+ LPC_USB->USBTxPLen = size;
+ offset = 0;
+ data = 0;
+
+ if (size>0) {
+ do {
+ // Fetch next data byte into a word-sized temporary variable
+ temp = *buffer++;
+
+ // Add to current data word
+ temp = temp << offset;
+ data = data | temp;
+
+ // move on to the next byte
+ offset = (offset + 8) % 32;
+ size--;
+
+ if ((offset==0) || (size==0)) {
+ // Write the word to the endpoint
+ LPC_USB->USBTxData = data;
+ data = 0;
+ }
+ } while (size>0);
+ } else {
+ LPC_USB->USBTxData = 0;
+ }
+
+ // Clear WR_EN to cover zero length packet case
+ LPC_USB->USBCtrl=0;
+
+ SIEselectEndpoint(endpoint);
+ SIEvalidateBuffer();
+}
+
+USBHAL::USBHAL(void) {
+ // Disable IRQ
+ NVIC_DisableIRQ(USB_IRQn);
+
+ // fill in callback array
+ epCallback[0] = &USBHAL::EP1_OUT_callback;
+ epCallback[1] = &USBHAL::EP1_IN_callback;
+ epCallback[2] = &USBHAL::EP2_OUT_callback;
+ epCallback[3] = &USBHAL::EP2_IN_callback;
+ epCallback[4] = &USBHAL::EP3_OUT_callback;
+ epCallback[5] = &USBHAL::EP3_IN_callback;
+ epCallback[6] = &USBHAL::EP4_OUT_callback;
+ epCallback[7] = &USBHAL::EP4_IN_callback;
+ epCallback[8] = &USBHAL::EP5_OUT_callback;
+ epCallback[9] = &USBHAL::EP5_IN_callback;
+ epCallback[10] = &USBHAL::EP6_OUT_callback;
+ epCallback[11] = &USBHAL::EP6_IN_callback;
+ epCallback[12] = &USBHAL::EP7_OUT_callback;
+ epCallback[13] = &USBHAL::EP7_IN_callback;
+ epCallback[14] = &USBHAL::EP8_OUT_callback;
+ epCallback[15] = &USBHAL::EP8_IN_callback;
+ epCallback[16] = &USBHAL::EP9_OUT_callback;
+ epCallback[17] = &USBHAL::EP9_IN_callback;
+ epCallback[18] = &USBHAL::EP10_OUT_callback;
+ epCallback[19] = &USBHAL::EP10_IN_callback;
+ epCallback[20] = &USBHAL::EP11_OUT_callback;
+ epCallback[21] = &USBHAL::EP11_IN_callback;
+ epCallback[22] = &USBHAL::EP12_OUT_callback;
+ epCallback[23] = &USBHAL::EP12_IN_callback;
+ epCallback[24] = &USBHAL::EP13_OUT_callback;
+ epCallback[25] = &USBHAL::EP13_IN_callback;
+ epCallback[26] = &USBHAL::EP14_OUT_callback;
+ epCallback[27] = &USBHAL::EP14_IN_callback;
+ epCallback[28] = &USBHAL::EP15_OUT_callback;
+ epCallback[29] = &USBHAL::EP15_IN_callback;
+
+ // Enable power to USB device controller
+ LPC_SC->PCONP |= PCUSB;
+
+ // Enable USB clocks
+ LPC_USB->USBClkCtrl |= DEV_CLK_EN | AHB_CLK_EN;
+ while (LPC_USB->USBClkSt != (DEV_CLK_ON | AHB_CLK_ON));
+
+ // Configure pins P0.29 and P0.30 to be USB D+ and USB D-
+ LPC_PINCON->PINSEL1 &= 0xc3ffffff;
+ LPC_PINCON->PINSEL1 |= 0x14000000;
+
+ // Disconnect USB device
+ SIEdisconnect();
+
+ // Configure pin P2.9 to be Connect
+ LPC_PINCON->PINSEL4 &= 0xfffcffff;
+ LPC_PINCON->PINSEL4 |= 0x00040000;
+
+ // Connect must be low for at least 2.5uS
+ wait(0.3);
+
+ // Set the maximum packet size for the control endpoints
+ realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
+ realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
+
+ // Attach IRQ
+ instance = this;
+ NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
+
+ // Enable interrupts for device events and EP0
+ LPC_USB->USBDevIntEn = EP_SLOW | DEV_STAT | FRAME;
+ enableEndpointEvent(EP0IN);
+ enableEndpointEvent(EP0OUT);
+}
+
+USBHAL::~USBHAL(void) {
+ // Ensure device disconnected
+ SIEdisconnect();
+ // Disable USB interrupts
+ NVIC_DisableIRQ(USB_IRQn);
+}
+
+void USBHAL::connect(void) {
+ NVIC_EnableIRQ(USB_IRQn);
+ // Connect USB device
+ SIEconnect();
+}
+
+void USBHAL::disconnect(void) {
+ NVIC_DisableIRQ(USB_IRQn);
+ // Disconnect USB device
+ SIEdisconnect();
+}
+
+void USBHAL::configureDevice(void) {
+ SIEconfigureDevice();
+}
+
+void USBHAL::unconfigureDevice(void) {
+ SIEunconfigureDevice();
+}
+
+void USBHAL::setAddress(uint8_t address) {
+ SIEsetAddress(address);
+}
+
+void USBHAL::EP0setup(uint8_t *buffer) {
+ endpointReadcore(EP0OUT, buffer);
+}
+
+void USBHAL::EP0read(void) {
+ // Not required
+}
+
+void USBHAL::EP0readStage(void) {
+ // Not required
+}
+
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
+ return endpointReadcore(EP0OUT, buffer);
+}
+
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
+ endpointWritecore(EP0IN, buffer, size);
+}
+
+void USBHAL::EP0getWriteResult(void) {
+ // Not required
+}
+
+void USBHAL::EP0stall(void) {
+ // This will stall both control endpoints
+ stallEndpoint(EP0OUT);
+}
+
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
+
+ //for isochronous endpoint, we don't wait an interrupt
+ if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) {
+ if (!(epComplete & EP(endpoint)))
+ return EP_PENDING;
+ }
+
+ *bytesRead = endpointReadcore(endpoint, buffer);
+ epComplete &= ~EP(endpoint);
+ return EP_COMPLETED;
+}
+
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
+ if (getEndpointStallState(endpoint)) {
+ return EP_STALLED;
+ }
+
+ epComplete &= ~EP(endpoint);
+
+ endpointWritecore(endpoint, data, size);
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
+ if (epComplete & EP(endpoint)) {
+ epComplete &= ~EP(endpoint);
+ return EP_COMPLETED;
+ }
+
+ return EP_PENDING;
+}
+
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
+ // Realise an endpoint
+ LPC_USB->USBDevIntClr = EP_RLZED;
+ LPC_USB->USBReEp |= EP(endpoint);
+ LPC_USB->USBEpInd = endpoint;
+ LPC_USB->USBMaxPSize = maxPacket;
+
+ while (!(LPC_USB->USBDevIntSt & EP_RLZED));
+ LPC_USB->USBDevIntClr = EP_RLZED;
+
+ // Clear stall state
+ endpointStallState &= ~EP(endpoint);
+
+ enableEndpointEvent(endpoint);
+ return true;
+}
+
+void USBHAL::stallEndpoint(uint8_t endpoint) {
+ // Stall an endpoint
+ if ( (endpoint==EP0IN) || (endpoint==EP0OUT) ) {
+ // Conditionally stall both control endpoints
+ SIEsetEndpointStatus(EP0OUT, SIE_SES_CND_ST);
+ } else {
+ SIEsetEndpointStatus(endpoint, SIE_SES_ST);
+
+ // Update stall state
+ endpointStallState |= EP(endpoint);
+ }
+}
+
+void USBHAL::unstallEndpoint(uint8_t endpoint) {
+ // Unstall an endpoint. The endpoint will also be reinitialised
+ SIEsetEndpointStatus(endpoint, 0);
+
+ // Update stall state
+ endpointStallState &= ~EP(endpoint);
+}
+
+bool USBHAL::getEndpointStallState(uint8_t endpoint) {
+ // Returns true if endpoint stalled
+ return endpointStallState & EP(endpoint);
+}
+
+void USBHAL::remoteWakeup(void) {
+ // Remote wakeup
+ uint8_t status;
+
+ // Enable USB clocks
+ LPC_USB->USBClkCtrl |= DEV_CLK_EN | AHB_CLK_EN;
+ while (LPC_USB->USBClkSt != (DEV_CLK_ON | AHB_CLK_ON));
+
+ status = SIEgetDeviceStatus();
+ SIEsetDeviceStatus(status & ~SIE_DS_SUS);
+}
+
+void USBHAL::_usbisr(void) {
+ instance->usbisr();
+}
+
+
+void USBHAL::usbisr(void) {
+ uint8_t devStat;
+
+ if (LPC_USB->USBDevIntSt & FRAME) {
+ // Start of frame event
+ SOF(SIEgetFrameNumber());
+ // Clear interrupt status flag
+ LPC_USB->USBDevIntClr = FRAME;
+ }
+
+ if (LPC_USB->USBDevIntSt & DEV_STAT) {
+ // Device Status interrupt
+ // Must clear the interrupt status flag before reading the device status from the SIE
+ LPC_USB->USBDevIntClr = DEV_STAT;
+
+ // Read device status from SIE
+ devStat = SIEgetDeviceStatus();
+ //printf("devStat: %d\r\n", devStat);
+
+ if (devStat & SIE_DS_SUS_CH) {
+ // Suspend status changed
+ if((devStat & SIE_DS_SUS) != 0) {
+ suspendStateChanged(0);
+ }
+ }
+
+ if (devStat & SIE_DS_RST) {
+ // Bus reset
+ if((devStat & SIE_DS_SUS) == 0) {
+ suspendStateChanged(1);
+ }
+ busReset();
+ }
+ }
+
+ if (LPC_USB->USBDevIntSt & EP_SLOW) {
+ // (Slow) Endpoint Interrupt
+
+ // Process each endpoint interrupt
+ if (LPC_USB->USBEpIntSt & EP(EP0OUT)) {
+ if (selectEndpointClearInterrupt(EP0OUT) & SIE_SE_STP) {
+ // this is a setup packet
+ EP0setupCallback();
+ } else {
+ EP0out();
+ }
+ LPC_USB->USBDevIntClr = EP_SLOW;
+ }
+
+ if (LPC_USB->USBEpIntSt & EP(EP0IN)) {
+ selectEndpointClearInterrupt(EP0IN);
+ LPC_USB->USBDevIntClr = EP_SLOW;
+ EP0in();
+ }
+
+ for (uint8_t num = 2; num < 16*2; num++) {
+ if (LPC_USB->USBEpIntSt & EP(num)) {
+ selectEndpointClearInterrupt(num);
+ epComplete |= EP(num);
+ LPC_USB->USBDevIntClr = EP_SLOW;
+ if ((instance->*(epCallback[num - 2]))()) {
+ epComplete &= ~EP(num);
+ }
+ }
+ }
+ }
+}
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC40.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC40.cpp
new file mode 100644
index 000000000..a5d7b4440
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_LPC40.cpp
@@ -0,0 +1,628 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined(TARGET_LPC4088) || defined(TARGET_LPC4088_DM)
+
+#include "USBHAL.h"
+
+
+// Get endpoint direction
+#define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
+#define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
+
+// Convert physical endpoint number to register bit
+#define EP(endpoint) (1UL<<endpoint)
+
+// Power Control for Peripherals register
+#define PCUSB (1UL<<31)
+
+// USB Clock Control register
+#define DEV_CLK_EN (1UL<<1)
+#define PORT_CLK_EN (1UL<<3)
+#define AHB_CLK_EN (1UL<<4)
+
+// USB Clock Status register
+#define DEV_CLK_ON (1UL<<1)
+#define AHB_CLK_ON (1UL<<4)
+
+// USB Device Interupt registers
+#define FRAME (1UL<<0)
+#define EP_FAST (1UL<<1)
+#define EP_SLOW (1UL<<2)
+#define DEV_STAT (1UL<<3)
+#define CCEMPTY (1UL<<4)
+#define CDFULL (1UL<<5)
+#define RxENDPKT (1UL<<6)
+#define TxENDPKT (1UL<<7)
+#define EP_RLZED (1UL<<8)
+#define ERR_INT (1UL<<9)
+
+// USB Control register
+#define RD_EN (1<<0)
+#define WR_EN (1<<1)
+#define LOG_ENDPOINT(endpoint) ((endpoint>>1)<<2)
+
+// USB Receive Packet Length register
+#define DV (1UL<<10)
+#define PKT_RDY (1UL<<11)
+#define PKT_LNGTH_MASK (0x3ff)
+
+// Serial Interface Engine (SIE)
+#define SIE_WRITE (0x01)
+#define SIE_READ (0x02)
+#define SIE_COMMAND (0x05)
+#define SIE_CMD_CODE(phase, data) ((phase<<8)|(data<<16))
+
+// SIE Command codes
+#define SIE_CMD_SET_ADDRESS (0xD0)
+#define SIE_CMD_CONFIGURE_DEVICE (0xD8)
+#define SIE_CMD_SET_MODE (0xF3)
+#define SIE_CMD_READ_FRAME_NUMBER (0xF5)
+#define SIE_CMD_READ_TEST_REGISTER (0xFD)
+#define SIE_CMD_SET_DEVICE_STATUS (0xFE)
+#define SIE_CMD_GET_DEVICE_STATUS (0xFE)
+#define SIE_CMD_GET_ERROR_CODE (0xFF)
+#define SIE_CMD_READ_ERROR_STATUS (0xFB)
+
+#define SIE_CMD_SELECT_ENDPOINT(endpoint) (0x00+endpoint)
+#define SIE_CMD_SELECT_ENDPOINT_CLEAR_INTERRUPT(endpoint) (0x40+endpoint)
+#define SIE_CMD_SET_ENDPOINT_STATUS(endpoint) (0x40+endpoint)
+
+#define SIE_CMD_CLEAR_BUFFER (0xF2)
+#define SIE_CMD_VALIDATE_BUFFER (0xFA)
+
+// SIE Device Status register
+#define SIE_DS_CON (1<<0)
+#define SIE_DS_CON_CH (1<<1)
+#define SIE_DS_SUS (1<<2)
+#define SIE_DS_SUS_CH (1<<3)
+#define SIE_DS_RST (1<<4)
+
+// SIE Device Set Address register
+#define SIE_DSA_DEV_EN (1<<7)
+
+// SIE Configue Device register
+#define SIE_CONF_DEVICE (1<<0)
+
+// Select Endpoint register
+#define SIE_SE_FE (1<<0)
+#define SIE_SE_ST (1<<1)
+#define SIE_SE_STP (1<<2)
+#define SIE_SE_PO (1<<3)
+#define SIE_SE_EPN (1<<4)
+#define SIE_SE_B_1_FULL (1<<5)
+#define SIE_SE_B_2_FULL (1<<6)
+
+// Set Endpoint Status command
+#define SIE_SES_ST (1<<0)
+#define SIE_SES_DA (1<<5)
+#define SIE_SES_RF_MO (1<<6)
+#define SIE_SES_CND_ST (1<<7)
+
+
+USBHAL * USBHAL::instance;
+
+static volatile int epComplete;
+static uint32_t endpointStallState;
+
+static void SIECommand(uint32_t command) {
+ // The command phase of a SIE transaction
+ LPC_USB->DevIntClr = CCEMPTY;
+ LPC_USB->CmdCode = SIE_CMD_CODE(SIE_COMMAND, command);
+ while (!(LPC_USB->DevIntSt & CCEMPTY));
+}
+
+static void SIEWriteData(uint8_t data) {
+ // The data write phase of a SIE transaction
+ LPC_USB->DevIntClr = CCEMPTY;
+ LPC_USB->CmdCode = SIE_CMD_CODE(SIE_WRITE, data);
+ while (!(LPC_USB->DevIntSt & CCEMPTY));
+}
+
+static uint8_t SIEReadData(uint32_t command) {
+ // The data read phase of a SIE transaction
+ LPC_USB->DevIntClr = CDFULL;
+ LPC_USB->CmdCode = SIE_CMD_CODE(SIE_READ, command);
+ while (!(LPC_USB->DevIntSt & CDFULL));
+ return (uint8_t)LPC_USB->CmdData;
+}
+
+static void SIEsetDeviceStatus(uint8_t status) {
+ // Write SIE device status register
+ SIECommand(SIE_CMD_SET_DEVICE_STATUS);
+ SIEWriteData(status);
+}
+
+static uint8_t SIEgetDeviceStatus(void) {
+ // Read SIE device status register
+ SIECommand(SIE_CMD_GET_DEVICE_STATUS);
+ return SIEReadData(SIE_CMD_GET_DEVICE_STATUS);
+}
+
+void SIEsetAddress(uint8_t address) {
+ // Write SIE device address register
+ SIECommand(SIE_CMD_SET_ADDRESS);
+ SIEWriteData((address & 0x7f) | SIE_DSA_DEV_EN);
+}
+
+static uint8_t SIEselectEndpoint(uint8_t endpoint) {
+ // SIE select endpoint command
+ SIECommand(SIE_CMD_SELECT_ENDPOINT(endpoint));
+ return SIEReadData(SIE_CMD_SELECT_ENDPOINT(endpoint));
+}
+
+static uint8_t SIEclearBuffer(void) {
+ // SIE clear buffer command
+ SIECommand(SIE_CMD_CLEAR_BUFFER);
+ return SIEReadData(SIE_CMD_CLEAR_BUFFER);
+}
+
+static void SIEvalidateBuffer(void) {
+ // SIE validate buffer command
+ SIECommand(SIE_CMD_VALIDATE_BUFFER);
+}
+
+static void SIEsetEndpointStatus(uint8_t endpoint, uint8_t status) {
+ // SIE set endpoint status command
+ SIECommand(SIE_CMD_SET_ENDPOINT_STATUS(endpoint));
+ SIEWriteData(status);
+}
+
+static uint16_t SIEgetFrameNumber(void) __attribute__ ((unused));
+static uint16_t SIEgetFrameNumber(void) {
+ // Read current frame number
+ uint16_t lowByte;
+ uint16_t highByte;
+
+ SIECommand(SIE_CMD_READ_FRAME_NUMBER);
+ lowByte = SIEReadData(SIE_CMD_READ_FRAME_NUMBER);
+ highByte = SIEReadData(SIE_CMD_READ_FRAME_NUMBER);
+
+ return (highByte << 8) | lowByte;
+}
+
+static void SIEconfigureDevice(void) {
+ // SIE Configure device command
+ SIECommand(SIE_CMD_CONFIGURE_DEVICE);
+ SIEWriteData(SIE_CONF_DEVICE);
+}
+
+static void SIEunconfigureDevice(void) {
+ // SIE Configure device command
+ SIECommand(SIE_CMD_CONFIGURE_DEVICE);
+ SIEWriteData(0);
+}
+
+static void SIEconnect(void) {
+ // Connect USB device
+ uint8_t status = SIEgetDeviceStatus();
+ SIEsetDeviceStatus(status | SIE_DS_CON);
+}
+
+
+static void SIEdisconnect(void) {
+ // Disconnect USB device
+ uint8_t status = SIEgetDeviceStatus();
+ SIEsetDeviceStatus(status & ~SIE_DS_CON);
+}
+
+
+static uint8_t selectEndpointClearInterrupt(uint8_t endpoint) {
+ // Implemented using using EP_INT_CLR.
+ LPC_USB->EpIntClr = EP(endpoint);
+ while (!(LPC_USB->DevIntSt & CDFULL));
+ return (uint8_t)LPC_USB->CmdData;
+}
+
+
+static void enableEndpointEvent(uint8_t endpoint) {
+ // Enable an endpoint interrupt
+ LPC_USB->EpIntEn |= EP(endpoint);
+}
+
+static void disableEndpointEvent(uint8_t endpoint) __attribute__ ((unused));
+static void disableEndpointEvent(uint8_t endpoint) {
+ // Disable an endpoint interrupt
+ LPC_USB->EpIntEn &= ~EP(endpoint);
+}
+
+static volatile uint32_t __attribute__((used)) dummyRead;
+uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
+ // Read from an OUT endpoint
+ uint32_t size;
+ uint32_t i;
+ uint32_t data = 0;
+ uint8_t offset;
+
+ LPC_USB->Ctrl = LOG_ENDPOINT(endpoint) | RD_EN;
+ while (!(LPC_USB->RxPLen & PKT_RDY));
+
+ size = LPC_USB->RxPLen & PKT_LNGTH_MASK;
+
+ offset = 0;
+
+ if (size > 0) {
+ for (i=0; i<size; i++) {
+ if (offset==0) {
+ // Fetch up to four bytes of data as a word
+ data = LPC_USB->RxData;
+ }
+
+ // extract a byte
+ *buffer = (data>>offset) & 0xff;
+ buffer++;
+
+ // move on to the next byte
+ offset = (offset + 8) % 32;
+ }
+ } else {
+ dummyRead = LPC_USB->RxData;
+ }
+
+ LPC_USB->Ctrl = 0;
+
+ if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) {
+ SIEselectEndpoint(endpoint);
+ SIEclearBuffer();
+ }
+
+ return size;
+}
+
+static void endpointWritecore(uint8_t endpoint, uint8_t *buffer, uint32_t size) {
+ // Write to an IN endpoint
+ uint32_t temp, data;
+ uint8_t offset;
+
+ LPC_USB->Ctrl = LOG_ENDPOINT(endpoint) | WR_EN;
+
+ LPC_USB->TxPLen = size;
+ offset = 0;
+ data = 0;
+
+ if (size>0) {
+ do {
+ // Fetch next data byte into a word-sized temporary variable
+ temp = *buffer++;
+
+ // Add to current data word
+ temp = temp << offset;
+ data = data | temp;
+
+ // move on to the next byte
+ offset = (offset + 8) % 32;
+ size--;
+
+ if ((offset==0) || (size==0)) {
+ // Write the word to the endpoint
+ LPC_USB->TxData = data;
+ data = 0;
+ }
+ } while (size>0);
+ } else {
+ LPC_USB->TxData = 0;
+ }
+
+ // Clear WR_EN to cover zero length packet case
+ LPC_USB->Ctrl=0;
+
+ SIEselectEndpoint(endpoint);
+ SIEvalidateBuffer();
+}
+
+USBHAL::USBHAL(void) {
+ // Disable IRQ
+ NVIC_DisableIRQ(USB_IRQn);
+
+ // fill in callback array
+ epCallback[0] = &USBHAL::EP1_OUT_callback;
+ epCallback[1] = &USBHAL::EP1_IN_callback;
+ epCallback[2] = &USBHAL::EP2_OUT_callback;
+ epCallback[3] = &USBHAL::EP2_IN_callback;
+ epCallback[4] = &USBHAL::EP3_OUT_callback;
+ epCallback[5] = &USBHAL::EP3_IN_callback;
+ epCallback[6] = &USBHAL::EP4_OUT_callback;
+ epCallback[7] = &USBHAL::EP4_IN_callback;
+ epCallback[8] = &USBHAL::EP5_OUT_callback;
+ epCallback[9] = &USBHAL::EP5_IN_callback;
+ epCallback[10] = &USBHAL::EP6_OUT_callback;
+ epCallback[11] = &USBHAL::EP6_IN_callback;
+ epCallback[12] = &USBHAL::EP7_OUT_callback;
+ epCallback[13] = &USBHAL::EP7_IN_callback;
+ epCallback[14] = &USBHAL::EP8_OUT_callback;
+ epCallback[15] = &USBHAL::EP8_IN_callback;
+ epCallback[16] = &USBHAL::EP9_OUT_callback;
+ epCallback[17] = &USBHAL::EP9_IN_callback;
+ epCallback[18] = &USBHAL::EP10_OUT_callback;
+ epCallback[19] = &USBHAL::EP10_IN_callback;
+ epCallback[20] = &USBHAL::EP11_OUT_callback;
+ epCallback[21] = &USBHAL::EP11_IN_callback;
+ epCallback[22] = &USBHAL::EP12_OUT_callback;
+ epCallback[23] = &USBHAL::EP12_IN_callback;
+ epCallback[24] = &USBHAL::EP13_OUT_callback;
+ epCallback[25] = &USBHAL::EP13_IN_callback;
+ epCallback[26] = &USBHAL::EP14_OUT_callback;
+ epCallback[27] = &USBHAL::EP14_IN_callback;
+ epCallback[28] = &USBHAL::EP15_OUT_callback;
+ epCallback[29] = &USBHAL::EP15_IN_callback;
+
+ // Enable power to USB device controller
+ LPC_SC->PCONP |= PCUSB;
+
+ // Enable USB clocks
+ LPC_USB->USBClkCtrl |= DEV_CLK_EN | AHB_CLK_EN | PORT_CLK_EN;
+ while ((LPC_USB->USBClkSt & (DEV_CLK_EN | AHB_CLK_EN | PORT_CLK_EN)) != (DEV_CLK_ON | AHB_CLK_ON | PORT_CLK_EN));
+
+ // Select port USB2
+ LPC_USB->StCtrl |= 3;
+
+
+ // Configure pin P0.31 to be USB2
+ LPC_IOCON->P0_31 &= ~0x07;
+ LPC_IOCON->P0_31 |= 0x01;
+
+ // Disconnect USB device
+ SIEdisconnect();
+
+ // Configure pin P0.14 to be Connect
+ LPC_IOCON->P0_14 &= ~0x07;
+ LPC_IOCON->P0_14 |= 0x03;
+
+ // Connect must be low for at least 2.5uS
+ wait(0.3);
+
+ // Set the maximum packet size for the control endpoints
+ realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
+ realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
+
+ // Attach IRQ
+ instance = this;
+ NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
+
+ // Enable interrupts for device events and EP0
+ LPC_USB->DevIntEn = EP_SLOW | DEV_STAT | FRAME;
+ enableEndpointEvent(EP0IN);
+ enableEndpointEvent(EP0OUT);
+}
+
+USBHAL::~USBHAL(void) {
+ // Ensure device disconnected
+ SIEdisconnect();
+ // Disable USB interrupts
+ NVIC_DisableIRQ(USB_IRQn);
+}
+
+void USBHAL::connect(void) {
+ NVIC_EnableIRQ(USB_IRQn);
+ // Connect USB device
+ SIEconnect();
+}
+
+void USBHAL::disconnect(void) {
+ NVIC_DisableIRQ(USB_IRQn);
+ // Disconnect USB device
+ SIEdisconnect();
+}
+
+void USBHAL::configureDevice(void) {
+ SIEconfigureDevice();
+}
+
+void USBHAL::unconfigureDevice(void) {
+ SIEunconfigureDevice();
+}
+
+void USBHAL::setAddress(uint8_t address) {
+ SIEsetAddress(address);
+}
+
+void USBHAL::EP0setup(uint8_t *buffer) {
+ endpointReadcore(EP0OUT, buffer);
+}
+
+void USBHAL::EP0read(void) {
+ // Not required
+}
+
+void USBHAL::EP0readStage(void) {
+ // Not required
+}
+
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
+ return endpointReadcore(EP0OUT, buffer);
+}
+
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
+ endpointWritecore(EP0IN, buffer, size);
+}
+
+void USBHAL::EP0getWriteResult(void) {
+ // Not required
+}
+
+void USBHAL::EP0stall(void) {
+ // This will stall both control endpoints
+ stallEndpoint(EP0OUT);
+}
+
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
+
+ //for isochronous endpoint, we don't wait an interrupt
+ if ((endpoint >> 1) % 3 || (endpoint >> 1) == 0) {
+ if (!(epComplete & EP(endpoint)))
+ return EP_PENDING;
+ }
+
+ *bytesRead = endpointReadcore(endpoint, buffer);
+ epComplete &= ~EP(endpoint);
+ return EP_COMPLETED;
+}
+
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
+ if (getEndpointStallState(endpoint)) {
+ return EP_STALLED;
+ }
+
+ epComplete &= ~EP(endpoint);
+
+ endpointWritecore(endpoint, data, size);
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
+ if (epComplete & EP(endpoint)) {
+ epComplete &= ~EP(endpoint);
+ return EP_COMPLETED;
+ }
+
+ return EP_PENDING;
+}
+
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
+ // Realise an endpoint
+ LPC_USB->DevIntClr = EP_RLZED;
+ LPC_USB->ReEp |= EP(endpoint);
+ LPC_USB->EpInd = endpoint;
+ LPC_USB->MaxPSize = maxPacket;
+
+ while (!(LPC_USB->DevIntSt & EP_RLZED));
+ LPC_USB->DevIntClr = EP_RLZED;
+
+ // Clear stall state
+ endpointStallState &= ~EP(endpoint);
+
+ enableEndpointEvent(endpoint);
+ return true;
+}
+
+void USBHAL::stallEndpoint(uint8_t endpoint) {
+ // Stall an endpoint
+ if ( (endpoint==EP0IN) || (endpoint==EP0OUT) ) {
+ // Conditionally stall both control endpoints
+ SIEsetEndpointStatus(EP0OUT, SIE_SES_CND_ST);
+ } else {
+ SIEsetEndpointStatus(endpoint, SIE_SES_ST);
+
+ // Update stall state
+ endpointStallState |= EP(endpoint);
+ }
+}
+
+void USBHAL::unstallEndpoint(uint8_t endpoint) {
+ // Unstall an endpoint. The endpoint will also be reinitialised
+ SIEsetEndpointStatus(endpoint, 0);
+
+ // Update stall state
+ endpointStallState &= ~EP(endpoint);
+}
+
+bool USBHAL::getEndpointStallState(uint8_t endpoint) {
+ // Returns true if endpoint stalled
+ return endpointStallState & EP(endpoint);
+}
+
+void USBHAL::remoteWakeup(void) {
+ // Remote wakeup
+ uint8_t status;
+
+ // Enable USB clocks
+ LPC_USB->USBClkCtrl |= DEV_CLK_EN | AHB_CLK_EN;
+ while (LPC_USB->USBClkSt != (DEV_CLK_ON | AHB_CLK_ON));
+
+ status = SIEgetDeviceStatus();
+ SIEsetDeviceStatus(status & ~SIE_DS_SUS);
+}
+
+void USBHAL::_usbisr(void) {
+ instance->usbisr();
+}
+
+
+void USBHAL::usbisr(void) {
+ uint8_t devStat;
+
+ if (LPC_USB->DevIntSt & FRAME) {
+ // Start of frame event
+ SOF(SIEgetFrameNumber());
+ // Clear interrupt status flag
+ LPC_USB->DevIntClr = FRAME;
+ }
+
+ if (LPC_USB->DevIntSt & DEV_STAT) {
+ // Device Status interrupt
+ // Must clear the interrupt status flag before reading the device status from the SIE
+ LPC_USB->DevIntClr = DEV_STAT;
+
+ // Read device status from SIE
+ devStat = SIEgetDeviceStatus();
+ //printf("devStat: %d\r\n", devStat);
+
+ if (devStat & SIE_DS_SUS_CH) {
+ // Suspend status changed
+ if((devStat & SIE_DS_SUS) != 0) {
+ suspendStateChanged(0);
+ }
+ }
+
+ if (devStat & SIE_DS_RST) {
+ // Bus reset
+ if((devStat & SIE_DS_SUS) == 0) {
+ suspendStateChanged(1);
+ }
+ busReset();
+ }
+ }
+
+ if (LPC_USB->DevIntSt & EP_SLOW) {
+ // (Slow) Endpoint Interrupt
+
+ // Process each endpoint interrupt
+ if (LPC_USB->EpIntSt & EP(EP0OUT)) {
+ if (selectEndpointClearInterrupt(EP0OUT) & SIE_SE_STP) {
+ // this is a setup packet
+ EP0setupCallback();
+ } else {
+ EP0out();
+ }
+ LPC_USB->DevIntClr = EP_SLOW;
+ }
+
+ if (LPC_USB->EpIntSt & EP(EP0IN)) {
+ selectEndpointClearInterrupt(EP0IN);
+ LPC_USB->DevIntClr = EP_SLOW;
+ EP0in();
+ }
+
+ for (uint8_t num = 2; num < 16*2; num++) {
+ if (LPC_USB->EpIntSt & EP(num)) {
+ selectEndpointClearInterrupt(num);
+ epComplete |= EP(num);
+ LPC_USB->DevIntClr = EP_SLOW;
+ if ((instance->*(epCallback[num - 2]))()) {
+ epComplete &= ~EP(num);
+ }
+ }
+ }
+ }
+}
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_Maxim.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_Maxim.cpp
new file mode 100644
index 000000000..13e193cd2
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_Maxim.cpp
@@ -0,0 +1,473 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+#if defined(TARGET_Maxim)
+
+#include "USBHAL.h"
+#include "usb_regs.h"
+#include "clkman_regs.h"
+
+#define CONNECT_INTS (MXC_F_USB_DEV_INTEN_BRST | MXC_F_USB_DEV_INTEN_SETUP | MXC_F_USB_DEV_INTEN_EP_IN | MXC_F_USB_DEV_INTEN_EP_OUT | MXC_F_USB_DEV_INTEN_DMA_ERR)
+
+USBHAL *USBHAL::instance;
+
+typedef struct {
+ volatile uint32_t buf0_desc;
+ volatile uint32_t buf0_address;
+ volatile uint32_t buf1_desc;
+ volatile uint32_t buf1_address;
+} ep_buffer_t;
+
+typedef struct {
+ ep_buffer_t out_buffer;
+ ep_buffer_t in_buffer;
+} ep0_buffer_t;
+
+typedef struct {
+ ep0_buffer_t ep0;
+ ep_buffer_t ep[MXC_USB_NUM_EP - 1];
+} ep_buffer_descriptor_t;
+
+// Static storage for endpoint buffer descriptor table. Must be 512 byte alligned for DMA.
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma data_alignment = 512
+#else
+__attribute__ ((aligned (512)))
+#endif
+ep_buffer_descriptor_t ep_buffer_descriptor;
+
+// static storage for temporary data buffers. Must be 32 byte alligned.
+#ifdef __IAR_SYSTEMS_ICC__
+#pragma data_alignment = 4
+#else
+__attribute__ ((aligned (4)))
+#endif
+static uint8_t aligned_buffer[NUMBER_OF_LOGICAL_ENDPOINTS][MXC_USB_MAX_PACKET];
+
+// contorl packet state
+static enum {
+ CTRL_NONE = 0,
+ CTRL_SETUP,
+ CTRL_OUT,
+ CTRL_IN,
+} control_state;
+
+USBHAL::USBHAL(void)
+{
+ NVIC_DisableIRQ(USB_IRQn);
+
+ // The PLL must be enabled for USB
+ MBED_ASSERT(MXC_CLKMAN->clk_config & MXC_F_CLKMAN_CLK_CONFIG_PLL_ENABLE);
+
+ // Enable the USB clock
+ MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_USB_GATE_N;
+
+ // reset the device
+ MXC_USB->cn = 0;
+ MXC_USB->cn = 1;
+ MXC_USB->dev_inten = 0;
+ MXC_USB->dev_cn = 0;
+ MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST;
+ MXC_USB->dev_cn = 0;
+
+ // fill in callback arrays
+ epCallback[EP0OUT] = NULL;
+ epCallback[EP0IN] = NULL;
+ epCallback[EP1OUT] = &USBHAL::EP1_OUT_callback;
+ epCallback[EP1IN ] = &USBHAL::EP1_IN_callback;
+ epCallback[EP2OUT] = &USBHAL::EP2_OUT_callback;
+ epCallback[EP2IN ] = &USBHAL::EP2_IN_callback;
+ epCallback[EP3OUT] = &USBHAL::EP3_OUT_callback;
+ epCallback[EP3IN ] = &USBHAL::EP3_IN_callback;
+ epCallback[EP4OUT] = &USBHAL::EP4_OUT_callback;
+ epCallback[EP4IN ] = &USBHAL::EP4_IN_callback;
+ epCallback[EP5OUT] = &USBHAL::EP5_OUT_callback;
+ epCallback[EP5IN ] = &USBHAL::EP5_IN_callback;
+ epCallback[EP6OUT] = &USBHAL::EP6_OUT_callback;
+ epCallback[EP6IN ] = &USBHAL::EP6_IN_callback;
+ epCallback[EP7OUT] = &USBHAL::EP7_OUT_callback;
+ epCallback[EP7IN ] = &USBHAL::EP7_IN_callback;
+
+ // clear driver state
+ control_state = CTRL_NONE;
+
+ // set the descriptor location
+ MXC_USB->ep_base = (uint32_t)&ep_buffer_descriptor;
+
+ // attach IRQ handler and enable interrupts
+ instance = this;
+ NVIC_SetVector(USB_IRQn, (uint32_t)&_usbisr);
+ NVIC_EnableIRQ(USB_IRQn);
+}
+
+USBHAL::~USBHAL(void)
+{
+ MXC_USB->dev_cn = MXC_F_USB_DEV_CN_URST;
+ MXC_USB->dev_cn = 0;
+ MXC_USB->cn = 0;
+}
+
+void USBHAL::connect(void)
+{
+ // enable interrupts
+ MXC_USB->dev_inten |= CONNECT_INTS;
+
+ // allow interrupts on ep0
+ MXC_USB->ep[0] |= MXC_F_USB_EP_INT_EN;
+
+ // pullup enable
+ MXC_USB->dev_cn |= (MXC_F_USB_DEV_CN_CONNECT | MXC_F_USB_DEV_CN_FIFO_MODE);
+}
+
+void USBHAL::disconnect(void)
+{
+ // disable interrupts
+ MXC_USB->dev_inten &= ~CONNECT_INTS;
+
+ // disable pullup
+ MXC_USB->dev_cn &= ~MXC_F_USB_DEV_CN_CONNECT;
+}
+
+void USBHAL::configureDevice(void)
+{
+ // do nothing
+}
+
+void USBHAL::unconfigureDevice(void)
+{
+ // reset endpoints
+ for (int i = 0; i < MXC_USB_NUM_EP; i++) {
+ // Disable endpoint and clear the data toggle
+ MXC_USB->ep[i] &= ~MXC_F_USB_EP_DIR;
+ MXC_USB->ep[i] |= MXC_F_USB_EP_DT;
+ }
+}
+
+void USBHAL::setAddress(uint8_t address)
+{
+ // do nothing
+}
+
+void USBHAL::remoteWakeup(void)
+{
+ // do nothing
+}
+
+static ep_buffer_t *get_desc(uint8_t endpoint)
+{
+ uint8_t epnum = EP_NUM(endpoint);
+ ep_buffer_t *desc;
+
+ if (epnum == 0) {
+ if (IN_EP(endpoint)) {
+ desc = &ep_buffer_descriptor.ep0.in_buffer;
+ } else {
+ desc = &ep_buffer_descriptor.ep0.out_buffer;
+ }
+ } else {
+ desc = &ep_buffer_descriptor.ep[epnum - 1];
+ }
+
+ return desc;
+}
+
+void USBHAL::EP0setup(uint8_t *buffer)
+{
+ memcpy(buffer, (void*)&MXC_USB->setup0, 8); // setup packet is fixed at 8 bytes
+}
+
+void USBHAL::EP0read(void)
+{
+ if (control_state == CTRL_IN) {
+ // This is the status stage. ACK.
+ MXC_USB->ep[0] |= MXC_F_USB_EP_ST_ACK;
+ control_state = CTRL_NONE;
+ return;
+ }
+
+ control_state = CTRL_OUT;
+
+ endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
+}
+
+void USBHAL::EP0readStage(void)
+{
+ // do nothing
+}
+
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer)
+{
+ uint32_t size;
+
+ if (MXC_USB->out_owner & 1) {
+ return 0;
+ }
+
+ // get the packet length and contents
+ ep_buffer_t *desc = get_desc(EP0OUT);
+ size = desc->buf0_desc;
+ memcpy(buffer, aligned_buffer[0], size);
+
+ return size;
+}
+
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size)
+{
+ if ((size == 0) && (control_state != CTRL_IN)) {
+ // This is a status stage ACK. Handle in hardware.
+ MXC_USB->ep[0] |= MXC_F_USB_EP_ST_ACK;
+ control_state = CTRL_NONE;
+ return;
+ }
+
+ control_state = CTRL_IN;
+
+ endpointWrite(EP0IN, buffer, size);
+}
+
+void USBHAL::EP0stall(void)
+{
+ stallEndpoint(0);
+}
+
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize)
+{
+ uint8_t epnum = EP_NUM(endpoint);
+
+ if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || IN_EP(endpoint)) {
+ return EP_INVALID;
+ }
+
+ if (maximumSize > MXC_USB_MAX_PACKET) {
+ return EP_INVALID;
+ }
+
+ uint32_t mask = (1 << epnum);
+ if (MXC_USB->out_owner & mask) {
+ return EP_INVALID;
+ }
+
+ ep_buffer_t *desc = get_desc(endpoint);
+ desc->buf0_desc = maximumSize;
+ desc->buf0_address = (uint32_t)aligned_buffer[epnum];
+
+ MXC_USB->out_owner = mask;
+
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *data, uint32_t *bytesRead)
+{
+ if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || IN_EP(endpoint)) {
+ return EP_INVALID;
+ }
+
+ uint32_t mask = (1 << EP_NUM(endpoint));
+ if (MXC_USB->out_owner & mask) {
+ return EP_PENDING;
+ }
+
+ // get the packet length and contents
+ ep_buffer_t *desc = get_desc(endpoint);
+ *bytesRead = desc->buf0_desc;
+ memcpy(data, aligned_buffer[EP_NUM(endpoint)], *bytesRead);
+
+ return EP_COMPLETED;
+}
+
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
+{
+ uint8_t epnum = EP_NUM(endpoint);
+
+ if ((endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS) || OUT_EP(endpoint)) {
+ return EP_INVALID;
+ }
+
+ if (size > MXC_USB_MAX_PACKET) {
+ return EP_INVALID;
+ }
+
+ uint32_t mask = (1 << epnum);
+ if (MXC_USB->in_owner & mask) {
+ return EP_INVALID;
+ }
+
+ memcpy(aligned_buffer[epnum], data, size);
+
+ ep_buffer_t *desc = get_desc(endpoint);
+ desc->buf0_desc = size;
+ desc->buf0_address = (uint32_t)aligned_buffer[epnum];
+
+ // start the DMA
+ MXC_USB->in_owner = mask;
+
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint)
+{
+ uint32_t mask = (1 << EP_NUM(endpoint));
+ if (MXC_USB->in_owner & mask) {
+ return EP_PENDING;
+ }
+
+ return EP_COMPLETED;
+}
+
+void USBHAL::stallEndpoint(uint8_t endpoint)
+{
+ uint8_t epnum = EP_NUM(endpoint);
+
+ if (epnum == 0) {
+ MXC_USB->ep[epnum] |= MXC_F_USB_EP_ST_STALL;
+ }
+
+ MXC_USB->ep[epnum] |= MXC_F_USB_EP_STALL;
+}
+
+void USBHAL::unstallEndpoint(uint8_t endpoint)
+{
+ MXC_USB->ep[EP_NUM(endpoint)] &= ~MXC_F_USB_EP_STALL;
+}
+
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t options)
+{
+ uint8_t epnum = EP_NUM(endpoint);
+ uint32_t ep_ctrl;
+
+ if (epnum >= NUMBER_OF_PHYSICAL_ENDPOINTS) {
+ return false;
+ }
+
+ if (IN_EP(endpoint)) {
+ ep_ctrl = (MXC_V_USB_EP_DIR_IN << MXC_F_USB_EP_DIR_POS);
+ } else {
+ ep_ctrl = (MXC_S_USB_EP_DIR_OUT << MXC_F_USB_EP_DIR_POS);
+ }
+
+ ep_ctrl |= (MXC_F_USB_EP_DT | MXC_F_USB_EP_INT_EN);
+
+ MXC_USB->ep[epnum] = ep_ctrl;
+
+ return true;
+}
+
+bool USBHAL::getEndpointStallState(unsigned char endpoint)
+{
+ return !!(MXC_USB->ep[endpoint] & MXC_F_USB_EP_STALL);
+}
+
+void USBHAL::_usbisr(void)
+{
+ instance->usbisr();
+}
+
+void USBHAL::usbisr(void)
+{
+ // get and clear irqs
+ uint32_t irq_flags = MXC_USB->dev_intfl;
+ MXC_USB->dev_intfl = irq_flags;
+
+ // process only enabled interrupts
+ irq_flags &= MXC_USB->dev_inten;
+
+ // suspend
+ if (irq_flags & MXC_F_USB_DEV_INTFL_SUSP) {
+ suspendStateChanged(1);
+ }
+
+ // bus reset
+ if (irq_flags & MXC_F_USB_DEV_INTFL_BRST) {
+
+ // reset endpoints
+ for (int i = 0; i < MXC_USB_NUM_EP; i++) {
+ // Disable endpoint and clear the data toggle
+ MXC_USB->ep[i] &= ~MXC_F_USB_EP_DIR;
+ MXC_USB->ep[i] |= MXC_F_USB_EP_DT;
+ }
+
+ // clear driver state
+ control_state = CTRL_NONE;
+
+ busReset();
+
+ // no need to process events after reset
+ return;
+ }
+
+ // Setup packet
+ if (irq_flags & MXC_F_USB_DEV_INTFL_SETUP) {
+ control_state = CTRL_SETUP;
+ EP0setupCallback();
+ }
+
+ // IN packets
+ if (irq_flags & MXC_F_USB_DEV_INTFL_EP_IN) {
+ // get and clear IN irqs
+ uint32_t in_irqs = MXC_USB->in_int;
+ MXC_USB->in_int = in_irqs;
+
+ if (in_irqs & 1) {
+ EP0in();
+ }
+
+ for (uint8_t epnum = 1; epnum < NUMBER_OF_LOGICAL_ENDPOINTS; epnum++) {
+ uint32_t irq_mask = (1 << epnum);
+ if (in_irqs & irq_mask) {
+ uint8_t endpoint = (epnum << 1) | DIR_IN;
+ (instance->*(epCallback[endpoint]))();
+ }
+ }
+ }
+
+ // OUT packets
+ if (irq_flags & MXC_F_USB_DEV_INTFL_EP_OUT) {
+ // get and clear OUT irqs
+ uint32_t out_irqs = MXC_USB->out_int;
+ MXC_USB->out_int = out_irqs;
+
+ if (out_irqs & 1) {
+ EP0out();
+ }
+
+ for (uint8_t epnum = 1; epnum < NUMBER_OF_LOGICAL_ENDPOINTS; epnum++) {
+ uint32_t irq_mask = (1 << epnum);
+ if (out_irqs & irq_mask) {
+ uint8_t endpoint = (epnum << 1) | DIR_OUT;
+ (instance->*(epCallback[endpoint]))();
+ }
+ }
+ }
+}
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp
new file mode 100644
index 000000000..5eee82a64
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_RZ_A1H.cpp
@@ -0,0 +1,1497 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person
+* obtaining a copy of this software and associated documentation
+* files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use,
+* copy, modify, merge, publish, distribute, sublicense, and/or
+* sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following
+* conditions:
+*
+* The above copyright notice and this permission notice shall be
+* included in all copies or substantial portions of the
+* Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
+* KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
+* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+* PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined(TARGET_RZ_A1H)
+
+/*
+ This class can use the pipe1, pipe3 and pipe6 only. You should
+ re-program this class if you wanted to use other pipe.
+ */
+
+/*************************************************************************/
+extern "C"
+{
+#include "r_typedefs.h"
+#include "iodefine.h"
+}
+#include "USBHAL.h"
+#include "devdrv_usb_function_api.h"
+#include "usb_iobitmask.h"
+#include "rza_io_regrw.h"
+#include "USBDevice_Types.h"
+#include "usb_function_setting.h"
+
+
+/*************************************************************************/
+/* constants */
+const struct PIPECFGREC {
+ uint16_t endpoint;
+ uint16_t pipesel;
+ uint16_t pipecfg;
+ uint16_t pipebuf;
+ uint16_t pipemaxp;
+ uint16_t pipeperi;
+} def_pipecfg[] = {
+ /*EP0OUT and EP0IN are configured by USB IP*/
+ {
+ EP1OUT, /*EP1: Host -> Func, INT*/
+ 6 | USB_FUNCTION_D0FIFO_USE,
+ USB_FUNCTION_INTERRUPT |
+ USB_FUNCTION_BFREOFF |
+ USB_FUNCTION_DBLBOFF |
+ USB_FUNCTION_CNTMDON |
+ USB_FUNCTION_SHTNAKOFF |
+ USB_FUNCTION_DIR_P_OUT |
+ USB_FUNCTION_EP1,
+ ( ( ( 64) / 64 - 1 ) << 10 ) | 0x04u,
+ MAX_PACKET_SIZE_EP1,
+ DEVDRV_USBF_OFF |
+ ( 3 << USB_PIPEPERI_IITV_SHIFT ),
+ },
+ {
+ EP1IN, /*EP1: Host <- Func, INT*/
+ 7 | USB_FUNCTION_D1FIFO_USE,
+ USB_FUNCTION_INTERRUPT |
+ USB_FUNCTION_BFREOFF |
+ USB_FUNCTION_DBLBOFF |
+ USB_FUNCTION_CNTMDOFF |
+ USB_FUNCTION_SHTNAKOFF |
+ USB_FUNCTION_DIR_P_IN |
+ USB_FUNCTION_EP1,
+ ( ( ( 64) / 64 - 1 ) << 10 ) | 0x05u,
+ MAX_PACKET_SIZE_EP1,
+ DEVDRV_USBF_OFF |
+ ( 3 << USB_PIPEPERI_IITV_SHIFT ),
+ },
+ {
+ EP2OUT, /*EP2: Host -> Func, BULK*/
+ 3 | USB_FUNCTION_D0FIFO_USE,
+ USB_FUNCTION_BULK |
+ USB_FUNCTION_BFREOFF |
+ USB_FUNCTION_DBLBON |
+ USB_FUNCTION_CNTMDON |
+ USB_FUNCTION_SHTNAKON |
+ USB_FUNCTION_DIR_P_OUT |
+ USB_FUNCTION_EP2,
+ ( ( (2048) / 64 - 1 ) << 10 ) | 0x30u,
+ MAX_PACKET_SIZE_EP2,
+ DEVDRV_USBF_OFF |
+ ( 0 << USB_PIPEPERI_IITV_SHIFT ),
+ },
+ {
+ EP2IN, /*EP2: Host <- Func, BULK*/
+ 4 | USB_FUNCTION_D1FIFO_USE,
+ USB_FUNCTION_BULK |
+ USB_FUNCTION_BFREOFF |
+ USB_FUNCTION_DBLBOFF |
+ USB_FUNCTION_CNTMDON |
+ USB_FUNCTION_SHTNAKOFF |
+ USB_FUNCTION_DIR_P_IN |
+ USB_FUNCTION_EP2,
+ ( ( (2048) / 64 - 1 ) << 10 ) | 0x50u,
+ MAX_PACKET_SIZE_EP2,
+ DEVDRV_USBF_OFF |
+ ( 0 << USB_PIPEPERI_IITV_SHIFT ),
+ },
+ {
+ EP3OUT, /*EP3: Host -> Func, ISO*/
+ 1 | USB_FUNCTION_D0FIFO_USE,
+ USB_FUNCTION_ISO |
+ USB_FUNCTION_BFREOFF |
+ USB_FUNCTION_DBLBON |
+ USB_FUNCTION_CNTMDOFF |
+ USB_FUNCTION_SHTNAKON |
+ USB_FUNCTION_DIR_P_OUT |
+ USB_FUNCTION_EP3,
+ ( ( ( 512) / 64 - 1 ) << 10 ) | 0x10u,
+ MAX_PACKET_SIZE_EP3,
+ DEVDRV_USBF_OFF |
+ ( 0 << USB_PIPEPERI_IITV_SHIFT ),
+ },
+ {
+ EP3IN, /*EP3: Host <- Func, ISO*/
+ 2 | USB_FUNCTION_D1FIFO_USE,
+ USB_FUNCTION_ISO |
+ USB_FUNCTION_BFREOFF |
+ USB_FUNCTION_DBLBON |
+ USB_FUNCTION_CNTMDOFF |
+ USB_FUNCTION_SHTNAKOFF |
+ USB_FUNCTION_DIR_P_IN |
+ USB_FUNCTION_EP3,
+ ( ( ( 512) / 64 - 1 ) << 10 ) | 0x20u,
+ MAX_PACKET_SIZE_EP3,
+ DEVDRV_USBF_OFF |
+ ( 0 << USB_PIPEPERI_IITV_SHIFT ),
+ },
+ { /*terminator*/
+ 0, 0, 0, 0, 0,
+ },
+};
+
+
+/*************************************************************************/
+/* workareas */
+USBHAL * USBHAL::instance;
+
+static IRQn_Type int_id; /* interrupt ID */
+static uint16_t int_level; /* initerrupt level */
+static uint16_t clock_mode; /* input clock selector */
+static uint16_t mode; /* USB speed (HIGH/FULL) */
+
+//static DigitalOut *usbx_en;
+
+static uint16_t EP0_read_status;
+static uint16_t EPx_read_status;
+
+static uint16_t setup_buffer[MAX_PACKET_SIZE_EP0 / 2];
+
+/* 0: not used / other: a pipe number to use recv_buffer*/
+static uint8_t recv_buffer[MAX_PACKET_SIZE_EPBULK];
+volatile static uint16_t recv_error;
+
+
+/*************************************************************************/
+/* prototypes for C */
+extern "C" {
+ void usbx_function_BRDYInterruptPIPE0 (uint16_t status, uint16_t intenb,
+ USBHAL *object, void (USBHAL::*EP0func)(void));
+
+ void usbx_function_BRDYInterrupt (uint16_t status, uint16_t intenb,
+ USBHAL *object, bool (USBHAL::*epCallback[])(void));
+
+ void usbx_function_NRDYInterruptPIPE0(uint16_t status, uint16_t intenb,
+ USBHAL *object, void (USBHAL::*EP0func)(void));
+
+ void usbx_function_NRDYInterrupt (uint16_t status, uint16_t intenb,
+ USBHAL *object, bool (USBHAL::*epCallback[])(void));
+
+ void usbx_function_BEMPInterruptPIPE0(uint16_t status, uint16_t intenb,
+ USBHAL *object, void (USBHAL::*EP0func)(void));
+
+ void usbx_function_BEMPInterrupt (uint16_t status, uint16_t intenb,
+ USBHAL *object, bool (USBHAL::*epCallback[])(void));
+}
+
+
+/*************************************************************************/
+/* macros */
+
+/******************************************************************************
+ * Function Name: usbx_function_BRDYInterruptPIPE0
+ * Description : Executes BRDY interrupt for pipe0.
+ * Arguments : uint16_t status ; BRDYSTS Register Value
+ * : uint16_t intenb ; BRDYENB Register Value
+ * Return Value : none
+ *****************************************************************************/
+extern "C" {
+ void usbx_function_BRDYInterruptPIPE0 (
+ uint16_t status,
+ uint16_t intenb,
+ USBHAL *object,
+ void (USBHAL::*EP0func)(void)
+ )
+ {
+ volatile uint16_t dumy_sts;
+ uint16_t read_status;
+
+ USB20X.BRDYSTS =
+ (uint16_t)~g_usbx_function_bit_set[USB_FUNCTION_PIPE0];
+ RZA_IO_RegWrite_16(
+ &USB20X.CFIFOSEL, USB_FUNCTION_PIPE0,
+ USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE);
+
+ g_usbx_function_PipeDataSize[USB_FUNCTION_PIPE0] =
+ g_usbx_function_data_count[USB_FUNCTION_PIPE0];
+
+ read_status = usbx_function_read_buffer_c(USB_FUNCTION_PIPE0);
+
+ g_usbx_function_PipeDataSize[USB_FUNCTION_PIPE0] -=
+ g_usbx_function_data_count[USB_FUNCTION_PIPE0];
+
+ switch (read_status) {
+ case USB_FUNCTION_READING: /* Continue of data read */
+ case USB_FUNCTION_READEND: /* End of data read */
+ /* PID = BUF */
+ usbx_function_set_pid_buf(USB_FUNCTION_PIPE0);
+
+ /*callback*/
+ (object->*EP0func)();
+ break;
+
+ case USB_FUNCTION_READSHRT: /* End of data read */
+ usbx_function_disable_brdy_int(USB_FUNCTION_PIPE0);
+ /* PID = BUF */
+ usbx_function_set_pid_buf(USB_FUNCTION_PIPE0);
+
+ /*callback*/
+ (object->*EP0func)();
+ break;
+
+ case USB_FUNCTION_READOVER: /* FIFO access error */
+ /* Buffer Clear */
+ USB20X.CFIFOCTR = USB_FUNCTION_BITBCLR;
+ usbx_function_disable_brdy_int(USB_FUNCTION_PIPE0);
+ /* Req Error */
+ usbx_function_set_pid_stall(USB_FUNCTION_PIPE0);
+
+ /*callback*/
+ (object->*EP0func)();
+ break;
+
+ case DEVDRV_USBF_FIFOERROR: /* FIFO access error */
+ default:
+ usbx_function_disable_brdy_int(USB_FUNCTION_PIPE0);
+ /* Req Error */
+ usbx_function_set_pid_stall(USB_FUNCTION_PIPE0);
+ break;
+ }
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB20X.BRDYSTS;
+ }
+}
+
+
+/******************************************************************************
+ * Function Name: usbx_function_BRDYInterrupt
+ * Description : Executes BRDY interrupt uxclude pipe0.
+ * Arguments : uint16_t status ; BRDYSTS Register Value
+ * : uint16_t intenb ; BRDYENB Register Value
+ * Return Value : none
+ *****************************************************************************/
+extern "C" {
+ void usbx_function_BRDYInterrupt(
+ uint16_t status,
+ uint16_t intenb,
+ USBHAL *object,
+ bool (USBHAL::*epCallback[])(void)
+ )
+ {
+ volatile uint16_t dumy_sts;
+
+ /**************************************************************
+ * Function Name: usbx_function_brdy_int
+ * Description : Executes BRDY interrupt(USB_FUNCTION_PIPE1-9).
+ * : According to the pipe that interrupt is generated in,
+ * : reads/writes buffer allocated in the pipe.
+ * : This function is executed in the BRDY
+ * : interrupt handler. This function
+ * : clears BRDY interrupt status and BEMP
+ * : interrupt status.
+ * Arguments : uint16_t Status ; BRDYSTS Register Value
+ * : uint16_t Int_enbl ; BRDYENB Register Value
+ * Return Value : none
+ *************************************************************/
+ /* copied from usbx_function_intrn.c */
+ uint32_t int_sense = 0;
+ uint16_t pipe;
+ uint16_t pipebit;
+ uint16_t ep;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) {
+ pipebit = g_usbx_function_bit_set[pipe];
+
+ if ((status & pipebit) && (intenb & pipebit)) {
+ USB20X.BRDYSTS = (uint16_t)~pipebit;
+ USB20X.BEMPSTS = (uint16_t)~pipebit;
+
+ switch (g_usbx_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) {
+ case USB_FUNCTION_D0FIFO_DMA:
+ if (g_usbx_function_DmaStatus[USB_FUNCTION_D0FIFO] != USB_FUNCTION_DMA_READY) {
+ /*now, DMA is not supported*/
+ usbx_function_dma_interrupt_d0fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(
+ &g_usbx_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) {
+ /*now, DMA is not supported*/
+ usbx_function_read_dma(pipe);
+ usbx_function_disable_brdy_int(pipe);
+ } else {
+ USB20X.D0FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ if (g_usbx_function_DmaStatus[USB_FUNCTION_D1FIFO] != USB_FUNCTION_DMA_READY) {
+ /*now, DMA is not supported*/
+ usbx_function_dma_interrupt_d1fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(
+ &g_usbx_function_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0) {
+ /*now, DMA is not supported*/
+ usbx_function_read_dma(pipe);
+ usbx_function_disable_brdy_int(pipe);
+ } else {
+ USB20X.D1FIFOCTR = USB_FUNCTION_BITBCLR;
+ g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+ }
+ break;
+
+ default:
+ ep = (g_usbx_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT;
+ ep <<= 1;
+ if (RZA_IO_RegRead_16(
+ &g_usbx_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) {
+ /* read */
+ EPx_read_status = DEVDRV_USBF_PIPE_WAIT;
+ (object->*(epCallback[ep - 2])) ();
+ EPx_read_status = DEVDRV_USBF_PIPE_DONE;
+ } else {
+ /* write */
+ EPx_read_status = DEVDRV_USBF_PIPE_WAIT;
+ (object->*(epCallback[ep - 2 + 1])) ();
+ EPx_read_status = DEVDRV_USBF_PIPE_DONE;
+ usbx_function_write_buffer(pipe);
+ }
+ }
+ }
+ }
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB20X.BRDYSTS;
+ }
+}
+
+
+/******************************************************************************
+ * Function Name: usbx_function_NRDYInterruptPIPE0
+ * Description : Executes NRDY interrupt for pipe0.
+ * Arguments : uint16_t status ; NRDYSTS Register Value
+ * : uint16_t intenb ; NRDYENB Register Value
+ * Return Value : none
+ *****************************************************************************/
+extern "C" {
+ void usbx_function_NRDYInterruptPIPE0(
+ uint16_t status,
+ uint16_t intenb,
+ USBHAL *object,
+ void (USBHAL::*EP0func)(void)
+ )
+ {
+ volatile uint16_t dumy_sts;
+
+ USB20X.NRDYSTS =
+ (uint16_t)~g_usbx_function_bit_set[USB_FUNCTION_PIPE0];
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB20X.NRDYSTS;
+ }
+}
+
+
+/******************************************************************************
+ * Function Name: usbx_function_NRDYInterrupt
+ * Description : Executes NRDY interrupt exclude pipe0.
+ * Arguments : uint16_t status ; NRDYSTS Register Value
+ * : uint16_t intenb ; NRDYENB Register Value
+ * Return Value : none
+ *****************************************************************************/
+extern "C" {
+ void usbx_function_NRDYInterrupt(
+ uint16_t status,
+ uint16_t intenb,
+ USBHAL *object,
+ bool (USBHAL::*epCallback[])(void)
+ )
+ {
+ volatile uint16_t dumy_sts;
+
+ /**************************************************************
+ * Function Name: usbx_function_nrdy_int
+ * Description : Executes NRDY interrupt(USB_FUNCTION_PIPE1-9).
+ * : Checks NRDY interrupt cause by PID. When the cause if STALL,
+ * : regards the pipe state as STALL and ends the processing.
+ * : Then the cause is not STALL, increments the error count to
+ * : communicate again. When the error count is 3, determines
+ * : the pipe state as DEVDRV_USBF_PIPE_NORES and ends the processing.
+ * : This function is executed in the NRDY interrupt handler.
+ * : This function clears NRDY interrupt status.
+ * Arguments : uint16_t status ; NRDYSTS Register Value
+ * : uint16_t int_enb ; NRDYENB Register Value
+ * Return Value : none
+ *************************************************************/
+ /* copied from usbx_function_intrn.c */
+#if 0
+ uint16_t usefifo;
+#endif
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+#if 0
+ uint16_t mbw;
+ uint32_t size;
+#endif
+ uint16_t ep;
+
+ bitcheck = (uint16_t)(status & intenb);
+
+ USB20X.NRDYSTS = (uint16_t)~status;
+
+
+ if (RZA_IO_RegRead_16(&USB20X.SYSCFG0, USB_SYSCFG_DCFM_SHIFT, USB_SYSCFG_DCFM) == 1) {
+ /* USB HOST */
+ /* not support */
+
+ } else {
+ /* USB Function */
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) {
+ if ((bitcheck&g_usbx_function_bit_set[pipe]) != g_usbx_function_bit_set[pipe]) {
+ continue;
+ }
+
+ if (g_usbx_function_pipe_status[pipe] != DEVDRV_USBF_PIPE_WAIT) {
+ continue;
+ }
+
+#if 0
+ usbx_function_set_pid_nak(pipe);
+
+ size = (uint32_t)g_usbx_function_data_count[pipe];
+ mbw = usbx_function_get_mbw(
+ size, (uint32_t)g_usbx_function_data_pointer[pipe]);
+
+ usefifo = (uint16_t)(g_usbx_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE);
+ switch (usefifo) {
+
+ case USB_FUNCTION_D0FIFO_USE:
+ usbx_function_set_curpipe(
+ pipe, USB_FUNCTION_D0USE, DEVDRV_USBF_NO, mbw);
+ USB20X.D0FIFOCTR = USB_FUNCTION_BITBCLR;
+ break;
+
+ case USB_FUNCTION_D1FIFO_USE:
+ usbx_function_set_curpipe(
+ pipe, USB_FUNCTION_D1USE, DEVDRV_USBF_NO, mbw);
+ USB20X.D1FIFOCTR = USB_FUNCTION_BITBCLR;
+ break;
+
+ default:
+ usbx_function_set_curpipe(
+ pipe, USB_FUNCTION_CUSE, USB_FUNCTION_CFIFO_READ, mbw);
+ USB20X.CFIFOCTR = USB_FUNCTION_BITBCLR;
+ break;
+ }
+
+ usbx_function_aclrm(pipe);
+
+ usbx_function_enable_nrdy_int(pipe);
+ usbx_function_enable_brdy_int(pipe);
+
+ usbx_function_set_pid_buf(pipe);
+#endif
+
+ pid = usbx_function_get_pid(pipe);
+ if ((pid == DEVDRV_USBF_PID_STALL) || (pid == DEVDRV_USBF_PID_STALL2)) {
+ g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL;
+ } else {
+ usbx_function_set_pid_buf(pipe);
+ }
+
+ ep = (g_usbx_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT;
+ ep <<= 1;
+ if (RZA_IO_RegRead_16(
+ &g_usbx_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) {
+ /* read */
+ __NOP();
+ } else {
+ /* write */
+ __NOP();
+ }
+ }
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB20X.NRDYSTS;
+ }
+}
+
+/******************************************************************************
+ * Function Name: usbx_function_BEMPInterruptPIPE0
+ * Description : Executes BEMP interrupt for pipe0.
+ * Arguments : uint16_t status ; BEMPSTS Register Value
+ * : uint16_t intenb ; BEMPENB Register Value
+ * Return Value : none
+ *****************************************************************************/
+extern "C" {
+ void usbx_function_BEMPInterruptPIPE0(
+ uint16_t status,
+ uint16_t intenb,
+ USBHAL *object,
+ void (USBHAL::*EP0func)(void)
+ )
+ {
+ volatile uint16_t dumy_sts;
+
+ USB20X.BEMPSTS =
+ (uint16_t)~g_usbx_function_bit_set[USB_FUNCTION_PIPE0];
+ RZA_IO_RegWrite_16(
+ &USB20X.CFIFOSEL, USB_FUNCTION_PIPE0,
+ USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE);
+
+ /*usbx_function_write_buffer_c(USB_FUNCTION_PIPE0);*/
+ (object->*EP0func)();
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB20X.BEMPSTS;
+ }
+}
+
+
+/******************************************************************************
+ * Function Name: usbx_function_BEMPInterrupt
+ * Description : Executes BEMP interrupt exclude pipe0.
+ * Arguments : uint16_t status ; BEMPSTS Register Value
+ * : uint16_t intenb ; BEMPENB Register Value
+ * Return Value : none
+ *****************************************************************************/
+extern "C" {
+ void usbx_function_BEMPInterrupt(
+ uint16_t status,
+ uint16_t intenb,
+ USBHAL *object,
+ bool (USBHAL::*epCallback[])(void)
+ )
+ {
+ volatile uint16_t dumy_sts;
+
+ /**************************************************************
+ * Function Name: usbx_function_bemp_int
+ * Description : Executes BEMP interrupt(USB_FUNCTION_PIPE1-9).
+ * Arguments : uint16_t status ; BEMPSTS Register Value
+ * : uint16_t intenb ; BEMPENB Register Value
+ * Return Value : none
+ *************************************************************/
+ /* copied from usbx_function_intrn.c */
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+ uint16_t inbuf;
+ uint16_t ep;
+
+ bitcheck = (uint16_t)(status & intenb);
+
+ USB20X.BEMPSTS = (uint16_t)~status;
+
+ for (pipe = USB_FUNCTION_PIPE1; pipe <= USB_FUNCTION_MAX_PIPE_NO; pipe++) {
+ if ((bitcheck&g_usbx_function_bit_set[pipe]) != g_usbx_function_bit_set[pipe]) {
+ continue;
+ }
+
+ pid = usbx_function_get_pid(pipe);
+
+ if ((pid == DEVDRV_USBF_PID_STALL) ||
+ (pid == DEVDRV_USBF_PID_STALL2)) {
+ g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_STALL;
+
+ } else {
+ inbuf = usbx_function_get_inbuf(pipe);
+
+ if (inbuf == 0) {
+ usbx_function_disable_bemp_int(pipe);
+ usbx_function_set_pid_nak(pipe);
+ g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_DONE;
+
+ switch (g_usbx_function_PipeTbl[pipe] & USB_FUNCTION_FIFO_USE) {
+ case USB_FUNCTION_D0FIFO_DMA:
+ /*now, DMA is not supported*/
+ break;
+
+ case USB_FUNCTION_D1FIFO_DMA:
+ /*now, DMA is not supported*/
+ break;
+
+ default:
+ ep = (g_usbx_function_pipecfg[pipe] & USB_PIPECFG_EPNUM) >> USB_PIPECFG_EPNUM_SHIFT;
+ ep <<= 1;
+ if (RZA_IO_RegRead_16(
+ &g_usbx_function_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0) {
+ /* read */
+ __NOP();
+ } else {
+ /* write */
+ EPx_read_status = DEVDRV_USBF_PIPE_WAIT;
+ (object->*(epCallback[ep - 2 + 1])) ();
+ EPx_read_status = DEVDRV_USBF_PIPE_DONE;
+ }
+ }
+ }
+ }
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB20X.BEMPSTS;
+ }
+}
+
+/******************************************************************************
+ * Function Name: EP2PIPE
+ * Description : Converts from endpoint to pipe
+ * Arguments : number of endpoint
+ * Return Value : number of pipe
+ *****************************************************************************/
+/*EP2PIPE converter is for pipe1, pipe3 and pipe6 only.*/
+#define EP2PIPE(endpoint) ((uint32_t)usbx_function_EpToPipe(endpoint))
+
+
+/******************************************************************************
+ * Function Name: usbx_function_save_request
+ * Description : Retains the USB request information in variables.
+ * Arguments : none
+ * Return Value : none
+ *****************************************************************************/
+#define usbx_function_save_request() \
+ { \
+ uint16_t *bufO = &setup_buffer[0]; \
+ \
+ USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITVALID; \
+ /*data[0] <= bmRequest, data[1] <= bmRequestType */ \
+ *bufO++ = USB20X.USBREQ; \
+ /*data[2] data[3] <= wValue*/ \
+ *bufO++ = USB20X.USBVAL; \
+ /*data[4] data[5] <= wIndex*/ \
+ *bufO++ = USB20X.USBINDX; \
+ /*data[6] data[6] <= wIndex*/ \
+ *bufO++ = USB20X.USBLENG; \
+ }
+
+
+/*************************************************************************/
+/*************************************************************************/
+/*************************************************************************/
+
+/*************************************************************************/
+/* constructor */
+USBHAL::USBHAL(void)
+{
+ /* ---- P4_1 : P4_1 (USB0_EN for GR-PEACH) ---- */
+ //usbx_en = new DigitalOut(P4_1, 1);
+
+ /* some constants */
+ int_id = USBIX_IRQn;
+ int_level = ( 2 << 3 );
+ clock_mode = USBFCLOCK_X1_48MHZ;
+#if (USB_FUNCTION_HISPEED == 0)
+ mode = USB_FUNCTION_FULL_SPEED;
+#else
+ mode = USB_FUNCTION_HIGH_SPEED;
+#endif
+ EP0_read_status = DEVDRV_USBF_WRITEEND;
+ EPx_read_status = DEVDRV_USBF_PIPE_DONE;
+
+ /* Disables interrupt for usb */
+ GIC_DisableIRQ(int_id);
+
+ /* Setup the end point */
+ epCallback[ 0] = &USBHAL::EP1_OUT_callback;
+ epCallback[ 1] = &USBHAL::EP1_IN_callback;
+ epCallback[ 2] = &USBHAL::EP2_OUT_callback;
+ epCallback[ 3] = &USBHAL::EP2_IN_callback;
+ epCallback[ 4] = &USBHAL::EP3_OUT_callback;
+ epCallback[ 5] = &USBHAL::EP3_IN_callback;
+ epCallback[ 6] = &USBHAL::EP4_OUT_callback;
+ epCallback[ 7] = &USBHAL::EP4_IN_callback;
+ epCallback[ 8] = &USBHAL::EP5_OUT_callback;
+ epCallback[ 9] = &USBHAL::EP5_IN_callback;
+ epCallback[10] = &USBHAL::EP6_OUT_callback;
+ epCallback[11] = &USBHAL::EP6_IN_callback;
+ epCallback[12] = &USBHAL::EP7_OUT_callback;
+ epCallback[13] = &USBHAL::EP7_IN_callback;
+ epCallback[14] = &USBHAL::EP8_OUT_callback;
+ epCallback[15] = &USBHAL::EP8_IN_callback;
+ epCallback[16] = &USBHAL::EP9_OUT_callback;
+ epCallback[17] = &USBHAL::EP9_IN_callback;
+ epCallback[18] = &USBHAL::EP10_OUT_callback;
+ epCallback[19] = &USBHAL::EP10_IN_callback;
+ epCallback[20] = &USBHAL::EP11_OUT_callback;
+ epCallback[21] = &USBHAL::EP11_IN_callback;
+ epCallback[22] = &USBHAL::EP12_OUT_callback;
+ epCallback[23] = &USBHAL::EP12_IN_callback;
+ epCallback[24] = &USBHAL::EP13_OUT_callback;
+ epCallback[25] = &USBHAL::EP13_IN_callback;
+ epCallback[26] = &USBHAL::EP14_OUT_callback;
+ epCallback[27] = &USBHAL::EP14_IN_callback;
+ epCallback[28] = &USBHAL::EP15_OUT_callback;
+ epCallback[29] = &USBHAL::EP15_IN_callback;
+
+ /* registers me */
+ instance = this;
+
+ /* Clear pipe table */
+ usbx_function_clear_pipe_tbl();
+
+/******************************************************************************
+ * Function Name: usbx_api_function_init
+ * Description : Initializes the USB module in the USB function mode.
+ *****************************************************************************/
+ /* The clock of USB0 modules is permitted */
+#if (USB_FUNCTION_CH == 0)
+ CPG.STBCR7 &= ~(CPG_STBCR7_MSTP71);
+#else
+ CPG.STBCR7 &= ~(CPG_STBCR7_MSTP71 | CPG_STBCR7_MSTP70);
+#endif
+ volatile uint8_t dummy8;
+ dummy8 = CPG.STBCR7;
+
+ {
+/******************************************************************************
+ * Function Name: usbx_function_setting_interrupt
+ * Description : Sets the USB module interrupt level.
+ *****************************************************************************/
+#if 0 /*DMA is not supported*/
+ IRQn_Type d0fifo_dmaintid;
+ IRQn_Type d1fifo_dmaintid;
+#endif
+
+ InterruptHandlerRegister(int_id, &_usbisr);
+ GIC_SetPriority(int_id, int_level);
+ GIC_EnableIRQ(int_id);
+
+#if 0 /*DMA is not supported*/
+ d0fifo_dmaintid = Userdef_USB_usbx_function_d0fifo_dmaintid();
+ if (d0fifo_dmaintid != 0xFFFF) {
+ InterruptHandlerRegister(d0fifo_dmaintid, usbx_function_dma_interrupt_d0fifo);
+ GIC_SetPriority(d0fifo_dmaintid, int_level);
+ GIC_EnableIRQ(d0fifo_dmaintid);
+ }
+#endif
+
+#if 0 /*DMA is not supported*/
+ d1fifo_dmaintid = Userdef_USB_usbx_function_d1fifo_dmaintid();
+ if (d1fifo_dmaintid != 0xFFFF) {
+ InterruptHandlerRegister(d1fifo_dmaintid, usbx_function_dma_interrupt_d1fifo);
+ GIC_SetPriority(d1fifo_dmaintid, int_level);
+ GIC_EnableIRQ(d1fifo_dmaintid);
+ }
+#endif
+/*****************************************************************************/
+ }
+
+ /* reset USB module with setting tranciever and HSE=1 */
+ usbx_function_reset_module(clock_mode);
+
+ /* clear variables */
+ usbx_function_init_status();
+
+ /* select USB Function and Interrupt Enable */
+ /* Detect USB Device to attach or detach */
+ usbx_function_InitModule(mode);
+
+ {
+ uint16_t buf;
+ buf = USB20X.INTENB0;
+ buf |= USB_INTENB0_SOFE;
+ USB20X.INTENB0 = buf;
+ }
+}
+
+/*************************************************************************/
+USBHAL::~USBHAL(void)
+{
+ /* Disables interrupt for usb */
+ GIC_DisableIRQ( int_id );
+ /* Unregisters interrupt function and priority */
+ InterruptHandlerRegister( int_id, (uint32_t)NULL );
+
+ //usbx_en = NULL;
+ instance = NULL;
+}
+
+/*************************************************************************/
+void USBHAL::connect(void)
+{
+ /* Activates USB0_EN */
+ //(*usbx_en) = 0;
+}
+
+
+/*************************************************************************/
+void USBHAL::disconnect(void)
+{
+ /* Deactivates USB0_EN */
+ //(*usbx_en) = 1;
+}
+
+
+/*************************************************************************/
+void USBHAL::configureDevice(void)
+{
+ /*The pipes set up in USBHAL::realiseEndpoint*/
+ /*usbx_function_clear_alt();*/ /* Alternate setting clear */
+ /*usbx_function_set_pid_buf(USB_FUNCTION_PIPE0);*/
+}
+
+
+/*************************************************************************/
+void USBHAL::unconfigureDevice(void)
+{
+ /* The Interface would be managed by USBDevice */
+ /*usbx_function_clear_alt();*/ /* Alternate setting clear */
+ /*usbx_function_set_pid_buf(USB_FUNCTION_PIPE0);*/
+}
+
+
+/*************************************************************************/
+void USBHAL::setAddress(uint8_t address)
+{
+ if (address <= 127) {
+ usbx_function_set_pid_buf(USB_FUNCTION_PIPE0); /* OK */
+ } else {
+ usbx_function_set_pid_stall(USB_FUNCTION_PIPE0); /* Not Spec */
+ }
+}
+
+
+/*************************************************************************/
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags)
+{
+ const struct PIPECFGREC *cfg;
+ uint16_t pipe;
+ uint16_t buf;
+
+ if ( (EP0OUT == endpoint) || (EP0IN == endpoint) ) {
+ return true;
+ }
+
+ for (cfg = &def_pipecfg[0]; cfg->pipesel != 0; cfg++) {
+ if (cfg->endpoint == endpoint) {
+ break;
+ }
+ }
+ if (cfg->pipesel == 0) {
+ return false;
+ }
+
+ pipe = ((cfg->pipesel & USB_PIPESEL_PIPESEL) >> USB_PIPESEL_PIPESEL_SHIFT);
+
+ g_usbx_function_PipeTbl[ pipe ] = (uint16_t)(endpoint | ((cfg->pipesel & USB_FUNCTION_FIFO_USE) << 0));
+
+ /* There are maintenance routine of SHTNAK and BFRE bits
+ * in original sample program. This sample is not
+ * programmed. Do maintenance the "def_pipecfg" array if
+ * you want it. */
+
+ /* Interrupt Disable */
+ buf = USB20X.BRDYENB;
+ buf &= (uint16_t)~g_usbx_function_bit_set[pipe];
+ USB20X.BRDYENB = buf;
+ buf = USB20X.NRDYENB;
+ buf &= (uint16_t)~g_usbx_function_bit_set[pipe];
+ USB20X.NRDYENB = buf;
+ buf = USB20X.BEMPENB;
+ buf &= (uint16_t)~g_usbx_function_bit_set[pipe];
+ USB20X.BEMPENB = buf;
+
+ usbx_function_set_pid_nak(pipe);
+
+ /* CurrentPIPE Clear */
+ if (RZA_IO_RegRead_16(&USB20X.CFIFOSEL, USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE) == pipe) {
+ RZA_IO_RegWrite_16(&USB20X.CFIFOSEL, 0, USB_CFIFOSEL_CURPIPE_SHIFT, USB_CFIFOSEL_CURPIPE);
+ }
+
+ if (RZA_IO_RegRead_16(&USB20X.D0FIFOSEL, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE) == pipe) {
+ RZA_IO_RegWrite_16(&USB20X.D0FIFOSEL, 0, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE);
+ }
+
+ if (RZA_IO_RegRead_16(&USB20X.D1FIFOSEL, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE) == pipe) {
+ RZA_IO_RegWrite_16(&USB20X.D1FIFOSEL, 0, USB_DnFIFOSEL_CURPIPE_SHIFT, USB_DnFIFOSEL_CURPIPE);
+ }
+
+ /* PIPE Configuration */
+ USB20X.PIPESEL = pipe;
+ USB20X.PIPECFG = cfg->pipecfg;
+ USB20X.PIPEBUF = cfg->pipebuf;
+ USB20X.PIPEMAXP = cfg->pipemaxp;
+ USB20X.PIPEPERI = cfg->pipeperi;
+
+ g_usbx_function_pipecfg[pipe] = cfg->pipecfg;
+ g_usbx_function_pipebuf[pipe] = cfg->pipebuf;
+ g_usbx_function_pipemaxp[pipe] = cfg->pipemaxp;
+ g_usbx_function_pipeperi[pipe] = cfg->pipeperi;
+
+ /* Buffer Clear */
+ usbx_function_set_sqclr(pipe);
+ usbx_function_aclrm(pipe);
+
+ /* init Global */
+ g_usbx_function_pipe_status[pipe] = DEVDRV_USBF_PIPE_IDLE;
+ g_usbx_function_PipeDataSize[pipe] = 0;
+
+ return true;
+}
+
+
+/*************************************************************************/
+// read setup packet
+void USBHAL::EP0setup(uint8_t *buffer)
+{
+ memcpy(buffer, setup_buffer, MAX_PACKET_SIZE_EP0);
+}
+
+
+/*************************************************************************/
+void USBHAL::EP0readStage(void)
+{
+ // No implements
+}
+
+
+/*************************************************************************/
+void USBHAL::EP0read(void)
+{
+ uint8_t *buffer;
+ uint32_t size;
+
+ /* remain of last writing */
+ while (EP0_read_status != DEVDRV_USBF_WRITEEND) {
+ static uint8_t bbb[2] = { 255, 255 };
+ EP0write(&bbb[0], 0);
+ }
+
+ buffer = (uint8_t*)(&setup_buffer[4]);
+ size = (MAX_PACKET_SIZE_EP0 / 2) - 8;
+ usbx_api_function_CtrlWriteStart(size, buffer);
+}
+
+
+/*************************************************************************/
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer)
+{
+ memcpy(buffer, (uint8_t*)(&setup_buffer[4]), g_usbx_function_PipeDataSize[USB_FUNCTION_PIPE0]);
+
+ return g_usbx_function_PipeDataSize[USB_FUNCTION_PIPE0];
+}
+
+
+/*************************************************************************/
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size)
+{
+ /* zero byte writing */
+ if ( (size == 0) && (EP0_read_status == DEVDRV_USBF_WRITEEND) ) {
+ return;
+ }
+
+ if (EP0_read_status == DEVDRV_USBF_WRITEEND) {
+ /*1st block*/
+ EP0_read_status = usbx_api_function_CtrlReadStart(size, buffer);
+ } else {
+ /* waits the last transmission */
+ /*other blocks*/
+ g_usbx_function_data_count[ USB_FUNCTION_PIPE0 ] = size;
+ g_usbx_function_data_pointer [ USB_FUNCTION_PIPE0 ] = buffer;
+ EP0_read_status = usbx_function_write_buffer_c(USB_FUNCTION_PIPE0);
+ }
+ /*max size may be deblocking outside*/
+ if (size == MAX_PACKET_SIZE_EP0) {
+ EP0_read_status = DEVDRV_USBF_WRITING;
+ }
+}
+
+
+/*************************************************************************/
+#if 0 // No implements
+void USBHAL::EP0getWriteResult(void)
+{
+}
+#endif
+
+/*************************************************************************/
+void USBHAL::EP0stall(void)
+{
+ stallEndpoint( 0 );
+}
+
+
+/*************************************************************************/
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t max_size)
+{
+ uint32_t pipe = EP2PIPE(endpoint);
+ uint32_t pipe_size;
+ uint16_t pipe_status;
+ EP_STATUS status = EP_COMPLETED;
+
+ pipe_status = usbx_api_function_check_pipe_status(pipe, &pipe_size);
+
+ switch (pipe_status) {
+ case DEVDRV_USBF_PIPE_IDLE:
+ case DEVDRV_USBF_PIPE_WAIT:
+ usbx_api_function_set_pid_nak(pipe);
+ usbx_api_function_clear_pipe_status(pipe);
+
+ usbx_api_function_start_receive_transfer(pipe, max_size, recv_buffer);
+ break;
+
+ default:
+ status = EP_PENDING;
+ break;
+ }
+
+ return status;
+}
+
+
+/*************************************************************************/
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t *bytes_read )
+{
+ uint32_t pipe = EP2PIPE(endpoint);
+ uint16_t pipe_status;
+ uint16_t err;
+ EP_STATUS status = EP_PENDING;
+
+
+ if (EPx_read_status != DEVDRV_USBF_PIPE_WAIT) {
+ return status;
+ }
+
+ pipe_status = usbx_api_function_check_pipe_status(pipe, bytes_read);
+ switch (pipe_status) {
+ case DEVDRV_USBF_PIPE_IDLE:
+ return EP_COMPLETED;
+
+ case DEVDRV_USBF_PIPE_DONE:
+ return EP_COMPLETED;
+
+ case DEVDRV_USBF_PIPE_WAIT:
+ break;
+
+ default:
+ return status;
+ }
+
+ /* sets the output buffer and size */
+ g_usbx_function_data_pointer[pipe] = buffer;
+
+ /* receives data from pipe */
+ err = usbx_function_read_buffer(pipe);
+ recv_error = err;
+ switch (err) {
+ case USB_FUNCTION_READEND:
+ case USB_FUNCTION_READSHRT:
+ case USB_FUNCTION_READOVER:
+ *bytes_read = g_usbx_function_PipeDataSize[pipe];
+ break;
+
+ case USB_FUNCTION_READING:
+ case DEVDRV_USBF_FIFOERROR:
+ break;
+ }
+
+ pipe_status = usbx_api_function_check_pipe_status(pipe, bytes_read);
+ switch (pipe_status) {
+ case DEVDRV_USBF_PIPE_DONE:
+ status = EP_COMPLETED;
+ break;
+
+ case DEVDRV_USBF_PIPE_IDLE:
+ case DEVDRV_USBF_PIPE_NORES:
+ case DEVDRV_USBF_PIPE_STALL:
+ case DEVDRV_USBF_FIFOERROR:
+ default:
+ break;
+ }
+
+ return status;
+}
+
+
+/*************************************************************************/
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size)
+{
+ uint32_t pipe = EP2PIPE(endpoint);
+ uint32_t pipe_size;
+ uint16_t pipe_status;
+ uint16_t err;
+ uint16_t count;
+ EP_STATUS status = EP_PENDING;
+
+ pipe_status = usbx_api_function_check_pipe_status(pipe, &pipe_size);
+
+ /* waits the last transmission */
+ count = 30000;
+ while ((pipe_status == DEVDRV_USBF_PIPE_WAIT) || (pipe_status == DEVDRV_USBF_PIPE_DONE)) {
+ pipe_status = usbx_api_function_check_pipe_status(pipe, &pipe_size);
+ if( --count == 0 ) {
+ pipe_status = DEVDRV_USBF_PIPE_STALL;
+ break;
+ }
+ }
+
+ switch (pipe_status) {
+ case DEVDRV_USBF_PIPE_IDLE:
+ err = usbx_api_function_start_send_transfer(pipe, size, data);
+
+ switch (err) {
+ /* finish to write */
+ case DEVDRV_USBF_WRITEEND:
+ /* finish to write, but data is short */
+ case DEVDRV_USBF_WRITESHRT:
+ /* continue to write */
+ case DEVDRV_USBF_WRITING:
+ /* use DMA */
+ case DEVDRV_USBF_WRITEDMA:
+ /* error */
+ case DEVDRV_USBF_FIFOERROR:
+ status = EP_PENDING;
+ break;
+ }
+ break;
+
+ case DEVDRV_USBF_PIPE_WAIT:
+ case DEVDRV_USBF_PIPE_DONE:
+ status = EP_PENDING;
+ break;
+
+ case DEVDRV_USBF_PIPE_NORES:
+ case DEVDRV_USBF_PIPE_STALL:
+ default:
+ status = EP_STALLED;
+ break;
+ }
+
+ return status;
+}
+
+
+/*************************************************************************/
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint)
+{
+ uint32_t pipe = EP2PIPE(endpoint);
+ uint32_t pipe_size;
+ uint16_t pipe_status;
+ EP_STATUS status = EP_PENDING;
+
+ pipe_status = usbx_api_function_check_pipe_status(pipe, &pipe_size);
+
+ switch (pipe_status) {
+ case DEVDRV_USBF_PIPE_IDLE:
+ status = EP_COMPLETED;
+ break;
+
+ case DEVDRV_USBF_PIPE_WAIT:
+ status = EP_PENDING;
+ break;
+
+ case DEVDRV_USBF_PIPE_DONE:
+ usbx_function_stop_transfer(pipe);
+ status = EP_COMPLETED;
+ break;
+
+ case DEVDRV_USBF_PIPE_NORES:
+ status = EP_STALLED;
+ break;
+
+ case DEVDRV_USBF_PIPE_STALL:
+ status = EP_STALLED;
+ break;
+
+ default:
+ status = EP_PENDING;
+ }
+
+ return status;
+}
+
+
+/*************************************************************************/
+void USBHAL::stallEndpoint(uint8_t endpoint)
+{
+ uint32_t pipe = EP2PIPE(endpoint);
+
+ usbx_function_clear_pid_stall(pipe);
+}
+
+
+/*************************************************************************/
+void USBHAL::unstallEndpoint(uint8_t endpoint)
+{
+ uint32_t pipe = EP2PIPE(endpoint);
+
+ usbx_function_set_pid_stall( pipe );
+}
+
+
+/*************************************************************************/
+bool USBHAL::getEndpointStallState(uint8_t endpoint)
+{
+ // No implemens
+ return false;
+}
+
+
+/*************************************************************************/
+#if 0 // No implements
+void USBHAL::remoteWakeup(void)
+{
+}
+#endif
+
+/*************************************************************************/
+void USBHAL::_usbisr(void)
+{
+ instance->usbisr();
+}
+
+
+/*************************************************************************/
+void USBHAL::usbisr(void)
+{
+ uint16_t int_sts0;
+ uint16_t int_sts1;
+ uint16_t int_sts2;
+ uint16_t int_sts3;
+ uint16_t int_enb0;
+ uint16_t int_enb2;
+ uint16_t int_enb3;
+ uint16_t int_enb4;
+ volatile uint16_t dumy_sts;
+
+
+ int_sts0 = USB20X.INTSTS0;
+
+ if (!(int_sts0 & (
+ USB_FUNCTION_BITVBINT |
+ USB_FUNCTION_BITRESM |
+ USB_FUNCTION_BITSOFR |
+ USB_FUNCTION_BITDVST |
+ USB_FUNCTION_BITCTRT |
+ USB_FUNCTION_BITBEMP |
+ USB_FUNCTION_BITNRDY |
+ USB_FUNCTION_BITBRDY ))) {
+ return;
+ }
+
+ int_sts1 = USB20X.BRDYSTS;
+ int_sts2 = USB20X.NRDYSTS;
+ int_sts3 = USB20X.BEMPSTS;
+ int_enb0 = USB20X.INTENB0;
+ int_enb2 = USB20X.BRDYENB;
+ int_enb3 = USB20X.NRDYENB;
+ int_enb4 = USB20X.BEMPENB;
+
+ if ((int_sts0 & USB_FUNCTION_BITRESM) &&
+ (int_enb0 & USB_FUNCTION_BITRSME)) {
+ USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITRESM;
+ RZA_IO_RegWrite_16(&USB20X.INTENB0, 0, USB_INTENB0_RSME_SHIFT, USB_INTENB0_RSME);
+ /*usbx_function_USB_FUNCTION_Resume();*/
+ suspendStateChanged(1);
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITVBINT) &&
+ (int_enb0 & USB_FUNCTION_BITVBSE)) {
+ USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITVBINT;
+
+ if (usbx_function_CheckVBUStaus() == DEVDRV_USBF_ON) {
+ usbx_function_USB_FUNCTION_Attach();
+ } else {
+ usbx_function_USB_FUNCTION_Detach();
+ }
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITSOFR) &&
+ (int_enb0 & USB_FUNCTION_BITSOFE)) {
+ USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITSOFR;
+ SOF((USB20X.FRMNUM & USB_FRMNUM_FRNM) >> USB_FRMNUM_FRNM_SHIFT);
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITDVST) &&
+ (int_enb0 & USB_FUNCTION_BITDVSE)) {
+ USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITDVST;
+ switch (int_sts0 & USB_FUNCTION_BITDVSQ) {
+ case USB_FUNCTION_DS_POWR:
+ break;
+
+ case USB_FUNCTION_DS_DFLT:
+ /*****************************************************************************
+ * Function Name: usbx_function_USB_FUNCTION_BusReset
+ * Description : This function is executed when the USB device is transitioned
+ * : to POWERD_STATE. Sets the device descriptor according to the
+ * : connection speed determined by the USB reset hand shake.
+ * Arguments : none
+ * Return Value : none
+ *****************************************************************************/
+ usbx_function_init_status(); /* memory clear */
+
+#if 0
+ /* You would program those steps in USBCallback_busReset
+ * if the system need the comment out steps.
+ */
+
+ if (usbx_function_is_hispeed() == USB_FUNCTION_HIGH_SPEED) {
+ /* Device Descriptor reset */
+ usbx_function_ResetDescriptor(USB_FUNCTION_HIGH_SPEED);
+ } else {
+ /* Device Descriptor reset */
+ usbx_function_ResetDescriptor(USB_FUNCTION_FULL_SPEED);
+ }
+#endif
+ /* Default Control PIPE reset */
+ /*****************************************************************************
+ * Function Name: usbx_function_ResetDCP
+ * Description : Initializes the default control pipe(DCP).
+ * Outline : Reset default control pipe
+ * Arguments : none
+ * Return Value : none
+ *****************************************************************************/
+ USB20X.DCPCFG = 0;
+ USB20X.DCPMAXP = 64; /*TODO: This value is copied from sample*/
+
+ USB20X.CFIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+ USB20X.D0FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+ USB20X.D1FIFOSEL = (uint16_t)(USB_FUNCTION_BITMBW_8 | USB_FUNCTION_BITBYTE_LITTLE);
+
+ busReset();
+ break;
+
+ case USB_FUNCTION_DS_ADDS:
+ break;
+
+ case USB_FUNCTION_DS_CNFG:
+ break;
+
+ case USB_FUNCTION_DS_SPD_POWR:
+ case USB_FUNCTION_DS_SPD_DFLT:
+ case USB_FUNCTION_DS_SPD_ADDR:
+ case USB_FUNCTION_DS_SPD_CNFG:
+ suspendStateChanged(0);
+ /*usbx_function_USB_FUNCTION_Suspend();*/
+ break;
+
+ default:
+ break;
+ }
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITBEMP) &&
+ (int_enb0 & USB_FUNCTION_BITBEMP) &&
+ ((int_sts3 & int_enb4) & g_usbx_function_bit_set[USB_FUNCTION_PIPE0])) {
+ /* ==== BEMP PIPE0 ==== */
+ usbx_function_BEMPInterruptPIPE0(int_sts3, int_enb4, this, &USBHAL::EP0in);
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITBRDY) &&
+ (int_enb0 & USB_FUNCTION_BITBRDY) &&
+ ((int_sts1 & int_enb2) & g_usbx_function_bit_set[USB_FUNCTION_PIPE0])) {
+ /* ==== BRDY PIPE0 ==== */
+ usbx_function_BRDYInterruptPIPE0(int_sts1, int_enb2, this, &USBHAL::EP0out);
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITNRDY) &&
+ (int_enb0 & USB_FUNCTION_BITNRDY) &&
+ ((int_sts2 & int_enb3) & g_usbx_function_bit_set[USB_FUNCTION_PIPE0])) {
+ /* ==== NRDY PIPE0 ==== */
+ usbx_function_NRDYInterruptPIPE0(int_sts2, int_enb3, this, NULL);
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITCTRT) && (int_enb0 & USB_FUNCTION_BITCTRE)) {
+ int_sts0 = USB20X.INTSTS0;
+ USB20X.INTSTS0 = (uint16_t)~USB_FUNCTION_BITCTRT;
+
+ if (((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_RDDS) ||
+ ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_WRDS) ||
+ ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_WRND)) {
+
+ /* remake EP0 into buffer */
+ usbx_function_save_request();
+ if ((USB20X.INTSTS0 & USB_FUNCTION_BITVALID) && (
+ ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_RDDS) ||
+ ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_WRDS) ||
+ ((int_sts0 & USB_FUNCTION_BITCTSQ) == USB_FUNCTION_CS_WRND))) {
+ /* New SETUP token received */
+ /* Three dummy reads for cleearing interrupt requests */
+ dumy_sts = USB20X.INTSTS0;
+ dumy_sts = USB20X.INTSTS0;
+ dumy_sts = USB20X.INTSTS0;
+ return;
+ }
+ }
+
+ switch (int_sts0 & USB_FUNCTION_BITCTSQ) {
+ case USB_FUNCTION_CS_IDST:
+ if (g_usbx_function_TestModeFlag == DEVDRV_USBF_YES) {
+ /* ==== Test Mode ==== */
+ usbx_function_USB_FUNCTION_TestMode();
+ }
+ /* Needs not procedure in this state */
+ break;
+
+ case USB_FUNCTION_CS_RDDS:
+ /* Reads a setup packet */
+ EP0setupCallback();
+ break;
+
+ case USB_FUNCTION_CS_WRDS:
+ /* Original code was the SetDescriptor was called */
+ EP0setupCallback();
+ break;
+
+ case USB_FUNCTION_CS_WRND:
+ EP0setupCallback();
+
+ /*The EP0setupCallback should finish in successful */
+ usbx_function_set_pid_buf(USB_FUNCTION_PIPE0);
+
+ RZA_IO_RegWrite_16(&USB20X.DCPCTR, 1, USB_DCPCTR_CCPL_SHIFT, USB_DCPCTR_CCPL);
+ break;
+
+ case USB_FUNCTION_CS_RDSS:
+ RZA_IO_RegWrite_16(&USB20X.DCPCTR, 1, USB_DCPCTR_CCPL_SHIFT, USB_DCPCTR_CCPL);
+ break;
+
+ case USB_FUNCTION_CS_WRSS:
+ RZA_IO_RegWrite_16(&USB20X.DCPCTR, 1, USB_DCPCTR_CCPL_SHIFT, USB_DCPCTR_CCPL);
+ break;
+
+ case USB_FUNCTION_CS_SQER:
+ usbx_function_set_pid_stall(USB_FUNCTION_PIPE0);
+ break;
+
+ default:
+ usbx_function_set_pid_stall(USB_FUNCTION_PIPE0);
+ break;
+ }
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITBEMP) &&
+ (int_enb0 & USB_FUNCTION_BITBEMP) &&
+ (int_sts3 & int_enb4) ) {
+ /* ==== BEMP PIPEx ==== */
+ usbx_function_BEMPInterrupt(int_sts3, int_enb4, this, epCallback);
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITBRDY) &&
+ (int_enb0 & USB_FUNCTION_BITBRDY) &&
+ (int_sts1 & int_enb2) ) {
+ /* ==== BRDY PIPEx ==== */
+ usbx_function_BRDYInterrupt(int_sts1, int_enb2, this, epCallback);
+ } else if (
+ (int_sts0 & USB_FUNCTION_BITNRDY) &&
+ (int_enb0 & USB_FUNCTION_BITNRDY) &&
+ (int_sts2 & int_enb3)) {
+ /* ==== NRDY PIPEx ==== */
+ usbx_function_NRDYInterrupt(int_sts2, int_enb3, this, epCallback);
+ } else {
+ /* Do Nothing */
+ }
+
+ /* Three dummy reads for cleearing interrupt requests */
+ dumy_sts = USB20X.INTSTS0;
+ dumy_sts = USB20X.INTSTS1;
+}
+
+/*************************************************************************/
+#endif
+/*************************************************************************/
+/*EOF*/
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_STM32F4.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_STM32F4.cpp
new file mode 100644
index 000000000..8faac6170
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBHAL_STM32F4.cpp
@@ -0,0 +1,410 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined(TARGET_STM32F4)
+
+#include "USBHAL.h"
+#include "USBRegs_STM32.h"
+#include "pinmap.h"
+
+USBHAL * USBHAL::instance;
+
+static volatile int epComplete = 0;
+
+static uint32_t bufferEnd = 0;
+static const uint32_t rxFifoSize = 512;
+static uint32_t rxFifoCount = 0;
+
+static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
+
+uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
+ return 0;
+}
+
+USBHAL::USBHAL(void) {
+ NVIC_DisableIRQ(OTG_FS_IRQn);
+ epCallback[0] = &USBHAL::EP1_OUT_callback;
+ epCallback[1] = &USBHAL::EP1_IN_callback;
+ epCallback[2] = &USBHAL::EP2_OUT_callback;
+ epCallback[3] = &USBHAL::EP2_IN_callback;
+ epCallback[4] = &USBHAL::EP3_OUT_callback;
+ epCallback[5] = &USBHAL::EP3_IN_callback;
+
+ // Enable power and clocking
+ RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
+
+#if defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE)
+ pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
+ pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLDOWN, GPIO_AF10_OTG_FS));
+ pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS));
+ pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
+ pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
+#else
+ pin_function(PA_8, STM_PIN_DATA(2, 10));
+ pin_function(PA_9, STM_PIN_DATA(0, 0));
+ pin_function(PA_10, STM_PIN_DATA(2, 10));
+ pin_function(PA_11, STM_PIN_DATA(2, 10));
+ pin_function(PA_12, STM_PIN_DATA(2, 10));
+
+ // Set ID pin to open drain with pull-up resistor
+ pin_mode(PA_10, OpenDrain);
+ GPIOA->PUPDR &= ~(0x3 << 20);
+ GPIOA->PUPDR |= 1 << 20;
+
+ // Set VBUS pin to open drain
+ pin_mode(PA_9, OpenDrain);
+#endif
+
+ RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
+
+ // Enable interrupts
+ OTG_FS->GREGS.GAHBCFG |= (1 << 0);
+
+ // Turnaround time to maximum value - too small causes packet loss
+ OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
+
+ // Unmask global interrupts
+ OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
+ (1 << 4) | // RX FIFO not empty
+ (1 << 12); // USB reset
+
+ OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
+ (1 << 2); // Non-zero-length status OUT handshake
+
+ OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
+ (1 << 16); // Power Up
+
+ instance = this;
+ NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
+ NVIC_SetPriority(OTG_FS_IRQn, 1);
+}
+
+USBHAL::~USBHAL(void) {
+}
+
+void USBHAL::connect(void) {
+ NVIC_EnableIRQ(OTG_FS_IRQn);
+}
+
+void USBHAL::disconnect(void) {
+ NVIC_DisableIRQ(OTG_FS_IRQn);
+}
+
+void USBHAL::configureDevice(void) {
+ // Not needed
+}
+
+void USBHAL::unconfigureDevice(void) {
+ // Not needed
+}
+
+void USBHAL::setAddress(uint8_t address) {
+ OTG_FS->DREGS.DCFG |= (address << 4);
+ EP0write(0, 0);
+}
+
+bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
+ uint32_t flags) {
+ uint32_t epIndex = endpoint >> 1;
+
+ uint32_t type;
+ switch (endpoint) {
+ case EP0IN:
+ case EP0OUT:
+ type = 0;
+ break;
+ case EPISO_IN:
+ case EPISO_OUT:
+ type = 1;
+ case EPBULK_IN:
+ case EPBULK_OUT:
+ type = 2;
+ break;
+ case EPINT_IN:
+ case EPINT_OUT:
+ type = 3;
+ break;
+ }
+
+ // Generic in or out EP controls
+ uint32_t control = (maxPacket << 0) | // Packet size
+ (1 << 15) | // Active endpoint
+ (type << 18); // Endpoint type
+
+ if (endpoint & 0x1) { // In Endpoint
+ // Set up the Tx FIFO
+ if (endpoint == EP0IN) {
+ OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
+ (bufferEnd << 0);
+ }
+ else {
+ OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
+ (bufferEnd << 0);
+ }
+ bufferEnd += maxPacket >> 2;
+
+ // Set the In EP specific control settings
+ if (endpoint != EP0IN) {
+ control |= (1 << 28); // SD0PID
+ }
+
+ control |= (epIndex << 22) | // TxFIFO index
+ (1 << 27); // SNAK
+ OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
+
+ // Unmask the interrupt
+ OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
+ }
+ else { // Out endpoint
+ // Set the out EP specific control settings
+ control |= (1 << 26); // CNAK
+ OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
+
+ // Unmask the interrupt
+ OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
+ }
+ return true;
+}
+
+// read setup packet
+void USBHAL::EP0setup(uint8_t *buffer) {
+ memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
+}
+
+void USBHAL::EP0readStage(void) {
+}
+
+void USBHAL::EP0read(void) {
+}
+
+uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
+ uint32_t* buffer32 = (uint32_t *) buffer;
+ uint32_t length = rxFifoCount;
+ for (uint32_t i = 0; i < length; i += 4) {
+ buffer32[i >> 2] = OTG_FS->FIFO[0][0];
+ }
+
+ rxFifoCount = 0;
+ return length;
+}
+
+void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
+ endpointWrite(0, buffer, size);
+}
+
+void USBHAL::EP0getWriteResult(void) {
+}
+
+void USBHAL::EP0stall(void) {
+ // If we stall the out endpoint here then we have problems transferring
+ // and setup requests after the (stalled) get device qualifier requests.
+ // TODO: Find out if this is correct behavior, or whether we are doing
+ // something else wrong
+ stallEndpoint(EP0IN);
+// stallEndpoint(EP0OUT);
+}
+
+EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
+ uint32_t epIndex = endpoint >> 1;
+ uint32_t size = (1 << 19) | // 1 packet
+ (maximumSize << 0); // Packet size
+// if (endpoint == EP0OUT) {
+ size |= (1 << 29); // 1 setup packet
+// }
+ OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
+ OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
+ (1 << 26); // Clear NAK
+
+ epComplete &= ~(1 << endpoint);
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
+ if (!(epComplete & (1 << endpoint))) {
+ return EP_PENDING;
+ }
+
+ uint32_t* buffer32 = (uint32_t *) buffer;
+ uint32_t length = rxFifoCount;
+ for (uint32_t i = 0; i < length; i += 4) {
+ buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
+ }
+ rxFifoCount = 0;
+ *bytesRead = length;
+ return EP_COMPLETED;
+}
+
+EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
+ uint32_t epIndex = endpoint >> 1;
+ OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
+ (size << 0); // Size of packet
+ OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
+ (1 << 26); // CNAK
+ OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
+
+ while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
+
+ for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
+ OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
+ }
+
+ epComplete &= ~(1 << endpoint);
+
+ return EP_PENDING;
+}
+
+EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
+ if (epComplete & (1 << endpoint)) {
+ epComplete &= ~(1 << endpoint);
+ return EP_COMPLETED;
+ }
+
+ return EP_PENDING;
+}
+
+void USBHAL::stallEndpoint(uint8_t endpoint) {
+ if (endpoint & 0x1) { // In EP
+ OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
+ (1 << 21); // Stall
+ }
+ else { // Out EP
+ OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
+ OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
+ (1 << 21); // Stall
+ }
+}
+
+void USBHAL::unstallEndpoint(uint8_t endpoint) {
+
+}
+
+bool USBHAL::getEndpointStallState(uint8_t endpoint) {
+ return false;
+}
+
+void USBHAL::remoteWakeup(void) {
+}
+
+
+void USBHAL::_usbisr(void) {
+ instance->usbisr();
+}
+
+
+void USBHAL::usbisr(void) {
+ if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
+ // Set SNAK bits
+ OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
+ OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
+ OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
+ OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
+
+ OTG_FS->DREGS.DIEPMSK = (1 << 0);
+
+ bufferEnd = 0;
+
+ // Set the receive FIFO size
+ OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
+ bufferEnd += rxFifoSize >> 2;
+
+ // Create the endpoints, and wait for setup packets on out EP0
+ realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
+ realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
+ endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
+
+ OTG_FS->GREGS.GINTSTS = (1 << 12);
+ }
+
+ if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
+ uint32_t status = OTG_FS->GREGS.GRXSTSP;
+
+ uint32_t endpoint = (status & 0xF) << 1;
+ uint32_t length = (status >> 4) & 0x7FF;
+ uint32_t type = (status >> 17) & 0xF;
+
+ rxFifoCount = length;
+
+ if (type == 0x6) {
+ // Setup packet
+ for (uint32_t i=0; i<length; i+=4) {
+ setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
+ }
+ rxFifoCount = 0;
+ }
+
+ if (type == 0x4) {
+ // Setup complete
+ EP0setupCallback();
+ endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
+ }
+
+ if (type == 0x2) {
+ // Out packet
+ if (endpoint == EP0OUT) {
+ EP0out();
+ }
+ else {
+ epComplete |= (1 << endpoint);
+ if ((instance->*(epCallback[endpoint - 2]))()) {
+ epComplete &= (1 << endpoint);
+ }
+ }
+ }
+
+ for (uint32_t i=0; i<rxFifoCount; i+=4) {
+ (void) OTG_FS->FIFO[0][0];
+ }
+ OTG_FS->GREGS.GINTSTS = (1 << 4);
+ }
+
+ if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
+ // Loop through the in endpoints
+ for (uint32_t i=0; i<4; i++) {
+ if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
+
+ if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
+ // If the Tx FIFO is empty on EP0 we need to send a further
+ // packet, so call EP0in()
+ if (i == 0) {
+ EP0in();
+ }
+ // Clear the interrupt
+ OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
+ // Stop firing Tx empty interrupts
+ // Will get turned on again if another write is called
+ OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
+ }
+
+ // If the transfer is complete
+ if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
+ epComplete |= (1 << (1 + (i << 1)));
+ OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
+ }
+ }
+ }
+ OTG_FS->GREGS.GINTSTS = (1 << 18);
+ }
+
+ if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
+ SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
+ OTG_FS->GREGS.GINTSTS = (1 << 3);
+ }
+}
+
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBRegs_STM32.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBRegs_STM32.h
new file mode 100644
index 000000000..3e11a49c1
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBDevice/USBRegs_STM32.h
@@ -0,0 +1,149 @@
+/**
+ ******************************************************************************
+ * @file usb_regs.h
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 19-March-2012
+ * @brief hardware registers
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+#ifndef __USB_OTG_REGS_H__
+#define __USB_OTG_REGS_H__
+
+typedef struct //000h
+{
+ __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
+ __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
+ __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
+ __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
+ __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
+ __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
+ __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
+ __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
+ __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
+ __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
+ __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
+ uint32_t Reserved30[2]; /* Reserved 030h*/
+ __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
+ __IO uint32_t CID; /* User ID Register 03Ch*/
+ uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
+ __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
+ __IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
+}
+USB_OTG_GREGS;
+
+typedef struct // 800h
+{
+ __IO uint32_t DCFG; /* dev Configuration Register 800h*/
+ __IO uint32_t DCTL; /* dev Control Register 804h*/
+ __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
+ uint32_t Reserved0C; /* Reserved 80Ch*/
+ __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
+ __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
+ __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
+ __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
+ uint32_t Reserved20; /* Reserved 820h*/
+ uint32_t Reserved9; /* Reserved 824h*/
+ __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
+ __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
+ __IO uint32_t DTHRCTL; /* dev thr 830h*/
+ __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
+}
+USB_OTG_DREGS;
+
+typedef struct
+{
+ __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
+ uint32_t Reserved14;
+ __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
+ uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
+}
+USB_OTG_INEPREGS;
+
+typedef struct
+{
+ __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
+ uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
+ __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
+ uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
+ __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
+ uint32_t Reserved14[3];
+}
+USB_OTG_OUTEPREGS;
+
+typedef struct
+{
+ __IO uint32_t HCFG; /* Host Configuration Register 400h*/
+ __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
+ __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
+ uint32_t Reserved40C; /* Reserved 40Ch*/
+ __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
+ __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
+ __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
+}
+USB_OTG_HREGS;
+
+typedef struct
+{
+ __IO uint32_t HCCHAR;
+ __IO uint32_t HCSPLT;
+ __IO uint32_t HCINT;
+ __IO uint32_t HCINTMSK;
+ __IO uint32_t HCTSIZ;
+ uint32_t Reserved[3];
+}
+USB_OTG_HC_REGS;
+
+typedef struct
+{
+ USB_OTG_GREGS GREGS;
+ uint32_t RESERVED0[188];
+ USB_OTG_HREGS HREGS;
+ uint32_t RESERVED1[9];
+ __IO uint32_t HPRT;
+ uint32_t RESERVED2[47];
+ USB_OTG_HC_REGS HC_REGS[8];
+ uint32_t RESERVED3[128];
+ USB_OTG_DREGS DREGS;
+ uint32_t RESERVED4[50];
+ USB_OTG_INEPREGS INEP_REGS[4];
+ uint32_t RESERVED5[96];
+ USB_OTG_OUTEPREGS OUTEP_REGS[4];
+ uint32_t RESERVED6[160];
+ __IO uint32_t PCGCCTL;
+ uint32_t RESERVED7[127];
+ __IO uint32_t FIFO[4][1024];
+}
+USB_OTG_CORE_REGS;
+
+
+#define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
+#define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
+
+#endif //__USB_OTG_REGS_H__
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID.cpp
new file mode 100644
index 000000000..571421d82
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID.cpp
@@ -0,0 +1,276 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBHAL.h"
+#include "USBHID.h"
+
+
+USBHID::USBHID(uint8_t output_report_length, uint8_t input_report_length, uint16_t vendor_id, uint16_t product_id, uint16_t product_release, bool connect): USBDevice(vendor_id, product_id, product_release)
+{
+ output_length = output_report_length;
+ input_length = input_report_length;
+ if(connect) {
+ USBDevice::connect();
+ }
+}
+
+
+bool USBHID::send(HID_REPORT *report)
+{
+ return write(EPINT_IN, report->data, report->length, MAX_HID_REPORT_SIZE);
+}
+
+bool USBHID::sendNB(HID_REPORT *report)
+{
+ return writeNB(EPINT_IN, report->data, report->length, MAX_HID_REPORT_SIZE);
+}
+
+
+bool USBHID::read(HID_REPORT *report)
+{
+ uint32_t bytesRead = 0;
+ bool result;
+ result = USBDevice::readEP(EPINT_OUT, report->data, &bytesRead, MAX_HID_REPORT_SIZE);
+ if(!readStart(EPINT_OUT, MAX_HID_REPORT_SIZE))
+ return false;
+ report->length = bytesRead;
+ return result;
+}
+
+
+bool USBHID::readNB(HID_REPORT *report)
+{
+ uint32_t bytesRead = 0;
+ bool result;
+ result = USBDevice::readEP_NB(EPINT_OUT, report->data, &bytesRead, MAX_HID_REPORT_SIZE);
+ // if readEP_NB did not succeed, does not issue a readStart
+ if (!result)
+ return false;
+ report->length = bytesRead;
+ if(!readStart(EPINT_OUT, MAX_HID_REPORT_SIZE))
+ return false;
+ return result;
+}
+
+
+uint16_t USBHID::reportDescLength() {
+ reportDesc();
+ return reportLength;
+}
+
+
+
+//
+// Route callbacks from lower layers to class(es)
+//
+
+
+// Called in ISR context
+// Called by USBDevice on Endpoint0 request
+// This is used to handle extensions to standard requests
+// and class specific requests
+// Return true if class handles this request
+bool USBHID::USBCallback_request() {
+ bool success = false;
+ CONTROL_TRANSFER * transfer = getTransferPtr();
+ uint8_t *hidDescriptor;
+
+ // Process additional standard requests
+
+ if ((transfer->setup.bmRequestType.Type == STANDARD_TYPE))
+ {
+ switch (transfer->setup.bRequest)
+ {
+ case GET_DESCRIPTOR:
+ switch (DESCRIPTOR_TYPE(transfer->setup.wValue))
+ {
+ case REPORT_DESCRIPTOR:
+ if ((reportDesc() != NULL) \
+ && (reportDescLength() != 0))
+ {
+ transfer->remaining = reportDescLength();
+ transfer->ptr = reportDesc();
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ }
+ break;
+ case HID_DESCRIPTOR:
+ // Find the HID descriptor, after the configuration descriptor
+ hidDescriptor = findDescriptor(HID_DESCRIPTOR);
+ if (hidDescriptor != NULL)
+ {
+ transfer->remaining = HID_DESCRIPTOR_LENGTH;
+ transfer->ptr = hidDescriptor;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ }
+ break;
+
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+
+ // Process class-specific requests
+
+ if (transfer->setup.bmRequestType.Type == CLASS_TYPE)
+ {
+ switch (transfer->setup.bRequest)
+ {
+ case SET_REPORT:
+ // First byte will be used for report ID
+ outputReport.data[0] = transfer->setup.wValue & 0xff;
+ outputReport.length = transfer->setup.wLength + 1;
+
+ transfer->remaining = sizeof(outputReport.data) - 1;
+ transfer->ptr = &outputReport.data[1];
+ transfer->direction = HOST_TO_DEVICE;
+ transfer->notify = true;
+ success = true;
+ default:
+ break;
+ }
+ }
+
+ return success;
+}
+
+
+#define DEFAULT_CONFIGURATION (1)
+
+
+// Called in ISR context
+// Set configuration. Return false if the
+// configuration is not supported
+bool USBHID::USBCallback_setConfiguration(uint8_t configuration) {
+ if (configuration != DEFAULT_CONFIGURATION) {
+ return false;
+ }
+
+ // Configure endpoints > 0
+ addEndpoint(EPINT_IN, MAX_PACKET_SIZE_EPINT);
+ addEndpoint(EPINT_OUT, MAX_PACKET_SIZE_EPINT);
+
+ // We activate the endpoint to be able to recceive data
+ readStart(EPINT_OUT, MAX_PACKET_SIZE_EPINT);
+ return true;
+}
+
+
+uint8_t * USBHID::stringIinterfaceDesc() {
+ static uint8_t stringIinterfaceDescriptor[] = {
+ 0x08, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'H',0,'I',0,'D',0, //bString iInterface - HID
+ };
+ return stringIinterfaceDescriptor;
+}
+
+uint8_t * USBHID::stringIproductDesc() {
+ static uint8_t stringIproductDescriptor[] = {
+ 0x16, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'H',0,'I',0,'D',0,' ',0,'D',0,'E',0,'V',0,'I',0,'C',0,'E',0 //bString iProduct - HID device
+ };
+ return stringIproductDescriptor;
+}
+
+
+
+uint8_t * USBHID::reportDesc() {
+ static uint8_t reportDescriptor[] = {
+ 0x06, LSB(0xFFAB), MSB(0xFFAB),
+ 0x0A, LSB(0x0200), MSB(0x0200),
+ 0xA1, 0x01, // Collection 0x01
+ 0x75, 0x08, // report size = 8 bits
+ 0x15, 0x00, // logical minimum = 0
+ 0x26, 0xFF, 0x00, // logical maximum = 255
+ 0x95, input_length, // report count
+ 0x09, 0x01, // usage
+ 0x81, 0x02, // Input (array)
+ 0x95, output_length,// report count
+ 0x09, 0x02, // usage
+ 0x91, 0x02, // Output (array)
+ 0xC0 // end collection
+
+ };
+ reportLength = sizeof(reportDescriptor);
+ return reportDescriptor;
+}
+
+#define DEFAULT_CONFIGURATION (1)
+#define TOTAL_DESCRIPTOR_LENGTH ((1 * CONFIGURATION_DESCRIPTOR_LENGTH) \
+ + (1 * INTERFACE_DESCRIPTOR_LENGTH) \
+ + (1 * HID_DESCRIPTOR_LENGTH) \
+ + (2 * ENDPOINT_DESCRIPTOR_LENGTH))
+
+uint8_t * USBHID::configurationDesc() {
+ static uint8_t configurationDescriptor[] = {
+ CONFIGURATION_DESCRIPTOR_LENGTH,// bLength
+ CONFIGURATION_DESCRIPTOR, // bDescriptorType
+ LSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (LSB)
+ MSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (MSB)
+ 0x01, // bNumInterfaces
+ DEFAULT_CONFIGURATION, // bConfigurationValue
+ 0x00, // iConfiguration
+ C_RESERVED | C_SELF_POWERED, // bmAttributes
+ C_POWER(0), // bMaxPower
+
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x00, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x02, // bNumEndpoints
+ HID_CLASS, // bInterfaceClass
+ HID_SUBCLASS_NONE, // bInterfaceSubClass
+ HID_PROTOCOL_NONE, // bInterfaceProtocol
+ 0x00, // iInterface
+
+ HID_DESCRIPTOR_LENGTH, // bLength
+ HID_DESCRIPTOR, // bDescriptorType
+ LSB(HID_VERSION_1_11), // bcdHID (LSB)
+ MSB(HID_VERSION_1_11), // bcdHID (MSB)
+ 0x00, // bCountryCode
+ 0x01, // bNumDescriptors
+ REPORT_DESCRIPTOR, // bDescriptorType
+ (uint8_t)(LSB(this->reportDescLength())), // wDescriptorLength (LSB)
+ (uint8_t)(MSB(this->reportDescLength())), // wDescriptorLength (MSB)
+
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPINT_IN), // bEndpointAddress
+ E_INTERRUPT, // bmAttributes
+ LSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB)
+ 1, // bInterval (milliseconds)
+
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPINT_OUT), // bEndpointAddress
+ E_INTERRUPT, // bmAttributes
+ LSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB)
+ 1, // bInterval (milliseconds)
+ };
+ return configurationDescriptor;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID.h
new file mode 100644
index 000000000..faa75cb94
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID.h
@@ -0,0 +1,172 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USB_HID_H
+#define USB_HID_H
+
+/* These headers are included for child class. */
+#include "USBEndpoints.h"
+#include "USBDescriptor.h"
+#include "USBDevice_Types.h"
+
+#include "USBHID_Types.h"
+#include "USBDevice.h"
+
+
+/**
+ * USBHID example
+ * @code
+ * #include "mbed.h"
+ * #include "USBHID.h"
+ *
+ * USBHID hid;
+ * HID_REPORT recv;
+ * BusOut leds(LED1,LED2,LED3,LED4);
+ *
+ * int main(void) {
+ * while (1) {
+ * hid.read(&recv);
+ * leds = recv.data[0];
+ * }
+ * }
+ * @endcode
+ */
+
+class USBHID: public USBDevice {
+public:
+
+ /**
+ * Constructor
+ *
+ * @param output_report_length Maximum length of a sent report (up to 64 bytes) (default: 64 bytes)
+ * @param input_report_length Maximum length of a received report (up to 64 bytes) (default: 64 bytes)
+ * @param vendor_id Your vendor_id
+ * @param product_id Your product_id
+ * @param product_release Your preoduct_release
+ * @param connect Connect the device
+ */
+ USBHID(uint8_t output_report_length = 64, uint8_t input_report_length = 64, uint16_t vendor_id = 0x1234, uint16_t product_id = 0x0006, uint16_t product_release = 0x0001, bool connect = true);
+
+
+ /**
+ * Send a Report. warning: blocking
+ *
+ * @param report Report which will be sent (a report is defined by all data and the length)
+ * @returns true if successful
+ */
+ bool send(HID_REPORT *report);
+
+
+ /**
+ * Send a Report. warning: non blocking
+ *
+ * @param report Report which will be sent (a report is defined by all data and the length)
+ * @returns true if successful
+ */
+ bool sendNB(HID_REPORT *report);
+
+ /**
+ * Read a report: blocking
+ *
+ * @param report pointer to the report to fill
+ * @returns true if successful
+ */
+ bool read(HID_REPORT * report);
+
+ /**
+ * Read a report: non blocking
+ *
+ * @param report pointer to the report to fill
+ * @returns true if successful
+ */
+ bool readNB(HID_REPORT * report);
+
+protected:
+ uint16_t reportLength;
+
+ /*
+ * Get the Report descriptor
+ *
+ * @returns pointer to the report descriptor
+ */
+ virtual uint8_t * reportDesc();
+
+ /*
+ * Get the length of the report descriptor
+ *
+ * @returns the length of the report descriptor
+ */
+ virtual uint16_t reportDescLength();
+
+ /*
+ * Get string product descriptor
+ *
+ * @returns pointer to the string product descriptor
+ */
+ virtual uint8_t * stringIproductDesc();
+
+ /*
+ * Get string interface descriptor
+ *
+ * @returns pointer to the string interface descriptor
+ */
+ virtual uint8_t * stringIinterfaceDesc();
+
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc();
+
+
+ /*
+ * HID Report received by SET_REPORT request. Warning: Called in ISR context
+ * First byte of data will be the report ID
+ *
+ * @param report Data and length received
+ */
+ virtual void HID_callbackSetReport(HID_REPORT *report){};
+
+
+ /*
+ * Called by USBDevice on Endpoint0 request. Warning: Called in ISR context
+ * This is used to handle extensions to standard requests
+ * and class specific requests
+ *
+ * @returns true if class handles this request
+ */
+ virtual bool USBCallback_request();
+
+
+ /*
+ * Called by USBDevice layer. Set configuration of the device.
+ * For instance, you can add all endpoints that you need on this function.
+ *
+ * @param configuration Number of the configuration
+ * @returns true if class handles this request
+ */
+ virtual bool USBCallback_setConfiguration(uint8_t configuration);
+
+private:
+ HID_REPORT outputReport;
+ uint8_t output_length;
+ uint8_t input_length;
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID_Types.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID_Types.h
new file mode 100644
index 000000000..b8b181bed
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBHID_Types.h
@@ -0,0 +1,91 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBCLASS_HID_TYPES
+#define USBCLASS_HID_TYPES
+
+#include <stdint.h>
+
+/* */
+#define HID_VERSION_1_11 (0x0111)
+
+/* HID Class */
+#define HID_CLASS (3)
+#define HID_SUBCLASS_NONE (0)
+#define HID_PROTOCOL_NONE (0)
+
+/* Descriptors */
+#define HID_DESCRIPTOR (33)
+#define HID_DESCRIPTOR_LENGTH (0x09)
+#define REPORT_DESCRIPTOR (34)
+
+/* Class requests */
+#define GET_REPORT (0x1)
+#define GET_IDLE (0x2)
+#define SET_REPORT (0x9)
+#define SET_IDLE (0xa)
+
+/* HID Class Report Descriptor */
+/* Short items: size is 0, 1, 2 or 3 specifying 0, 1, 2 or 4 (four) bytes */
+/* of data as per HID Class standard */
+
+/* Main items */
+#define INPUT(size) (0x80 | size)
+#define OUTPUT(size) (0x90 | size)
+#define FEATURE(size) (0xb0 | size)
+#define COLLECTION(size) (0xa0 | size)
+#define END_COLLECTION(size) (0xc0 | size)
+
+/* Global items */
+#define USAGE_PAGE(size) (0x04 | size)
+#define LOGICAL_MINIMUM(size) (0x14 | size)
+#define LOGICAL_MAXIMUM(size) (0x24 | size)
+#define PHYSICAL_MINIMUM(size) (0x34 | size)
+#define PHYSICAL_MAXIMUM(size) (0x44 | size)
+#define UNIT_EXPONENT(size) (0x54 | size)
+#define UNIT(size) (0x64 | size)
+#define REPORT_SIZE(size) (0x74 | size)
+#define REPORT_ID(size) (0x84 | size)
+#define REPORT_COUNT(size) (0x94 | size)
+#define PUSH(size) (0xa4 | size)
+#define POP(size) (0xb4 | size)
+
+/* Local items */
+#define USAGE(size) (0x08 | size)
+#define USAGE_MINIMUM(size) (0x18 | size)
+#define USAGE_MAXIMUM(size) (0x28 | size)
+#define DESIGNATOR_INDEX(size) (0x38 | size)
+#define DESIGNATOR_MINIMUM(size) (0x48 | size)
+#define DESIGNATOR_MAXIMUM(size) (0x58 | size)
+#define STRING_INDEX(size) (0x78 | size)
+#define STRING_MINIMUM(size) (0x88 | size)
+#define STRING_MAXIMUM(size) (0x98 | size)
+#define DELIMITER(size) (0xa8 | size)
+
+/* HID Report */
+/* Where report IDs are used the first byte of 'data' will be the */
+/* report ID and 'length' will include this report ID byte. */
+
+#define MAX_HID_REPORT_SIZE (64)
+
+typedef struct {
+ uint32_t length;
+ uint8_t data[MAX_HID_REPORT_SIZE];
+} HID_REPORT;
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBKeyboard.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBKeyboard.cpp
new file mode 100644
index 000000000..df4ca4798
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBKeyboard.cpp
@@ -0,0 +1,553 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+
+#include "USBKeyboard.h"
+
+#define REPORT_ID_KEYBOARD 1
+#define REPORT_ID_VOLUME 3
+
+
+typedef struct {
+ unsigned char usage;
+ unsigned char modifier;
+} KEYMAP;
+
+#ifdef US_KEYBOARD
+/* US keyboard (as HID standard) */
+#define KEYMAP_SIZE (152)
+const KEYMAP keymap[KEYMAP_SIZE] = {
+ {0, 0}, /* NUL */
+ {0, 0}, /* SOH */
+ {0, 0}, /* STX */
+ {0, 0}, /* ETX */
+ {0, 0}, /* EOT */
+ {0, 0}, /* ENQ */
+ {0, 0}, /* ACK */
+ {0, 0}, /* BEL */
+ {0x2a, 0}, /* BS */ /* Keyboard Delete (Backspace) */
+ {0x2b, 0}, /* TAB */ /* Keyboard Tab */
+ {0x28, 0}, /* LF */ /* Keyboard Return (Enter) */
+ {0, 0}, /* VT */
+ {0, 0}, /* FF */
+ {0, 0}, /* CR */
+ {0, 0}, /* SO */
+ {0, 0}, /* SI */
+ {0, 0}, /* DEL */
+ {0, 0}, /* DC1 */
+ {0, 0}, /* DC2 */
+ {0, 0}, /* DC3 */
+ {0, 0}, /* DC4 */
+ {0, 0}, /* NAK */
+ {0, 0}, /* SYN */
+ {0, 0}, /* ETB */
+ {0, 0}, /* CAN */
+ {0, 0}, /* EM */
+ {0, 0}, /* SUB */
+ {0, 0}, /* ESC */
+ {0, 0}, /* FS */
+ {0, 0}, /* GS */
+ {0, 0}, /* RS */
+ {0, 0}, /* US */
+ {0x2c, 0}, /* */
+ {0x1e, KEY_SHIFT}, /* ! */
+ {0x34, KEY_SHIFT}, /* " */
+ {0x20, KEY_SHIFT}, /* # */
+ {0x21, KEY_SHIFT}, /* $ */
+ {0x22, KEY_SHIFT}, /* % */
+ {0x24, KEY_SHIFT}, /* & */
+ {0x34, 0}, /* ' */
+ {0x26, KEY_SHIFT}, /* ( */
+ {0x27, KEY_SHIFT}, /* ) */
+ {0x25, KEY_SHIFT}, /* * */
+ {0x2e, KEY_SHIFT}, /* + */
+ {0x36, 0}, /* , */
+ {0x2d, 0}, /* - */
+ {0x37, 0}, /* . */
+ {0x38, 0}, /* / */
+ {0x27, 0}, /* 0 */
+ {0x1e, 0}, /* 1 */
+ {0x1f, 0}, /* 2 */
+ {0x20, 0}, /* 3 */
+ {0x21, 0}, /* 4 */
+ {0x22, 0}, /* 5 */
+ {0x23, 0}, /* 6 */
+ {0x24, 0}, /* 7 */
+ {0x25, 0}, /* 8 */
+ {0x26, 0}, /* 9 */
+ {0x33, KEY_SHIFT}, /* : */
+ {0x33, 0}, /* ; */
+ {0x36, KEY_SHIFT}, /* < */
+ {0x2e, 0}, /* = */
+ {0x37, KEY_SHIFT}, /* > */
+ {0x38, KEY_SHIFT}, /* ? */
+ {0x1f, KEY_SHIFT}, /* @ */
+ {0x04, KEY_SHIFT}, /* A */
+ {0x05, KEY_SHIFT}, /* B */
+ {0x06, KEY_SHIFT}, /* C */
+ {0x07, KEY_SHIFT}, /* D */
+ {0x08, KEY_SHIFT}, /* E */
+ {0x09, KEY_SHIFT}, /* F */
+ {0x0a, KEY_SHIFT}, /* G */
+ {0x0b, KEY_SHIFT}, /* H */
+ {0x0c, KEY_SHIFT}, /* I */
+ {0x0d, KEY_SHIFT}, /* J */
+ {0x0e, KEY_SHIFT}, /* K */
+ {0x0f, KEY_SHIFT}, /* L */
+ {0x10, KEY_SHIFT}, /* M */
+ {0x11, KEY_SHIFT}, /* N */
+ {0x12, KEY_SHIFT}, /* O */
+ {0x13, KEY_SHIFT}, /* P */
+ {0x14, KEY_SHIFT}, /* Q */
+ {0x15, KEY_SHIFT}, /* R */
+ {0x16, KEY_SHIFT}, /* S */
+ {0x17, KEY_SHIFT}, /* T */
+ {0x18, KEY_SHIFT}, /* U */
+ {0x19, KEY_SHIFT}, /* V */
+ {0x1a, KEY_SHIFT}, /* W */
+ {0x1b, KEY_SHIFT}, /* X */
+ {0x1c, KEY_SHIFT}, /* Y */
+ {0x1d, KEY_SHIFT}, /* Z */
+ {0x2f, 0}, /* [ */
+ {0x31, 0}, /* \ */
+ {0x30, 0}, /* ] */
+ {0x23, KEY_SHIFT}, /* ^ */
+ {0x2d, KEY_SHIFT}, /* _ */
+ {0x35, 0}, /* ` */
+ {0x04, 0}, /* a */
+ {0x05, 0}, /* b */
+ {0x06, 0}, /* c */
+ {0x07, 0}, /* d */
+ {0x08, 0}, /* e */
+ {0x09, 0}, /* f */
+ {0x0a, 0}, /* g */
+ {0x0b, 0}, /* h */
+ {0x0c, 0}, /* i */
+ {0x0d, 0}, /* j */
+ {0x0e, 0}, /* k */
+ {0x0f, 0}, /* l */
+ {0x10, 0}, /* m */
+ {0x11, 0}, /* n */
+ {0x12, 0}, /* o */
+ {0x13, 0}, /* p */
+ {0x14, 0}, /* q */
+ {0x15, 0}, /* r */
+ {0x16, 0}, /* s */
+ {0x17, 0}, /* t */
+ {0x18, 0}, /* u */
+ {0x19, 0}, /* v */
+ {0x1a, 0}, /* w */
+ {0x1b, 0}, /* x */
+ {0x1c, 0}, /* y */
+ {0x1d, 0}, /* z */
+ {0x2f, KEY_SHIFT}, /* { */
+ {0x31, KEY_SHIFT}, /* | */
+ {0x30, KEY_SHIFT}, /* } */
+ {0x35, KEY_SHIFT}, /* ~ */
+ {0,0}, /* DEL */
+
+ {0x3a, 0}, /* F1 */
+ {0x3b, 0}, /* F2 */
+ {0x3c, 0}, /* F3 */
+ {0x3d, 0}, /* F4 */
+ {0x3e, 0}, /* F5 */
+ {0x3f, 0}, /* F6 */
+ {0x40, 0}, /* F7 */
+ {0x41, 0}, /* F8 */
+ {0x42, 0}, /* F9 */
+ {0x43, 0}, /* F10 */
+ {0x44, 0}, /* F11 */
+ {0x45, 0}, /* F12 */
+
+ {0x46, 0}, /* PRINT_SCREEN */
+ {0x47, 0}, /* SCROLL_LOCK */
+ {0x39, 0}, /* CAPS_LOCK */
+ {0x53, 0}, /* NUM_LOCK */
+ {0x49, 0}, /* INSERT */
+ {0x4a, 0}, /* HOME */
+ {0x4b, 0}, /* PAGE_UP */
+ {0x4e, 0}, /* PAGE_DOWN */
+
+ {0x4f, 0}, /* RIGHT_ARROW */
+ {0x50, 0}, /* LEFT_ARROW */
+ {0x51, 0}, /* DOWN_ARROW */
+ {0x52, 0}, /* UP_ARROW */
+};
+
+#else
+/* UK keyboard */
+#define KEYMAP_SIZE (152)
+const KEYMAP keymap[KEYMAP_SIZE] = {
+ {0, 0}, /* NUL */
+ {0, 0}, /* SOH */
+ {0, 0}, /* STX */
+ {0, 0}, /* ETX */
+ {0, 0}, /* EOT */
+ {0, 0}, /* ENQ */
+ {0, 0}, /* ACK */
+ {0, 0}, /* BEL */
+ {0x2a, 0}, /* BS */ /* Keyboard Delete (Backspace) */
+ {0x2b, 0}, /* TAB */ /* Keyboard Tab */
+ {0x28, 0}, /* LF */ /* Keyboard Return (Enter) */
+ {0, 0}, /* VT */
+ {0, 0}, /* FF */
+ {0, 0}, /* CR */
+ {0, 0}, /* SO */
+ {0, 0}, /* SI */
+ {0, 0}, /* DEL */
+ {0, 0}, /* DC1 */
+ {0, 0}, /* DC2 */
+ {0, 0}, /* DC3 */
+ {0, 0}, /* DC4 */
+ {0, 0}, /* NAK */
+ {0, 0}, /* SYN */
+ {0, 0}, /* ETB */
+ {0, 0}, /* CAN */
+ {0, 0}, /* EM */
+ {0, 0}, /* SUB */
+ {0, 0}, /* ESC */
+ {0, 0}, /* FS */
+ {0, 0}, /* GS */
+ {0, 0}, /* RS */
+ {0, 0}, /* US */
+ {0x2c, 0}, /* */
+ {0x1e, KEY_SHIFT}, /* ! */
+ {0x1f, KEY_SHIFT}, /* " */
+ {0x32, 0}, /* # */
+ {0x21, KEY_SHIFT}, /* $ */
+ {0x22, KEY_SHIFT}, /* % */
+ {0x24, KEY_SHIFT}, /* & */
+ {0x34, 0}, /* ' */
+ {0x26, KEY_SHIFT}, /* ( */
+ {0x27, KEY_SHIFT}, /* ) */
+ {0x25, KEY_SHIFT}, /* * */
+ {0x2e, KEY_SHIFT}, /* + */
+ {0x36, 0}, /* , */
+ {0x2d, 0}, /* - */
+ {0x37, 0}, /* . */
+ {0x38, 0}, /* / */
+ {0x27, 0}, /* 0 */
+ {0x1e, 0}, /* 1 */
+ {0x1f, 0}, /* 2 */
+ {0x20, 0}, /* 3 */
+ {0x21, 0}, /* 4 */
+ {0x22, 0}, /* 5 */
+ {0x23, 0}, /* 6 */
+ {0x24, 0}, /* 7 */
+ {0x25, 0}, /* 8 */
+ {0x26, 0}, /* 9 */
+ {0x33, KEY_SHIFT}, /* : */
+ {0x33, 0}, /* ; */
+ {0x36, KEY_SHIFT}, /* < */
+ {0x2e, 0}, /* = */
+ {0x37, KEY_SHIFT}, /* > */
+ {0x38, KEY_SHIFT}, /* ? */
+ {0x34, KEY_SHIFT}, /* @ */
+ {0x04, KEY_SHIFT}, /* A */
+ {0x05, KEY_SHIFT}, /* B */
+ {0x06, KEY_SHIFT}, /* C */
+ {0x07, KEY_SHIFT}, /* D */
+ {0x08, KEY_SHIFT}, /* E */
+ {0x09, KEY_SHIFT}, /* F */
+ {0x0a, KEY_SHIFT}, /* G */
+ {0x0b, KEY_SHIFT}, /* H */
+ {0x0c, KEY_SHIFT}, /* I */
+ {0x0d, KEY_SHIFT}, /* J */
+ {0x0e, KEY_SHIFT}, /* K */
+ {0x0f, KEY_SHIFT}, /* L */
+ {0x10, KEY_SHIFT}, /* M */
+ {0x11, KEY_SHIFT}, /* N */
+ {0x12, KEY_SHIFT}, /* O */
+ {0x13, KEY_SHIFT}, /* P */
+ {0x14, KEY_SHIFT}, /* Q */
+ {0x15, KEY_SHIFT}, /* R */
+ {0x16, KEY_SHIFT}, /* S */
+ {0x17, KEY_SHIFT}, /* T */
+ {0x18, KEY_SHIFT}, /* U */
+ {0x19, KEY_SHIFT}, /* V */
+ {0x1a, KEY_SHIFT}, /* W */
+ {0x1b, KEY_SHIFT}, /* X */
+ {0x1c, KEY_SHIFT}, /* Y */
+ {0x1d, KEY_SHIFT}, /* Z */
+ {0x2f, 0}, /* [ */
+ {0x64, 0}, /* \ */
+ {0x30, 0}, /* ] */
+ {0x23, KEY_SHIFT}, /* ^ */
+ {0x2d, KEY_SHIFT}, /* _ */
+ {0x35, 0}, /* ` */
+ {0x04, 0}, /* a */
+ {0x05, 0}, /* b */
+ {0x06, 0}, /* c */
+ {0x07, 0}, /* d */
+ {0x08, 0}, /* e */
+ {0x09, 0}, /* f */
+ {0x0a, 0}, /* g */
+ {0x0b, 0}, /* h */
+ {0x0c, 0}, /* i */
+ {0x0d, 0}, /* j */
+ {0x0e, 0}, /* k */
+ {0x0f, 0}, /* l */
+ {0x10, 0}, /* m */
+ {0x11, 0}, /* n */
+ {0x12, 0}, /* o */
+ {0x13, 0}, /* p */
+ {0x14, 0}, /* q */
+ {0x15, 0}, /* r */
+ {0x16, 0}, /* s */
+ {0x17, 0}, /* t */
+ {0x18, 0}, /* u */
+ {0x19, 0}, /* v */
+ {0x1a, 0}, /* w */
+ {0x1b, 0}, /* x */
+ {0x1c, 0}, /* y */
+ {0x1d, 0}, /* z */
+ {0x2f, KEY_SHIFT}, /* { */
+ {0x64, KEY_SHIFT}, /* | */
+ {0x30, KEY_SHIFT}, /* } */
+ {0x32, KEY_SHIFT}, /* ~ */
+ {0,0}, /* DEL */
+
+ {0x3a, 0}, /* F1 */
+ {0x3b, 0}, /* F2 */
+ {0x3c, 0}, /* F3 */
+ {0x3d, 0}, /* F4 */
+ {0x3e, 0}, /* F5 */
+ {0x3f, 0}, /* F6 */
+ {0x40, 0}, /* F7 */
+ {0x41, 0}, /* F8 */
+ {0x42, 0}, /* F9 */
+ {0x43, 0}, /* F10 */
+ {0x44, 0}, /* F11 */
+ {0x45, 0}, /* F12 */
+
+ {0x46, 0}, /* PRINT_SCREEN */
+ {0x47, 0}, /* SCROLL_LOCK */
+ {0x39, 0}, /* CAPS_LOCK */
+ {0x53, 0}, /* NUM_LOCK */
+ {0x49, 0}, /* INSERT */
+ {0x4a, 0}, /* HOME */
+ {0x4b, 0}, /* PAGE_UP */
+ {0x4e, 0}, /* PAGE_DOWN */
+
+ {0x4f, 0}, /* RIGHT_ARROW */
+ {0x50, 0}, /* LEFT_ARROW */
+ {0x51, 0}, /* DOWN_ARROW */
+ {0x52, 0}, /* UP_ARROW */
+};
+#endif
+
+uint8_t * USBKeyboard::reportDesc() {
+ static uint8_t reportDescriptor[] = {
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x06, // Keyboard
+ COLLECTION(1), 0x01, // Application
+ REPORT_ID(1), REPORT_ID_KEYBOARD,
+
+ USAGE_PAGE(1), 0x07, // Key Codes
+ USAGE_MINIMUM(1), 0xE0,
+ USAGE_MAXIMUM(1), 0xE7,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ REPORT_SIZE(1), 0x01,
+ REPORT_COUNT(1), 0x08,
+ INPUT(1), 0x02, // Data, Variable, Absolute
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x08,
+ INPUT(1), 0x01, // Constant
+
+
+ REPORT_COUNT(1), 0x05,
+ REPORT_SIZE(1), 0x01,
+ USAGE_PAGE(1), 0x08, // LEDs
+ USAGE_MINIMUM(1), 0x01,
+ USAGE_MAXIMUM(1), 0x05,
+ OUTPUT(1), 0x02, // Data, Variable, Absolute
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x03,
+ OUTPUT(1), 0x01, // Constant
+
+
+ REPORT_COUNT(1), 0x06,
+ REPORT_SIZE(1), 0x08,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x65,
+ USAGE_PAGE(1), 0x07, // Key Codes
+ USAGE_MINIMUM(1), 0x00,
+ USAGE_MAXIMUM(1), 0x65,
+ INPUT(1), 0x00, // Data, Array
+ END_COLLECTION(0),
+
+ // Media Control
+ USAGE_PAGE(1), 0x0C,
+ USAGE(1), 0x01,
+ COLLECTION(1), 0x01,
+ REPORT_ID(1), REPORT_ID_VOLUME,
+ USAGE_PAGE(1), 0x0C,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ REPORT_SIZE(1), 0x01,
+ REPORT_COUNT(1), 0x07,
+ USAGE(1), 0xB5, // Next Track
+ USAGE(1), 0xB6, // Previous Track
+ USAGE(1), 0xB7, // Stop
+ USAGE(1), 0xCD, // Play / Pause
+ USAGE(1), 0xE2, // Mute
+ USAGE(1), 0xE9, // Volume Up
+ USAGE(1), 0xEA, // Volume Down
+ INPUT(1), 0x02, // Input (Data, Variable, Absolute)
+ REPORT_COUNT(1), 0x01,
+ INPUT(1), 0x01,
+ END_COLLECTION(0),
+ };
+ reportLength = sizeof(reportDescriptor);
+ return reportDescriptor;
+}
+
+
+bool USBKeyboard::EPINT_OUT_callback() {
+ uint32_t bytesRead = 0;
+ uint8_t led[65];
+ USBDevice::readEP(EPINT_OUT, led, &bytesRead, MAX_HID_REPORT_SIZE);
+
+ // we take led[1] because led[0] is the report ID
+ lock_status = led[1] & 0x07;
+
+ // We activate the endpoint to be able to recceive data
+ if (!readStart(EPINT_OUT, MAX_HID_REPORT_SIZE))
+ return false;
+ return true;
+}
+
+uint8_t USBKeyboard::lockStatus() {
+ return lock_status;
+}
+
+int USBKeyboard::_putc(int c) {
+ return keyCode(c, keymap[c].modifier);
+}
+
+bool USBKeyboard::keyCode(uint8_t key, uint8_t modifier) {
+ // Send a simulated keyboard keypress. Returns true if successful.
+ HID_REPORT report;
+
+ report.data[0] = REPORT_ID_KEYBOARD;
+ report.data[1] = modifier;
+ report.data[2] = 0;
+ report.data[3] = keymap[key].usage;
+ report.data[4] = 0;
+ report.data[5] = 0;
+ report.data[6] = 0;
+ report.data[7] = 0;
+ report.data[8] = 0;
+
+ report.length = 9;
+
+ if (!send(&report)) {
+ return false;
+ }
+
+ report.data[1] = 0;
+ report.data[3] = 0;
+
+ if (!send(&report)) {
+ return false;
+ }
+
+ return true;
+
+}
+
+
+bool USBKeyboard::mediaControl(MEDIA_KEY key) {
+ HID_REPORT report;
+
+ report.data[0] = REPORT_ID_VOLUME;
+ report.data[1] = (1 << key) & 0x7f;
+
+ report.length = 2;
+
+ if (!send(&report)) {
+ return false;
+ }
+
+ report.data[0] = REPORT_ID_VOLUME;
+ report.data[1] = 0;
+
+ report.length = 2;
+
+ return send(&report);
+}
+
+
+#define DEFAULT_CONFIGURATION (1)
+#define TOTAL_DESCRIPTOR_LENGTH ((1 * CONFIGURATION_DESCRIPTOR_LENGTH) \
+ + (1 * INTERFACE_DESCRIPTOR_LENGTH) \
+ + (1 * HID_DESCRIPTOR_LENGTH) \
+ + (2 * ENDPOINT_DESCRIPTOR_LENGTH))
+
+uint8_t * USBKeyboard::configurationDesc() {
+ static uint8_t configurationDescriptor[] = {
+ CONFIGURATION_DESCRIPTOR_LENGTH,// bLength
+ CONFIGURATION_DESCRIPTOR, // bDescriptorType
+ LSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (LSB)
+ MSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (MSB)
+ 0x01, // bNumInterfaces
+ DEFAULT_CONFIGURATION, // bConfigurationValue
+ 0x00, // iConfiguration
+ C_RESERVED | C_SELF_POWERED, // bmAttributes
+ C_POWER(0), // bMaxPowerHello World from Mbed
+
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x00, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x02, // bNumEndpoints
+ HID_CLASS, // bInterfaceClass
+ 1, // bInterfaceSubClass
+ 1, // bInterfaceProtocol (keyboard)
+ 0x00, // iInterface
+
+ HID_DESCRIPTOR_LENGTH, // bLength
+ HID_DESCRIPTOR, // bDescriptorType
+ LSB(HID_VERSION_1_11), // bcdHID (LSB)
+ MSB(HID_VERSION_1_11), // bcdHID (MSB)
+ 0x00, // bCountryCode
+ 0x01, // bNumDescriptors
+ REPORT_DESCRIPTOR, // bDescriptorType
+ (uint8_t)(LSB(reportDescLength())), // wDescriptorLength (LSB)
+ (uint8_t)(MSB(reportDescLength())), // wDescriptorLength (MSB)
+
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPINT_IN), // bEndpointAddress
+ E_INTERRUPT, // bmAttributes
+ LSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB)
+ 1, // bInterval (milliseconds)
+
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPINT_OUT), // bEndpointAddress
+ E_INTERRUPT, // bmAttributes
+ LSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB)
+ 1, // bInterval (milliseconds)
+ };
+ return configurationDescriptor;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBKeyboard.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBKeyboard.h
new file mode 100644
index 000000000..c58ae56f0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBKeyboard.h
@@ -0,0 +1,183 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBKEYBOARD_H
+#define USBKEYBOARD_H
+
+#include "USBHID.h"
+#include "Stream.h"
+
+/* Modifiers */
+enum MODIFIER_KEY {
+ KEY_CTRL = 1,
+ KEY_SHIFT = 2,
+ KEY_ALT = 4,
+};
+
+
+enum MEDIA_KEY {
+ KEY_NEXT_TRACK, /*!< next Track Button */
+ KEY_PREVIOUS_TRACK, /*!< Previous track Button */
+ KEY_STOP, /*!< Stop Button */
+ KEY_PLAY_PAUSE, /*!< Play/Pause Button */
+ KEY_MUTE, /*!< Mute Button */
+ KEY_VOLUME_UP, /*!< Volume Up Button */
+ KEY_VOLUME_DOWN, /*!< Volume Down Button */
+};
+
+enum FUNCTION_KEY {
+ KEY_F1 = 128, /* F1 key */
+ KEY_F2, /* F2 key */
+ KEY_F3, /* F3 key */
+ KEY_F4, /* F4 key */
+ KEY_F5, /* F5 key */
+ KEY_F6, /* F6 key */
+ KEY_F7, /* F7 key */
+ KEY_F8, /* F8 key */
+ KEY_F9, /* F9 key */
+ KEY_F10, /* F10 key */
+ KEY_F11, /* F11 key */
+ KEY_F12, /* F12 key */
+
+ KEY_PRINT_SCREEN, /* Print Screen key */
+ KEY_SCROLL_LOCK, /* Scroll lock */
+ KEY_CAPS_LOCK, /* caps lock */
+ KEY_NUM_LOCK, /* num lock */
+ KEY_INSERT, /* Insert key */
+ KEY_HOME, /* Home key */
+ KEY_PAGE_UP, /* Page Up key */
+ KEY_PAGE_DOWN, /* Page Down key */
+
+ RIGHT_ARROW, /* Right arrow */
+ LEFT_ARROW, /* Left arrow */
+ DOWN_ARROW, /* Down arrow */
+ UP_ARROW, /* Up arrow */
+};
+
+/**
+ * USBKeyboard example
+ * @code
+ *
+ * #include "mbed.h"
+ * #include "USBKeyboard.h"
+ *
+ * USBKeyboard key;
+ *
+ * int main(void)
+ * {
+ * while (1)
+ * {
+ * key.printf("Hello World\r\n");
+ * wait(1);
+ * }
+ * }
+ *
+ * @endcode
+ */
+class USBKeyboard: public USBHID, public Stream {
+public:
+
+ /**
+ * Constructor
+ *
+ *
+ * @param leds Leds bus: first: NUM_LOCK, second: CAPS_LOCK, third: SCROLL_LOCK
+ * @param vendor_id Your vendor_id (default: 0x1235)
+ * @param product_id Your product_id (default: 0x0050)
+ * @param product_release Your preoduct_release (default: 0x0001)
+ *
+ */
+ USBKeyboard(uint16_t vendor_id = 0x1235, uint16_t product_id = 0x0050, uint16_t product_release = 0x0001):
+ USBHID(0, 0, vendor_id, product_id, product_release, false) {
+ lock_status = 0;
+ connect();
+ };
+
+ /**
+ * To send a character defined by a modifier(CTRL, SHIFT, ALT) and the key
+ *
+ * @code
+ * //To send CTRL + s (save)
+ * keyboard.keyCode('s', KEY_CTRL);
+ * @endcode
+ *
+ * @param modifier bit 0: KEY_CTRL, bit 1: KEY_SHIFT, bit 2: KEY_ALT (default: 0)
+ * @param key character to send
+ * @returns true if there is no error, false otherwise
+ */
+ bool keyCode(uint8_t key, uint8_t modifier = 0);
+
+ /**
+ * Send a character
+ *
+ * @param c character to be sent
+ * @returns true if there is no error, false otherwise
+ */
+ virtual int _putc(int c);
+
+ /**
+ * Control media keys
+ *
+ * @param key media key pressed (KEY_NEXT_TRACK, KEY_PREVIOUS_TRACK, KEY_STOP, KEY_PLAY_PAUSE, KEY_MUTE, KEY_VOLUME_UP, KEY_VOLUME_DOWN)
+ * @returns true if there is no error, false otherwise
+ */
+ bool mediaControl(MEDIA_KEY key);
+
+ /*
+ * To define the report descriptor. Warning: this method has to store the length of the report descriptor in reportLength.
+ *
+ * @returns pointer to the report descriptor
+ */
+ virtual uint8_t * reportDesc();
+
+ /*
+ * Called when a data is received on the OUT endpoint. Useful to switch on LED of LOCK keys
+ *
+ * @returns if handle by subclass, return true
+ */
+ virtual bool EPINT_OUT_callback();
+
+ /**
+ * Read status of lock keys. Useful to switch-on/off leds according to key pressed. Only the first three bits of the result is important:
+ * - First bit: NUM_LOCK
+ * - Second bit: CAPS_LOCK
+ * - Third bit: SCROLL_LOCK
+ *
+ * @returns status of lock keys
+ */
+ uint8_t lockStatus();
+
+protected:
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc();
+
+private:
+ //dummy otherwise it doesn,t compile (we must define all methods of an abstract class)
+ virtual int _getc() {
+ return -1;
+ };
+
+ uint8_t lock_status;
+
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouse.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouse.cpp
new file mode 100644
index 000000000..980e67909
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouse.cpp
@@ -0,0 +1,245 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBMouse.h"
+
+bool USBMouse::update(int16_t x, int16_t y, uint8_t button, int8_t z) {
+ switch (mouse_type) {
+ case REL_MOUSE:
+ while (x > 127) {
+ if (!mouseSend(127, 0, button, z)) return false;
+ x = x - 127;
+ }
+ while (x < -128) {
+ if (!mouseSend(-128, 0, button, z)) return false;
+ x = x + 128;
+ }
+ while (y > 127) {
+ if (!mouseSend(0, 127, button, z)) return false;
+ y = y - 127;
+ }
+ while (y < -128) {
+ if (!mouseSend(0, -128, button, z)) return false;
+ y = y + 128;
+ }
+ return mouseSend(x, y, button, z);
+ case ABS_MOUSE:
+ HID_REPORT report;
+
+ report.data[0] = x & 0xff;
+ report.data[1] = (x >> 8) & 0xff;
+ report.data[2] = y & 0xff;
+ report.data[3] = (y >> 8) & 0xff;
+ report.data[4] = -z;
+ report.data[5] = button & 0x07;
+
+ report.length = 6;
+
+ return send(&report);
+ default:
+ return false;
+ }
+}
+
+bool USBMouse::mouseSend(int8_t x, int8_t y, uint8_t buttons, int8_t z) {
+ HID_REPORT report;
+ report.data[0] = buttons & 0x07;
+ report.data[1] = x;
+ report.data[2] = y;
+ report.data[3] = -z; // >0 to scroll down, <0 to scroll up
+
+ report.length = 4;
+
+ return send(&report);
+}
+
+bool USBMouse::move(int16_t x, int16_t y) {
+ return update(x, y, button, 0);
+}
+
+bool USBMouse::scroll(int8_t z) {
+ return update(0, 0, button, z);
+}
+
+
+bool USBMouse::doubleClick() {
+ if (!click(MOUSE_LEFT))
+ return false;
+ wait(0.1);
+ return click(MOUSE_LEFT);
+}
+
+bool USBMouse::click(uint8_t button) {
+ if (!update(0, 0, button, 0))
+ return false;
+ wait(0.01);
+ return update(0, 0, 0, 0);
+}
+
+bool USBMouse::press(uint8_t button_) {
+ button = button_ & 0x07;
+ return update(0, 0, button, 0);
+}
+
+bool USBMouse::release(uint8_t button_) {
+ button = (button & (~button_)) & 0x07;
+ return update(0, 0, button, 0);
+}
+
+
+uint8_t * USBMouse::reportDesc() {
+
+ if (mouse_type == REL_MOUSE) {
+ static uint8_t reportDescriptor[] = {
+ USAGE_PAGE(1), 0x01, // Genric Desktop
+ USAGE(1), 0x02, // Mouse
+ COLLECTION(1), 0x01, // Application
+ USAGE(1), 0x01, // Pointer
+ COLLECTION(1), 0x00, // Physical
+
+ REPORT_COUNT(1), 0x03,
+ REPORT_SIZE(1), 0x01,
+ USAGE_PAGE(1), 0x09, // Buttons
+ USAGE_MINIMUM(1), 0x1,
+ USAGE_MAXIMUM(1), 0x3,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ INPUT(1), 0x02,
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x05,
+ INPUT(1), 0x01,
+
+ REPORT_COUNT(1), 0x03,
+ REPORT_SIZE(1), 0x08,
+ USAGE_PAGE(1), 0x01,
+ USAGE(1), 0x30, // X
+ USAGE(1), 0x31, // Y
+ USAGE(1), 0x38, // scroll
+ LOGICAL_MINIMUM(1), 0x81,
+ LOGICAL_MAXIMUM(1), 0x7f,
+ INPUT(1), 0x06, // Relative data
+
+ END_COLLECTION(0),
+ END_COLLECTION(0),
+ };
+ reportLength = sizeof(reportDescriptor);
+ return reportDescriptor;
+ } else if (mouse_type == ABS_MOUSE) {
+ static uint8_t reportDescriptor[] = {
+
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x02, // Mouse
+ COLLECTION(1), 0x01, // Application
+ USAGE(1), 0x01, // Pointer
+ COLLECTION(1), 0x00, // Physical
+
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x30, // X
+ USAGE(1), 0x31, // Y
+ LOGICAL_MINIMUM(1), 0x00, // 0
+ LOGICAL_MAXIMUM(2), 0xff, 0x7f, // 32767
+ REPORT_SIZE(1), 0x10,
+ REPORT_COUNT(1), 0x02,
+ INPUT(1), 0x02, // Data, Variable, Absolute
+
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x38, // scroll
+ LOGICAL_MINIMUM(1), 0x81, // -127
+ LOGICAL_MAXIMUM(1), 0x7f, // 127
+ REPORT_SIZE(1), 0x08,
+ REPORT_COUNT(1), 0x01,
+ INPUT(1), 0x06, // Data, Variable, Relative
+
+ USAGE_PAGE(1), 0x09, // Buttons
+ USAGE_MINIMUM(1), 0x01,
+ USAGE_MAXIMUM(1), 0x03,
+ LOGICAL_MINIMUM(1), 0x00, // 0
+ LOGICAL_MAXIMUM(1), 0x01, // 1
+ REPORT_COUNT(1), 0x03,
+ REPORT_SIZE(1), 0x01,
+ INPUT(1), 0x02, // Data, Variable, Absolute
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x05,
+ INPUT(1), 0x01, // Constant
+
+ END_COLLECTION(0),
+ END_COLLECTION(0)
+ };
+ reportLength = sizeof(reportDescriptor);
+ return reportDescriptor;
+ }
+ return NULL;
+}
+
+#define DEFAULT_CONFIGURATION (1)
+#define TOTAL_DESCRIPTOR_LENGTH ((1 * CONFIGURATION_DESCRIPTOR_LENGTH) \
+ + (1 * INTERFACE_DESCRIPTOR_LENGTH) \
+ + (1 * HID_DESCRIPTOR_LENGTH) \
+ + (2 * ENDPOINT_DESCRIPTOR_LENGTH))
+
+uint8_t * USBMouse::configurationDesc() {
+ static uint8_t configurationDescriptor[] = {
+ CONFIGURATION_DESCRIPTOR_LENGTH,// bLength
+ CONFIGURATION_DESCRIPTOR, // bDescriptorType
+ LSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (LSB)
+ MSB(TOTAL_DESCRIPTOR_LENGTH), // wTotalLength (MSB)
+ 0x01, // bNumInterfaces
+ DEFAULT_CONFIGURATION, // bConfigurationValue
+ 0x00, // iConfiguration
+ C_RESERVED | C_SELF_POWERED, // bmAttributes
+ C_POWER(0), // bMaxPowerHello World from Mbed
+
+ INTERFACE_DESCRIPTOR_LENGTH, // bLength
+ INTERFACE_DESCRIPTOR, // bDescriptorType
+ 0x00, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x02, // bNumEndpoints
+ HID_CLASS, // bInterfaceClass
+ 1, // bInterfaceSubClass
+ 2, // bInterfaceProtocol (mouse)
+ 0x00, // iInterface
+
+ HID_DESCRIPTOR_LENGTH, // bLength
+ HID_DESCRIPTOR, // bDescriptorType
+ LSB(HID_VERSION_1_11), // bcdHID (LSB)
+ MSB(HID_VERSION_1_11), // bcdHID (MSB)
+ 0x00, // bCountryCode
+ 0x01, // bNumDescriptors
+ REPORT_DESCRIPTOR, // bDescriptorType
+ (uint8_t)(LSB(reportDescLength())), // wDescriptorLength (LSB)
+ (uint8_t)(MSB(reportDescLength())), // wDescriptorLength (MSB)
+
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPINT_IN), // bEndpointAddress
+ E_INTERRUPT, // bmAttributes
+ LSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB)
+ 1, // bInterval (milliseconds)
+
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPINT_OUT), // bEndpointAddress
+ E_INTERRUPT, // bmAttributes
+ LSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB)
+ 1, // bInterval (milliseconds)
+ };
+ return configurationDescriptor;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouse.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouse.h
new file mode 100644
index 000000000..7aa426334
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouse.h
@@ -0,0 +1,209 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBMOUSE_H
+#define USBMOUSE_H
+
+#include "USBHID.h"
+
+#define REPORT_ID_MOUSE 2
+
+/* Common usage */
+
+enum MOUSE_BUTTON
+{
+ MOUSE_LEFT = 1,
+ MOUSE_RIGHT = 2,
+ MOUSE_MIDDLE = 4,
+};
+
+/* X and Y limits */
+/* These values do not directly map to screen pixels */
+/* Zero may be interpreted as meaning 'no movement' */
+#define X_MIN_ABS (1) /*!< Minimum value on x-axis */
+#define Y_MIN_ABS (1) /*!< Minimum value on y-axis */
+#define X_MAX_ABS (0x7fff) /*!< Maximum value on x-axis */
+#define Y_MAX_ABS (0x7fff) /*!< Maximum value on y-axis */
+
+#define X_MIN_REL (-127) /*!< The maximum value that we can move to the left on the x-axis */
+#define Y_MIN_REL (-127) /*!< The maximum value that we can move up on the y-axis */
+#define X_MAX_REL (127) /*!< The maximum value that we can move to the right on the x-axis */
+#define Y_MAX_REL (127) /*!< The maximum value that we can move down on the y-axis */
+
+enum MOUSE_TYPE
+{
+ ABS_MOUSE,
+ REL_MOUSE,
+};
+
+/**
+ *
+ * USBMouse example
+ * @code
+ * #include "mbed.h"
+ * #include "USBMouse.h"
+ *
+ * USBMouse mouse;
+ *
+ * int main(void)
+ * {
+ * while (1)
+ * {
+ * mouse.move(20, 0);
+ * wait(0.5);
+ * }
+ * }
+ *
+ * @endcode
+ *
+ *
+ * @code
+ * #include "mbed.h"
+ * #include "USBMouse.h"
+ * #include <math.h>
+ *
+ * USBMouse mouse(ABS_MOUSE);
+ *
+ * int main(void)
+ * {
+ * uint16_t x_center = (X_MAX_ABS - X_MIN_ABS)/2;
+ * uint16_t y_center = (Y_MAX_ABS - Y_MIN_ABS)/2;
+ * uint16_t x_screen = 0;
+ * uint16_t y_screen = 0;
+ *
+ * uint32_t x_origin = x_center;
+ * uint32_t y_origin = y_center;
+ * uint32_t radius = 5000;
+ * uint32_t angle = 0;
+ *
+ * while (1)
+ * {
+ * x_screen = x_origin + cos((double)angle*3.14/180.0)*radius;
+ * y_screen = y_origin + sin((double)angle*3.14/180.0)*radius;
+ *
+ * mouse.move(x_screen, y_screen);
+ * angle += 3;
+ * wait(0.01);
+ * }
+ * }
+ *
+ * @endcode
+ */
+class USBMouse: public USBHID
+{
+ public:
+
+ /**
+ * Constructor
+ *
+ * @param mouse_type Mouse type: ABS_MOUSE (absolute mouse) or REL_MOUSE (relative mouse) (default: REL_MOUSE)
+ * @param vendor_id Your vendor_id (default: 0x1234)
+ * @param product_id Your product_id (default: 0x0001)
+ * @param product_release Your preoduct_release (default: 0x0001)
+ *
+ */
+ USBMouse(MOUSE_TYPE mouse_type = REL_MOUSE, uint16_t vendor_id = 0x1234, uint16_t product_id = 0x0001, uint16_t product_release = 0x0001):
+ USBHID(0, 0, vendor_id, product_id, product_release, false)
+ {
+ button = 0;
+ this->mouse_type = mouse_type;
+ connect();
+ };
+
+ /**
+ * Write a state of the mouse
+ *
+ * @param x x-axis position
+ * @param y y-axis position
+ * @param buttons buttons state (first bit represents MOUSE_LEFT, second bit MOUSE_RIGHT and third bit MOUSE_MIDDLE)
+ * @param z wheel state (>0 to scroll down, <0 to scroll up)
+ * @returns true if there is no error, false otherwise
+ */
+ bool update(int16_t x, int16_t y, uint8_t buttons, int8_t z);
+
+
+ /**
+ * Move the cursor to (x, y)
+ *
+ * @param x-axis position
+ * @param y-axis position
+ * @returns true if there is no error, false otherwise
+ */
+ bool move(int16_t x, int16_t y);
+
+ /**
+ * Press one or several buttons
+ *
+ * @param button button state (ex: press(MOUSE_LEFT))
+ * @returns true if there is no error, false otherwise
+ */
+ bool press(uint8_t button);
+
+ /**
+ * Release one or several buttons
+ *
+ * @param button button state (ex: release(MOUSE_LEFT))
+ * @returns true if there is no error, false otherwise
+ */
+ bool release(uint8_t button);
+
+ /**
+ * Double click (MOUSE_LEFT)
+ *
+ * @returns true if there is no error, false otherwise
+ */
+ bool doubleClick();
+
+ /**
+ * Click
+ *
+ * @param button state of the buttons ( ex: clic(MOUSE_LEFT))
+ * @returns true if there is no error, false otherwise
+ */
+ bool click(uint8_t button);
+
+ /**
+ * Scrolling
+ *
+ * @param z value of the wheel (>0 to go down, <0 to go up)
+ * @returns true if there is no error, false otherwise
+ */
+ bool scroll(int8_t z);
+
+ /*
+ * To define the report descriptor. Warning: this method has to store the length of the report descriptor in reportLength.
+ *
+ * @returns pointer to the report descriptor
+ */
+ virtual uint8_t * reportDesc();
+
+ protected:
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc();
+
+ private:
+ MOUSE_TYPE mouse_type;
+ uint8_t button;
+ bool mouseSend(int8_t x, int8_t y, uint8_t buttons, int8_t z);
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouseKeyboard.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouseKeyboard.cpp
new file mode 100644
index 000000000..cd6809120
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouseKeyboard.cpp
@@ -0,0 +1,706 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBMouseKeyboard.h"
+
+typedef struct {
+ unsigned char usage;
+ unsigned char modifier;
+} KEYMAP;
+
+#ifdef US_KEYBOARD
+/* US keyboard (as HID standard) */
+#define KEYMAP_SIZE (152)
+const KEYMAP keymap[KEYMAP_SIZE] = {
+ {0, 0}, /* NUL */
+ {0, 0}, /* SOH */
+ {0, 0}, /* STX */
+ {0, 0}, /* ETX */
+ {0, 0}, /* EOT */
+ {0, 0}, /* ENQ */
+ {0, 0}, /* ACK */
+ {0, 0}, /* BEL */
+ {0x2a, 0}, /* BS */ /* Keyboard Delete (Backspace) */
+ {0x2b, 0}, /* TAB */ /* Keyboard Tab */
+ {0x28, 0}, /* LF */ /* Keyboard Return (Enter) */
+ {0, 0}, /* VT */
+ {0, 0}, /* FF */
+ {0, 0}, /* CR */
+ {0, 0}, /* SO */
+ {0, 0}, /* SI */
+ {0, 0}, /* DEL */
+ {0, 0}, /* DC1 */
+ {0, 0}, /* DC2 */
+ {0, 0}, /* DC3 */
+ {0, 0}, /* DC4 */
+ {0, 0}, /* NAK */
+ {0, 0}, /* SYN */
+ {0, 0}, /* ETB */
+ {0, 0}, /* CAN */
+ {0, 0}, /* EM */
+ {0, 0}, /* SUB */
+ {0, 0}, /* ESC */
+ {0, 0}, /* FS */
+ {0, 0}, /* GS */
+ {0, 0}, /* RS */
+ {0, 0}, /* US */
+ {0x2c, 0}, /* */
+ {0x1e, KEY_SHIFT}, /* ! */
+ {0x34, KEY_SHIFT}, /* " */
+ {0x20, KEY_SHIFT}, /* # */
+ {0x21, KEY_SHIFT}, /* $ */
+ {0x22, KEY_SHIFT}, /* % */
+ {0x24, KEY_SHIFT}, /* & */
+ {0x34, 0}, /* ' */
+ {0x26, KEY_SHIFT}, /* ( */
+ {0x27, KEY_SHIFT}, /* ) */
+ {0x25, KEY_SHIFT}, /* * */
+ {0x2e, KEY_SHIFT}, /* + */
+ {0x36, 0}, /* , */
+ {0x2d, 0}, /* - */
+ {0x37, 0}, /* . */
+ {0x38, 0}, /* / */
+ {0x27, 0}, /* 0 */
+ {0x1e, 0}, /* 1 */
+ {0x1f, 0}, /* 2 */
+ {0x20, 0}, /* 3 */
+ {0x21, 0}, /* 4 */
+ {0x22, 0}, /* 5 */
+ {0x23, 0}, /* 6 */
+ {0x24, 0}, /* 7 */
+ {0x25, 0}, /* 8 */
+ {0x26, 0}, /* 9 */
+ {0x33, KEY_SHIFT}, /* : */
+ {0x33, 0}, /* ; */
+ {0x36, KEY_SHIFT}, /* < */
+ {0x2e, 0}, /* = */
+ {0x37, KEY_SHIFT}, /* > */
+ {0x38, KEY_SHIFT}, /* ? */
+ {0x1f, KEY_SHIFT}, /* @ */
+ {0x04, KEY_SHIFT}, /* A */
+ {0x05, KEY_SHIFT}, /* B */
+ {0x06, KEY_SHIFT}, /* C */
+ {0x07, KEY_SHIFT}, /* D */
+ {0x08, KEY_SHIFT}, /* E */
+ {0x09, KEY_SHIFT}, /* F */
+ {0x0a, KEY_SHIFT}, /* G */
+ {0x0b, KEY_SHIFT}, /* H */
+ {0x0c, KEY_SHIFT}, /* I */
+ {0x0d, KEY_SHIFT}, /* J */
+ {0x0e, KEY_SHIFT}, /* K */
+ {0x0f, KEY_SHIFT}, /* L */
+ {0x10, KEY_SHIFT}, /* M */
+ {0x11, KEY_SHIFT}, /* N */
+ {0x12, KEY_SHIFT}, /* O */
+ {0x13, KEY_SHIFT}, /* P */
+ {0x14, KEY_SHIFT}, /* Q */
+ {0x15, KEY_SHIFT}, /* R */
+ {0x16, KEY_SHIFT}, /* S */
+ {0x17, KEY_SHIFT}, /* T */
+ {0x18, KEY_SHIFT}, /* U */
+ {0x19, KEY_SHIFT}, /* V */
+ {0x1a, KEY_SHIFT}, /* W */
+ {0x1b, KEY_SHIFT}, /* X */
+ {0x1c, KEY_SHIFT}, /* Y */
+ {0x1d, KEY_SHIFT}, /* Z */
+ {0x2f, 0}, /* [ */
+ {0x31, 0}, /* \ */
+ {0x30, 0}, /* ] */
+ {0x23, KEY_SHIFT}, /* ^ */
+ {0x2d, KEY_SHIFT}, /* _ */
+ {0x35, 0}, /* ` */
+ {0x04, 0}, /* a */
+ {0x05, 0}, /* b */
+ {0x06, 0}, /* c */
+ {0x07, 0}, /* d */
+ {0x08, 0}, /* e */
+ {0x09, 0}, /* f */
+ {0x0a, 0}, /* g */
+ {0x0b, 0}, /* h */
+ {0x0c, 0}, /* i */
+ {0x0d, 0}, /* j */
+ {0x0e, 0}, /* k */
+ {0x0f, 0}, /* l */
+ {0x10, 0}, /* m */
+ {0x11, 0}, /* n */
+ {0x12, 0}, /* o */
+ {0x13, 0}, /* p */
+ {0x14, 0}, /* q */
+ {0x15, 0}, /* r */
+ {0x16, 0}, /* s */
+ {0x17, 0}, /* t */
+ {0x18, 0}, /* u */
+ {0x19, 0}, /* v */
+ {0x1a, 0}, /* w */
+ {0x1b, 0}, /* x */
+ {0x1c, 0}, /* y */
+ {0x1d, 0}, /* z */
+ {0x2f, KEY_SHIFT}, /* { */
+ {0x31, KEY_SHIFT}, /* | */
+ {0x30, KEY_SHIFT}, /* } */
+ {0x35, KEY_SHIFT}, /* ~ */
+ {0,0}, /* DEL */
+
+ {0x3a, 0}, /* F1 */
+ {0x3b, 0}, /* F2 */
+ {0x3c, 0}, /* F3 */
+ {0x3d, 0}, /* F4 */
+ {0x3e, 0}, /* F5 */
+ {0x3f, 0}, /* F6 */
+ {0x40, 0}, /* F7 */
+ {0x41, 0}, /* F8 */
+ {0x42, 0}, /* F9 */
+ {0x43, 0}, /* F10 */
+ {0x44, 0}, /* F11 */
+ {0x45, 0}, /* F12 */
+
+ {0x46, 0}, /* PRINT_SCREEN */
+ {0x47, 0}, /* SCROLL_LOCK */
+ {0x39, 0}, /* CAPS_LOCK */
+ {0x53, 0}, /* NUM_LOCK */
+ {0x49, 0}, /* INSERT */
+ {0x4a, 0}, /* HOME */
+ {0x4b, 0}, /* PAGE_UP */
+ {0x4e, 0}, /* PAGE_DOWN */
+
+ {0x4f, 0}, /* RIGHT_ARROW */
+ {0x50, 0}, /* LEFT_ARROW */
+ {0x51, 0}, /* DOWN_ARROW */
+ {0x52, 0}, /* UP_ARROW */
+};
+
+#else
+/* UK keyboard */
+#define KEYMAP_SIZE (152)
+const KEYMAP keymap[KEYMAP_SIZE] = {
+ {0, 0}, /* NUL */
+ {0, 0}, /* SOH */
+ {0, 0}, /* STX */
+ {0, 0}, /* ETX */
+ {0, 0}, /* EOT */
+ {0, 0}, /* ENQ */
+ {0, 0}, /* ACK */
+ {0, 0}, /* BEL */
+ {0x2a, 0}, /* BS */ /* Keyboard Delete (Backspace) */
+ {0x2b, 0}, /* TAB */ /* Keyboard Tab */
+ {0x28, 0}, /* LF */ /* Keyboard Return (Enter) */
+ {0, 0}, /* VT */
+ {0, 0}, /* FF */
+ {0, 0}, /* CR */
+ {0, 0}, /* SO */
+ {0, 0}, /* SI */
+ {0, 0}, /* DEL */
+ {0, 0}, /* DC1 */
+ {0, 0}, /* DC2 */
+ {0, 0}, /* DC3 */
+ {0, 0}, /* DC4 */
+ {0, 0}, /* NAK */
+ {0, 0}, /* SYN */
+ {0, 0}, /* ETB */
+ {0, 0}, /* CAN */
+ {0, 0}, /* EM */
+ {0, 0}, /* SUB */
+ {0, 0}, /* ESC */
+ {0, 0}, /* FS */
+ {0, 0}, /* GS */
+ {0, 0}, /* RS */
+ {0, 0}, /* US */
+ {0x2c, 0}, /* */
+ {0x1e, KEY_SHIFT}, /* ! */
+ {0x1f, KEY_SHIFT}, /* " */
+ {0x32, 0}, /* # */
+ {0x21, KEY_SHIFT}, /* $ */
+ {0x22, KEY_SHIFT}, /* % */
+ {0x24, KEY_SHIFT}, /* & */
+ {0x34, 0}, /* ' */
+ {0x26, KEY_SHIFT}, /* ( */
+ {0x27, KEY_SHIFT}, /* ) */
+ {0x25, KEY_SHIFT}, /* * */
+ {0x2e, KEY_SHIFT}, /* + */
+ {0x36, 0}, /* , */
+ {0x2d, 0}, /* - */
+ {0x37, 0}, /* . */
+ {0x38, 0}, /* / */
+ {0x27, 0}, /* 0 */
+ {0x1e, 0}, /* 1 */
+ {0x1f, 0}, /* 2 */
+ {0x20, 0}, /* 3 */
+ {0x21, 0}, /* 4 */
+ {0x22, 0}, /* 5 */
+ {0x23, 0}, /* 6 */
+ {0x24, 0}, /* 7 */
+ {0x25, 0}, /* 8 */
+ {0x26, 0}, /* 9 */
+ {0x33, KEY_SHIFT}, /* : */
+ {0x33, 0}, /* ; */
+ {0x36, KEY_SHIFT}, /* < */
+ {0x2e, 0}, /* = */
+ {0x37, KEY_SHIFT}, /* > */
+ {0x38, KEY_SHIFT}, /* ? */
+ {0x34, KEY_SHIFT}, /* @ */
+ {0x04, KEY_SHIFT}, /* A */
+ {0x05, KEY_SHIFT}, /* B */
+ {0x06, KEY_SHIFT}, /* C */
+ {0x07, KEY_SHIFT}, /* D */
+ {0x08, KEY_SHIFT}, /* E */
+ {0x09, KEY_SHIFT}, /* F */
+ {0x0a, KEY_SHIFT}, /* G */
+ {0x0b, KEY_SHIFT}, /* H */
+ {0x0c, KEY_SHIFT}, /* I */
+ {0x0d, KEY_SHIFT}, /* J */
+ {0x0e, KEY_SHIFT}, /* K */
+ {0x0f, KEY_SHIFT}, /* L */
+ {0x10, KEY_SHIFT}, /* M */
+ {0x11, KEY_SHIFT}, /* N */
+ {0x12, KEY_SHIFT}, /* O */
+ {0x13, KEY_SHIFT}, /* P */
+ {0x14, KEY_SHIFT}, /* Q */
+ {0x15, KEY_SHIFT}, /* R */
+ {0x16, KEY_SHIFT}, /* S */
+ {0x17, KEY_SHIFT}, /* T */
+ {0x18, KEY_SHIFT}, /* U */
+ {0x19, KEY_SHIFT}, /* V */
+ {0x1a, KEY_SHIFT}, /* W */
+ {0x1b, KEY_SHIFT}, /* X */
+ {0x1c, KEY_SHIFT}, /* Y */
+ {0x1d, KEY_SHIFT}, /* Z */
+ {0x2f, 0}, /* [ */
+ {0x64, 0}, /* \ */
+ {0x30, 0}, /* ] */
+ {0x23, KEY_SHIFT}, /* ^ */
+ {0x2d, KEY_SHIFT}, /* _ */
+ {0x35, 0}, /* ` */
+ {0x04, 0}, /* a */
+ {0x05, 0}, /* b */
+ {0x06, 0}, /* c */
+ {0x07, 0}, /* d */
+ {0x08, 0}, /* e */
+ {0x09, 0}, /* f */
+ {0x0a, 0}, /* g */
+ {0x0b, 0}, /* h */
+ {0x0c, 0}, /* i */
+ {0x0d, 0}, /* j */
+ {0x0e, 0}, /* k */
+ {0x0f, 0}, /* l */
+ {0x10, 0}, /* m */
+ {0x11, 0}, /* n */
+ {0x12, 0}, /* o */
+ {0x13, 0}, /* p */
+ {0x14, 0}, /* q */
+ {0x15, 0}, /* r */
+ {0x16, 0}, /* s */
+ {0x17, 0}, /* t */
+ {0x18, 0}, /* u */
+ {0x19, 0}, /* v */
+ {0x1a, 0}, /* w */
+ {0x1b, 0}, /* x */
+ {0x1c, 0}, /* y */
+ {0x1d, 0}, /* z */
+ {0x2f, KEY_SHIFT}, /* { */
+ {0x64, KEY_SHIFT}, /* | */
+ {0x30, KEY_SHIFT}, /* } */
+ {0x32, KEY_SHIFT}, /* ~ */
+ {0,0}, /* DEL */
+
+ {0x3a, 0}, /* F1 */
+ {0x3b, 0}, /* F2 */
+ {0x3c, 0}, /* F3 */
+ {0x3d, 0}, /* F4 */
+ {0x3e, 0}, /* F5 */
+ {0x3f, 0}, /* F6 */
+ {0x40, 0}, /* F7 */
+ {0x41, 0}, /* F8 */
+ {0x42, 0}, /* F9 */
+ {0x43, 0}, /* F10 */
+ {0x44, 0}, /* F11 */
+ {0x45, 0}, /* F12 */
+
+ {0x46, 0}, /* PRINT_SCREEN */
+ {0x47, 0}, /* SCROLL_LOCK */
+ {0x39, 0}, /* CAPS_LOCK */
+ {0x53, 0}, /* NUM_LOCK */
+ {0x49, 0}, /* INSERT */
+ {0x4a, 0}, /* HOME */
+ {0x4b, 0}, /* PAGE_UP */
+ {0x4e, 0}, /* PAGE_DOWN */
+
+ {0x4f, 0}, /* RIGHT_ARROW */
+ {0x50, 0}, /* LEFT_ARROW */
+ {0x51, 0}, /* DOWN_ARROW */
+ {0x52, 0}, /* UP_ARROW */
+};
+#endif
+
+
+uint8_t * USBMouseKeyboard::reportDesc() {
+ if (mouse_type == REL_MOUSE) {
+ static uint8_t reportDescriptor[] = {
+ // Keyboard
+ USAGE_PAGE(1), 0x01,
+ USAGE(1), 0x06,
+ COLLECTION(1), 0x01,
+ REPORT_ID(1), REPORT_ID_KEYBOARD,
+ USAGE_PAGE(1), 0x07,
+ USAGE_MINIMUM(1), 0xE0,
+ USAGE_MAXIMUM(1), 0xE7,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ REPORT_SIZE(1), 0x01,
+ REPORT_COUNT(1), 0x08,
+ INPUT(1), 0x02,
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x08,
+ INPUT(1), 0x01,
+ REPORT_COUNT(1), 0x05,
+ REPORT_SIZE(1), 0x01,
+ USAGE_PAGE(1), 0x08,
+ USAGE_MINIMUM(1), 0x01,
+ USAGE_MAXIMUM(1), 0x05,
+ OUTPUT(1), 0x02,
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x03,
+ OUTPUT(1), 0x01,
+ REPORT_COUNT(1), 0x06,
+ REPORT_SIZE(1), 0x08,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(2), 0xff, 0x00,
+ USAGE_PAGE(1), 0x07,
+ USAGE_MINIMUM(1), 0x00,
+ USAGE_MAXIMUM(2), 0xff, 0x00,
+ INPUT(1), 0x00,
+ END_COLLECTION(0),
+
+ // Mouse
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x02, // Mouse
+ COLLECTION(1), 0x01, // Application
+ USAGE(1), 0x01, // Pointer
+ COLLECTION(1), 0x00, // Physical
+ REPORT_ID(1), REPORT_ID_MOUSE,
+ REPORT_COUNT(1), 0x03,
+ REPORT_SIZE(1), 0x01,
+ USAGE_PAGE(1), 0x09, // Buttons
+ USAGE_MINIMUM(1), 0x1,
+ USAGE_MAXIMUM(1), 0x3,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ INPUT(1), 0x02,
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x05,
+ INPUT(1), 0x01,
+ REPORT_COUNT(1), 0x03,
+ REPORT_SIZE(1), 0x08,
+ USAGE_PAGE(1), 0x01,
+ USAGE(1), 0x30, // X
+ USAGE(1), 0x31, // Y
+ USAGE(1), 0x38, // scroll
+ LOGICAL_MINIMUM(1), 0x81,
+ LOGICAL_MAXIMUM(1), 0x7f,
+ INPUT(1), 0x06,
+ END_COLLECTION(0),
+ END_COLLECTION(0),
+
+
+ // Media Control
+ USAGE_PAGE(1), 0x0C,
+ USAGE(1), 0x01,
+ COLLECTION(1), 0x01,
+ REPORT_ID(1), REPORT_ID_VOLUME,
+ USAGE_PAGE(1), 0x0C,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ REPORT_SIZE(1), 0x01,
+ REPORT_COUNT(1), 0x07,
+ USAGE(1), 0xB5, // Next Track
+ USAGE(1), 0xB6, // Previous Track
+ USAGE(1), 0xB7, // Stop
+ USAGE(1), 0xCD, // Play / Pause
+ USAGE(1), 0xE2, // Mute
+ USAGE(1), 0xE9, // Volume Up
+ USAGE(1), 0xEA, // Volume Down
+ INPUT(1), 0x02, // Input (Data, Variable, Absolute)
+ REPORT_COUNT(1), 0x01,
+ INPUT(1), 0x01,
+ END_COLLECTION(0),
+ };
+ reportLength = sizeof(reportDescriptor);
+ return reportDescriptor;
+ } else if (mouse_type == ABS_MOUSE) {
+ static uint8_t reportDescriptor[] = {
+
+ // Keyboard
+ USAGE_PAGE(1), 0x01,
+ USAGE(1), 0x06,
+ COLLECTION(1), 0x01,
+ REPORT_ID(1), REPORT_ID_KEYBOARD,
+ USAGE_PAGE(1), 0x07,
+ USAGE_MINIMUM(1), 0xE0,
+ USAGE_MAXIMUM(1), 0xE7,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ REPORT_SIZE(1), 0x01,
+ REPORT_COUNT(1), 0x08,
+ INPUT(1), 0x02,
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x08,
+ INPUT(1), 0x01,
+ REPORT_COUNT(1), 0x05,
+ REPORT_SIZE(1), 0x01,
+ USAGE_PAGE(1), 0x08,
+ USAGE_MINIMUM(1), 0x01,
+ USAGE_MAXIMUM(1), 0x05,
+ OUTPUT(1), 0x02,
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x03,
+ OUTPUT(1), 0x01,
+ REPORT_COUNT(1), 0x06,
+ REPORT_SIZE(1), 0x08,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(2), 0xff, 0x00,
+ USAGE_PAGE(1), 0x07,
+ USAGE_MINIMUM(1), 0x00,
+ USAGE_MAXIMUM(2), 0xff, 0x00,
+ INPUT(1), 0x00,
+ END_COLLECTION(0),
+
+ // Mouse
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x02, // Mouse
+ COLLECTION(1), 0x01, // Application
+ USAGE(1), 0x01, // Pointer
+ COLLECTION(1), 0x00, // Physical
+ REPORT_ID(1), REPORT_ID_MOUSE,
+
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x30, // X
+ USAGE(1), 0x31, // Y
+ LOGICAL_MINIMUM(1), 0x00, // 0
+ LOGICAL_MAXIMUM(2), 0xff, 0x7f, // 32767
+ REPORT_SIZE(1), 0x10,
+ REPORT_COUNT(1), 0x02,
+ INPUT(1), 0x02, // Data, Variable, Absolute
+
+ USAGE_PAGE(1), 0x01, // Generic Desktop
+ USAGE(1), 0x38, // scroll
+ LOGICAL_MINIMUM(1), 0x81, // -127
+ LOGICAL_MAXIMUM(1), 0x7f, // 127
+ REPORT_SIZE(1), 0x08,
+ REPORT_COUNT(1), 0x01,
+ INPUT(1), 0x06, // Data, Variable, Relative
+
+ USAGE_PAGE(1), 0x09, // Buttons
+ USAGE_MINIMUM(1), 0x01,
+ USAGE_MAXIMUM(1), 0x03,
+ LOGICAL_MINIMUM(1), 0x00, // 0
+ LOGICAL_MAXIMUM(1), 0x01, // 1
+ REPORT_COUNT(1), 0x03,
+ REPORT_SIZE(1), 0x01,
+ INPUT(1), 0x02, // Data, Variable, Absolute
+ REPORT_COUNT(1), 0x01,
+ REPORT_SIZE(1), 0x05,
+ INPUT(1), 0x01, // Constant
+
+ END_COLLECTION(0),
+ END_COLLECTION(0),
+
+ // Media Control
+ USAGE_PAGE(1), 0x0C,
+ USAGE(1), 0x01,
+ COLLECTION(1), 0x01,
+ REPORT_ID(1), REPORT_ID_VOLUME,
+ USAGE_PAGE(1), 0x0C,
+ LOGICAL_MINIMUM(1), 0x00,
+ LOGICAL_MAXIMUM(1), 0x01,
+ REPORT_SIZE(1), 0x01,
+ REPORT_COUNT(1), 0x07,
+ USAGE(1), 0xB5, // Next Track
+ USAGE(1), 0xB6, // Previous Track
+ USAGE(1), 0xB7, // Stop
+ USAGE(1), 0xCD, // Play / Pause
+ USAGE(1), 0xE2, // Mute
+ USAGE(1), 0xE9, // Volume Up
+ USAGE(1), 0xEA, // Volume Down
+ INPUT(1), 0x02, // Input (Data, Variable, Absolute)
+ REPORT_COUNT(1), 0x01,
+ INPUT(1), 0x01,
+ END_COLLECTION(0),
+ };
+ reportLength = sizeof(reportDescriptor);
+ return reportDescriptor;
+ }
+
+ return NULL;
+}
+
+bool USBMouseKeyboard::EPINT_OUT_callback() {
+ uint32_t bytesRead = 0;
+ uint8_t led[65];
+ USBDevice::readEP(EPINT_OUT, led, &bytesRead, MAX_HID_REPORT_SIZE);
+
+ // we take led[1] because led[0] is the report ID
+ lock_status = led[1] & 0x07;
+
+ // We activate the endpoint to be able to recceive data
+ if (!readStart(EPINT_OUT, MAX_HID_REPORT_SIZE))
+ return false;
+ return true;
+}
+
+uint8_t USBMouseKeyboard::lockStatus() {
+ return lock_status;
+}
+
+bool USBMouseKeyboard::update(int16_t x, int16_t y, uint8_t button, int8_t z) {
+ switch (mouse_type) {
+ case REL_MOUSE:
+ while (x > 127) {
+ if (!mouseSend(127, 0, button, z)) return false;
+ x = x - 127;
+ }
+ while (x < -128) {
+ if (!mouseSend(-128, 0, button, z)) return false;
+ x = x + 128;
+ }
+ while (y > 127) {
+ if (!mouseSend(0, 127, button, z)) return false;
+ y = y - 127;
+ }
+ while (y < -128) {
+ if (!mouseSend(0, -128, button, z)) return false;
+ y = y + 128;
+ }
+ return mouseSend(x, y, button, z);
+ case ABS_MOUSE:
+ HID_REPORT report;
+
+ report.data[0] = REPORT_ID_MOUSE;
+ report.data[1] = x & 0xff;
+ report.data[2] = (x >> 8) & 0xff;
+ report.data[3] = y & 0xff;
+ report.data[4] = (y >> 8) & 0xff;
+ report.data[5] = -z;
+ report.data[6] = button & 0x07;
+
+ report.length = 7;
+
+ return send(&report);
+ default:
+ return false;
+ }
+}
+
+bool USBMouseKeyboard::mouseSend(int8_t x, int8_t y, uint8_t buttons, int8_t z) {
+ HID_REPORT report;
+ report.data[0] = REPORT_ID_MOUSE;
+ report.data[1] = buttons & 0x07;
+ report.data[2] = x;
+ report.data[3] = y;
+ report.data[4] = -z; // >0 to scroll down, <0 to scroll up
+
+ report.length = 5;
+
+ return send(&report);
+}
+
+bool USBMouseKeyboard::move(int16_t x, int16_t y) {
+ return update(x, y, button, 0);
+}
+
+bool USBMouseKeyboard::scroll(int8_t z) {
+ return update(0, 0, button, z);
+}
+
+bool USBMouseKeyboard::doubleClick() {
+ if (!click(MOUSE_LEFT))
+ return false;
+ wait(0.1);
+ return click(MOUSE_LEFT);
+}
+
+bool USBMouseKeyboard::click(uint8_t button) {
+ if (!update(0, 0, button, 0))
+ return false;
+ wait(0.01);
+ return update(0, 0, 0, 0);
+}
+
+bool USBMouseKeyboard::press(uint8_t button_) {
+ button = button_ & 0x07;
+ return update(0, 0, button, 0);
+}
+
+bool USBMouseKeyboard::release(uint8_t button_) {
+ button = (button & (~button_)) & 0x07;
+ return update(0, 0, button, 0);
+}
+
+int USBMouseKeyboard::_putc(int c) {
+ return keyCode(c, keymap[c].modifier);
+}
+
+bool USBMouseKeyboard::keyCode(uint8_t key, uint8_t modifier) {
+ // Send a simulated keyboard keypress. Returns true if successful.
+
+ HID_REPORT report;
+
+ report.data[0] = REPORT_ID_KEYBOARD;
+ report.data[1] = modifier;
+ report.data[2] = 0;
+ report.data[3] = keymap[key].usage;
+ report.data[4] = 0;
+ report.data[5] = 0;
+ report.data[6] = 0;
+ report.data[7] = 0;
+ report.data[8] = 0;
+
+ report.length = 9;
+
+ if (!send(&report)) {
+ return false;
+ }
+
+ report.data[1] = 0;
+ report.data[3] = 0;
+
+ if (!send(&report)) {
+ return false;
+ }
+
+ return true;
+
+}
+
+
+bool USBMouseKeyboard::mediaControl(MEDIA_KEY key) {
+ HID_REPORT report;
+
+ report.data[0] = REPORT_ID_VOLUME;
+ report.data[1] = (1 << key) & 0x7f;
+
+ report.length = 2;
+
+ send(&report);
+
+ report.data[0] = REPORT_ID_VOLUME;
+ report.data[1] = 0;
+
+ report.length = 2;
+
+ return send(&report);
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouseKeyboard.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouseKeyboard.h
new file mode 100644
index 000000000..1b19b10db
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBHID/USBMouseKeyboard.h
@@ -0,0 +1,220 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBMOUSEKEYBOARD_H
+#define USBMOUSEKEYBOARD_H
+
+#define REPORT_ID_KEYBOARD 1
+#define REPORT_ID_MOUSE 2
+#define REPORT_ID_VOLUME 3
+
+#include "USBMouse.h"
+#include "USBKeyboard.h"
+#include "Stream.h"
+#include "USBHID.h"
+
+/**
+ * USBMouseKeyboard example
+ * @code
+ *
+ * #include "mbed.h"
+ * #include "USBMouseKeyboard.h"
+ *
+ * USBMouseKeyboard key_mouse;
+ *
+ * int main(void)
+ * {
+ * while(1)
+ * {
+ * key_mouse.move(20, 0);
+ * key_mouse.printf("Hello From MBED\r\n");
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ *
+ *
+ * @code
+ *
+ * #include "mbed.h"
+ * #include "USBMouseKeyboard.h"
+ *
+ * USBMouseKeyboard key_mouse(ABS_MOUSE);
+ *
+ * int main(void)
+ * {
+ * while(1)
+ * {
+ * key_mouse.move(X_MAX_ABS/2, Y_MAX_ABS/2);
+ * key_mouse.printf("Hello from MBED\r\n");
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ */
+class USBMouseKeyboard: public USBHID, public Stream
+{
+ public:
+
+ /**
+ * Constructor
+ *
+ * @param mouse_type Mouse type: ABS_MOUSE (absolute mouse) or REL_MOUSE (relative mouse) (default: REL_MOUSE)
+ * @param leds Leds bus: first: NUM_LOCK, second: CAPS_LOCK, third: SCROLL_LOCK
+ * @param vendor_id Your vendor_id (default: 0x1234)
+ * @param product_id Your product_id (default: 0x0001)
+ * @param product_release Your preoduct_release (default: 0x0001)
+ *
+ */
+ USBMouseKeyboard(MOUSE_TYPE mouse_type = REL_MOUSE, uint16_t vendor_id = 0x0021, uint16_t product_id = 0x0011, uint16_t product_release = 0x0001):
+ USBHID(0, 0, vendor_id, product_id, product_release, false)
+ {
+ lock_status = 0;
+ button = 0;
+ this->mouse_type = mouse_type;
+ connect();
+ };
+
+ /**
+ * Write a state of the mouse
+ *
+ * @param x x-axis position
+ * @param y y-axis position
+ * @param buttons buttons state (first bit represents MOUSE_LEFT, second bit MOUSE_RIGHT and third bit MOUSE_MIDDLE)
+ * @param z wheel state (>0 to scroll down, <0 to scroll up)
+ * @returns true if there is no error, false otherwise
+ */
+ bool update(int16_t x, int16_t y, uint8_t buttons, int8_t z);
+
+
+ /**
+ * Move the cursor to (x, y)
+ *
+ * @param x x-axis position
+ * @param y y-axis position
+ * @returns true if there is no error, false otherwise
+ */
+ bool move(int16_t x, int16_t y);
+
+ /**
+ * Press one or several buttons
+ *
+ * @param button button state (ex: press(MOUSE_LEFT))
+ * @returns true if there is no error, false otherwise
+ */
+ bool press(uint8_t button);
+
+ /**
+ * Release one or several buttons
+ *
+ * @param button button state (ex: release(MOUSE_LEFT))
+ * @returns true if there is no error, false otherwise
+ */
+ bool release(uint8_t button);
+
+ /**
+ * Double click (MOUSE_LEFT)
+ *
+ * @returns true if there is no error, false otherwise
+ */
+ bool doubleClick();
+
+ /**
+ * Click
+ *
+ * @param button state of the buttons ( ex: clic(MOUSE_LEFT))
+ * @returns true if there is no error, false otherwise
+ */
+ bool click(uint8_t button);
+
+ /**
+ * Scrolling
+ *
+ * @param z value of the wheel (>0 to go down, <0 to go up)
+ * @returns true if there is no error, false otherwise
+ */
+ bool scroll(int8_t z);
+
+ /**
+ * To send a character defined by a modifier(CTRL, SHIFT, ALT) and the key
+ *
+ * @code
+ * //To send CTRL + s (save)
+ * keyboard.keyCode('s', KEY_CTRL);
+ * @endcode
+ *
+ * @param modifier bit 0: KEY_CTRL, bit 1: KEY_SHIFT, bit 2: KEY_ALT (default: 0)
+ * @param key character to send
+ * @returns true if there is no error, false otherwise
+ */
+ bool keyCode(uint8_t key, uint8_t modifier = 0);
+
+ /**
+ * Send a character
+ *
+ * @param c character to be sent
+ * @returns true if there is no error, false otherwise
+ */
+ virtual int _putc(int c);
+
+ /**
+ * Control media keys
+ *
+ * @param key media key pressed (KEY_NEXT_TRACK, KEY_PREVIOUS_TRACK, KEY_STOP, KEY_PLAY_PAUSE, KEY_MUTE, KEY_VOLUME_UP, KEY_VOLUME_DOWN)
+ * @returns true if there is no error, false otherwise
+ */
+ bool mediaControl(MEDIA_KEY key);
+
+ /**
+ * Read status of lock keys. Useful to switch-on/off leds according to key pressed. Only the first three bits of the result is important:
+ * - First bit: NUM_LOCK
+ * - Second bit: CAPS_LOCK
+ * - Third bit: SCROLL_LOCK
+ *
+ * @returns status of lock keys
+ */
+ uint8_t lockStatus();
+
+ /*
+ * To define the report descriptor. Warning: this method has to store the length of the report descriptor in reportLength.
+ *
+ * @returns pointer to the report descriptor
+ */
+ virtual uint8_t * reportDesc();
+
+ /*
+ * Called when a data is received on the OUT endpoint. Useful to switch on LED of LOCK keys
+ *
+ * @returns if handle by subclass, return true
+ */
+ virtual bool EPINT_OUT_callback();
+
+
+ private:
+ bool mouseWrite(int8_t x, int8_t y, uint8_t buttons, int8_t z);
+ MOUSE_TYPE mouse_type;
+ uint8_t button;
+ bool mouseSend(int8_t x, int8_t y, uint8_t buttons, int8_t z);
+
+ uint8_t lock_status;
+
+ //dummy otherwise it doesn't compile (we must define all methods of an abstract class)
+ virtual int _getc() { return -1;}
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/MIDIMessage.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/MIDIMessage.h
new file mode 100644
index 000000000..9cfcf1363
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/MIDIMessage.h
@@ -0,0 +1,276 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef MIDIMESSAGE_H
+#define MIDIMESSAGE_H
+
+#include "mbed.h"
+
+#define MAX_MIDI_MESSAGE_SIZE 256 // Max message size. SysEx can be up to 65536 but 256 should be fine for most usage
+
+// MIDI Message Format
+//
+// [ msg(4) | channel(4) ] [ 0 | n(7) ] [ 0 | m(7) ]
+//
+// MIDI Data Messages (Channel Specific)
+//
+// Message msg n m
+// ---------------------------------------------
+// Note Off 0x8 Key Velocity
+// Note On 0x9 Key Velocity
+// Polyphonic Aftertouch 0xA Key Pressure
+// Control Change 0xB Controller Value
+// Program Change 0xC Program -
+// Channel Aftertouch 0xD Pressure -
+// Pitch Wheel 0xE LSB MSB
+
+#define CABLE_NUM (0<<4)
+
+/** A MIDI message container */
+class MIDIMessage {
+public:
+ MIDIMessage() : length(4) {}
+
+ MIDIMessage(uint8_t *buf) : length(4) {
+ for (int i = 0; i < 4; i++)
+ data[i] = buf[i];
+ }
+
+ // New constructor, buf is a true MIDI message (not USBMidi message) and buf_len true message length.
+ MIDIMessage(uint8_t *buf, int buf_len) {
+ length=buf_len+1;
+ // first byte keeped for retro-compatibility
+ data[0]=0;
+
+ for (int i = 0; i < buf_len; i++)
+ data[i+1] = buf[i];
+ }
+
+ // create messages
+
+ /** Create a NoteOff message
+ * @param key Key ID
+ * @param velocity Key velocity (0-127, default = 127)
+ * @param channel Key channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage NoteOff(int key, int velocity = 127, int channel = 0) {
+ MIDIMessage msg;
+ msg.data[0] = CABLE_NUM | 0x08;
+ msg.data[1] = 0x80 | (channel & 0x0F);
+ msg.data[2] = key & 0x7F;
+ msg.data[3] = velocity & 0x7F;
+ return msg;
+ }
+
+ /** Create a NoteOn message
+ * @param key Key ID
+ * @param velocity Key velocity (0-127, default = 127)
+ * @param channel Key channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage NoteOn(int key, int velocity = 127, int channel = 0) {
+ MIDIMessage msg;
+ msg.data[0] = CABLE_NUM | 0x09;
+ msg.data[1] = 0x90 | (channel & 0x0F);
+ msg.data[2] = key & 0x7F;
+ msg.data[3] = velocity & 0x7F;
+ return msg;
+ }
+
+ /** Create a PolyPhonic Aftertouch message
+ * @param key Key ID
+ * @param pressure Aftertouch pressure (0-127)
+ * @param channel Key channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage PolyphonicAftertouch(int key, int pressure, int channel = 0) {
+ MIDIMessage msg;
+ msg.data[0] = CABLE_NUM | 0x0A;
+ msg.data[1] = 0xA0 | (channel & 0x0F);
+ msg.data[2] = key & 0x7F;
+ msg.data[3] = pressure & 0x7F;
+ return msg;
+ }
+
+ /** Create a Control Change message
+ * @param control Controller ID
+ * @param value Controller value (0-127)
+ * @param channel Controller channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage ControlChange(int control, int value, int channel = 0) {
+ MIDIMessage msg;
+ msg.data[0] = CABLE_NUM | 0x0B;
+ msg.data[1] = 0xB0 | (channel & 0x0F);
+ msg.data[2] = control & 0x7F;
+ msg.data[3] = value & 0x7F;
+ return msg;
+ }
+
+ /** Create a Program Change message
+ * @param program Program ID
+ * @param channel Channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage ProgramChange(int program, int channel = 0) {
+ MIDIMessage msg;
+ msg.data[0] = CABLE_NUM | 0x0C;
+ msg.data[1] = 0xC0 | (channel & 0x0F);
+ msg.data[2] = program & 0x7F;
+ msg.data[3] = 0x00;
+ return msg;
+ }
+
+ /** Create a Channel Aftertouch message
+ * @param pressure Pressure
+ * @param channel Key channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage ChannelAftertouch(int pressure, int channel = 0) {
+ MIDIMessage msg;
+ msg.data[0] = CABLE_NUM | 0x0D;
+ msg.data[1] = 0xD0 | (channel & 0x0F);
+ msg.data[2] = pressure & 0x7F;
+ msg.data[3] = 0x00;
+ return msg;
+ }
+
+ /** Create a Pitch Wheel message
+ * @param pitch Pitch (-8192 - 8191, default = 0)
+ * @param channel Channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage PitchWheel(int pitch = 0, int channel = 0) {
+ MIDIMessage msg;
+ int p = pitch + 8192; // 0 - 16383, 8192 is center
+ msg.data[0] = CABLE_NUM | 0x0E;
+ msg.data[1] = 0xE0 | (channel & 0x0F);
+ msg.data[2] = p & 0x7F;
+ msg.data[3] = (p >> 7) & 0x7F;
+ return msg;
+ }
+
+ /** Create an All Notes Off message
+ * @param channel Channel (0-15, default 0)
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage AllNotesOff(int channel = 0) {
+ return ControlChange(123, 0, channel);
+ }
+
+ /** Create a SysEx message
+ * @param data SysEx data (including 0xF0 .. 0xF7)
+ * @param len SysEx data length
+ * @returns A MIDIMessage
+ */
+ static MIDIMessage SysEx(uint8_t *data, int len) {
+ MIDIMessage msg=MIDIMessage(data,len);
+ return msg;
+ }
+
+ // decode messages
+
+ /** MIDI Message Types */
+ enum MIDIMessageType {
+ ErrorType,
+ NoteOffType,
+ NoteOnType,
+ PolyphonicAftertouchType,
+ ControlChangeType,
+ ProgramChangeType,
+ ChannelAftertouchType,
+ PitchWheelType,
+ AllNotesOffType,
+ SysExType
+ };
+
+ /** Read the message type
+ * @returns MIDIMessageType
+ */
+ MIDIMessageType type() {
+ switch((data[1] >> 4) & 0xF) {
+ case 0x8: return NoteOffType;
+ case 0x9: return NoteOnType;
+ case 0xA: return PolyphonicAftertouchType;
+ case 0xB:
+ if(controller() < 120) { // standard controllers
+ return ControlChangeType;
+ } else if(controller() == 123) {
+ return AllNotesOffType;
+ } else {
+ return ErrorType; // unsupported atm
+ }
+ case 0xC: return ProgramChangeType;
+ case 0xD: return ChannelAftertouchType;
+ case 0xE: return PitchWheelType;
+ case 0xF: return SysExType;
+ default: return ErrorType;
+ }
+ }
+
+ /** Read the channel number */
+ int channel() {
+ return (data[1] & 0x0F);
+ }
+
+ /** Read the key ID */
+ int key() {
+ return (data[2] & 0x7F);
+ }
+
+ /** Read the velocity */
+ int velocity() {
+ return (data[3] & 0x7F);
+ }
+
+ /** Read the controller value */
+ int value() {
+ return (data[3] & 0x7F);
+ }
+
+ /** Read the aftertouch pressure */
+ int pressure() {
+ if(type() == PolyphonicAftertouchType) {
+ return (data[3] & 0x7F);
+ } else {
+ return (data[2] & 0x7F);
+ }
+ }
+
+ /** Read the controller number */
+ int controller() {
+ return (data[2] & 0x7F);
+ }
+
+ /** Read the program number */
+ int program() {
+ return (data[2] & 0x7F);
+ }
+
+ /** Read the pitch value */
+ int pitch() {
+ int p = ((data[3] & 0x7F) << 7) | (data[2] & 0x7F);
+ return p - 8192; // 0 - 16383, 8192 is center
+ }
+
+ uint8_t data[MAX_MIDI_MESSAGE_SIZE+1];
+ uint8_t length;
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/USBMIDI.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/USBMIDI.cpp
new file mode 100644
index 000000000..084574a79
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/USBMIDI.cpp
@@ -0,0 +1,207 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBMIDI.h"
+
+
+USBMIDI::USBMIDI(uint16_t vendor_id, uint16_t product_id, uint16_t product_release)
+ : USBDevice(vendor_id, product_id, product_release), cur_data(0), data_end(true)
+{
+ midi_evt = NULL;
+ USBDevice::connect();
+}
+
+// write plain MIDIMessage that will be converted to USBMidi event packet
+void USBMIDI::write(MIDIMessage m) {
+ // first byte keeped for retro-compatibility
+ for(int p=1; p < m.length; p+=3) {
+ uint8_t buf[4];
+ // Midi message to USBMidi event packet
+ buf[0]=m.data[1] >> 4;
+ // SysEx
+ if(buf[0] == 0xF) {
+ if((m.length - p) > 3) {
+ // SysEx start or continue
+ buf[0]=0x4;
+ } else {
+ switch(m.length - p) {
+ case 1:
+ // SysEx end with one byte
+ buf[0]=0x5;
+ break;
+ case 2:
+ // SysEx end with two bytes
+ buf[0]=0x6;
+ break;
+ case 3:
+ // SysEx end with three bytes
+ buf[0]=0x7;
+ break;
+ }
+ }
+ }
+ buf[1]=m.data[p];
+
+ if(p+1 < m.length)
+ buf[2]=m.data[p+1];
+ else
+ buf[2]=0;
+
+ if(p+2 < m.length)
+ buf[3]=m.data[p+2];
+ else
+ buf[3]=0;
+
+ USBDevice::write(EPBULK_IN, buf, 4, MAX_PACKET_SIZE_EPBULK);
+ }
+}
+
+
+void USBMIDI::attach(void (*fptr)(MIDIMessage)) {
+ midi_evt = fptr;
+}
+
+bool USBMIDI::EPBULK_OUT_callback() {
+ uint8_t buf[64];
+ uint32_t len;
+ readEP(EPBULK_OUT, buf, &len, 64);
+
+ if (midi_evt != NULL) {
+ for (uint32_t i=0; i<len; i+=4) {
+ uint8_t data_read;
+ data_end=true;
+ switch(buf[i]) {
+ case 0x2:
+ // Two-bytes System Common Message - undefined in USBMidi 1.0
+ data_read=2;
+ break;
+ case 0x4:
+ // SysEx start or continue
+ data_end=false;
+ data_read=3;
+ break;
+ case 0x5:
+ // Single-byte System Common Message or SysEx end with one byte
+ data_read=1;
+ break;
+ case 0x6:
+ // SysEx end with two bytes
+ data_read=2;
+ break;
+ case 0xC:
+ // Program change
+ data_read=2;
+ break;
+ case 0xD:
+ // Channel pressure
+ data_read=2;
+ break;
+ case 0xF:
+ // Single byte
+ data_read=1;
+ break;
+ default:
+ // Others three-bytes messages
+ data_read=3;
+ break;
+ }
+
+ for(uint8_t j=1;j<data_read+1;j++) {
+ data[cur_data]=buf[i+j];
+ cur_data++;
+ }
+
+ if(data_end) {
+ midi_evt(MIDIMessage(data,cur_data));
+ cur_data=0;
+ }
+ }
+ }
+
+ // We reactivate the endpoint to receive next characters
+ readStart(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+ return true;
+}
+
+// Called in ISR context
+// Set configuration. Return false if the
+// configuration is not supported.
+bool USBMIDI::USBCallback_setConfiguration(uint8_t configuration) {
+ if (configuration != DEFAULT_CONFIGURATION) {
+ return false;
+ }
+
+ // Configure endpoints > 0
+ addEndpoint(EPBULK_IN, MAX_PACKET_SIZE_EPBULK);
+ addEndpoint(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+
+ // We activate the endpoint to be able to receive data
+ readStart(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+ return true;
+}
+
+
+uint8_t * USBMIDI::stringIinterfaceDesc() {
+ static uint8_t stringIinterfaceDescriptor[] = {
+ 0x0c, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'A',0,'u',0,'d',0,'i',0,'o',0 //bString iInterface - Audio
+ };
+ return stringIinterfaceDescriptor;
+}
+
+uint8_t * USBMIDI::stringIproductDesc() {
+ static uint8_t stringIproductDescriptor[] = {
+ 0x16, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'M',0,'b',0,'e',0,'d',0,' ',0,'A',0,'u',0,'d',0,'i',0,'o',0 //bString iProduct - Mbed Audio
+ };
+ return stringIproductDescriptor;
+}
+
+
+uint8_t * USBMIDI::configurationDesc() {
+ static uint8_t configDescriptor[] = {
+ // configuration descriptor
+ 0x09, 0x02, 0x65, 0x00, 0x02, 0x01, 0x00, 0xc0, 0x50,
+
+ // The Audio Interface Collection
+ 0x09, 0x04, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x00, // Standard AC Interface Descriptor
+ 0x09, 0x24, 0x01, 0x00, 0x01, 0x09, 0x00, 0x01, 0x01, // Class-specific AC Interface Descriptor
+ 0x09, 0x04, 0x01, 0x00, 0x02, 0x01, 0x03, 0x00, 0x00, // MIDIStreaming Interface Descriptors
+ 0x07, 0x24, 0x01, 0x00, 0x01, 0x41, 0x00, // Class-Specific MS Interface Header Descriptor
+
+ // MIDI IN JACKS
+ 0x06, 0x24, 0x02, 0x01, 0x01, 0x00,
+ 0x06, 0x24, 0x02, 0x02, 0x02, 0x00,
+
+ // MIDI OUT JACKS
+ 0x09, 0x24, 0x03, 0x01, 0x03, 0x01, 0x02, 0x01, 0x00,
+ 0x09, 0x24, 0x03, 0x02, 0x06, 0x01, 0x01, 0x01, 0x00,
+
+ // OUT endpoint descriptor
+ 0x09, 0x05, 0x02, 0x02, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x25, 0x01, 0x01, 0x01,
+
+ // IN endpoint descriptor
+ 0x09, 0x05, 0x82, 0x02, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0x05, 0x25, 0x01, 0x01, 0x03,
+ };
+ return configDescriptor;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/USBMIDI.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/USBMIDI.h
new file mode 100644
index 000000000..cc5be5b7d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMIDI/USBMIDI.h
@@ -0,0 +1,112 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBMIDI_H
+#define USBMIDI_H
+
+/* These headers are included for child class. */
+#include "USBEndpoints.h"
+#include "USBDescriptor.h"
+#include "USBDevice_Types.h"
+
+#include "USBDevice.h"
+#include "MIDIMessage.h"
+
+#define DEFAULT_CONFIGURATION (1)
+
+/**
+* USBMIDI example
+*
+* @code
+* #include "mbed.h"
+* #include "USBMIDI.h"
+*
+* USBMIDI midi;
+*
+* int main() {
+* while (1) {
+* for(int i=48; i<83; i++) { // send some messages!
+* midi.write(MIDIMessage::NoteOn(i));
+* wait(0.25);
+* midi.write(MIDIMessage::NoteOff(i));
+* wait(0.5);
+* }
+* }
+* }
+* @endcode
+*/
+class USBMIDI: public USBDevice {
+public:
+
+ /**
+ * Constructor
+ *
+ * @param vendor_id Your vendor_id
+ * @param product_id Your product_id
+ * @param product_release Your preoduct_release
+ */
+ USBMIDI(uint16_t vendor_id = 0x0700, uint16_t product_id = 0x0101, uint16_t product_release = 0x0001);
+
+ /**
+ * Send a MIDIMessage
+ *
+ * @param m The MIDIMessage to send
+ */
+ void write(MIDIMessage m);
+
+ /**
+ * Attach a callback for when a MIDIEvent is received
+ *
+ * @param fptr function pointer
+ */
+ void attach(void (*fptr)(MIDIMessage));
+
+
+protected:
+ virtual bool EPBULK_OUT_callback();
+ virtual bool USBCallback_setConfiguration(uint8_t configuration);
+ /*
+ * Get string product descriptor
+ *
+ * @returns pointer to the string product descriptor
+ */
+ virtual uint8_t * stringIproductDesc();
+
+ /*
+ * Get string interface descriptor
+ *
+ * @returns pointer to the string interface descriptor
+ */
+ virtual uint8_t * stringIinterfaceDesc();
+
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc();
+
+private:
+ uint8_t data[MAX_MIDI_MESSAGE_SIZE+1];
+ uint8_t cur_data;
+ bool data_end;
+
+ void (*midi_evt)(MIDIMessage);
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMSD/USBMSD.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMSD/USBMSD.cpp
new file mode 100644
index 000000000..ee5ad2473
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMSD/USBMSD.cpp
@@ -0,0 +1,655 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBMSD.h"
+
+#define DISK_OK 0x00
+#define NO_INIT 0x01
+#define NO_DISK 0x02
+#define WRITE_PROTECT 0x04
+
+#define CBW_Signature 0x43425355
+#define CSW_Signature 0x53425355
+
+// SCSI Commands
+#define TEST_UNIT_READY 0x00
+#define REQUEST_SENSE 0x03
+#define FORMAT_UNIT 0x04
+#define INQUIRY 0x12
+#define MODE_SELECT6 0x15
+#define MODE_SENSE6 0x1A
+#define START_STOP_UNIT 0x1B
+#define MEDIA_REMOVAL 0x1E
+#define READ_FORMAT_CAPACITIES 0x23
+#define READ_CAPACITY 0x25
+#define READ10 0x28
+#define WRITE10 0x2A
+#define VERIFY10 0x2F
+#define READ12 0xA8
+#define WRITE12 0xAA
+#define MODE_SELECT10 0x55
+#define MODE_SENSE10 0x5A
+
+// MSC class specific requests
+#define MSC_REQUEST_RESET 0xFF
+#define MSC_REQUEST_GET_MAX_LUN 0xFE
+
+#define DEFAULT_CONFIGURATION (1)
+
+// max packet size
+#define MAX_PACKET MAX_PACKET_SIZE_EPBULK
+
+// CSW Status
+enum Status {
+ CSW_PASSED,
+ CSW_FAILED,
+ CSW_ERROR,
+};
+
+
+USBMSD::USBMSD(uint16_t vendor_id, uint16_t product_id, uint16_t product_release): USBDevice(vendor_id, product_id, product_release) {
+ stage = READ_CBW;
+ memset((void *)&cbw, 0, sizeof(CBW));
+ memset((void *)&csw, 0, sizeof(CSW));
+ page = NULL;
+}
+
+USBMSD::~USBMSD() {
+ disconnect();
+}
+
+
+// Called in ISR context to process a class specific request
+bool USBMSD::USBCallback_request(void) {
+
+ bool success = false;
+ CONTROL_TRANSFER * transfer = getTransferPtr();
+ static uint8_t maxLUN[1] = {0};
+
+ if (transfer->setup.bmRequestType.Type == CLASS_TYPE) {
+ switch (transfer->setup.bRequest) {
+ case MSC_REQUEST_RESET:
+ reset();
+ success = true;
+ break;
+ case MSC_REQUEST_GET_MAX_LUN:
+ transfer->remaining = 1;
+ transfer->ptr = maxLUN;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ default:
+ break;
+ }
+ }
+
+ return success;
+}
+
+
+bool USBMSD::connect(bool blocking) {
+ //disk initialization
+ if (disk_status() & NO_INIT) {
+ if (disk_initialize()) {
+ return false;
+ }
+ }
+
+ // get number of blocks
+ BlockCount = disk_sectors();
+
+ // get memory size
+ MemorySize = disk_size();
+
+ if (BlockCount > 0) {
+ BlockSize = MemorySize / BlockCount;
+ if (BlockSize != 0) {
+ free(page);
+ page = (uint8_t *)malloc(BlockSize * sizeof(uint8_t));
+ if (page == NULL)
+ return false;
+ }
+ } else {
+ return false;
+ }
+
+ //connect the device
+ USBDevice::connect(blocking);
+ return true;
+}
+
+void USBMSD::disconnect() {
+ USBDevice::disconnect();
+ //De-allocate MSD page size:
+ free(page);
+ page = NULL;
+}
+
+void USBMSD::reset() {
+ stage = READ_CBW;
+}
+
+
+// Called in ISR context called when a data is received
+bool USBMSD::EPBULK_OUT_callback() {
+ uint32_t size = 0;
+ uint8_t buf[MAX_PACKET_SIZE_EPBULK];
+ readEP(EPBULK_OUT, buf, &size, MAX_PACKET_SIZE_EPBULK);
+ switch (stage) {
+ // the device has to decode the CBW received
+ case READ_CBW:
+ CBWDecode(buf, size);
+ break;
+
+ // the device has to receive data from the host
+ case PROCESS_CBW:
+ switch (cbw.CB[0]) {
+ case WRITE10:
+ case WRITE12:
+ memoryWrite(buf, size);
+ break;
+ case VERIFY10:
+ memoryVerify(buf, size);
+ break;
+ }
+ break;
+
+ // an error has occured: stall endpoint and send CSW
+ default:
+ stallEndpoint(EPBULK_OUT);
+ csw.Status = CSW_ERROR;
+ sendCSW();
+ break;
+ }
+
+ //reactivate readings on the OUT bulk endpoint
+ readStart(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+ return true;
+}
+
+// Called in ISR context when a data has been transferred
+bool USBMSD::EPBULK_IN_callback() {
+ switch (stage) {
+
+ // the device has to send data to the host
+ case PROCESS_CBW:
+ switch (cbw.CB[0]) {
+ case READ10:
+ case READ12:
+ memoryRead();
+ break;
+ }
+ break;
+
+ //the device has to send a CSW
+ case SEND_CSW:
+ sendCSW();
+ break;
+
+ // the host has received the CSW -> we wait a CBW
+ case WAIT_CSW:
+ stage = READ_CBW;
+ break;
+
+ // an error has occured
+ default:
+ stallEndpoint(EPBULK_IN);
+ sendCSW();
+ break;
+ }
+ return true;
+}
+
+
+void USBMSD::memoryWrite (uint8_t * buf, uint16_t size) {
+
+ if ((addr + size) > MemorySize) {
+ size = MemorySize - addr;
+ stage = ERROR;
+ stallEndpoint(EPBULK_OUT);
+ }
+
+ // we fill an array in RAM of 1 block before writing it in memory
+ for (int i = 0; i < size; i++)
+ page[addr%BlockSize + i] = buf[i];
+
+ // if the array is filled, write it in memory
+ if (!((addr + size)%BlockSize)) {
+ if (!(disk_status() & WRITE_PROTECT)) {
+ disk_write(page, addr/BlockSize, 1);
+ }
+ }
+
+ addr += size;
+ length -= size;
+ csw.DataResidue -= size;
+
+ if ((!length) || (stage != PROCESS_CBW)) {
+ csw.Status = (stage == ERROR) ? CSW_FAILED : CSW_PASSED;
+ sendCSW();
+ }
+}
+
+void USBMSD::memoryVerify (uint8_t * buf, uint16_t size) {
+ uint32_t n;
+
+ if ((addr + size) > MemorySize) {
+ size = MemorySize - addr;
+ stage = ERROR;
+ stallEndpoint(EPBULK_OUT);
+ }
+
+ // beginning of a new block -> load a whole block in RAM
+ if (!(addr%BlockSize))
+ disk_read(page, addr/BlockSize, 1);
+
+ // info are in RAM -> no need to re-read memory
+ for (n = 0; n < size; n++) {
+ if (page[addr%BlockSize + n] != buf[n]) {
+ memOK = false;
+ break;
+ }
+ }
+
+ addr += size;
+ length -= size;
+ csw.DataResidue -= size;
+
+ if ( !length || (stage != PROCESS_CBW)) {
+ csw.Status = (memOK && (stage == PROCESS_CBW)) ? CSW_PASSED : CSW_FAILED;
+ sendCSW();
+ }
+}
+
+
+bool USBMSD::inquiryRequest (void) {
+ uint8_t inquiry[] = { 0x00, 0x80, 0x00, 0x01,
+ 36 - 4, 0x80, 0x00, 0x00,
+ 'M', 'B', 'E', 'D', '.', 'O', 'R', 'G',
+ 'M', 'B', 'E', 'D', ' ', 'U', 'S', 'B', ' ', 'D', 'I', 'S', 'K', ' ', ' ', ' ',
+ '1', '.', '0', ' ',
+ };
+ if (!write(inquiry, sizeof(inquiry))) {
+ return false;
+ }
+ return true;
+}
+
+
+bool USBMSD::readFormatCapacity() {
+ uint8_t capacity[] = { 0x00, 0x00, 0x00, 0x08,
+ (uint8_t)((BlockCount >> 24) & 0xff),
+ (uint8_t)((BlockCount >> 16) & 0xff),
+ (uint8_t)((BlockCount >> 8) & 0xff),
+ (uint8_t)((BlockCount >> 0) & 0xff),
+
+ 0x02,
+ (uint8_t)((BlockSize >> 16) & 0xff),
+ (uint8_t)((BlockSize >> 8) & 0xff),
+ (uint8_t)((BlockSize >> 0) & 0xff),
+ };
+ if (!write(capacity, sizeof(capacity))) {
+ return false;
+ }
+ return true;
+}
+
+
+bool USBMSD::readCapacity (void) {
+ uint8_t capacity[] = {
+ (uint8_t)(((BlockCount - 1) >> 24) & 0xff),
+ (uint8_t)(((BlockCount - 1) >> 16) & 0xff),
+ (uint8_t)(((BlockCount - 1) >> 8) & 0xff),
+ (uint8_t)(((BlockCount - 1) >> 0) & 0xff),
+
+ (uint8_t)((BlockSize >> 24) & 0xff),
+ (uint8_t)((BlockSize >> 16) & 0xff),
+ (uint8_t)((BlockSize >> 8) & 0xff),
+ (uint8_t)((BlockSize >> 0) & 0xff),
+ };
+ if (!write(capacity, sizeof(capacity))) {
+ return false;
+ }
+ return true;
+}
+
+bool USBMSD::write (uint8_t * buf, uint16_t size) {
+
+ if (size >= cbw.DataLength) {
+ size = cbw.DataLength;
+ }
+ stage = SEND_CSW;
+
+ if (!writeNB(EPBULK_IN, buf, size, MAX_PACKET_SIZE_EPBULK)) {
+ return false;
+ }
+
+ csw.DataResidue -= size;
+ csw.Status = CSW_PASSED;
+ return true;
+}
+
+
+bool USBMSD::modeSense6 (void) {
+ uint8_t sense6[] = { 0x03, 0x00, 0x00, 0x00 };
+ if (!write(sense6, sizeof(sense6))) {
+ return false;
+ }
+ return true;
+}
+
+void USBMSD::sendCSW() {
+ csw.Signature = CSW_Signature;
+ writeNB(EPBULK_IN, (uint8_t *)&csw, sizeof(CSW), MAX_PACKET_SIZE_EPBULK);
+ stage = WAIT_CSW;
+}
+
+bool USBMSD::requestSense (void) {
+ uint8_t request_sense[] = {
+ 0x70,
+ 0x00,
+ 0x05, // Sense Key: illegal request
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x0A,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x30,
+ 0x01,
+ 0x00,
+ 0x00,
+ 0x00,
+ 0x00,
+ };
+
+ if (!write(request_sense, sizeof(request_sense))) {
+ return false;
+ }
+
+ return true;
+}
+
+void USBMSD::fail() {
+ csw.Status = CSW_FAILED;
+ sendCSW();
+}
+
+
+void USBMSD::CBWDecode(uint8_t * buf, uint16_t size) {
+ if (size == sizeof(cbw)) {
+ memcpy((uint8_t *)&cbw, buf, size);
+ if (cbw.Signature == CBW_Signature) {
+ csw.Tag = cbw.Tag;
+ csw.DataResidue = cbw.DataLength;
+ if ((cbw.CBLength < 1) || (cbw.CBLength > 16) ) {
+ fail();
+ } else {
+ switch (cbw.CB[0]) {
+ case TEST_UNIT_READY:
+ testUnitReady();
+ break;
+ case REQUEST_SENSE:
+ requestSense();
+ break;
+ case INQUIRY:
+ inquiryRequest();
+ break;
+ case MODE_SENSE6:
+ modeSense6();
+ break;
+ case READ_FORMAT_CAPACITIES:
+ readFormatCapacity();
+ break;
+ case READ_CAPACITY:
+ readCapacity();
+ break;
+ case READ10:
+ case READ12:
+ if (infoTransfer()) {
+ if ((cbw.Flags & 0x80)) {
+ stage = PROCESS_CBW;
+ memoryRead();
+ } else {
+ stallEndpoint(EPBULK_OUT);
+ csw.Status = CSW_ERROR;
+ sendCSW();
+ }
+ }
+ break;
+ case WRITE10:
+ case WRITE12:
+ if (infoTransfer()) {
+ if (!(cbw.Flags & 0x80)) {
+ stage = PROCESS_CBW;
+ } else {
+ stallEndpoint(EPBULK_IN);
+ csw.Status = CSW_ERROR;
+ sendCSW();
+ }
+ }
+ break;
+ case VERIFY10:
+ if (!(cbw.CB[1] & 0x02)) {
+ csw.Status = CSW_PASSED;
+ sendCSW();
+ break;
+ }
+ if (infoTransfer()) {
+ if (!(cbw.Flags & 0x80)) {
+ stage = PROCESS_CBW;
+ memOK = true;
+ } else {
+ stallEndpoint(EPBULK_IN);
+ csw.Status = CSW_ERROR;
+ sendCSW();
+ }
+ }
+ break;
+ case MEDIA_REMOVAL:
+ csw.Status = CSW_PASSED;
+ sendCSW();
+ break;
+ default:
+ fail();
+ break;
+ }
+ }
+ }
+ }
+}
+
+void USBMSD::testUnitReady (void) {
+
+ if (cbw.DataLength != 0) {
+ if ((cbw.Flags & 0x80) != 0) {
+ stallEndpoint(EPBULK_IN);
+ } else {
+ stallEndpoint(EPBULK_OUT);
+ }
+ }
+
+ csw.Status = CSW_PASSED;
+ sendCSW();
+}
+
+
+void USBMSD::memoryRead (void) {
+ uint32_t n;
+
+ n = (length > MAX_PACKET) ? MAX_PACKET : length;
+
+ if ((addr + n) > MemorySize) {
+ n = MemorySize - addr;
+ stage = ERROR;
+ }
+
+ // we read an entire block
+ if (!(addr%BlockSize))
+ disk_read(page, addr/BlockSize, 1);
+
+ // write data which are in RAM
+ writeNB(EPBULK_IN, &page[addr%BlockSize], n, MAX_PACKET_SIZE_EPBULK);
+
+ addr += n;
+ length -= n;
+
+ csw.DataResidue -= n;
+
+ if ( !length || (stage != PROCESS_CBW)) {
+ csw.Status = (stage == PROCESS_CBW) ? CSW_PASSED : CSW_FAILED;
+ stage = (stage == PROCESS_CBW) ? SEND_CSW : stage;
+ }
+}
+
+
+bool USBMSD::infoTransfer (void) {
+ uint32_t n;
+
+ // Logical Block Address of First Block
+ n = (cbw.CB[2] << 24) | (cbw.CB[3] << 16) | (cbw.CB[4] << 8) | (cbw.CB[5] << 0);
+
+ addr = n * BlockSize;
+
+ // Number of Blocks to transfer
+ switch (cbw.CB[0]) {
+ case READ10:
+ case WRITE10:
+ case VERIFY10:
+ n = (cbw.CB[7] << 8) | (cbw.CB[8] << 0);
+ break;
+
+ case READ12:
+ case WRITE12:
+ n = (cbw.CB[6] << 24) | (cbw.CB[7] << 16) | (cbw.CB[8] << 8) | (cbw.CB[9] << 0);
+ break;
+ }
+
+ length = n * BlockSize;
+
+ if (!cbw.DataLength) { // host requests no data
+ csw.Status = CSW_FAILED;
+ sendCSW();
+ return false;
+ }
+
+ if (cbw.DataLength != length) {
+ if ((cbw.Flags & 0x80) != 0) {
+ stallEndpoint(EPBULK_IN);
+ } else {
+ stallEndpoint(EPBULK_OUT);
+ }
+
+ csw.Status = CSW_FAILED;
+ sendCSW();
+ return false;
+ }
+
+ return true;
+}
+
+
+
+
+
+// Called in ISR context
+// Set configuration. Return false if the
+// configuration is not supported.
+bool USBMSD::USBCallback_setConfiguration(uint8_t configuration) {
+ if (configuration != DEFAULT_CONFIGURATION) {
+ return false;
+ }
+
+ // Configure endpoints > 0
+ addEndpoint(EPBULK_IN, MAX_PACKET_SIZE_EPBULK);
+ addEndpoint(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+
+ //activate readings
+ readStart(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+ return true;
+}
+
+
+uint8_t * USBMSD::stringIinterfaceDesc() {
+ static uint8_t stringIinterfaceDescriptor[] = {
+ 0x08, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'M',0,'S',0,'D',0 //bString iInterface - MSD
+ };
+ return stringIinterfaceDescriptor;
+}
+
+uint8_t * USBMSD::stringIproductDesc() {
+ static uint8_t stringIproductDescriptor[] = {
+ 0x12, //bLength
+ STRING_DESCRIPTOR, //bDescriptorType 0x03
+ 'M',0,'b',0,'e',0,'d',0,' ',0,'M',0,'S',0,'D',0 //bString iProduct - Mbed Audio
+ };
+ return stringIproductDescriptor;
+}
+
+
+uint8_t * USBMSD::configurationDesc() {
+ static uint8_t configDescriptor[] = {
+
+ // Configuration 1
+ 9, // bLength
+ 2, // bDescriptorType
+ LSB(9 + 9 + 7 + 7), // wTotalLength
+ MSB(9 + 9 + 7 + 7),
+ 0x01, // bNumInterfaces
+ 0x01, // bConfigurationValue: 0x01 is used to select this configuration
+ 0x00, // iConfiguration: no string to describe this configuration
+ 0xC0, // bmAttributes
+ 100, // bMaxPower, device power consumption is 100 mA
+
+ // Interface 0, Alternate Setting 0, MSC Class
+ 9, // bLength
+ 4, // bDescriptorType
+ 0x00, // bInterfaceNumber
+ 0x00, // bAlternateSetting
+ 0x02, // bNumEndpoints
+ 0x08, // bInterfaceClass
+ 0x06, // bInterfaceSubClass
+ 0x50, // bInterfaceProtocol
+ 0x04, // iInterface
+
+ // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+ 7, // bLength
+ 5, // bDescriptorType
+ PHY_TO_DESC(EPBULK_IN), // bEndpointAddress
+ 0x02, // bmAttributes (0x02=bulk)
+ LSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (MSB)
+ 0, // bInterval
+
+ // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+ 7, // bLength
+ 5, // bDescriptorType
+ PHY_TO_DESC(EPBULK_OUT), // bEndpointAddress
+ 0x02, // bmAttributes (0x02=bulk)
+ LSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (MSB)
+ 0 // bInterval
+ };
+ return configDescriptor;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMSD/USBMSD.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMSD/USBMSD.h
new file mode 100644
index 000000000..ff750026c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBMSD/USBMSD.h
@@ -0,0 +1,251 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#ifndef USBMSD_H
+#define USBMSD_H
+
+/* These headers are included for child class. */
+#include "USBEndpoints.h"
+#include "USBDescriptor.h"
+#include "USBDevice_Types.h"
+
+#include "USBDevice.h"
+
+/**
+ * USBMSD class: generic class in order to use all kinds of blocks storage chip
+ *
+ * Introduction
+ *
+ * The USBMSD implements the MSD protocol. It permits to access a memory chip (flash, sdcard,...)
+ * from a computer over USB. But this class doesn't work standalone, you need to subclass this class
+ * and define virtual functions which are called in USBMSD.
+ *
+ * How to use this class with your chip ?
+ *
+ * You have to inherit and define some pure virtual functions (mandatory step):
+ * - virtual int disk_read(char * data, int block): function to read a block
+ * - virtual int disk_write(const char * data, int block): function to write a block
+ * - virtual int disk_initialize(): function to initialize the memory
+ * - virtual int disk_sectors(): return the number of blocks
+ * - virtual int disk_size(): return the memory size
+ * - virtual int disk_status(): return the status of the storage chip (0: OK, 1: not initialized, 2: no medium in the drive, 4: write protection)
+ *
+ * All functions names are compatible with the fat filesystem library. So you can imagine using your own class with
+ * USBMSD and the fat filesystem library in the same program. Just be careful because there are two different parts which
+ * will access the sd card. You can do a master/slave system using the disk_status method.
+ *
+ * Once these functions defined, you can call connect() (at the end of the constructor of your class for instance)
+ * of USBMSD to connect your mass storage device. connect() will first call disk_status() to test the status of the disk.
+ * If disk_status() returns 1 (disk not initialized), then disk_initialize() is called. After this step, connect() will collect information
+ * such as the number of blocks and the memory size.
+ */
+class USBMSD: public USBDevice {
+public:
+
+ /**
+ * Constructor
+ *
+ * @param vendor_id Your vendor_id
+ * @param product_id Your product_id
+ * @param product_release Your preoduct_release
+ */
+ USBMSD(uint16_t vendor_id = 0x0703, uint16_t product_id = 0x0104, uint16_t product_release = 0x0001);
+
+ /**
+ * Connect the USB MSD device. Establish disk initialization before really connect the device.
+ *
+ * @param blocking if not configured
+ * @returns true if successful
+ */
+ bool connect(bool blocking = true);
+
+ /**
+ * Disconnect the USB MSD device.
+ */
+ void disconnect();
+
+ /**
+ * Destructor
+ */
+ ~USBMSD();
+
+protected:
+
+ /*
+ * read one or more blocks on a storage chip
+ *
+ * @param data pointer where will be stored read data
+ * @param block starting block number
+ * @param count number of blocks to read
+ * @returns 0 if successful
+ */
+ virtual int disk_read(uint8_t* data, uint64_t block, uint8_t count) = 0;
+
+ /*
+ * write one or more blocks on a storage chip
+ *
+ * @param data data to write
+ * @param block starting block number
+ * @param count number of blocks to write
+ * @returns 0 if successful
+ */
+ virtual int disk_write(const uint8_t* data, uint64_t block, uint8_t count) = 0;
+
+ /*
+ * Disk initilization
+ */
+ virtual int disk_initialize() = 0;
+
+ /*
+ * Return the number of blocks
+ *
+ * @returns number of blocks
+ */
+ virtual uint64_t disk_sectors() = 0;
+
+ /*
+ * Return memory size
+ *
+ * @returns memory size
+ */
+ virtual uint64_t disk_size() = 0;
+
+
+ /*
+ * To check the status of the storage chip
+ *
+ * @returns status: 0: OK, 1: disk not initialized, 2: no medium in the drive, 4: write protected
+ */
+ virtual int disk_status() = 0;
+
+ /*
+ * Get string product descriptor
+ *
+ * @returns pointer to the string product descriptor
+ */
+ virtual uint8_t * stringIproductDesc();
+
+ /*
+ * Get string interface descriptor
+ *
+ * @returns pointer to the string interface descriptor
+ */
+ virtual uint8_t * stringIinterfaceDesc();
+
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc();
+
+ /*
+ * Callback called when a packet is received
+ */
+ virtual bool EPBULK_OUT_callback();
+
+ /*
+ * Callback called when a packet has been sent
+ */
+ virtual bool EPBULK_IN_callback();
+
+ /*
+ * Set configuration of device. Add endpoints
+ */
+ virtual bool USBCallback_setConfiguration(uint8_t configuration);
+
+ /*
+ * Callback called to process class specific requests
+ */
+ virtual bool USBCallback_request();
+
+
+private:
+
+ // MSC Bulk-only Stage
+ enum Stage {
+ READ_CBW, // wait a CBW
+ ERROR, // error
+ PROCESS_CBW, // process a CBW request
+ SEND_CSW, // send a CSW
+ WAIT_CSW, // wait that a CSW has been effectively sent
+ };
+
+ // Bulk-only CBW
+ typedef struct {
+ uint32_t Signature;
+ uint32_t Tag;
+ uint32_t DataLength;
+ uint8_t Flags;
+ uint8_t LUN;
+ uint8_t CBLength;
+ uint8_t CB[16];
+ } PACKED CBW;
+
+ // Bulk-only CSW
+ typedef struct {
+ uint32_t Signature;
+ uint32_t Tag;
+ uint32_t DataResidue;
+ uint8_t Status;
+ } PACKED CSW;
+
+ //state of the bulk-only state machine
+ Stage stage;
+
+ // current CBW
+ CBW cbw;
+
+ // CSW which will be sent
+ CSW csw;
+
+ // addr where will be read or written data
+ uint32_t addr;
+
+ // length of a reading or writing
+ uint32_t length;
+
+ // memory OK (after a memoryVerify)
+ bool memOK;
+
+ // cache in RAM before writing in memory. Useful also to read a block.
+ uint8_t * page;
+
+ int BlockSize;
+ uint64_t MemorySize;
+ uint64_t BlockCount;
+
+ void CBWDecode(uint8_t * buf, uint16_t size);
+ void sendCSW (void);
+ bool inquiryRequest (void);
+ bool write (uint8_t * buf, uint16_t size);
+ bool readFormatCapacity();
+ bool readCapacity (void);
+ bool infoTransfer (void);
+ void memoryRead (void);
+ bool modeSense6 (void);
+ void testUnitReady (void);
+ bool requestSense (void);
+ void memoryVerify (uint8_t * buf, uint16_t size);
+ void memoryWrite (uint8_t * buf, uint16_t size);
+ void reset();
+ void fail();
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/CircBuffer.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/CircBuffer.h
new file mode 100644
index 000000000..ea46bdfe6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/CircBuffer.h
@@ -0,0 +1,63 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef CIRCBUFFER_H
+#define CIRCBUFFER_H
+
+template <class T, int Size>
+class CircBuffer {
+public:
+ CircBuffer():write(0), read(0){}
+ bool isFull() {
+ return ((write + 1) % size == read);
+ };
+
+ bool isEmpty() {
+ return (read == write);
+ };
+
+ void queue(T k) {
+ if (isFull()) {
+ read++;
+ read %= size;
+ }
+ buf[write++] = k;
+ write %= size;
+ }
+
+ uint16_t available() {
+ return (write >= read) ? write - read : size - read + write;
+ };
+
+ bool dequeue(T * c) {
+ bool empty = isEmpty();
+ if (!empty) {
+ *c = buf[read++];
+ read %= size;
+ }
+ return(!empty);
+ };
+
+private:
+ volatile uint16_t write;
+ volatile uint16_t read;
+ static const int size = Size+1; //a modern optimizer should be able to remove this so it uses no ram.
+ T buf[Size];
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBCDC.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBCDC.cpp
new file mode 100644
index 000000000..aa55541f3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBCDC.cpp
@@ -0,0 +1,286 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBCDC.h"
+
+static uint8_t cdc_line_coding[7]= {0x80, 0x25, 0x00, 0x00, 0x00, 0x00, 0x08};
+
+#define DEFAULT_CONFIGURATION (1)
+
+#define CDC_SET_LINE_CODING 0x20
+#define CDC_GET_LINE_CODING 0x21
+#define CDC_SET_CONTROL_LINE_STATE 0x22
+
+// Control Line State bits
+#define CLS_DTR (1 << 0)
+#define CLS_RTS (1 << 1)
+
+#define MAX_CDC_REPORT_SIZE MAX_PACKET_SIZE_EPBULK
+
+USBCDC::USBCDC(uint16_t vendor_id, uint16_t product_id, uint16_t product_release, bool connect_blocking): USBDevice(vendor_id, product_id, product_release) {
+ terminal_connected = false;
+ USBDevice::connect(connect_blocking);
+}
+
+bool USBCDC::USBCallback_request(void) {
+ /* Called in ISR context */
+
+ bool success = false;
+ CONTROL_TRANSFER * transfer = getTransferPtr();
+
+ /* Process class-specific requests */
+
+ if (transfer->setup.bmRequestType.Type == CLASS_TYPE) {
+ switch (transfer->setup.bRequest) {
+ case CDC_GET_LINE_CODING:
+ transfer->remaining = 7;
+ transfer->ptr = cdc_line_coding;
+ transfer->direction = DEVICE_TO_HOST;
+ success = true;
+ break;
+ case CDC_SET_LINE_CODING:
+ transfer->remaining = 7;
+ transfer->notify = true;
+ success = true;
+ break;
+ case CDC_SET_CONTROL_LINE_STATE:
+ if (transfer->setup.wValue & CLS_DTR) {
+ terminal_connected = true;
+ } else {
+ terminal_connected = false;
+ }
+ success = true;
+ break;
+ default:
+ break;
+ }
+ }
+
+ return success;
+}
+
+void USBCDC::USBCallback_requestCompleted(uint8_t *buf, uint32_t length) {
+ // Request of setting line coding has 7 bytes
+ if (length != 7) {
+ return;
+ }
+
+ CONTROL_TRANSFER * transfer = getTransferPtr();
+
+ /* Process class-specific requests */
+ if (transfer->setup.bmRequestType.Type == CLASS_TYPE) {
+ if (transfer->setup.bRequest == CDC_SET_LINE_CODING) {
+ if (memcmp(cdc_line_coding, buf, 7)) {
+ memcpy(cdc_line_coding, buf, 7);
+
+ int baud = buf[0] + (buf[1] << 8)
+ + (buf[2] << 16) + (buf[3] << 24);
+ int stop = buf[4];
+ int bits = buf[6];
+ int parity = buf[5];
+
+ lineCodingChanged(baud, bits, parity, stop);
+ }
+ }
+ }
+}
+
+// Called in ISR context
+// Set configuration. Return false if the
+// configuration is not supported.
+bool USBCDC::USBCallback_setConfiguration(uint8_t configuration) {
+ if (configuration != DEFAULT_CONFIGURATION) {
+ return false;
+ }
+
+ // Configure endpoints > 0
+ addEndpoint(EPINT_IN, MAX_PACKET_SIZE_EPINT);
+ addEndpoint(EPBULK_IN, MAX_PACKET_SIZE_EPBULK);
+ addEndpoint(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+
+ // We activate the endpoint to be able to recceive data
+ readStart(EPBULK_OUT, MAX_PACKET_SIZE_EPBULK);
+ return true;
+}
+
+bool USBCDC::send(uint8_t * buffer, uint32_t size) {
+ return USBDevice::write(EPBULK_IN, buffer, size, MAX_CDC_REPORT_SIZE);
+}
+
+bool USBCDC::readEP(uint8_t * buffer, uint32_t * size) {
+ if (!USBDevice::readEP(EPBULK_OUT, buffer, size, MAX_CDC_REPORT_SIZE))
+ return false;
+ if (!readStart(EPBULK_OUT, MAX_CDC_REPORT_SIZE))
+ return false;
+ return true;
+}
+
+bool USBCDC::readEP_NB(uint8_t * buffer, uint32_t * size) {
+ if (!USBDevice::readEP_NB(EPBULK_OUT, buffer, size, MAX_CDC_REPORT_SIZE))
+ return false;
+ if (!readStart(EPBULK_OUT, MAX_CDC_REPORT_SIZE))
+ return false;
+ return true;
+}
+
+
+uint8_t * USBCDC::deviceDesc() {
+ static uint8_t deviceDescriptor[] = {
+ 18, // bLength
+ 1, // bDescriptorType
+ 0x10, 0x01, // bcdUSB
+ 2, // bDeviceClass
+ 0, // bDeviceSubClass
+ 0, // bDeviceProtocol
+ MAX_PACKET_SIZE_EP0, // bMaxPacketSize0
+ (uint8_t)(LSB(VENDOR_ID)), (uint8_t)(MSB(VENDOR_ID)), // idVendor
+ (uint8_t)(LSB(PRODUCT_ID)), (uint8_t)(MSB(PRODUCT_ID)),// idProduct
+ 0x00, 0x01, // bcdDevice
+ 1, // iManufacturer
+ 2, // iProduct
+ 3, // iSerialNumber
+ 1 // bNumConfigurations
+ };
+ return deviceDescriptor;
+}
+
+uint8_t * USBCDC::stringIinterfaceDesc() {
+ static uint8_t stringIinterfaceDescriptor[] = {
+ 0x08,
+ STRING_DESCRIPTOR,
+ 'C',0,'D',0,'C',0,
+ };
+ return stringIinterfaceDescriptor;
+}
+
+uint8_t * USBCDC::stringIproductDesc() {
+ static uint8_t stringIproductDescriptor[] = {
+ 0x16,
+ STRING_DESCRIPTOR,
+ 'C',0,'D',0,'C',0,' ',0,'D',0,'E',0,'V',0,'I',0,'C',0,'E',0
+ };
+ return stringIproductDescriptor;
+}
+
+
+#define CONFIG1_DESC_SIZE (9+8+9+5+5+4+5+7+9+7+7)
+
+uint8_t * USBCDC::configurationDesc() {
+ static uint8_t configDescriptor[] = {
+ // configuration descriptor
+ 9, // bLength
+ 2, // bDescriptorType
+ LSB(CONFIG1_DESC_SIZE), // wTotalLength
+ MSB(CONFIG1_DESC_SIZE),
+ 2, // bNumInterfaces
+ 1, // bConfigurationValue
+ 0, // iConfiguration
+ 0x80, // bmAttributes
+ 50, // bMaxPower
+
+ // IAD to associate the two CDC interfaces
+ 0x08, // bLength
+ 0x0b, // bDescriptorType
+ 0x00, // bFirstInterface
+ 0x02, // bInterfaceCount
+ 0x02, // bFunctionClass
+ 0x02, // bFunctionSubClass
+ 0, // bFunctionProtocol
+ 0, // iFunction
+
+ // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12
+ 9, // bLength
+ 4, // bDescriptorType
+ 0, // bInterfaceNumber
+ 0, // bAlternateSetting
+ 1, // bNumEndpoints
+ 0x02, // bInterfaceClass
+ 0x02, // bInterfaceSubClass
+ 0x01, // bInterfaceProtocol
+ 0, // iInterface
+
+ // CDC Header Functional Descriptor, CDC Spec 5.2.3.1, Table 26
+ 5, // bFunctionLength
+ 0x24, // bDescriptorType
+ 0x00, // bDescriptorSubtype
+ 0x10, 0x01, // bcdCDC
+
+ // Call Management Functional Descriptor, CDC Spec 5.2.3.2, Table 27
+ 5, // bFunctionLength
+ 0x24, // bDescriptorType
+ 0x01, // bDescriptorSubtype
+ 0x03, // bmCapabilities
+ 1, // bDataInterface
+
+ // Abstract Control Management Functional Descriptor, CDC Spec 5.2.3.3, Table 28
+ 4, // bFunctionLength
+ 0x24, // bDescriptorType
+ 0x02, // bDescriptorSubtype
+ 0x06, // bmCapabilities
+
+ // Union Functional Descriptor, CDC Spec 5.2.3.8, Table 33
+ 5, // bFunctionLength
+ 0x24, // bDescriptorType
+ 0x06, // bDescriptorSubtype
+ 0, // bMasterInterface
+ 1, // bSlaveInterface0
+
+ // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPINT_IN), // bEndpointAddress
+ E_INTERRUPT, // bmAttributes (0x03=intr)
+ LSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPINT), // wMaxPacketSize (MSB)
+ 16, // bInterval
+
+
+
+
+ // interface descriptor, USB spec 9.6.5, page 267-269, Table 9-12
+ 9, // bLength
+ 4, // bDescriptorType
+ 1, // bInterfaceNumber
+ 0, // bAlternateSetting
+ 2, // bNumEndpoints
+ 0x0A, // bInterfaceClass
+ 0x00, // bInterfaceSubClass
+ 0x00, // bInterfaceProtocol
+ 0, // iInterface
+
+ // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPBULK_IN), // bEndpointAddress
+ E_BULK, // bmAttributes (0x02=bulk)
+ LSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (MSB)
+ 0, // bInterval
+
+ // endpoint descriptor, USB spec 9.6.6, page 269-271, Table 9-13
+ ENDPOINT_DESCRIPTOR_LENGTH, // bLength
+ ENDPOINT_DESCRIPTOR, // bDescriptorType
+ PHY_TO_DESC(EPBULK_OUT), // bEndpointAddress
+ E_BULK, // bmAttributes (0x02=bulk)
+ LSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (LSB)
+ MSB(MAX_PACKET_SIZE_EPBULK),// wMaxPacketSize (MSB)
+ 0 // bInterval
+ };
+ return configDescriptor;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBCDC.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBCDC.h
new file mode 100644
index 000000000..33c6b0a02
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBCDC.h
@@ -0,0 +1,123 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBCDC_H
+#define USBCDC_H
+
+/* These headers are included for child class. */
+#include "USBEndpoints.h"
+#include "USBDescriptor.h"
+#include "USBDevice_Types.h"
+
+#include "USBDevice.h"
+
+class USBCDC: public USBDevice {
+public:
+
+ /*
+ * Constructor
+ *
+ * @param vendor_id Your vendor_id
+ * @param product_id Your product_id
+ * @param product_release Your preoduct_release
+ * @param connect_blocking define if the connection must be blocked if USB not plugged in
+ */
+ USBCDC(uint16_t vendor_id, uint16_t product_id, uint16_t product_release, bool connect_blocking);
+
+protected:
+
+ /*
+ * Get device descriptor. Warning: this method has to store the length of the report descriptor in reportLength.
+ *
+ * @returns pointer to the device descriptor
+ */
+ virtual uint8_t * deviceDesc();
+
+ /*
+ * Get string product descriptor
+ *
+ * @returns pointer to the string product descriptor
+ */
+ virtual uint8_t * stringIproductDesc();
+
+ /*
+ * Get string interface descriptor
+ *
+ * @returns pointer to the string interface descriptor
+ */
+ virtual uint8_t * stringIinterfaceDesc();
+
+ /*
+ * Get configuration descriptor
+ *
+ * @returns pointer to the configuration descriptor
+ */
+ virtual uint8_t * configurationDesc();
+
+ /*
+ * Send a buffer
+ *
+ * @param endpoint endpoint which will be sent the buffer
+ * @param buffer buffer to be sent
+ * @param size length of the buffer
+ * @returns true if successful
+ */
+ bool send(uint8_t * buffer, uint32_t size);
+
+ /*
+ * Read a buffer from a certain endpoint. Warning: blocking
+ *
+ * @param endpoint endpoint to read
+ * @param buffer buffer where will be stored bytes
+ * @param size the number of bytes read will be stored in *size
+ * @param maxSize the maximum length that can be read
+ * @returns true if successful
+ */
+ bool readEP(uint8_t * buffer, uint32_t * size);
+
+ /*
+ * Read a buffer from a certain endpoint. Warning: non blocking
+ *
+ * @param endpoint endpoint to read
+ * @param buffer buffer where will be stored bytes
+ * @param size the number of bytes read will be stored in *size
+ * @param maxSize the maximum length that can be read
+ * @returns true if successful
+ */
+ bool readEP_NB(uint8_t * buffer, uint32_t * size);
+
+ /*
+ * Called by USBCallback_requestCompleted when CDC line coding is changed
+ * Warning: Called in ISR
+ *
+ * @param baud The baud rate
+ * @param bits The number of bits in a word (5-8)
+ * @param parity The parity
+ * @param stop The number of stop bits (1 or 2)
+ */
+ virtual void lineCodingChanged(int baud, int bits, int parity, int stop) {};
+
+protected:
+ virtual bool USBCallback_request();
+ virtual void USBCallback_requestCompleted(uint8_t *buf, uint32_t length);
+ virtual bool USBCallback_setConfiguration(uint8_t configuration);
+ volatile bool terminal_connected;
+
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBSerial.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBSerial.cpp
new file mode 100644
index 000000000..4dc28b9e3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBSerial.cpp
@@ -0,0 +1,67 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "stdint.h"
+#include "USBSerial.h"
+
+int USBSerial::_putc(int c) {
+ if (!terminal_connected)
+ return 0;
+ send((uint8_t *)&c, 1);
+ return 1;
+}
+
+int USBSerial::_getc() {
+ uint8_t c = 0;
+ while (buf.isEmpty());
+ buf.dequeue(&c);
+ return c;
+}
+
+
+bool USBSerial::writeBlock(uint8_t * buf, uint16_t size) {
+ if(size > MAX_PACKET_SIZE_EPBULK) {
+ return false;
+ }
+ if(!send(buf, size)) {
+ return false;
+ }
+ return true;
+}
+
+
+
+bool USBSerial::EPBULK_OUT_callback() {
+ uint8_t c[65];
+ uint32_t size = 0;
+
+ //we read the packet received and put it on the circular buffer
+ readEP(c, &size);
+ for (uint32_t i = 0; i < size; i++) {
+ buf.queue(c[i]);
+ }
+
+ //call a potential handler
+ rx.call();
+
+ return true;
+}
+
+uint8_t USBSerial::available() {
+ return buf.available();
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBSerial.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBSerial.h
new file mode 100644
index 000000000..164cf9bc7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBDevice/USBSerial/USBSerial.h
@@ -0,0 +1,161 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef USBSERIAL_H
+#define USBSERIAL_H
+
+#include "USBCDC.h"
+#include "Stream.h"
+#include "CircBuffer.h"
+
+
+/**
+* USBSerial example
+*
+* @code
+* #include "mbed.h"
+* #include "USBSerial.h"
+*
+* //Virtual serial port over USB
+* USBSerial serial;
+*
+* int main(void) {
+*
+* while(1)
+* {
+* serial.printf("I am a virtual serial port\n");
+* wait(1);
+* }
+* }
+* @endcode
+*/
+class USBSerial: public USBCDC, public Stream {
+public:
+
+ /**
+ * Constructor
+ *
+ * @param vendor_id Your vendor_id (default: 0x1f00)
+ * @param product_id Your product_id (default: 0x2012)
+ * @param product_release Your preoduct_release (default: 0x0001)
+ * @param connect_blocking define if the connection must be blocked if USB not plugged in
+ *
+ */
+ USBSerial(uint16_t vendor_id = 0x1f00, uint16_t product_id = 0x2012, uint16_t product_release = 0x0001, bool connect_blocking = true): USBCDC(vendor_id, product_id, product_release, connect_blocking){
+ settingsChangedCallback = 0;
+ };
+
+
+ /**
+ * Send a character. You can use puts, printf.
+ *
+ * @param c character to be sent
+ * @returns true if there is no error, false otherwise
+ */
+ virtual int _putc(int c);
+
+ /**
+ * Read a character: blocking
+ *
+ * @returns character read
+ */
+ virtual int _getc();
+
+ /**
+ * Check the number of bytes available.
+ *
+ * @returns the number of bytes available
+ */
+ uint8_t available();
+
+ /** Determine if there is a character available to read
+ *
+ * @returns
+ * 1 if there is a character available to read,
+ * 0 otherwise
+ */
+ int readable() { return available() ? 1 : 0; }
+
+ /** Determine if there is space available to write a character
+ *
+ * @returns
+ * 1 if there is space to write a character,
+ * 0 otherwise
+ */
+ int writeable() { return 1; } // always return 1, for write operation is blocking
+
+ /**
+ * Write a block of data.
+ *
+ * For more efficiency, a block of size 64 (maximum size of a bulk endpoint) has to be written.
+ *
+ * @param buf pointer on data which will be written
+ * @param size size of the buffer. The maximum size of a block is limited by the size of the endpoint (64 bytes)
+ *
+ * @returns true if successfull
+ */
+ bool writeBlock(uint8_t * buf, uint16_t size);
+
+ /**
+ * Attach a member function to call when a packet is received.
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ */
+ template<typename T>
+ void attach(T* tptr, void (T::*mptr)(void)) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ rx.attach(tptr, mptr);
+ }
+ }
+
+ /**
+ * Attach a callback called when a packet is received
+ *
+ * @param fptr function pointer
+ */
+ void attach(void (*fptr)(void)) {
+ if(fptr != NULL) {
+ rx.attach(fptr);
+ }
+ }
+
+ /**
+ * Attach a callback to call when serial's settings are changed.
+ *
+ * @param fptr function pointer
+ */
+ void attach(void (*fptr)(int baud, int bits, int parity, int stop)) {
+ settingsChangedCallback = fptr;
+ }
+
+protected:
+ virtual bool EPBULK_OUT_callback();
+ virtual void lineCodingChanged(int baud, int bits, int parity, int stop){
+ if (settingsChangedCallback) {
+ settingsChangedCallback(baud, bits, parity, stop);
+ }
+ }
+
+private:
+ FunctionPointer rx;
+ CircBuffer<uint8_t,128> buf;
+ void (*settingsChangedCallback)(int baud, int bits, int parity, int stop);
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/IUSBEnumerator.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/IUSBEnumerator.h
new file mode 100644
index 000000000..06ea4301a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/IUSBEnumerator.h
@@ -0,0 +1,36 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef IUSBENUMERATOR_H_
+#define IUSBENUMERATOR_H_
+
+#include "stdint.h"
+#include "USBEndpoint.h"
+
+/*
+Generic interface to implement for "smart" USB enumeration
+*/
+
+class IUSBEnumerator
+{
+public:
+ virtual void setVidPid(uint16_t vid, uint16_t pid) = 0;
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) = 0; //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) = 0; //Must return true if the endpoint will be used
+};
+
+#endif /*IUSBENUMERATOR_H_*/
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h
new file mode 100644
index 000000000..fbbf066e3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/devdrv_usb_host_api.h
@@ -0,0 +1,329 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : devdrv_usb_host_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_HOST_API_H
+#define USB_HOST_API_H
+
+#include "r_typedefs.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define USB_HOST_PORTNUM (2)
+
+#define USB_HOST_ELT_INTERRUPT_LEVEL (9)
+
+#define USBHCLOCK_X1_48MHZ (0x0000u) /* USB_X1_48MHz */
+#define USBHCLOCK_EXTAL_12MHZ (0x0004u) /* EXTAL_12MHz */
+
+#define USB_HOST_MAX_DEVICE (10)
+
+#define USB_HOST_ON (1)
+#define USB_HOST_OFF (0)
+#define USB_HOST_YES (1)
+#define USB_HOST_NO (0)
+
+#define USB_HOST_NON_SPEED (0)
+#define USB_HOST_LOW_SPEED (1)
+#define USB_HOST_FULL_SPEED (2)
+#define USB_HOST_HIGH_SPEED (3)
+
+/* DEVDRV_SUCCESS(0) & DEVDRV_ERROR(-1) is dev_drv.h */
+#define DEVDRV_USBH_STALL (-2)
+#define DEVDRV_USBH_TIMEOUT (-3)
+#define DEVDRV_USBH_NAK_TIMEOUT (-4)
+#define DEVDRV_USBH_DETACH_ERR (-5)
+#define DEVDRV_USBH_SETUP_ERR (-6)
+#define DEVDRV_USBH_CTRL_COM_ERR (-7)
+#define DEVDRV_USBH_COM_ERR (-8)
+#define DEVDRV_USBH_DEV_ADDR_ERR (-9)
+
+#define USB_HOST_ATTACH (1)
+#define USB_HOST_DETACH (0)
+
+#define USB_HOST_MAX_PIPE_NO (9u)
+#define USB_HOST_PIPE0 (0)
+#define USB_HOST_PIPE1 (1)
+#define USB_HOST_PIPE2 (2)
+#define USB_HOST_PIPE3 (3)
+#define USB_HOST_PIPE4 (4)
+#define USB_HOST_PIPE5 (5)
+#define USB_HOST_PIPE6 (6)
+#define USB_HOST_PIPE7 (7)
+#define USB_HOST_PIPE8 (8)
+#define USB_HOST_PIPE9 (9)
+
+#define USB_HOST_ISO (0xc000u)
+#define USB_HOST_INTERRUPT (0x8000u)
+#define USB_HOST_BULK (0x4000u)
+
+#define USB_HOST_PIPE_IDLE (0x00)
+#define USB_HOST_PIPE_WAIT (0x01)
+#define USB_HOST_PIPE_DONE (0x02)
+#define USB_HOST_PIPE_NORES (0x03)
+#define USB_HOST_PIPE_STALL (0x04)
+#define USB_HOST_PIPE_ERROR (0x05)
+
+#define USB_HOST_NONE (0x0000u)
+#define USB_HOST_BFREFIELD (0x0400u)
+#define USB_HOST_BFREON (0x0400u)
+#define USB_HOST_BFREOFF (0x0000u)
+#define USB_HOST_DBLBFIELD (0x0200u)
+#define USB_HOST_DBLBON (0x0200u)
+#define USB_HOST_DBLBOFF (0x0000u)
+#define USB_HOST_CNTMDFIELD (0x0100u)
+#define USB_HOST_CNTMDON (0x0100u)
+#define USB_HOST_CNTMDOFF (0x0000u)
+#define USB_HOST_SHTNAKON (0x0080u)
+#define USB_HOST_SHTNAKOFF (0x0000u)
+#define USB_HOST_DIRFIELD (0x0010u)
+#define USB_HOST_DIR_H_OUT (0x0010u)
+#define USB_HOST_DIR_H_IN (0x0000u)
+#define USB_HOST_EPNUMFIELD (0x000fu)
+
+#define USB_HOST_CUSE (0)
+#define USB_HOST_D0USE (1)
+#define USB_HOST_D0DMA (2)
+#define USB_HOST_D1USE (3)
+#define USB_HOST_D1DMA (4)
+
+#define USB_HOST_CFIFO_USE (0x0000)
+#define USB_HOST_D0FIFO_USE (0x1000)
+#define USB_HOST_D1FIFO_USE (0x2000)
+#define USB_HOST_D0FIFO_DMA (0x5000)
+#define USB_HOST_D1FIFO_DMA (0x6000)
+
+#define USB_HOST_BUF2FIFO (0)
+#define USB_HOST_FIFO2BUF (1)
+
+#define USB_HOST_DRV_DETACHED (0x0000)
+#define USB_HOST_DRV_ATTACHED (0x0001)
+#define USB_HOST_DRV_GET_DEVICE_DESC_64 (0x0002)
+#define USB_HOST_DRV_POWERED (0x0003)
+#define USB_HOST_DRV_DEFAULT (0x0004)
+#define USB_HOST_DRV_SET_ADDRESS (0x0005)
+#define USB_HOST_DRV_ADDRESSED (0x0006)
+#define USB_HOST_DRV_GET_DEVICE_DESC_18 (0x0007)
+#define USB_HOST_DRV_GET_CONGIG_DESC_9 (0x0008)
+#define USB_HOST_DRV_GET_CONGIG_DESC (0x0009)
+#define USB_HOST_DRV_SET_CONFIG (0x000a)
+#define USB_HOST_DRV_CONFIGURED (0x000b)
+#define USB_HOST_DRV_SUSPEND (0x1000)
+#define USB_HOST_DRV_NORES (0x0100)
+#define USB_HOST_DRV_STALL (0x0200)
+
+#define USB_HOST_TESTMODE_FORCE (0x000du)
+#define USB_HOST_TESTMODE_TESTPACKET (0x000cu)
+#define USB_HOST_TESTMODE_SE0_NAK (0x000bu)
+#define USB_HOST_TESTMODE_K (0x000au)
+#define USB_HOST_TESTMODE_J (0x0009u)
+#define USB_HOST_TESTMODE_NORMAL (0x0000u)
+
+#define USB_HOST_DT_DEVICE (0x01)
+#define USB_HOST_DT_CONFIGURATION (0x02)
+#define USB_HOST_DT_STRING (0x03)
+#define USB_HOST_DT_INTERFACE (0x04)
+#define USB_HOST_DT_ENDPOINT (0x05)
+#define USB_HOST_DT_DEVICE_QUALIFIER (0x06)
+#define USB_HOST_DT_OTHER_SPEED_CONFIGURATION (0x07)
+#define USB_HOST_DT_INTERFACE_POWER (0x08)
+
+#define USB_HOST_IF_CLS_NOT (0x00)
+#define USB_HOST_IF_CLS_AUDIO (0x01)
+#define USB_HOST_IF_CLS_CDC_CTRL (0x02)
+#define USB_HOST_IF_CLS_HID (0x03)
+#define USB_HOST_IF_CLS_PHYSICAL (0x05)
+#define USB_HOST_IF_CLS_IMAGE (0x06)
+#define USB_HOST_IF_CLS_PRINTER (0x07)
+#define USB_HOST_IF_CLS_MASS (0x08)
+#define USB_HOST_IF_CLS_HUB (0x09)
+#define USB_HOST_IF_CLS_CDC_DATA (0x0a)
+#define USB_HOST_IF_CLS_CRAD (0x0b)
+#define USB_HOST_IF_CLS_CONTENT (0x0d)
+#define USB_HOST_IF_CLS_VIDEO (0x0e)
+#define USB_HOST_IF_CLS_DIAG (0xdc)
+#define USB_HOST_IF_CLS_WIRELESS (0xe0)
+#define USB_HOST_IF_CLS_APL (0xfe)
+#define USB_HOST_IF_CLS_VENDOR (0xff)
+#define USB_HOST_IF_CLS_HELE (0xaa)
+
+#define USB_HOST_EP_DIR_MASK (0x80)
+#define USB_HOST_EP_OUT (0x00)
+#define USB_HOST_EP_IN (0x80)
+#define USB_HOST_EP_TYPE (0x03)
+#define USB_HOST_EP_CNTRL (0x00)
+#define USB_HOST_EP_ISO (0x01)
+#define USB_HOST_EP_BULK (0x02)
+#define USB_HOST_EP_INT (0x03)
+#define USB_HOST_EP_NUM_MASK (0x0f)
+
+#define USB_HOST_PIPE_IN (0)
+#define USB_HOST_PIPE_OUT (1)
+
+#define USB_END_POINT_ERROR (0xffff)
+
+#define USB_HOST_REQ_GET_STATUS (0x0000)
+#define USB_HOST_REQ_CLEAR_FEATURE (0x0100)
+#define USB_HOST_REQ_RESERVED2 (0x0200)
+#define USB_HOST_REQ_SET_FEATURE (0x0300)
+#define USB_HOST_REQ_RESERVED4 (0x0400)
+#define USB_HOST_REQ_SET_ADDRESS (0x0500)
+#define USB_HOST_REQ_GET_DESCRIPTOR (0x0600)
+#define USB_HOST_REQ_SET_DESCRIPTOR (0x0700)
+#define USB_HOST_REQ_GET_CONFIGURATION (0x0800)
+#define USB_HOST_REQ_SET_CONFIGURATION (0x0900)
+#define USB_HOST_REQ_GET_INTERFACE (0x0a00)
+#define USB_HOST_REQ_SET_INTERFACE (0x0b00)
+#define USB_HOST_REQ_SYNCH_FRAME (0x0c00)
+
+#define USB_HOST_REQTYPE_HOST_TO_DEVICE (0x0000)
+#define USB_HOST_REQTYPE_DEVICE_TO_HOST (0x0080)
+#define USB_HOST_REQTYPE_STANDARD (0x0020)
+#define USB_HOST_REQTYPE_CLASS (0x0040)
+#define USB_HOST_REQTYPE_VENDOR (0x0060)
+#define USB_HOST_REQTYPE_DEVICE (0x0000)
+#define USB_HOST_REQTYPE_INTERFACE (0x0001)
+#define USB_HOST_REQTYPE_ENDPOINT (0x0002)
+#define USB_HOST_REQTYPE_OTHER (0x0003)
+
+#define USB_HOST_DESCTYPE_DEVICE (0x0100)
+#define USB_HOST_DESCTYPE_CONFIGURATION (0x0200)
+#define USB_HOST_DESCTYPE_STRING (0x0300)
+#define USB_HOST_DESCTYPE_INTERFACE (0x0400)
+#define USB_HOST_DESCTYPE_ENDPOINT (0x0500)
+#define USB_HOST_DESCTYPE_DEVICE_QUALIFIER (0x0600)
+#define USB_HOST_DESCTYPE_OTHER_SPEED_CONFIGURATION (0x0700)
+#define USB_HOST_DESCTYPE_INTERFACE_POWER (0x0800)
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+typedef struct
+{
+ uint16_t pipe_number;
+ uint16_t pipe_cfg;
+ uint16_t pipe_buf;
+ uint16_t pipe_max_pktsize;
+ uint16_t pipe_cycle;
+ uint16_t fifo_port;
+} USB_HOST_CFG_PIPETBL_t;
+
+typedef struct
+{
+ uint32_t fifo;
+ uint32_t buffer;
+ uint32_t bytes;
+ uint32_t dir;
+ uint32_t size;
+} USB_HOST_DMA_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+uint16_t R_USB_api_host_init(uint16_t root, uint8_t int_level, uint16_t mode, uint16_t clockmode);
+int32_t R_USB_api_host_enumeration(uint16_t root, uint16_t devadr);
+int32_t R_USB_api_host_detach(uint16_t root);
+int32_t R_USB_api_host_data_in(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t R_USB_api_host_data_in2(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf, uint32_t *bytes);
+int32_t R_USB_api_host_data_out(uint16_t root, uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t R_USB_api_host_control_transfer(uint16_t root, uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+int32_t R_USB_api_host_set_endpoint(uint16_t root, uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor);
+int32_t R_USB_api_host_clear_endpoint(uint16_t root, USB_HOST_CFG_PIPETBL_t *user_table);
+int32_t R_USB_api_host_clear_endpoint_pipe(uint16_t root, uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table);
+uint16_t R_USB_api_host_SetEndpointTable(uint16_t root, uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t* Table);
+
+int32_t R_USB_api_host_GetDeviceDescriptor(uint16_t root, uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t R_USB_api_host_GetConfigDescriptor(uint16_t root, uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t R_USB_api_host_SetConfig(uint16_t root, uint16_t devadr, uint16_t confignum);
+int32_t R_USB_api_host_SetInterface(uint16_t root, uint16_t devadr, uint16_t interface_alt, uint16_t interface_index);
+int32_t R_USB_api_host_ClearStall(uint16_t root, uint16_t devadr, uint16_t ep_dir);
+uint16_t R_USB_api_host_GetUsbDeviceState(uint16_t root);
+
+void R_USB_api_host_elt_clocksel(uint16_t clockmode);
+void R_USB_api_host_elt_4_4(uint16_t root);
+void R_USB_api_host_elt_4_5(uint16_t root);
+void R_USB_api_host_elt_4_6(uint16_t root);
+void R_USB_api_host_elt_4_7(uint16_t root);
+void R_USB_api_host_elt_4_8(uint16_t root);
+void R_USB_api_host_elt_4_9(uint16_t root);
+void R_USB_api_host_elt_get_desc(uint16_t root);
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host_api.h"
+#include "usb1_host_api.h"
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+#ifdef USB0_HOST_API_H
+uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid(void);
+void Userdef_USB_usb0_host_attach(void);
+void Userdef_USB_usb0_host_detach(void);
+void Userdef_USB_usb0_host_delay_1ms(void);
+void Userdef_USB_usb0_host_delay_xms(uint32_t msec);
+void Userdef_USB_usb0_host_delay_10us(uint32_t usec);
+void Userdef_USB_usb0_host_delay_500ns(void);
+void Userdef_USB_usb0_host_start_dma(USB_HOST_DMA_t * dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb0_host_stop_dma0(void);
+uint32_t Userdef_USB_usb0_host_stop_dma1(void);
+void Userdef_USB_usb0_host_notice(const char * format);
+void Userdef_USB_usb0_host_user_rdy(const char * format, uint16_t data);
+#endif
+
+#ifdef USB1_HOST_API_H
+uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid(void);
+void Userdef_USB_usb1_host_attach(void);
+void Userdef_USB_usb1_host_detach(void);
+void Userdef_USB_usb1_host_delay_1ms(void);
+void Userdef_USB_usb1_host_delay_xms(uint32_t msec);
+void Userdef_USB_usb1_host_delay_10us(uint32_t usec);
+void Userdef_USB_usb1_host_delay_500ns(void);
+void Userdef_USB_usb1_host_start_dma(USB_HOST_DMA_t * dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb1_host_stop_dma0(void);
+uint32_t Userdef_USB_usb1_host_stop_dma1(void);
+void Userdef_USB_usb1_host_notice(const char * format);
+void Userdef_USB_usb1_host_user_rdy(const char * format, uint16_t data);
+#endif
+
+#endif /* USB_HOST_API_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host.h
new file mode 100644
index 000000000..287e0860e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host.h
@@ -0,0 +1,201 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb_host.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB_HOST_H
+#define USB_HOST_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define USB_HOST_DEVICE_0 (0u)
+#define USB_HOST_DEVICE_1 (1u)
+#define USB_HOST_DEVICE_2 (2u)
+#define USB_HOST_DEVICE_3 (3u)
+#define USB_HOST_DEVICE_4 (4u)
+#define USB_HOST_DEVICE_5 (5u)
+#define USB_HOST_DEVICE_6 (6u)
+#define USB_HOST_DEVICE_7 (7u)
+#define USB_HOST_DEVICE_8 (8u)
+#define USB_HOST_DEVICE_9 (9u)
+#define USB_HOST_DEVICE_10 (10u)
+
+#define USB_HOST_ENDPOINT_DESC (0x05)
+
+#define USB_HOST_BITUPLLE (0x0002u)
+#define USB_HOST_BITUCKSEL (0x0004u)
+#define USB_HOST_BITBWAIT (0x003fu)
+
+#define USB_HOST_BUSWAIT_02 (0x0000u)
+#define USB_HOST_BUSWAIT_03 (0x0001u)
+#define USB_HOST_BUSWAIT_04 (0x0002u)
+#define USB_HOST_BUSWAIT_05 (0x0003u)
+#define USB_HOST_BUSWAIT_06 (0x0004u)
+#define USB_HOST_BUSWAIT_07 (0x0005u)
+#define USB_HOST_BUSWAIT_08 (0x0006u)
+#define USB_HOST_BUSWAIT_09 (0x0007u)
+#define USB_HOST_BUSWAIT_10 (0x0008u)
+#define USB_HOST_BUSWAIT_11 (0x0009u)
+#define USB_HOST_BUSWAIT_12 (0x000au)
+#define USB_HOST_BUSWAIT_13 (0x000bu)
+#define USB_HOST_BUSWAIT_14 (0x000cu)
+#define USB_HOST_BUSWAIT_15 (0x000du)
+#define USB_HOST_BUSWAIT_16 (0x000eu)
+#define USB_HOST_BUSWAIT_17 (0x000fu)
+
+#define USB_HOST_FS_JSTS (0x0001u)
+#define USB_HOST_LS_JSTS (0x0002u)
+
+#define USB_HOST_BITRST (0x0040u)
+#define USB_HOST_BITRESUME (0x0020u)
+#define USB_HOST_BITUACT (0x0010u)
+#define USB_HOST_HSPROC (0x0004u)
+#define USB_HOST_HSMODE (0x0003u)
+#define USB_HOST_FSMODE (0x0002u)
+#define USB_HOST_LSMODE (0x0001u)
+#define USB_HOST_UNDECID (0x0000u)
+
+#define USB_HOST_BITRCNT (0x8000u)
+#define USB_HOST_BITDREQE (0x1000u)
+#define USB_HOST_BITMBW (0x0c00u)
+#define USB_HOST_BITMBW_8 (0x0000u)
+#define USB_HOST_BITMBW_16 (0x0400u)
+#define USB_HOST_BITMBW_32 (0x0800u)
+#define USB_HOST_BITBYTE_LITTLE (0x0000u)
+#define USB_HOST_BITBYTE_BIG (0x0100u)
+#define USB_HOST_BITISEL (0x0020u)
+#define USB_HOST_BITCURPIPE (0x000fu)
+
+#define USB_HOST_CFIFO_READ (0x0000u)
+#define USB_HOST_CFIFO_WRITE (0x0020u)
+
+#define USB_HOST_BITBVAL (0x8000u)
+#define USB_HOST_BITBCLR (0x4000u)
+#define USB_HOST_BITFRDY (0x2000u)
+#define USB_HOST_BITDTLN (0x0fffu)
+
+#define USB_HOST_BITBEMPE (0x0400u)
+#define USB_HOST_BITNRDYE (0x0200u)
+#define USB_HOST_BITBRDYE (0x0100u)
+#define USB_HOST_BITBEMP (0x0400u)
+#define USB_HOST_BITNRDY (0x0200u)
+#define USB_HOST_BITBRDY (0x0100u)
+
+#define USB_HOST_BITBCHGE (0x4000u)
+#define USB_HOST_BITDTCHE (0x1000u)
+#define USB_HOST_BITATTCHE (0x0800u)
+#define USB_HOST_BITEOFERRE (0x0040u)
+#define USB_HOST_BITBCHG (0x4000u)
+#define USB_HOST_BITDTCH (0x1000u)
+#define USB_HOST_BITATTCH (0x0800u)
+#define USB_HOST_BITEOFERR (0x0040u)
+
+#define USB_HOST_BITSIGNE (0x0020u)
+#define USB_HOST_BITSACKE (0x0010u)
+#define USB_HOST_BITSIGN (0x0020u)
+#define USB_HOST_BITSACK (0x0010u)
+
+#define USB_HOST_BITSUREQ (0x4000u)
+#define USB_HOST_BITSQSET (0x0080u)
+#define USB_HOST_PID_STALL2 (0x0003u)
+#define USB_HOST_PID_STALL (0x0002u)
+#define USB_HOST_PID_BUF (0x0001u)
+#define USB_HOST_PID_NAK (0x0000u)
+
+#define USB_HOST_PIPExBUF (64u)
+
+#define USB_HOST_D0FIFO (0)
+#define USB_HOST_D1FIFO (1)
+#define USB_HOST_DMA_READY (0)
+#define USB_HOST_DMA_BUSY (1)
+#define USB_HOST_DMA_BUSYEND (2)
+
+#define USB_HOST_FIFO_USE (0x7000)
+
+#define USB_HOST_FIFOERROR (0xffff)
+#define USB_HOST_WRITEEND (0)
+#define USB_HOST_WRITESHRT (1)
+#define USB_HOST_WRITING (2)
+#define USB_HOST_WRITEDMA (3)
+#define USB_HOST_READEND (0)
+#define USB_HOST_READSHRT (1)
+#define USB_HOST_READING (2)
+#define USB_HOST_READOVER (3)
+#define USB_HOST_READZERO (4)
+
+#define USB_HOST_CMD_IDLE (0x0000)
+#define USB_HOST_CMD_DOING (0x0001)
+#define USB_HOST_CMD_DONE (0x0002)
+#define USB_HOST_CMD_NORES (0x0003)
+#define USB_HOST_CMD_STALL (0x0004)
+#define USB_HOST_CMD_FIELD (0x000f)
+
+#if 0
+#define USB_HOST_CHG_CMDFIELD( r, v ) do { r &= ( ~USB_HOST_CMD_FIELD ); \
+ r |= v; } while(0)
+#endif
+
+#define USB_HOST_MODE_WRITE (0x0100)
+#define USB_HOST_MODE_READ (0x0200)
+#define USB_HOST_MODE_NO_DATA (0x0300)
+#define USB_HOST_MODE_FIELD (0x0f00)
+
+#define USB_HOST_STAGE_SETUP (0x0010)
+#define USB_HOST_STAGE_DATA (0x0020)
+#define USB_HOST_STAGE_STATUS (0x0030)
+#define USB_HOST_STAGE_FIELD (0x00f0)
+
+#if 0
+#define USB_HOST_CHG_STAGEFIELD( r, v ) do { r &= ( ~USB_HOST_STAGE_FIELD ); \
+ r |= v; } while(0)
+#endif
+
+#define USB_HOST_DEVADD_MASK (0x7fc0)
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern uint16_t g_usb_host_elt_clockmode;
+
+#endif /* USB_HOST_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host_version.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host_version.h
new file mode 100644
index 000000000..33b82ea6f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/inc/usb_host_version.h
@@ -0,0 +1,32 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb_host_version.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+
+#define USB_HOST_LOCAL_Rev "VER080_140709"
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c
new file mode 100644
index 000000000..0b1b7da65
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.c
@@ -0,0 +1,1486 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include <string.h>
+#include "cmsis.h"
+#include "cmsis_os.h"
+#include "ohci_wrapp_RZ_A1.h"
+#include "ohci_wrapp_RZ_A1_local.h"
+#include "rza_io_regrw.h"
+#include "usb_host_setting.h"
+
+/* ------------------ HcControl Register --------------------- */
+#define OR_CONTROL_PLE (0x00000004)
+#define OR_CONTROL_IE (0x00000008)
+#define OR_CONTROL_CLE (0x00000010)
+#define OR_CONTROL_BLE (0x00000020)
+/* ----------------- HcCommandStatus Register ----------------- */
+#define OR_CMD_STATUS_HCR (0x00000001)
+#define OR_CMD_STATUS_CLF (0x00000002)
+#define OR_CMD_STATUS_BLF (0x00000004)
+#define OR_CMD_STATUS_OCR (0x00000008)
+/* --------------- HcInterruptStatus Register ----------------- */
+#define OR_INTR_STATUS_WDH (0x00000002)
+#define OR_INTR_STATUS_RHSC (0x00000040)
+/* --------------- HcInterruptEnable Register ----------------- */
+#define OR_INTR_ENABLE_WDH (0x00000002)
+#define OR_INTR_ENABLE_RHSC (0x00000040)
+/* -------------- HcRhPortStatus[1:NDP] Register -------------- */
+#define OR_RH_PORT_CSC (0x00010000)
+#define OR_RH_PORT_LSDA (0x00000200)
+#define OR_RH_PORT_PRS (0x00000010)
+#define OR_RH_PORT_POCI (0x00000008)
+#define OR_RH_PORT_CCS (0x00000001)
+
+#define ED_FORMAT (0x00008000) /* Format */
+#define ED_SKIP (0x00004000) /* Skip this ep in queue */
+#define ED_TOGLE_CARRY (0x00000002)
+#define ED_HALTED (0x00000001)
+
+#define TD_SETUP (0x00000000) /* Direction of Setup Packet */
+#define TD_OUT (0x00080000) /* Direction Out */
+#define TD_TOGGLE_0 (0x02000000) /* Toggle 0 */
+#define TD_TOGGLE_1 (0x03000000) /* Toggle 1 */
+
+/* -------------- USB Standard Requests -------------- */
+#define GET_STATUS (0x00)
+#define SET_FEATURE (0x03)
+#define SET_ADDRESS (0x05)
+
+#define TD_CTL_MSK_DP (0x00180000)
+#define TD_CTL_MSK_T (0x03000000)
+#define TD_CTL_MSK_CC (0xF0000000)
+#define TD_CTL_MSK_EC (0x0C000000)
+#define TD_CTL_SHFT_CC (28)
+#define TD_CTL_SHFT_EC (26)
+#define TD_CTL_SHFT_T (24)
+#define ED_SHFT_TOGLE_CARRY (1)
+#define SIG_GEN_LIST_REQ (1)
+#if (ISO_TRANS_MAX_NUM > 0)
+#define TD_PSW_MSK_CC (0xF000)
+#define TD_PSW_SHFT_CC (12)
+#define TD_CTL_MSK_FC (0x07000000)
+#define TD_CTL_SHFT_FC (24)
+#endif
+
+#define CTL_TRANS_TIMEOUT (1000)
+#define BLK_TRANS_TIMEOUT (5)
+#define TOTAL_SEM_NUM (5 + (2 * INT_TRANS_MAX_NUM) + (2 * ISO_TRANS_MAX_NUM))
+
+#define PORT_LOW_SPEED (0x00000200)
+#define PORT_HIGH_SPEED (0x00000400)
+#define PORT_NUM (16 + 1) /* num + root(1) */
+
+typedef struct tag_hctd {
+ uint32_t control; /* Transfer descriptor control */
+ uint8_t *currBufPtr; /* Physical address of current buffer pointer */
+ struct tag_hctd *nextTD; /* Physical pointer to next Transfer Descriptor */
+ uint8_t *bufEnd; /* Physical address of end of buffer */
+} hctd_t;
+
+#if (ISO_TRANS_MAX_NUM > 0)
+#define PSW_NUM (8)
+typedef struct tag_hcisotd {
+ uint32_t control; /* Transfer descriptor control */
+ uint8_t *bufferPage0; /* Buffer Page 0 */
+ struct tag_hcisotd *nextTD; /* Physical pointer to next Transfer Descriptor */
+ uint8_t *bufEnd; /* Physical address of end of buffer */
+ uint16_t offsetPSW[PSW_NUM]; /* Offset/PSW */
+} hcisotd_t;
+#endif
+
+typedef struct tag_hced {
+ uint32_t control; /* Endpoint descriptor control */
+ uint32_t tailTD; /* Physical address of tail in Transfer descriptor list */
+ uint32_t headTD; /* Physcial address of head in Transfer descriptor list */
+ struct tag_hced *nextED; /* Physical address of next Endpoint descriptor */
+} hced_t;
+
+typedef struct tag_hcca {
+ uint32_t IntTable[32]; /* Interrupt Table */
+ uint32_t FrameNumber; /* Frame Number */
+ uint32_t DoneHead; /* Done Head */
+ volatile uint8_t Reserved[116]; /* Reserved for future use */
+ volatile uint8_t Unknown[4]; /* Unused */
+} hcca_t;
+
+typedef struct tag_usb_ohci_reg {
+ volatile uint32_t HcRevision;
+ volatile uint32_t HcControl;
+ volatile uint32_t HcCommandStatus;
+ volatile uint32_t HcInterruptStatus;
+ volatile uint32_t HcInterruptEnable;
+ volatile uint32_t HcInterruptDisable;
+ volatile uint32_t HcHCCA;
+ volatile uint32_t HcPeriodCurrentED;
+ volatile uint32_t HcControlHeadED;
+ volatile uint32_t HcControlCurrentED;
+ volatile uint32_t HcBulkHeadED;
+ volatile uint32_t HcBulkCurrentED;
+ volatile uint32_t HcDoneHead;
+ volatile uint32_t HcFmInterval;
+ volatile uint32_t HcFmRemaining;
+ volatile uint32_t HcFmNumber;
+ volatile uint32_t HcPeriodicStart;
+ volatile uint32_t HcLSThreshold;
+ volatile uint32_t HcRhDescriptorA;
+ volatile uint32_t HcRhDescriptorB;
+ volatile uint32_t HcRhStatus;
+ volatile uint32_t HcRhPortStatus1;
+} usb_ohci_reg_t;
+
+typedef struct tag_genelal_ed {
+ osThreadId tskid;
+ osSemaphoreId semid_wait;
+ osSemaphoreId semid_list;
+ void *p_curr_td; /* pointer of hctd_t or hcisotd_t */
+ hced_t *p_curr_ed;
+ uint32_t pipe_no;
+ uint32_t trans_wait;
+ uint32_t cycle_time;
+ uint8_t *p_start_buf;
+#if (ISO_TRANS_MAX_NUM > 0)
+ uint32_t psw_idx;
+#endif
+} genelal_ed_t;
+
+typedef struct tag_tdinfo {
+ uint32_t count;
+ uint32_t direction;
+ uint32_t msp;
+ uint16_t devadr;
+ uint16_t speed; /* 1:Speed = Low */
+ uint8_t endpoint_no;
+} tdinfo_t;
+
+typedef struct tag_split_trans {
+ uint16_t root_devadr;
+ uint16_t get_port;
+ uint16_t port_speed;
+ uint16_t reset_port;
+ uint32_t seq_cnt;
+ uint32_t port_sts_bits[PORT_NUM];
+} split_trans_t;
+
+static void callback_task(void const * argument);
+static void control_ed_task(void const * argument);
+static void bulk_ed_task(void const * argument);
+static void int_ed_task(void const * argument);
+static int32_t int_trans_doing(hced_t *p_ed, uint32_t index);
+static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed);
+static void chk_genelal_td_done(genelal_ed_t *p_g_ed);
+static void chk_split_trans_setting(genelal_ed_t *p_g_ed);
+static void set_split_trans_setting(void);
+static void control_trans(genelal_ed_t *p_g_ed);
+static void bulk_trans(genelal_ed_t *p_g_ed);
+static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index);
+static uint32_t chk_cycle(hced_t *p_ed);
+static void int_trans(genelal_ed_t *p_g_ed);
+static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info);
+static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed);
+#if (ISO_TRANS_MAX_NUM > 0)
+static void iso_ed_task(void const * argument);
+static int32_t iso_trans_doing(hced_t *p_ed, uint32_t index);
+static void chk_iso_td_done(genelal_ed_t *p_g_ed);
+static int32_t chk_iso_ed(genelal_ed_t *p_g_ed);
+static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index);
+static uint32_t iso_chk_starting_frame(genelal_ed_t *p_g_ed);
+static void iso_trans(genelal_ed_t *p_g_ed);
+#endif
+static void connect_check(void);
+
+extern USB_HOST_CFG_PIPETBL_t usb_host_blk_ep_tbl1[];
+extern USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[];
+#if (ISO_TRANS_MAX_NUM > 0)
+extern USB_HOST_CFG_PIPETBL_t usb_host_iso_ep_tbl1[];
+#endif
+
+static usb_ohci_reg_t usb_reg;
+static usb_ohci_reg_t *p_usb_reg = &usb_reg;
+static usbisr_fnc_t *p_usbisr_cb = NULL;
+static osSemaphoreId semid_cb = NULL;
+static uint32_t connect_change = 0xFFFFFFFF;
+static uint32_t init_end = 0;
+static genelal_ed_t ctl_ed;
+static genelal_ed_t blk_ed;
+static genelal_ed_t int_ed[INT_TRANS_MAX_NUM];
+static split_trans_t split_ctl;
+
+#if (ISO_TRANS_MAX_NUM > 0)
+static genelal_ed_t iso_ed[ISO_TRANS_MAX_NUM];
+#endif
+
+osSemaphoreDef(ohciwrapp_sem_01);
+osSemaphoreDef(ohciwrapp_sem_02);
+osSemaphoreDef(ohciwrapp_sem_03);
+osSemaphoreDef(ohciwrapp_sem_04);
+osSemaphoreDef(ohciwrapp_sem_05);
+osSemaphoreDef(ohciwrapp_sem_06);
+osSemaphoreDef(ohciwrapp_sem_07);
+#if (INT_TRANS_MAX_NUM >= 2)
+osSemaphoreDef(ohciwrapp_sem_08);
+osSemaphoreDef(ohciwrapp_sem_09);
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+osSemaphoreDef(ohciwrapp_sem_10);
+osSemaphoreDef(ohciwrapp_sem_11);
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+osSemaphoreDef(ohciwrapp_sem_12);
+osSemaphoreDef(ohciwrapp_sem_13);
+#endif
+#if (ISO_TRANS_MAX_NUM >= 1)
+osSemaphoreDef(ohciwrapp_sem_14);
+osSemaphoreDef(ohciwrapp_sem_15);
+#endif
+#if (ISO_TRANS_MAX_NUM >= 2)
+osSemaphoreDef(ohciwrapp_sem_16);
+osSemaphoreDef(ohciwrapp_sem_17);
+#endif
+
+osThreadDef(callback_task, osPriorityHigh, 512);
+osThreadDef(control_ed_task, osPriorityNormal, 512);
+osThreadDef(bulk_ed_task, osPriorityNormal, 512);
+static void int_ed_task_1(void const * argument) {
+ int_ed_task(argument);
+}
+osThreadDef(int_ed_task_1, osPriorityNormal, 512);
+#if (INT_TRANS_MAX_NUM >= 2)
+static void int_ed_task_2(void const * argument) {
+ int_ed_task(argument);
+}
+osThreadDef(int_ed_task_2, osPriorityNormal, 512);
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+static void int_ed_task_3(void const * argument) {
+ int_ed_task(argument);
+}
+osThreadDef(int_ed_task_3, osPriorityNormal, 512);
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+static void int_ed_task_4(void const * argument) {
+ int_ed_task(argument);
+}
+osThreadDef(int_ed_task_4, osPriorityNormal, 512);
+#endif
+
+#if (ISO_TRANS_MAX_NUM >= 1)
+static void iso_ed_task_1(void const * argument) {
+ iso_ed_task(argument);
+}
+osThreadDef(iso_ed_task_1, osPriorityNormal, 512);
+#endif
+#if (ISO_TRANS_MAX_NUM >= 2)
+static void iso_ed_task_2(void const * argument) {
+ iso_ed_task(argument);
+}
+osThreadDef(iso_ed_task_2, osPriorityNormal, 512);
+#endif
+
+void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc) {
+ static const osSemaphoreDef_t * const sem_def_tbl[TOTAL_SEM_NUM] = {
+ osSemaphore(ohciwrapp_sem_01), osSemaphore(ohciwrapp_sem_02), osSemaphore(ohciwrapp_sem_03)
+ , osSemaphore(ohciwrapp_sem_04), osSemaphore(ohciwrapp_sem_05), osSemaphore(ohciwrapp_sem_06)
+ , osSemaphore(ohciwrapp_sem_07)
+#if (INT_TRANS_MAX_NUM >= 2)
+ , osSemaphore(ohciwrapp_sem_08), osSemaphore(ohciwrapp_sem_09)
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+ , osSemaphore(ohciwrapp_sem_10), osSemaphore(ohciwrapp_sem_11)
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+ , osSemaphore(ohciwrapp_sem_12), osSemaphore(ohciwrapp_sem_13)
+#endif
+#if (ISO_TRANS_MAX_NUM >= 1)
+ , osSemaphore(ohciwrapp_sem_14), osSemaphore(ohciwrapp_sem_15)
+#endif
+#if (ISO_TRANS_MAX_NUM >= 2)
+ , osSemaphore(ohciwrapp_sem_16), osSemaphore(ohciwrapp_sem_17)
+#endif
+ };
+ static const osThreadDef_t * const int_tsk_def_tbl[INT_TRANS_MAX_NUM] = {
+ osThread(int_ed_task_1)
+#if (INT_TRANS_MAX_NUM >= 2)
+ , osThread(int_ed_task_2)
+#endif
+#if (INT_TRANS_MAX_NUM >= 3)
+ , osThread(int_ed_task_3)
+#endif
+#if (INT_TRANS_MAX_NUM >= 4)
+ , osThread(int_ed_task_4)
+#endif
+ };
+#if (ISO_TRANS_MAX_NUM > 0)
+ static const osThreadDef_t * const iso_tsk_def_tbl[ISO_TRANS_MAX_NUM] = {
+ osThread(iso_ed_task_1)
+#if (ISO_TRANS_MAX_NUM >= 2)
+ , osThread(iso_ed_task_2)
+#endif
+ };
+#endif
+
+ uint32_t cnt;
+ uint32_t index = 0;
+
+ /* Disables interrupt for usb */
+ GIC_DisableIRQ(USBIXUSBIX);
+
+#if (USB_HOST_CH == 0)
+ /* P4_1(USB0_EN) */
+ GPIOP4 &= ~0x0002; /* Outputs low level */
+ GPIOPMC4 &= ~0x0002; /* Port mode */
+ GPIOPM4 &= ~0x0002; /* Output mode */
+#endif
+
+ p_usbisr_cb = p_usbisr_fnc;
+#if (USB_HOST_HISPEED == 0)
+ g_usbx_host_SupportUsbDeviceSpeed = USB_HOST_FULL_SPEED;
+#else
+ g_usbx_host_SupportUsbDeviceSpeed = USB_HOST_HIGH_SPEED;
+#endif
+ p_usb_reg->HcRevision = 0x00000010;
+ p_usb_reg->HcControl = 0x00000000;
+ p_usb_reg->HcCommandStatus = 0x00000000;
+ p_usb_reg->HcInterruptStatus = 0x00000000;
+ p_usb_reg->HcInterruptEnable = 0x00000000;
+ p_usb_reg->HcInterruptDisable = 0x00000000;
+ p_usb_reg->HcHCCA = 0x00000000;
+ p_usb_reg->HcPeriodCurrentED = 0x00000000;
+ p_usb_reg->HcControlHeadED = 0x00000000;
+ p_usb_reg->HcControlCurrentED = 0x00000000;
+ p_usb_reg->HcBulkHeadED = 0x00000000;
+ p_usb_reg->HcBulkCurrentED = 0x00000000;
+ p_usb_reg->HcDoneHead = 0x00000000;
+ p_usb_reg->HcFmInterval = 0x00002EDF;
+ p_usb_reg->HcFmRemaining = 0x00002EDF;
+ p_usb_reg->HcFmNumber = 0x00000000;
+ p_usb_reg->HcPeriodicStart = 0x00000000;
+ p_usb_reg->HcLSThreshold = 0x00000628;
+ p_usb_reg->HcRhDescriptorA = 0xFF000901;
+ p_usb_reg->HcRhDescriptorB = 0x00020000;
+ p_usb_reg->HcRhStatus = 0x00000000;
+ p_usb_reg->HcRhPortStatus1 = 0x00000000;
+
+#if (USB_HOST_CH == 0)
+ GPIOP4 |= 0x0002; /* P4_1 Outputs high level */
+ osDelay(5);
+ GPIOP4 &= ~0x0002; /* P4_1 Outputs low level */
+ osDelay(10);
+#else
+ osDelay(15);
+#endif
+
+ if (init_end == 0) {
+ (void)memset(&ctl_ed, 0, sizeof(ctl_ed));
+ (void)memset(&blk_ed, 0, sizeof(blk_ed));
+ (void)memset(&int_ed[0], 0, sizeof(int_ed));
+#if (ISO_TRANS_MAX_NUM > 0)
+ (void)memset(&iso_ed[0], 0, sizeof(iso_ed));
+#endif
+
+ /* callback */
+ semid_cb = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ (void)osThreadCreate(osThread(callback_task), 0);
+
+ /* control transfer */
+ ctl_ed.semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ ctl_ed.semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ ctl_ed.tskid = osThreadCreate(osThread(control_ed_task), 0);
+
+ /* bulk transfer */
+ blk_ed.semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ blk_ed.semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ blk_ed.tskid = osThreadCreate(osThread(bulk_ed_task), 0);
+
+ /* interrupt transfer */
+ for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+ int_ed[cnt].semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ int_ed[cnt].semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ int_ed[cnt].tskid = osThreadCreate(int_tsk_def_tbl[cnt], (void *)cnt);
+ }
+
+#if (ISO_TRANS_MAX_NUM > 0)
+ /* isochronous transfer */
+ for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
+ iso_ed[cnt].semid_wait = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ iso_ed[cnt].semid_list = osSemaphoreCreate(sem_def_tbl[index], 0);
+ index++;
+ iso_ed[cnt].tskid = osThreadCreate(iso_tsk_def_tbl[cnt], (void *)cnt);
+ }
+#endif
+ init_end = 1;
+ }
+}
+
+uint32_t ohciwrapp_reg_r(uint32_t reg_ofs) {
+ if (init_end == 0) {
+ return 0;
+ }
+
+ return *(uint32_t *)((uint8_t *)p_usb_reg + reg_ofs);
+}
+
+void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data) {
+ uint32_t cnt;
+ uint32_t last_data;
+ hcca_t *p_hcca;
+
+ if (init_end == 0) {
+ return;
+ }
+
+ switch (reg_ofs) {
+ case OHCI_REG_CONTROL:
+ last_data = p_usb_reg->HcControl;
+ p_usb_reg->HcControl = (set_data & 0x000007FF);
+ if ((last_data & OR_CONTROL_CLE) != (set_data & OR_CONTROL_CLE)) {
+ /* change CLE */
+ if ((set_data & OR_CONTROL_CLE) != 0) {
+ (void)osSemaphoreRelease(ctl_ed.semid_list);
+ } else {
+ if (ctl_ed.trans_wait == 1) {
+ ctl_ed.trans_wait = 0;
+ (void)osSemaphoreRelease(ctl_ed.semid_wait);
+ }
+ (void)osSemaphoreWait(ctl_ed.semid_list, osWaitForever);
+ }
+ }
+ if ((last_data & OR_CONTROL_BLE) != (set_data & OR_CONTROL_BLE)) {
+ /* change BLE */
+ if ((set_data & OR_CONTROL_BLE) != 0) {
+ (void)osSemaphoreRelease(blk_ed.semid_list);
+ } else {
+ if (blk_ed.trans_wait == 1) {
+ blk_ed.trans_wait = 0;
+ (void)osSemaphoreRelease(blk_ed.semid_wait);
+ }
+ (void)osSemaphoreWait(blk_ed.semid_list, osWaitForever);
+ }
+ }
+#if (ISO_TRANS_MAX_NUM > 0)
+ if ((last_data & OR_CONTROL_IE) != (set_data & OR_CONTROL_IE)) {
+ /* change IE */
+ for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
+ if ((set_data & OR_CONTROL_IE) != 0) {
+ (void)osSemaphoreRelease(iso_ed[cnt].semid_list);
+ } else {
+ if (iso_ed[cnt].trans_wait == 1) {
+ iso_ed[cnt].trans_wait = 0;
+ (void)osSemaphoreRelease(iso_ed[cnt].semid_wait);
+ }
+ (void)osSemaphoreWait(iso_ed[cnt].semid_list, osWaitForever);
+ }
+ }
+ }
+#endif
+ if ((last_data & OR_CONTROL_PLE) != (set_data & OR_CONTROL_PLE)) {
+ /* change PLE */
+ for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+ if ((set_data & OR_CONTROL_PLE) != 0) {
+ (void)osSemaphoreRelease(int_ed[cnt].semid_list);
+ } else {
+ if (int_ed[cnt].trans_wait == 1) {
+ int_ed[cnt].trans_wait = 0;
+ (void)osSemaphoreRelease(int_ed[cnt].semid_wait);
+ }
+ (void)osSemaphoreWait(int_ed[cnt].semid_list, osWaitForever);
+ }
+ }
+ }
+ break;
+ case OHCI_REG_COMMANDSTATUS:
+ if ((set_data & OR_CMD_STATUS_HCR) != 0) { /* HostController Reset */
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_HCR;
+ if (usbx_api_host_init(16, g_usbx_host_SupportUsbDeviceSpeed, USBHCLOCK_X1_48MHZ) == USB_HOST_ATTACH) {
+ ohciwrapp_loc_Connect(1);
+ }
+ p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_HCR;
+ }
+ if ((set_data & OR_CMD_STATUS_CLF) != 0) {
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF;
+ osSignalSet(ctl_ed.tskid, SIG_GEN_LIST_REQ);
+ }
+ if ((set_data & OR_CMD_STATUS_BLF) != 0) {
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF;
+ osSignalSet(blk_ed.tskid, SIG_GEN_LIST_REQ);
+ }
+ if ((set_data & OR_CMD_STATUS_OCR) != 0) {
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_OCR;
+ } else {
+ p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_OCR;
+ }
+ break;
+ case OHCI_REG_INTERRUPTSTATUS:
+ if (((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) != 0)
+ && ((set_data & OR_INTR_STATUS_WDH) != 0)) {
+ if (p_usb_reg->HcDoneHead != 0x00000000) {
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+ p_hcca->DoneHead = p_usb_reg->HcDoneHead;
+ p_usb_reg->HcDoneHead = 0x00000000;
+ p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
+ (void)osSemaphoreRelease(semid_cb);
+ } else {
+ p_usb_reg->HcInterruptStatus &= ~OR_INTR_STATUS_WDH;
+ }
+ }
+ if ((set_data & OR_INTR_STATUS_RHSC) != 0) {
+ p_usb_reg->HcInterruptStatus &= ~OR_INTR_STATUS_RHSC;
+ }
+ break;
+ case OHCI_REG_INTERRUPTENABLE:
+ case OHCI_REG_INTERRUPTDISABLE:
+ case OHCI_REG_HCCA:
+ case OHCI_REG_CONTROLHEADED:
+ case OHCI_REG_CONTROLCURRENTED:
+ case OHCI_REG_BULKHEADED:
+ case OHCI_REG_BULKCURRENTED:
+ case OHCI_REG_FMINTERVAL:
+ case OHCI_REG_FMREMAINING:
+ case OHCI_REG_PERIODICSTART:
+ case OHCI_REG_LSTHRESHOLD:
+ case OHCI_REG_RHDESCRIPTORA:
+ case OHCI_REG_RHDESCRIPTORB:
+ case OHCI_REG_RHSTATUS:
+ *(uint32_t *)((uint8_t *)p_usb_reg + reg_ofs) = set_data;
+ break;
+ case OHCI_REG_RHPORTSTATUS1:
+ p_usb_reg->HcRhPortStatus1 &= ~(set_data & 0xFFFF0000);
+ if ((set_data & OR_RH_PORT_PRS) != 0) { /* Set Port Reset */
+ p_usb_reg->HcRhPortStatus1 |= OR_RH_PORT_PRS;
+ usbx_host_UsbBusReset();
+ p_usb_reg->HcRhPortStatus1 &= ~OR_RH_PORT_PRS;
+ }
+ break;
+ case OHCI_REG_REVISION:
+ case OHCI_REG_PERIODCURRENTED:
+ case OHCI_REG_DONEHEADED:
+ case OHCI_REG_FMNUMBER:
+ default:
+ /* Do Nothing */
+ break;
+ }
+}
+
+static void callback_task(void const * argument) {
+ usbisr_fnc_t *p_wk_cb = p_usbisr_cb;
+
+ if (p_wk_cb == NULL) {
+ return;
+ }
+
+ while (1) {
+ osSemaphoreWait(semid_cb, osWaitForever);
+ if (connect_change != 0xFFFFFFFF) {
+ connect_change = 0xFFFFFFFF;
+ connect_check();
+ }
+ p_wk_cb();
+ }
+}
+
+static void control_ed_task(void const * argument) {
+ while (1) {
+ osSignalWait(SIG_GEN_LIST_REQ, osWaitForever);
+ (void)osSemaphoreWait(ctl_ed.semid_list, osWaitForever);
+ while ((p_usb_reg->HcControl & OR_CONTROL_CLE) != 0) {
+ if ((p_usb_reg->HcControlCurrentED == 0)
+ && ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_CLF) != 0)) {
+ p_usb_reg->HcControlCurrentED = p_usb_reg->HcControlHeadED;
+ p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_CLF;
+ }
+ if (p_usb_reg->HcControlCurrentED != 0) {
+ ctl_ed.p_curr_ed = (hced_t *)p_usb_reg->HcControlCurrentED;
+ if (chk_genelal_ed(&ctl_ed) != 0) {
+ control_trans(&ctl_ed);
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_CLF;
+ }
+ p_usb_reg->HcControlCurrentED = (uint32_t)ctl_ed.p_curr_ed->nextED;
+ } else {
+ break;
+ }
+ }
+ if ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_CLF) != 0) {
+ osSignalSet(ctl_ed.tskid, SIG_GEN_LIST_REQ);
+ }
+ (void)osSemaphoreRelease(ctl_ed.semid_list);
+ }
+}
+
+static void bulk_ed_task(void const * argument) {
+ while (1) {
+ osSignalWait(SIG_GEN_LIST_REQ, osWaitForever);
+ (void)osSemaphoreWait(blk_ed.semid_list, osWaitForever);
+ while ((p_usb_reg->HcControl & OR_CONTROL_BLE) != 0) {
+ if ((p_usb_reg->HcBulkCurrentED == 0)
+ && ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_BLF) != 0)) {
+ p_usb_reg->HcBulkCurrentED = p_usb_reg->HcBulkHeadED;
+ p_usb_reg->HcCommandStatus &= ~OR_CMD_STATUS_BLF;
+ }
+ if (p_usb_reg->HcBulkCurrentED != 0) {
+ blk_ed.p_curr_ed = (hced_t *)p_usb_reg->HcBulkCurrentED;
+ if (chk_genelal_ed(&blk_ed) != 0) {
+ bulk_trans(&blk_ed);
+ p_usb_reg->HcCommandStatus |= OR_CMD_STATUS_BLF;
+ }
+ p_usb_reg->HcBulkCurrentED = (uint32_t)blk_ed.p_curr_ed->nextED;
+ } else {
+ break;
+ }
+ }
+ if ((p_usb_reg->HcCommandStatus & OR_CMD_STATUS_BLF) != 0) {
+ osSignalSet(blk_ed.tskid, SIG_GEN_LIST_REQ);
+ }
+ (void)osSemaphoreRelease(blk_ed.semid_list);
+ }
+}
+
+static void int_ed_task(void const * argument) {
+ genelal_ed_t *p_int_ed = &int_ed[(uint32_t)argument];
+ uint32_t cnt;
+ uint32_t wait_cnt = 0;
+ hcca_t *p_hcca;
+ hced_t *p_ed;
+
+ while (1) {
+ (void)osSemaphoreWait(p_int_ed->semid_list, osWaitForever);
+ if (p_int_ed->p_curr_ed == NULL) {
+ for (cnt = 0; (cnt < 32) && ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0)
+ && (p_int_ed->p_curr_ed == NULL); cnt++) {
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+ p_ed = (hced_t *)p_hcca->IntTable[cnt];
+ while ((p_ed != NULL) && ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0)
+ && (p_int_ed->p_curr_ed == NULL)) {
+ if (int_trans_doing(p_ed, (uint32_t)argument) == 0) {
+ p_int_ed->p_curr_ed = p_ed;
+ if (chk_genelal_ed(p_int_ed) != 0) {
+ int_trans_setting(p_int_ed, (uint32_t)argument);
+ } else {
+ p_int_ed->p_curr_ed = NULL;
+ }
+ }
+ p_ed = p_ed->nextED;
+ }
+ }
+ }
+ if (p_int_ed->p_curr_ed != NULL) {
+ while ((p_usb_reg->HcControl & OR_CONTROL_PLE) != 0) {
+ if (chk_genelal_ed(p_int_ed) != 0) {
+ int_trans(p_int_ed);
+ (void)osSemaphoreWait(p_int_ed->semid_wait, osWaitForever);
+ usbx_host_stop_transfer(p_int_ed->pipe_no);
+ wait_cnt = p_int_ed->cycle_time;
+ } else {
+ if (wait_cnt > 0) {
+ wait_cnt--;
+ } else {
+ p_int_ed->p_curr_ed = NULL;
+ }
+ break;
+ }
+ }
+ }
+ (void)osSemaphoreRelease(p_int_ed->semid_list);
+ if (p_int_ed->p_curr_ed == NULL) {
+ osDelay(10);
+ } else {
+ osDelay(1);
+ }
+ }
+}
+
+static int32_t int_trans_doing(hced_t *p_ed, uint32_t index) {
+ uint32_t cnt;
+ int32_t ret = 0;
+
+ for (cnt = 0; cnt < INT_TRANS_MAX_NUM; cnt++) {
+ if ((index != cnt) && (int_ed[cnt].p_curr_ed == p_ed)) {
+ ret = 1;
+ }
+ }
+
+ return ret;
+}
+
+static int32_t chk_genelal_ed(genelal_ed_t *p_g_ed){
+ int32_t ret = 0;
+ hced_t *p_ed = p_g_ed->p_curr_ed;
+
+ if (((p_ed->control & ED_SKIP) != 0)
+ || ((p_ed->control & ED_FORMAT) != 0)
+ || ((p_ed->headTD & ED_HALTED) != 0)
+ || ((p_ed->tailTD & 0xFFFFFFF0) == (p_ed->headTD & 0xFFFFFFF0))) {
+ /* Do Nothing */
+ } else if ((p_ed->control & 0x0000007F) > 10) {
+ p_ed->headTD |= ED_HALTED;
+ } else {
+ p_g_ed->p_curr_td = (void *)(p_ed->headTD & 0xFFFFFFF0);
+ if (p_g_ed->p_curr_td == NULL) {
+ p_ed->headTD |= ED_HALTED;
+ } else {
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+
+ p_g_ed->p_start_buf = p_td->currBufPtr;
+ ret = 1;
+ }
+ }
+
+ return ret;
+}
+
+static void chk_genelal_td_done(genelal_ed_t *p_g_ed) {
+ hcca_t *p_hcca;
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+ uint32_t ConditionCode = RZA_IO_RegRead_32(&p_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+
+ if ((ConditionCode != TD_CC_NOT_ACCESSED_1) && (ConditionCode != TD_CC_NOT_ACCESSED_2)) {
+ p_g_ed->p_curr_ed->headTD = ((uint32_t)p_td->nextTD & 0xFFFFFFF0)
+ | (p_g_ed->p_curr_ed->headTD & 0x0000000F);
+ p_td->nextTD = (hctd_t *)p_usb_reg->HcDoneHead;
+ p_usb_reg->HcDoneHead = (uint32_t)p_g_ed->p_curr_td;
+ if ((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) == 0) {
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+ p_hcca->DoneHead = p_usb_reg->HcDoneHead;
+ p_usb_reg->HcDoneHead = 0x00000000;
+ p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
+ (void)osSemaphoreRelease(semid_cb);
+ }
+ }
+}
+
+static void chk_split_trans_setting(genelal_ed_t *p_g_ed) {
+ uint8_t *p_buf;
+ tdinfo_t td_info;
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+
+ /* Hi-Speed mode only */
+ if (g_usbx_host_UsbDeviceSpeed != USB_HOST_HIGH_SPEED) {
+ return;
+ }
+
+ if (RZA_IO_RegRead_32(&p_td->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC) != TD_CC_NOERROR) {
+ return;
+ }
+
+ get_td_info(p_g_ed, &td_info);
+ p_buf = p_g_ed->p_start_buf;
+
+ if (td_info.direction == 0) {
+ uint8_t bRequest = p_buf[1];
+ uint16_t wValue = (p_buf[3] << 8) + p_buf[2];
+ uint16_t wIndx = (p_buf[5] << 8) + p_buf[4];
+ uint16_t devadd;
+
+ if ((td_info.devadr == 0) && (bRequest == SET_ADDRESS)) {
+ /* SET_ADDRESS */
+ usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+ usbx_host_set_devadd(wValue, &devadd);
+ if (split_ctl.root_devadr == 0) {
+ split_ctl.root_devadr = wValue; /* New Address */
+ }
+ } else if ((td_info.devadr == split_ctl.root_devadr) && (bRequest == SET_FEATURE)
+ && (wValue == 0x0004) && (split_ctl.root_devadr != 0)) {
+ /* SET_FEATURE PORT_RESET */
+ split_ctl.reset_port = (wIndx & 0x00FF);
+ } else if ((td_info.devadr == split_ctl.root_devadr) && (bRequest == GET_STATUS)) {
+ /* GET_STATUS */
+ split_ctl.get_port = wIndx;
+ split_ctl.seq_cnt = 1;
+ } else {
+ /* Do Nothing */
+ }
+ } else if (td_info.direction == 2) {
+ if ((td_info.devadr == split_ctl.root_devadr) && (split_ctl.seq_cnt == 1)) {
+ if (split_ctl.get_port < PORT_NUM) {
+ split_ctl.port_sts_bits[split_ctl.get_port] = (p_buf[1] << 8) + p_buf[0];
+ }
+ split_ctl.seq_cnt = 0;
+ }
+ } else {
+ /* Do Nothing */
+ }
+}
+
+static void set_split_trans_setting(void) {
+ uint16_t port_speed;
+ uint16_t devadd;
+
+ if ((split_ctl.root_devadr != 0) && (split_ctl.reset_port != 0) && (split_ctl.reset_port < PORT_NUM)) {
+ usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+ RZA_IO_RegWrite_16(&devadd, split_ctl.root_devadr, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB);
+ RZA_IO_RegWrite_16(&devadd, split_ctl.reset_port, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT);
+ if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_HIGH_SPEED) != 0) {
+ port_speed = USB_HOST_HIGH_SPEED;
+ } else if ((split_ctl.port_sts_bits[split_ctl.reset_port] & PORT_LOW_SPEED) != 0) {
+ port_speed = USB_HOST_LOW_SPEED;
+ } else {
+ port_speed = USB_HOST_FULL_SPEED;
+ }
+ RZA_IO_RegWrite_16(&devadd, port_speed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+ usbx_host_set_devadd(USB_HOST_DEVICE_0, &devadd);
+ split_ctl.reset_port = 0;
+ }
+}
+
+static void control_trans(genelal_ed_t *p_g_ed) {
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+ tdinfo_t td_info;
+ uint16_t devadd;
+
+ get_td_info(p_g_ed, &td_info);
+
+ if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
+ if (td_info.devadr == 0) {
+ set_split_trans_setting();
+ }
+ } else {
+ /* When a non-Hi-Speed, the communication speed is determined from the TD. */
+ usbx_host_get_devadd(USB_HOST_DEVICE_0, &devadd);
+ if (td_info.speed == 1) {
+ RZA_IO_RegWrite_16(&devadd, USB_HOST_LOW_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+ } else {
+ RZA_IO_RegWrite_16(&devadd, USB_HOST_FULL_SPEED, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+ }
+ usbx_host_set_devadd(td_info.devadr, &devadd);
+ }
+
+ USB20X.DCPMAXP = (td_info.devadr << 12) + td_info.msp;
+ if (td_info.direction == 0) {
+ g_usbx_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
+ } else if (td_info.count != 0) {
+ g_usbx_host_CmdStage = (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE);
+ } else {
+ g_usbx_host_CmdStage = (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE);
+ }
+ g_usbx_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
+ p_g_ed->pipe_no = USB_HOST_PIPE0;
+
+ p_g_ed->trans_wait = 1;
+
+ if (td_info.direction == 0) {
+ uint16_t Req = (p_td->currBufPtr[1] << 8) + p_td->currBufPtr[0];
+ uint16_t Val = (p_td->currBufPtr[3] << 8) + p_td->currBufPtr[2];
+ uint16_t Indx = (p_td->currBufPtr[5] << 8) + p_td->currBufPtr[4];
+ uint16_t Len = (p_td->currBufPtr[7] << 8) + p_td->currBufPtr[6];
+
+ g_usbx_host_data_pointer[USB_HOST_PIPE0] = p_td->bufEnd;
+ usbx_host_SetupStage(Req, Val, Indx, Len);
+ } else if (td_info.direction == 1) {
+ usbx_host_CtrlWriteStart(td_info.count, p_td->currBufPtr);
+ } else {
+ usbx_host_CtrlReadStart(td_info.count, p_td->currBufPtr);
+ }
+
+ (void)osSemaphoreWait(p_g_ed->semid_wait, CTL_TRANS_TIMEOUT);
+ if (p_g_ed->trans_wait == 1) {
+ p_g_ed->trans_wait = 0;
+ RZA_IO_RegWrite_32(&p_td->control, TD_CC_DEVICENOTRESPONDING, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+ }
+
+ g_usbx_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usbx_host_CmdStage |= USB_HOST_CMD_IDLE;
+ g_usbx_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
+}
+
+static void bulk_trans(genelal_ed_t *p_g_ed) {
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+ hced_t *p_ed = p_g_ed->p_curr_ed;
+ tdinfo_t td_info;
+ USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_blk_ep_tbl1[0];
+ uint8_t wk_table[6];
+
+ get_td_info(p_g_ed, &td_info);
+
+ wk_table[0] = 0;
+ wk_table[1] = USB_HOST_ENDPOINT_DESC;
+ wk_table[2] = td_info.endpoint_no;
+ if (td_info.direction == 2) {
+ wk_table[2] |= USB_HOST_EP_IN;
+ }
+ wk_table[3] = USB_HOST_EP_BULK;
+ wk_table[4] = (uint8_t)td_info.msp;
+ wk_table[5] = (uint8_t)(td_info.msp >> 8);
+ p_g_ed->pipe_no = user_table->pipe_number;
+ usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
+
+ set_togle(p_g_ed->pipe_no, p_td, p_ed);
+
+ p_g_ed->trans_wait = 1;
+ if (td_info.direction == 1) {
+ usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+ } else {
+ usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+ }
+
+ (void)osSemaphoreWait(p_g_ed->semid_wait, BLK_TRANS_TIMEOUT);
+ usbx_host_stop_transfer(p_g_ed->pipe_no);
+}
+
+static void int_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) {
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+ hced_t *p_ed = p_g_ed->p_curr_ed;
+ tdinfo_t td_info;
+ USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_int_ep_tbl1[index];
+ uint8_t wk_table[6];
+ uint32_t cycle_time;
+ uint16_t devadd;
+
+ get_td_info(p_g_ed, &td_info);
+
+ wk_table[0] = 0;
+ wk_table[1] = USB_HOST_ENDPOINT_DESC;
+ wk_table[2] = td_info.endpoint_no;
+ if (td_info.direction == 2) {
+ wk_table[2] |= USB_HOST_EP_IN;
+ }
+ wk_table[3] = USB_HOST_EP_INT;
+ wk_table[4] = (uint8_t)td_info.msp;
+ wk_table[5] = (uint8_t)(td_info.msp >> 8);
+ cycle_time = chk_cycle(p_ed);
+ p_g_ed->cycle_time = cycle_time;
+ user_table->pipe_cycle = 0;
+ while (cycle_time > 1) {
+ cycle_time >>= 1;
+ user_table->pipe_cycle++;
+ }
+ if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
+ usbx_host_get_devadd(td_info.devadr, &devadd);
+ if (RZA_IO_RegRead_16(&devadd, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD) == USB_HOST_HIGH_SPEED) {
+ user_table->pipe_cycle += 3;
+ if (user_table->pipe_cycle > 7) {
+ user_table->pipe_cycle = 7;
+ }
+ }
+ }
+
+ p_g_ed->pipe_no = user_table->pipe_number;
+ usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
+
+ set_togle(p_g_ed->pipe_no, p_td, p_ed);
+}
+
+static uint32_t chk_cycle(hced_t *p_ed) {
+ uint32_t cnt;
+ uint32_t hit_cnt = 0;
+ uint32_t cycle_time = 1;
+ hcca_t *p_hcca;
+ hced_t *p_wk_ed;
+
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+
+ for (cnt = 0; cnt < 32; cnt++) {
+ p_wk_ed = (hced_t *)p_hcca->IntTable[cnt];
+ while (p_wk_ed != NULL) {
+ if (p_wk_ed == p_ed) {
+ hit_cnt++;
+ break;
+ }
+ p_wk_ed = p_wk_ed->nextED;
+ }
+ }
+ if (hit_cnt < 2) {
+ cycle_time = 32;
+ } else if (hit_cnt < 4) {
+ cycle_time = 16;
+ } else if (hit_cnt < 8) {
+ cycle_time = 8;
+ } else if (hit_cnt < 16) {
+ cycle_time = 4;
+ } else if (hit_cnt < 32) {
+ cycle_time = 2;
+ } else{
+ cycle_time = 1;
+ }
+
+ return cycle_time;
+}
+
+static void int_trans(genelal_ed_t *p_g_ed) {
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+ tdinfo_t td_info;
+
+ get_td_info(p_g_ed, &td_info);
+ p_g_ed->trans_wait = 1;
+ if (td_info.direction == 1) {
+ usbx_host_start_send_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+ } else {
+ usbx_host_start_receive_transfer(p_g_ed->pipe_no, td_info.count, p_td->currBufPtr);
+ }
+}
+
+static void get_td_info(genelal_ed_t *p_g_ed, tdinfo_t *p_td_info) {
+ hced_t *p_ed = p_g_ed->p_curr_ed;
+
+ p_td_info->endpoint_no = (uint8_t)((p_ed->control >> 7) & 0x0000000F);
+ p_td_info->msp = (p_ed->control >> 16) & 0x000007FF;
+ p_td_info->devadr = p_ed->control & 0x0000000F;
+ p_td_info->speed = (p_ed->control >> 13) & 0x00000001;
+ p_td_info->direction = (p_ed->control >> 11) & 0x00000003;
+
+ if ((p_ed->control & ED_FORMAT) == 0) {
+ hctd_t *p_td = (hctd_t *)p_g_ed->p_curr_td;
+
+ if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) {
+ if ((p_td->control & TD_CTL_MSK_DP) == TD_SETUP) {
+ p_td_info->direction = 0;
+ } else if ((p_td->control & TD_CTL_MSK_DP) == TD_OUT) {
+ p_td_info->direction = 1;
+ } else {
+ p_td_info->direction = 2;
+ }
+ }
+ if (p_td->currBufPtr != NULL) {
+ p_td_info->count = (uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1;
+ } else {
+ p_td_info->count = 0;
+ }
+ } else {
+#if (ISO_TRANS_MAX_NUM > 0)
+ hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+
+ if ((p_td_info->direction == 0) || (p_td_info->direction == 3)) {
+ if ((p_isotd->control & TD_CTL_MSK_DP) == TD_SETUP) {
+ p_td_info->direction = 0;
+ } else if ((p_isotd->control & TD_CTL_MSK_DP) == TD_OUT) {
+ p_td_info->direction = 1;
+ } else {
+ p_td_info->direction = 2;
+ }
+ }
+#endif
+ }
+}
+
+static void set_togle(uint32_t pipe, hctd_t *p_td, hced_t *p_ed) {
+ if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_0) {
+ usbx_host_set_sqclr(pipe);
+ } else if ((p_td->control & TD_CTL_MSK_T) == TD_TOGGLE_1) {
+ usbx_host_set_sqset(pipe);
+ } else if ((p_ed->headTD & ED_TOGLE_CARRY) == 0) {
+ usbx_host_set_sqclr(pipe);
+ } else {
+ usbx_host_set_sqset(pipe);
+ }
+}
+
+#if (ISO_TRANS_MAX_NUM > 0)
+static void iso_ed_task(void const * argument) {
+ genelal_ed_t *p_iso_ed = &iso_ed[(uint32_t)argument];
+ uint32_t wait_cnt = 0;
+ uint32_t wait_time = 0;
+ hcca_t *p_hcca;
+ hced_t *p_ed;
+
+ while (1) {
+ (void)osSemaphoreWait(p_iso_ed->semid_list, osWaitForever);
+ if (p_iso_ed->p_curr_ed == NULL) {
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+ p_ed = (hced_t *)p_hcca->IntTable[0];
+ while ((p_ed != NULL) && ((p_usb_reg->HcControl & OR_CONTROL_IE) != 0)
+ && (p_iso_ed->p_curr_ed == NULL)) {
+ if (iso_trans_doing(p_ed, (uint32_t)argument) == 0) {
+ p_iso_ed->p_curr_ed = p_ed;
+ if (chk_iso_ed(p_iso_ed) != 0) {
+ iso_trans_setting(p_iso_ed, (uint32_t)argument);
+ } else {
+ p_iso_ed->p_curr_ed = NULL;
+ }
+ }
+ p_ed = p_ed->nextED;
+ }
+ p_iso_ed->psw_idx = 0;
+ }
+ if (p_iso_ed->p_curr_ed != NULL) {
+ while ((p_usb_reg->HcControl & OR_CONTROL_IE) != 0) {
+ if (chk_iso_ed(p_iso_ed) != 0) {
+ wait_time = iso_chk_starting_frame(p_iso_ed);
+ if (wait_time != 0) {
+ osDelay(wait_time);
+ p_usb_reg->HcFmNumber += wait_time;
+ p_usb_reg->HcFmNumber &= 0x0000FFFF;
+ }
+ p_iso_ed->psw_idx = 0;
+ iso_trans(p_iso_ed);
+ (void)osSemaphoreWait(p_iso_ed->semid_wait, osWaitForever);
+ usbx_host_stop_transfer(p_iso_ed->pipe_no);
+ wait_cnt = 1;
+ } else {
+ if (wait_cnt > 0) {
+ wait_cnt--;
+ } else {
+ p_iso_ed->p_curr_ed = NULL;
+ }
+ break;
+ }
+ }
+ }
+ (void)osSemaphoreRelease(p_iso_ed->semid_list);
+ if (p_iso_ed->p_curr_ed == NULL) {
+ osDelay(10);
+ } else {
+ osDelay(1);
+ }
+ }
+}
+
+static int32_t iso_trans_doing(hced_t *p_ed, uint32_t index) {
+ uint32_t cnt;
+ int32_t ret = 0;
+
+ for (cnt = 0; cnt < ISO_TRANS_MAX_NUM; cnt++) {
+ if ((index != cnt) && (iso_ed[cnt].p_curr_ed == p_ed)) {
+ ret = 1;
+ }
+ }
+
+ return ret;
+}
+
+static void chk_iso_td_done(genelal_ed_t *p_g_ed) {
+ hcca_t *p_hcca;
+ hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+ uint32_t ConditionCode = RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+
+ if ((ConditionCode != TD_CC_NOT_ACCESSED_1) && (ConditionCode != TD_CC_NOT_ACCESSED_2)) {
+ p_g_ed->p_curr_ed->headTD = ((uint32_t)p_isotd->nextTD & 0xFFFFFFF0)
+ | (p_g_ed->p_curr_ed->headTD & 0x0000000F);
+ p_isotd->nextTD = (hcisotd_t *)p_usb_reg->HcDoneHead;
+ p_usb_reg->HcDoneHead = (uint32_t)p_g_ed->p_curr_td;
+ if ((p_usb_reg->HcInterruptStatus & OR_INTR_STATUS_WDH) == 0) {
+ p_hcca = (hcca_t *)p_usb_reg->HcHCCA;
+ p_hcca->DoneHead = p_usb_reg->HcDoneHead;
+ p_usb_reg->HcDoneHead = 0x00000000;
+ p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_WDH;
+ (void)osSemaphoreRelease(semid_cb);
+ }
+ }
+}
+
+static int32_t chk_iso_ed(genelal_ed_t *p_g_ed){
+ int32_t ret = 0;
+ hced_t *p_ed = p_g_ed->p_curr_ed;
+
+ if (((p_ed->control & ED_SKIP) != 0)
+ || ((p_ed->control & ED_FORMAT) == 0)
+ || ((p_ed->headTD & ED_HALTED) != 0)
+ || ((p_ed->tailTD & 0xFFFFFFF0) == (p_ed->headTD & 0xFFFFFFF0))) {
+ /* Do Nothing */
+ } else if ((p_ed->control & 0x0000007F) > 10) {
+ p_ed->headTD |= ED_HALTED;
+ } else {
+ p_g_ed->p_curr_td = (void *)(p_ed->headTD & 0xFFFFFFF0);
+ if (p_g_ed->p_curr_td == NULL) {
+ p_ed->headTD |= ED_HALTED;
+ } else {
+ hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+
+ p_g_ed->p_start_buf = p_isotd->bufferPage0;
+ ret = 1;
+ }
+ }
+
+ return ret;
+}
+
+static void iso_trans_setting(genelal_ed_t *p_g_ed, uint32_t index) {
+ tdinfo_t td_info;
+ USB_HOST_CFG_PIPETBL_t *user_table = &usb_host_iso_ep_tbl1[index];
+ uint8_t wk_table[6];
+ uint16_t devadd;
+
+ get_td_info(p_g_ed, &td_info);
+
+ wk_table[0] = 0;
+ wk_table[1] = USB_HOST_ENDPOINT_DESC;
+ wk_table[2] = td_info.endpoint_no;
+ if (td_info.direction == 2) {
+ wk_table[2] |= USB_HOST_EP_IN;
+ }
+ wk_table[3] = USB_HOST_EP_ISO;
+ wk_table[4] = (uint8_t)td_info.msp;
+ wk_table[5] = (uint8_t)(td_info.msp >> 8);
+ p_g_ed->cycle_time = 1;
+ user_table->pipe_cycle = 0;
+ if (g_usbx_host_UsbDeviceSpeed == USB_HOST_HIGH_SPEED) {
+ usbx_host_get_devadd(td_info.devadr, &devadd);
+ if (RZA_IO_RegRead_16(&devadd, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD) == USB_HOST_HIGH_SPEED) {
+ user_table->pipe_cycle += 3;
+ }
+ }
+
+ p_g_ed->pipe_no = user_table->pipe_number;
+ usbx_api_host_SetEndpointTable(td_info.devadr, user_table, wk_table);
+}
+
+static uint32_t iso_chk_starting_frame(genelal_ed_t *p_g_ed) {
+ hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+ uint32_t starting_frame = p_isotd->control & 0x0000FFFF;
+ uint32_t wait_time = 0;
+
+ if ((p_g_ed->psw_idx == 0) && (starting_frame > p_usb_reg->HcFmNumber)) {
+ wait_time = starting_frame - p_usb_reg->HcFmNumber;
+ }
+
+ return wait_time;
+}
+
+static void iso_trans(genelal_ed_t *p_g_ed) {
+ hcisotd_t *p_isotd = (hcisotd_t *)p_g_ed->p_curr_td;
+ tdinfo_t td_info;
+ uint32_t buff_addr;
+ uint32_t data_size;
+
+ if (((uint32_t)p_isotd->offsetPSW[p_g_ed->psw_idx] & 0x00001000) == 0) {
+ buff_addr = (uint32_t)p_isotd->bufferPage0 & 0xFFFFF000;
+ } else {
+ buff_addr = (uint32_t)p_isotd->bufEnd & 0xFFFFF000;
+ }
+ buff_addr |= (uint32_t)p_isotd->offsetPSW[p_g_ed->psw_idx] & 0x00000FFF;
+
+ if (p_g_ed->psw_idx < RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_FC, TD_CTL_MSK_FC)) {
+ data_size = p_isotd->offsetPSW[p_g_ed->psw_idx + 1] - p_isotd->offsetPSW[p_g_ed->psw_idx];
+ } else {
+ data_size = (uint32_t)p_isotd->bufEnd - buff_addr + 1;
+ }
+ p_isotd->offsetPSW[p_g_ed->psw_idx] = (uint16_t)data_size;
+
+ get_td_info(p_g_ed, &td_info);
+ p_g_ed->trans_wait = 1;
+ if (td_info.direction == 1) {
+ usbx_host_start_send_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr);
+ } else {
+ usbx_host_start_receive_transfer(p_g_ed->pipe_no, data_size, (uint8_t *)buff_addr);
+ }
+}
+#endif
+
+static void connect_check(void) {
+ uint32_t type = 0;
+ uint16_t stat;
+ uint16_t devadd = 0;
+ uint32_t wk_HcRhPortStatus1 = p_usb_reg->HcRhPortStatus1;
+
+ if (usbx_host_CheckAttach() == USB_HOST_ATTACH) {
+ type = 1;
+ }
+
+ if ((((wk_HcRhPortStatus1 & OR_RH_PORT_CCS) == 0) && (type == 0))
+ || (((wk_HcRhPortStatus1 & OR_RH_PORT_CCS) != 0) && (type != 0))) {
+ return;
+ }
+
+ if (type == 0) {
+ usbx_host_UsbDetach();
+ wk_HcRhPortStatus1 &= ~OR_RH_PORT_CCS;
+ } else {
+ usbx_host_UsbAttach();
+ stat = usbx_host_UsbBusReset();
+ RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_UPPHUB_SHIFT, USB_DEVADDn_UPPHUB);
+ RZA_IO_RegWrite_16(&devadd, 0, USB_DEVADDn_HUBPORT_SHIFT, USB_DEVADDn_HUBPORT);
+ if (stat == USB_HOST_HSMODE) {
+ wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA;
+ RZA_IO_RegWrite_16(&USB20X.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+ g_usbx_host_UsbDeviceSpeed = USB_HOST_HIGH_SPEED;
+ } else if (stat == USB_HOST_FSMODE) {
+ wk_HcRhPortStatus1 &= ~OR_RH_PORT_LSDA;
+ RZA_IO_RegWrite_16(&USB20X.SOFCFG, 0, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+ g_usbx_host_UsbDeviceSpeed = USB_HOST_FULL_SPEED;
+ } else {
+ wk_HcRhPortStatus1 |= OR_RH_PORT_LSDA;
+ RZA_IO_RegWrite_16(&USB20X.SOFCFG, 1, USB_SOFCFG_TRNENSEL_SHIFT, USB_SOFCFG_TRNENSEL);
+ g_usbx_host_UsbDeviceSpeed = USB_HOST_LOW_SPEED;
+ }
+ RZA_IO_RegWrite_16(&devadd, g_usbx_host_UsbDeviceSpeed, USB_DEVADDn_USBSPD_SHIFT, USB_DEVADDn_USBSPD);
+ usbx_host_init_pipe_status();
+ usbx_host_set_devadd(USB_HOST_DEVICE_0, &devadd);
+ wk_HcRhPortStatus1 |= OR_RH_PORT_CCS;
+ }
+ wk_HcRhPortStatus1 |= OR_RH_PORT_CSC;
+ p_usb_reg->HcRhPortStatus1 = wk_HcRhPortStatus1;
+ p_usb_reg->HcInterruptStatus |= OR_INTR_STATUS_RHSC;
+ (void)memset(&split_ctl, 0, sizeof(split_ctl));
+}
+
+void ohciwrapp_loc_Connect(uint32_t type) {
+ uint32_t cnt;
+
+ connect_change = type;
+ if (type == 0) {
+ if (ctl_ed.trans_wait == 1) {
+ ohciwrapp_loc_TransEnd(ctl_ed.pipe_no, TD_CC_DEVICENOTRESPONDING);
+ }
+ if (blk_ed.trans_wait == 1) {
+ ohciwrapp_loc_TransEnd(blk_ed.pipe_no, TD_CC_DEVICENOTRESPONDING);
+ }
+ for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) {
+ if (int_ed[cnt].trans_wait == 1) {
+ ohciwrapp_loc_TransEnd(int_ed[cnt].pipe_no, TD_CC_DEVICENOTRESPONDING);
+ }
+ }
+#if (ISO_TRANS_MAX_NUM > 0)
+ for (cnt = 0; cnt< ISO_TRANS_MAX_NUM; cnt++) {
+ if (iso_ed[cnt].trans_wait == 1) {
+ hced_t *p_ed = iso_ed[cnt].p_curr_ed;
+
+ p_ed->headTD |= ED_HALTED;
+ ohciwrapp_loc_TransEnd(iso_ed[cnt].pipe_no, TD_CC_DEVICENOTRESPONDING);
+ }
+ }
+#endif
+ }
+ (void)osSemaphoreRelease(semid_cb);
+}
+
+void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode) {
+ uint32_t periodic = 0;
+ uint32_t cnt;
+ uint32_t sqmon;
+ hced_t *p_ed;
+ genelal_ed_t *p_wait_ed = NULL;
+
+ if (ctl_ed.pipe_no == pipe) {
+ p_wait_ed = &ctl_ed;
+ } else if (blk_ed.pipe_no == pipe) {
+ p_wait_ed = &blk_ed;
+ } else {
+#if (ISO_TRANS_MAX_NUM > 0)
+ if (p_wait_ed == NULL) {
+ for (cnt = 0; cnt< ISO_TRANS_MAX_NUM; cnt++) {
+ if (iso_ed[cnt].pipe_no == pipe) {
+ p_wait_ed = &iso_ed[cnt];
+ break;
+ }
+ }
+ }
+#endif
+ if (p_wait_ed == NULL) {
+ for (cnt = 0; cnt< INT_TRANS_MAX_NUM; cnt++) {
+ if (int_ed[cnt].pipe_no == pipe) {
+ p_wait_ed = &int_ed[cnt];
+ periodic = 1;
+ break;
+ }
+ }
+ }
+ }
+
+ if (p_wait_ed == NULL) {
+ return;
+ }
+ p_ed = p_wait_ed->p_curr_ed;
+ if (p_ed == NULL) {
+ return;
+ }
+
+ if ((p_ed->control & ED_FORMAT) == 0) {
+ hctd_t *p_td = (hctd_t *)p_wait_ed->p_curr_td;
+
+ if (p_td != NULL) {
+ if (ConditionCode == TD_CC_NOERROR) {
+ /* ErrorCount */
+ RZA_IO_RegWrite_32(&p_td->control, 0, TD_CTL_SHFT_EC, TD_CTL_MSK_EC);
+
+ /* CurrentBufferPointer */
+ p_td->currBufPtr += ((uint32_t)p_td->bufEnd - (uint32_t)p_td->currBufPtr + 1) - g_usbx_host_data_count[pipe];
+ } else {
+ /* ErrorCount */
+ RZA_IO_RegWrite_32(&p_td->control, 3, TD_CTL_SHFT_EC, TD_CTL_MSK_EC);
+ }
+
+ /* DataToggle */
+ sqmon = usbx_host_get_sqmon(pipe);
+ RZA_IO_RegWrite_32(&p_td->control, sqmon, TD_CTL_SHFT_T, TD_CTL_MSK_T);
+ if (sqmon == 0) {
+ p_ed->headTD &= ~ED_TOGLE_CARRY;
+ } else {
+ p_ed->headTD |= ED_TOGLE_CARRY;
+ }
+
+ /* ConditionCode */
+ RZA_IO_RegWrite_32(&p_td->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+
+ if (p_wait_ed == &ctl_ed) {
+ chk_split_trans_setting(&ctl_ed);
+ }
+ chk_genelal_td_done(p_wait_ed);
+
+ if (periodic != 0) {
+ if (chk_genelal_ed(p_wait_ed) != 0) {
+ int_trans(p_wait_ed);
+ } else {
+ p_wait_ed->trans_wait = 0;
+ (void)osSemaphoreRelease(p_wait_ed->semid_wait);
+ }
+ } else {
+ p_wait_ed->trans_wait = 0;
+ (void)osSemaphoreRelease(p_wait_ed->semid_wait);
+ }
+ }
+ } else {
+#if (ISO_TRANS_MAX_NUM > 0)
+ hcisotd_t *p_isotd = (hcisotd_t *)p_wait_ed->p_curr_td;
+ uint32_t next_trans = 0;
+
+ if (p_isotd != NULL) {
+ usbx_host_stop_transfer(pipe);
+ if (p_usb_reg->HcFmNumber < 0x0000FFFF) {
+ p_usb_reg->HcFmNumber++;
+ } else {
+ p_usb_reg->HcFmNumber = 0;
+ }
+
+ /* Size of packet */
+ p_isotd->offsetPSW[p_wait_ed->psw_idx] -= g_usbx_host_data_count[pipe];
+
+ /* ConditionCode */
+ RZA_IO_RegWrite_32(&p_isotd->control, ConditionCode, TD_CTL_SHFT_CC, TD_CTL_MSK_CC);
+ RZA_IO_RegWrite_16(&p_isotd->offsetPSW[p_wait_ed->psw_idx],
+ (uint16_t)ConditionCode, TD_PSW_SHFT_CC, TD_PSW_MSK_CC);
+
+ if (usbx_host_CheckAttach() != USB_HOST_ATTACH) {
+ p_ed->headTD |= ED_HALTED;
+ }
+ if (p_wait_ed->psw_idx >= RZA_IO_RegRead_32(&p_isotd->control, TD_CTL_SHFT_FC, TD_CTL_MSK_FC)) {
+ p_wait_ed->psw_idx = 0;
+ chk_iso_td_done(p_wait_ed);
+ } else {
+ p_wait_ed->psw_idx++;
+ }
+ if (chk_iso_ed(p_wait_ed) != 0) {
+ if (iso_chk_starting_frame(p_wait_ed) == 0) {
+ iso_trans(p_wait_ed);
+ next_trans = 1;
+ }
+ }
+ if (next_trans == 0) {
+ p_wait_ed->trans_wait = 0;
+ (void)osSemaphoreRelease(p_wait_ed->semid_wait);
+ }
+ }
+#endif
+ }
+
+}
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h
new file mode 100644
index 000000000..0b1a9ef81
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h
@@ -0,0 +1,60 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef OHCI_WRAPP_RZ_A1_H
+#define OHCI_WRAPP_RZ_A1_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define OHCI_REG_REVISION (0x00) /* HcRevision */
+#define OHCI_REG_CONTROL (0x04) /* HcControl */
+#define OHCI_REG_COMMANDSTATUS (0x08) /* HcCommandStatus */
+#define OHCI_REG_INTERRUPTSTATUS (0x0C) /* HcInterruptStatus */
+#define OHCI_REG_INTERRUPTENABLE (0x10) /* HcInterruptEnable */
+#define OHCI_REG_INTERRUPTDISABLE (0x14) /* HcInterruptDisable */
+#define OHCI_REG_HCCA (0x18) /* HcHCCA */
+#define OHCI_REG_PERIODCURRENTED (0x1C) /* HcPeriodCurrentED */
+#define OHCI_REG_CONTROLHEADED (0x20) /* HcControlHeadED */
+#define OHCI_REG_CONTROLCURRENTED (0x24) /* HcControlCurrentED */
+#define OHCI_REG_BULKHEADED (0x28) /* HcBulkHeadED */
+#define OHCI_REG_BULKCURRENTED (0x2C) /* HcBulkCurrentED */
+#define OHCI_REG_DONEHEADED (0x30) /* HcDoneHead */
+#define OHCI_REG_FMINTERVAL (0x34) /* HcFmInterval */
+#define OHCI_REG_FMREMAINING (0x38) /* HcFmRemaining */
+#define OHCI_REG_FMNUMBER (0x3C) /* HcFmNumber */
+#define OHCI_REG_PERIODICSTART (0x40) /* HcPeriodicStart */
+#define OHCI_REG_LSTHRESHOLD (0x44) /* HcLSThreshold */
+#define OHCI_REG_RHDESCRIPTORA (0x48) /* HcRhDescriptorA */
+#define OHCI_REG_RHDESCRIPTORB (0x4C) /* HcRhDescriptorB */
+#define OHCI_REG_RHSTATUS (0x50) /* HcRhStatus */
+#define OHCI_REG_RHPORTSTATUS1 (0x54) /* HcRhPortStatus1 */
+
+typedef void (usbisr_fnc_t)(void);
+
+extern void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc);
+extern uint32_t ohciwrapp_reg_r(uint32_t reg_ofs);
+extern void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data);
+extern void ohciwrapp_interrupt(uint32_t int_sense);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* OHCI_WRAPP_RZ_A1_H */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1_local.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1_local.h
new file mode 100644
index 000000000..250c45b66
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1_local.h
@@ -0,0 +1,49 @@
+/* Copyright (c) 2010-2011 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef OHCI_WRAPP_RZ_A1_LOCAL_H
+#define OHCI_WRAPP_RZ_A1_LOCAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ConditionCode */
+#define TD_CC_NOERROR (0)
+#define TD_CC_CRC (1)
+#define TD_CC_BITSTUFFING (2)
+#define TD_CC_DATATOGGLEMISMATCH (3)
+#define TD_CC_STALL (4)
+#define TD_CC_DEVICENOTRESPONDING (5)
+#define TD_CC_PIDCHECKFAILURE (6)
+#define TD_CC_UNEXPECTEDPID (7)
+#define TD_CC_DATAOVERRUN (8)
+#define TD_CC_DATAUNDERRUN (9)
+#define TD_CC_BUFFEROVERRUN (12)
+#define TD_CC_BUFFERUNDERRUN (13)
+#define TD_CC_NOT_ACCESSED_1 (14)
+#define TD_CC_NOT_ACCESSED_2 (15)
+
+extern void ohciwrapp_loc_Connect(uint32_t type);
+extern void ohciwrapp_loc_TransEnd(uint32_t pipe, uint32_t ConditionCode);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* OHCI_WRAPP_RZ_A1_LOCAL_H */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_pipe.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_pipe.c
new file mode 100644
index 000000000..2a6d126dd
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_pipe.c
@@ -0,0 +1,190 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_host_api.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/********************************************************************************************************/
+/* Endpoint Configuration Data Format */
+/********************************************************************************************************/
+/* LINE1: Pipe Window Select Register */
+/* CPU Access PIPE : PIPE1 to PIPE9 [ ### SET ### ] */
+/* LINE2: Pipe Configuration Register */
+/* Transfer Type : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* Buffer Ready interrupt : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* Double Buffer Mode : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */
+/* Continuous Transmit: : USB_HOST_CNT_ON / USB_HOST_CNT_OFF [ ### SET ### ] */
+/* Short NAK : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* Transfer Direction : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* Endpoint Number : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* LINE3: Pipe Buffer Configuration Register */
+/* Buffer Size : (uint16_t)((uint16_t)(((x) / 64) - 1) << 10) */
+/* [ ### SET ### ] */
+/* Buffer Top Number : (uint16_t)(x) [ ### SET ### ] */
+/* LINE4: Pipe Maxpacket Size Register */
+/* Max Packet Size : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* LINE5: Pipe Cycle Configuration Register (0x6C) */
+/* ISO Buffer Flush Mode : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* ISO Interval Value : USB_HOST_NONE [ USB_HOST_NONE ] */
+/* LINE6: use FIFO port */
+/* : USB_HOST_CUSE [ ### SET ### ] */
+/* : USB_HOST_D0USE / USB_HOST_D1USE */
+/* : USB_HOST_D0DMA / USB_HOST_D0DMA */
+/* LINE7: use FIFO port Endian : USB_HOST_FIFO_BIG / USB_HOST_FIFO_LITTLE [ #SET# ] */
+/********************************************************************************************************/
+
+/* Device Address 1 */
+USB_HOST_CFG_PIPETBL_t usb_host_blk_ep_tbl1[ ] =
+{
+ {
+ USB_HOST_PIPE3,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(8),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D0USE
+ },
+
+ {
+ /* Pipe end */
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ }
+};
+
+USB_HOST_CFG_PIPETBL_t usb_host_int_ep_tbl1[ ] =
+{
+ {
+ USB_HOST_PIPE6,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(40),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ USB_HOST_PIPE7,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(41),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ USB_HOST_PIPE8,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(42),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ USB_HOST_PIPE9,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((64) / 64) - 1) << 10) | (uint16_t)(43),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ /* Pipe end */
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ }
+};
+
+USB_HOST_CFG_PIPETBL_t usb_host_iso_ep_tbl1[ ] =
+{
+ {
+ USB_HOST_PIPE1,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(44),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ USB_HOST_PIPE2,
+ /* TYPE / BFRE / DBLB / CNTMD / SHTNAK / DIR / EPNUM */
+ USB_HOST_NONE | USB_HOST_NONE | USB_HOST_DBLBON | USB_HOST_CNTMDON | USB_HOST_NONE | USB_HOST_NONE | USB_HOST_NONE,
+ (uint16_t)((uint16_t)(((1024) / 64) - 1) << 10) | (uint16_t)(60),
+ USB_HOST_NONE,
+ USB_HOST_NONE,
+ USB_HOST_D1USE
+ },
+
+ {
+ /* Pipe end */
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF,
+ 0xFFFF
+ }
+};
+
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host.h
new file mode 100644
index 000000000..70e5c2115
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host.h
@@ -0,0 +1,156 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_HOST_H
+#define USB0_HOST_H
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_host_api.h"
+#include "usb_host.h"
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern const uint16_t g_usb0_host_bit_set[];
+extern uint32_t g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+extern uint8_t *g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+extern uint16_t g_usb0_host_PipeIgnore[];
+extern uint16_t g_usb0_host_PipeTbl[];
+extern uint16_t g_usb0_host_pipe_status[];
+extern uint32_t g_usb0_host_PipeDataSize[];
+
+extern USB_HOST_DMA_t g_usb0_host_DmaInfo[];
+extern uint16_t g_usb0_host_DmaPipe[];
+extern uint16_t g_usb0_host_DmaBval[];
+extern uint16_t g_usb0_host_DmaStatus[];
+
+extern uint16_t g_usb0_host_driver_state;
+extern uint16_t g_usb0_host_ConfigNum;
+extern uint16_t g_usb0_host_CmdStage;
+extern uint16_t g_usb0_host_bchg_flag;
+extern uint16_t g_usb0_host_detach_flag;
+extern uint16_t g_usb0_host_attach_flag;
+
+extern uint16_t g_usb0_host_UsbAddress;
+extern uint16_t g_usb0_host_setUsbAddress;
+extern uint16_t g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+extern uint16_t g_usb0_host_UsbDeviceSpeed;
+extern uint16_t g_usb0_host_SupportUsbDeviceSpeed;
+
+extern uint16_t g_usb0_host_SavReq;
+extern uint16_t g_usb0_host_SavVal;
+extern uint16_t g_usb0_host_SavIndx;
+extern uint16_t g_usb0_host_SavLen;
+
+extern uint16_t g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+/* ==== common ==== */
+void usb0_host_dma_stop_d0(uint16_t pipe, uint32_t remain);
+void usb0_host_dma_stop_d1(uint16_t pipe, uint32_t remain);
+uint16_t usb0_host_is_hispeed(void);
+uint16_t usb0_host_is_hispeed_enable(void);
+uint16_t usb0_host_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb0_host_write_buffer(uint16_t pipe);
+uint16_t usb0_host_write_buffer_c(uint16_t pipe);
+uint16_t usb0_host_write_buffer_d0(uint16_t pipe);
+uint16_t usb0_host_write_buffer_d1(uint16_t pipe);
+void usb0_host_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb0_host_read_buffer(uint16_t pipe);
+uint16_t usb0_host_read_buffer_c(uint16_t pipe);
+uint16_t usb0_host_read_buffer_d0(uint16_t pipe);
+uint16_t usb0_host_read_buffer_d1(uint16_t pipe);
+uint16_t usb0_host_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb0_host_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb0_host_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc);
+uint16_t usb0_host_get_mbw(uint32_t trncount, uint32_t dtptr);
+uint16_t usb0_host_read_dma(uint16_t pipe);
+void usb0_host_stop_transfer(uint16_t pipe);
+void usb0_host_brdy_int(uint16_t status, uint16_t int_enb);
+void usb0_host_nrdy_int(uint16_t status, uint16_t int_enb);
+void usb0_host_bemp_int(uint16_t status, uint16_t int_enb);
+void usb0_host_setting_interrupt(uint8_t level);
+void usb0_host_reset_module(uint16_t clockmode);
+uint16_t usb0_host_get_buf_size(uint16_t pipe);
+uint16_t usb0_host_get_mxps(uint16_t pipe);
+void usb0_host_enable_brdy_int(uint16_t pipe);
+void usb0_host_disable_brdy_int(uint16_t pipe);
+void usb0_host_clear_brdy_sts(uint16_t pipe);
+void usb0_host_enable_bemp_int(uint16_t pipe);
+void usb0_host_disable_bemp_int(uint16_t pipe);
+void usb0_host_clear_bemp_sts(uint16_t pipe);
+void usb0_host_enable_nrdy_int(uint16_t pipe);
+void usb0_host_disable_nrdy_int(uint16_t pipe);
+void usb0_host_clear_nrdy_sts(uint16_t pipe);
+void usb0_host_set_pid_buf(uint16_t pipe);
+void usb0_host_set_pid_nak(uint16_t pipe);
+void usb0_host_set_pid_stall(uint16_t pipe);
+void usb0_host_clear_pid_stall(uint16_t pipe);
+uint16_t usb0_host_get_pid(uint16_t pipe);
+void usb0_host_set_sqclr(uint16_t pipe);
+void usb0_host_set_sqset(uint16_t pipe);
+void usb0_host_set_csclr(uint16_t pipe);
+void usb0_host_aclrm(uint16_t pipe);
+void usb0_host_set_aclrm(uint16_t pipe);
+void usb0_host_clr_aclrm(uint16_t pipe);
+uint16_t usb0_host_get_sqmon(uint16_t pipe);
+uint16_t usb0_host_get_inbuf(uint16_t pipe);
+
+/* ==== host ==== */
+void usb0_host_init_pipe_status(void);
+int32_t usb0_host_CtrlTransStart(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+void usb0_host_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void usb0_host_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+uint16_t usb0_host_CtrlWriteStart(uint32_t Bsize, uint8_t *Table);
+void usb0_host_StatusStage(void);
+void usb0_host_get_devadd(uint16_t addr, uint16_t *devadd);
+void usb0_host_set_devadd(uint16_t addr, uint16_t *devadd);
+void usb0_host_InitModule(void);
+uint16_t usb0_host_CheckAttach(void);
+void usb0_host_UsbDetach(void);
+void usb0_host_UsbDetach2(void);
+void usb0_host_UsbAttach(void);
+uint16_t usb0_host_UsbBusReset(void);
+int32_t usb0_host_UsbResume(void);
+int32_t usb0_host_UsbSuspend(void);
+void usb0_host_Enable_DetachINT(void);
+void usb0_host_Disable_DetachINT(void);
+void usb0_host_UsbStateManager(void);
+
+
+#endif /* USB0_HOST_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_api.h
new file mode 100644
index 000000000..dbdd64d6d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_api.h
@@ -0,0 +1,112 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_HOST_API_H
+#define USB0_HOST_API_H
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void usb0_host_interrupt(uint32_t int_sense);
+void usb0_host_dma_interrupt_d0fifo(uint32_t int_sense);
+void usb0_host_dma_interrupt_d1fifo(uint32_t int_sense);
+
+uint16_t usb0_api_host_init(uint8_t int_level, uint16_t mode, uint16_t clockmode);
+int32_t usb0_api_host_enumeration(uint16_t devadr);
+int32_t usb0_api_host_detach(void);
+int32_t usb0_api_host_data_in(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t usb0_api_host_data_out(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t usb0_api_host_control_transfer(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+int32_t usb0_api_host_set_endpoint(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor);
+int32_t usb0_api_host_clear_endpoint(USB_HOST_CFG_PIPETBL_t *user_table);
+int32_t usb0_api_host_clear_endpoint_pipe(uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table);
+uint16_t usb0_api_host_SetEndpointTable(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t* Table);
+int32_t usb0_api_host_data_count(uint16_t pipe, uint32_t *data_count);
+
+int32_t usb0_api_host_GetDeviceDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t usb0_api_host_GetConfigDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t usb0_api_host_SetConfig(uint16_t devadr, uint16_t confignum);
+int32_t usb0_api_host_SetInterface(uint16_t devadr, uint16_t interface_alt, uint16_t interface_index);
+int32_t usb0_api_host_ClearStall(uint16_t devadr, uint16_t ep_dir);
+uint16_t usb0_api_host_GetUsbDeviceState(void);
+
+void usb0_api_host_elt_4_4(void);
+void usb0_api_host_elt_4_5(void);
+void usb0_api_host_elt_4_6(void);
+void usb0_api_host_elt_4_7(void);
+void usb0_api_host_elt_4_8(void);
+void usb0_api_host_elt_4_9(void);
+void usb0_api_host_elt_get_desc(void);
+
+void usb0_host_EL_ModeInit(void);
+void usb0_host_EL_SetUACT(void);
+void usb0_host_EL_ClearUACT(void);
+void usb0_host_EL_SetTESTMODE(uint16_t mode);
+void usb0_host_EL_ClearNRDYSTS(uint16_t pipe);
+uint16_t usb0_host_EL_GetINTSTS1(void);
+void usb0_host_EL_UsbBusReset(void);
+void usb0_host_EL_UsbAttach(void);
+void usb0_host_EL_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void usb0_host_EL_StatusStage(void);
+void usb0_host_EL_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+int32_t usb0_host_EL_UsbSuspend(void);
+int32_t usb0_host_EL_UsbResume(void);
+
+#if 0 /* prototype in devdrv_usb_host_api.h */
+uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid(void);
+void Userdef_USB_usb0_host_attach(void);
+void Userdef_USB_usb0_host_detach(void);
+void Userdef_USB_usb0_host_delay_1ms(void);
+void Userdef_USB_usb0_host_delay_xms(uint32_t msec);
+void Userdef_USB_usb0_host_delay_10us(uint32_t usec);
+void Userdef_USB_usb0_host_delay_500ns(void);
+void Userdef_USB_usb0_host_start_dma(USB_HOST_DMA_t *dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb0_host_stop_dma0(void);
+uint32_t Userdef_USB_usb0_host_stop_dma1(void);
+#endif
+
+#endif /* USB0_HOST_API_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_dmacdrv.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_dmacdrv.h
new file mode 100644
index 000000000..3e5e40c3b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_dmacdrv.h
@@ -0,0 +1,139 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_dmacdrv.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB0_HOST_DMACDRV_H
+#define USB0_HOST_DMACDRV_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct dmac_transinfo
+{
+ uint32_t src_addr; /* Transfer source address */
+ uint32_t dst_addr; /* Transfer destination address */
+ uint32_t count; /* Transfer byte count */
+ uint32_t src_size; /* Transfer source data size */
+ uint32_t dst_size; /* Transfer destination data size */
+ uint32_t saddr_dir; /* Transfer source address direction */
+ uint32_t daddr_dir; /* Transfer destination address direction */
+} dmac_transinfo_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+/* ==== Transfer specification of the sample program ==== */
+#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */
+#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */
+
+/* ==== DMA modes ==== */
+#define DMAC_MODE_REGISTER (0) /* Register mode */
+#define DMAC_MODE_LINK (1) /* Link mode */
+
+/* ==== Transfer requests ==== */
+#define DMAC_REQ_MODE_EXT (0) /* External request */
+#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */
+#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */
+
+/* ==== DMAC transfer sizes ==== */
+#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */
+#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */
+#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */
+#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */
+#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */
+#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */
+#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */
+#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */
+
+/* ==== Address increment for transferring ==== */
+#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */
+#define DMAC_TRANS_ADR_INC (0) /* Increment */
+
+/* ==== Method for detecting DMA request ==== */
+#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */
+#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */
+#define DMAC_REQ_DET_LOW (2) /* Low level detection */
+#define DMAC_REQ_DET_HIGH (3) /* High level detection */
+
+/* ==== Request Direction ==== */
+#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */
+#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */
+
+/* ==== Descriptors ==== */
+#define DMAC_DESC_HEADER (0) /* Header */
+#define DMAC_DESC_SRC_ADDR (1) /* Source Address */
+#define DMAC_DESC_DST_ADDR (2) /* Destination Address */
+#define DMAC_DESC_COUNT (3) /* Transaction Byte */
+#define DMAC_DESC_CHCFG (4) /* Channel Confg */
+#define DMAC_DESC_CHITVL (5) /* Channel Interval */
+#define DMAC_DESC_CHEXT (6) /* Channel Extension */
+#define DMAC_DESC_LINK_ADDR (7) /* Link Address */
+
+/* ==== On-chip peripheral module requests ===== */
+typedef enum dmac_request_factor
+{
+ DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */
+ DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */
+ DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */
+ DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */
+} dmac_request_factor_t;
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void usb0_host_DMAC1_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb0_host_DMAC1_Open(uint32_t req);
+void usb0_host_DMAC1_Close(uint32_t * remain);
+void usb0_host_DMAC1_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+void usb0_host_DMAC2_PeriReqInit(const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb0_host_DMAC2_Open(uint32_t req);
+void usb0_host_DMAC2_Close(uint32_t * remain);
+void usb0_host_DMAC2_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+#endif /* USB0_HOST_DMACDRV_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dataio.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dataio.c
new file mode 100644
index 000000000..bb7b68f2b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dataio.c
@@ -0,0 +1,2835 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_dataio.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static uint16_t g_usb0_host_mbw[(USB_HOST_MAX_PIPE_NO + 1)];
+
+static void usb0_host_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_host_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_host_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_host_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb0_host_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static uint16_t usb0_host_read_dma_d0(uint16_t pipe);
+static uint16_t usb0_host_read_dma_d1(uint16_t pipe);
+static uint16_t usb0_host_write_dma_d0(uint16_t pipe);
+static uint16_t usb0_host_write_dma_d1(uint16_t pipe);
+
+static void usb0_host_read_c_fifo(uint16_t pipe, uint16_t count);
+static void usb0_host_write_c_fifo(uint16_t Pipe, uint16_t count);
+static void usb0_host_read_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb0_host_write_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb0_host_read_d1_fifo(uint16_t pipe, uint16_t count);
+static void usb0_host_write_d1_fifo(uint16_t pipe, uint16_t count);
+
+static void usb0_host_clear_transaction_counter(uint16_t pipe);
+static void usb0_host_set_transaction_counter(uint16_t pipe, uint32_t count);
+
+static uint32_t usb0_host_com_get_dmasize(uint32_t trncount, uint32_t dtptr);
+
+static uint16_t usb0_host_set_dfacc_d0(uint16_t mbw, uint32_t count);
+static uint16_t usb0_host_set_dfacc_d1(uint16_t mbw, uint32_t count);
+
+
+/*******************************************************************************
+* Function Name: usb0_host_start_send_transfer
+* Description : Starts the USB data communication using pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data data Address
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+ uint16_t usefifo;
+ uint16_t mbw;
+
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ usb0_host_clear_bemp_sts(pipe);
+ usb0_host_clear_brdy_sts(pipe);
+ usb0_host_clear_nrdy_sts(pipe);
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+
+ usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ case USB_HOST_D0FIFO_DMA:
+ usefifo = USB_HOST_D0USE;
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ case USB_HOST_D1FIFO_DMA:
+ usefifo = USB_HOST_D1USE;
+ break;
+
+ default:
+ usefifo = USB_HOST_CUSE;
+ break;
+ };
+
+ usb0_host_set_curpipe(USB_HOST_PIPE0, usefifo, USB_HOST_NO, mbw);
+
+ usb0_host_clear_transaction_counter(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ status = usb0_host_write_buffer(pipe);
+
+ if (status != USB_HOST_FIFOERROR)
+ {
+ usb0_host_set_pid_buf(pipe);
+ }
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer
+* Description : Writes data in the buffer allocated in the pipe specified by
+* : the argument. The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer (uint16_t pipe)
+{
+ uint16_t status;
+ uint16_t usefifo;
+
+ g_usb0_host_PipeIgnore[pipe] = 0;
+ usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ status = usb0_host_write_buffer_d0(pipe);
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ status = usb0_host_write_buffer_d1(pipe);
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ status = usb0_host_write_dma_d0(pipe);
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ status = usb0_host_write_dma_d1(pipe);
+ break;
+
+ default:
+ status = usb0_host_write_buffer_c(pipe);
+ break;
+ };
+
+ switch (status)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ usb0_host_enable_brdy_int(pipe); /* Enable Ready Interrupt */
+ break;
+
+ case USB_HOST_WRITEEND: /* End of data write */
+ case USB_HOST_WRITESHRT: /* End of data write */
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+
+ usb0_host_clear_nrdy_sts(pipe);
+ usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+
+ /* for last transfer */
+ usb0_host_enable_bemp_int(pipe); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_WRITEDMA: /* DMA write */
+ usb0_host_clear_nrdy_sts(pipe);
+ usb0_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ usb0_host_disable_bemp_int(pipe); /* Disable Empty Interrupt */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_c
+* Description : Writes data in the buffer allocated in the pipe specified in
+* : the argument. Writes data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_CFIFO_WRITE, mbw);
+ }
+ else
+ {
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+ }
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_host_write_c_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB200.CFIFOCTR,
+ USB_CFIFOCTR_BVAL_SHIFT,
+ USB_CFIFOCTR_BVAL) == 0)
+ {
+ USB200.CFIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_host_write_d0_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_buffer_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_write_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb0_host_write_d1_fifo(pipe, (uint16_t)count);
+
+ if (g_usb0_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb0_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D0FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND : Write end
+* : USB_HOST_WRITESHRT : short data
+* : USB_HOST_WRITING : Continue of data write
+* : USB_HOST_WRITEDMA : Write DMA
+* : USB_HOST_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_write_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe;
+
+ if ((count % size) != 0)
+ {
+ g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 1;
+ }
+ else
+ {
+ g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0;
+ }
+
+ dfacc = usb0_host_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA;
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_BUF2FIFO;
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes = count;
+
+ Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+ usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+
+ g_usb0_host_data_count[pipe] = 0;
+ g_usb0_host_data_pointer[pipe] += count;
+
+ status = USB_HOST_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_dma_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D1FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb0_host_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND : Write end
+* : USB_HOST_WRITESHRT : short data
+* : USB_HOST_WRITING : Continue of data write
+* : USB_HOST_WRITEDMA : Write DMA
+* : USB_HOST_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_write_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb0_host_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe;
+
+ if ((count % size) != 0)
+ {
+ g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 1;
+ }
+ else
+ {
+ g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0;
+ }
+
+ dfacc = usb0_host_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA;
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_BUF2FIFO;
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes = count;
+
+ Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+ usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+
+ g_usb0_host_data_count[pipe] = 0;
+ g_usb0_host_data_pointer[pipe] += count;
+
+ status = USB_HOST_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_transfer
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb0_host_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t usefifo;
+
+ usb0_host_clear_bemp_sts(pipe);
+ usb0_host_clear_brdy_sts(pipe);
+ usb0_host_clear_nrdy_sts(pipe);
+
+ usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ usb0_host_start_receive_trns_d0(pipe, size, data);
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ usb0_host_start_receive_trns_d1(pipe, size, data);
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ usb0_host_start_receive_dma_d0(pipe, size, data);
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ usb0_host_start_receive_dma_d1(pipe, size, data);
+ break;
+
+ default:
+ usb0_host_start_receive_trns_c(pipe, size, data);
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* : When storing data in the buffer allocated in the pipe specified in the
+* : argument, BRDY interrupt is generated to read data
+* : in the interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = size;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_CFIFO_READ, mbw);
+ USB200.CFIFOCTR = USB_HOST_BITBCLR;
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data in the
+* : interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = size;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_trns_d1
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = size;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_dma_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = 0;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb0_host_read_dma(pipe);
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+ }
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_start_receive_dma_d1
+* Description : Read data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_data_count[pipe] = size;
+ g_usb0_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ g_usb0_host_PipeDataSize[pipe] = 0;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb0_host_get_mbw(size, (uint32_t)data);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ usb0_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb0_host_read_dma(pipe);
+
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb0_host_enable_nrdy_int(pipe);
+ usb0_host_enable_brdy_int(pipe);
+ }
+
+ usb0_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Uses FIF0 set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+ {
+ status = usb0_host_read_buffer_d0(pipe);
+ }
+ else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+ {
+ status = usb0_host_read_buffer_d1(pipe);
+ }
+ else
+ {
+ status = usb0_host_read_buffer_c(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb0_host_disable_brdy_int(pipe);
+ g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#else
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+#endif
+ g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_host_read_c_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_d0
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_host_read_d0_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_buffer_d1
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) !=0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb0_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb0_host_read_d1_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb0_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO or D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb0_host_read_dma (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb0_host_PipeIgnore[pipe] = 0;
+
+ if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+ {
+ status = usb0_host_read_dma_d0(pipe);
+ }
+ else
+ {
+ status = usb0_host_read_dma_d1(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READZERO: /* End of data read */
+ usb0_host_disable_brdy_int(pipe);
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb0_host_disable_brdy_int(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+ }
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb0_host_PipeDataSize[pipe] -= g_usb0_host_data_count[pipe];
+ }
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#else
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+#endif
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb0_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_read_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb0_host_data_count[pipe];
+ status = USB_HOST_READING;
+ }
+ else
+ {
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear B_CLR */
+ status = USB_HOST_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb0_host_set_curpipe(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb0_host_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_host_DmaPipe[USB_HOST_D0FIFO] = pipe; /* not use in read operation */
+ g_usb0_host_DmaBval[USB_HOST_D0FIFO] = 0; /* not use in read operation */
+
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA;
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_FIFO2BUF;
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+ g_usb0_host_DmaInfo[USB_HOST_D0FIFO].bytes = count;
+
+ if (status == USB_HOST_READING)
+ {
+ g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSY;
+ }
+ else
+ {
+ g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+ usb0_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ g_usb0_host_data_pointer[pipe] += count;
+ g_usb0_host_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_dma_d1
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by DMA transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb0_host_read_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[pipe], (uint32_t)g_usb0_host_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb0_host_data_count[pipe];
+ status = USB_HOST_READING;
+ }
+ else
+ {
+ buffer = usb0_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb0_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ count = g_usb0_host_data_count[pipe];
+ }
+ else if (g_usb0_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb0_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ status = USB_HOST_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb0_host_set_curpipe(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb0_host_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb0_host_DmaPipe[USB_HOST_D1FIFO] = pipe; /* not use in read operation */
+ g_usb0_host_DmaBval[USB_HOST_D1FIFO] = 0; /* not use in read operation */
+
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA;
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_FIFO2BUF;
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb0_host_data_pointer[pipe];
+ g_usb0_host_DmaInfo[USB_HOST_D1FIFO].bytes = count;
+
+ if (status == USB_HOST_READING)
+ {
+ g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSY;
+ }
+ else
+ {
+ g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb0_host_start_dma(&g_usb0_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+ usb0_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb0_host_data_count[pipe] -= count;
+ g_usb0_host_data_pointer[pipe] += count;
+ g_usb0_host_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_change_fifo_port
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument. After allocating FIF0, waits in the software
+* : till the corresponding pipe becomes ready.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : USB_HOST_FIFOERROR ; Error
+* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value
+*******************************************************************************/
+uint16_t usb0_host_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ usb0_host_set_curpipe(pipe, fifosel, isel, mbw);
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB200.CFIFOCTR;
+ break;
+
+ case USB_HOST_D0USE:
+ case USB_HOST_D0DMA:
+ buffer = USB200.D0FIFOCTR;
+ break;
+
+ case USB_HOST_D1USE:
+ case USB_HOST_D1DMA:
+ buffer = USB200.D1FIFOCTR;
+ break;
+
+ default:
+ buffer = 0;
+ break;
+ }
+
+ if ((buffer & USB_HOST_BITFRDY) == USB_HOST_BITFRDY)
+ {
+ return buffer;
+ }
+
+ loop2 = 25;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ return USB_HOST_FIFOERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_curpipe
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ g_usb0_host_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB200.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D0USE:
+ buffer = USB200.D0FIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D1DMA:
+ case USB_HOST_D1USE:
+ buffer = USB200.D1FIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_curpipe2
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.(DFACC)
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* : uint16_t dfacc ; DFACC Access mode
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc)
+{
+ uint16_t buffer;
+ uint32_t loop;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ uint32_t dummy;
+#endif
+ volatile uint32_t loop2;
+
+ g_usb0_host_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB200.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB200.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D0USE:
+ buffer = USB200.D0FIFOSEL;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB200.D0FIFO.UINT32;
+ }
+#endif
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D1DMA:
+ case USB_HOST_D1USE:
+ buffer = USB200.D1FIFOSEL;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB200.D1FIFO.UINT32;
+ loop = dummy; // avoid warning.
+ }
+#endif
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB200.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB200.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_c_fifo
+* Description : Writes data in CFIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.CFIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.CFIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.CFIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_c_fifo
+* Description : Reads data from CFIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_host_data_pointer[pipe] = USB200.CFIFO.UINT8[HH];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT16[H];
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.CFIFO.UINT32;
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_d0_fifo
+* Description : Writes data in D0FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.D0FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.D0FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.D0FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_d0_fifo
+* Description : Reads data from D0FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating DOFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t Pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_host_data_pointer[pipe] = USB200.D0FIFO.UINT8[HH];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT16[H];
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D0FIFO.UINT32;
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_write_d1_fifo
+* Description : Writes data in D1FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_write_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB200.D1FIFO.UINT8[HH] = *g_usb0_host_data_pointer[pipe];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB200.D1FIFO.UINT16[H] = *((uint16_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB200.D1FIFO.UINT32 = *((uint32_t *)g_usb0_host_data_pointer[pipe]);
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_read_d1_fifo
+* Description : Reads data from D1FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_read_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb0_host_data_pointer[pipe] = USB200.D1FIFO.UINT8[HH];
+ g_usb0_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb0_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT16[H];
+ g_usb0_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb0_host_data_pointer[pipe]) = USB200.D1FIFO.UINT32;
+ g_usb0_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_com_get_dmasize
+* Description : Calculates access width of DMA transfer by the argument to
+ return as the Return Value.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : DMA transfer size : 0 8bit
+* : : 1 16bit
+* : : 2 32bit
+*******************************************************************************/
+static uint32_t usb0_host_com_get_dmasize (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+
+ if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0))
+ {
+ /* When transfer byte count is odd */
+ /* or transfer data area is 8-bit alignment */
+ size = 0; /* 8bit */
+ }
+ else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0))
+ {
+ /* When the transfer byte count is multiples of 2 */
+ /* or the transfer data area is 16-bit alignment */
+ size = 1; /* 16bit */
+ }
+ else
+ {
+ /* When the transfer byte count is multiples of 4 */
+ /* or the transfer data area is 32-bit alignment */
+ size = 2; /* 32bit */
+ }
+
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_mbw
+* Description : Calculates access width of DMA to return the value set in MBW.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : FIFO transfer size : USB_HOST_BITMBW_8 8bit
+* : : USB_HOST_BITMBW_16 16bit
+* : : USB_HOST_BITMBW_32 32bit
+*******************************************************************************/
+uint16_t usb0_host_get_mbw (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+ uint16_t mbw;
+
+ size = usb0_host_com_get_dmasize(trncount, dtptr);
+
+ if (size == 0)
+ {
+ /* 8bit */
+ mbw = USB_HOST_BITMBW_8;
+ }
+ else if (size == 1)
+ {
+ /* 16bit */
+ mbw = USB_HOST_BITMBW_16;
+ }
+ else
+ {
+ /* 32bit */
+ mbw = USB_HOST_BITMBW_32;
+ }
+
+ return mbw;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_transaction_counter
+* Description : Sets transaction counter by the argument(PIPEnTRN).
+* : Clears transaction before setting to enable transaction counter setting.
+* Arguments : uint16_t pipe ; Pipe number
+* : uint32_t bsize : Data transfer size
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_set_transaction_counter (uint16_t pipe, uint32_t bsize)
+{
+ uint16_t mxps;
+ uint16_t cnt;
+
+ if (bsize == 0)
+ {
+ return;
+ }
+
+ mxps = usb0_host_get_mxps(pipe); /* Max Packet Size */
+
+ if ((bsize % mxps) == 0)
+ {
+ cnt = (uint16_t)(bsize / mxps);
+ }
+ else
+ {
+ cnt = (uint16_t)((bsize / mxps) + 1);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE1TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE2TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE3TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE4TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE5TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB200.PIPE9TRN = cnt;
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_transaction_counter
+* Description : Clears the transaction counter by the argument.
+* : After executing this function, the transaction counter is invalid.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_transaction_counter (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB200.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_stop_transfer
+* Description : Stops the USB transfer in the pipe specified by the argument.
+* : After stopping the USB transfer, clears the buffer allocated in
+* : the pipe.
+* : After executing this function, allocation in FIF0 becomes USB_HOST_PIPE0;
+* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt
+* : in the corresponding pipe becomes invalid. Sequence bit is also
+* : cleared.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_stop_transfer (uint16_t pipe)
+{
+ uint16_t usefifo;
+ uint32_t remain;
+
+ usb0_host_set_pid_nak(pipe);
+
+ usefifo = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ remain = Userdef_USB_usb0_host_stop_dma0();
+ usb0_host_dma_stop_d0(pipe, remain);
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ remain = Userdef_USB_usb0_host_stop_dma1();
+ usb0_host_dma_stop_d1(pipe, remain);
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ default:
+ usb0_host_clear_transaction_counter(pipe);
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+ }
+
+ /* Interrupt of pipe set is disabled */
+ usb0_host_disable_brdy_int(pipe);
+ usb0_host_disable_nrdy_int(pipe);
+ usb0_host_disable_bemp_int(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb0_host_aclrm(pipe);
+#endif
+ usb0_host_set_csclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_dfacc_d0
+* Description : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb0_host_set_dfacc_d0 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+
+ return dfacc;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_dfacc_d1
+* Description : Sets the DFACC setting value in D1FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb0_host_set_dfacc_d1 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB200.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+
+ return dfacc;
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dma.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dma.c
new file mode 100644
index 000000000..57e6e5a08
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_dma.c
@@ -0,0 +1,355 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_dma.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+/* #include "usb0_host_dmacdrv.h" */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static void usb0_host_dmaint(uint16_t fifo);
+static void usb0_host_dmaint_buf2fifo(uint16_t pipe);
+static void usb0_host_dmaint_fifo2buf(uint16_t pipe);
+
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_stop_d0
+* Description : D0FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_stop_d0 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB200.D0FBCFG,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb0_host_DmaInfo[USB_HOST_D0FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ buffer = USB200.D0FIFOCTR;
+ dtln = (buffer & USB_HOST_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain);
+ g_usb0_host_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB200.D0FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_stop_d1
+* Description : D1FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_stop_d1 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB200.D1FBCFG,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb0_host_DmaInfo[USB_HOST_D1FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ buffer = USB200.D1FIFOCTR;
+ dtln = (buffer & USB_HOST_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb0_host_PipeDataSize[pipe] = (g_usb0_host_data_count[pipe] - remain);
+ g_usb0_host_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB200.D1FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_interrupt_d0fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb1_host_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_HOST_D0FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_interrupt_d0fifo (uint32_t int_sense)
+{
+ usb0_host_dmaint(USB_HOST_D0FIFO);
+ g_usb0_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dma_interrupt_d1fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb0_host_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_HOST_D1FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_dma_interrupt_d1fifo (uint32_t int_sense)
+{
+ usb0_host_dmaint(USB_HOST_D1FIFO);
+ g_usb0_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint
+* Description : This function is DMA transfer end interrupt
+* Arguments : uint16_t fifo ; fifo number
+* : ; USB_HOST_D0FIFO
+* : ; USB_HOST_D1FIFO
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint (uint16_t fifo)
+{
+ uint16_t pipe;
+
+ pipe = g_usb0_host_DmaPipe[fifo];
+
+ if (g_usb0_host_DmaInfo[fifo].dir == USB_HOST_BUF2FIFO)
+ {
+ usb0_host_dmaint_buf2fifo(pipe);
+ }
+ else
+ {
+ usb0_host_dmaint_fifo2buf(pipe);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint_fifo2buf
+* Description : Executes read completion from FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint_fifo2buf (uint16_t pipe)
+{
+ uint32_t remain;
+ uint16_t useport;
+
+ if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ if (useport == USB_HOST_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb0_host_stop_dma0();
+ usb0_host_dma_stop_d0(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] == USB_HOST_DMA_BUSYEND)
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ else
+ {
+ usb0_host_enable_brdy_int(pipe);
+ }
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb0_host_stop_dma1();
+ usb0_host_dma_stop_d1(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] == USB_HOST_DMA_BUSYEND)
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ else
+ {
+ usb0_host_enable_brdy_int(pipe);
+ }
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_dmaint_buf2fifo
+* Description : Executes write completion in FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_dmaint_buf2fifo (uint16_t pipe)
+{
+ uint16_t useport;
+ uint32_t remain;
+
+ useport = (uint16_t)(g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ if (useport == USB_HOST_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb0_host_stop_dma0();
+ usb0_host_dma_stop_d0(pipe, remain);
+
+ if (g_usb0_host_DmaBval[USB_HOST_D0FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D0FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb0_host_stop_dma1();
+ usb0_host_dma_stop_d1(pipe, remain);
+
+ if (g_usb0_host_DmaBval[USB_HOST_D1FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB200.D1FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+
+ usb0_host_enable_bemp_int(pipe);
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_intrn.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_intrn.c
new file mode 100644
index 000000000..0dbce8e91
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_intrn.c
@@ -0,0 +1,285 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_intrn.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_brdy_int
+* Description : Executes BRDY interrupt(USB_HOST_PIPE1-9).
+* : According to the pipe that interrupt is generated in,
+* : reads/writes buffer allocated in the pipe.
+* : This function is executed in the BRDY interrupt handler.
+* : This function clears BRDY interrupt status and BEMP interrupt
+* : status.
+* Arguments : uint16_t status ; BRDYSTS Register Value
+* : uint16_t int_enb ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_brdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint32_t int_sense = 0;
+ uint16_t pipe;
+ uint16_t pipebit;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ pipebit = g_usb0_host_bit_set[pipe];
+
+ if ((status & pipebit) && (int_enb & pipebit))
+ {
+ USB200.BRDYSTS = (uint16_t)~pipebit;
+ USB200.BEMPSTS = (uint16_t)~pipebit;
+
+ if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+ {
+ if (g_usb0_host_DmaStatus[USB_HOST_D0FIFO] != USB_HOST_DMA_READY)
+ {
+ usb0_host_dma_interrupt_d0fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb0_host_read_dma(pipe);
+ usb0_host_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB200.D0FIFOCTR = USB_HOST_BITBCLR;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ }
+ else if ((g_usb0_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_DMA)
+ {
+ if (g_usb0_host_DmaStatus[USB_HOST_D1FIFO] != USB_HOST_DMA_READY)
+ {
+ usb0_host_dma_interrupt_d1fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb0_host_read_dma(pipe);
+ usb0_host_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB200.D1FIFOCTR = USB_HOST_BITBCLR;
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+ {
+ usb0_host_read_buffer(pipe);
+ }
+ else
+ {
+ usb0_host_write_buffer(pipe);
+ }
+ }
+#if(1) /* ohci_wrapp */
+ switch (g_usb0_host_pipe_status[pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+ break;
+ case USB_HOST_PIPE_NORES:
+ case USB_HOST_PIPE_STALL:
+ case USB_HOST_PIPE_ERROR:
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+ break;
+ default:
+ /* Do Nothing */
+ break;
+ }
+#endif
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_nrdy_int
+* Description : Executes NRDY interrupt(USB_HOST_PIPE1-9).
+* : Checks NRDY interrupt cause by PID. When the cause if STALL,
+* : regards the pipe state as STALL and ends the processing.
+* : Then the cause is not STALL, increments the error count to
+* : communicate again. When the error count is 3, determines
+* : the pipe state as USB_HOST_PIPE_NORES and ends the processing.
+* : This function is executed in the NRDY interrupt handler.
+* : This function clears NRDY interrupt status.
+* Arguments : uint16_t status ; NRDYSTS Register Value
+* : uint16_t int_enb ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_nrdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB200.NRDYSTS = (uint16_t)~status;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe])
+ {
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM) == 1)
+ {
+ if (g_usb0_host_pipe_status[pipe] == USB_HOST_PIPE_WAIT)
+ {
+ pid = usb0_host_get_pid(pipe);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_DEVICENOTRESPONDING);
+#else
+ g_usb0_host_PipeIgnore[pipe]++;
+
+ if (g_usb0_host_PipeIgnore[pipe] == 3)
+ {
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+ }
+ else
+ {
+ usb0_host_set_pid_buf(pipe);
+ }
+#endif
+ }
+ }
+ }
+ else
+ {
+ /* USB Function */
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_bemp_int
+* Description : Executes BEMP interrupt(USB_HOST_PIPE1-9).
+* Arguments : uint16_t status ; BEMPSTS Register Value
+* : uint16_t int_enb ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_bemp_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+ uint16_t inbuf;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB200.BEMPSTS = (uint16_t)~status;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb0_host_bit_set[pipe]) == g_usb0_host_bit_set[pipe])
+ {
+ pid = usb0_host_get_pid(pipe);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+ inbuf = usb0_host_get_inbuf(pipe);
+
+ if (inbuf == 0)
+ {
+ usb0_host_disable_bemp_int(pipe);
+ usb0_host_set_pid_nak(pipe);
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+#endif
+ }
+ }
+ }
+ }
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_lib.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_lib.c
new file mode 100644
index 000000000..eb3359e28
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/common/usb0_host_lib.c
@@ -0,0 +1,1580 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_lib.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#if(1) /* ohci_wrapp */
+#include "MBRZA1H.h" /* INTC Driver Header */
+#else
+#include "devdrv_intc.h" /* INTC Driver Header */
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_brdy_int
+* Description : Enables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_brdy_int (uint16_t pipe)
+{
+ /* enable brdy interrupt */
+ USB200.BRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_brdy_int
+* Description : Disables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_brdy_int (uint16_t pipe)
+{
+ /* disable brdy interrupt */
+ USB200.BRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_brdy_sts
+* Description : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_brdy_sts (uint16_t pipe)
+{
+ /* clear brdy status */
+ USB200.BRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_bemp_int
+* Description : Enables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_bemp_int (uint16_t pipe)
+{
+ /* enable bemp interrupt */
+ USB200.BEMPENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_bemp_int
+* Description : Disables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_bemp_int (uint16_t pipe)
+{
+ /* disable bemp interrupt */
+ USB200.BEMPENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_bemp_sts
+* Description : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_bemp_sts (uint16_t pipe)
+{
+ /* clear bemp status */
+ USB200.BEMPSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_nrdy_int
+* Description : Enables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : NRDY. Enables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_enable_nrdy_int (uint16_t pipe)
+{
+ /* enable nrdy interrupt */
+ USB200.NRDYENB |= (uint16_t)g_usb0_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_disable_nrdy_int
+* Description : Disables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : NRDY. Disables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_disable_nrdy_int (uint16_t pipe)
+{
+ /* disable nrdy interrupt */
+ USB200.NRDYENB &= (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_nrdy_sts
+* Description : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_nrdy_sts (uint16_t pipe)
+{
+ /* clear nrdy status */
+ USB200.NRDYSTS = (uint16_t)~(g_usb0_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_is_hispeed
+* Description : Returns the result of USB reset hand shake (RHST) as
+* : return value.
+* Arguments : none
+* Return Value : USB_HOST_HIGH_SPEED ; Hi-Speed
+* : USB_HOST_FULL_SPEED ; Full-Speed
+* : USB_HOST_LOW_SPEED ; Low-Speed
+* : USB_HOST_NON_SPEED ; error
+*******************************************************************************/
+uint16_t usb0_host_is_hispeed (void)
+{
+ uint16_t rhst;
+ uint16_t speed;
+
+ rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (rhst == USB_HOST_HSMODE)
+ {
+ speed = USB_HOST_HIGH_SPEED;
+ }
+ else if (rhst == USB_HOST_FSMODE)
+ {
+ speed = USB_HOST_FULL_SPEED;
+ }
+ else if (rhst == USB_HOST_LSMODE)
+ {
+ speed = USB_HOST_LOW_SPEED;
+ }
+ else
+ {
+ speed = USB_HOST_NON_SPEED;
+ }
+
+ return speed;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_is_hispeed_enable
+* Description : Returns the USB High-Speed connection enabled status as
+* : return value.
+* Arguments : none
+* Return Value : USB_HOST_YES : Hi-Speed Enable
+* : USB_HOST_NO : Hi-Speed Disable
+*******************************************************************************/
+uint16_t usb0_host_is_hispeed_enable (void)
+{
+ uint16_t ret;
+
+ ret = USB_HOST_NO;
+
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE) == 1)
+ {
+ ret = USB_HOST_YES;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_buf
+* Description : Enables communicaqtion in the pipe specified by the argument
+* : (BUF).
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_buf (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb0_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_STALL2)
+ {
+ usb0_host_set_pid_nak(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ USB_HOST_PID_BUF,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_nak
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* : When the pipe status was enabling communication (BUF) before
+* : executing before executing this function, waits in the software
+* : until the pipe becomes ready after setting disabled.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_nak (uint16_t pipe)
+{
+ uint16_t pid;
+ uint16_t pbusy;
+ uint32_t loop;
+
+ pid = usb0_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_STALL2)
+ {
+ usb0_host_set_pid_stall(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ USB_HOST_PID_NAK,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+
+ if (pid == USB_HOST_PID_BUF)
+ {
+ for (loop = 0; loop < 200; loop++)
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ pbusy = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_PBUSY_SHIFT,
+ USB_DCPCTR_PBUSY);
+ break;
+
+ case USB_HOST_PIPE1:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE2:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE3:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE4:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE5:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE6:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE7:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE8:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE9:
+ pbusy = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_PBUSY_SHIFT,
+ USB_PIPEnCTR_9_PBUSY);
+ break;
+
+ default:
+ pbusy = 1;
+ break;
+ }
+
+ if (pbusy == 0)
+ {
+ break;
+ }
+
+ Userdef_USB_usb0_host_delay_500ns();
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_pid_stall
+* Description : Disables communication (STALL) in the pipe specified by the
+* : argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_pid_stall (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb0_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_BUF)
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ USB_HOST_PID_STALL2,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ USB_HOST_PID_STALL,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clear_pid_stall
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clear_pid_stall (uint16_t pipe)
+{
+ usb0_host_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_pid
+* Description : Returns the pipe state specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb0_host_get_pid (uint16_t pipe)
+{
+ uint16_t pid;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ pid = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ pid = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ pid = 0;
+ break;
+ }
+
+ return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_csclr
+* Description : CSPLIT status clear setting of sprit transaction in specified
+* : pipe is performed.
+* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+* : in DCPCTR register are continuously changed (when the sequence
+* : toggle bit of data PID is continuously changed over two or more pipes),
+* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+* : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+* : In addition, both bits should be operated after PID is set to NAK.
+* : However, when it is set to the isochronous transfer as the transfer type
+* : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_csclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_CSCLR_SHIFT,
+ USB_DCPCTR_CSCLR);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_CSCLR_SHIFT,
+ USB_PIPEnCTR_9_CSCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_sqclr
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA0.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_sqclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_SQCLR_SHIFT,
+ USB_DCPCTR_SQCLR);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQCLR_SHIFT,
+ USB_PIPEnCTR_9_SQCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_sqset
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA1.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_sqset (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB200.DCPCTR,
+ 1,
+ USB_DCPCTR_SQSET_SHIFT,
+ USB_DCPCTR_SQSET);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQSET_SHIFT,
+ USB_PIPEnCTR_9_SQSET);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_sqmon
+* Description : Toggle bit of specified pipe is obtained
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : sqmon
+*******************************************************************************/
+uint16_t usb0_host_get_sqmon (uint16_t pipe)
+{
+ uint16_t sqmon;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ sqmon = RZA_IO_RegRead_16(&USB200.DCPCTR,
+ USB_DCPCTR_SQMON_SHIFT,
+ USB_DCPCTR_SQMON);
+ break;
+
+ case USB_HOST_PIPE1:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE2:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE3:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE4:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE5:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE6:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE6CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE7:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE7CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE8:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE8CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE9:
+ sqmon = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_SQMON_SHIFT,
+ USB_PIPEnCTR_9_SQMON);
+ break;
+
+ default:
+ sqmon = 0;
+ break;
+ }
+
+ return sqmon;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_aclrm
+* Description : The buffer of specified pipe is initialized
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_aclrm (uint16_t pipe)
+{
+ usb0_host_set_aclrm(pipe);
+ usb0_host_clr_aclrm(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_clr_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb0_host_clr_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB200.PIPE1CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB200.PIPE2CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB200.PIPE3CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB200.PIPE4CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB200.PIPE5CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB200.PIPE6CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB200.PIPE7CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB200.PIPE8CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB200.PIPE9CTR,
+ 0,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_inbuf
+* Description : Returns INBUFM of the pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : inbuf
+*******************************************************************************/
+uint16_t usb0_host_get_inbuf (uint16_t pipe)
+{
+ uint16_t inbuf;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE1:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE1CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE2:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE2CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE3:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE3CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE4:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE4CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE5:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE5CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE6:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE7:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE8:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE9:
+ inbuf = RZA_IO_RegRead_16(&USB200.PIPE9CTR,
+ USB_PIPEnCTR_9_INBUFM_SHIFT,
+ USB_PIPEnCTR_9_INBUFM);
+ break;
+
+ default:
+ inbuf = 0;
+ break;
+ }
+
+ return inbuf;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_setting_interrupt
+* Description : Sets the USB module interrupt level.
+* Arguments : uint8_t level ; interrupt level
+* Return Value : none
+*******************************************************************************/
+void usb0_host_setting_interrupt (uint8_t level)
+{
+#if(1) /* ohci_wrapp */
+ IRQn_Type d0fifo_dmaintid;
+ IRQn_Type d1fifo_dmaintid;
+
+ InterruptHandlerRegister(USBI0_IRQn, usb0_host_interrupt);
+ GIC_SetPriority(USBI0_IRQn, level);
+ GIC_EnableIRQ(USBI0_IRQn);
+
+ d0fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d0fifo_dmaintid();
+
+ if (d0fifo_dmaintid != 0xFFFF)
+ {
+ InterruptHandlerRegister(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo);
+ GIC_SetPriority(d0fifo_dmaintid, level);
+ GIC_EnableIRQ(d0fifo_dmaintid);
+ }
+
+ d1fifo_dmaintid = (IRQn_Type)Userdef_USB_usb0_host_d1fifo_dmaintid();
+
+ if (d1fifo_dmaintid != 0xFFFF)
+ {
+ InterruptHandlerRegister(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo);
+ GIC_SetPriority(d1fifo_dmaintid, level);
+ GIC_EnableIRQ(d1fifo_dmaintid);
+ }
+#else
+ uint16_t d0fifo_dmaintid;
+ uint16_t d1fifo_dmaintid;
+
+ R_INTC_RegistIntFunc(INTC_ID_USBI0, usb0_host_interrupt);
+ R_INTC_SetPriority(INTC_ID_USBI0, level);
+ R_INTC_Enable(INTC_ID_USBI0);
+
+ d0fifo_dmaintid = Userdef_USB_usb0_host_d0fifo_dmaintid();
+
+ if (d0fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d0fifo_dmaintid, usb0_host_dma_interrupt_d0fifo);
+ R_INTC_SetPriority(d0fifo_dmaintid, level);
+ R_INTC_Enable(d0fifo_dmaintid);
+ }
+
+ d1fifo_dmaintid = Userdef_USB_usb0_host_d1fifo_dmaintid();
+
+ if (d1fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d1fifo_dmaintid, usb0_host_dma_interrupt_d1fifo);
+ R_INTC_SetPriority(d1fifo_dmaintid, level);
+ R_INTC_Enable(d1fifo_dmaintid);
+ }
+#endif
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_reset_module
+* Description : Initializes the USB module.
+* : Enables providing clock to the USB module.
+* : Sets USB bus wait register.
+* Arguments : uint16_t clockmode ; 48MHz ; USBHCLOCK_X1_48MHZ
+* : ; 12MHz ; USBHCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+void usb0_host_reset_module (uint16_t clockmode)
+{
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_UPLLE_SHIFT,
+ USB_SYSCFG_UPLLE) == 1)
+ {
+ if ((USB200.SYSCFG0 & USB_HOST_BITUCKSEL) != clockmode)
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+ Userdef_USB_usb0_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ Userdef_USB_usb0_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+ Userdef_USB_usb0_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+
+ USB200.BUSWAIT = (uint16_t)(USB_HOST_BUSWAIT_05 & USB_HOST_BITBWAIT);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_buf_size
+* Description : Obtains pipe buffer size specified by the argument and
+* : maximum packet size of the USB device in use.
+* : When USB_HOST_PIPE0 is specified by the argument, obtains the maximum
+* : packet size of the USB device using the corresponding pipe.
+* : For the case that USB_HOST_PIPE0 is not assigned by the argument, when the
+* : corresponding pipe is in continuous transfer mode,
+* : obtains the buffer size allocated in the corresponcing pipe,
+* : when incontinuous transfer, obtains maximum packet size.
+* Arguments : uint16_t ; pipe Number
+* Return Value : Maximum packet size or buffer size
+*******************************************************************************/
+uint16_t usb0_host_get_buf_size (uint16_t pipe)
+{
+ uint16_t size;
+ uint16_t bufsize;
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1)
+ {
+ bufsize = RZA_IO_RegRead_16(&g_usb0_host_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE);
+ size = (uint16_t)((bufsize + 1) * USB_HOST_PIPExBUF);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+ }
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_mxps
+* Description : Obtains maximum packet size of the USB device using the pipe
+* : specified by the argument.
+* Arguments : uint16_t ; Pipe Number
+* Return Value : Max Packet Size
+*******************************************************************************/
+uint16_t usb0_host_get_mxps (uint16_t pipe)
+{
+ uint16_t size;
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+
+ return size;
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_controlrw.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_controlrw.c
new file mode 100644
index 000000000..2f8ef12a3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_controlrw.c
@@ -0,0 +1,434 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_controlrw.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlTransStart
+* Description : Executes USB control transfer.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* : uint8_t *Buf ; Data buffer
+* Return Value : DEVDRV_SUCCESS ; SUCCESS
+* : DEVDRV_ERROR ; ERROR
+*******************************************************************************/
+int32_t usb0_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val,
+ uint16_t Indx, uint16_t Len, uint8_t * Buf)
+{
+ if (g_usb0_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED)
+ {
+ RZA_IO_RegWrite_16(&USB200.SOFCFG,
+ 1,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SOFCFG,
+ 0,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+
+ USB200.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb0_host_default_max_packet[devadr]);
+
+ if (g_usb0_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE)
+ {
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ g_usb0_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
+
+ if (Len == 0)
+ {
+ g_usb0_host_CmdStage |= USB_HOST_MODE_NO_DATA; /* No-data Control */
+ }
+ else
+ {
+ if ((Req & 0x0080) != 0)
+ {
+ g_usb0_host_CmdStage |= USB_HOST_MODE_READ; /* Control Read */
+ }
+ else
+ {
+ g_usb0_host_CmdStage |= USB_HOST_MODE_WRITE; /* Control Write */
+ }
+ }
+
+ g_usb0_host_SavReq = Req; /* save request */
+ g_usb0_host_SavVal = Val;
+ g_usb0_host_SavIndx = Indx;
+ g_usb0_host_SavLen = Len;
+ }
+ else
+ {
+ if ((g_usb0_host_SavReq != Req) || (g_usb0_host_SavVal != Val)
+ || (g_usb0_host_SavIndx != Indx) || (g_usb0_host_SavLen != Len))
+ {
+ return DEVDRV_ERROR;
+ }
+ }
+
+ switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ /* --------------- SETUP STAGE --------------- */
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE):
+ usb0_host_SetupStage(Req, Val, Indx, Len);
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE): /* goto next stage */
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_WRITE:
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA;
+ break;
+
+ case USB_HOST_MODE_READ:
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_DATA;
+ break;
+
+ case USB_HOST_MODE_NO_DATA:
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ break;
+
+ default:
+ break;
+ }
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES):
+ if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+ }
+ break;
+
+ /* --------------- DATA STAGE --------------- */
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE):
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_WRITE:
+ usb0_host_CtrlWriteStart((uint32_t)Len, Buf);
+ break;
+
+ case USB_HOST_MODE_READ:
+ usb0_host_CtrlReadStart((uint32_t)Len, Buf);
+ break;
+
+ default:
+ break;
+ }
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE): /* goto next stage */
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES):
+ if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+ usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb0_host_set_pid_buf(USB_HOST_PIPE0);
+ }
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL):
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ break;
+
+ /* --------------- STATUS STAGE --------------- */
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE):
+ usb0_host_StatusStage();
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE): /* end of Control transfer */
+ usb0_host_set_pid_nak(USB_HOST_PIPE0);
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE; /* exit DONE */
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES):
+ if (g_usb0_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb0_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+ usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb0_host_set_pid_buf(USB_HOST_PIPE0);
+ }
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL):
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ break;
+
+ default:
+ break;
+ }
+
+ if (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)
+ {
+ RZA_IO_RegWrite_16(&USB200.SOFCFG,
+ 0,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_SetupStage
+* Description : Executes USB control transfer/set up stage.
+* Arguments : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* Return Value : none
+*******************************************************************************/
+void usb0_host_SetupStage (uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len)
+{
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ USB200.INTSTS1 = (uint16_t)~(USB_HOST_BITSACK | USB_HOST_BITSIGN); /* Status Clear */
+ USB200.USBREQ = Req;
+ USB200.USBVAL = Val;
+ USB200.USBINDX = Indx;
+ USB200.USBLENG = Len;
+ USB200.DCPCTR = USB_HOST_BITSUREQ; /* PID=NAK & Send Setup */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_StatusStage
+* Description : Executes USB control transfer/status stage.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_StatusStage (void)
+{
+ uint8_t Buf1[16];
+
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_READ:
+ usb0_host_CtrlWriteStart((uint32_t)0, (uint8_t *)&Buf1);
+ break;
+
+ case USB_HOST_MODE_WRITE:
+ usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1);
+ break;
+
+ case USB_HOST_MODE_NO_DATA:
+ usb0_host_CtrlReadStart((uint32_t)0, (uint8_t *)&Buf1);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlWriteStart
+* Description : Executes USB control transfer/data stage(write).
+* Arguments : uint32_t Bsize ; Data Size
+* : uint8_t *Table ; Data Table Address
+* Return Value : USB_HOST_WRITESHRT ; End of data write
+* : USB_HOST_WRITEEND ; End of data write (not null)
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_FIFOERROR ; FIFO access error
+*******************************************************************************/
+uint16_t usb0_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table)
+{
+ uint16_t EndFlag_K;
+ uint16_t mbw;
+
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ usb0_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */
+ g_usb0_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */
+ g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */
+
+ USB200.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+ Userdef_USB_usb0_host_delay_10us(3);
+#endif
+ RZA_IO_RegWrite_16(&USB200.DCPCFG,
+ 1,
+ USB_DCPCFG_DIR_SHIFT,
+ USB_DCPCFG_DIR);
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw);
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+
+ usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+ EndFlag_K = usb0_host_write_buffer_c(USB_HOST_PIPE0);
+ /* Host Control sequence */
+ switch (EndFlag_K)
+ {
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb0_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_WRITEEND: /* End of data write (not null) */
+ case USB_HOST_WRITING: /* Continue of data write */
+ usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb0_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ break;
+
+ default:
+ break;
+ }
+ usb0_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */
+ return (EndFlag_K); /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CtrlReadStart
+* Description : Executes USB control transfer/data stage(read).
+* Arguments : uint32_t Bsize ; Data Size
+* : uint8_t *Table ; Data Table Address
+* Return Value : none
+*******************************************************************************/
+void usb0_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table)
+{
+ uint16_t mbw;
+
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ usb0_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */
+ g_usb0_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */
+ g_usb0_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */
+
+ USB200.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+ Userdef_USB_usb0_host_delay_10us(3);
+#endif
+ RZA_IO_RegWrite_16(&USB200.DCPCFG,
+ 0,
+ USB_DCPCFG_DIR_SHIFT,
+ USB_DCPCFG_DIR);
+
+ mbw = usb0_host_get_mbw(g_usb0_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb0_host_data_pointer[USB_HOST_PIPE0]);
+ usb0_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw);
+ USB200.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+
+ usb0_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb0_host_enable_brdy_int(USB_HOST_PIPE0); /* Ok */
+ usb0_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb0_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_drv_api.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_drv_api.c
new file mode 100644
index 000000000..baa39adaa
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_drv_api.c
@@ -0,0 +1,889 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_drv_api.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_resetEP(USB_HOST_CFG_PIPETBL_t *tbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_api_host_init
+* Description : Initializes USB module in the USB host mode.
+* : USB connection is executed when executing this function in
+* : the states that USB device isconnected to the USB port.
+* Arguments : uint8_t int_level : USB Module interrupt level
+* : USBU16 mode : USB_HOST_HIGH_SPEED
+* : USB_HOST_FULL_SPEED
+* : uint16_t clockmode : USB Clock mode
+* Return Value : USB detach or attach
+* : USB_HOST_ATTACH
+* : USB_HOST_DETACH
+*******************************************************************************/
+uint16_t usb0_api_host_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
+{
+ uint16_t connect;
+ volatile uint8_t dummy_buf;
+
+ CPG.STBCR7 &= 0xfd; /*The clock of USB0 modules is permitted */
+ dummy_buf = CPG.STBCR7; /* (Dummy read) */
+
+ g_usb0_host_SupportUsbDeviceSpeed = mode;
+
+ usb0_host_setting_interrupt(int_level);
+ usb0_host_reset_module(clockmode);
+
+ g_usb0_host_bchg_flag = USB_HOST_NO;
+ g_usb0_host_detach_flag = USB_HOST_NO;
+ g_usb0_host_attach_flag = USB_HOST_NO;
+
+ g_usb0_host_driver_state = USB_HOST_DRV_DETACHED;
+ g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+ usb0_host_InitModule();
+
+ connect = usb0_host_CheckAttach();
+
+ if (connect == USB_HOST_ATTACH)
+ {
+ g_usb0_host_attach_flag = USB_HOST_YES;
+ }
+ else
+ {
+ usb0_host_UsbDetach2();
+ }
+
+ return connect;
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb0_api_host_enumeration
+* Description : Initializes USB module in the USB host mode.
+* : USB connection is executed when executing this function in
+* : the states that USB device isconnected to the USB port.
+* Arguments : uint16_t devadr : device address
+* Return Value : DEVDRV_USBH_DETACH_ERR : device detach
+* : DEVDRV_SUCCESS : device enumeration success
+* : DEVDRV_ERROR : device enumeration error
+*******************************************************************************/
+int32_t usb0_api_host_enumeration (uint16_t devadr)
+{
+ int32_t ret;
+ uint16_t driver_sts;
+
+ g_usb0_host_setUsbAddress = devadr;
+
+ while (1)
+ {
+ driver_sts = usb0_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ ret = DEVDRV_USBH_DETACH_ERR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+ {
+ ret = DEVDRV_SUCCESS;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_STALL)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+
+ if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ while (1)
+ {
+ driver_sts = usb0_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_detach
+* Description : USB detach routine
+* Arguments : none
+* Return Value : USB_HOST_DETACH : USB detach
+* : USB_HOST_ATTACH : USB attach
+* : DEVDRV_ERROR : error
+*******************************************************************************/
+int32_t usb0_api_host_detach (void)
+{
+ int32_t ret;
+ uint16_t driver_sts;
+
+ while (1)
+ {
+ driver_sts = usb0_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ ret = USB_HOST_DETACH;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+ {
+ ret = USB_HOST_ATTACH;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_STALL)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+
+ if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ while (1)
+ {
+ driver_sts = usb0_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_data_in
+* Description : Executes USB transfer as data-in in the argument specified pipe.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Pipe ; Pipe Number
+* : uint32_t Size ; Data Size
+* : uint8_t *data_buf ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_in (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+ int32_t ret;
+
+ if (Pipe == USB_HOST_PIPE0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 1)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+ {
+ usb0_host_start_receive_transfer(Pipe, Size, data_buf);
+ }
+ else
+ {
+ return DEVDRV_ERROR; /* Now pipe is busy */
+ }
+
+ /* waiting for completing routine */
+ do
+ {
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+
+ } while (1);
+
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb0_host_pipe_status[Pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ usb0_host_stop_transfer(Pipe);
+
+ g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_data_out
+* Description : Executes USB transfer as data-out in the argument specified pipe.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Pipe ; Pipe Number
+* : uint32_t Size ; Data Size
+* : uint8_t *data_buf ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_out (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+ int32_t ret;
+
+ if (Pipe == USB_HOST_PIPE0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb0_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (g_usb0_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+ {
+ usb0_host_start_send_transfer(Pipe, Size, data_buf);
+ }
+ else
+ {
+ return DEVDRV_ERROR; /* Now pipe is busy */
+ }
+
+ /* waiting for completing routine */
+ do
+ {
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb0_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+
+ } while (1);
+
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb0_host_pipe_status[Pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ usb0_host_stop_transfer(Pipe);
+
+ g_usb0_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_control_transfer
+* Description : Executes USB control transfer.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* : uint8_t *buf ; Buffer
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_USBH_DETACH_ERR ; device detach
+* : DEVDRV_USBH_CTRL_COM_ERR ; device no response
+* : DEVDRV_USBH_STALL ; STALL
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_control_transfer (uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx,
+ uint16_t Len, uint8_t * Buf)
+{
+ int32_t ret;
+
+ do
+ {
+ ret = usb0_host_CtrlTransStart(devadr, Req, Val, Indx, Len, Buf);
+
+ if (ret == DEVDRV_SUCCESS)
+ {
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_IDLE)
+ && (g_usb0_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+ }
+ else
+ {
+ return DEVDRV_ERROR;
+ }
+ } while (1);
+
+ if (g_usb0_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb0_host_pipe_status[USB_HOST_PIPE0])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_CTRL_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_set_endpoint
+* Description : Sets end point on the information specified in the argument.
+* Arguments : uint16_t devadr ; device address
+* : uint8_t *configdescriptor ; device configration descriptor
+* : USB_HOST_CFG_PIPETBL_t *user_table ; pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_set_endpoint (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * configdescriptor)
+{
+ uint16_t ret;
+ uint32_t end_point;
+ uint32_t offset;
+ uint32_t totalLength;
+ USB_HOST_CFG_PIPETBL_t * pipe_table;
+
+ /* End Point Search */
+ end_point = 0;
+ offset = configdescriptor[0];
+ totalLength = (uint16_t)(configdescriptor[2] + ((uint16_t)configdescriptor[3] << 8));
+
+ do
+ {
+ if (configdescriptor[offset + 1] == USB_HOST_ENDPOINT_DESC)
+ {
+ pipe_table = &user_table[end_point];
+
+ if (pipe_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+
+ ret = usb0_api_host_SetEndpointTable(devadr, pipe_table, (uint8_t *)&configdescriptor[offset]);
+
+ if ((ret != USB_HOST_PIPE_IN) && (ret != USB_HOST_PIPE_OUT))
+ {
+ return DEVDRV_ERROR;
+ }
+
+ ++end_point;
+ }
+
+ /* Next End Point Search */
+ offset += configdescriptor[offset];
+
+ } while (offset < totalLength);
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_clear_endpoint
+* Description : Clears the pipe definition table specified in the argument.
+* Arguments : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_clear_endpoint (USB_HOST_CFG_PIPETBL_t * user_table)
+{
+ uint16_t pipe;
+
+ for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+ {
+ if (user_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+ user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+ user_table->pipe_max_pktsize = 0;
+ user_table->pipe_cycle = 0;
+
+ user_table++;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_api_host_clear_endpoint_pipe
+* Description : Clears the pipe definition table specified in the argument.
+* Arguments : uint16_t pipe_sel : Pipe Number
+* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_clear_endpoint_pipe (uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t * user_table)
+{
+ uint16_t pipe;
+
+ for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+ {
+ if (user_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+
+ if (user_table->pipe_number == pipe_sel)
+ {
+ user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+ user_table->pipe_max_pktsize = 0;
+ user_table->pipe_cycle = 0;
+ break;
+ }
+
+ user_table++;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb0_api_host_SetEndpointTable
+* Description : Sets the end point on the information specified by the argument.
+* Arguments : uint16_t devadr : device address
+* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* : uint8_t *Table : Endpoint descriptor
+* Return Value : USB_HOST_DIR_H_IN ; IN endpoint
+* : USB_HOST_DIR_H_OUT ; OUT endpoint
+* : USB_END_POINT_ERROR ; error
+*******************************************************************************/
+uint16_t usb0_api_host_SetEndpointTable (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * Table)
+{
+ uint16_t PipeCfg;
+ uint16_t PipeMaxp;
+ uint16_t pipe_number;
+ uint16_t ret;
+ uint16_t ret_flag = 0; // avoid warning.
+
+ pipe_number = user_table->pipe_number;
+
+ if (Table[1] != USB_HOST_ENDPOINT_DESC)
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ switch (Table[3] & USB_HOST_EP_TYPE)
+ {
+ case USB_HOST_EP_CNTRL:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+
+ case USB_HOST_EP_ISO:
+ if ((pipe_number != USB_HOST_PIPE1) && (pipe_number != USB_HOST_PIPE2))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_ISO;
+ break;
+
+ case USB_HOST_EP_BULK:
+ if ((pipe_number < USB_HOST_PIPE1) || (pipe_number > USB_HOST_PIPE5))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_BULK;
+ break;
+
+ case USB_HOST_EP_INT:
+ if ((pipe_number < USB_HOST_PIPE6) || (pipe_number > USB_HOST_PIPE9))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_INTERRUPT;
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+
+ /* Set pipe configuration table */
+ if ((Table[2] & USB_HOST_EP_DIR_MASK) == USB_HOST_EP_IN) /* IN(receive) */
+ {
+ if (PipeCfg == USB_HOST_ISO)
+ {
+ /* Transfer Type is ISO*/
+ PipeCfg |= USB_HOST_DIR_H_IN;
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ case USB_HOST_D0USE:
+ case USB_HOST_D1USE:
+ case USB_HOST_D0DMA:
+ case USB_HOST_D1DMA:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+ }
+ else
+ {
+ /* Transfer Type is BULK or INT */
+ PipeCfg |= (USB_HOST_SHTNAKON | USB_HOST_DIR_H_IN); /* Compulsory SHTNAK */
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ case USB_HOST_D0USE:
+ case USB_HOST_D1USE:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D1DMA:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+#ifdef __USB_DMA_BFRE_ENABLE__
+ /* this routine cannnot be perfomred if read operation is executed in buffer size */
+ PipeCfg |= USB_HOST_BFREON;
+#endif
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+ }
+ ret = USB_HOST_PIPE_IN;
+ }
+ else /* OUT(send) */
+ {
+ if (PipeCfg == USB_HOST_ISO)
+ {
+ /* Transfer Type is ISO*/
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+ }
+ else
+ {
+ /* Transfer Type is BULK or INT */
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+ }
+ PipeCfg |= USB_HOST_DIR_H_OUT;
+ ret = USB_HOST_PIPE_OUT;
+ }
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_CFIFO_USE;
+ break;
+
+ case USB_HOST_D0USE:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_USE;
+ break;
+
+ case USB_HOST_D1USE:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_USE;
+ break;
+
+ case USB_HOST_D0DMA:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_DMA;
+ break;
+
+ case USB_HOST_D1DMA:
+ g_usb0_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_DMA;
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+
+ /* Endpoint number set */
+ PipeCfg |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+ g_usb0_host_PipeTbl[pipe_number] |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+
+ /* Max packet size set */
+ PipeMaxp = (uint16_t)((uint16_t)Table[4] | (uint16_t)((uint16_t)Table[5] << 8));
+
+ if (PipeMaxp == 0u)
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ /* Set device address */
+ PipeMaxp |= (uint16_t)(devadr << 12);
+
+ user_table->pipe_cfg = PipeCfg;
+ user_table->pipe_max_pktsize = PipeMaxp;
+
+ usb0_host_resetEP(user_table);
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_resetEP
+* Description : Sets the end point on the information specified by the argument.
+* Arguments : USB_HOST_CFG_PIPETBL_t *tbl : pipe table
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_resetEP (USB_HOST_CFG_PIPETBL_t * tbl)
+{
+
+ uint16_t pipe;
+
+ /* Host pipe */
+ /* The pipe number of pipe definition table is obtained */
+ pipe = (uint16_t)(tbl->pipe_number & USB_HOST_BITCURPIPE); /* Pipe Number */
+
+ /* FIFO port access pipe is set to initial value */
+ /* The connection with FIFO should be cut before setting the pipe */
+ if (RZA_IO_RegRead_16(&USB200.CFIFOSEL,
+ USB_CFIFOSEL_CURPIPE_SHIFT,
+ USB_CFIFOSEL_CURPIPE) == pipe)
+ {
+ usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ if (RZA_IO_RegRead_16(&USB200.D0FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ if (RZA_IO_RegRead_16(&USB200.D1FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ usb0_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ /* Interrupt of pipe set is disabled */
+ usb0_host_disable_brdy_int(pipe);
+ usb0_host_disable_nrdy_int(pipe);
+ usb0_host_disable_bemp_int(pipe);
+
+ /* Pipe to set is set to NAK */
+ usb0_host_set_pid_nak(pipe);
+
+ /* Pipe is set */
+ USB200.PIPESEL = pipe;
+
+ USB200.PIPECFG = tbl->pipe_cfg;
+ USB200.PIPEBUF = tbl->pipe_buf;
+ USB200.PIPEMAXP = tbl->pipe_max_pktsize;
+ USB200.PIPEPERI = tbl->pipe_cycle;
+
+ g_usb0_host_pipecfg[pipe] = tbl->pipe_cfg;
+ g_usb0_host_pipebuf[pipe] = tbl->pipe_buf;
+ g_usb0_host_pipemaxp[pipe] = tbl->pipe_max_pktsize;
+ g_usb0_host_pipeperi[pipe] = tbl->pipe_cycle;
+
+ /* Sequence bit clear */
+ usb0_host_set_sqclr(pipe);
+
+ usb0_host_aclrm(pipe);
+ usb0_host_set_csclr(pipe);
+
+ /* Pipe window selection is set to unused */
+ USB200.PIPESEL = USB_HOST_PIPE0;
+
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb0_api_host_data_count
+* Description : Get g_usb0_host_data_count[pipe]
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t *data_count ; return g_usb0_data_count[pipe]
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb0_api_host_data_count (uint16_t pipe, uint32_t * data_count)
+{
+ if (pipe > USB_HOST_MAX_PIPE_NO)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ *data_count = g_usb0_host_PipeDataSize[pipe];
+
+ return DEVDRV_SUCCESS;
+}
+#endif
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_global.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_global.c
new file mode 100644
index 000000000..2d1d5f5fc
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_global.c
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_global.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+const uint16_t g_usb0_host_bit_set[16] =
+{
+ 0x0001, 0x0002, 0x0004, 0x0008,
+ 0x0010, 0x0020, 0x0040, 0x0080,
+ 0x0100, 0x0200, 0x0400, 0x0800,
+ 0x1000, 0x2000, 0x4000, 0x8000
+};
+
+uint32_t g_usb0_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+uint8_t * g_usb0_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+uint16_t g_usb0_host_PipeIgnore[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_PipeTbl[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_pipe_status[USB_HOST_MAX_PIPE_NO + 1];
+uint32_t g_usb0_host_PipeDataSize[USB_HOST_MAX_PIPE_NO + 1];
+
+USB_HOST_DMA_t g_usb0_host_DmaInfo[2];
+
+uint16_t g_usb0_host_DmaPipe[2];
+uint16_t g_usb0_host_DmaBval[2];
+uint16_t g_usb0_host_DmaStatus[2];
+
+uint16_t g_usb0_host_driver_state;
+uint16_t g_usb0_host_ConfigNum;
+uint16_t g_usb0_host_CmdStage;
+uint16_t g_usb0_host_bchg_flag;
+uint16_t g_usb0_host_detach_flag;
+uint16_t g_usb0_host_attach_flag;
+
+uint16_t g_usb0_host_UsbAddress;
+uint16_t g_usb0_host_setUsbAddress;
+uint16_t g_usb0_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+uint16_t g_usb0_host_UsbDeviceSpeed;
+uint16_t g_usb0_host_SupportUsbDeviceSpeed;
+
+uint16_t g_usb0_host_SavReq;
+uint16_t g_usb0_host_SavVal;
+uint16_t g_usb0_host_SavIndx;
+uint16_t g_usb0_host_SavLen;
+
+uint16_t g_usb0_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb0_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_init_pipe_status
+* Description : Initialize pipe status.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_init_pipe_status (void)
+{
+ uint16_t loop;
+
+ g_usb0_host_ConfigNum = 0;
+
+ for (loop = 0; loop < (USB_HOST_MAX_PIPE_NO + 1); ++loop)
+ {
+ g_usb0_host_pipe_status[loop] = USB_HOST_PIPE_IDLE;
+ g_usb0_host_PipeDataSize[loop] = 0;
+
+ /* pipe configuration in usb0_host_resetEP() */
+ g_usb0_host_pipecfg[loop] = 0;
+ g_usb0_host_pipebuf[loop] = 0;
+ g_usb0_host_pipemaxp[loop] = 0;
+ g_usb0_host_pipeperi[loop] = 0;
+ }
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbint.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbint.c
new file mode 100644
index 000000000..f4e5a27c7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbint.c
@@ -0,0 +1,496 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_usbint.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_interrupt1(void);
+static void usb0_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb0_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb0_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_interrupt
+* Description : Executes USB interrupt.
+* : Register this function in the USB interrupt handler.
+* : Set CFIF0 in the pipe set before the interrupt after executing
+* : this function.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb0_host_interrupt (uint32_t int_sense)
+{
+ uint16_t savepipe1;
+ uint16_t savepipe2;
+ uint16_t buffer;
+
+ savepipe1 = USB200.CFIFOSEL;
+ savepipe2 = USB200.PIPESEL;
+ usb0_host_interrupt1();
+
+ /* Control transmission changes ISEL within interruption processing. */
+ /* For this reason, write return of ISEL cannot be performed. */
+ buffer = USB200.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE);
+ USB200.CFIFOSEL = buffer;
+ USB200.PIPESEL = savepipe2;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_interrupt1
+* Description : Execue the USB interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_interrupt1 (void)
+{
+ uint16_t intsts0;
+ uint16_t intsts1;
+ uint16_t intenb0;
+ uint16_t intenb1;
+ uint16_t brdysts;
+ uint16_t nrdysts;
+ uint16_t bempsts;
+ uint16_t brdyenb;
+ uint16_t nrdyenb;
+ uint16_t bempenb;
+ volatile uint16_t dumy_sts;
+
+ intsts0 = USB200.INTSTS0;
+ intsts1 = USB200.INTSTS1;
+ intenb0 = USB200.INTENB0;
+ intenb1 = USB200.INTENB1;
+
+ if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG;
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+ g_usb0_host_bchg_flag = USB_HOST_YES;
+ }
+ else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSACK;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+#else
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+#endif
+ }
+ else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN;
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#else
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_NORES;
+#endif
+ }
+ else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH)
+ && ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH;
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+ g_usb0_host_detach_flag = USB_HOST_YES;
+
+ Userdef_USB_usb0_host_detach();
+
+ usb0_host_UsbDetach2();
+ }
+ else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH)
+ && ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE))
+ {
+ USB200.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH;
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+ g_usb0_host_attach_flag = USB_HOST_YES;
+
+ Userdef_USB_usb0_host_attach();
+
+ usb0_host_UsbAttach();
+ }
+ else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY)))
+ {
+ brdysts = USB200.BRDYSTS;
+ nrdysts = USB200.NRDYSTS;
+ bempsts = USB200.BEMPSTS;
+ brdyenb = USB200.BRDYENB;
+ nrdyenb = USB200.NRDYENB;
+ bempenb = USB200.BEMPENB;
+
+ if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb))
+ {
+ usb0_host_BRDYInterrupt(brdysts, brdyenb);
+ }
+ else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb))
+ {
+ usb0_host_BEMPInterrupt(bempsts, bempenb);
+ }
+ else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb))
+ {
+ usb0_host_NRDYInterrupt(nrdysts, nrdyenb);
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* Three dummy read for clearing interrupt requests */
+ dumy_sts = USB200.INTSTS0;
+ dumy_sts = USB200.INTSTS1;
+
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_BRDYInterrupt
+* Description : Executes USB BRDY interrupt.
+* Arguments : uint16_t Status ; BRDYSTS Register Value
+* : uint16_t Int_enbl ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t buffer;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB200.BRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+
+#if(1) /* ohci_wrapp */
+ switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ USB200.CFIFOCTR = USB_HOST_BITBCLR;
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ break;
+ }
+#else
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case (USB_HOST_MODE_READ | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb0_host_read_buffer_c(USB_HOST_PIPE0);
+
+ switch (buffer)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ USB200.CFIFOCTR = USB_HOST_BITBCLR;
+ usb0_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ break;
+ }
+#endif
+ }
+ else
+ {
+ usb0_host_brdy_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB200.BRDYSTS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_NRDYInterrupt
+* Description : Executes USB NRDY interrupt.
+* Arguments : uint16_t Status ; NRDYSTS Register Value
+* : uint16_t Int_enbl ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t pid;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB200.NRDYSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+ pid = usb0_host_get_pid(USB_HOST_PIPE0);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+ }
+ else if (pid == USB_HOST_PID_NAK)
+ {
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_NORES;
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else
+ {
+ usb0_host_nrdy_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB200.NRDYSTS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_BEMPInterrupt
+* Description : Executes USB BEMP interrupt.
+* Arguments : uint16_t Status ; BEMPSTS Register Value
+* : uint16_t Int_enbl ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t buffer;
+ uint16_t pid;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb0_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb0_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB200.BEMPSTS = (uint16_t)~g_usb0_host_bit_set[USB_HOST_PIPE0];
+ pid = usb0_host_get_pid(USB_HOST_PIPE0);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+ g_usb0_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+#if(1) /* ohci_wrapp */
+ switch ((g_usb0_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb0_host_write_buffer(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ case USB_HOST_WRITEEND: /* End of data write (zero-length) */
+ break;
+
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ /* do nothing */
+ break;
+ }
+#else
+ switch ((g_usb0_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb0_host_write_buffer(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ case USB_HOST_WRITEEND: /* End of data write (zero-length) */
+ break;
+
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb0_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb0_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb0_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ default:
+ /* do nothing */
+ break;
+ }
+#endif
+ }
+ }
+ else
+ {
+ usb0_host_bemp_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB200.BEMPSTS;
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbsig.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbsig.c
new file mode 100644
index 000000000..4c5f810db
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/host/usb0_host_usbsig.c
@@ -0,0 +1,637 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_usbsig.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb0_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_EnableINT_Module(void);
+static void usb0_host_Enable_AttachINT(void);
+static void usb0_host_Disable_AttachINT(void);
+static void usb0_host_Disable_BchgINT(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb0_host_InitModule
+* Description : Initializes the USB module in USB host module.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_InitModule (void)
+{
+ uint16_t buf1;
+ uint16_t buf2;
+ uint16_t buf3;
+
+ usb0_host_init_pipe_status();
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM); /* HOST mode */
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_DRPD_SHIFT,
+ USB_SYSCFG_DRPD); /* PORT0 D+, D- setting */
+
+ do
+ {
+ buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb0_host_delay_xms(50);
+ buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb0_host_delay_xms(50);
+ buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+
+ } while ((buf1 != buf2) || (buf1 != buf3));
+
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE);
+
+ USB200.CFIFOSEL = (uint16_t)(USB_HOST_BITRCNT | USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+ USB200.D0FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+ USB200.D1FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_CheckAttach
+* Description : Returns the USB device connection state.
+* Arguments : none
+* Return Value : uint16_t ; USB_HOST_ATTACH : Attached
+* : ; USB_HOST_DETACH : not Attached
+*******************************************************************************/
+uint16_t usb0_host_CheckAttach (void)
+{
+ uint16_t buf1;
+ uint16_t buf2;
+ uint16_t buf3;
+ uint16_t rhst;
+
+ do
+ {
+ buf1 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb0_host_delay_xms(50);
+ buf2 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb0_host_delay_xms(50);
+ buf3 = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+
+ } while ((buf1 != buf2) || (buf1 != buf3));
+
+ rhst = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (rhst == USB_HOST_UNDECID)
+ {
+ if (buf1 == USB_HOST_FS_JSTS)
+ {
+ if (g_usb0_host_SupportUsbDeviceSpeed == USB_HOST_HIGH_SPEED)
+ {
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 1,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ }
+ return USB_HOST_ATTACH;
+ }
+ else if (buf1 == USB_HOST_LS_JSTS)
+ {
+ /* Low Speed Device */
+ RZA_IO_RegWrite_16(&USB200.SYSCFG0,
+ 0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ return USB_HOST_ATTACH;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else if ((rhst == USB_HOST_HSMODE) || (rhst == USB_HOST_FSMODE))
+ {
+ return USB_HOST_ATTACH;
+ }
+ else if (rhst == USB_HOST_LSMODE)
+ {
+ return USB_HOST_ATTACH;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ return USB_HOST_DETACH;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbAttach
+* Description : Connects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbAttach (void)
+{
+ usb0_host_EnableINT_Module();
+ usb0_host_Disable_BchgINT();
+ usb0_host_Disable_AttachINT();
+ usb0_host_Enable_DetachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbDetach
+* Description : Disconnects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbDetach (void)
+{
+ uint16_t pipe;
+ uint16_t devadr;
+
+ g_usb0_host_driver_state = USB_HOST_DRV_DETACHED;
+
+ /* Terminate all the pipes in which communications on port */
+ /* are currently carried out */
+ for (pipe = 0; pipe < (USB_HOST_MAX_PIPE_NO + 1); ++pipe)
+ {
+ if (g_usb0_host_pipe_status[pipe] != USB_HOST_PIPE_IDLE)
+ {
+ if (pipe == USB_HOST_PIPE0)
+ {
+ devadr = RZA_IO_RegRead_16(&USB200.DCPMAXP,
+ USB_DCPMAXP_DEVSEL_SHIFT,
+ USB_DCPMAXP_DEVSEL);
+ }
+ else
+ {
+ devadr = RZA_IO_RegRead_16(&g_usb0_host_pipemaxp[pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL);
+ }
+
+ if (devadr == g_usb0_host_UsbAddress)
+ {
+ usb0_host_stop_transfer(pipe);
+ }
+
+ g_usb0_host_pipe_status[pipe] = USB_HOST_PIPE_IDLE;
+ }
+ }
+
+ g_usb0_host_ConfigNum = 0;
+ g_usb0_host_UsbAddress = 0;
+ g_usb0_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+ usb0_host_UsbDetach2();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbDetach2
+* Description : Disconnects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_UsbDetach2 (void)
+{
+ usb0_host_Disable_DetachINT();
+ usb0_host_Disable_BchgINT();
+ usb0_host_Enable_AttachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbBusReset
+* Description : Issues the USB bus reset signal.
+* Arguments : none
+* Return Value : uint16_t ; RHST
+*******************************************************************************/
+uint16_t usb0_host_UsbBusReset (void)
+{
+ uint16_t buffer;
+ uint16_t loop;
+
+ RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+ 1,
+ USB_DVSTCTR0_USBRST_SHIFT,
+ USB_DVSTCTR0_USBRST);
+ RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+ 0,
+ USB_DVSTCTR0_UACT_SHIFT,
+ USB_DVSTCTR0_UACT);
+
+ Userdef_USB_usb0_host_delay_xms(50);
+
+ buffer = USB200.DVSTCTR0;
+ buffer &= (uint16_t)(~(USB_HOST_BITRST));
+ buffer |= USB_HOST_BITUACT;
+ USB200.DVSTCTR0 = buffer;
+
+ Userdef_USB_usb0_host_delay_xms(20);
+
+ for (loop = 0, buffer = USB_HOST_HSPROC; loop < 3; ++loop)
+ {
+ buffer = RZA_IO_RegRead_16(&USB200.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (buffer == USB_HOST_HSPROC)
+ {
+ Userdef_USB_usb0_host_delay_xms(10);
+ }
+ else
+ {
+ break;
+ }
+ }
+
+ return buffer;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbResume
+* Description : Issues the USB resume signal.
+* Arguments : none
+* Return Value : int32_t ; DEVDRV_SUCCESS
+* : ; DEVDRV_ERROR
+*******************************************************************************/
+int32_t usb0_host_UsbResume (void)
+{
+ uint16_t buf;
+
+ if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) == 0)
+ {
+ /* not SUSPEND */
+ return DEVDRV_ERROR;
+ }
+
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+ RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+ 1,
+ USB_DVSTCTR0_RESUME_SHIFT,
+ USB_DVSTCTR0_RESUME);
+ Userdef_USB_usb0_host_delay_xms(20);
+
+ buf = USB200.DVSTCTR0;
+ buf &= (uint16_t)(~(USB_HOST_BITRESUME));
+ buf |= USB_HOST_BITUACT;
+ USB200.DVSTCTR0 = buf;
+
+ g_usb0_host_driver_state &= (uint16_t)~USB_HOST_DRV_SUSPEND;
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_UsbSuspend
+* Description : Issues the USB suspend signal.
+* Arguments : none
+* Return Value : int32_t ; DEVDRV_SUCCESS :not SUSPEND
+* : ; DEVDRV_ERROR :SUSPEND
+*******************************************************************************/
+int32_t usb0_host_UsbSuspend (void)
+{
+ uint16_t buf;
+
+ if ((g_usb0_host_driver_state & USB_HOST_DRV_SUSPEND) != 0)
+ {
+ /* SUSPEND */
+ return DEVDRV_ERROR;
+ }
+
+ RZA_IO_RegWrite_16(&USB200.DVSTCTR0,
+ 0,
+ USB_DVSTCTR0_UACT_SHIFT,
+ USB_DVSTCTR0_UACT);
+
+ Userdef_USB_usb0_host_delay_xms(5);
+
+ buf = RZA_IO_RegRead_16(&USB200.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ if ((buf != USB_HOST_FS_JSTS) && (buf != USB_HOST_LS_JSTS))
+ {
+ usb0_host_UsbDetach();
+ }
+ else
+ {
+ g_usb0_host_driver_state |= USB_HOST_DRV_SUSPEND;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Enable_DetachINT
+* Description : Enables the USB disconnection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Enable_DetachINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 1,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_DetachINT
+* Description : Disables the USB disconnection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_DetachINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Enable_AttachINT
+* Description : Enables the USB connection detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Enable_AttachINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 1,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_AttachINT
+* Description : Disables the USB connection detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_AttachINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_Disable_BchgINT
+* Description : Disables the USB bus change detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_Disable_BchgINT (void)
+{
+ USB200.INTSTS1 = (uint16_t)(~(USB_HOST_BITBCHG));
+ RZA_IO_RegWrite_16(&USB200.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_set_devadd
+* Description : DEVADDn register is set by specified value
+* Arguments : uint16_t addr : Device address
+* : uint16_t *devadd : Set value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_set_devadd (uint16_t addr, uint16_t * devadd)
+{
+ uint16_t * ptr;
+ uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning.
+
+ switch (addr)
+ {
+ case USB_HOST_DEVICE_0:
+ ptr = (uint16_t *)&USB200.DEVADD0;
+ break;
+
+ case USB_HOST_DEVICE_1:
+ ptr = (uint16_t *)&USB200.DEVADD1;
+ break;
+
+ case USB_HOST_DEVICE_2:
+ ptr = (uint16_t *)&USB200.DEVADD2;
+ break;
+
+ case USB_HOST_DEVICE_3:
+ ptr = (uint16_t *)&USB200.DEVADD3;
+ break;
+
+ case USB_HOST_DEVICE_4:
+ ptr = (uint16_t *)&USB200.DEVADD4;
+ break;
+
+ case USB_HOST_DEVICE_5:
+ ptr = (uint16_t *)&USB200.DEVADD5;
+ break;
+
+ case USB_HOST_DEVICE_6:
+ ptr = (uint16_t *)&USB200.DEVADD6;
+ break;
+
+ case USB_HOST_DEVICE_7:
+ ptr = (uint16_t *)&USB200.DEVADD7;
+ break;
+
+ case USB_HOST_DEVICE_8:
+ ptr = (uint16_t *)&USB200.DEVADD8;
+ break;
+
+ case USB_HOST_DEVICE_9:
+ ptr = (uint16_t *)&USB200.DEVADD9;
+ break;
+
+ case USB_HOST_DEVICE_10:
+ ptr = (uint16_t *)&USB200.DEVADDA;
+ break;
+
+ default:
+ ret_flag = DEVDRV_FLAG_OFF;
+ break;
+ }
+
+ if (ret_flag == DEVDRV_FLAG_ON)
+ {
+ *ptr = (uint16_t)(*devadd & USB_HOST_DEVADD_MASK);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_get_devadd
+* Description : DEVADDn register is obtained
+* Arguments : uint16_t addr : Device address
+* : uint16_t *devadd : USB_HOST_DEVADD register value
+* Return Value : none
+*******************************************************************************/
+void usb0_host_get_devadd (uint16_t addr, uint16_t * devadd)
+{
+ uint16_t * ptr;
+ uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning.
+
+ switch (addr)
+ {
+ case USB_HOST_DEVICE_0:
+ ptr = (uint16_t *)&USB200.DEVADD0;
+ break;
+
+ case USB_HOST_DEVICE_1:
+ ptr = (uint16_t *)&USB200.DEVADD1;
+ break;
+
+ case USB_HOST_DEVICE_2:
+ ptr = (uint16_t *)&USB200.DEVADD2;
+ break;
+
+ case USB_HOST_DEVICE_3:
+ ptr = (uint16_t *)&USB200.DEVADD3;
+ break;
+
+ case USB_HOST_DEVICE_4:
+ ptr = (uint16_t *)&USB200.DEVADD4;
+ break;
+
+ case USB_HOST_DEVICE_5:
+ ptr = (uint16_t *)&USB200.DEVADD5;
+ break;
+
+ case USB_HOST_DEVICE_6:
+ ptr = (uint16_t *)&USB200.DEVADD6;
+ break;
+
+ case USB_HOST_DEVICE_7:
+ ptr = (uint16_t *)&USB200.DEVADD7;
+ break;
+
+ case USB_HOST_DEVICE_8:
+ ptr = (uint16_t *)&USB200.DEVADD8;
+ break;
+
+ case USB_HOST_DEVICE_9:
+ ptr = (uint16_t *)&USB200.DEVADD9;
+ break;
+
+ case USB_HOST_DEVICE_10:
+ ptr = (uint16_t *)&USB200.DEVADDA;
+ break;
+
+ default:
+ ret_flag = DEVDRV_FLAG_OFF;
+ break;
+ }
+
+ if (ret_flag == DEVDRV_FLAG_ON)
+ {
+ *devadd = *ptr;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_EnableINT_Module
+* Description : Enables BEMP/NRDY/BRDY interrupt and SIGN/SACK interrupt.
+* : Enables NRDY/BEMP interrupt in the pipe0.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb0_host_EnableINT_Module (void)
+{
+ uint16_t buf;
+
+ buf = USB200.INTENB0;
+ buf |= (USB_HOST_BITBEMPE | USB_HOST_BITNRDYE | USB_HOST_BITBRDYE);
+ USB200.INTENB0 = buf;
+
+ buf = USB200.INTENB1;
+ buf |= (USB_HOST_BITSIGNE | USB_HOST_BITSACKE);
+ USB200.INTENB1 = buf;
+
+ usb0_host_enable_nrdy_int(USB_HOST_PIPE0);
+ usb0_host_enable_bemp_int(USB_HOST_PIPE0);
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c
new file mode 100644
index 000000000..8f081a618
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_dmacdrv.c
@@ -0,0 +1,698 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_dmacdrv.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+#include "usb0_host_dmacdrv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
+
+/* ==== Request setting information for on-chip peripheral module ==== */
+typedef enum dmac_peri_req_reg_type
+{
+ DMAC_REQ_MID,
+ DMAC_REQ_RID,
+ DMAC_REQ_AM,
+ DMAC_REQ_LVL,
+ DMAC_REQ_REQD
+} dmac_peri_req_reg_type_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+/* ==== Prototype declaration ==== */
+
+/* ==== Global variable ==== */
+/* On-chip peripheral module request setting table */
+static const uint8_t usb0_host_dmac_peri_req_init_table[8][5] =
+{
+ /* MID,RID, AM,LVL,REQD */
+ { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
+ { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
+ { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
+ { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
+ { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
+ { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
+ { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
+ { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
+};
+
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 1.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 1 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
+* : : register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous
+* : : transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module
+* : : request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction : Setting value of CHCFG_n register
+* : : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC1.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC1.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC1.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC1_CHCFG_n_DAD_SHIFT,
+ DMAC1_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC1_CHCFG_n_SAD_SHIFT,
+ DMAC1_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->dst_size,
+ DMAC1_CHCFG_n_DDS_SHIFT,
+ DMAC1_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ trans_info->src_size,
+ DMAC1_CHCFG_n_SDS_SHIFT,
+ DMAC1_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_DMS_SHIFT,
+ DMAC1_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_RSEL_SHIFT,
+ DMAC1_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_SBE_SHIFT,
+ DMAC1_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_DEM_SHIFT,
+ DMAC1_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_REN_SHIFT,
+ DMAC1_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_RSW_SHIFT,
+ DMAC1_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_REN_SHIFT,
+ DMAC1_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_RSW_SHIFT,
+ DMAC1_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_TM_SHIFT,
+ DMAC1_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_SEL_SHIFT,
+ DMAC1_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 1,
+ DMAC1_CHCFG_n_HIEN_SHIFT,
+ DMAC1_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ 0,
+ DMAC1_CHCFG_n_LOEN_SHIFT,
+ DMAC1_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC1_CHCFG_n_AM_SHIFT,
+ DMAC1_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC1_CHCFG_n_LVL_SHIFT,
+ DMAC1_CHCFG_n_LVL);
+ if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC1_CHCFG_n_REQD_SHIFT,
+ DMAC1_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC1.CHCFG_n,
+ req_direction,
+ DMAC1_CHCFG_n_REQD_SHIFT,
+ DMAC1_CHCFG_n_REQD);
+ }
+ RZA_IO_RegWrite_32(&DMAC01.DMARS,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC01_DMARS_CH1_RID_SHIFT,
+ DMAC01_DMARS_CH1_RID);
+ RZA_IO_RegWrite_32(&DMAC01.DMARS,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC01_DMARS_CH1_MID_SHIFT,
+ DMAC01_DMARS_CH1_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Open
+* Description : Enables DMAC channel 1 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb0_host_DMAC1_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_EN_SHIFT,
+ DMAC1_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_TACT_SHIFT,
+ DMAC1_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_SWRST_SHIFT,
+ DMAC1_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC1.CHCTRL_n,
+ DMAC1_CHCTRL_n_SWRST_SHIFT,
+ DMAC1_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_SETEN_SHIFT,
+ DMAC1_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_STG_SHIFT,
+ DMAC1_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Close
+* Description : Aborts DMAC channel 1 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC1.CHCTRL_n,
+ 1,
+ DMAC1_CHCTRL_n_CLREN_SHIFT,
+ DMAC1_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_TACT_SHIFT,
+ DMAC1_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_EN_SHIFT,
+ DMAC1_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC1.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC1_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 1 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 1 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC1_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC1.CHSTAT_n,
+ DMAC1_CHSTAT_n_SR_SHIFT,
+ DMAC1_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC1.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC1.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC1.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC1.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC1.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC1.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 2.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 2 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
+* : : register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous
+* : : transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module
+* : : request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction : Setting value of CHCFG_n register
+* : : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC2.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC2.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC2.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC2_CHCFG_n_DAD_SHIFT,
+ DMAC2_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC2_CHCFG_n_SAD_SHIFT,
+ DMAC2_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->dst_size,
+ DMAC2_CHCFG_n_DDS_SHIFT,
+ DMAC2_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ trans_info->src_size,
+ DMAC2_CHCFG_n_SDS_SHIFT,
+ DMAC2_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_DMS_SHIFT,
+ DMAC2_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_RSEL_SHIFT,
+ DMAC2_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_SBE_SHIFT,
+ DMAC2_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_DEM_SHIFT,
+ DMAC2_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_REN_SHIFT,
+ DMAC2_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_RSW_SHIFT,
+ DMAC2_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_REN_SHIFT,
+ DMAC2_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_RSW_SHIFT,
+ DMAC2_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_TM_SHIFT,
+ DMAC2_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 2,
+ DMAC2_CHCFG_n_SEL_SHIFT,
+ DMAC2_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 1,
+ DMAC2_CHCFG_n_HIEN_SHIFT,
+ DMAC2_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ 0,
+ DMAC2_CHCFG_n_LOEN_SHIFT,
+ DMAC2_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC2_CHCFG_n_AM_SHIFT,
+ DMAC2_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC2_CHCFG_n_LVL_SHIFT,
+ DMAC2_CHCFG_n_LVL);
+ if (usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC2_CHCFG_n_REQD_SHIFT,
+ DMAC2_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC2.CHCFG_n,
+ req_direction,
+ DMAC2_CHCFG_n_REQD_SHIFT,
+ DMAC2_CHCFG_n_REQD);
+ }
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC23_DMARS_CH2_RID_SHIFT,
+ DMAC23_DMARS_CH2_RID);
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb0_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC23_DMARS_CH2_MID_SHIFT,
+ DMAC23_DMARS_CH2_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Open
+* Description : Enables DMAC channel 2 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb0_host_DMAC2_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_EN_SHIFT,
+ DMAC2_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_TACT_SHIFT,
+ DMAC2_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_SWRST_SHIFT,
+ DMAC2_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC2.CHCTRL_n,
+ DMAC2_CHCTRL_n_SWRST_SHIFT,
+ DMAC2_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_SETEN_SHIFT,
+ DMAC2_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_STG_SHIFT,
+ DMAC2_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Close
+* Description : Aborts DMAC channel 2 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC2.CHCTRL_n,
+ 1,
+ DMAC2_CHCTRL_n_CLREN_SHIFT,
+ DMAC2_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_TACT_SHIFT,
+ DMAC2_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_EN_SHIFT,
+ DMAC2_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC2.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_DMAC2_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 2 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 2 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb0_host_DMAC2_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC2.CHSTAT_n,
+ DMAC2_CHSTAT_n_SR_SHIFT,
+ DMAC2_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC2.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC2.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC2.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC2.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC2.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC2.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_userdef.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_userdef.c
new file mode 100644
index 000000000..db0b4cfd1
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/src/userdef/usb0_host_userdef.c
@@ -0,0 +1,778 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb0_host_userdef.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "cmsis_os.h"
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "devdrv_usb_host_api.h"
+#include "usb0_host.h"
+#include "MBRZA1H.h" /* INTC Driver Header */
+#include "usb0_host_dmacdrv.h"
+#include "ohci_wrapp_RZ_A1_local.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DUMMY_ACCESS OSTM0CNT
+
+/* #define CACHE_WRITEBACK */
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern int32_t io_cwb(unsigned long start, unsigned long end);
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb0_host_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void usb0_host_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void Userdef_USB_usb0_host_delay_10us_2(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_d0fifo_dmaintid
+* Description : get D0FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D0FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb0_host_d0fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+ return 0xFFFF;
+#else
+ return DMAINT1_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_d1fifo_dmaintid
+* Description : get D1FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D1FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb0_host_d1fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+ return 0xFFFF;
+#else
+ return DMAINT2_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_attach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_attach (void)
+{
+// printf("\n");
+// printf("channel 0 attach device\n");
+// printf("\n");
+ ohciwrapp_loc_Connect(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_detach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_detach (void)
+{
+// printf("\n");
+// printf("channel 0 detach device\n");
+// printf("\n");
+ ohciwrapp_loc_Connect(0);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_1ms
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_1ms (void)
+{
+ osDelay(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_xms
+* Description : Wait for the software in the period of time specified by the
+* : argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t msec ; Wait Time (msec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_xms (uint32_t msec)
+{
+ osDelay(msec);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_10us
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t usec ; Wait Time(x 10usec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_10us (uint32_t usec)
+{
+ volatile int i;
+
+ /* Wait 10us (Please change for your MCU) */
+ for (i = 0; i < usec; ++i)
+ {
+ Userdef_USB_usb0_host_delay_10us_2();
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_10us_2
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+static void Userdef_USB_usb0_host_delay_10us_2 (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 1us (Please change for your MCU) */
+ for (i = 0; i < 14; ++i)
+ {
+ tmp = DUMMY_ACCESS;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_delay_500ns
+* Description : Wait for software for 500ns.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_delay_500ns (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 500ns (Please change for your MCU) */
+ /* Wait 500ns I clock 266MHz */
+ tmp = DUMMY_ACCESS;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_start_dma
+* Description : Enables DMA transfer on the information specified by the argument.
+* : Set DMAC register by this function to enable DMA transfer.
+* : After executing this function, USB module is set to start DMA
+* : transfer. DMA transfer should not wait for DMA transfer complete.
+* Arguments : USB_HOST_DMA_t *dma : DMA parameter
+* : typedef struct{
+* : uint32_t fifo; FIFO for using
+* : uint32_t buffer; Start address of transfer source/destination
+* : uint32_t bytes; Transfer size(Byte)
+* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
+* : uint32_t size; DMA transfer size
+* : } USB_HOST_DMA_t;
+* : uint16_t dfacc ; 0 : cycle steal mode
+* : 1 : 16byte continuous mode
+* : 2 : 32byte continuous mode
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_start_dma (USB_HOST_DMA_t * dma, uint16_t dfacc)
+{
+ uint32_t trncount;
+ uint32_t src;
+ uint32_t dst;
+ uint32_t size;
+ uint32_t dir;
+#ifdef CACHE_WRITEBACK
+ uint32_t ptr;
+#endif
+
+ trncount = dma->bytes;
+ dir = dma->dir;
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ /* DxFIFO determination */
+ dst = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ src += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ src += 3; /* byte access */
+ }
+#endif
+ }
+ else
+ {
+ /* DxFIFO determination */
+ src = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ dst += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB200.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB200.D1FIFO.UINT32);
+ }
+ dst += 3; /* byte access */
+ }
+#endif
+ }
+
+#ifdef CACHE_WRITEBACK
+ ptr = (uint32_t)dma->buffer;
+ if ((ptr & 0x20000000ul) == 0)
+ {
+ io_cwb((uint32_t)ptr,(uint32_t)(ptr)+trncount);
+ }
+#endif
+
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ usb0_host_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+ else
+ {
+ usb0_host_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_dmac0
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ request_factor = DMAC_REQ_USB0_DMA0_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_HOST_BUF2FIFO)
+ {
+ request_factor = DMAC_REQ_USB0_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb0_host_DMAC1_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC1_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb0_host_DMAC1_Open(DMAC_REQ_MODE_PERI);
+
+ if (ret != 0)
+ {
+// printf("DMAC1 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: usb0_host_enable_dmac1
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb0_host_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ request_factor =DMAC_REQ_USB0_DMA1_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_HOST_BUF2FIFO)
+ {
+ request_factor =DMAC_REQ_USB0_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb0_host_DMAC2_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in usb0_host_DMAC2_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb0_host_DMAC2_Open(DMAC_REQ_MODE_PERI);
+
+ if (ret != 0)
+ {
+// printf("DMAC2 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_stop_dma0
+* Description : Disables DMA transfer.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+* Notice : This function should be executed to DMAC executed at the time
+* : of specification of D0_FIF0_DMA in dma->fifo.
+*******************************************************************************/
+uint32_t Userdef_USB_usb0_host_stop_dma0 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb0_host_DMAC1_Close(&remain);
+
+ return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_stop_dma1
+* Description : Disables DMA transfer.
+* : This function should be executed to DMAC executed at the time
+* : of specification of D1_FIF0_DMA in dma->fifo.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb0_host_stop_dma1 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb0_host_DMAC2_Close(&remain);
+
+ return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_notice
+* Description : Notice of USER
+* Arguments : const char *format
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_notice (const char * format)
+{
+// printf(format);
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb0_host_user_rdy
+* Description : This function notify a user and wait for trigger
+* Arguments : const char *format
+* : uint16_t data
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb0_host_user_rdy (const char * format, uint16_t data)
+{
+// printf(format, data);
+ getchar();
+
+ return;
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host.h
new file mode 100644
index 000000000..1759e7038
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host.h
@@ -0,0 +1,156 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_HOST_H
+#define USB1_HOST_H
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "devdrv_usb_host_api.h"
+#include "usb_host.h"
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern const uint16_t g_usb1_host_bit_set[];
+extern uint32_t g_usb1_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+extern uint8_t *g_usb1_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+extern uint16_t g_usb1_host_PipeIgnore[];
+extern uint16_t g_usb1_host_PipeTbl[];
+extern uint16_t g_usb1_host_pipe_status[];
+extern uint32_t g_usb1_host_PipeDataSize[];
+
+extern USB_HOST_DMA_t g_usb1_host_DmaInfo[];
+extern uint16_t g_usb1_host_DmaPipe[];
+extern uint16_t g_usb1_host_DmaBval[];
+extern uint16_t g_usb1_host_DmaStatus[];
+
+extern uint16_t g_usb1_host_driver_state;
+extern uint16_t g_usb1_host_ConfigNum;
+extern uint16_t g_usb1_host_CmdStage;
+extern uint16_t g_usb1_host_bchg_flag;
+extern uint16_t g_usb1_host_detach_flag;
+extern uint16_t g_usb1_host_attach_flag;
+
+extern uint16_t g_usb1_host_UsbAddress;
+extern uint16_t g_usb1_host_setUsbAddress;
+extern uint16_t g_usb1_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+extern uint16_t g_usb1_host_UsbDeviceSpeed;
+extern uint16_t g_usb1_host_SupportUsbDeviceSpeed;
+
+extern uint16_t g_usb1_host_SavReq;
+extern uint16_t g_usb1_host_SavVal;
+extern uint16_t g_usb1_host_SavIndx;
+extern uint16_t g_usb1_host_SavLen;
+
+extern uint16_t g_usb1_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t g_usb1_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t g_usb1_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+extern uint16_t g_usb1_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+/* ==== common ==== */
+void usb1_host_dma_stop_d0(uint16_t pipe, uint32_t remain);
+void usb1_host_dma_stop_d1(uint16_t pipe, uint32_t remain);
+uint16_t usb1_host_is_hispeed(void);
+uint16_t usb1_host_is_hispeed_enable(void);
+uint16_t usb1_host_start_send_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb1_host_write_buffer(uint16_t pipe);
+uint16_t usb1_host_write_buffer_c(uint16_t pipe);
+uint16_t usb1_host_write_buffer_d0(uint16_t pipe);
+uint16_t usb1_host_write_buffer_d1(uint16_t pipe);
+void usb1_host_start_receive_transfer(uint16_t pipe, uint32_t size, uint8_t *data);
+uint16_t usb1_host_read_buffer(uint16_t pipe);
+uint16_t usb1_host_read_buffer_c(uint16_t pipe);
+uint16_t usb1_host_read_buffer_d0(uint16_t pipe);
+uint16_t usb1_host_read_buffer_d1(uint16_t pipe);
+uint16_t usb1_host_change_fifo_port(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb1_host_set_curpipe(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw);
+void usb1_host_set_curpipe2(uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc);
+uint16_t usb1_host_get_mbw(uint32_t trncount, uint32_t dtptr);
+uint16_t usb1_host_read_dma(uint16_t pipe);
+void usb1_host_stop_transfer(uint16_t pipe);
+void usb1_host_brdy_int(uint16_t status, uint16_t int_enb);
+void usb1_host_nrdy_int(uint16_t status, uint16_t int_enb);
+void usb1_host_bemp_int(uint16_t status, uint16_t int_enb);
+void usb1_host_setting_interrupt(uint8_t level);
+void usb1_host_reset_module(uint16_t clockmode);
+uint16_t usb1_host_get_buf_size(uint16_t pipe);
+uint16_t usb1_host_get_mxps(uint16_t pipe);
+void usb1_host_enable_brdy_int(uint16_t pipe);
+void usb1_host_disable_brdy_int(uint16_t pipe);
+void usb1_host_clear_brdy_sts(uint16_t pipe);
+void usb1_host_enable_bemp_int(uint16_t pipe);
+void usb1_host_disable_bemp_int(uint16_t pipe);
+void usb1_host_clear_bemp_sts(uint16_t pipe);
+void usb1_host_enable_nrdy_int(uint16_t pipe);
+void usb1_host_disable_nrdy_int(uint16_t pipe);
+void usb1_host_clear_nrdy_sts(uint16_t pipe);
+void usb1_host_set_pid_buf(uint16_t pipe);
+void usb1_host_set_pid_nak(uint16_t pipe);
+void usb1_host_set_pid_stall(uint16_t pipe);
+void usb1_host_clear_pid_stall(uint16_t pipe);
+uint16_t usb1_host_get_pid(uint16_t pipe);
+void usb1_host_set_sqclr(uint16_t pipe);
+void usb1_host_set_sqset(uint16_t pipe);
+void usb1_host_set_csclr(uint16_t pipe);
+void usb1_host_aclrm(uint16_t pipe);
+void usb1_host_set_aclrm(uint16_t pipe);
+void usb1_host_clr_aclrm(uint16_t pipe);
+uint16_t usb1_host_get_sqmon(uint16_t pipe);
+uint16_t usb1_host_get_inbuf(uint16_t pipe);
+
+/* ==== host ==== */
+void usb1_host_init_pipe_status(void);
+int32_t usb1_host_CtrlTransStart(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+void usb1_host_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void usb1_host_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+uint16_t usb1_host_CtrlWriteStart(uint32_t Bsize, uint8_t *Table);
+void usb1_host_StatusStage(void);
+void usb1_host_get_devadd(uint16_t addr, uint16_t *devadd);
+void usb1_host_set_devadd(uint16_t addr, uint16_t *devadd);
+void usb1_host_InitModule(void);
+uint16_t usb1_host_CheckAttach(void);
+void usb1_host_UsbDetach(void);
+void usb1_host_UsbDetach2(void);
+void usb1_host_UsbAttach(void);
+uint16_t usb1_host_UsbBusReset(void);
+int32_t usb1_host_UsbResume(void);
+int32_t usb1_host_UsbSuspend(void);
+void usb1_host_Enable_DetachINT(void);
+void usb1_host_Disable_DetachINT(void);
+void usb1_host_UsbStateManager(void);
+
+
+#endif /* USB1_HOST_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_api.h
new file mode 100644
index 000000000..63ae6d650
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_api.h
@@ -0,0 +1,112 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_api.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_HOST_API_H
+#define USB1_HOST_API_H
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void usb1_host_interrupt(uint32_t int_sense);
+void usb1_host_dma_interrupt_d0fifo(uint32_t int_sense);
+void usb1_host_dma_interrupt_d1fifo(uint32_t int_sense);
+
+uint16_t usb1_api_host_init(uint8_t int_level, uint16_t mode, uint16_t clockmode);
+int32_t usb1_api_host_enumeration(uint16_t devadr);
+int32_t usb1_api_host_detach(void);
+int32_t usb1_api_host_data_in(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t usb1_api_host_data_out(uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t *data_buf);
+int32_t usb1_api_host_control_transfer(uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len, uint8_t *Buf);
+int32_t usb1_api_host_set_endpoint(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *configdescriptor);
+int32_t usb1_api_host_clear_endpoint(USB_HOST_CFG_PIPETBL_t *user_table);
+int32_t usb1_api_host_clear_endpoint_pipe(uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t *user_table);
+uint16_t usb1_api_host_SetEndpointTable(uint16_t devadr, USB_HOST_CFG_PIPETBL_t *user_table, uint8_t *Table);
+int32_t usb1_api_host_data_count(uint16_t pipe, uint32_t *data_count);
+
+int32_t usb1_api_host_GetDeviceDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t usb1_api_host_GetConfigDescriptor(uint16_t devadr, uint16_t size, uint8_t *buf);
+int32_t usb1_api_host_SetConfig(uint16_t devadr, uint16_t confignum);
+int32_t usb1_api_host_SetInterface(uint16_t devadr, uint16_t interface_alt, uint16_t interface_index);
+int32_t usb1_api_host_ClearStall(uint16_t devadr, uint16_t ep_dir);
+uint16_t usb1_api_host_GetUsbDeviceState(void);
+
+void usb1_api_host_elt_4_4(void);
+void usb1_api_host_elt_4_5(void);
+void usb1_api_host_elt_4_6(void);
+void usb1_api_host_elt_4_7(void);
+void usb1_api_host_elt_4_8(void);
+void usb1_api_host_elt_4_9(void);
+void usb1_api_host_elt_get_desc(void);
+
+void usb1_host_EL_ModeInit(void);
+void usb1_host_EL_SetUACT(void);
+void usb1_host_EL_ClearUACT(void);
+void usb1_host_EL_SetTESTMODE(uint16_t mode);
+void usb1_host_EL_ClearNRDYSTS(uint16_t pipe);
+uint16_t usb1_host_EL_GetINTSTS1(void);
+void usb1_host_EL_UsbBusReset(void);
+void usb1_host_EL_UsbAttach(void);
+void usb1_host_EL_SetupStage(uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len);
+void usb1_host_EL_StatusStage(void);
+void usb1_host_EL_CtrlReadStart(uint32_t Bsize, uint8_t *Table);
+int32_t usb1_host_EL_UsbSuspend(void);
+int32_t usb1_host_EL_UsbResume(void);
+
+#if 0 /* prototype in devdrv_usb_host_api.h */
+uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid(void);
+uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid(void);
+void Userdef_USB_usb1_host_attach(void);
+void Userdef_USB_usb1_host_detach(void);
+void Userdef_USB_usb1_host_delay_1ms(void);
+void Userdef_USB_usb1_host_delay_xms(uint32_t msec);
+void Userdef_USB_usb1_host_delay_10us(uint32_t usec);
+void Userdef_USB_usb1_host_delay_500ns(void);
+void Userdef_USB_usb1_host_start_dma(USB_HOST_DMA_t *dma, uint16_t dfacc);
+uint32_t Userdef_USB_usb1_host_stop_dma0(void);
+uint32_t Userdef_USB_usb1_host_stop_dma1(void);
+#endif
+
+#endif /* USB1_HOST_API_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_dmacdrv.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_dmacdrv.h
new file mode 100644
index 000000000..a4c3943d7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/inc/usb1_host_dmacdrv.h
@@ -0,0 +1,139 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_dmacdrv.h
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Description : RZ/A1H R7S72100 USB Sample Program
+*******************************************************************************/
+#ifndef USB1_HOST_DMACDRV_H
+#define USB1_HOST_DMACDRV_H
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+typedef struct dmac_transinfo
+{
+ uint32_t src_addr; /* Transfer source address */
+ uint32_t dst_addr; /* Transfer destination address */
+ uint32_t count; /* Transfer byte count */
+ uint32_t src_size; /* Transfer source data size */
+ uint32_t dst_size; /* Transfer destination data size */
+ uint32_t saddr_dir; /* Transfer source address direction */
+ uint32_t daddr_dir; /* Transfer destination address direction */
+} dmac_transinfo_t;
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+/* ==== Transfer specification of the sample program ==== */
+#define DMAC_SAMPLE_SINGLE (0) /* Single transfer */
+#define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */
+
+/* ==== DMA modes ==== */
+#define DMAC_MODE_REGISTER (0) /* Register mode */
+#define DMAC_MODE_LINK (1) /* Link mode */
+
+/* ==== Transfer requests ==== */
+#define DMAC_REQ_MODE_EXT (0) /* External request */
+#define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */
+#define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */
+
+/* ==== DMAC transfer sizes ==== */
+#define DMAC_TRANS_SIZE_8 (0) /* 8 bits */
+#define DMAC_TRANS_SIZE_16 (1) /* 16 bits */
+#define DMAC_TRANS_SIZE_32 (2) /* 32 bits */
+#define DMAC_TRANS_SIZE_64 (3) /* 64 bits */
+#define DMAC_TRANS_SIZE_128 (4) /* 128 bits */
+#define DMAC_TRANS_SIZE_256 (5) /* 256 bits */
+#define DMAC_TRANS_SIZE_512 (6) /* 512 bits */
+#define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */
+
+/* ==== Address increment for transferring ==== */
+#define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */
+#define DMAC_TRANS_ADR_INC (0) /* Increment */
+
+/* ==== Method for detecting DMA request ==== */
+#define DMAC_REQ_DET_FALL (0) /* Falling edge detection */
+#define DMAC_REQ_DET_RISE (1) /* Rising edge detection */
+#define DMAC_REQ_DET_LOW (2) /* Low level detection */
+#define DMAC_REQ_DET_HIGH (3) /* High level detection */
+
+/* ==== Request Direction ==== */
+#define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */
+#define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */
+
+/* ==== Descriptors ==== */
+#define DMAC_DESC_HEADER (0) /* Header */
+#define DMAC_DESC_SRC_ADDR (1) /* Source Address */
+#define DMAC_DESC_DST_ADDR (2) /* Destination Address */
+#define DMAC_DESC_COUNT (3) /* Transaction Byte */
+#define DMAC_DESC_CHCFG (4) /* Channel Confg */
+#define DMAC_DESC_CHITVL (5) /* Channel Interval */
+#define DMAC_DESC_CHEXT (6) /* Channel Extension */
+#define DMAC_DESC_LINK_ADDR (7) /* Link Address */
+
+/* ==== On-chip peripheral module requests ===== */
+typedef enum dmac_request_factor
+{
+ DMAC_REQ_USB0_DMA0_TX, /* USB_0 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA0_RX, /* USB_0 channel 0 receive FIFO full */
+ DMAC_REQ_USB0_DMA1_TX, /* USB_0 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB0_DMA1_RX, /* USB_0 channel 1 receive FIFO full */
+ DMAC_REQ_USB1_DMA0_TX, /* USB_1 channel 0 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA0_RX, /* USB_1 channel 0 receive FIFO full */
+ DMAC_REQ_USB1_DMA1_TX, /* USB_1 channel 1 transmit FIFO empty */
+ DMAC_REQ_USB1_DMA1_RX, /* USB_1 channel 1 receive FIFO full */
+} dmac_request_factor_t;
+
+
+/*******************************************************************************
+Variable Externs
+*******************************************************************************/
+
+
+/*******************************************************************************
+Functions Prototypes
+*******************************************************************************/
+void usb1_host_DMAC3_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb1_host_DMAC3_Open(uint32_t req);
+void usb1_host_DMAC3_Close(uint32_t *remain);
+void usb1_host_DMAC3_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+void usb1_host_DMAC4_PeriReqInit(const dmac_transinfo_t *trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction);
+int32_t usb1_host_DMAC4_Open(uint32_t req);
+void usb1_host_DMAC4_Close(uint32_t *remain);
+void usb1_host_DMAC4_Load_Set(uint32_t src_addr, uint32_t dst_addr, uint32_t count);
+
+#endif /* USB1_HOST_DMACDRV_H */
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dataio.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dataio.c
new file mode 100644
index 000000000..aa76d6143
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dataio.c
@@ -0,0 +1,2835 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_dataio.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static uint16_t g_usb1_host_mbw[(USB_HOST_MAX_PIPE_NO + 1)];
+
+static void usb1_host_start_receive_trns_c(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_host_start_receive_trns_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_host_start_receive_trns_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_host_start_receive_dma_d0(uint16_t pipe, uint32_t size, uint8_t *data);
+static void usb1_host_start_receive_dma_d1(uint16_t pipe, uint32_t size, uint8_t *data);
+static uint16_t usb1_host_read_dma_d0(uint16_t pipe);
+static uint16_t usb1_host_read_dma_d1(uint16_t pipe);
+static uint16_t usb1_host_write_dma_d0(uint16_t pipe);
+static uint16_t usb1_host_write_dma_d1(uint16_t pipe);
+
+static void usb1_host_read_c_fifo(uint16_t pipe, uint16_t count);
+static void usb1_host_write_c_fifo(uint16_t Pipe, uint16_t count);
+static void usb1_host_read_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb1_host_write_d0_fifo(uint16_t pipe, uint16_t count);
+static void usb1_host_read_d1_fifo(uint16_t pipe, uint16_t count);
+static void usb1_host_write_d1_fifo(uint16_t pipe, uint16_t count);
+
+static void usb1_host_clear_transaction_counter(uint16_t pipe);
+static void usb1_host_set_transaction_counter(uint16_t pipe, uint32_t count);
+
+static uint32_t usb1_host_com_get_dmasize(uint32_t trncount, uint32_t dtptr);
+
+static uint16_t usb1_host_set_dfacc_d0(uint16_t mbw, uint32_t count);
+static uint16_t usb1_host_set_dfacc_d1(uint16_t mbw, uint32_t count);
+
+
+/*******************************************************************************
+* Function Name: usb1_host_start_send_transfer
+* Description : Starts the USB data communication using pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data data Address
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_start_send_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t status;
+ uint16_t usefifo;
+ uint16_t mbw;
+
+ g_usb1_host_data_count[pipe] = size;
+ g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ usb1_host_clear_bemp_sts(pipe);
+ usb1_host_clear_brdy_sts(pipe);
+ usb1_host_clear_nrdy_sts(pipe);
+
+ mbw = usb1_host_get_mbw(size, (uint32_t)data);
+
+ usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ case USB_HOST_D0FIFO_DMA:
+ usefifo = USB_HOST_D0USE;
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ case USB_HOST_D1FIFO_DMA:
+ usefifo = USB_HOST_D1USE;
+ break;
+
+ default:
+ usefifo = USB_HOST_CUSE;
+ break;
+ };
+
+ usb1_host_set_curpipe(USB_HOST_PIPE0, usefifo, USB_HOST_NO, mbw);
+
+ usb1_host_clear_transaction_counter(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb1_host_aclrm(pipe);
+#endif
+
+ status = usb1_host_write_buffer(pipe);
+
+ if (status != USB_HOST_FIFOERROR)
+ {
+ usb1_host_set_pid_buf(pipe);
+ }
+
+ return status;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer
+* Description : Writes data in the buffer allocated in the pipe specified by
+* : the argument. The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer (uint16_t pipe)
+{
+ uint16_t status;
+ uint16_t usefifo;
+
+ g_usb1_host_PipeIgnore[pipe] = 0;
+ usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ status = usb1_host_write_buffer_d0(pipe);
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ status = usb1_host_write_buffer_d1(pipe);
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ status = usb1_host_write_dma_d0(pipe);
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ status = usb1_host_write_dma_d1(pipe);
+ break;
+
+ default:
+ status = usb1_host_write_buffer_c(pipe);
+ break;
+ };
+
+ switch (status)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ usb1_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ usb1_host_enable_brdy_int(pipe); /* Enable Ready Interrupt */
+ break;
+
+ case USB_HOST_WRITEEND: /* End of data write */
+ case USB_HOST_WRITESHRT: /* End of data write */
+ usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+
+ usb1_host_clear_nrdy_sts(pipe);
+ usb1_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+
+ /* for last transfer */
+ usb1_host_enable_bemp_int(pipe); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_WRITEDMA: /* DMA write */
+ usb1_host_clear_nrdy_sts(pipe);
+ usb1_host_enable_nrdy_int(pipe); /* Error (NORES or STALL) */
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ usb1_host_disable_bemp_int(pipe); /* Disable Empty Interrupt */
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer_c
+* Description : Writes data in the buffer allocated in the pipe specified in
+* : the argument. Writes data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_CFIFO_WRITE, mbw);
+ }
+ else
+ {
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+ }
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb1_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb1_host_write_c_fifo(pipe, (uint16_t)count);
+
+ if (g_usb1_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb1_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB201.CFIFOCTR,
+ USB_CFIFOCTR_BVAL_SHIFT,
+ USB_CFIFOCTR_BVAL) == 0)
+ {
+ USB201.CFIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb1_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb1_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb1_host_write_d0_fifo(pipe, (uint16_t)count);
+
+ if (g_usb1_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb1_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB201.D0FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb1_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_buffer_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND ; Write end
+* : USB_HOST_WRITESHRT ; short data
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_WRITEDMA ; Write DMA
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_write_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] <= (uint32_t)size)
+ {
+ status = USB_HOST_WRITEEND; /* write continues */
+ count = g_usb1_host_data_count[pipe];
+
+ if (count == 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Null Packet is end of write */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+ }
+ else
+ {
+ status = USB_HOST_WRITING; /* write continues */
+ count = (uint32_t)size;
+ }
+
+ usb1_host_write_d1_fifo(pipe, (uint16_t)count);
+
+ if (g_usb1_host_data_count[pipe] < (uint32_t)size)
+ {
+ g_usb1_host_data_count[pipe] = 0;
+
+ if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ USB201.D1FIFOCTR = USB_HOST_BITBVAL; /* Short Packet */
+ }
+ }
+ else
+ {
+ g_usb1_host_data_count[pipe] -= count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D0FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb1_host_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND : Write end
+* : USB_HOST_WRITESHRT : short data
+* : USB_HOST_WRITING : Continue of data write
+* : USB_HOST_WRITEDMA : Write DMA
+* : USB_HOST_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_write_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb1_host_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb1_host_DmaPipe[USB_HOST_D0FIFO] = pipe;
+
+ if ((count % size) != 0)
+ {
+ g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 1;
+ }
+ else
+ {
+ g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 0;
+ }
+
+ dfacc = usb1_host_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA;
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_BUF2FIFO;
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].bytes = count;
+
+ Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+ usb1_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw, dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+
+ g_usb1_host_data_count[pipe] = 0;
+ g_usb1_host_data_pointer[pipe] += count;
+
+ status = USB_HOST_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB201.D0FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_dma_d1
+* Description : Writes data in the buffer allocated in the pipe specified in the argument.
+* : Writes data by DMA transfer using D1FIFO.
+* : The DMA-ch for using is specified by Userdef_USB_usb1_host_start_dma().
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_WRITEEND : Write end
+* : USB_HOST_WRITESHRT : short data
+* : USB_HOST_WRITING : Continue of data write
+* : USB_HOST_WRITEDMA : Write DMA
+* : USB_HOST_FIFOERROR : FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_write_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint16_t size;
+ uint16_t buffer;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+ count = g_usb1_host_data_count[pipe];
+
+ if (count != 0)
+ {
+ g_usb1_host_DmaPipe[USB_HOST_D1FIFO] = pipe;
+
+ if ((count % size) != 0)
+ {
+ g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 1;
+ }
+ else
+ {
+ g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 0;
+ }
+
+ dfacc = usb1_host_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA;
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_BUF2FIFO;
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].bytes = count;
+
+ Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+ usb1_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw , dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+
+ g_usb1_host_data_count[pipe] = 0;
+ g_usb1_host_data_pointer[pipe] += count;
+
+ status = USB_HOST_WRITEDMA; /* DMA write */
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&USB201.D1FIFOCTR,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL) == 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL); /* Short Packet */
+ }
+ status = USB_HOST_WRITESHRT; /* Short Packet is end of write */
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_transfer
+* Description : Starts USB data reception using the pipe specified in the argument.
+* : The FIFO for using is set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+void usb1_host_start_receive_transfer (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t usefifo;
+
+ usb1_host_clear_bemp_sts(pipe);
+ usb1_host_clear_brdy_sts(pipe);
+ usb1_host_clear_nrdy_sts(pipe);
+
+ usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ usb1_host_start_receive_trns_d0(pipe, size, data);
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ usb1_host_start_receive_trns_d1(pipe, size, data);
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ usb1_host_start_receive_dma_d0(pipe, size, data);
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ usb1_host_start_receive_dma_d1(pipe, size, data);
+ break;
+
+ default:
+ usb1_host_start_receive_trns_c(pipe, size, data);
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_trns_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* : When storing data in the buffer allocated in the pipe specified in the
+* : argument, BRDY interrupt is generated to read data
+* : in the interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_trns_c (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_host_set_pid_nak(pipe);
+ g_usb1_host_data_count[pipe] = size;
+ g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_host_PipeIgnore[pipe] = 0;
+
+ g_usb1_host_PipeDataSize[pipe] = size;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb1_host_get_mbw(size, (uint32_t)data);
+ usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_CFIFO_READ, mbw);
+ USB201.CFIFOCTR = USB_HOST_BITBCLR;
+
+ usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb1_host_aclrm(pipe);
+#endif
+
+ usb1_host_enable_nrdy_int(pipe);
+ usb1_host_enable_brdy_int(pipe);
+
+ usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_trns_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data in the
+* : interrupt.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_trns_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_host_set_pid_nak(pipe);
+ g_usb1_host_data_count[pipe] = size;
+ g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_host_PipeIgnore[pipe] = 0;
+
+ g_usb1_host_PipeDataSize[pipe] = size;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb1_host_get_mbw(size, (uint32_t)data);
+ usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb1_host_aclrm(pipe);
+#endif
+
+ usb1_host_enable_nrdy_int(pipe);
+ usb1_host_enable_brdy_int(pipe);
+
+ usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_trns_d1
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, BRDY interrupt is generated to read data.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_trns_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_host_set_pid_nak(pipe);
+ g_usb1_host_data_count[pipe] = size;
+ g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_host_PipeIgnore[pipe] = 0;
+
+ g_usb1_host_PipeDataSize[pipe] = size;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb1_host_get_mbw(size, (uint32_t)data);
+ usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb1_host_aclrm(pipe);
+#endif
+
+ usb1_host_enable_nrdy_int(pipe);
+ usb1_host_enable_brdy_int(pipe);
+
+ usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_dma_d0
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_dma_d0 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_host_set_pid_nak(pipe);
+ g_usb1_host_data_count[pipe] = size;
+ g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_host_PipeIgnore[pipe] = 0;
+
+ g_usb1_host_PipeDataSize[pipe] = 0;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb1_host_get_mbw(size, (uint32_t)data);
+ usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb1_host_aclrm(pipe);
+#endif
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb1_host_read_dma(pipe);
+
+ usb1_host_enable_nrdy_int(pipe);
+ usb1_host_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb1_host_enable_nrdy_int(pipe);
+ usb1_host_enable_brdy_int(pipe);
+ }
+
+ usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_start_receive_dma_d1
+* Description : Read data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* : This function does not read data from the buffer.
+* : When storing data in the buffer allocated in the pipe specified
+* : in the argument, delivered read request to DMAC to read data from
+* : the buffer by DMAC.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t size ; Data Size
+* : uint8_t *data ; Data Address
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_start_receive_dma_d1 (uint16_t pipe, uint32_t size, uint8_t * data)
+{
+ uint16_t mbw;
+
+ usb1_host_set_pid_nak(pipe);
+ g_usb1_host_data_count[pipe] = size;
+ g_usb1_host_data_pointer[pipe] = (uint8_t *)data;
+ g_usb1_host_PipeIgnore[pipe] = 0;
+
+ g_usb1_host_PipeDataSize[pipe] = 0;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_WAIT;
+
+ mbw = usb1_host_get_mbw(size, (uint32_t)data);
+ usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ usb1_host_set_transaction_counter(pipe, size);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb1_host_aclrm(pipe);
+#endif
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ usb1_host_read_dma(pipe);
+
+ usb1_host_enable_nrdy_int(pipe);
+ usb1_host_enable_brdy_int(pipe);
+ }
+ else
+ {
+ usb1_host_enable_nrdy_int(pipe);
+ usb1_host_enable_brdy_int(pipe);
+ }
+
+ usb1_host_set_pid_buf(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Uses FIF0 set in the pipe definition table.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb1_host_PipeIgnore[pipe] = 0;
+
+ if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+ {
+ status = usb1_host_read_buffer_d0(pipe);
+ }
+ else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+ {
+ status = usb1_host_read_buffer_d1(pipe);
+ }
+ else
+ {
+ status = usb1_host_read_buffer_c(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb1_host_disable_brdy_int(pipe);
+ g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_USE)
+ {
+ USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_USE)
+ {
+ USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+#if(1) /* ohci_wrapp */
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#else
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+#endif
+ g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer_c
+* Description : Reads data from the buffer allocated in the pipe specified in the argument.
+* : Reads data by CPU transfer using CFIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer_c (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_CUSE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb1_host_data_count[pipe];
+ }
+ else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb1_host_read_c_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb1_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer_d0
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by CPU transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb1_host_data_count[pipe];
+ }
+ else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb1_host_read_d0_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb1_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_buffer_d1
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by CPU transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_buffer_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t pipebuf_size;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1USE, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ count = g_usb1_host_data_count[pipe];
+ }
+ else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) !=0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ else
+ {
+ pipebuf_size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ usb1_host_set_pid_nak(pipe); /* Set NAK */
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ }
+ else
+ {
+ usb1_host_read_d1_fifo(pipe, (uint16_t)count);
+ }
+
+ g_usb1_host_data_count[pipe] -= count;
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_dma
+* Description : Reads data from the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO or D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+uint16_t usb1_host_read_dma (uint16_t pipe)
+{
+ uint16_t status;
+
+ g_usb1_host_PipeIgnore[pipe] = 0;
+
+ if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+ {
+ status = usb1_host_read_dma_d0(pipe);
+ }
+ else
+ {
+ status = usb1_host_read_dma_d1(pipe);
+ }
+
+ switch (status)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READZERO: /* End of data read */
+ usb1_host_disable_brdy_int(pipe);
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb1_host_disable_brdy_int(pipe);
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+ }
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ g_usb1_host_PipeDataSize[pipe] -= g_usb1_host_data_count[pipe];
+ }
+#if(1) /* ohci_wrapp */
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#else
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+#endif
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access status */
+ default:
+ usb1_host_disable_brdy_int(pipe); /* Disable Ready Interrupt */
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_ERROR;
+ break;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_dma_d0
+* Description : Writes data in the buffer allocated in the pipe specified
+* : in the argument.
+* : Reads data by DMA transfer using D0FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_read_dma_d0 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb1_host_data_count[pipe];
+ status = USB_HOST_READING;
+ }
+ else
+ {
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ count = g_usb1_host_data_count[pipe];
+ }
+ else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ status = USB_HOST_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb1_host_set_curpipe(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb1_host_set_dfacc_d0(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_host_DmaPipe[USB_HOST_D0FIFO] = pipe; /* not use in read operation */
+ g_usb1_host_DmaBval[USB_HOST_D0FIFO] = 0; /* not use in read operation */
+
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].fifo = USB_HOST_D0FIFO_DMA;
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].dir = USB_HOST_FIFO2BUF;
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+ g_usb1_host_DmaInfo[USB_HOST_D0FIFO].bytes = count;
+
+ if (status == USB_HOST_READING)
+ {
+ g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSY;
+ }
+ else
+ {
+ g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D0FIFO], dfacc);
+
+ usb1_host_set_curpipe2(pipe, USB_HOST_D0DMA, USB_HOST_NO, mbw , dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb1_host_data_count[pipe] -= count;
+ g_usb1_host_data_pointer[pipe] += count;
+ g_usb1_host_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_dma_d1
+* Description : Reads data from the buffer allocated in the pipe specified in
+* : the argument.
+* : Reads data by DMA transfer using D1FIFO.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : USB_HOST_READEND ; Read end
+* : USB_HOST_READSHRT ; short data
+* : USB_HOST_READZERO ; zero data
+* : USB_HOST_READING ; Continue of data read
+* : USB_HOST_READOVER ; buffer over
+* : USB_HOST_FIFOERROR ; FIFO status
+*******************************************************************************/
+static uint16_t usb1_host_read_dma_d1 (uint16_t pipe)
+{
+ uint32_t count;
+ uint32_t dtln;
+ uint16_t buffer;
+ uint16_t mxps;
+ uint16_t status;
+ uint16_t mbw;
+ uint16_t dfacc = 0;
+ uint16_t pipebuf_size;
+
+ g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[pipe], (uint32_t)g_usb1_host_data_pointer[pipe]);
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ count = g_usb1_host_data_count[pipe];
+ status = USB_HOST_READING;
+ }
+ else
+ {
+ buffer = usb1_host_change_fifo_port(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+
+ if (buffer == USB_HOST_FIFOERROR) /* FIFO access status */
+ {
+ return USB_HOST_FIFOERROR;
+ }
+
+ dtln = (uint32_t)(buffer & USB_HOST_BITDTLN);
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if (g_usb1_host_data_count[pipe] < dtln) /* Buffer Over ? */
+ {
+ status = USB_HOST_READOVER;
+ count = g_usb1_host_data_count[pipe];
+ }
+ else if (g_usb1_host_data_count[pipe] == dtln) /* just Receive Size */
+ {
+ status = USB_HOST_READEND;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ else /* continue Receive data */
+ {
+ status = USB_HOST_READING;
+ count = dtln;
+
+ if (count == 0)
+ {
+ status = USB_HOST_READSHRT; /* Null Packet receive */
+ }
+
+ if ((count % mxps) != 0)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ else
+ {
+ pipebuf_size = usb1_host_get_buf_size(pipe); /* Data buffer size */
+
+ if (count != pipebuf_size)
+ {
+ status = USB_HOST_READSHRT; /* Short Packet receive */
+ }
+ }
+ }
+ }
+
+ if (count == 0) /* 0 length packet */
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Clear BCLR */
+ status = USB_HOST_READZERO; /* Null Packet receive */
+ }
+ else
+ {
+ usb1_host_set_curpipe(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw);
+ /* transaction counter No set */
+ /* FRDY = 1, DTLN = 0 -> BRDY */
+ }
+ }
+ else
+ {
+ dfacc = usb1_host_set_dfacc_d1(mbw, count);
+
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 2; /* 32bit transfer */
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 1; /* 16bit transfer */
+ }
+ else
+ {
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size = 0; /* 8bit transfer */
+ }
+
+ g_usb1_host_DmaPipe[USB_HOST_D1FIFO] = pipe; /* not use in read operation */
+ g_usb1_host_DmaBval[USB_HOST_D1FIFO] = 0; /* not use in read operation */
+
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].fifo = USB_HOST_D1FIFO_DMA;
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].dir = USB_HOST_FIFO2BUF;
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].buffer = (uint32_t)g_usb1_host_data_pointer[pipe];
+ g_usb1_host_DmaInfo[USB_HOST_D1FIFO].bytes = count;
+
+ if (status == USB_HOST_READING)
+ {
+ g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSY;
+ }
+ else
+ {
+ g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_BUSYEND;
+ }
+
+ Userdef_USB_usb1_host_start_dma(&g_usb1_host_DmaInfo[USB_HOST_D1FIFO], dfacc);
+
+ usb1_host_set_curpipe2(pipe, USB_HOST_D1DMA, USB_HOST_NO, mbw , dfacc);
+
+ RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+ 1,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ g_usb1_host_data_count[pipe] -= count;
+ g_usb1_host_data_pointer[pipe] += count;
+ g_usb1_host_PipeDataSize[pipe] += count;
+ }
+
+ return status; /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_change_fifo_port
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument. After allocating FIF0, waits in the software
+* : till the corresponding pipe becomes ready.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : USB_HOST_FIFOERROR ; Error
+* : Others ; CFIFOCTR/D0FIFOCTR/D1FIFOCTR Register Value
+*******************************************************************************/
+uint16_t usb1_host_change_fifo_port (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ usb1_host_set_curpipe(pipe, fifosel, isel, mbw);
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB201.CFIFOCTR;
+ break;
+
+ case USB_HOST_D0USE:
+ case USB_HOST_D0DMA:
+ buffer = USB201.D0FIFOCTR;
+ break;
+
+ case USB_HOST_D1USE:
+ case USB_HOST_D1DMA:
+ buffer = USB201.D1FIFOCTR;
+ break;
+
+ default:
+ buffer = 0;
+ break;
+ }
+
+ if ((buffer & USB_HOST_BITFRDY) == USB_HOST_BITFRDY)
+ {
+ return buffer;
+ }
+
+ loop2 = 25;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ return USB_HOST_FIFOERROR;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_curpipe
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_curpipe (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw)
+{
+ uint16_t buffer;
+ uint32_t loop;
+ volatile uint32_t loop2;
+
+ g_usb1_host_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB201.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D0USE:
+ buffer = USB201.D0FIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D1DMA:
+ case USB_HOST_D1USE:
+ buffer = USB201.D1FIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_curpipe2
+* Description : Allocates FIF0 specified by the argument in the pipe assigned
+* : by the argument.(DFACC)
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t fifosel ; Select FIFO
+* : uint16_t isel ; FIFO Access Direction
+* : uint16_t mbw ; FIFO Port Access Bit Width
+* : uint16_t dfacc ; DFACC Access mode
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_curpipe2 (uint16_t pipe, uint16_t fifosel, uint16_t isel, uint16_t mbw, uint16_t dfacc)
+{
+ uint16_t buffer;
+ uint32_t loop;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ uint32_t dummy;
+#endif
+ volatile uint32_t loop2;
+
+ g_usb1_host_mbw[pipe] = mbw;
+
+ switch (fifosel)
+ {
+ case USB_HOST_CUSE:
+ buffer = USB201.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(~isel & USB_HOST_BITISEL);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+ buffer &= (uint16_t)~(USB_HOST_BITISEL | USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(isel | pipe | mbw);
+ USB201.CFIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.CFIFOSEL & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE))
+ == (buffer & (USB_HOST_BITISEL | USB_HOST_BITCURPIPE)))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D0USE:
+ buffer = USB201.D0FIFOSEL;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB201.D0FIFO.UINT32;
+ }
+#endif
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D0FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D0FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ case USB_HOST_D1DMA:
+ case USB_HOST_D1USE:
+ buffer = USB201.D1FIFOSEL;
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+
+ if (dfacc != 0)
+ {
+ buffer |= (uint16_t)(USB_HOST_BITMBW_32);
+ }
+#else
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+#endif
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+
+#ifdef __USB_HOST_DF_ACC_ENABLE__
+ if (dfacc != 0)
+ {
+ dummy = USB201.D1FIFO.UINT32;
+ loop = dummy; // avoid warning.
+ }
+#endif
+
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE | USB_HOST_BITMBW);
+ buffer |= (uint16_t)(pipe | mbw);
+ USB201.D1FIFOSEL = buffer;
+
+ for (loop = 0; loop < 4; loop++)
+ {
+ if ((USB201.D1FIFOSEL & USB_HOST_BITCURPIPE) == (buffer & USB_HOST_BITCURPIPE))
+ {
+ break;
+ }
+
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ /* Cautions !!!
+ * Depending on the external bus speed of CPU, you may need to wait for 450ns here.
+ * For details, please look at the data sheet. */
+ loop2 = 100;
+ while (loop2-- > 0)
+ {
+ /* wait */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_c_fifo
+* Description : Writes data in CFIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_write_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB201.CFIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe];
+ g_usb1_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB201.CFIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]);
+ g_usb1_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB201.CFIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]);
+ g_usb1_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_c_fifo
+* Description : Reads data from CFIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_read_c_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb1_host_data_pointer[pipe] = USB201.CFIFO.UINT8[HH];
+ g_usb1_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.CFIFO.UINT16[H];
+ g_usb1_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.CFIFO.UINT32;
+ g_usb1_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_d0_fifo
+* Description : Writes data in D0FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating CFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_write_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB201.D0FIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe];
+ g_usb1_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB201.D0FIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]);
+ g_usb1_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB201.D0FIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]);
+ g_usb1_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_d0_fifo
+* Description : Reads data from D0FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating DOFIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb0_host_mbw[].
+* Arguments : uint16_t Pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_read_d0_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb1_host_data_pointer[pipe] = USB201.D0FIFO.UINT8[HH];
+ g_usb1_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.D0FIFO.UINT16[H];
+ g_usb1_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.D0FIFO.UINT32;
+ g_usb1_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_write_d1_fifo
+* Description : Writes data in D1FIFO.
+* : Writes data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_write_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ USB201.D1FIFO.UINT8[HH] = *g_usb1_host_data_pointer[pipe];
+ g_usb1_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)(count / 2); even; --even)
+ {
+ USB201.D1FIFO.UINT16[H] = *((uint16_t *)g_usb1_host_data_pointer[pipe]);
+ g_usb1_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)(count / 4); even; --even)
+ {
+ USB201.D1FIFO.UINT32 = *((uint32_t *)g_usb1_host_data_pointer[pipe]);
+ g_usb1_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_read_d1_fifo
+* Description : Reads data from D1FIFO.
+* : Reads data by BYTE/WORD/LONG according to access size
+* : to the pipe specified by the arguments.
+* : Before executing this function, allocating D1FIF0 in the specified pipe
+* : should be completed.
+* : Before executing this function, access size to the specified pipe
+* : should be fixed and set in g_usb1_host_mbw[].
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint16_t count ; Data Size(Byte)
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_read_d1_fifo (uint16_t pipe, uint16_t count)
+{
+ uint16_t even;
+
+ if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_8)
+ {
+ for (even = count; even; --even)
+ {
+ *g_usb1_host_data_pointer[pipe] = USB201.D1FIFO.UINT8[HH];
+ g_usb1_host_data_pointer[pipe] += 1;
+ }
+ }
+ else if (g_usb1_host_mbw[pipe] == USB_HOST_BITMBW_16)
+ {
+ for (even = (uint16_t)((count + 1) / 2); even; --even)
+ {
+ *((uint16_t *)g_usb1_host_data_pointer[pipe]) = USB201.D1FIFO.UINT16[H];
+ g_usb1_host_data_pointer[pipe] += 2;
+ }
+ }
+ else
+ {
+ for (even = (uint16_t)((count + 3) / 4); even; --even)
+ {
+ *((uint32_t *)g_usb1_host_data_pointer[pipe]) = USB201.D1FIFO.UINT32;
+ g_usb1_host_data_pointer[pipe] += 4;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_com_get_dmasize
+* Description : Calculates access width of DMA transfer by the argument to
+ return as the Return Value.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : DMA transfer size : 0 8bit
+* : : 1 16bit
+* : : 2 32bit
+*******************************************************************************/
+static uint32_t usb1_host_com_get_dmasize (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+
+ if (((trncount & 0x0001) != 0) || ((dtptr & 0x00000001) != 0))
+ {
+ /* When transfer byte count is odd */
+ /* or transfer data area is 8-bit alignment */
+ size = 0; /* 8bit */
+ }
+ else if (((trncount & 0x0003) != 0) || ((dtptr & 0x00000003) != 0))
+ {
+ /* When the transfer byte count is multiples of 2 */
+ /* or the transfer data area is 16-bit alignment */
+ size = 1; /* 16bit */
+ }
+ else
+ {
+ /* When the transfer byte count is multiples of 4 */
+ /* or the transfer data area is 32-bit alignment */
+ size = 2; /* 32bit */
+ }
+
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_mbw
+* Description : Calculates access width of DMA to return the value set in MBW.
+* Arguments : uint32_t trncount : transfer byte
+* : uint32_t dtptr : transfer data pointer
+* Return Value : FIFO transfer size : USB_HOST_BITMBW_8 8bit
+* : : USB_HOST_BITMBW_16 16bit
+* : : USB_HOST_BITMBW_32 32bit
+*******************************************************************************/
+uint16_t usb1_host_get_mbw (uint32_t trncount, uint32_t dtptr)
+{
+ uint32_t size;
+ uint16_t mbw;
+
+ size = usb1_host_com_get_dmasize(trncount, dtptr);
+
+ if (size == 0)
+ {
+ /* 8bit */
+ mbw = USB_HOST_BITMBW_8;
+ }
+ else if (size == 1)
+ {
+ /* 16bit */
+ mbw = USB_HOST_BITMBW_16;
+ }
+ else
+ {
+ /* 32bit */
+ mbw = USB_HOST_BITMBW_32;
+ }
+
+ return mbw;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_transaction_counter
+* Description : Sets transaction counter by the argument(PIPEnTRN).
+* : Clears transaction before setting to enable transaction counter setting.
+* Arguments : uint16_t pipe ; Pipe number
+* : uint32_t bsize : Data transfer size
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_set_transaction_counter (uint16_t pipe, uint32_t bsize)
+{
+ uint16_t mxps;
+ uint16_t cnt;
+
+ if (bsize == 0)
+ {
+ return;
+ }
+
+ mxps = usb1_host_get_mxps(pipe); /* Max Packet Size */
+
+ if ((bsize % mxps) == 0)
+ {
+ cnt = (uint16_t)(bsize / mxps);
+ }
+ else
+ {
+ cnt = (uint16_t)((bsize / mxps) + 1);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE1TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE2TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE3TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE4TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE5TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ USB201.PIPE9TRN = cnt;
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_transaction_counter
+* Description : Clears the transaction counter by the argument.
+* : After executing this function, the transaction counter is invalid.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_transaction_counter (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE1TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE2TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE3TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE4TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE5TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 0,
+ USB_PIPEnTRE_TRENB_SHIFT,
+ USB_PIPEnTRE_TRENB);
+ RZA_IO_RegWrite_16(&USB201.PIPE9TRE,
+ 1,
+ USB_PIPEnTRE_TRCLR_SHIFT,
+ USB_PIPEnTRE_TRCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_stop_transfer
+* Description : Stops the USB transfer in the pipe specified by the argument.
+* : After stopping the USB transfer, clears the buffer allocated in
+* : the pipe.
+* : After executing this function, allocation in FIF0 becomes USB_HOST_PIPE0;
+* : invalid. After executing this function, BRDY/NRDY/BEMP interrupt
+* : in the corresponding pipe becomes invalid. Sequence bit is also
+* : cleared.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_stop_transfer (uint16_t pipe)
+{
+ uint16_t usefifo;
+ uint32_t remain;
+
+ usb1_host_set_pid_nak(pipe);
+
+ usefifo = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ switch (usefifo)
+ {
+ case USB_HOST_D0FIFO_USE:
+ usb1_host_clear_transaction_counter(pipe);
+ USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D1FIFO_USE:
+ usb1_host_clear_transaction_counter(pipe);
+ USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D0FIFO_DMA:
+ remain = Userdef_USB_usb1_host_stop_dma0();
+ usb1_host_dma_stop_d0(pipe, remain);
+ usb1_host_clear_transaction_counter(pipe);
+ USB201.D0FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ case USB_HOST_D1FIFO_DMA:
+ remain = Userdef_USB_usb1_host_stop_dma1();
+ usb1_host_dma_stop_d1(pipe, remain);
+ usb1_host_clear_transaction_counter(pipe);
+ USB201.D1FIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+
+ default:
+ usb1_host_clear_transaction_counter(pipe);
+ USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+ break;
+ }
+
+ /* Interrupt of pipe set is disabled */
+ usb1_host_disable_brdy_int(pipe);
+ usb1_host_disable_nrdy_int(pipe);
+ usb1_host_disable_bemp_int(pipe);
+
+#if(1) /* ohci_wrapp */
+#else
+ usb1_host_aclrm(pipe);
+#endif
+ usb1_host_set_csclr(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_dfacc_d0
+* Description : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb1_host_set_dfacc_d0 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D0FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+
+ return dfacc;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_dfacc_d1
+* Description : Sets the DFACC setting value in D0FIFO using the transfer size.
+* Arguments : uint16_t mbw ; MBW
+* : uint16_t count ; data count
+* Return Value : DFACC Access mode
+*******************************************************************************/
+static uint16_t usb1_host_set_dfacc_d1 (uint16_t mbw, uint32_t count)
+{
+ uint16_t dfacc = 0;
+
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+#else
+ if (mbw == USB_HOST_BITMBW_32)
+ {
+ if ((count % 32) == 0)
+ {
+ /* 32byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 2,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 2;
+ }
+ else if ((count % 16) == 0)
+ {
+ /* 16byte transfer */
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 1,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 1;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ }
+ else if (mbw == USB_HOST_BITMBW_16)
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ RZA_IO_RegWrite_16(&USB201.D1FBCFG,
+ 0,
+ USB_DnFBCFG_TENDE_SHIFT,
+ USB_DnFBCFG_TENDE);
+ dfacc = 0;
+ }
+#endif
+
+ return dfacc;
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dma.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dma.c
new file mode 100644
index 000000000..6c8a5f9d7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_dma.c
@@ -0,0 +1,355 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_dma.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+/* #include "usb1_host_dmacdrv.h" */
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+static void usb1_host_dmaint(uint16_t fifo);
+static void usb1_host_dmaint_buf2fifo(uint16_t pipe);
+static void usb1_host_dmaint_fifo2buf(uint16_t pipe);
+
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_stop_d0
+* Description : D0FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_stop_d0 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB201.D0FBCFG,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb1_host_DmaInfo[USB_HOST_D0FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ buffer = USB201.D0FIFOCTR;
+ dtln = (buffer & USB_HOST_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb1_host_PipeDataSize[pipe] = (g_usb1_host_data_count[pipe] - remain);
+ g_usb1_host_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB201.D0FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_stop_d1
+* Description : D1FIFO DMA stop
+* Arguments : uint16_t pipe : pipe number
+* : uint32_t remain : transfer byte
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_stop_d1 (uint16_t pipe, uint32_t remain)
+{
+ uint16_t dtln;
+ uint16_t dfacc;
+ uint16_t buffer;
+ uint16_t sds_b = 1;
+
+ dfacc = RZA_IO_RegRead_16(&USB201.D1FBCFG,
+ USB_DnFBCFG_DFACC_SHIFT,
+ USB_DnFBCFG_DFACC);
+ if (dfacc == 2)
+ {
+ sds_b = 32;
+ }
+ else if (dfacc == 1)
+ {
+ sds_b = 16;
+ }
+ else
+ {
+ if (g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size == 2)
+ {
+ sds_b = 4;
+ }
+ else if (g_usb1_host_DmaInfo[USB_HOST_D1FIFO].size == 1)
+ {
+ sds_b = 2;
+ }
+ else
+ {
+ sds_b = 1;
+ }
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 1)
+ {
+ if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ buffer = USB201.D1FIFOCTR;
+ dtln = (buffer & USB_HOST_BITDTLN);
+
+ if ((dtln % sds_b) != 0)
+ {
+ remain += (sds_b - (dtln % sds_b));
+ }
+ g_usb1_host_PipeDataSize[pipe] = (g_usb1_host_data_count[pipe] - remain);
+ g_usb1_host_data_count[pipe] = remain;
+ }
+ }
+
+ RZA_IO_RegWrite_16(&USB201.D1FIFOSEL,
+ 0,
+ USB_DnFIFOSEL_DREQE_SHIFT,
+ USB_DnFIFOSEL_DREQE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_interrupt_d0fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb1_host_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_HOST_D0FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_interrupt_d0fifo (uint32_t int_sense)
+{
+ usb1_host_dmaint(USB_HOST_D0FIFO);
+ g_usb1_host_DmaStatus[USB_HOST_D0FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dma_interrupt_d1fifo
+* Description : This function is DMA interrupt handler entry.
+* : Execute usb0_host_dmaint() after disabling DMA interrupt in this function.
+* : Disable DMA interrupt to DMAC executed when USB_HOST_D1FIFO_DMA is
+* : specified by dma->fifo.
+* : Register this function as DMA complete interrupt.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_host_dma_interrupt_d1fifo (uint32_t int_sense)
+{
+ usb1_host_dmaint(USB_HOST_D1FIFO);
+ g_usb1_host_DmaStatus[USB_HOST_D1FIFO] = USB_HOST_DMA_READY;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dmaint
+* Description : This function is DMA transfer end interrupt
+* Arguments : uint16_t fifo ; fifo number
+* : ; USB_HOST_D0FIFO
+* : ; USB_HOST_D1FIFO
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_dmaint (uint16_t fifo)
+{
+ uint16_t pipe;
+
+ pipe = g_usb1_host_DmaPipe[fifo];
+
+ if (g_usb1_host_DmaInfo[fifo].dir == USB_HOST_BUF2FIFO)
+ {
+ usb1_host_dmaint_buf2fifo(pipe);
+ }
+ else
+ {
+ usb1_host_dmaint_fifo2buf(pipe);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dmaint_fifo2buf
+* Description : Executes read completion from FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_dmaint_fifo2buf (uint16_t pipe)
+{
+ uint32_t remain;
+ uint16_t useport;
+
+ if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_DONE)
+ {
+ useport = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ if (useport == USB_HOST_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb1_host_stop_dma0();
+ usb1_host_dma_stop_d0(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb1_host_DmaStatus[USB_HOST_D0FIFO] == USB_HOST_DMA_BUSYEND)
+ {
+ USB201.D0FIFOCTR = USB_HOST_BITBCLR;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ else
+ {
+ usb1_host_enable_brdy_int(pipe);
+ }
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb1_host_stop_dma1();
+ usb1_host_dma_stop_d1(pipe, remain);
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ if (g_usb1_host_DmaStatus[USB_HOST_D1FIFO] == USB_HOST_DMA_BUSYEND)
+ {
+ USB201.D1FIFOCTR = USB_HOST_BITBCLR;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ else
+ {
+ usb1_host_enable_brdy_int(pipe);
+ }
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_dmaint_buf2fifo
+* Description : Executes write completion in FIFO by DMAC.
+* Arguments : uint16_t pipe : pipe number
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_dmaint_buf2fifo (uint16_t pipe)
+{
+ uint16_t useport;
+ uint32_t remain;
+
+ useport = (uint16_t)(g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE);
+
+ if (useport == USB_HOST_D0FIFO_DMA)
+ {
+ remain = Userdef_USB_usb1_host_stop_dma0();
+ usb1_host_dma_stop_d0(pipe, remain);
+
+ if (g_usb1_host_DmaBval[USB_HOST_D0FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D0FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+ else
+ {
+ remain = Userdef_USB_usb1_host_stop_dma1();
+ usb1_host_dma_stop_d1(pipe, remain);
+
+ if (g_usb1_host_DmaBval[USB_HOST_D1FIFO] != 0)
+ {
+ RZA_IO_RegWrite_16(&USB201.D1FIFOCTR,
+ 1,
+ USB_DnFIFOCTR_BVAL_SHIFT,
+ USB_DnFIFOCTR_BVAL);
+ }
+ }
+
+ usb1_host_enable_bemp_int(pipe);
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_intrn.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_intrn.c
new file mode 100644
index 000000000..503ec7a13
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_intrn.c
@@ -0,0 +1,285 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_intrn.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_brdy_int
+* Description : Executes BRDY interrupt(USB_HOST_PIPE1-9).
+* : According to the pipe that interrupt is generated in,
+* : reads/writes buffer allocated in the pipe.
+* : This function is executed in the BRDY interrupt handler.
+* : This function clears BRDY interrupt status and BEMP interrupt
+* : status.
+* Arguments : uint16_t status ; BRDYSTS Register Value
+* : uint16_t int_enb ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_brdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint32_t int_sense = 0;
+ uint16_t pipe;
+ uint16_t pipebit;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ pipebit = g_usb1_host_bit_set[pipe];
+
+ if ((status & pipebit) && (int_enb & pipebit))
+ {
+ USB201.BRDYSTS = (uint16_t)~pipebit;
+ USB201.BEMPSTS = (uint16_t)~pipebit;
+
+ if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D0FIFO_DMA)
+ {
+ if (g_usb1_host_DmaStatus[USB_HOST_D0FIFO] != USB_HOST_DMA_READY)
+ {
+ usb1_host_dma_interrupt_d0fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb1_host_read_dma(pipe);
+ usb1_host_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB201.D0FIFOCTR = USB_HOST_BITBCLR;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ }
+ else if ((g_usb1_host_PipeTbl[pipe] & USB_HOST_FIFO_USE) == USB_HOST_D1FIFO_DMA)
+ {
+ if (g_usb1_host_DmaStatus[USB_HOST_D1FIFO] != USB_HOST_DMA_READY)
+ {
+ usb1_host_dma_interrupt_d1fifo(int_sense);
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_BFRE_SHIFT, USB_PIPECFG_BFRE) == 0)
+ {
+ usb1_host_read_dma(pipe);
+ usb1_host_disable_brdy_int(pipe);
+ }
+ else
+ {
+ USB201.D1FIFOCTR = USB_HOST_BITBCLR;
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+ }
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+ {
+ usb1_host_read_buffer(pipe);
+ }
+ else
+ {
+ usb1_host_write_buffer(pipe);
+ }
+ }
+#if(1) /* ohci_wrapp */
+ switch (g_usb1_host_pipe_status[pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+ break;
+ case USB_HOST_PIPE_NORES:
+ case USB_HOST_PIPE_STALL:
+ case USB_HOST_PIPE_ERROR:
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+ break;
+ default:
+ /* Do Nothing */
+ break;
+ }
+#endif
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_nrdy_int
+* Description : Executes NRDY interrupt(USB_HOST_PIPE1-9).
+* : Checks NRDY interrupt cause by PID. When the cause if STALL,
+* : regards the pipe state as STALL and ends the processing.
+* : Then the cause is not STALL, increments the error count to
+* : communicate again. When the error count is 3, determines
+* : the pipe state as USB_HOST_PIPE_NORES and ends the processing.
+* : This function is executed in the NRDY interrupt handler.
+* : This function clears NRDY interrupt status.
+* Arguments : uint16_t status ; NRDYSTS Register Value
+* : uint16_t int_enb ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_nrdy_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB201.NRDYSTS = (uint16_t)~status;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb1_host_bit_set[pipe]) == g_usb1_host_bit_set[pipe])
+ {
+ if (RZA_IO_RegRead_16(&USB201.SYSCFG0,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM) == 1)
+ {
+ if (g_usb1_host_pipe_status[pipe] == USB_HOST_PIPE_WAIT)
+ {
+ pid = usb1_host_get_pid(pipe);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+#if(1) /* ohci_wrapp */
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_DEVICENOTRESPONDING);
+#else
+ g_usb1_host_PipeIgnore[pipe]++;
+
+ if (g_usb1_host_PipeIgnore[pipe] == 3)
+ {
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_NORES;
+ }
+ else
+ {
+ usb1_host_set_pid_buf(pipe);
+ }
+#endif
+ }
+ }
+ }
+ else
+ {
+ /* USB Function */
+ }
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_bemp_int
+* Description : Executes BEMP interrupt(USB_HOST_PIPE1-9).
+* Arguments : uint16_t status ; BEMPSTS Register Value
+* : uint16_t int_enb ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_bemp_int (uint16_t status, uint16_t int_enb)
+{
+ uint16_t pid;
+ uint16_t pipe;
+ uint16_t bitcheck;
+ uint16_t inbuf;
+
+ bitcheck = (uint16_t)(status & int_enb);
+
+ USB201.BEMPSTS = (uint16_t)~status;
+
+ for (pipe = USB_HOST_PIPE1; pipe <= USB_HOST_MAX_PIPE_NO; pipe++)
+ {
+ if ((bitcheck&g_usb1_host_bit_set[pipe]) == g_usb1_host_bit_set[pipe])
+ {
+ pid = usb1_host_get_pid(pipe);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_STALL;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+ inbuf = usb1_host_get_inbuf(pipe);
+
+ if (inbuf == 0)
+ {
+ usb1_host_disable_bemp_int(pipe);
+ usb1_host_set_pid_nak(pipe);
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_DONE;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(pipe, TD_CC_NOERROR);
+#endif
+ }
+ }
+ }
+ }
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_lib.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_lib.c
new file mode 100644
index 000000000..b242794fa
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/common/usb1_host_lib.c
@@ -0,0 +1,1598 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_lib.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#if(1) /* ohci_wrapp */
+#include "MBRZA1H.h" /* INTC Driver Header */
+#else
+#include "devdrv_intc.h" /* INTC Driver Header */
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_brdy_int
+* Description : Enables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_enable_brdy_int (uint16_t pipe)
+{
+ /* enable brdy interrupt */
+ USB201.BRDYENB |= (uint16_t)g_usb1_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_disable_brdy_int
+* Description : Disables BRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BRDY. Enables BRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling BRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_disable_brdy_int (uint16_t pipe)
+{
+ /* disable brdy interrupt */
+ USB201.BRDYENB &= (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_brdy_sts
+* Description : Clear BRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_brdy_sts (uint16_t pipe)
+{
+ /* clear brdy status */
+ USB201.BRDYSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_bemp_int
+* Description : Enables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_enable_bemp_int (uint16_t pipe)
+{
+ /* enable bemp interrupt */
+ USB201.BEMPENB |= (uint16_t)g_usb1_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_disable_bemp_int
+* Description : Disables BEMP interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : BEMP. Enables BEMP interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling BEMP, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_disable_bemp_int (uint16_t pipe)
+{
+ /* disable bemp interrupt */
+ USB201.BEMPENB &= (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_bemp_sts
+* Description : Clear BEMP interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_bemp_sts (uint16_t pipe)
+{
+ /* clear bemp status */
+ USB201.BEMPSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_nrdy_int
+* Description : Enables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before enabling
+* : NRDY. Enables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After enabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_enable_nrdy_int (uint16_t pipe)
+{
+ /* enable nrdy interrupt */
+ USB201.NRDYENB |= (uint16_t)g_usb1_host_bit_set[pipe];
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_disable_nrdy_int
+* Description : Disables NRDY interrupt in the pipe spceified by the argument.
+* : Disables BEMP/NRDY/BRDY interrupts in all pipes before disabling
+* : NRDY. Disables NRDY interrupt in the pipe specified by the argument
+* : in the disabled status. After disabling NRDY, recover all
+* : BEMP/NRDY/BRDY disabled/enabled status.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_disable_nrdy_int (uint16_t pipe)
+{
+ /* disable nrdy interrupt */
+ USB201.NRDYENB &= (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_nrdy_sts
+* Description : Clear NRDY interrupt status in the pipe spceified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_nrdy_sts (uint16_t pipe)
+{
+ /* clear nrdy status */
+ USB201.NRDYSTS = (uint16_t)~(g_usb1_host_bit_set[pipe]);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_is_hispeed
+* Description : Returns the result of USB reset hand shake (RHST) as
+* : return value.
+* Arguments : none
+* Return Value : USB_HOST_HIGH_SPEED ; Hi-Speed
+* : USB_HOST_FULL_SPEED ; Full-Speed
+* : USB_HOST_LOW_SPEED ; Low-Speed
+* : USB_HOST_NON_SPEED ; error
+*******************************************************************************/
+uint16_t usb1_host_is_hispeed (void)
+{
+ uint16_t rhst;
+ uint16_t speed;
+
+ rhst = RZA_IO_RegRead_16(&USB201.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (rhst == USB_HOST_HSMODE)
+ {
+ speed = USB_HOST_HIGH_SPEED;
+ }
+ else if (rhst == USB_HOST_FSMODE)
+ {
+ speed = USB_HOST_FULL_SPEED;
+ }
+ else if (rhst == USB_HOST_LSMODE)
+ {
+ speed = USB_HOST_LOW_SPEED;
+ }
+ else
+ {
+ speed = USB_HOST_NON_SPEED;
+ }
+
+ return speed;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_is_hispeed_enable
+* Description : Returns the USB High-Speed connection enabled status as
+* : return value.
+* Arguments : none
+* Return Value : USB_HOST_YES : Hi-Speed Enable
+* : USB_HOST_NO : Hi-Speed Disable
+*******************************************************************************/
+uint16_t usb1_host_is_hispeed_enable (void)
+{
+ uint16_t ret;
+
+ ret = USB_HOST_NO;
+
+ if (RZA_IO_RegRead_16(&USB201.SYSCFG0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE) == 1)
+ {
+ ret = USB_HOST_YES;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_pid_buf
+* Description : Enables communicaqtion in the pipe specified by the argument
+* : (BUF).
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_pid_buf (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb1_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_STALL2)
+ {
+ usb1_host_set_pid_nak(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ USB_HOST_PID_BUF,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ USB_HOST_PID_BUF,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_pid_nak
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* : When the pipe status was enabling communication (BUF) before
+* : executing before executing this function, waits in the software
+* : until the pipe becomes ready after setting disabled.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_pid_nak (uint16_t pipe)
+{
+ uint16_t pid;
+ uint16_t pbusy;
+ uint32_t loop;
+
+ pid = usb1_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_STALL2)
+ {
+ usb1_host_set_pid_stall(pipe);
+ }
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ USB_HOST_PID_NAK,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ USB_HOST_PID_NAK,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+
+ if (pid == USB_HOST_PID_BUF)
+ {
+ for (loop = 0; loop < 200; loop++)
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ pbusy = RZA_IO_RegRead_16(&USB201.DCPCTR,
+ USB_DCPCTR_PBUSY_SHIFT,
+ USB_DCPCTR_PBUSY);
+ break;
+
+ case USB_HOST_PIPE1:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE2:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE3:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE4:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE5:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PBUSY_SHIFT,
+ USB_PIPEnCTR_1_5_PBUSY);
+ break;
+
+ case USB_HOST_PIPE6:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE7:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE8:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PBUSY_SHIFT,
+ USB_PIPEnCTR_6_8_PBUSY);
+ break;
+
+ case USB_HOST_PIPE9:
+ pbusy = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_PBUSY_SHIFT,
+ USB_PIPEnCTR_9_PBUSY);
+ break;
+
+ default:
+ pbusy = 1;
+ break;
+ }
+
+ if (pbusy == 0)
+ {
+ break;
+ }
+
+ Userdef_USB_usb1_host_delay_500ns();
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_pid_stall
+* Description : Disables communication (STALL) in the pipe specified by the
+* : argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_pid_stall (uint16_t pipe)
+{
+ uint16_t pid;
+
+ pid = usb1_host_get_pid(pipe);
+
+ if (pid == USB_HOST_PID_BUF)
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ USB_HOST_PID_STALL2,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ USB_HOST_PID_STALL2,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+ else
+ {
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ USB_HOST_PID_STALL,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ USB_HOST_PID_STALL,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ break;
+ }
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clear_pid_stall
+* Description : Disables communication (NAK) in the pipe specified by the argument.
+* Arguments : uint16_t pipe ; pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clear_pid_stall (uint16_t pipe)
+{
+ usb1_host_set_pid_nak(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_pid
+* Description : Returns the pipe state specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : PID
+*******************************************************************************/
+uint16_t usb1_host_get_pid (uint16_t pipe)
+{
+ uint16_t pid;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ pid = RZA_IO_RegRead_16(&USB201.DCPCTR,
+ USB_DCPCTR_PID_SHIFT,
+ USB_DCPCTR_PID);
+ break;
+
+ case USB_HOST_PIPE1:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE2:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE3:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE4:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE5:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_PID_SHIFT,
+ USB_PIPEnCTR_1_5_PID);
+ break;
+
+ case USB_HOST_PIPE6:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE7:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE8:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+ USB_PIPEnCTR_6_8_PID_SHIFT,
+ USB_PIPEnCTR_6_8_PID);
+ break;
+
+ case USB_HOST_PIPE9:
+ pid = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_PID_SHIFT,
+ USB_PIPEnCTR_9_PID);
+ break;
+
+ default:
+ pid = 0;
+ break;
+ }
+
+ return pid;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_csclr
+* Description : CSPLIT status clear setting of sprit transaction in specified
+* : pipe is performed.
+* : When SQSET bit or SQCLR bit, and SQSET bit or SQCLR bit
+* : in DCPCTR register are continuously changed (when the sequence
+* : toggle bit of data PID is continuously changed over two or more pipes),
+* : the access cycle with 120 ns and more than 5 cycle bus clock is necessary.
+* : Do not set both SQCLR bit and SQSET bit to 1 at the same time.
+* : In addition, both bits should be operated after PID is set to NAK.
+* : However, when it is set to the isochronous transfer as the transfer type
+* : (TYPE=11), writing in SQSET bit is disabled.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_csclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ 1,
+ USB_DCPCTR_CSCLR_SHIFT,
+ USB_DCPCTR_CSCLR);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_CSCLR_SHIFT,
+ USB_PIPEnCTR_1_5_CSCLR);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_CSCLR_SHIFT,
+ USB_PIPEnCTR_6_8_CSCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_CSCLR_SHIFT,
+ USB_PIPEnCTR_9_CSCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_sqclr
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA0.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_sqclr (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ 1,
+ USB_DCPCTR_SQCLR_SHIFT,
+ USB_DCPCTR_SQCLR);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQCLR_SHIFT,
+ USB_PIPEnCTR_1_5_SQCLR);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQCLR_SHIFT,
+ USB_PIPEnCTR_6_8_SQCLR);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQCLR_SHIFT,
+ USB_PIPEnCTR_9_SQCLR);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_sqset
+* Description : Sets the sequence bit of the pipe specified by the argument to
+* : DATA1.
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_sqset (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ RZA_IO_RegWrite_16(&USB201.DCPCTR,
+ 1,
+ USB_DCPCTR_SQSET_SHIFT,
+ USB_DCPCTR_SQSET);
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_SQSET_SHIFT,
+ USB_PIPEnCTR_1_5_SQSET);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_SQSET_SHIFT,
+ USB_PIPEnCTR_6_8_SQSET);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_SQSET_SHIFT,
+ USB_PIPEnCTR_9_SQSET);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_sqmon
+* Description : Toggle bit of specified pipe is obtained
+* Arguments : uint16_t pipe ; Pipe number
+* Return Value : sqmon
+*******************************************************************************/
+uint16_t usb1_host_get_sqmon (uint16_t pipe)
+{
+ uint16_t sqmon;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ sqmon = RZA_IO_RegRead_16(&USB201.DCPCTR,
+ USB_DCPCTR_SQMON_SHIFT,
+ USB_DCPCTR_SQMON);
+ break;
+
+ case USB_HOST_PIPE1:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE2:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE3:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE4:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE5:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_SQMON_SHIFT,
+ USB_PIPEnCTR_1_5_SQMON);
+ break;
+
+ case USB_HOST_PIPE6:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE6CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE7:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE7CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE8:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE8CTR,
+ USB_PIPEnCTR_6_8_SQMON_SHIFT,
+ USB_PIPEnCTR_6_8_SQMON);
+ break;
+
+ case USB_HOST_PIPE9:
+ sqmon = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_SQMON_SHIFT,
+ USB_PIPEnCTR_9_SQMON);
+ break;
+
+ default:
+ sqmon = 0;
+ break;
+ }
+
+ return sqmon;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_aclrm
+* Description : The buffer of specified pipe is initialized
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_host_aclrm (uint16_t pipe)
+{
+ usb1_host_set_aclrm(pipe);
+ usb1_host_clr_aclrm(pipe);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 1,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 1,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 1,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_clr_aclrm
+* Description : The auto buffer clear mode of specified pipe is enabled
+* Arguments : uint16_t pipe : Pipe
+* Return Value : none
+*******************************************************************************/
+void usb1_host_clr_aclrm (uint16_t pipe)
+{
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ break;
+
+ case USB_HOST_PIPE1:
+ RZA_IO_RegWrite_16(&USB201.PIPE1CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE2:
+ RZA_IO_RegWrite_16(&USB201.PIPE2CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE3:
+ RZA_IO_RegWrite_16(&USB201.PIPE3CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE4:
+ RZA_IO_RegWrite_16(&USB201.PIPE4CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE5:
+ RZA_IO_RegWrite_16(&USB201.PIPE5CTR,
+ 0,
+ USB_PIPEnCTR_1_5_ACLRM_SHIFT,
+ USB_PIPEnCTR_1_5_ACLRM);
+ break;
+
+ case USB_HOST_PIPE6:
+ RZA_IO_RegWrite_16(&USB201.PIPE6CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE7:
+ RZA_IO_RegWrite_16(&USB201.PIPE7CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE8:
+ RZA_IO_RegWrite_16(&USB201.PIPE8CTR,
+ 0,
+ USB_PIPEnCTR_6_8_ACLRM_SHIFT,
+ USB_PIPEnCTR_6_8_ACLRM);
+ break;
+
+ case USB_HOST_PIPE9:
+ RZA_IO_RegWrite_16(&USB201.PIPE9CTR,
+ 0,
+ USB_PIPEnCTR_9_ACLRM_SHIFT,
+ USB_PIPEnCTR_9_ACLRM);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_inbuf
+* Description : Returns INBUFM of the pipe specified by the argument.
+* Arguments : uint16_t pipe ; Pipe Number
+* Return Value : inbuf
+*******************************************************************************/
+uint16_t usb1_host_get_inbuf (uint16_t pipe)
+{
+ uint16_t inbuf;
+
+ switch (pipe)
+ {
+ case USB_HOST_PIPE0:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE1:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE1CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE2:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE2CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE3:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE3CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE4:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE4CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE5:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE5CTR,
+ USB_PIPEnCTR_1_5_INBUFM_SHIFT,
+ USB_PIPEnCTR_1_5_INBUFM);
+ break;
+
+ case USB_HOST_PIPE6:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE7:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE8:
+ inbuf = 0;
+ break;
+
+ case USB_HOST_PIPE9:
+ inbuf = RZA_IO_RegRead_16(&USB201.PIPE9CTR,
+ USB_PIPEnCTR_9_INBUFM_SHIFT,
+ USB_PIPEnCTR_9_INBUFM);
+ break;
+
+ default:
+ inbuf = 0;
+ break;
+ }
+
+ return inbuf;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_setting_interrupt
+* Description : Sets the USB module interrupt level.
+* Arguments : uint8_t level ; interrupt level
+* Return Value : none
+*******************************************************************************/
+void usb1_host_setting_interrupt (uint8_t level)
+{
+#if(1) /* ohci_wrapp */
+ IRQn_Type d0fifo_dmaintid;
+ IRQn_Type d1fifo_dmaintid;
+
+ InterruptHandlerRegister(USBI1_IRQn, usb1_host_interrupt);
+ GIC_SetPriority(USBI1_IRQn, level);
+ GIC_EnableIRQ(USBI1_IRQn);
+
+ d0fifo_dmaintid = (IRQn_Type)Userdef_USB_usb1_host_d0fifo_dmaintid();
+
+ if (d0fifo_dmaintid != 0xFFFF)
+ {
+ InterruptHandlerRegister(d0fifo_dmaintid, usb1_host_dma_interrupt_d0fifo);
+ GIC_SetPriority(d0fifo_dmaintid, level);
+ GIC_EnableIRQ(d0fifo_dmaintid);
+ }
+
+ d1fifo_dmaintid = (IRQn_Type)Userdef_USB_usb1_host_d1fifo_dmaintid();
+
+ if (d1fifo_dmaintid != 0xFFFF)
+ {
+ InterruptHandlerRegister(d1fifo_dmaintid, usb1_host_dma_interrupt_d1fifo);
+ GIC_SetPriority(d1fifo_dmaintid, level);
+ GIC_EnableIRQ(d1fifo_dmaintid);
+ }
+#else
+ uint16_t d0fifo_dmaintid;
+ uint16_t d1fifo_dmaintid;
+
+ R_INTC_RegistIntFunc(INTC_ID_USBI1, usb1_host_interrupt);
+ R_INTC_SetPriority(INTC_ID_USBI1, level);
+ R_INTC_Enable(INTC_ID_USBI1);
+
+ d0fifo_dmaintid = Userdef_USB_usb1_host_d0fifo_dmaintid();
+
+ if (d0fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d0fifo_dmaintid, usb1_host_dma_interrupt_d0fifo);
+ R_INTC_SetPriority(d0fifo_dmaintid, level);
+ R_INTC_Enable(d0fifo_dmaintid);
+ }
+
+ d1fifo_dmaintid = Userdef_USB_usb1_host_d1fifo_dmaintid();
+
+ if (d1fifo_dmaintid != 0xFFFF)
+ {
+ R_INTC_RegistIntFunc(d1fifo_dmaintid, usb1_host_dma_interrupt_d1fifo);
+ R_INTC_SetPriority(d1fifo_dmaintid, level);
+ R_INTC_Enable(d1fifo_dmaintid);
+ }
+#endif
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_reset_module
+* Description : Initializes the USB module.
+* : Enables providing clock to the USB module.
+* : Sets USB bus wait register.
+* Arguments : uint16_t clockmode ; 48MHz ; USBHCLOCK_X1_48MHZ
+* : ; 12MHz ; USBHCLOCK_EXTAL_12MHZ
+* Return Value : none
+*******************************************************************************/
+void usb1_host_reset_module (uint16_t clockmode)
+{
+ if (RZA_IO_RegRead_16(&USB200.SYSCFG0,
+ USB_SYSCFG_UPLLE_SHIFT,
+ USB_SYSCFG_UPLLE) == 1)
+ {
+ if ((USB200.SYSCFG0 & USB_HOST_BITUCKSEL) != clockmode)
+ {
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB201.SYSCFG0 = 0;
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+ Userdef_USB_usb1_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ Userdef_USB_usb1_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 0,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ USB201.SYSCFG0 = 0;
+ USB200.SYSCFG0 = 0;
+ USB200.SYSCFG0 = (USB_HOST_BITUPLLE | clockmode);
+ Userdef_USB_usb1_host_delay_xms(1);
+ RZA_IO_RegWrite_16(&USB200.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ RZA_IO_RegWrite_16(&USB201.SUSPMODE,
+ 1,
+ USB_SUSPMODE_SUSPM_SHIFT,
+ USB_SUSPMODE_SUSPM);
+ }
+
+ USB201.BUSWAIT = (uint16_t)(USB_HOST_BUSWAIT_05 & USB_HOST_BITBWAIT);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_buf_size
+* Description : Obtains pipe buffer size specified by the argument and
+* : maximum packet size of the USB device in use.
+* : When USB_HOST_PIPE0 is specified by the argument, obtains the maximum
+* : packet size of the USB device using the corresponding pipe.
+* : For the case that USB_HOST_PIPE0 is not assigned by the argument, when the
+* : corresponding pipe is in continuous transfer mode,
+* : obtains the buffer size allocated in the corresponcing pipe,
+* : when incontinuous transfer, obtains maximum packet size.
+* Arguments : uint16_t ; pipe Number
+* Return Value : Maximum packet size or buffer size
+*******************************************************************************/
+uint16_t usb1_host_get_buf_size (uint16_t pipe)
+{
+ uint16_t size;
+ uint16_t bufsize;
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[pipe], USB_PIPECFG_CNTMD_SHIFT, USB_PIPECFG_CNTMD) == 1)
+ {
+ bufsize = RZA_IO_RegRead_16(&g_usb1_host_pipebuf[pipe], USB_PIPEBUF_BUFSIZE_SHIFT, USB_PIPEBUF_BUFSIZE);
+ size = (uint16_t)((bufsize + 1) * USB_HOST_PIPExBUF);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+ }
+ return size;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_mxps
+* Description : Obtains maximum packet size of the USB device using the pipe
+* : specified by the argument.
+* Arguments : uint16_t ; Pipe Number
+* Return Value : Max Packet Size
+*******************************************************************************/
+uint16_t usb1_host_get_mxps (uint16_t pipe)
+{
+ uint16_t size;
+
+ if (pipe == USB_HOST_PIPE0)
+ {
+ size = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+ USB_DCPMAXP_MXPS_SHIFT,
+ USB_DCPMAXP_MXPS);
+ }
+ else
+ {
+ size = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_MXPS_SHIFT, USB_PIPEMAXP_MXPS);
+ }
+
+ return size;
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_controlrw.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_controlrw.c
new file mode 100644
index 000000000..913e5ad9c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_controlrw.c
@@ -0,0 +1,434 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_controlrw.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_CtrlTransStart
+* Description : Executes USB control transfer.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* : uint8_t *Buf ; Data buffer
+* Return Value : DEVDRV_SUCCESS ; SUCCESS
+* : DEVDRV_ERROR ; ERROR
+*******************************************************************************/
+int32_t usb1_host_CtrlTransStart (uint16_t devadr, uint16_t Req, uint16_t Val,
+ uint16_t Indx, uint16_t Len, uint8_t * Buf)
+{
+ if (g_usb1_host_UsbDeviceSpeed == USB_HOST_LOW_SPEED)
+ {
+ RZA_IO_RegWrite_16(&USB201.SOFCFG,
+ 1,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.SOFCFG,
+ 0,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+
+ USB201.DCPMAXP = (uint16_t)((uint16_t)(devadr << 12) + g_usb1_host_default_max_packet[devadr]);
+
+ if (g_usb1_host_pipe_status[USB_HOST_PIPE0] == USB_HOST_PIPE_IDLE)
+ {
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_WAIT;
+ g_usb1_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ g_usb1_host_CmdStage = (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE);
+
+ if (Len == 0)
+ {
+ g_usb1_host_CmdStage |= USB_HOST_MODE_NO_DATA; /* No-data Control */
+ }
+ else
+ {
+ if ((Req & 0x0080) != 0)
+ {
+ g_usb1_host_CmdStage |= USB_HOST_MODE_READ; /* Control Read */
+ }
+ else
+ {
+ g_usb1_host_CmdStage |= USB_HOST_MODE_WRITE; /* Control Write */
+ }
+ }
+
+ g_usb1_host_SavReq = Req; /* save request */
+ g_usb1_host_SavVal = Val;
+ g_usb1_host_SavIndx = Indx;
+ g_usb1_host_SavLen = Len;
+ }
+ else
+ {
+ if ((g_usb1_host_SavReq != Req) || (g_usb1_host_SavVal != Val)
+ || (g_usb1_host_SavIndx != Indx) || (g_usb1_host_SavLen != Len))
+ {
+ return DEVDRV_ERROR;
+ }
+ }
+
+ switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ /* --------------- SETUP STAGE --------------- */
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_IDLE):
+ usb1_host_SetupStage(Req, Val, Indx, Len);
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_DONE): /* goto next stage */
+ g_usb1_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_WRITE:
+ g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_STAGE_DATA;
+ break;
+
+ case USB_HOST_MODE_READ:
+ g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_STAGE_DATA;
+ break;
+
+ case USB_HOST_MODE_NO_DATA:
+ g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ break;
+
+ default:
+ break;
+ }
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ case (USB_HOST_STAGE_SETUP | USB_HOST_CMD_NORES):
+ if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+ }
+ break;
+
+ /* --------------- DATA STAGE --------------- */
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_IDLE):
+ switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_WRITE:
+ usb1_host_CtrlWriteStart((uint32_t)Len, Buf);
+ break;
+
+ case USB_HOST_MODE_READ:
+ usb1_host_CtrlReadStart((uint32_t)Len, Buf);
+ break;
+
+ default:
+ break;
+ }
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DONE): /* goto next stage */
+ g_usb1_host_PipeIgnore[USB_HOST_PIPE0] = 0; /* Ignore count clear */
+ g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_NORES):
+ if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+ usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb1_host_set_pid_buf(USB_HOST_PIPE0);
+ }
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_STALL):
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ break;
+
+ /* --------------- STATUS STAGE --------------- */
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_IDLE):
+ usb1_host_StatusStage();
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ /* do nothing */
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DONE): /* end of Control transfer */
+ usb1_host_set_pid_nak(USB_HOST_PIPE0);
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_DONE; /* exit DONE */
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_NORES):
+ if (g_usb1_host_PipeIgnore[USB_HOST_PIPE0] == 3)
+ {
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ }
+ else
+ {
+ g_usb1_host_PipeIgnore[USB_HOST_PIPE0]++; /* Ignore count */
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+ usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb1_host_set_pid_buf(USB_HOST_PIPE0);
+ }
+ break;
+
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_STALL):
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ break;
+
+ default:
+ break;
+ }
+
+ if (g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT)
+ {
+ RZA_IO_RegWrite_16(&USB201.SOFCFG,
+ 0,
+ USB_SOFCFG_TRNENSEL_SHIFT,
+ USB_SOFCFG_TRNENSEL);
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_SetupStage
+* Description : Executes USB control transfer/set up stage.
+* Arguments : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* Return Value : none
+*******************************************************************************/
+void usb1_host_SetupStage (uint16_t Req, uint16_t Val, uint16_t Indx, uint16_t Len)
+{
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ USB201.INTSTS1 = (uint16_t)~(USB_HOST_BITSACK | USB_HOST_BITSIGN); /* Status Clear */
+ USB201.USBREQ = Req;
+ USB201.USBVAL = Val;
+ USB201.USBINDX = Indx;
+ USB201.USBLENG = Len;
+ USB201.DCPCTR = USB_HOST_BITSUREQ; /* PID=NAK & Send Setup */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_StatusStage
+* Description : Executes USB control transfer/status stage.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_StatusStage (void)
+{
+ uint8_t Buf1[16];
+
+ switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD)))
+ {
+ case USB_HOST_MODE_READ:
+ usb1_host_CtrlWriteStart((uint32_t)0, (uint8_t*)&Buf1);
+ break;
+
+ case USB_HOST_MODE_WRITE:
+ usb1_host_CtrlReadStart((uint32_t)0, (uint8_t*)&Buf1);
+ break;
+
+ case USB_HOST_MODE_NO_DATA:
+ usb1_host_CtrlReadStart((uint32_t)0, (uint8_t*)&Buf1);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_CtrlWriteStart
+* Description : Executes USB control transfer/data stage(write).
+* Arguments : uint32_t Bsize ; Data Size
+* : uint8_t *Table ; Data Table Address
+* Return Value : USB_HOST_WRITESHRT ; End of data write
+* : USB_HOST_WRITEEND ; End of data write (not null)
+* : USB_HOST_WRITING ; Continue of data write
+* : USB_HOST_FIFOERROR ; FIFO access error
+*******************************************************************************/
+uint16_t usb1_host_CtrlWriteStart (uint32_t Bsize, uint8_t * Table)
+{
+ uint16_t EndFlag_K;
+ uint16_t mbw;
+
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ usb1_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */
+ g_usb1_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */
+ g_usb1_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */
+
+ USB201.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+ Userdef_USB_usb1_host_delay_10us(3);
+#endif
+ RZA_IO_RegWrite_16(&USB201.DCPCFG,
+ 1,
+ USB_DCPCFG_DIR_SHIFT,
+ USB_DCPCFG_DIR);
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb1_host_data_pointer[USB_HOST_PIPE0]);
+ usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_BITISEL, mbw);
+ USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+
+ usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+ EndFlag_K = usb1_host_write_buffer_c(USB_HOST_PIPE0);
+ /* Host Control sequence */
+ switch (EndFlag_K)
+ {
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ usb1_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb1_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_WRITEEND: /* End of data write (not null) */
+ case USB_HOST_WRITING: /* Continue of data write */
+ usb1_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb1_host_enable_bemp_int(USB_HOST_PIPE0); /* Enable Empty Interrupt */
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ break;
+
+ default:
+ break;
+ }
+ usb1_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */
+ return (EndFlag_K); /* End or Err or Continue */
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_CtrlReadStart
+* Description : Executes USB control transfer/data stage(read).
+* Arguments : uint32_t Bsize ; Data Size
+* : uint8_t *Table ; Data Table Address
+* Return Value : none
+*******************************************************************************/
+void usb1_host_CtrlReadStart (uint32_t Bsize, uint8_t * Table)
+{
+ uint16_t mbw;
+
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DOING;
+
+ usb1_host_set_pid_nak(USB_HOST_PIPE0); /* Set NAK */
+ g_usb1_host_data_count[USB_HOST_PIPE0] = Bsize; /* Transfer size set */
+ g_usb1_host_data_pointer[USB_HOST_PIPE0] = Table; /* Transfer address set */
+
+ USB201.DCPCTR = USB_HOST_BITSQSET; /* SQSET=1, PID=NAK */
+#if(1) /* ohci_wrapp */
+ Userdef_USB_usb1_host_delay_10us(3);
+#endif
+ RZA_IO_RegWrite_16(&USB201.DCPCFG,
+ 0,
+ USB_DCPCFG_DIR_SHIFT,
+ USB_DCPCFG_DIR);
+
+ mbw = usb1_host_get_mbw(g_usb1_host_data_count[USB_HOST_PIPE0], (uint32_t)g_usb1_host_data_pointer[USB_HOST_PIPE0]);
+ usb1_host_set_curpipe(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, mbw);
+ USB201.CFIFOCTR = USB_HOST_BITBCLR; /* Buffer Clear */
+
+ usb1_host_enable_nrdy_int(USB_HOST_PIPE0); /* Error (NORES or STALL) */
+ usb1_host_enable_brdy_int(USB_HOST_PIPE0); /* Ok */
+ usb1_host_clear_pid_stall(USB_HOST_PIPE0);
+ usb1_host_set_pid_buf(USB_HOST_PIPE0); /* Set BUF */
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_drv_api.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_drv_api.c
new file mode 100644
index 000000000..260328e04
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_drv_api.c
@@ -0,0 +1,889 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_drv_api.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_resetEP(USB_HOST_CFG_PIPETBL_t *tbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_api_host_init
+* Description : Initializes USB module in the USB host mode.
+* : USB connection is executed when executing this function in
+* : the states that USB device isconnected to the USB port.
+* Arguments : uint8_t int_level : USB Module interrupt level
+* : USBU16 mode : USB_HOST_HIGH_SPEED
+* : USB_HOST_FULL_SPEED
+* : uint16_t clockmode : USB Clock mode
+* Return Value : USB detach or attach
+* : USB_HOST_ATTACH
+* : USB_HOST_DETACH
+*******************************************************************************/
+uint16_t usb1_api_host_init (uint8_t int_level, uint16_t mode, uint16_t clockmode)
+{
+ uint16_t connect;
+ volatile uint8_t dummy_buf;
+
+ CPG.STBCR7 &= 0xfc; /*The clock of USB0/1 modules is permitted */
+ dummy_buf = CPG.STBCR7; /* (Dummy read) */
+
+ g_usb1_host_SupportUsbDeviceSpeed = mode;
+
+ usb1_host_setting_interrupt(int_level);
+ usb1_host_reset_module(clockmode);
+
+ g_usb1_host_bchg_flag = USB_HOST_NO;
+ g_usb1_host_detach_flag = USB_HOST_NO;
+ g_usb1_host_attach_flag = USB_HOST_NO;
+
+ g_usb1_host_driver_state = USB_HOST_DRV_DETACHED;
+ g_usb1_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+ usb1_host_InitModule();
+
+ connect = usb1_host_CheckAttach();
+
+ if (connect == USB_HOST_ATTACH)
+ {
+ g_usb1_host_attach_flag = USB_HOST_YES;
+ }
+ else
+ {
+ usb1_host_UsbDetach2();
+ }
+
+ return connect;
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb1_api_host_enumeration
+* Description : Initializes USB module in the USB host mode.
+* : USB connection is executed when executing this function in
+* : the states that USB device isconnected to the USB port.
+* Arguments : uint16_t devadr : device address
+* Return Value : DEVDRV_USBH_DETACH_ERR : device detach
+* : DEVDRV_SUCCESS : device enumeration success
+* : DEVDRV_ERROR : device enumeration error
+*******************************************************************************/
+int32_t usb1_api_host_enumeration (uint16_t devadr)
+{
+ int32_t ret;
+ uint16_t driver_sts;
+
+ g_usb1_host_setUsbAddress = devadr;
+
+ while (1)
+ {
+ driver_sts = usb1_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ ret = DEVDRV_USBH_DETACH_ERR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+ {
+ ret = DEVDRV_SUCCESS;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_STALL)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+
+ if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ while (1)
+ {
+ driver_sts = usb1_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_detach
+* Description : USB detach routine
+* Arguments : none
+* Return Value : USB_HOST_DETACH : USB detach
+* : USB_HOST_ATTACH : USB attach
+* : DEVDRV_ERROR : error
+*******************************************************************************/
+int32_t usb1_api_host_detach (void)
+{
+ int32_t ret;
+ uint16_t driver_sts;
+
+ while (1)
+ {
+ driver_sts = usb1_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ ret = USB_HOST_DETACH;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_CONFIGURED)
+ {
+ ret = USB_HOST_ATTACH;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_STALL)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ ret = DEVDRV_ERROR;
+ break;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+
+ if (driver_sts == USB_HOST_DRV_NORES)
+ {
+ while (1)
+ {
+ driver_sts = usb1_api_host_GetUsbDeviceState();
+
+ if (driver_sts == USB_HOST_DRV_DETACHED)
+ {
+ break;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_data_in
+* Description : Executes USB transfer as data-in in the argument specified pipe.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Pipe ; Pipe Number
+* : uint32_t Size ; Data Size
+* : uint8_t *data_buf ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb1_api_host_data_in (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+ int32_t ret;
+
+ if (Pipe == USB_HOST_PIPE0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 1)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (g_usb1_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+ {
+ usb1_host_start_receive_transfer(Pipe, Size, data_buf);
+ }
+ else
+ {
+ return DEVDRV_ERROR; /* Now pipe is busy */
+ }
+
+ /* waiting for completing routine */
+ do
+ {
+ if (g_usb1_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+
+ } while (1);
+
+ if (g_usb1_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb1_host_pipe_status[Pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ usb1_host_stop_transfer(Pipe);
+
+ g_usb1_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_data_out
+* Description : Executes USB transfer as data-out in the argument specified pipe.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Pipe ; Pipe Number
+* : uint32_t Size ; Data Size
+* : uint8_t *data_buf ; Data data_buf Address
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb1_api_host_data_out (uint16_t devadr, uint16_t Pipe, uint32_t Size, uint8_t * data_buf)
+{
+ int32_t ret;
+
+ if (Pipe == USB_HOST_PIPE0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[Pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL) != devadr)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (RZA_IO_RegRead_16(&g_usb1_host_pipecfg[Pipe], USB_PIPECFG_DIR_SHIFT, USB_PIPECFG_DIR) == 0)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ if (g_usb1_host_pipe_status[Pipe] == USB_HOST_PIPE_IDLE)
+ {
+ usb1_host_start_send_transfer(Pipe, Size, data_buf);
+ }
+ else
+ {
+ return DEVDRV_ERROR; /* Now pipe is busy */
+ }
+
+ /* waiting for completing routine */
+ do
+ {
+ if (g_usb1_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_IDLE) && (g_usb1_host_pipe_status[Pipe] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+
+ } while (1);
+
+ if (g_usb1_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb1_host_pipe_status[Pipe])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ usb1_host_stop_transfer(Pipe);
+
+ g_usb1_host_pipe_status[Pipe] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_control_transfer
+* Description : Executes USB control transfer.
+* Arguments : uint16_t devadr ; device address
+* : uint16_t Req ; bmRequestType & bRequest
+* : uint16_t Val ; wValue
+* : uint16_t Indx ; wIndex
+* : uint16_t Len ; wLength
+* : uint8_t *buf ; Buffer
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_USBH_DETACH_ERR ; device detach
+* : DEVDRV_USBH_CTRL_COM_ERR ; device no response
+* : DEVDRV_USBH_STALL ; STALL
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb1_api_host_control_transfer (uint16_t devadr, uint16_t Req, uint16_t Val, uint16_t Indx,
+ uint16_t Len, uint8_t * Buf)
+{
+ int32_t ret;
+
+ do
+ {
+ ret = usb1_host_CtrlTransStart(devadr, Req, Val, Indx, Len, Buf);
+
+ if (ret == DEVDRV_SUCCESS)
+ {
+ if (g_usb1_host_detach_flag == USB_HOST_YES)
+ {
+ break;
+ }
+
+ if ((g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_IDLE)
+ && (g_usb1_host_pipe_status[USB_HOST_PIPE0] != USB_HOST_PIPE_WAIT))
+ {
+ break;
+ }
+ }
+ else
+ {
+ return DEVDRV_ERROR;
+ }
+ } while (1);
+
+ if (g_usb1_host_detach_flag == USB_HOST_YES)
+ {
+ return DEVDRV_USBH_DETACH_ERR;
+ }
+
+ switch (g_usb1_host_pipe_status[USB_HOST_PIPE0])
+ {
+ case USB_HOST_PIPE_DONE:
+ ret = DEVDRV_SUCCESS;
+ break;
+
+ case USB_HOST_PIPE_STALL:
+ ret = DEVDRV_USBH_STALL;
+ break;
+
+ case USB_HOST_PIPE_NORES:
+ ret = DEVDRV_USBH_CTRL_COM_ERR;
+ break;
+
+ default:
+ ret = DEVDRV_ERROR;
+ break;
+ }
+
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_IDLE;
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_set_endpoint
+* Description : Sets end point on the information specified in the argument.
+* Arguments : uint16_t devadr ; device address
+* : uint8_t *configdescriptor ; device configration descriptor
+* : USB_HOST_CFG_PIPETBL_t *user_table ; pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb1_api_host_set_endpoint (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * configdescriptor)
+{
+ uint16_t ret;
+ uint32_t end_point;
+ uint32_t offset;
+ uint32_t totalLength;
+ USB_HOST_CFG_PIPETBL_t * pipe_table;
+
+ /* End Point Search */
+ end_point = 0;
+ offset = configdescriptor[0];
+ totalLength = (uint16_t)(configdescriptor[2] + ((uint16_t)configdescriptor[3] << 8));
+
+ do
+ {
+ if (configdescriptor[offset + 1] == USB_HOST_ENDPOINT_DESC)
+ {
+ pipe_table = &user_table[end_point];
+
+ if (pipe_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+
+ ret = usb1_api_host_SetEndpointTable(devadr, pipe_table, (uint8_t *)&configdescriptor[offset]);
+
+ if ((ret != USB_HOST_PIPE_IN) && (ret != USB_HOST_PIPE_OUT))
+ {
+ return DEVDRV_ERROR;
+ }
+
+ ++end_point;
+ }
+
+ /* Next End Point Search */
+ offset += configdescriptor[offset];
+
+ } while (offset < totalLength);
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_clear_endpoint
+* Description : Clears the pipe definition table specified in the argument.
+* Arguments : uint16_t pipe_sel : Pipe Number
+* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb1_api_host_clear_endpoint (USB_HOST_CFG_PIPETBL_t * user_table)
+{
+ uint16_t pipe;
+
+ for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+ {
+ if (user_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+ user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+ user_table->pipe_max_pktsize = 0;
+ user_table->pipe_cycle = 0;
+
+ user_table++;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_api_host_clear_endpoint_pipe
+* Description : Clears the pipe definition table specified in the argument.
+* Arguments : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb1_api_host_clear_endpoint_pipe (uint16_t pipe_sel, USB_HOST_CFG_PIPETBL_t * user_table)
+{
+ uint16_t pipe;
+
+ for (pipe = USB_HOST_PIPE0; pipe <= USB_HOST_MAX_PIPE_NO; ++pipe)
+ {
+ if (user_table->pipe_number == 0xffff)
+ {
+ break;
+ }
+
+ if (user_table->pipe_number == pipe_sel)
+ {
+ user_table->pipe_cfg &= (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD);
+ user_table->pipe_max_pktsize = 0;
+ user_table->pipe_cycle = 0;
+ break;
+ }
+
+ user_table++;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+#endif
+
+/*******************************************************************************
+* Function Name: usb1_api_host_SetEndpointTable
+* Description : Sets the end point on the information specified by the argument.
+* Arguments : uint16_t devadr : device address
+* : USB_HOST_CFG_PIPETBL_t *user_table : pipe table
+* : uint8_t *Table : Endpoint descriptor
+* Return Value : USB_HOST_DIR_H_IN ; IN endpoint
+* : USB_HOST_DIR_H_OUT ; OUT endpoint
+* : USB_END_POINT_ERROR ; error
+*******************************************************************************/
+uint16_t usb1_api_host_SetEndpointTable (uint16_t devadr, USB_HOST_CFG_PIPETBL_t * user_table, uint8_t * Table)
+{
+ uint16_t PipeCfg;
+ uint16_t PipeMaxp;
+ uint16_t pipe_number;
+ uint16_t ret;
+ uint16_t ret_flag = 0; // avoid warning.
+
+ pipe_number = user_table->pipe_number;
+
+ if (Table[1] != USB_HOST_ENDPOINT_DESC)
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ switch (Table[3] & USB_HOST_EP_TYPE)
+ {
+ case USB_HOST_EP_CNTRL:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+
+ case USB_HOST_EP_ISO:
+ if ((pipe_number != USB_HOST_PIPE1) && (pipe_number != USB_HOST_PIPE2))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_ISO;
+ break;
+
+ case USB_HOST_EP_BULK:
+ if ((pipe_number < USB_HOST_PIPE1) || (pipe_number > USB_HOST_PIPE5))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_BULK;
+ break;
+
+ case USB_HOST_EP_INT:
+ if ((pipe_number < USB_HOST_PIPE6) || (pipe_number > USB_HOST_PIPE9))
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ PipeCfg = USB_HOST_INTERRUPT;
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+
+ /* Set pipe configuration table */
+ if ((Table[2] & USB_HOST_EP_DIR_MASK) == USB_HOST_EP_IN) /* IN(receive) */
+ {
+ if (PipeCfg == USB_HOST_ISO)
+ {
+ /* Transfer Type is ISO*/
+ PipeCfg |= USB_HOST_DIR_H_IN;
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ case USB_HOST_D0USE:
+ case USB_HOST_D1USE:
+ case USB_HOST_D0DMA:
+ case USB_HOST_D1DMA:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+ }
+ else
+ {
+ /* Transfer Type is BULK or INT */
+ PipeCfg |= (USB_HOST_SHTNAKON | USB_HOST_DIR_H_IN); /* Compulsory SHTNAK */
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ case USB_HOST_D0USE:
+ case USB_HOST_D1USE:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+ break;
+
+ case USB_HOST_D0DMA:
+ case USB_HOST_D1DMA:
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+#ifdef __USB_DMA_BFRE_ENABLE__
+ /* this routine cannnot be perfomred if read operation is executed in buffer size */
+ PipeCfg |= USB_HOST_BFREON;
+#endif
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+ }
+ ret = USB_HOST_PIPE_IN;
+ }
+ else /* OUT(send) */
+ {
+ if (PipeCfg == USB_HOST_ISO)
+ {
+ /* Transfer Type is ISO*/
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & USB_HOST_DBLBFIELD);
+ }
+ else
+ {
+ /* Transfer Type is BULK or INT */
+ PipeCfg |= (uint16_t)(user_table->pipe_cfg & (USB_HOST_DBLBFIELD | USB_HOST_CNTMDFIELD));
+ }
+ PipeCfg |= USB_HOST_DIR_H_OUT;
+ ret = USB_HOST_PIPE_OUT;
+ }
+
+ switch (user_table->fifo_port)
+ {
+ case USB_HOST_CUSE:
+ g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_CFIFO_USE;
+ break;
+
+ case USB_HOST_D0USE:
+ g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_USE;
+ break;
+
+ case USB_HOST_D1USE:
+ g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_USE;
+ break;
+
+ case USB_HOST_D0DMA:
+ g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D0FIFO_DMA;
+ break;
+
+ case USB_HOST_D1DMA:
+ g_usb1_host_PipeTbl[pipe_number] = (uint16_t)USB_HOST_D1FIFO_DMA;
+ break;
+
+ default:
+ ret_flag = USB_END_POINT_ERROR;
+ break;
+ }
+
+ if (ret_flag == USB_END_POINT_ERROR)
+ {
+ return ret_flag;
+ }
+
+ /* Endpoint number set */
+ PipeCfg |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+ g_usb1_host_PipeTbl[pipe_number] |= (uint16_t)(Table[2] & USB_HOST_EP_NUM_MASK);
+
+ /* Max packet size set */
+ PipeMaxp = (uint16_t)((uint16_t)Table[4] | (uint16_t)((uint16_t)Table[5] << 8));
+
+ if (PipeMaxp == 0u)
+ {
+ return USB_END_POINT_ERROR;
+ }
+
+ /* Set device address */
+ PipeMaxp |= (uint16_t)(devadr << 12);
+
+ user_table->pipe_cfg = PipeCfg;
+ user_table->pipe_max_pktsize = PipeMaxp;
+
+ usb1_host_resetEP(user_table);
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_resetEP
+* Description : Sets the end point on the information specified by the argument.
+* Arguments : USB_HOST_CFG_PIPETBL_t *tbl : pipe table
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_resetEP (USB_HOST_CFG_PIPETBL_t * tbl)
+{
+
+ uint16_t pipe;
+
+ /* Host pipe */
+ /* The pipe number of pipe definition table is obtained */
+ pipe = (uint16_t)(tbl->pipe_number & USB_HOST_BITCURPIPE); /* Pipe Number */
+
+ /* FIFO port access pipe is set to initial value */
+ /* The connection with FIFO should be cut before setting the pipe */
+ if (RZA_IO_RegRead_16(&USB201.CFIFOSEL,
+ USB_CFIFOSEL_CURPIPE_SHIFT,
+ USB_CFIFOSEL_CURPIPE) == pipe)
+ {
+ usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_CUSE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ if (RZA_IO_RegRead_16(&USB201.D0FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D0USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ if (RZA_IO_RegRead_16(&USB201.D1FIFOSEL,
+ USB_DnFIFOSEL_CURPIPE_SHIFT,
+ USB_DnFIFOSEL_CURPIPE) == pipe)
+ {
+ usb1_host_change_fifo_port(USB_HOST_PIPE0, USB_HOST_D1USE, USB_HOST_NO, USB_HOST_BITMBW_16);
+ }
+
+ /* Interrupt of pipe set is disabled */
+ usb1_host_disable_brdy_int(pipe);
+ usb1_host_disable_nrdy_int(pipe);
+ usb1_host_disable_bemp_int(pipe);
+
+ /* Pipe to set is set to NAK */
+ usb1_host_set_pid_nak(pipe);
+
+ /* Pipe is set */
+ USB201.PIPESEL = pipe;
+
+ USB201.PIPECFG = tbl->pipe_cfg;
+ USB201.PIPEBUF = tbl->pipe_buf;
+ USB201.PIPEMAXP = tbl->pipe_max_pktsize;
+ USB201.PIPEPERI = tbl->pipe_cycle;
+
+ g_usb1_host_pipecfg[pipe] = tbl->pipe_cfg;
+ g_usb1_host_pipebuf[pipe] = tbl->pipe_buf;
+ g_usb1_host_pipemaxp[pipe] = tbl->pipe_max_pktsize;
+ g_usb1_host_pipeperi[pipe] = tbl->pipe_cycle;
+
+ /* Sequence bit clear */
+ usb1_host_set_sqclr(pipe);
+
+ usb1_host_aclrm(pipe);
+ usb1_host_set_csclr(pipe);
+
+ /* Pipe window selection is set to unused */
+ USB201.PIPESEL = USB_HOST_PIPE0;
+
+}
+
+#if(1) /* ohci_wrapp */
+#else
+/*******************************************************************************
+* Function Name: usb1_api_host_data_count
+* Description : Get g_usb0_host_data_count[pipe]
+* Arguments : uint16_t pipe ; Pipe Number
+* : uint32_t *data_count ; return g_usb0_data_count[pipe]
+* Return Value : DEVDRV_SUCCESS ; success
+* : DEVDRV_ERROR ; error
+*******************************************************************************/
+int32_t usb1_api_host_data_count (uint16_t pipe, uint32_t * data_count)
+{
+ if (pipe > USB_HOST_MAX_PIPE_NO)
+ {
+ return DEVDRV_ERROR;
+ }
+
+ *data_count = g_usb1_host_PipeDataSize[pipe];
+
+ return DEVDRV_SUCCESS;
+}
+#endif
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_global.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_global.c
new file mode 100644
index 000000000..245da23af
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_global.c
@@ -0,0 +1,137 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_global.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+const uint16_t g_usb1_host_bit_set[16] =
+{
+ 0x0001, 0x0002, 0x0004, 0x0008,
+ 0x0010, 0x0020, 0x0040, 0x0080,
+ 0x0100, 0x0200, 0x0400, 0x0800,
+ 0x1000, 0x2000, 0x4000, 0x8000
+};
+
+uint32_t g_usb1_host_data_count[USB_HOST_MAX_PIPE_NO + 1];
+uint8_t * g_usb1_host_data_pointer[USB_HOST_MAX_PIPE_NO + 1];
+
+uint16_t g_usb1_host_PipeIgnore[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb1_host_PipeTbl[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb1_host_pipe_status[USB_HOST_MAX_PIPE_NO + 1];
+uint32_t g_usb1_host_PipeDataSize[USB_HOST_MAX_PIPE_NO + 1];
+
+USB_HOST_DMA_t g_usb1_host_DmaInfo[2];
+
+uint16_t g_usb1_host_DmaPipe[2];
+uint16_t g_usb1_host_DmaBval[2];
+uint16_t g_usb1_host_DmaStatus[2];
+
+uint16_t g_usb1_host_driver_state;
+uint16_t g_usb1_host_ConfigNum;
+uint16_t g_usb1_host_CmdStage;
+uint16_t g_usb1_host_bchg_flag;
+uint16_t g_usb1_host_detach_flag;
+uint16_t g_usb1_host_attach_flag;
+
+uint16_t g_usb1_host_UsbAddress;
+uint16_t g_usb1_host_setUsbAddress;
+uint16_t g_usb1_host_default_max_packet[USB_HOST_MAX_DEVICE + 1];
+uint16_t g_usb1_host_UsbDeviceSpeed;
+uint16_t g_usb1_host_SupportUsbDeviceSpeed;
+
+uint16_t g_usb1_host_SavReq;
+uint16_t g_usb1_host_SavVal;
+uint16_t g_usb1_host_SavIndx;
+uint16_t g_usb1_host_SavLen;
+
+uint16_t g_usb1_host_pipecfg[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb1_host_pipebuf[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb1_host_pipemaxp[USB_HOST_MAX_PIPE_NO + 1];
+uint16_t g_usb1_host_pipeperi[USB_HOST_MAX_PIPE_NO + 1];
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_init_pipe_status
+* Description : Initialize pipe status.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_init_pipe_status (void)
+{
+ uint16_t loop;
+
+ g_usb1_host_ConfigNum = 0;
+
+ for (loop = 0; loop < (USB_HOST_MAX_PIPE_NO + 1); ++loop)
+ {
+ g_usb1_host_pipe_status[loop] = USB_HOST_PIPE_IDLE;
+ g_usb1_host_PipeDataSize[loop] = 0;
+
+ /* pipe configuration in usb1_host_resetEP() */
+ g_usb1_host_pipecfg[loop] = 0;
+ g_usb1_host_pipebuf[loop] = 0;
+ g_usb1_host_pipemaxp[loop] = 0;
+ g_usb1_host_pipeperi[loop] = 0;
+ }
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbint.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbint.c
new file mode 100644
index 000000000..d05b19d0e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbint.c
@@ -0,0 +1,497 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_usbint.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#if(1) /* ohci_wrapp */
+#include "ohci_wrapp_RZ_A1_local.h"
+#endif
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_interrupt1(void);
+static void usb1_host_BRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb1_host_NRDYInterrupt(uint16_t Status, uint16_t Int_enbl);
+static void usb1_host_BEMPInterrupt(uint16_t Status, uint16_t Int_enbl);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_interrupt
+* Description : Executes USB interrupt.
+* : Register this function in the USB interrupt handler.
+* : Set CFIF0 in the pipe set before the interrupt after executing
+* : this function.
+* Arguments : uint32_t int_sense ; Interrupts detection mode
+* : ; INTC_LEVEL_SENSITIVE : Level sense
+* : ; INTC_EDGE_TRIGGER : Edge trigger
+* Return Value : none
+*******************************************************************************/
+void usb1_host_interrupt (uint32_t int_sense)
+{
+ uint16_t savepipe1;
+ uint16_t savepipe2;
+ uint16_t buffer;
+
+ savepipe1 = USB201.CFIFOSEL;
+ savepipe2 = USB201.PIPESEL;
+ usb1_host_interrupt1();
+
+ /* Control transmission changes ISEL within interruption processing. */
+ /* For this reason, write return of ISEL cannot be performed. */
+ buffer = USB201.CFIFOSEL;
+ buffer &= (uint16_t)~(USB_HOST_BITCURPIPE);
+ buffer |= (uint16_t)(savepipe1 & USB_HOST_BITCURPIPE);
+ USB201.CFIFOSEL = buffer;
+ USB201.PIPESEL = savepipe2;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_interrupt1
+* Description : Execue the USB interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_interrupt1 (void)
+{
+ uint16_t intsts0;
+ uint16_t intsts1;
+ uint16_t intenb0;
+ uint16_t intenb1;
+ uint16_t brdysts;
+ uint16_t nrdysts;
+ uint16_t bempsts;
+ uint16_t brdyenb;
+ uint16_t nrdyenb;
+ uint16_t bempenb;
+ volatile uint16_t dumy_sts;
+
+ intsts0 = USB201.INTSTS0;
+ intsts1 = USB201.INTSTS1;
+ intenb0 = USB201.INTENB0;
+ intenb1 = USB201.INTENB1;
+
+ if ((intsts1 & USB_HOST_BITBCHG) && (intenb1 & USB_HOST_BITBCHGE))
+ {
+ USB201.INTSTS1 = (uint16_t)~USB_HOST_BITBCHG;
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+ g_usb1_host_bchg_flag = USB_HOST_YES;
+ }
+ else if ((intsts1 & USB_HOST_BITSACK) && (intenb1 & USB_HOST_BITSACKE))
+ {
+ USB201.INTSTS1 = (uint16_t)~USB_HOST_BITSACK;
+#if(1) /* ohci_wrapp */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+#else
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+#endif
+ }
+ else if ((intsts1 & USB_HOST_BITSIGN) && (intenb1 & USB_HOST_BITSIGNE))
+ {
+ USB201.INTSTS1 = (uint16_t)~USB_HOST_BITSIGN;
+#if(1) /* ohci_wrapp */
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES; /* exit NORES */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#else
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_NORES;
+#endif
+ }
+ else if (((intsts1 & USB_HOST_BITDTCH) == USB_HOST_BITDTCH)
+ && ((intenb1 & USB_HOST_BITDTCHE) == USB_HOST_BITDTCHE))
+ {
+ USB201.INTSTS1 = (uint16_t)~USB_HOST_BITDTCH;
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 0,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+ g_usb1_host_detach_flag = USB_HOST_YES;
+
+ Userdef_USB_usb1_host_detach();
+
+ usb1_host_UsbDetach2();
+ }
+ else if (((intsts1 & USB_HOST_BITATTCH) == USB_HOST_BITATTCH)
+ && ((intenb1 & USB_HOST_BITATTCHE) == USB_HOST_BITATTCHE))
+ {
+ USB201.INTSTS1 = (uint16_t)~USB_HOST_BITATTCH;
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 0,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+ g_usb1_host_attach_flag = USB_HOST_YES;
+
+ Userdef_USB_usb1_host_attach();
+
+ usb1_host_UsbAttach();
+ }
+ else if ((intsts0 & intenb0 & (USB_HOST_BITBEMP | USB_HOST_BITNRDY | USB_HOST_BITBRDY)))
+ {
+ brdysts = USB201.BRDYSTS;
+ nrdysts = USB201.NRDYSTS;
+ bempsts = USB201.BEMPSTS;
+ brdyenb = USB201.BRDYENB;
+ nrdyenb = USB201.NRDYENB;
+ bempenb = USB201.BEMPENB;
+
+ if ((intsts0 & USB_HOST_BITBRDY) && (intenb0 & USB_HOST_BITBRDYE) && (brdysts & brdyenb))
+ {
+ usb1_host_BRDYInterrupt(brdysts, brdyenb);
+ }
+ else if ((intsts0 & USB_HOST_BITBEMP) && (intenb0 & USB_HOST_BITBEMPE) && (bempsts & bempenb))
+ {
+ usb1_host_BEMPInterrupt(bempsts, bempenb);
+ }
+ else if ((intsts0 & USB_HOST_BITNRDY) && (intenb0 & USB_HOST_BITNRDYE) && (nrdysts & nrdyenb))
+ {
+ usb1_host_NRDYInterrupt(nrdysts, nrdyenb);
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* Three dummy read for clearing interrupt requests */
+ dumy_sts = USB201.INTSTS0;
+ dumy_sts = USB201.INTSTS1;
+
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_BRDYInterrupt
+* Description : Executes USB BRDY interrupt.
+* Arguments : uint16_t Status ; BRDYSTS Register Value
+* : uint16_t Int_enbl ; BRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_BRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t buffer;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB201.BRDYSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
+
+#if(1) /* ohci_wrapp */
+ switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+ usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ USB201.CFIFOCTR = USB_HOST_BITBCLR;
+ usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ break;
+ }
+#else
+ switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ case (USB_HOST_MODE_NO_DATA | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+ usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case (USB_HOST_MODE_READ | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb1_host_read_buffer_c(USB_HOST_PIPE0);
+
+ switch (buffer)
+ {
+ case USB_HOST_READING: /* Continue of data read */
+ break;
+
+ case USB_HOST_READEND: /* End of data read */
+ case USB_HOST_READSHRT: /* End of data read */
+ usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case USB_HOST_READOVER: /* buffer over */
+ USB201.CFIFOCTR = USB_HOST_BITBCLR;
+ usb1_host_disable_brdy_int(USB_HOST_PIPE0);
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ break;
+ }
+#endif
+ }
+ else
+ {
+ usb1_host_brdy_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB201.BRDYSTS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_NRDYInterrupt
+* Description : Executes USB NRDY interrupt.
+* Arguments : uint16_t Status ; NRDYSTS Register Value
+* : uint16_t Int_enbl ; NRDYENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_NRDYInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t pid;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB201.NRDYSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
+ pid = usb1_host_get_pid(USB_HOST_PIPE0);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+
+ }
+ else if (pid == USB_HOST_PID_NAK)
+ {
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_NORES;
+#if(1) /* ohci_wrapp */
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_NORES;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else
+ {
+ usb1_host_nrdy_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB201.NRDYSTS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_BEMPInterrupt
+* Description : Executes USB BEMP interrupt.
+* Arguments : uint16_t Status ; BEMPSTS Register Value
+* : uint16_t Int_enbl ; BEMPENB Register Value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_BEMPInterrupt (uint16_t Status, uint16_t Int_enbl)
+{
+ uint16_t buffer;
+ uint16_t pid;
+ volatile uint16_t dumy_sts;
+
+ if ((Status & g_usb1_host_bit_set[USB_HOST_PIPE0]) && (Int_enbl & g_usb1_host_bit_set[USB_HOST_PIPE0]))
+ {
+ USB201.BEMPSTS = (uint16_t)~g_usb1_host_bit_set[USB_HOST_PIPE0];
+ pid = usb1_host_get_pid(USB_HOST_PIPE0);
+
+ if ((pid == USB_HOST_PID_STALL) || (pid == USB_HOST_PID_STALL2))
+ {
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_STALL;
+#if(1) /* ohci_wrapp */
+ g_usb1_host_pipe_status[USB_HOST_PIPE0] = USB_HOST_PIPE_STALL; /* exit STALL */
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_STALL);
+#endif
+ }
+ else
+ {
+#if(1) /* ohci_wrapp */
+ switch ((g_usb1_host_CmdStage & (USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case (USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb1_host_write_buffer(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ case USB_HOST_WRITEEND: /* End of data write (zero-length) */
+ break;
+
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ ohciwrapp_loc_TransEnd(USB_HOST_PIPE0, TD_CC_NOERROR);
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ default:
+ /* do nothing */
+ break;
+ }
+#else
+ switch ((g_usb1_host_CmdStage & (USB_HOST_MODE_FIELD | USB_HOST_STAGE_FIELD | USB_HOST_CMD_FIELD)))
+ {
+ case (USB_HOST_MODE_READ | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_DONE;
+ break;
+
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_DATA | USB_HOST_CMD_DOING):
+ buffer = usb1_host_write_buffer(USB_HOST_PIPE0);
+ switch (buffer)
+ {
+ case USB_HOST_WRITING: /* Continue of data write */
+ case USB_HOST_WRITEEND: /* End of data write (zero-length) */
+ break;
+
+ case USB_HOST_WRITESHRT: /* End of data write */
+ g_usb1_host_CmdStage &= (~USB_HOST_STAGE_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_STAGE_STATUS;
+ break;
+
+ case USB_HOST_FIFOERROR: /* FIFO access error */
+ default:
+ break;
+ }
+ break;
+
+ case (USB_HOST_MODE_WRITE | USB_HOST_STAGE_STATUS | USB_HOST_CMD_DOING):
+ g_usb1_host_CmdStage &= (~USB_HOST_CMD_FIELD);
+ g_usb1_host_CmdStage |= USB_HOST_CMD_IDLE;
+ break;
+
+ default:
+ /* do nothing */
+ break;
+ }
+#endif
+ }
+ }
+ else
+ {
+ usb1_host_bemp_int(Status, Int_enbl);
+ }
+
+ /* Three dummy reads for clearing interrupt requests */
+ dumy_sts = USB201.BEMPSTS;
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbsig.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbsig.c
new file mode 100644
index 000000000..ea8abf876
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/host/usb1_host_usbsig.c
@@ -0,0 +1,637 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_usbsig.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "usb1_host.h"
+#include "dev_drv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_EnableINT_Module(void);
+static void usb1_host_Enable_AttachINT(void);
+static void usb1_host_Disable_AttachINT(void);
+static void usb1_host_Disable_BchgINT(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: usb1_host_InitModule
+* Description : Initializes the USB module in USB host module.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_InitModule (void)
+{
+ uint16_t buf1;
+ uint16_t buf2;
+ uint16_t buf3;
+
+ usb1_host_init_pipe_status();
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_DCFM_SHIFT,
+ USB_SYSCFG_DCFM); /* HOST mode */
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_DRPD_SHIFT,
+ USB_SYSCFG_DRPD); /* PORT0 D+, D- setting */
+
+ do
+ {
+ buf1 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb1_host_delay_xms(50);
+ buf2 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb1_host_delay_xms(50);
+ buf3 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+
+ } while ((buf1 != buf2) || (buf1 != buf3));
+
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_USBE_SHIFT,
+ USB_SYSCFG_USBE);
+
+ USB201.CFIFOSEL = (uint16_t)(USB_HOST_BITRCNT | USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+ USB201.D0FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+ USB201.D1FIFOSEL = (uint16_t)( USB_HOST_BITMBW_8 | USB_HOST_BITBYTE_LITTLE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_CheckAttach
+* Description : Returns the USB device connection state.
+* Arguments : none
+* Return Value : uint16_t ; USB_HOST_ATTACH : Attached
+* : ; USB_HOST_DETACH : not Attached
+*******************************************************************************/
+uint16_t usb1_host_CheckAttach (void)
+{
+ uint16_t buf1;
+ uint16_t buf2;
+ uint16_t buf3;
+ uint16_t rhst;
+
+ do
+ {
+ buf1 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb1_host_delay_xms(50);
+ buf2 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ Userdef_USB_usb1_host_delay_xms(50);
+ buf3 = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+
+ } while ((buf1 != buf2) || (buf1 != buf3));
+
+ rhst = RZA_IO_RegRead_16(&USB201.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (rhst == USB_HOST_UNDECID)
+ {
+ if (buf1 == USB_HOST_FS_JSTS)
+ {
+ if (g_usb1_host_SupportUsbDeviceSpeed == USB_HOST_HIGH_SPEED)
+ {
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 1,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ }
+ else
+ {
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ }
+ return USB_HOST_ATTACH;
+ }
+ else if (buf1 == USB_HOST_LS_JSTS)
+ {
+ /* Low Speed Device */
+ RZA_IO_RegWrite_16(&USB201.SYSCFG0,
+ 0,
+ USB_SYSCFG_HSE_SHIFT,
+ USB_SYSCFG_HSE);
+ return USB_HOST_ATTACH;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+ }
+ else if ((rhst == USB_HOST_HSMODE) || (rhst == USB_HOST_FSMODE))
+ {
+ return USB_HOST_ATTACH;
+ }
+ else if (rhst == USB_HOST_LSMODE)
+ {
+ return USB_HOST_ATTACH;
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ return USB_HOST_DETACH;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbAttach
+* Description : Connects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_UsbAttach (void)
+{
+ usb1_host_EnableINT_Module();
+ usb1_host_Disable_BchgINT();
+ usb1_host_Disable_AttachINT();
+ usb1_host_Enable_DetachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbDetach
+* Description : Disconnects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_UsbDetach (void)
+{
+ uint16_t pipe;
+ uint16_t devadr;
+
+ g_usb1_host_driver_state = USB_HOST_DRV_DETACHED;
+
+ /* Terminate all the pipes in which communications on port */
+ /* are currently carried out */
+ for (pipe = 0; pipe < (USB_HOST_MAX_PIPE_NO + 1); ++pipe)
+ {
+ if (g_usb1_host_pipe_status[pipe] != USB_HOST_PIPE_IDLE)
+ {
+ if (pipe == USB_HOST_PIPE0)
+ {
+ devadr = RZA_IO_RegRead_16(&USB201.DCPMAXP,
+ USB_DCPMAXP_DEVSEL_SHIFT,
+ USB_DCPMAXP_DEVSEL);
+ }
+ else
+ {
+ devadr = RZA_IO_RegRead_16(&g_usb1_host_pipemaxp[pipe], USB_PIPEMAXP_DEVSEL_SHIFT, USB_PIPEMAXP_DEVSEL);
+ }
+
+ if (devadr == g_usb1_host_UsbAddress)
+ {
+ usb1_host_stop_transfer(pipe);
+ }
+
+ g_usb1_host_pipe_status[pipe] = USB_HOST_PIPE_IDLE;
+ }
+ }
+
+ g_usb1_host_ConfigNum = 0;
+ g_usb1_host_UsbAddress = 0;
+ g_usb1_host_default_max_packet[USB_HOST_DEVICE_0] = 64;
+
+ usb1_host_UsbDetach2();
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbDetach2
+* Description : Disconnects the USB device.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_UsbDetach2 (void)
+{
+ usb1_host_Disable_DetachINT();
+ usb1_host_Disable_BchgINT();
+ usb1_host_Enable_AttachINT();
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbBusReset
+* Description : Issues the USB bus reset signal.
+* Arguments : none
+* Return Value : uint16_t ; RHST
+*******************************************************************************/
+uint16_t usb1_host_UsbBusReset (void)
+{
+ uint16_t buffer;
+ uint16_t loop;
+
+ RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+ 1,
+ USB_DVSTCTR0_USBRST_SHIFT,
+ USB_DVSTCTR0_USBRST);
+ RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+ 0,
+ USB_DVSTCTR0_UACT_SHIFT,
+ USB_DVSTCTR0_UACT);
+
+ Userdef_USB_usb1_host_delay_xms(50);
+
+ buffer = USB201.DVSTCTR0;
+ buffer &= (uint16_t)(~(USB_HOST_BITRST));
+ buffer |= USB_HOST_BITUACT;
+ USB201.DVSTCTR0 = buffer;
+
+ Userdef_USB_usb1_host_delay_xms(20);
+
+ for (loop = 0, buffer = USB_HOST_HSPROC; loop < 3; ++loop)
+ {
+ buffer = RZA_IO_RegRead_16(&USB201.DVSTCTR0,
+ USB_DVSTCTR0_RHST_SHIFT,
+ USB_DVSTCTR0_RHST);
+ if (buffer == USB_HOST_HSPROC)
+ {
+ Userdef_USB_usb1_host_delay_xms(10);
+ }
+ else
+ {
+ break;
+ }
+ }
+
+ return buffer;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbResume
+* Description : Issues the USB resume signal.
+* Arguments : none
+* Return Value : int32_t ; DEVDRV_SUCCESS
+* : ; DEVDRV_ERROR
+*******************************************************************************/
+int32_t usb1_host_UsbResume (void)
+{
+ uint16_t buf;
+
+ if ((g_usb1_host_driver_state & USB_HOST_DRV_SUSPEND) == 0)
+ {
+ /* not SUSPEND */
+ return DEVDRV_ERROR;
+ }
+
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+ RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+ 1,
+ USB_DVSTCTR0_RESUME_SHIFT,
+ USB_DVSTCTR0_RESUME);
+ Userdef_USB_usb1_host_delay_xms(20);
+
+ buf = USB201.DVSTCTR0;
+ buf &= (uint16_t)(~(USB_HOST_BITRESUME));
+ buf |= USB_HOST_BITUACT;
+ USB201.DVSTCTR0 = buf;
+
+ g_usb1_host_driver_state &= (uint16_t)~USB_HOST_DRV_SUSPEND;
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_UsbSuspend
+* Description : Issues the USB suspend signal.
+* Arguments : none
+* Return Value : int32_t ; DEVDRV_SUCCESS :not SUSPEND
+* : ; DEVDRV_ERROR :SUSPEND
+*******************************************************************************/
+int32_t usb1_host_UsbSuspend (void)
+{
+ uint16_t buf;
+
+ if ((g_usb1_host_driver_state & USB_HOST_DRV_SUSPEND) != 0)
+ {
+ /* SUSPEND */
+ return DEVDRV_ERROR;
+ }
+
+ RZA_IO_RegWrite_16(&USB201.DVSTCTR0,
+ 0,
+ USB_DVSTCTR0_UACT_SHIFT,
+ USB_DVSTCTR0_UACT);
+
+ Userdef_USB_usb1_host_delay_xms(5);
+
+ buf = RZA_IO_RegRead_16(&USB201.SYSSTS0,
+ USB_SYSSTS0_LNST_SHIFT,
+ USB_SYSSTS0_LNST);
+ if ((buf != USB_HOST_FS_JSTS) && (buf != USB_HOST_LS_JSTS))
+ {
+ usb1_host_UsbDetach();
+ }
+ else
+ {
+ g_usb1_host_driver_state |= USB_HOST_DRV_SUSPEND;
+ }
+
+ return DEVDRV_SUCCESS;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Enable_DetachINT
+* Description : Enables the USB disconnection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Enable_DetachINT (void)
+{
+ USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 1,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Disable_DetachINT
+* Description : Disables the USB disconnection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Disable_DetachINT (void)
+{
+ USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITDTCH));
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 0,
+ USB_INTENB1_DTCHE_SHIFT,
+ USB_INTENB1_DTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Enable_AttachINT
+* Description : Enables the USB connection detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Enable_AttachINT (void)
+{
+ USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 1,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Disable_AttachINT
+* Description : Disables the USB connection detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Disable_AttachINT (void)
+{
+ USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITATTCH));
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 0,
+ USB_INTENB1_ATTCHE_SHIFT,
+ USB_INTENB1_ATTCHE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_Disable_BchgINT
+* Description : Disables the USB bus change detection interrupt.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_Disable_BchgINT (void)
+{
+ USB201.INTSTS1 = (uint16_t)(~(USB_HOST_BITBCHG));
+ RZA_IO_RegWrite_16(&USB201.INTENB1,
+ 0,
+ USB_INTENB1_BCHGE_SHIFT,
+ USB_INTENB1_BCHGE);
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_set_devadd
+* Description : DEVADDn register is set by specified value
+* Arguments : uint16_t addr : Device address
+* : uint16_t *devadd : Set value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_set_devadd (uint16_t addr, uint16_t * devadd)
+{
+ uint16_t * ptr;
+ uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning.
+
+ switch (addr)
+ {
+ case USB_HOST_DEVICE_0:
+ ptr = (uint16_t *)&USB201.DEVADD0;
+ break;
+
+ case USB_HOST_DEVICE_1:
+ ptr = (uint16_t *)&USB201.DEVADD1;
+ break;
+
+ case USB_HOST_DEVICE_2:
+ ptr = (uint16_t *)&USB201.DEVADD2;
+ break;
+
+ case USB_HOST_DEVICE_3:
+ ptr = (uint16_t *)&USB201.DEVADD3;
+ break;
+
+ case USB_HOST_DEVICE_4:
+ ptr = (uint16_t *)&USB201.DEVADD4;
+ break;
+
+ case USB_HOST_DEVICE_5:
+ ptr = (uint16_t *)&USB201.DEVADD5;
+ break;
+
+ case USB_HOST_DEVICE_6:
+ ptr = (uint16_t *)&USB201.DEVADD6;
+ break;
+
+ case USB_HOST_DEVICE_7:
+ ptr = (uint16_t *)&USB201.DEVADD7;
+ break;
+
+ case USB_HOST_DEVICE_8:
+ ptr = (uint16_t *)&USB201.DEVADD8;
+ break;
+
+ case USB_HOST_DEVICE_9:
+ ptr = (uint16_t *)&USB201.DEVADD9;
+ break;
+
+ case USB_HOST_DEVICE_10:
+ ptr = (uint16_t *)&USB201.DEVADDA;
+ break;
+
+ default:
+ ret_flag = DEVDRV_FLAG_OFF;
+ break;
+ }
+
+ if (ret_flag == DEVDRV_FLAG_ON)
+ {
+ *ptr = (uint16_t)(*devadd & USB_HOST_DEVADD_MASK);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_get_devadd
+* Description : DEVADDn register is obtained
+* Arguments : uint16_t addr : Device address
+* : uint16_t *devadd : USB_HOST_DEVADD register value
+* Return Value : none
+*******************************************************************************/
+void usb1_host_get_devadd (uint16_t addr, uint16_t * devadd)
+{
+ uint16_t * ptr;
+ uint16_t ret_flag = DEVDRV_FLAG_ON; // avoid warning.
+
+ switch (addr)
+ {
+ case USB_HOST_DEVICE_0:
+ ptr = (uint16_t *)&USB201.DEVADD0;
+ break;
+
+ case USB_HOST_DEVICE_1:
+ ptr = (uint16_t *)&USB201.DEVADD1;
+ break;
+
+ case USB_HOST_DEVICE_2:
+ ptr = (uint16_t *)&USB201.DEVADD2;
+ break;
+
+ case USB_HOST_DEVICE_3:
+ ptr = (uint16_t *)&USB201.DEVADD3;
+ break;
+
+ case USB_HOST_DEVICE_4:
+ ptr = (uint16_t *)&USB201.DEVADD4;
+ break;
+
+ case USB_HOST_DEVICE_5:
+ ptr = (uint16_t *)&USB201.DEVADD5;
+ break;
+
+ case USB_HOST_DEVICE_6:
+ ptr = (uint16_t *)&USB201.DEVADD6;
+ break;
+
+ case USB_HOST_DEVICE_7:
+ ptr = (uint16_t *)&USB201.DEVADD7;
+ break;
+
+ case USB_HOST_DEVICE_8:
+ ptr = (uint16_t *)&USB201.DEVADD8;
+ break;
+
+ case USB_HOST_DEVICE_9:
+ ptr = (uint16_t *)&USB201.DEVADD9;
+ break;
+
+ case USB_HOST_DEVICE_10:
+ ptr = (uint16_t *)&USB201.DEVADDA;
+ break;
+
+ default:
+ ret_flag = DEVDRV_FLAG_OFF;
+ break;
+ }
+
+ if (ret_flag == DEVDRV_FLAG_ON)
+ {
+ *devadd = *ptr;
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_EnableINT_Module
+* Description : Enables BEMP/NRDY/BRDY interrupt and SIGN/SACK interrupt.
+* : Enables NRDY/BEMP interrupt in the pipe0.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void usb1_host_EnableINT_Module (void)
+{
+ uint16_t buf;
+
+ buf = USB201.INTENB0;
+ buf |= (USB_HOST_BITBEMPE | USB_HOST_BITNRDYE | USB_HOST_BITBRDYE);
+ USB201.INTENB0 = buf;
+
+ buf = USB201.INTENB1;
+ buf |= (USB_HOST_BITSIGNE | USB_HOST_BITSACKE);
+ USB201.INTENB1 = buf;
+
+ usb1_host_enable_nrdy_int(USB_HOST_PIPE0);
+ usb1_host_enable_bemp_int(USB_HOST_PIPE0);
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_dmacdrv.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_dmacdrv.c
new file mode 100644
index 000000000..b3cc2e6e0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_dmacdrv.c
@@ -0,0 +1,698 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_dmacdrv.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "rza_io_regrw.h"
+#include "usb1_host_dmacdrv.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DMAC_INDEFINE (255) /* Macro definition when REQD bit is not used */
+
+/* ==== Request setting information for on-chip peripheral module ==== */
+typedef enum dmac_peri_req_reg_type
+{
+ DMAC_REQ_MID,
+ DMAC_REQ_RID,
+ DMAC_REQ_AM,
+ DMAC_REQ_LVL,
+ DMAC_REQ_REQD
+} dmac_peri_req_reg_type_t;
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+/* ==== Prototype declaration ==== */
+
+/* ==== Global variable ==== */
+/* On-chip peripheral module request setting table */
+static const uint8_t usb1_host_dmac_peri_req_init_table[8][5] =
+{
+ /* MID,RID, AM,LVL,REQD */
+ { 32, 3, 2, 1, 1}, /* USB_0 channel 0 transmit FIFO empty */
+ { 32, 3, 2, 1, 0}, /* USB_0 channel 0 receive FIFO full */
+ { 33, 3, 2, 1, 1}, /* USB_0 channel 1 transmit FIFO empty */
+ { 33, 3, 2, 1, 0}, /* USB_0 channel 1 receive FIFO full */
+ { 34, 3, 2, 1, 1}, /* USB_1 channel 0 transmit FIFO empty */
+ { 34, 3, 2, 1, 0}, /* USB_1 channel 0 receive FIFO full */
+ { 35, 3, 2, 1, 1}, /* USB_1 channel 1 transmit FIFO empty */
+ { 35, 3, 2, 1, 0}, /* USB_1 channel 1 receive FIFO full */
+};
+
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 3.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 3 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
+* : : register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous
+* : : transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module
+* : : request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction : Setting value of CHCFG_n register
+* : : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC3_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC3.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC3.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC3.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC3_CHCFG_n_DAD_SHIFT,
+ DMAC3_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC3_CHCFG_n_SAD_SHIFT,
+ DMAC3_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->dst_size,
+ DMAC3_CHCFG_n_DDS_SHIFT,
+ DMAC3_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ trans_info->src_size,
+ DMAC3_CHCFG_n_SDS_SHIFT,
+ DMAC3_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_DMS_SHIFT,
+ DMAC3_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_RSEL_SHIFT,
+ DMAC3_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_SBE_SHIFT,
+ DMAC3_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_DEM_SHIFT,
+ DMAC3_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 1,
+ DMAC3_CHCFG_n_REN_SHIFT,
+ DMAC3_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 1,
+ DMAC3_CHCFG_n_RSW_SHIFT,
+ DMAC3_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_REN_SHIFT,
+ DMAC3_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_RSW_SHIFT,
+ DMAC3_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_TM_SHIFT,
+ DMAC3_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 3,
+ DMAC3_CHCFG_n_SEL_SHIFT,
+ DMAC3_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 1,
+ DMAC3_CHCFG_n_HIEN_SHIFT,
+ DMAC3_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ 0,
+ DMAC3_CHCFG_n_LOEN_SHIFT,
+ DMAC3_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC3_CHCFG_n_AM_SHIFT,
+ DMAC3_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC3_CHCFG_n_LVL_SHIFT,
+ DMAC3_CHCFG_n_LVL);
+ if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC3_CHCFG_n_REQD_SHIFT,
+ DMAC3_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC3.CHCFG_n,
+ req_direction,
+ DMAC3_CHCFG_n_REQD_SHIFT,
+ DMAC3_CHCFG_n_REQD);
+ }
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC23_DMARS_CH3_RID_SHIFT,
+ DMAC23_DMARS_CH3_RID);
+ RZA_IO_RegWrite_32(&DMAC23.DMARS,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC23_DMARS_CH3_MID_SHIFT,
+ DMAC23_DMARS_CH3_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_Open
+* Description : Enables DMAC channel 3 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb1_host_DMAC3_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_EN_SHIFT,
+ DMAC3_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_TACT_SHIFT,
+ DMAC3_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_SWRST_SHIFT,
+ DMAC3_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC3.CHCTRL_n,
+ DMAC3_CHCTRL_n_SWRST_SHIFT,
+ DMAC3_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_SETEN_SHIFT,
+ DMAC3_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_STG_SHIFT,
+ DMAC3_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_Close
+* Description : Aborts DMAC channel 3 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC3_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC3.CHCTRL_n,
+ 1,
+ DMAC3_CHCTRL_n_CLREN_SHIFT,
+ DMAC3_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_TACT_SHIFT,
+ DMAC3_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_EN_SHIFT,
+ DMAC3_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC3.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC3_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 3 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 3 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC3_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC3.CHSTAT_n,
+ DMAC3_CHSTAT_n_SR_SHIFT,
+ DMAC3_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC3.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC3.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC3.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC3.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC3.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC3.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_PeriReqInit
+* Description : Sets the register mode for DMA mode and the on-chip peripheral
+* : module request for transfer request for DMAC channel 4.
+* : Executes DMAC initial setting using the DMA information
+* : specified by the argument *trans_info and the enabled/disabled
+* : continuous transfer specified by the argument continuation.
+* : Registers DMAC channel 4 interrupt handler function and sets
+* : the interrupt priority level. Then enables transfer completion
+* : interrupt.
+* Arguments : dmac_transinfo_t * trans_info : Setting information to DMAC
+* : : register
+* : uint32_t dmamode : DMA mode (only for DMAC_MODE_REGISTER)
+* : uint32_t continuation : Set continuous transfer to be valid
+* : : after DMA transfer has been completed
+* : DMAC_SAMPLE_CONTINUATION : Execute continuous transfer
+* : DMAC_SAMPLE_SINGLE : Do not execute continuous
+* : : transfer
+* : uint32_t request_factor : Factor for on-chip peripheral module
+* : : request
+* : DMAC_REQ_OSTM0TINT : OSTM_0 compare match
+* : DMAC_REQ_OSTM1TINT : OSTM_1 compare match
+* : DMAC_REQ_TGI0A : MTU2_0 input capture/compare match
+* : :
+* : uint32_t req_direction : Setting value of CHCFG_n register
+* : : REQD bit
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC4_PeriReqInit (const dmac_transinfo_t * trans_info, uint32_t dmamode, uint32_t continuation,
+ uint32_t request_factor, uint32_t req_direction)
+{
+ /* ==== Register mode ==== */
+ if (DMAC_MODE_REGISTER == dmamode)
+ {
+ /* ==== Next0 register set ==== */
+ DMAC4.N0SA_n = trans_info->src_addr; /* Start address of transfer source */
+ DMAC4.N0DA_n = trans_info->dst_addr; /* Start address of transfer destination */
+ DMAC4.N0TB_n = trans_info->count; /* Total transfer byte count */
+
+ /* DAD : Transfer destination address counting direction */
+ /* SAD : Transfer source address counting direction */
+ /* DDS : Transfer destination transfer size */
+ /* SDS : Transfer source transfer size */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->daddr_dir,
+ DMAC4_CHCFG_n_DAD_SHIFT,
+ DMAC4_CHCFG_n_DAD);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->saddr_dir,
+ DMAC4_CHCFG_n_SAD_SHIFT,
+ DMAC4_CHCFG_n_SAD);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->dst_size,
+ DMAC4_CHCFG_n_DDS_SHIFT,
+ DMAC4_CHCFG_n_DDS);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ trans_info->src_size,
+ DMAC4_CHCFG_n_SDS_SHIFT,
+ DMAC4_CHCFG_n_SDS);
+
+ /* DMS : Register mode */
+ /* RSEL : Select Next0 register set */
+ /* SBE : No discharge of buffer data when aborted */
+ /* DEM : No DMA interrupt mask */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_DMS_SHIFT,
+ DMAC4_CHCFG_n_DMS);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_RSEL_SHIFT,
+ DMAC4_CHCFG_n_RSEL);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_SBE_SHIFT,
+ DMAC4_CHCFG_n_SBE);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_DEM_SHIFT,
+ DMAC4_CHCFG_n_DEM);
+
+ /* ---- Continuous transfer ---- */
+ if (DMAC_SAMPLE_CONTINUATION == continuation)
+ {
+ /* REN : Execute continuous transfer */
+ /* RSW : Change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 1,
+ DMAC4_CHCFG_n_REN_SHIFT,
+ DMAC4_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 1,
+ DMAC4_CHCFG_n_RSW_SHIFT,
+ DMAC4_CHCFG_n_RSW);
+ }
+ /* ---- Single transfer ---- */
+ else
+ {
+ /* REN : Do not execute continuous transfer */
+ /* RSW : Do not change register set when DMA transfer is completed. */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_REN_SHIFT,
+ DMAC4_CHCFG_n_REN);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_RSW_SHIFT,
+ DMAC4_CHCFG_n_RSW);
+ }
+
+ /* TM : Single transfer */
+ /* SEL : Channel setting */
+ /* HIEN, LOEN : On-chip peripheral module request */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_TM_SHIFT,
+ DMAC4_CHCFG_n_TM);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 4,
+ DMAC4_CHCFG_n_SEL_SHIFT,
+ DMAC4_CHCFG_n_SEL);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 1,
+ DMAC4_CHCFG_n_HIEN_SHIFT,
+ DMAC4_CHCFG_n_HIEN);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ 0,
+ DMAC4_CHCFG_n_LOEN_SHIFT,
+ DMAC4_CHCFG_n_LOEN);
+
+ /* ---- Set factor by specified on-chip peripheral module request ---- */
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_AM],
+ DMAC4_CHCFG_n_AM_SHIFT,
+ DMAC4_CHCFG_n_AM);
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_LVL],
+ DMAC4_CHCFG_n_LVL_SHIFT,
+ DMAC4_CHCFG_n_LVL);
+ if (usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD] != DMAC_INDEFINE)
+ {
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_REQD],
+ DMAC4_CHCFG_n_REQD_SHIFT,
+ DMAC4_CHCFG_n_REQD);
+ }
+ else
+ {
+ RZA_IO_RegWrite_32(&DMAC4.CHCFG_n,
+ req_direction,
+ DMAC4_CHCFG_n_REQD_SHIFT,
+ DMAC4_CHCFG_n_REQD);
+ }
+ RZA_IO_RegWrite_32(&DMAC45.DMARS,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_RID],
+ DMAC45_DMARS_CH4_RID_SHIFT,
+ DMAC45_DMARS_CH4_RID);
+ RZA_IO_RegWrite_32(&DMAC45.DMARS,
+ usb1_host_dmac_peri_req_init_table[request_factor][DMAC_REQ_MID],
+ DMAC45_DMARS_CH4_MID_SHIFT,
+ DMAC45_DMARS_CH4_MID);
+
+ /* PR : Round robin mode */
+ RZA_IO_RegWrite_32(&DMAC07.DCTRL_0_7,
+ 1,
+ DMAC07_DCTRL_0_7_PR_SHIFT,
+ DMAC07_DCTRL_0_7_PR);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_Open
+* Description : Enables DMAC channel 4 transfer.
+* Arguments : uint32_t req : DMAC request mode
+* Return Value : 0 : Succeeded in enabling DMA transfer
+* : -1 : Failed to enable DMA transfer (due to DMA operation)
+*******************************************************************************/
+int32_t usb1_host_DMAC4_Open (uint32_t req)
+{
+ int32_t ret;
+ volatile uint8_t dummy;
+
+ /* Transferable? */
+ if ((0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_EN_SHIFT,
+ DMAC4_CHSTAT_n_EN)) &&
+ (0 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_TACT_SHIFT,
+ DMAC4_CHSTAT_n_TACT)))
+ {
+ /* Clear Channel Status Register */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_SWRST_SHIFT,
+ DMAC4_CHCTRL_n_SWRST);
+ dummy = RZA_IO_RegRead_32(&DMAC4.CHCTRL_n,
+ DMAC4_CHCTRL_n_SWRST_SHIFT,
+ DMAC4_CHCTRL_n_SWRST);
+ /* Enable DMA transfer */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_SETEN_SHIFT,
+ DMAC4_CHCTRL_n_SETEN);
+
+ /* ---- Request by software ---- */
+ if (DMAC_REQ_MODE_SOFT == req)
+ {
+ /* DMA transfer Request by software */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_STG_SHIFT,
+ DMAC4_CHCTRL_n_STG);
+ }
+
+ ret = 0;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_Close
+* Description : Aborts DMAC channel 4 transfer. Returns the remaining transfer
+* : byte count at the time of DMA transfer abort to the argument
+* : *remain.
+* Arguments : uint32_t * remain : Remaining transfer byte count when
+* : : DMA transfer is aborted
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC4_Close (uint32_t * remain)
+{
+
+ /* ==== Abort transfer ==== */
+ RZA_IO_RegWrite_32(&DMAC4.CHCTRL_n,
+ 1,
+ DMAC4_CHCTRL_n_CLREN_SHIFT,
+ DMAC4_CHCTRL_n_CLREN);
+
+ while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_TACT_SHIFT,
+ DMAC4_CHSTAT_n_TACT))
+ {
+ /* Loop until transfer is aborted */
+ }
+
+ while (1 == RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_EN_SHIFT,
+ DMAC4_CHSTAT_n_EN))
+ {
+ /* Loop until 0 is set in EN before checking the remaining transfer byte count */
+ }
+ /* ==== Obtain remaining transfer byte count ==== */
+ *remain = DMAC4.CRTB_n;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_DMAC4_Load_Set
+* Description : Sets the transfer source address, transfer destination
+* : address, and total transfer byte count respectively
+* : specified by the argument src_addr, dst_addr, and count to
+* : DMAC channel 4 as DMA transfer information.
+* : Sets the register set selected by the CHCFG_n register
+* : RSEL bit from the Next0 or Next1 register set.
+* : This function should be called when DMA transfer of DMAC
+* : channel 4 is aboted.
+* Arguments : uint32_t src_addr : Transfer source address
+* : uint32_t dst_addr : Transfer destination address
+* : uint32_t count : Total transfer byte count
+* Return Value : none
+*******************************************************************************/
+void usb1_host_DMAC4_Load_Set (uint32_t src_addr, uint32_t dst_addr, uint32_t count)
+{
+ uint8_t reg_set;
+
+ /* Obtain register set in use */
+ reg_set = RZA_IO_RegRead_32(&DMAC4.CHSTAT_n,
+ DMAC4_CHSTAT_n_SR_SHIFT,
+ DMAC4_CHSTAT_n_SR);
+
+ /* ==== Load ==== */
+ if (0 == reg_set)
+ {
+ /* ---- Next0 Register Set ---- */
+ DMAC4.N0SA_n = src_addr; /* Start address of transfer source */
+ DMAC4.N0DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC4.N0TB_n = count; /* Total transfer byte count */
+ }
+ else
+ {
+ /* ---- Next1 Register Set ---- */
+ DMAC4.N1SA_n = src_addr; /* Start address of transfer source */
+ DMAC4.N1DA_n = dst_addr; /* Start address of transfer destination */
+ DMAC4.N1TB_n = count; /* Total transfer byte count */
+ }
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_userdef.c b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_userdef.c
new file mode 100644
index 000000000..f002e54b0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb1/src/userdef/usb1_host_userdef.c
@@ -0,0 +1,778 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+/*******************************************************************************
+* File Name : usb1_host_userdef.c
+* $Rev: 1116 $
+* $Date:: 2014-07-09 16:29:19 +0900#$
+* Device(s) : RZ/A1H
+* Tool-Chain :
+* OS : None
+* H/W Platform :
+* Description : RZ/A1H R7S72100 USB Sample Program
+* Operation :
+* Limitations :
+*******************************************************************************/
+
+
+/*******************************************************************************
+Includes <System Includes> , "Project Includes"
+*******************************************************************************/
+#include <stdio.h>
+#include "cmsis_os.h"
+#include "r_typedefs.h"
+#include "iodefine.h"
+#include "devdrv_usb_host_api.h"
+#include "usb1_host.h"
+#include "MBRZA1H.h" /* INTC Driver Header */
+#include "usb1_host_dmacdrv.h"
+#include "ohci_wrapp_RZ_A1_local.h"
+
+
+/*******************************************************************************
+Typedef definitions
+*******************************************************************************/
+
+
+/*******************************************************************************
+Macro definitions
+*******************************************************************************/
+#define DUMMY_ACCESS OSTM0CNT
+
+/* #define CACHE_WRITEBACK */
+
+
+/*******************************************************************************
+Imported global variables and functions (from other files)
+*******************************************************************************/
+extern int32_t io_cwb(unsigned long start, unsigned long end);
+
+
+/*******************************************************************************
+Exported global variables and functions (to be accessed by other files)
+*******************************************************************************/
+static void usb1_host_enable_dmac0(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void usb1_host_enable_dmac1(uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc);
+static void Userdef_USB_usb1_host_delay_10us_2(void);
+
+
+/*******************************************************************************
+Private global variables and functions
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_d0fifo_dmaintid
+* Description : get D0FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D0FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb1_host_d0fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+ return 0xFFFF;
+#else
+ return DMAINT1_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_d1fifo_dmaintid
+* Description : get D1FIFO DMA Interrupt ID
+* Arguments : none
+* Return Value : D1FIFO DMA Interrupt ID
+*******************************************************************************/
+uint16_t Userdef_USB_usb1_host_d1fifo_dmaintid (void)
+{
+#if(1) /* ohci_wrapp */
+ return 0xFFFF;
+#else
+ return DMAINT2_IRQn;
+#endif
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_attach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_attach (void)
+{
+// printf("\n");
+// printf("channel 1 attach device\n");
+// printf("\n");
+ ohciwrapp_loc_Connect(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_detach
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_detach (void)
+{
+// printf("\n");
+// printf("channel 1 detach device\n");
+// printf("\n");
+ ohciwrapp_loc_Connect(0);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_1ms
+* Description : Wait for the software of 1ms.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_1ms (void)
+{
+ osDelay(1);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_xms
+* Description : Wait for the software in the period of time specified by the
+* : argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t msec ; Wait Time (msec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_xms (uint32_t msec)
+{
+ osDelay(msec);
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_10us
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : uint32_t usec ; Wait Time(x 10usec)
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_10us (uint32_t usec)
+{
+ volatile int i;
+
+ /* Wait 10us (Please change for your MCU) */
+ for (i = 0; i < usec; ++i)
+ {
+ Userdef_USB_usb1_host_delay_10us_2();
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_10us_2
+* Description : Waits for software for the period specified by the argument.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+static void Userdef_USB_usb1_host_delay_10us_2 (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 1us (Please change for your MCU) */
+ for (i = 0; i < 14; ++i)
+ {
+ tmp = DUMMY_ACCESS;
+ }
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_delay_500ns
+* Description : Wait for software for 500ns.
+* : Alter this function according to the user's system.
+* Arguments : none
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_delay_500ns (void)
+{
+ volatile int i;
+ volatile unsigned long tmp;
+
+ /* Wait 500ns (Please change for your MCU) */
+ /* Wait 500ns I clock 266MHz */
+ tmp = DUMMY_ACCESS;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_start_dma
+* Description : Enables DMA transfer on the information specified by the argument.
+* : Set DMAC register by this function to enable DMA transfer.
+* : After executing this function, USB module is set to start DMA
+* : transfer. DMA transfer should not wait for DMA transfer complete.
+* Arguments : USB_HOST_DMA_t *dma : DMA parameter
+* : typedef struct{
+* : uint32_t fifo; FIFO for using
+* : uint32_t buffer; Start address of transfer source/destination
+* : uint32_t bytes; Transfer size(Byte)
+* : uint32_t dir; Transfer direction(0:Buffer->FIFO, 1:FIFO->Buffer)
+* : uint32_t size; DMA transfer size
+* : } USB_HOST_DMA_t;
+* : uint16_t dfacc ; 0 : cycle steal mode
+* : 1 : 16byte continuous mode
+* : 2 : 32byte continuous mode
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_start_dma (USB_HOST_DMA_t * dma, uint16_t dfacc)
+{
+ uint32_t trncount;
+ uint32_t src;
+ uint32_t dst;
+ uint32_t size;
+ uint32_t dir;
+#ifdef CACHE_WRITEBACK
+ uint32_t ptr;
+#endif
+
+ trncount = dma->bytes;
+ dir = dma->dir;
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ /* DxFIFO determination */
+ dst = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ src += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ src += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ src = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ src = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ src += 3; /* byte access */
+ }
+#endif
+ }
+ else
+ {
+ /* DxFIFO determination */
+ src = dma->buffer;
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ size = dma->size;
+
+ if (size == 0)
+ {
+ dst += 3; /* byte access */
+ }
+ else if (size == 1)
+ {
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+#else
+ size = dma->size;
+ if (size == 2)
+ {
+ /* 32bit access */
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFOB0);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFOB0);
+ }
+ }
+ else
+ {
+ /* normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ }
+ }
+ else if (size == 1)
+ {
+ /* 16bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ dst += 2; /* short access */
+ }
+ else
+ {
+ /* 8bit access */
+ dfacc = 0; /* force normal access */
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ dst = (uint32_t)(&USB201.D0FIFO.UINT32);
+ }
+ else
+ {
+ dst = (uint32_t)(&USB201.D1FIFO.UINT32);
+ }
+ dst += 3; /* byte access */
+ }
+#endif
+ }
+
+#ifdef CACHE_WRITEBACK
+ ptr = (uint32_t)dma->buffer;
+ if ((ptr & 0x20000000ul) == 0)
+ {
+ io_cwb((uint32_t)ptr,(uint32_t)(ptr)+trncount);
+ }
+#endif
+
+ if (dma->fifo == USB_HOST_D0FIFO_DMA)
+ {
+ usb1_host_enable_dmac0(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+ else
+ {
+ usb1_host_enable_dmac1(src, dst, trncount, size, dir, dma->fifo, dfacc);
+ }
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_dmac0
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_enable_dmac0 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ request_factor = DMAC_REQ_USB1_DMA0_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_HOST_BUF2FIFO)
+ {
+ request_factor = DMAC_REQ_USB1_DMA0_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb1_host_DMAC3_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in usb1_host_DMAC3_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb1_host_DMAC3_Open(DMAC_REQ_MODE_PERI);
+
+ if (ret != 0)
+ {
+// printf("DMAC3 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: usb1_host_enable_dmac1
+* Description : Enables DMA transfer on the information specified by the argument.
+* Arguments : uint32_t src : src address
+* : uint32_t dst : dst address
+* : uint32_t count : transfer byte
+* : uint32_t size : transfer size
+* : uint32_t dir : direction
+* : uint32_t fifo : FIFO(D0FIFO or D1FIFO)
+* : uint16_t dfacc : 0 : normal access
+* : : 1 : 16byte access
+* : : 2 : 32byte access
+* Return Value : none
+*******************************************************************************/
+static void usb1_host_enable_dmac1 (uint32_t src, uint32_t dst, uint32_t count,
+ uint32_t size, uint32_t dir, uint32_t fifo, uint16_t dfacc)
+{
+ dmac_transinfo_t trans_info;
+ uint32_t request_factor = 0;
+ int32_t ret;
+
+ /* ==== Variable setting for DMAC initialization ==== */
+ trans_info.src_addr = (uint32_t)src; /* Start address of transfer source */
+ trans_info.dst_addr = (uint32_t)dst; /* Start address of transfer destination */
+ trans_info.count = (uint32_t)count; /* Total byte count to be transferred */
+#ifndef __USB_HOST_DF_ACC_ENABLE__
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+#else
+ if (dfacc == 2)
+ {
+ /* 32byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_256; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_256; /* Transfer destination transfer size */
+ }
+ else if (dfacc == 1)
+ {
+ /* 16byte access */
+ trans_info.src_size = DMAC_TRANS_SIZE_128; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_128; /* Transfer destination transfer size */
+ }
+ else
+ {
+ /* normal access */
+ if (size == 0)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_8; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_8; /* Transfer destination transfer size */
+ }
+ else if (size == 1)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_16; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_16; /* Transfer destination transfer size */
+ }
+ else if (size == 2)
+ {
+ trans_info.src_size = DMAC_TRANS_SIZE_32; /* Transfer source transfer size */
+ trans_info.dst_size = DMAC_TRANS_SIZE_32; /* Transfer destination transfer size */
+ }
+ else
+ {
+// printf("size error!!\n");
+ }
+ }
+#endif
+
+ if (dir == USB_HOST_FIFO2BUF)
+ {
+ request_factor =DMAC_REQ_USB1_DMA1_RX; /* USB_0 channel 0 receive FIFO full */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer destination address */
+ }
+ else if (dir == USB_HOST_BUF2FIFO)
+ {
+ request_factor =DMAC_REQ_USB1_DMA1_TX; /* USB_0 channel 0 receive FIFO empty */
+ trans_info.saddr_dir = DMAC_TRANS_ADR_INC; /* Count direction of transfer source address */
+ trans_info.daddr_dir = DMAC_TRANS_ADR_NO_INC; /* Count direction of transfer destination address */
+ }
+ else
+ {
+ /* Do Nothing */
+ }
+
+ /* ==== DMAC initialization ==== */
+ usb1_host_DMAC4_PeriReqInit((const dmac_transinfo_t *)&trans_info,
+ DMAC_MODE_REGISTER,
+ DMAC_SAMPLE_SINGLE,
+ request_factor,
+ 0); /* Don't care DMAC_REQ_REQD is setting in usb1_host_DMAC4_PeriReqInit() */
+
+ /* ==== DMAC startup ==== */
+ ret = usb1_host_DMAC4_Open(DMAC_REQ_MODE_PERI);
+
+ if (ret != 0)
+ {
+// printf("DMAC4 Open error!!\n");
+ }
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_stop_dma0
+* Description : Disables DMA transfer.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+* Notice : This function should be executed to DMAC executed at the time
+* : of specification of D0_FIF0_DMA in dma->fifo.
+*******************************************************************************/
+uint32_t Userdef_USB_usb1_host_stop_dma0 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb1_host_DMAC3_Close(&remain);
+
+ return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_stop_dma1
+* Description : Disables DMA transfer.
+* : This function should be executed to DMAC executed at the time
+* : of specification of D1_FIF0_DMA in dma->fifo.
+* Arguments : none
+* Return Value : uint32_t return Transfer Counter register(DMATCRn) value
+* : regarding to the bus width.
+*******************************************************************************/
+uint32_t Userdef_USB_usb1_host_stop_dma1 (void)
+{
+ uint32_t remain;
+
+ /* ==== DMAC release ==== */
+ usb1_host_DMAC4_Close(&remain);
+
+ return remain;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_notice
+* Description : Notice of USER
+* Arguments : const char *format
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_notice (const char * format)
+{
+// printf(format);
+
+ return;
+}
+
+/*******************************************************************************
+* Function Name: Userdef_USB_usb1_host_user_rdy
+* Description : This function notify a user and wait for trigger
+* Arguments : const char *format
+* : uint16_t data
+* Return Value : none
+*******************************************************************************/
+void Userdef_USB_usb1_host_user_rdy (const char * format, uint16_t data)
+{
+// printf(format, data);
+ getchar();
+
+ return;
+}
+
+/* End of File */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb_host_setting.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb_host_setting.h
new file mode 100644
index 000000000..b1c450cd1
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb_host_setting.h
@@ -0,0 +1,100 @@
+/*******************************************************************************
+* DISCLAIMER
+* This software is supplied by Renesas Electronics Corporation and is only
+* intended for use with Renesas products. No other uses are authorized. This
+* software is owned by Renesas Electronics Corporation and is protected under
+* all applicable laws, including copyright laws.
+* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
+* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
+* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
+* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
+* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
+* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
+* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
+* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
+* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+* Renesas reserves the right, without notice, to make changes to this software
+* and to discontinue the availability of this software. By using this software,
+* you agree to the additional terms and conditions found by accessing the
+* following link:
+* http://www.renesas.com/disclaimer
+* Copyright (C) 2014 - 2015 Renesas Electronics Corporation. All rights reserved.
+*******************************************************************************/
+
+#ifndef USB_HOST_SETTING_H
+#define USB_HOST_SETTING_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define USB_HOST_CH 0
+#define USB_HOST_HISPEED 1
+
+#define INT_TRANS_MAX_NUM 4 /* min:1 max:4 */
+#define ISO_TRANS_MAX_NUM 0 /* min:0 max:2 */
+
+#if (USB_HOST_CH == 0)
+#include "usb0_host.h"
+#define USB20X USB200
+#define USBIXUSBIX USBI0_IRQn
+#define g_usbx_host_SupportUsbDeviceSpeed g_usb0_host_SupportUsbDeviceSpeed
+#define g_usbx_host_UsbDeviceSpeed g_usb0_host_UsbDeviceSpeed
+#define g_usbx_host_CmdStage g_usb0_host_CmdStage
+#define g_usbx_host_pipe_status g_usb0_host_pipe_status
+#define g_usbx_host_data_pointer g_usb0_host_data_pointer
+#define g_usbx_host_data_count g_usb0_host_data_count
+#define usbx_api_host_init usb0_api_host_init
+#define usbx_host_UsbBusReset usb0_host_UsbBusReset
+#define usbx_host_get_devadd usb0_host_get_devadd
+#define usbx_host_set_devadd usb0_host_set_devadd
+#define usbx_host_SetupStage usb0_host_SetupStage
+#define usbx_host_CtrlWriteStart usb0_host_CtrlWriteStart
+#define usbx_host_CtrlReadStart usb0_host_CtrlReadStart
+#define usbx_api_host_SetEndpointTable usb0_api_host_SetEndpointTable
+#define usbx_host_start_send_transfer usb0_host_start_send_transfer
+#define usbx_host_start_receive_transfer usb0_host_start_receive_transfer
+#define usbx_host_stop_transfer usb0_host_stop_transfer
+#define usbx_host_set_sqclr usb0_host_set_sqclr
+#define usbx_host_set_sqset usb0_host_set_sqset
+#define usbx_host_CheckAttach usb0_host_CheckAttach
+#define usbx_host_UsbDetach usb0_host_UsbDetach
+#define usbx_host_UsbAttach usb0_host_UsbAttach
+#define usbx_host_init_pipe_status usb0_host_init_pipe_status
+#define usbx_host_get_sqmon usb0_host_get_sqmon
+#else
+#include "usb1_host.h"
+#define USB20X USB201
+#define USBIXUSBIX USBI1_IRQn
+#define g_usbx_host_SupportUsbDeviceSpeed g_usb1_host_SupportUsbDeviceSpeed
+#define g_usbx_host_UsbDeviceSpeed g_usb1_host_UsbDeviceSpeed
+#define g_usbx_host_CmdStage g_usb1_host_CmdStage
+#define g_usbx_host_pipe_status g_usb1_host_pipe_status
+#define g_usbx_host_data_pointer g_usb1_host_data_pointer
+#define g_usbx_host_data_count g_usb1_host_data_count
+#define usbx_api_host_init usb1_api_host_init
+#define usbx_host_UsbBusReset usb1_host_UsbBusReset
+#define usbx_host_get_devadd usb1_host_get_devadd
+#define usbx_host_set_devadd usb1_host_set_devadd
+#define usbx_host_SetupStage usb1_host_SetupStage
+#define usbx_host_CtrlWriteStart usb1_host_CtrlWriteStart
+#define usbx_host_CtrlReadStart usb1_host_CtrlReadStart
+#define usbx_api_host_SetEndpointTable usb1_api_host_SetEndpointTable
+#define usbx_host_start_send_transfer usb1_host_start_send_transfer
+#define usbx_host_start_receive_transfer usb1_host_start_receive_transfer
+#define usbx_host_stop_transfer usb1_host_stop_transfer
+#define usbx_host_set_sqclr usb1_host_set_sqclr
+#define usbx_host_set_sqset usb1_host_set_sqset
+#define usbx_host_CheckAttach usb1_host_CheckAttach
+#define usbx_host_UsbDetach usb1_host_UsbDetach
+#define usbx_host_UsbAttach usb1_host_UsbAttach
+#define usbx_host_init_pipe_status usb1_host_init_pipe_status
+#define usbx_host_get_sqmon usb1_host_get_sqmon
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* USB_HOST_SETTING_H */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBDeviceConnected.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBDeviceConnected.cpp
new file mode 100644
index 000000000..8314b3ef4
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBDeviceConnected.cpp
@@ -0,0 +1,124 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBDeviceConnected.h"
+#include "dbg.h"
+
+USBDeviceConnected::USBDeviceConnected() {
+ init();
+}
+
+void USBDeviceConnected::init() {
+ hub_nb = 0;
+ port = 0;
+ vid = 0;
+ pid = 0;
+ nb_interf = 0;
+ enumerated = false;
+ activeAddr = false;
+ sizeControlEndpoint = 8;
+ device_class = 0;
+ device_subclass = 0;
+ proto = 0;
+ speed = false;
+ for (int i = 0; i < MAX_INTF; i++) {
+ memset((void *)&intf[i], 0, sizeof(INTERFACE));
+ intf[i].in_use = false;
+ for (int j = 0; j < MAX_ENDPOINT_PER_INTERFACE; j++) {
+ intf[i].ep[j] = NULL;
+ strcpy(intf[i].name, "Unknown");
+ }
+ }
+ hub_parent = NULL;
+ hub = NULL;
+ nb_interf = 0;
+}
+
+INTERFACE * USBDeviceConnected::getInterface(uint8_t index) {
+ if (index >= MAX_INTF)
+ return NULL;
+
+ if (intf[index].in_use)
+ return &intf[index];
+
+ return NULL;
+}
+
+bool USBDeviceConnected::addInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) {
+ if ((intf_nb >= MAX_INTF) || (intf[intf_nb].in_use)) {
+ return false;
+ }
+ intf[intf_nb].in_use = true;
+ intf[intf_nb].intf_class = intf_class;
+ intf[intf_nb].intf_subclass = intf_subclass;
+ intf[intf_nb].intf_protocol = intf_protocol;
+ intf[intf_nb].nb_endpoint = 0;
+ return true;
+}
+
+bool USBDeviceConnected::addEndpoint(uint8_t intf_nb, USBEndpoint * ept) {
+ if ((intf_nb >= MAX_INTF) || (intf[intf_nb].in_use == false) || (intf[intf_nb].nb_endpoint >= MAX_ENDPOINT_PER_INTERFACE)) {
+ return false;
+ }
+ intf[intf_nb].nb_endpoint++;
+
+ for (int i = 0; i < MAX_ENDPOINT_PER_INTERFACE; i++) {
+ if (intf[intf_nb].ep[i] == NULL) {
+ intf[intf_nb].ep[i] = ept;
+ return true;
+ }
+ }
+ return false;
+}
+
+void USBDeviceConnected::init(uint8_t hub_, uint8_t port_, bool lowSpeed_) {
+ USB_DBG("init dev: %p", this);
+ init();
+ hub_nb = hub_;
+ port = port_;
+ speed = lowSpeed_;
+}
+
+void USBDeviceConnected::disconnect() {
+ for(int i = 0; i < MAX_INTF; i++) {
+ intf[i].detach.call();
+ }
+ init();
+}
+
+
+USBEndpoint * USBDeviceConnected::getEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint8_t index) {
+ if (intf_nb >= MAX_INTF) {
+ return NULL;
+ }
+ for (int i = 0; i < MAX_ENDPOINT_PER_INTERFACE; i++) {
+ if ((intf[intf_nb].ep[i]->getType() == type) && (intf[intf_nb].ep[i]->getDir() == dir)) {
+ if(index) {
+ index--;
+ } else {
+ return intf[intf_nb].ep[i];
+ }
+ }
+ }
+ return NULL;
+}
+
+USBEndpoint * USBDeviceConnected::getEndpoint(uint8_t intf_nb, uint8_t index) {
+ if ((intf_nb >= MAX_INTF) || (index >= MAX_ENDPOINT_PER_INTERFACE)) {
+ return NULL;
+ }
+ return intf[intf_nb].ep[index];
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBDeviceConnected.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBDeviceConnected.h
new file mode 100644
index 000000000..22a4c1d3e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBDeviceConnected.h
@@ -0,0 +1,185 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBDEVICECONNECTED_H
+#define USBDEVICECONNECTED_H
+
+#include "stdint.h"
+#include "USBEndpoint.h"
+#include "USBHostConf.h"
+#include "rtos.h"
+
+class USBHostHub;
+
+typedef struct {
+ bool in_use;
+ uint8_t nb_endpoint;
+ uint8_t intf_class;
+ uint8_t intf_subclass;
+ uint8_t intf_protocol;
+ USBEndpoint * ep[MAX_ENDPOINT_PER_INTERFACE];
+ FunctionPointer detach;
+ char name[10];
+} INTERFACE;
+
+/**
+* USBDeviceConnected class
+*/
+class USBDeviceConnected
+{
+public:
+
+ /**
+ * Constructor
+ */
+ USBDeviceConnected();
+
+ /**
+ * Attach an USBEndpoint to this device
+ *
+ * @param intf_nb interface number
+ * @param ep pointeur on the USBEndpoint which will be attached
+ * @returns true if successful, false otherwise
+ */
+ bool addEndpoint(uint8_t intf_nb, USBEndpoint * ep);
+
+ /**
+ * Retrieve an USBEndpoint by its TYPE and DIRECTION
+ *
+ * @param intf_nb the interface on which to lookup the USBEndpoint
+ * @param type type of the USBEndpoint looked for
+ * @param dir direction of the USBEndpoint looked for
+ * @param index the index of the USBEndpoint whitin the interface
+ * @returns pointer on the USBEndpoint if found, NULL otherwise
+ */
+ USBEndpoint * getEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint8_t index = 0);
+
+ /**
+ * Retrieve an USBEndpoint by its index
+ *
+ * @param intf_nb interface number
+ * @param index index of the USBEndpoint
+ * @returns pointer on the USBEndpoint if found, NULL otherwise
+ */
+ USBEndpoint * getEndpoint(uint8_t intf_nb, uint8_t index);
+
+ /**
+ * Add a new interface to this device
+ *
+ * @param intf_nb interface number
+ * @param intf_class interface class
+ * @param intf_subclass interface subclass
+ * @param intf_protocol interface protocol
+ * @returns true if successful, false otherwise
+ */
+ bool addInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol);
+
+ /**
+ * Get a specific interface
+ *
+ * @param index index of the interface to be fetched
+ * @returns interface
+ */
+ INTERFACE * getInterface(uint8_t index);
+
+ /**
+ * Attach a member function to call when a the device has been disconnected
+ *
+ * @param intf_nb interface number
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ */
+ template<typename T>
+ inline void onDisconnect(uint8_t intf_nb, T* tptr, void (T::*mptr)(void)) {
+ if ((mptr != NULL) && (tptr != NULL)) {
+ intf[intf_nb].detach.attach(tptr, mptr);
+ }
+ }
+
+ /**
+ * Attach a callback called when the device has been disconnected
+ *
+ * @param intf_nb interface number
+ * @param fn function pointer
+ */
+ inline void onDisconnect(uint8_t intf_nb, void (*fn)(void)) {
+ if (fn != NULL) {
+ intf[intf_nb].detach.attach(fn);
+ }
+ }
+
+ /**
+ * Disconnect the device by calling a callback function registered by a driver
+ */
+ void disconnect();
+
+ // setters
+ void init(uint8_t hub, uint8_t port, bool lowSpeed);
+ inline void setAddress(uint8_t addr_) { addr = addr_; };
+ inline void setVid(uint16_t vid_) { vid = vid_; };
+ inline void setPid(uint16_t pid_) { pid = pid_; };
+ inline void setClass(uint8_t device_class_) { device_class = device_class_; };
+ inline void setSubClass(uint8_t device_subclass_) { device_subclass = device_subclass_; };
+ inline void setProtocol(uint8_t pr) { proto = pr; };
+ inline void setSizeControlEndpoint(uint32_t size) { sizeControlEndpoint = size; };
+ inline void activeAddress(bool active) { activeAddr = active; };
+ inline void setEnumerated() { enumerated = true; };
+ inline void setNbIntf(uint8_t nb_intf) {nb_interf = nb_intf; };
+ inline void setHubParent(USBHostHub * hub) { hub_parent = hub; };
+ inline void setName(const char * name_, uint8_t intf_nb) { strcpy(intf[intf_nb].name, name_); };
+
+ //getters
+ inline uint8_t getPort() { return port; };
+ inline uint8_t getHub() { return hub_nb; };
+ inline uint8_t getAddress() { return addr; };
+ inline uint16_t getVid() { return vid; };
+ inline uint16_t getPid() { return pid; };
+ inline uint8_t getClass() { return device_class; };
+ inline uint8_t getSubClass() { return device_subclass; };
+ inline uint8_t getProtocol() { return proto; };
+ inline bool getSpeed() { return speed; };
+ inline uint32_t getSizeControlEndpoint() { return sizeControlEndpoint; };
+ inline bool isActiveAddress() { return activeAddr; };
+ inline bool isEnumerated() { return enumerated; };
+ inline USBHostHub * getHubParent() { return hub_parent; };
+ inline uint8_t getNbIntf() { return nb_interf; };
+ inline const char * getName(uint8_t intf_nb) { return intf[intf_nb].name; };
+
+ // in case this device is a hub
+ USBHostHub * hub;
+
+private:
+ USBHostHub * hub_parent;
+
+ INTERFACE intf[MAX_INTF];
+ uint32_t sizeControlEndpoint;
+ uint8_t hub_nb;
+ uint8_t port;
+ uint16_t vid;
+ uint16_t pid;
+ uint8_t addr;
+ uint8_t device_class;
+ uint8_t device_subclass;
+ uint8_t proto;
+ bool speed;
+ volatile bool activeAddr;
+ volatile bool enumerated;
+ uint8_t nb_interf;
+
+ void init();
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBEndpoint.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBEndpoint.cpp
new file mode 100644
index 000000000..fc372232f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBEndpoint.cpp
@@ -0,0 +1,162 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "dbg.h"
+#include "USBEndpoint.h"
+
+void USBEndpoint::init(HCED * hced_, ENDPOINT_TYPE type_, ENDPOINT_DIRECTION dir_, uint32_t size, uint8_t ep_number, HCTD* td_list_[2])
+{
+ hced = hced_;
+ type = type_;
+ dir = dir_;
+ setup = (type == CONTROL_ENDPOINT) ? true : false;
+
+ //TDs have been allocated by the host
+ memcpy((HCTD**)td_list, td_list_, sizeof(HCTD*)*2); //TODO: Maybe should add a param for td_list size... at least a define
+ memset(td_list_[0], 0, sizeof(HCTD));
+ memset(td_list_[1], 0, sizeof(HCTD));
+
+ td_list[0]->ep = this;
+ td_list[1]->ep = this;
+
+ hced->control = 0;
+ //Empty queue
+ hced->tailTD = td_list[0];
+ hced->headTD = td_list[0];
+ hced->nextED = 0;
+
+ address = (ep_number & 0x7F) | ((dir - 1) << 7);
+
+ hced->control = ((ep_number & 0x7F) << 7) // Endpoint address
+ | (type != CONTROL_ENDPOINT ? ( dir << 11) : 0 ) // direction : Out = 1, 2 = In
+ | ((size & 0x3ff) << 16); // MaxPkt Size
+
+ transfer_len = 0;
+ transferred = 0;
+ buf_start = 0;
+ nextEp = NULL;
+
+ td_current = td_list[0];
+ td_next = td_list[1];
+
+ intf_nb = 0;
+
+ state = USB_TYPE_IDLE;
+}
+
+void USBEndpoint::setSize(uint32_t size)
+{
+ hced->control &= ~(0x3ff << 16);
+ hced->control |= (size << 16);
+}
+
+
+void USBEndpoint::setDeviceAddress(uint8_t addr)
+{
+ hced->control &= ~(0x7f);
+ hced->control |= (addr & 0x7F);
+}
+
+void USBEndpoint::setSpeed(uint8_t speed)
+{
+ hced->control &= ~(1 << 13);
+ hced->control |= (speed << 13);
+}
+
+//Only for control Eps
+void USBEndpoint::setNextToken(uint32_t token)
+{
+ switch (token) {
+ case TD_SETUP:
+ dir = OUT;
+ setup = true;
+ break;
+ case TD_IN:
+ dir = IN;
+ setup = false;
+ break;
+ case TD_OUT:
+ dir = OUT;
+ setup = false;
+ break;
+ }
+}
+
+struct {
+ USB_TYPE type;
+ const char * str;
+} static type_string[] = {
+/*0*/ {USB_TYPE_OK, "USB_TYPE_OK"},
+ {USB_TYPE_CRC_ERROR, "USB_TYPE_CRC_ERROR"},
+ {USB_TYPE_BIT_STUFFING_ERROR, "USB_TYPE_BIT_STUFFING_ERROR"},
+ {USB_TYPE_DATA_TOGGLE_MISMATCH_ERROR, "USB_TYPE_DATA_TOGGLE_MISMATCH_ERROR"},
+ {USB_TYPE_STALL_ERROR, "USB_TYPE_STALL_ERROR"},
+/*5*/ {USB_TYPE_DEVICE_NOT_RESPONDING_ERROR, "USB_TYPE_DEVICE_NOT_RESPONDING_ERROR"},
+ {USB_TYPE_PID_CHECK_FAILURE_ERROR, "USB_TYPE_PID_CHECK_FAILURE_ERROR"},
+ {USB_TYPE_UNEXPECTED_PID_ERROR, "USB_TYPE_UNEXPECTED_PID_ERROR"},
+ {USB_TYPE_DATA_OVERRUN_ERROR, "USB_TYPE_DATA_OVERRUN_ERROR"},
+ {USB_TYPE_DATA_UNDERRUN_ERROR, "USB_TYPE_DATA_UNDERRUN_ERROR"},
+/*10*/ {USB_TYPE_ERROR, "USB_TYPE_ERROR"},
+ {USB_TYPE_ERROR, "USB_TYPE_ERROR"},
+ {USB_TYPE_BUFFER_OVERRUN_ERROR, "USB_TYPE_BUFFER_OVERRUN_ERROR"},
+ {USB_TYPE_BUFFER_UNDERRUN_ERROR, "USB_TYPE_BUFFER_UNDERRUN_ERROR"},
+ {USB_TYPE_DISCONNECTED, "USB_TYPE_DISCONNECTED"},
+/*15*/ {USB_TYPE_FREE, "USB_TYPE_FREE"},
+ {USB_TYPE_IDLE, "USB_TYPE_IDLE"},
+ {USB_TYPE_PROCESSING, "USB_TYPE_PROCESSING"},
+ {USB_TYPE_ERROR, "USB_TYPE_ERROR"}
+};
+
+void USBEndpoint::setState(uint8_t st) {
+ if (st > 18)
+ return;
+ state = type_string[st].type;
+}
+
+
+const char * USBEndpoint::getStateString() {
+ return type_string[state].str;
+}
+
+void USBEndpoint::queueTransfer()
+{
+ transfer_len = (uint32_t)td_current->bufEnd - (uint32_t)td_current->currBufPtr + 1;
+ transferred = transfer_len;
+ buf_start = (uint8_t *)td_current->currBufPtr;
+
+ //Now add this free TD at this end of the queue
+ state = USB_TYPE_PROCESSING;
+ td_current->nextTD = td_next;
+ hced->tailTD = td_next;
+}
+
+void USBEndpoint::unqueueTransfer(volatile HCTD * td)
+{
+ td->control=0;
+ td->currBufPtr=0;
+ td->bufEnd=0;
+ td->nextTD=0;
+ hced->headTD = (HCTD *)((uint32_t)hced->tailTD | ((uint32_t)hced->headTD & 0x2)); //Carry bit
+ td_current = td_next;
+ td_next = td;
+}
+
+void USBEndpoint::queueEndpoint(USBEndpoint * ed)
+{
+ nextEp = ed;
+ hced->nextED = (ed == NULL) ? 0 : ed->getHCED();
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBEndpoint.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBEndpoint.h
new file mode 100644
index 000000000..2ec90d729
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBEndpoint.h
@@ -0,0 +1,171 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBENDPOINT_H
+#define USBENDPOINT_H
+
+#include "FunctionPointer.h"
+#include "USBHostTypes.h"
+#include "rtos.h"
+
+class USBDeviceConnected;
+
+/**
+* USBEndpoint class
+*/
+class USBEndpoint
+{
+public:
+ /**
+ * Constructor
+ */
+ USBEndpoint() {
+ state = USB_TYPE_FREE;
+ nextEp = NULL;
+ };
+
+ /**
+ * Initialize an endpoint
+ *
+ * @param hced hced associated to the endpoint
+ * @param type endpoint type
+ * @param dir endpoint direction
+ * @param size endpoint size
+ * @param ep_number endpoint number
+ * @param td_list array of two allocated transfer descriptors
+ */
+ void init(HCED * hced, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint32_t size, uint8_t ep_number, HCTD* td_list[2]);
+
+ /**
+ * Set next token. Warning: only useful for the control endpoint
+ *
+ * @param token IN, OUT or SETUP token
+ */
+ void setNextToken(uint32_t token);
+
+ /**
+ * Queue an endpoint
+ *
+ * @param endpoint endpoint which will be queued in the linked list
+ */
+ void queueEndpoint(USBEndpoint * endpoint);
+
+
+ /**
+ * Queue a transfer on the endpoint
+ */
+ void queueTransfer();
+
+ /**
+ * Unqueue a transfer from the endpoint
+ *
+ * @param td hctd which will be unqueued
+ */
+ void unqueueTransfer(volatile HCTD * td);
+
+ /**
+ * Attach a member function to call when a transfer is finished
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ */
+ template<typename T>
+ inline void attach(T* tptr, void (T::*mptr)(void)) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ rx.attach(tptr, mptr);
+ }
+ }
+
+ /**
+ * Attach a callback called when a transfer is finished
+ *
+ * @param fptr function pointer
+ */
+ inline void attach(void (*fptr)(void)) {
+ if(fptr != NULL) {
+ rx.attach(fptr);
+ }
+ }
+
+ /**
+ * Call the handler associted to the end of a transfer
+ */
+ inline void call() {
+ rx.call();
+ };
+
+
+ // setters
+ inline void setState(USB_TYPE st) { state = st; }
+ void setState(uint8_t st);
+ void setDeviceAddress(uint8_t addr);
+ inline void setLengthTransferred(int len) { transferred = len; };
+ void setSpeed(uint8_t speed);
+ void setSize(uint32_t size);
+ inline void setDir(ENDPOINT_DIRECTION d) { dir = d; }
+ inline void setIntfNb(uint8_t intf_nb_) { intf_nb = intf_nb_; };
+
+ // getters
+ const char * getStateString();
+ inline USB_TYPE getState() { return state; }
+ inline ENDPOINT_TYPE getType() { return type; };
+ inline uint8_t getDeviceAddress() { return hced->control & 0x7f; };
+ inline int getLengthTransferred() { return transferred; }
+ inline uint8_t * getBufStart() { return buf_start; }
+ inline uint8_t getAddress(){ return address; };
+ inline uint32_t getSize() { return (hced->control >> 16) & 0x3ff; };
+ inline volatile HCTD * getHeadTD() { return (volatile HCTD*) ((uint32_t)hced->headTD & ~0xF); };
+ inline volatile HCTD** getTDList() { return td_list; };
+ inline volatile HCED * getHCED() { return hced; };
+ inline ENDPOINT_DIRECTION getDir() { return dir; }
+ inline volatile HCTD * getProcessedTD() { return td_current; };
+ inline volatile HCTD* getNextTD() { return td_current; };
+ inline bool isSetup() { return setup; }
+ inline USBEndpoint * nextEndpoint() { return (USBEndpoint*)nextEp; };
+ inline uint8_t getIntfNb() { return intf_nb; };
+
+ USBDeviceConnected * dev;
+
+ Queue<uint8_t, 1> ep_queue;
+
+private:
+ ENDPOINT_TYPE type;
+ volatile USB_TYPE state;
+ ENDPOINT_DIRECTION dir;
+ bool setup;
+
+ uint8_t address;
+
+ int transfer_len;
+ int transferred;
+ uint8_t * buf_start;
+
+ FunctionPointer rx;
+
+ USBEndpoint* nextEp;
+
+ // USBEndpoint descriptor
+ volatile HCED * hced;
+
+ volatile HCTD * td_list[2];
+ volatile HCTD * td_current;
+ volatile HCTD * td_next;
+
+ uint8_t intf_nb;
+
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost.h
new file mode 100644
index 000000000..e32969de3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost.h
@@ -0,0 +1,169 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHALHOST_H
+#define USBHALHOST_H
+
+#include "USBHostTypes.h"
+#include "USBHostConf.h"
+
+class USBHostHub;
+
+/**
+* USBHALHost class
+*/
+class USBHALHost {
+protected:
+
+ /**
+ * Constructor
+ * init variables and memory where will be stored HCCA, ED and TD
+ */
+ USBHALHost();
+
+ /**
+ * Initialize host controller. Enable USB interrupts. This part is not in the constructor because,
+ * this function calls a virtual method if a device is already connected
+ */
+ void init();
+
+ /**
+ * reset the root hub
+ */
+ void resetRootHub();
+
+ /**
+ * return the value contained in the control HEAD ED register
+ *
+ * @returns address of the control Head ED
+ */
+ uint32_t controlHeadED();
+
+ /**
+ * return the value contained in the bulk HEAD ED register
+ *
+ * @returns address of the bulk head ED
+ */
+ uint32_t bulkHeadED();
+
+ /**
+ * return the value of the head interrupt ED contained in the HCCA
+ *
+ * @returns address of the head interrupt ED contained in the HCCA
+ */
+ uint32_t interruptHeadED();
+
+ /**
+ * Update the head ED for control transfers
+ */
+ void updateControlHeadED(uint32_t addr);
+
+ /**
+ * Update the head ED for bulk transfers
+ */
+ void updateBulkHeadED(uint32_t addr);
+
+ /**
+ * Update the head ED for interrupt transfers
+ */
+ void updateInterruptHeadED(uint32_t addr);
+
+ /**
+ * Enable List for the specified endpoint type
+ *
+ * @param type enable the list of ENDPOINT_TYPE type
+ */
+ void enableList(ENDPOINT_TYPE type);
+
+ /**
+ * Disable List for the specified endpoint type
+ *
+ * @param type disable the list of ENDPOINT_TYPE type
+ */
+ bool disableList(ENDPOINT_TYPE type);
+
+ /**
+ * Virtual method called when a device has been connected
+ *
+ * @param hub hub number of the device
+ * @param port port number of the device
+ * @param lowSpeed 1 if low speed, 0 otherwise
+ * @param hub_parent reference to the hub where the device is connected (NULL if the hub parent is the root hub)
+ */
+ virtual void deviceConnected(int hub, int port, bool lowSpeed, USBHostHub * hub_parent = NULL) = 0;
+
+ /**
+ * Virtual method called when a device has been disconnected
+ *
+ * @param hub hub number of the device
+ * @param port port number of the device
+ * @param hub_parent reference to the hub where the device is connected (NULL if the hub parent is the root hub)
+ * @param addr list of the TDs which have been completed to dequeue freed TDs
+ */
+ virtual void deviceDisconnected(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr) = 0;
+
+ /**
+ * Virtual method called when a transfer has been completed
+ *
+ * @param addr list of the TDs which have been completed
+ */
+ virtual void transferCompleted(volatile uint32_t addr) = 0;
+
+ /**
+ * Find a memory section for a new ED
+ *
+ * @returns the address of the new ED
+ */
+ volatile uint8_t * getED();
+
+ /**
+ * Find a memory section for a new TD
+ *
+ * @returns the address of the new TD
+ */
+ volatile uint8_t * getTD();
+
+ /**
+ * Release a previous memory section reserved for an ED
+ *
+ * @param ed address of the ED
+ */
+ void freeED(volatile uint8_t * ed);
+
+ /**
+ * Release a previous memory section reserved for an TD
+ *
+ * @param td address of the TD
+ */
+ void freeTD(volatile uint8_t * td);
+
+private:
+ static void _usbisr(void);
+ void UsbIrqhandler();
+
+ void memInit();
+
+ HCCA volatile * usb_hcca; //256 bytes aligned
+ uint8_t volatile * usb_edBuf; //4 bytes aligned
+ uint8_t volatile * usb_tdBuf; //4 bytes aligned
+
+ static USBHALHost * instHost;
+
+ bool volatile edBufAlloc[MAX_ENDPOINT];
+ bool volatile tdBufAlloc[MAX_TD];
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost_LPC17.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost_LPC17.cpp
new file mode 100644
index 000000000..c1eadf389
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost_LPC17.cpp
@@ -0,0 +1,325 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(TARGET_LPC1768)
+
+#include "mbed.h"
+#include "USBHALHost.h"
+#include "dbg.h"
+
+// bits of the USB/OTG clock control register
+#define HOST_CLK_EN (1<<0)
+#define DEV_CLK_EN (1<<1)
+#define PORTSEL_CLK_EN (1<<3)
+#define AHB_CLK_EN (1<<4)
+
+// bits of the USB/OTG clock status register
+#define HOST_CLK_ON (1<<0)
+#define DEV_CLK_ON (1<<1)
+#define PORTSEL_CLK_ON (1<<3)
+#define AHB_CLK_ON (1<<4)
+
+// we need host clock, OTG/portsel clock and AHB clock
+#define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
+
+#define HCCA_SIZE sizeof(HCCA)
+#define ED_SIZE sizeof(HCED)
+#define TD_SIZE sizeof(HCTD)
+
+#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
+
+static volatile uint8_t usb_buf[TOTAL_SIZE] __attribute((section("AHBSRAM1"),aligned(256))); //256 bytes aligned!
+
+USBHALHost * USBHALHost::instHost;
+
+USBHALHost::USBHALHost() {
+ instHost = this;
+ memInit();
+ memset((void*)usb_hcca, 0, HCCA_SIZE);
+ for (int i = 0; i < MAX_ENDPOINT; i++) {
+ edBufAlloc[i] = false;
+ }
+ for (int i = 0; i < MAX_TD; i++) {
+ tdBufAlloc[i] = false;
+ }
+}
+
+void USBHALHost::init() {
+ NVIC_DisableIRQ(USB_IRQn);
+
+ //Cut power
+ LPC_SC->PCONP &= ~(1UL<<31);
+ wait_ms(100);
+
+ // turn on power for USB
+ LPC_SC->PCONP |= (1UL<<31);
+
+ // Enable USB host clock, port selection and AHB clock
+ LPC_USB->USBClkCtrl |= CLOCK_MASK;
+
+ // Wait for clocks to become available
+ while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK);
+
+ // it seems the bits[0:1] mean the following
+ // 0: U1=device, U2=host
+ // 1: U1=host, U2=host
+ // 2: reserved
+ // 3: U1=host, U2=device
+ // NB: this register is only available if OTG clock (aka "port select") is enabled!!
+ // since we don't care about port 2, set just bit 0 to 1 (U1=host)
+ LPC_USB->OTGStCtrl |= 1;
+
+ // now that we've configured the ports, we can turn off the portsel clock
+ LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
+
+ // configure USB D+/D- pins
+ // P0[29] = USB_D+, 01
+ // P0[30] = USB_D-, 01
+ LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
+ LPC_PINCON->PINSEL1 |= ((1<<26) | (1<<28));
+
+ LPC_USB->HcControl = 0; // HARDWARE RESET
+ LPC_USB->HcControlHeadED = 0; // Initialize Control list head to Zero
+ LPC_USB->HcBulkHeadED = 0; // Initialize Bulk list head to Zero
+
+ // Wait 100 ms before apply reset
+ wait_ms(100);
+
+ // software reset
+ LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
+
+ // Write Fm Interval and Largest Data Packet Counter
+ LPC_USB->HcFmInterval = DEFAULT_FMINTERVAL;
+ LPC_USB->HcPeriodicStart = FI * 90 / 100;
+
+ // Put HC in operational state
+ LPC_USB->HcControl = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
+ // Set Global Power
+ LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC;
+
+ LPC_USB->HcHCCA = (uint32_t)(usb_hcca);
+
+ // Clear Interrrupt Status
+ LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus;
+
+ LPC_USB->HcInterruptEnable = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
+
+ // Enable the USB Interrupt
+ NVIC_SetVector(USB_IRQn, (uint32_t)(_usbisr));
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+
+ NVIC_EnableIRQ(USB_IRQn);
+
+ // Check for any connected devices
+ if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
+ //Device connected
+ wait_ms(150);
+ USB_DBG("Device connected (%08x)\n\r", LPC_USB->HcRhPortStatus1);
+ deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
+ }
+}
+
+uint32_t USBHALHost::controlHeadED() {
+ return LPC_USB->HcControlHeadED;
+}
+
+uint32_t USBHALHost::bulkHeadED() {
+ return LPC_USB->HcBulkHeadED;
+}
+
+uint32_t USBHALHost::interruptHeadED() {
+ return usb_hcca->IntTable[0];
+}
+
+void USBHALHost::updateBulkHeadED(uint32_t addr) {
+ LPC_USB->HcBulkHeadED = addr;
+}
+
+
+void USBHALHost::updateControlHeadED(uint32_t addr) {
+ LPC_USB->HcControlHeadED = addr;
+}
+
+void USBHALHost::updateInterruptHeadED(uint32_t addr) {
+ usb_hcca->IntTable[0] = addr;
+}
+
+
+void USBHALHost::enableList(ENDPOINT_TYPE type) {
+ switch(type) {
+ case CONTROL_ENDPOINT:
+ LPC_USB->HcCommandStatus = OR_CMD_STATUS_CLF;
+ LPC_USB->HcControl |= OR_CONTROL_CLE;
+ break;
+ case ISOCHRONOUS_ENDPOINT:
+ break;
+ case BULK_ENDPOINT:
+ LPC_USB->HcCommandStatus = OR_CMD_STATUS_BLF;
+ LPC_USB->HcControl |= OR_CONTROL_BLE;
+ break;
+ case INTERRUPT_ENDPOINT:
+ LPC_USB->HcControl |= OR_CONTROL_PLE;
+ break;
+ }
+}
+
+
+bool USBHALHost::disableList(ENDPOINT_TYPE type) {
+ switch(type) {
+ case CONTROL_ENDPOINT:
+ if(LPC_USB->HcControl & OR_CONTROL_CLE) {
+ LPC_USB->HcControl &= ~OR_CONTROL_CLE;
+ return true;
+ }
+ return false;
+ case ISOCHRONOUS_ENDPOINT:
+ return false;
+ case BULK_ENDPOINT:
+ if(LPC_USB->HcControl & OR_CONTROL_BLE){
+ LPC_USB->HcControl &= ~OR_CONTROL_BLE;
+ return true;
+ }
+ return false;
+ case INTERRUPT_ENDPOINT:
+ if(LPC_USB->HcControl & OR_CONTROL_PLE) {
+ LPC_USB->HcControl &= ~OR_CONTROL_PLE;
+ return true;
+ }
+ return false;
+ }
+ return false;
+}
+
+
+void USBHALHost::memInit() {
+ usb_hcca = (volatile HCCA *)usb_buf;
+ usb_edBuf = usb_buf + HCCA_SIZE;
+ usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
+}
+
+volatile uint8_t * USBHALHost::getED() {
+ for (int i = 0; i < MAX_ENDPOINT; i++) {
+ if ( !edBufAlloc[i] ) {
+ edBufAlloc[i] = true;
+ return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
+ }
+ }
+ perror("Could not allocate ED\r\n");
+ return NULL; //Could not alloc ED
+}
+
+volatile uint8_t * USBHALHost::getTD() {
+ int i;
+ for (i = 0; i < MAX_TD; i++) {
+ if ( !tdBufAlloc[i] ) {
+ tdBufAlloc[i] = true;
+ return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
+ }
+ }
+ perror("Could not allocate TD\r\n");
+ return NULL; //Could not alloc TD
+}
+
+
+void USBHALHost::freeED(volatile uint8_t * ed) {
+ int i;
+ i = (ed - usb_edBuf) / ED_SIZE;
+ edBufAlloc[i] = false;
+}
+
+void USBHALHost::freeTD(volatile uint8_t * td) {
+ int i;
+ i = (td - usb_tdBuf) / TD_SIZE;
+ tdBufAlloc[i] = false;
+}
+
+
+void USBHALHost::resetRootHub() {
+ // Initiate port reset
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS;
+
+ while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS);
+
+ // ...and clear port reset signal
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+}
+
+
+void USBHALHost::_usbisr(void) {
+ if (instHost) {
+ instHost->UsbIrqhandler();
+ }
+}
+
+void USBHALHost::UsbIrqhandler() {
+ if( LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable ) //Is there something to actually process?
+ {
+
+ uint32_t int_status = LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable;
+
+ // Root hub status change interrupt
+ if (int_status & OR_INTR_STATUS_RHSC) {
+ if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
+ if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
+ // When DRWE is on, Connect Status Change
+ // means a remote wakeup event.
+ } else {
+
+ //Root device connected
+ if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
+
+ // wait 150ms to avoid bounce
+ wait_ms(150);
+
+ //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
+ deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
+ }
+
+ //Root device disconnected
+ else {
+
+ if (!(int_status & OR_INTR_STATUS_WDH)) {
+ usb_hcca->DoneHead = 0;
+ }
+
+ // wait 200ms to avoid bounce
+ wait_ms(200);
+
+ deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
+
+ if (int_status & OR_INTR_STATUS_WDH) {
+ usb_hcca->DoneHead = 0;
+ LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
+ }
+ }
+ }
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
+ }
+ if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
+ LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
+ }
+ LPC_USB->HcInterruptStatus = OR_INTR_STATUS_RHSC;
+ }
+
+ // Writeback Done Head interrupt
+ if (int_status & OR_INTR_STATUS_WDH) {
+ transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
+ LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
+ }
+ }
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp
new file mode 100644
index 000000000..38213c76a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost_RZ_A1.cpp
@@ -0,0 +1,292 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if defined(TARGET_RZ_A1H)
+
+#include "mbed.h"
+#include "USBHALHost.h"
+#include "dbg.h"
+
+#include "ohci_wrapp_RZ_A1.h"
+
+
+#define HCCA_SIZE sizeof(HCCA)
+#define ED_SIZE sizeof(HCED)
+#define TD_SIZE sizeof(HCTD)
+
+#define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
+#define ALIGNE_MSK (0x0000000F)
+
+static volatile uint8_t usb_buf[TOTAL_SIZE + ALIGNE_MSK]; //16 bytes aligned!
+
+USBHALHost * USBHALHost::instHost;
+
+USBHALHost::USBHALHost() {
+ instHost = this;
+ memInit();
+ memset((void*)usb_hcca, 0, HCCA_SIZE);
+ for (int i = 0; i < MAX_ENDPOINT; i++) {
+ edBufAlloc[i] = false;
+ }
+ for (int i = 0; i < MAX_TD; i++) {
+ tdBufAlloc[i] = false;
+ }
+}
+
+void USBHALHost::init() {
+ ohciwrapp_init(&_usbisr);
+
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, 1); // HARDWARE RESET
+ ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, 0); // Initialize Control list head to Zero
+ ohciwrapp_reg_w(OHCI_REG_BULKHEADED, 0); // Initialize Bulk list head to Zero
+
+ // Wait 100 ms before apply reset
+ wait_ms(100);
+
+ // software reset
+ ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_HCR);
+
+ // Write Fm Interval and Largest Data Packet Counter
+ ohciwrapp_reg_w(OHCI_REG_FMINTERVAL, DEFAULT_FMINTERVAL);
+ ohciwrapp_reg_w(OHCI_REG_PERIODICSTART, FI * 90 / 100);
+
+ // Put HC in operational state
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, (ohciwrapp_reg_r(OHCI_REG_CONTROL) & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER);
+ // Set Global Power
+ ohciwrapp_reg_w(OHCI_REG_RHSTATUS, OR_RH_STATUS_LPSC);
+
+ ohciwrapp_reg_w(OHCI_REG_HCCA, (uint32_t)(usb_hcca));
+
+ // Clear Interrrupt Status
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS));
+
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTENABLE, OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC);
+
+ // Enable the USB Interrupt
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+
+ // Check for any connected devices
+ if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) {
+ //Device connected
+ wait_ms(150);
+ USB_DBG("Device connected (%08x)\n\r", ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1));
+ deviceConnected(0, 1, ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA);
+ }
+}
+
+uint32_t USBHALHost::controlHeadED() {
+ return ohciwrapp_reg_r(OHCI_REG_CONTROLHEADED);
+}
+
+uint32_t USBHALHost::bulkHeadED() {
+ return ohciwrapp_reg_r(OHCI_REG_BULKHEADED);
+}
+
+uint32_t USBHALHost::interruptHeadED() {
+ return usb_hcca->IntTable[0];
+}
+
+void USBHALHost::updateBulkHeadED(uint32_t addr) {
+ ohciwrapp_reg_w(OHCI_REG_BULKHEADED, addr);
+}
+
+
+void USBHALHost::updateControlHeadED(uint32_t addr) {
+ ohciwrapp_reg_w(OHCI_REG_CONTROLHEADED, addr);
+}
+
+void USBHALHost::updateInterruptHeadED(uint32_t addr) {
+ usb_hcca->IntTable[0] = addr;
+}
+
+
+void USBHALHost::enableList(ENDPOINT_TYPE type) {
+ uint32_t wk_data;
+
+ switch(type) {
+ case CONTROL_ENDPOINT:
+ ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_CLF);
+ wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_CLE);
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ break;
+ case ISOCHRONOUS_ENDPOINT:
+ break;
+ case BULK_ENDPOINT:
+ ohciwrapp_reg_w(OHCI_REG_COMMANDSTATUS, OR_CMD_STATUS_BLF);
+ wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_BLE);
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ break;
+ case INTERRUPT_ENDPOINT:
+ wk_data = (ohciwrapp_reg_r(OHCI_REG_CONTROL) | OR_CONTROL_PLE);
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ break;
+ }
+}
+
+
+bool USBHALHost::disableList(ENDPOINT_TYPE type) {
+ uint32_t wk_data;
+
+ switch(type) {
+ case CONTROL_ENDPOINT:
+ wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+ if(wk_data & OR_CONTROL_CLE) {
+ wk_data &= ~OR_CONTROL_CLE;
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ return true;
+ }
+ return false;
+ case ISOCHRONOUS_ENDPOINT:
+ return false;
+ case BULK_ENDPOINT:
+ wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+ if(wk_data & OR_CONTROL_BLE) {
+ wk_data &= ~OR_CONTROL_BLE;
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ return true;
+ }
+ return false;
+ case INTERRUPT_ENDPOINT:
+ wk_data = ohciwrapp_reg_r(OHCI_REG_CONTROL);
+ if(wk_data & OR_CONTROL_PLE) {
+ wk_data &= ~OR_CONTROL_PLE;
+ ohciwrapp_reg_w(OHCI_REG_CONTROL, wk_data);
+ return true;
+ }
+ return false;
+ }
+ return false;
+}
+
+
+void USBHALHost::memInit() {
+ volatile uint8_t *p_wk_buf = (uint8_t *)(((uint32_t)usb_buf + ALIGNE_MSK) & ~ALIGNE_MSK);
+
+ usb_hcca = (volatile HCCA *)p_wk_buf;
+ usb_edBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE);
+ usb_tdBuf = (volatile uint8_t *)(p_wk_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE));
+}
+
+volatile uint8_t * USBHALHost::getED() {
+ for (int i = 0; i < MAX_ENDPOINT; i++) {
+ if ( !edBufAlloc[i] ) {
+ edBufAlloc[i] = true;
+ return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
+ }
+ }
+ perror("Could not allocate ED\r\n");
+ return NULL; //Could not alloc ED
+}
+
+volatile uint8_t * USBHALHost::getTD() {
+ int i;
+ for (i = 0; i < MAX_TD; i++) {
+ if ( !tdBufAlloc[i] ) {
+ tdBufAlloc[i] = true;
+ return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
+ }
+ }
+ perror("Could not allocate TD\r\n");
+ return NULL; //Could not alloc TD
+}
+
+
+void USBHALHost::freeED(volatile uint8_t * ed) {
+ int i;
+ i = (ed - usb_edBuf) / ED_SIZE;
+ edBufAlloc[i] = false;
+}
+
+void USBHALHost::freeTD(volatile uint8_t * td) {
+ int i;
+ i = (td - usb_tdBuf) / TD_SIZE;
+ tdBufAlloc[i] = false;
+}
+
+
+void USBHALHost::resetRootHub() {
+ // Initiate port reset
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRS);
+
+ while (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRS);
+
+ // ...and clear port reset signal
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+}
+
+
+void USBHALHost::_usbisr(void) {
+ if (instHost) {
+ instHost->UsbIrqhandler();
+ }
+}
+
+void USBHALHost::UsbIrqhandler() {
+ uint32_t int_status = ohciwrapp_reg_r(OHCI_REG_INTERRUPTSTATUS) & ohciwrapp_reg_r(OHCI_REG_INTERRUPTENABLE);
+ uint32_t data;
+
+ if (int_status != 0) { //Is there something to actually process?
+ // Root hub status change interrupt
+ if (int_status & OR_INTR_STATUS_RHSC) {
+ if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CSC) {
+ if (ohciwrapp_reg_r(OHCI_REG_RHSTATUS) & OR_RH_STATUS_DRWE) {
+ // When DRWE is on, Connect Status Change
+ // means a remote wakeup event.
+ } else {
+
+ //Root device connected
+ if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_CCS) {
+
+ // wait 150ms to avoid bounce
+ wait_ms(150);
+
+ //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
+ data = ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_LSDA;
+ deviceConnected(0, 1, data);
+ }
+
+ //Root device disconnected
+ else {
+
+ if (!(int_status & OR_INTR_STATUS_WDH)) {
+ usb_hcca->DoneHead = 0;
+ }
+
+ deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
+
+ if (int_status & OR_INTR_STATUS_WDH) {
+ usb_hcca->DoneHead = 0;
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH);
+ }
+ }
+ }
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_CSC);
+ }
+ if (ohciwrapp_reg_r(OHCI_REG_RHPORTSTATUS1) & OR_RH_PORT_PRSC) {
+ ohciwrapp_reg_w(OHCI_REG_RHPORTSTATUS1, OR_RH_PORT_PRSC);
+ }
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_RHSC);
+ }
+
+ // Writeback Done Head interrupt
+ if (int_status & OR_INTR_STATUS_WDH) {
+ transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
+ ohciwrapp_reg_w(OHCI_REG_INTERRUPTSTATUS, OR_INTR_STATUS_WDH);
+ }
+ }
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHost.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHost.cpp
new file mode 100644
index 000000000..d05486db9
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHost.cpp
@@ -0,0 +1,1160 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#include "USBHost.h"
+#include "USBHostHub.h"
+
+USBHost * USBHost::instHost = NULL;
+
+#define DEVICE_CONNECTED_EVENT (1 << 0)
+#define DEVICE_DISCONNECTED_EVENT (1 << 1)
+#define TD_PROCESSED_EVENT (1 << 2)
+
+#define MAX_TRY_ENUMERATE_HUB 3
+
+#define MIN(a, b) ((a > b) ? b : a)
+
+/**
+* How interrupts are processed:
+* - new device connected:
+* - a message is queued in queue_usb_event with the id DEVICE_CONNECTED_EVENT
+* - when the usb_thread receives the event, it:
+* - resets the device
+* - reads the device descriptor
+* - sets the address of the device
+* - if it is a hub, enumerates it
+* - device disconnected:
+* - a message is queued in queue_usb_event with the id DEVICE_DISCONNECTED_EVENT
+* - when the usb_thread receives the event, it:
+* - free the device and all its children (hub)
+* - td processed
+* - a message is queued in queue_usb_event with the id TD_PROCESSED_EVENT
+* - when the usb_thread receives the event, it:
+* - call the callback attached to the endpoint where the td is attached
+*/
+void USBHost::usb_process() {
+
+ bool controlListState;
+ bool bulkListState;
+ bool interruptListState;
+ USBEndpoint * ep;
+ uint8_t i, j, res, timeout_set_addr = 10;
+ uint8_t buf[8];
+ bool too_many_hub;
+ int idx;
+
+#if DEBUG_TRANSFER
+ uint8_t * buf_transfer;
+#endif
+
+#if MAX_HUB_NB
+ uint8_t k;
+#endif
+
+ while(1) {
+ osEvent evt = mail_usb_event.get();
+
+ if (evt.status == osEventMail) {
+
+ message_t * usb_msg = (message_t*)evt.value.p;
+
+ switch (usb_msg->event_id) {
+
+ // a new device has been connected
+ case DEVICE_CONNECTED_EVENT:
+ too_many_hub = false;
+ buf[4] = 0;
+
+ do
+ {
+ Lock lock(this);
+
+ for (i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ if (!deviceInUse[i]) {
+ USB_DBG_EVENT("new device connected: %p\r\n", &devices[i]);
+ devices[i].init(usb_msg->hub, usb_msg->port, usb_msg->lowSpeed);
+ deviceReset[i] = false;
+ deviceInited[i] = true;
+ break;
+ }
+ }
+
+ if (i == MAX_DEVICE_CONNECTED) {
+ USB_ERR("Too many device connected!!\r\n");
+ continue;
+ }
+
+ if (!controlEndpointAllocated) {
+ control = newEndpoint(CONTROL_ENDPOINT, OUT, 0x08, 0x00);
+ addEndpoint(NULL, 0, (USBEndpoint*)control);
+ controlEndpointAllocated = true;
+ }
+
+ #if MAX_HUB_NB
+ if (usb_msg->hub_parent)
+ devices[i].setHubParent((USBHostHub *)(usb_msg->hub_parent));
+ #endif
+
+ for (j = 0; j < timeout_set_addr; j++) {
+
+ resetDevice(&devices[i]);
+
+ // set size of control endpoint
+ devices[i].setSizeControlEndpoint(8);
+
+ devices[i].activeAddress(false);
+
+ // get first 8 bit of device descriptor
+ // and check if we deal with a hub
+ USB_DBG("usb_thread read device descriptor on dev: %p\r\n", &devices[i]);
+ res = getDeviceDescriptor(&devices[i], buf, 8);
+
+ if (res != USB_TYPE_OK) {
+ USB_ERR("usb_thread could not read dev descr");
+ continue;
+ }
+
+ // set size of control endpoint
+ devices[i].setSizeControlEndpoint(buf[7]);
+
+ // second step: set an address to the device
+ res = setAddress(&devices[i], devices[i].getAddress());
+
+ if (res != USB_TYPE_OK) {
+ USB_ERR("SET ADDR FAILED");
+ continue;
+ }
+ devices[i].activeAddress(true);
+ USB_DBG("Address of %p: %d", &devices[i], devices[i].getAddress());
+
+ // try to read again the device descriptor to check if the device
+ // answers to its new address
+ res = getDeviceDescriptor(&devices[i], buf, 8);
+
+ if (res == USB_TYPE_OK) {
+ break;
+ }
+
+ Thread::wait(100);
+ }
+
+ USB_INFO("New device connected: %p [hub: %d - port: %d]", &devices[i], usb_msg->hub, usb_msg->port);
+
+ #if MAX_HUB_NB
+ if (buf[4] == HUB_CLASS) {
+ for (k = 0; k < MAX_HUB_NB; k++) {
+ if (hub_in_use[k] == false) {
+ for (uint8_t j = 0; j < MAX_TRY_ENUMERATE_HUB; j++) {
+ if (hubs[k].connect(&devices[i])) {
+ devices[i].hub = &hubs[k];
+ hub_in_use[k] = true;
+ break;
+ }
+ }
+ if (hub_in_use[k] == true)
+ break;
+ }
+ }
+
+ if (k == MAX_HUB_NB) {
+ USB_ERR("Too many hubs connected!!\r\n");
+ too_many_hub = true;
+ }
+ }
+
+ if (usb_msg->hub_parent)
+ ((USBHostHub *)(usb_msg->hub_parent))->deviceConnected(&devices[i]);
+ #endif
+
+ if ((i < MAX_DEVICE_CONNECTED) && !too_many_hub) {
+ deviceInUse[i] = true;
+ }
+
+ } while(0);
+
+ break;
+
+ // a device has been disconnected
+ case DEVICE_DISCONNECTED_EVENT:
+
+ do
+ {
+ Lock lock(this);
+
+ controlListState = disableList(CONTROL_ENDPOINT);
+ bulkListState = disableList(BULK_ENDPOINT);
+ interruptListState = disableList(INTERRUPT_ENDPOINT);
+
+ idx = findDevice(usb_msg->hub, usb_msg->port, (USBHostHub *)(usb_msg->hub_parent));
+ if (idx != -1) {
+ freeDevice((USBDeviceConnected*)&devices[idx]);
+ }
+
+ if (controlListState) enableList(CONTROL_ENDPOINT);
+ if (bulkListState) enableList(BULK_ENDPOINT);
+ if (interruptListState) enableList(INTERRUPT_ENDPOINT);
+
+ } while(0);
+
+ break;
+
+ // a td has been processed
+ // call callback on the ed associated to the td
+ // we are not in ISR -> users can use printf in their callback method
+ case TD_PROCESSED_EVENT:
+ ep = (USBEndpoint *) ((HCTD *)usb_msg->td_addr)->ep;
+ if (usb_msg->td_state == USB_TYPE_IDLE) {
+ USB_DBG_EVENT("call callback on td %p [ep: %p state: %s - dev: %p - %s]", usb_msg->td_addr, ep, ep->getStateString(), ep->dev, ep->dev->getName(ep->getIntfNb()));
+
+#if DEBUG_TRANSFER
+ if (ep->getDir() == IN) {
+ buf_transfer = ep->getBufStart();
+ printf("READ SUCCESS [%d bytes transferred - td: 0x%08X] on ep: [%p - addr: %02X]: ", ep->getLengthTransferred(), usb_msg->td_addr, ep, ep->getAddress());
+ for (int i = 0; i < ep->getLengthTransferred(); i++)
+ printf("%02X ", buf_transfer[i]);
+ printf("\r\n\r\n");
+ }
+#endif
+ ep->call();
+ } else {
+ idx = findDevice(ep->dev);
+ if (idx != -1) {
+ if (deviceInUse[idx]) {
+ USB_WARN("td %p processed but not in idle state: %s [ep: %p - dev: %p - %s]", usb_msg->td_addr, ep->getStateString(), ep, ep->dev, ep->dev->getName(ep->getIntfNb()));
+ ep->setState(USB_TYPE_IDLE);
+ }
+ }
+ }
+ break;
+ }
+
+ mail_usb_event.free(usb_msg);
+ }
+ }
+}
+
+/* static */void USBHost::usb_process_static(void const * arg) {
+ ((USBHost *)arg)->usb_process();
+}
+
+USBHost::USBHost() : usbThread(USBHost::usb_process_static, (void *)this, osPriorityNormal, USB_THREAD_STACK)
+{
+ headControlEndpoint = NULL;
+ headBulkEndpoint = NULL;
+ headInterruptEndpoint = NULL;
+ tailControlEndpoint = NULL;
+ tailBulkEndpoint = NULL;
+ tailInterruptEndpoint = NULL;
+
+ lenReportDescr = 0;
+
+ controlEndpointAllocated = false;
+
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ deviceInUse[i] = false;
+ devices[i].setAddress(i + 1);
+ deviceReset[i] = false;
+ deviceInited[i] = false;
+ for (uint8_t j = 0; j < MAX_INTF; j++)
+ deviceAttachedDriver[i][j] = false;
+ }
+
+#if MAX_HUB_NB
+ for (uint8_t i = 0; i < MAX_HUB_NB; i++) {
+ hubs[i].setHost(this);
+ hub_in_use[i] = false;
+ }
+#endif
+}
+
+USBHost::Lock::Lock(USBHost* pHost) : m_pHost(pHost)
+{
+ m_pHost->usb_mutex.lock();
+}
+
+USBHost::Lock::~Lock()
+{
+ m_pHost->usb_mutex.unlock();
+}
+
+void USBHost::transferCompleted(volatile uint32_t addr)
+{
+ uint8_t state;
+
+ if(addr == 0)
+ return;
+
+ volatile HCTD* tdList = NULL;
+
+ //First we must reverse the list order and dequeue each TD
+ do {
+ volatile HCTD* td = (volatile HCTD*)addr;
+ addr = (uint32_t)td->nextTD; //Dequeue from physical list
+ td->nextTD = tdList; //Enqueue into reversed list
+ tdList = td;
+ } while(addr);
+
+ while(tdList != NULL) {
+ volatile HCTD* td = tdList;
+ tdList = (volatile HCTD*)td->nextTD; //Dequeue element now as it could be modified below
+ if (td->ep != NULL) {
+ USBEndpoint * ep = (USBEndpoint *)(td->ep);
+
+ if (((HCTD *)td)->control >> 28) {
+ state = ((HCTD *)td)->control >> 28;
+ } else {
+ if (td->currBufPtr)
+ ep->setLengthTransferred((uint32_t)td->currBufPtr - (uint32_t)ep->getBufStart());
+ state = 16 /*USB_TYPE_IDLE*/;
+ }
+
+ ep->unqueueTransfer(td);
+
+ if (ep->getType() != CONTROL_ENDPOINT) {
+ // callback on the processed td will be called from the usb_thread (not in ISR)
+ message_t * usb_msg = mail_usb_event.alloc();
+ usb_msg->event_id = TD_PROCESSED_EVENT;
+ usb_msg->td_addr = (void *)td;
+ usb_msg->td_state = state;
+ mail_usb_event.put(usb_msg);
+ }
+ ep->setState(state);
+ ep->ep_queue.put((uint8_t*)1);
+ }
+ }
+}
+
+USBHost * USBHost::getHostInst()
+{
+ if (instHost == NULL) {
+ instHost = new USBHost();
+ instHost->init();
+ }
+ return instHost;
+}
+
+
+/*
+ * Called when a device has been connected
+ * Called in ISR!!!! (no printf)
+ */
+/* virtual */ void USBHost::deviceConnected(int hub, int port, bool lowSpeed, USBHostHub * hub_parent)
+{
+ // be sure that the new device connected is not already connected...
+ int idx = findDevice(hub, port, hub_parent);
+ if (idx != -1) {
+ if (deviceInited[idx])
+ return;
+ }
+
+ message_t * usb_msg = mail_usb_event.alloc();
+ usb_msg->event_id = DEVICE_CONNECTED_EVENT;
+ usb_msg->hub = hub;
+ usb_msg->port = port;
+ usb_msg->lowSpeed = lowSpeed;
+ usb_msg->hub_parent = hub_parent;
+ mail_usb_event.put(usb_msg);
+}
+
+/*
+ * Called when a device has been disconnected
+ * Called in ISR!!!! (no printf)
+ */
+/* virtual */ void USBHost::deviceDisconnected(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr)
+{
+ // be sure that the device disconnected is connected...
+ int idx = findDevice(hub, port, hub_parent);
+ if (idx != -1) {
+ if (!deviceInUse[idx])
+ return;
+ } else {
+ return;
+ }
+
+ message_t * usb_msg = mail_usb_event.alloc();
+ usb_msg->event_id = DEVICE_DISCONNECTED_EVENT;
+ usb_msg->hub = hub;
+ usb_msg->port = port;
+ usb_msg->hub_parent = hub_parent;
+ mail_usb_event.put(usb_msg);
+}
+
+void USBHost::freeDevice(USBDeviceConnected * dev)
+{
+ USBEndpoint * ep = NULL;
+ HCED * ed = NULL;
+
+#if MAX_HUB_NB
+ if (dev->getClass() == HUB_CLASS) {
+ if (dev->hub == NULL) {
+ USB_ERR("HUB NULL!!!!!\r\n");
+ } else {
+ dev->hub->hubDisconnected();
+ for (uint8_t i = 0; i < MAX_HUB_NB; i++) {
+ if (dev->hub == &hubs[i]) {
+ hub_in_use[i] = false;
+ break;
+ }
+ }
+ }
+ }
+
+ // notify hub parent that this device has been disconnected
+ if (dev->getHubParent())
+ dev->getHubParent()->deviceDisconnected(dev);
+
+#endif
+
+ int idx = findDevice(dev);
+ if (idx != -1) {
+ deviceInUse[idx] = false;
+ deviceReset[idx] = false;
+
+ for (uint8_t j = 0; j < MAX_INTF; j++) {
+ deviceAttachedDriver[idx][j] = false;
+ if (dev->getInterface(j) != NULL) {
+ USB_DBG("FREE INTF %d on dev: %p, %p, nb_endpot: %d, %s", j, (void *)dev->getInterface(j), dev, dev->getInterface(j)->nb_endpoint, dev->getName(j));
+ for (int i = 0; i < dev->getInterface(j)->nb_endpoint; i++) {
+ if ((ep = dev->getEndpoint(j, i)) != NULL) {
+ ed = (HCED *)ep->getHCED();
+ ed->control |= (1 << 14); //sKip bit
+ unqueueEndpoint(ep);
+
+ freeTD((volatile uint8_t*)ep->getTDList()[0]);
+ freeTD((volatile uint8_t*)ep->getTDList()[1]);
+
+ freeED((uint8_t *)ep->getHCED());
+ }
+ printList(BULK_ENDPOINT);
+ printList(INTERRUPT_ENDPOINT);
+ }
+ USB_INFO("Device disconnected [%p - %s - hub: %d - port: %d]", dev, dev->getName(j), dev->getHub(), dev->getPort());
+ }
+ }
+ dev->disconnect();
+ }
+}
+
+
+void USBHost::unqueueEndpoint(USBEndpoint * ep)
+{
+ USBEndpoint * prec = NULL;
+ USBEndpoint * current = NULL;
+
+ for (int i = 0; i < 2; i++) {
+ current = (i == 0) ? (USBEndpoint*)headBulkEndpoint : (USBEndpoint*)headInterruptEndpoint;
+ prec = current;
+ while (current != NULL) {
+ if (current == ep) {
+ if (current->nextEndpoint() != NULL) {
+ prec->queueEndpoint(current->nextEndpoint());
+ if (current == headBulkEndpoint) {
+ updateBulkHeadED((uint32_t)current->nextEndpoint()->getHCED());
+ headBulkEndpoint = current->nextEndpoint();
+ } else if (current == headInterruptEndpoint) {
+ updateInterruptHeadED((uint32_t)current->nextEndpoint()->getHCED());
+ headInterruptEndpoint = current->nextEndpoint();
+ }
+ }
+ // here we are dequeuing the queue of ed
+ // we need to update the tail pointer
+ else {
+ prec->queueEndpoint(NULL);
+ if (current == headBulkEndpoint) {
+ updateBulkHeadED(0);
+ headBulkEndpoint = current->nextEndpoint();
+ } else if (current == headInterruptEndpoint) {
+ updateInterruptHeadED(0);
+ headInterruptEndpoint = current->nextEndpoint();
+ }
+
+ // modify tail
+ switch (current->getType()) {
+ case BULK_ENDPOINT:
+ tailBulkEndpoint = prec;
+ break;
+ case INTERRUPT_ENDPOINT:
+ tailInterruptEndpoint = prec;
+ break;
+ default:
+ break;
+ }
+ }
+ current->setState(USB_TYPE_FREE);
+ return;
+ }
+ prec = current;
+ current = current->nextEndpoint();
+ }
+ }
+}
+
+
+USBDeviceConnected * USBHost::getDevice(uint8_t index)
+{
+ if ((index >= MAX_DEVICE_CONNECTED) || (!deviceInUse[index])) {
+ return NULL;
+ }
+ return (USBDeviceConnected*)&devices[index];
+}
+
+// create an USBEndpoint descriptor. the USBEndpoint is not linked
+USBEndpoint * USBHost::newEndpoint(ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint32_t size, uint8_t addr)
+{
+ int i = 0;
+ HCED * ed = (HCED *)getED();
+ HCTD* td_list[2] = { (HCTD*)getTD(), (HCTD*)getTD() };
+
+ memset((void *)td_list[0], 0x00, sizeof(HCTD));
+ memset((void *)td_list[1], 0x00, sizeof(HCTD));
+
+ // search a free USBEndpoint
+ for (i = 0; i < MAX_ENDPOINT; i++) {
+ if (endpoints[i].getState() == USB_TYPE_FREE) {
+ endpoints[i].init(ed, type, dir, size, addr, td_list);
+ USB_DBG("USBEndpoint created (%p): type: %d, dir: %d, size: %d, addr: %d, state: %s", &endpoints[i], type, dir, size, addr, endpoints[i].getStateString());
+ return &endpoints[i];
+ }
+ }
+ USB_ERR("could not allocate more endpoints!!!!");
+ return NULL;
+}
+
+
+USB_TYPE USBHost::resetDevice(USBDeviceConnected * dev)
+{
+ int index = findDevice(dev);
+ if (index != -1) {
+ USB_DBG("Resetting hub %d, port %d\n", dev->getHub(), dev->getPort());
+ Thread::wait(100);
+ if (dev->getHub() == 0) {
+ resetRootHub();
+ }
+#if MAX_HUB_NB
+ else {
+ dev->getHubParent()->portReset(dev->getPort());
+ }
+#endif
+ Thread::wait(100);
+ deviceReset[index] = true;
+ return USB_TYPE_OK;
+ }
+
+ return USB_TYPE_ERROR;
+}
+
+// link the USBEndpoint to the linked list and attach an USBEndpoint to a device
+bool USBHost::addEndpoint(USBDeviceConnected * dev, uint8_t intf_nb, USBEndpoint * ep)
+{
+
+ if (ep == NULL) {
+ return false;
+ }
+
+ HCED * prevEd;
+
+ // set device address in the USBEndpoint descriptor
+ if (dev == NULL) {
+ ep->setDeviceAddress(0);
+ } else {
+ ep->setDeviceAddress(dev->getAddress());
+ }
+
+ if ((dev != NULL) && dev->getSpeed()) {
+ ep->setSpeed(dev->getSpeed());
+ }
+
+ ep->setIntfNb(intf_nb);
+
+ // queue the new USBEndpoint on the ED list
+ switch (ep->getType()) {
+
+ case CONTROL_ENDPOINT:
+ prevEd = ( HCED*) controlHeadED();
+ if (!prevEd) {
+ updateControlHeadED((uint32_t) ep->getHCED());
+ USB_DBG_TRANSFER("First control USBEndpoint: %08X", (uint32_t) ep->getHCED());
+ headControlEndpoint = ep;
+ tailControlEndpoint = ep;
+ return true;
+ }
+ tailControlEndpoint->queueEndpoint(ep);
+ tailControlEndpoint = ep;
+ return true;
+
+ case BULK_ENDPOINT:
+ prevEd = ( HCED*) bulkHeadED();
+ if (!prevEd) {
+ updateBulkHeadED((uint32_t) ep->getHCED());
+ USB_DBG_TRANSFER("First bulk USBEndpoint: %08X\r\n", (uint32_t) ep->getHCED());
+ headBulkEndpoint = ep;
+ tailBulkEndpoint = ep;
+ break;
+ }
+ USB_DBG_TRANSFER("Queue BULK Ed %p after %p\r\n",ep->getHCED(), prevEd);
+ tailBulkEndpoint->queueEndpoint(ep);
+ tailBulkEndpoint = ep;
+ break;
+
+ case INTERRUPT_ENDPOINT:
+ prevEd = ( HCED*) interruptHeadED();
+ if (!prevEd) {
+ updateInterruptHeadED((uint32_t) ep->getHCED());
+ USB_DBG_TRANSFER("First interrupt USBEndpoint: %08X\r\n", (uint32_t) ep->getHCED());
+ headInterruptEndpoint = ep;
+ tailInterruptEndpoint = ep;
+ break;
+ }
+ USB_DBG_TRANSFER("Queue INTERRUPT Ed %p after %p\r\n",ep->getHCED(), prevEd);
+ tailInterruptEndpoint->queueEndpoint(ep);
+ tailInterruptEndpoint = ep;
+ break;
+ default:
+ return false;
+ }
+
+ ep->dev = dev;
+ dev->addEndpoint(intf_nb, ep);
+
+ return true;
+}
+
+
+int USBHost::findDevice(USBDeviceConnected * dev)
+{
+ for (int i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ if (dev == &devices[i]) {
+ return i;
+ }
+ }
+ return -1;
+}
+
+int USBHost::findDevice(uint8_t hub, uint8_t port, USBHostHub * hub_parent)
+{
+ for (int i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ if (devices[i].getHub() == hub && devices[i].getPort() == port) {
+ if (hub_parent != NULL) {
+ if (hub_parent == devices[i].getHubParent())
+ return i;
+ } else {
+ return i;
+ }
+ }
+ }
+ return -1;
+}
+
+void USBHost::printList(ENDPOINT_TYPE type)
+{
+#if DEBUG_EP_STATE
+ volatile HCED * hced;
+ switch(type) {
+ case CONTROL_ENDPOINT:
+ hced = (HCED *)controlHeadED();
+ break;
+ case BULK_ENDPOINT:
+ hced = (HCED *)bulkHeadED();
+ break;
+ case INTERRUPT_ENDPOINT:
+ hced = (HCED *)interruptHeadED();
+ break;
+ }
+ volatile HCTD * hctd = NULL;
+ const char * type_str = (type == BULK_ENDPOINT) ? "BULK" :
+ ((type == INTERRUPT_ENDPOINT) ? "INTERRUPT" :
+ ((type == CONTROL_ENDPOINT) ? "CONTROL" : "ISOCHRONOUS"));
+ printf("State of %s:\r\n", type_str);
+ while (hced != NULL) {
+ uint8_t dir = ((hced->control & (3 << 11)) >> 11);
+ printf("hced: %p [ADDR: %d, DIR: %s, EP_NB: 0x%X]\r\n", hced,
+ hced->control & 0x7f,
+ (dir == 1) ? "OUT" : ((dir == 0) ? "FROM_TD":"IN"),
+ (hced->control & (0xf << 7)) >> 7);
+ hctd = (HCTD *)((uint32_t)(hced->headTD) & ~(0xf));
+ while (hctd != hced->tailTD) {
+ printf("\thctd: %p [DIR: %s]\r\n", hctd, ((hctd->control & (3 << 19)) >> 19) == 1 ? "OUT" : "IN");
+ hctd = hctd->nextTD;
+ }
+ printf("\thctd: %p\r\n", hctd);
+ hced = hced->nextED;
+ }
+ printf("\r\n\r\n");
+#endif
+}
+
+
+// add a transfer on the TD linked list
+USB_TYPE USBHost::addTransfer(USBEndpoint * ed, uint8_t * buf, uint32_t len)
+{
+ td_mutex.lock();
+
+ // allocate a TD which will be freed in TDcompletion
+ volatile HCTD * td = ed->getNextTD();
+ if (td == NULL) {
+ return USB_TYPE_ERROR;
+ }
+
+ uint32_t token = (ed->isSetup() ? TD_SETUP : ( (ed->getDir() == IN) ? TD_IN : TD_OUT ));
+
+ uint32_t td_toggle;
+
+ if (ed->getType() == CONTROL_ENDPOINT) {
+ if (ed->isSetup()) {
+ td_toggle = TD_TOGGLE_0;
+ } else {
+ td_toggle = TD_TOGGLE_1;
+ }
+ } else {
+ td_toggle = 0;
+ }
+
+ td->control = (TD_ROUNDING | token | TD_DELAY_INT(0) | td_toggle | TD_CC);
+ td->currBufPtr = buf;
+ td->bufEnd = (buf + (len - 1));
+
+ ENDPOINT_TYPE type = ed->getType();
+
+ disableList(type);
+ ed->queueTransfer();
+ printList(type);
+ enableList(type);
+
+ td_mutex.unlock();
+
+ return USB_TYPE_PROCESSING;
+}
+
+
+
+USB_TYPE USBHost::getDeviceDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_dev_descr)
+{
+ USB_TYPE t = controlRead( dev,
+ USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE,
+ GET_DESCRIPTOR,
+ (DEVICE_DESCRIPTOR << 8) | (0),
+ 0, buf, MIN(DEVICE_DESCRIPTOR_LENGTH, max_len_buf));
+ if (len_dev_descr)
+ *len_dev_descr = MIN(DEVICE_DESCRIPTOR_LENGTH, max_len_buf);
+
+ return t;
+}
+
+USB_TYPE USBHost::getConfigurationDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_conf_descr)
+{
+ USB_TYPE res;
+ uint16_t total_conf_descr_length = 0;
+
+ // fourth step: get the beginning of the configuration descriptor to have the total length of the conf descr
+ res = controlRead( dev,
+ USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE,
+ GET_DESCRIPTOR,
+ (CONFIGURATION_DESCRIPTOR << 8) | (0),
+ 0, buf, CONFIGURATION_DESCRIPTOR_LENGTH);
+
+ if (res != USB_TYPE_OK) {
+ USB_ERR("GET CONF 1 DESCR FAILED");
+ return res;
+ }
+ total_conf_descr_length = buf[2] | (buf[3] << 8);
+ total_conf_descr_length = MIN(max_len_buf, total_conf_descr_length);
+
+ if (len_conf_descr)
+ *len_conf_descr = total_conf_descr_length;
+
+ USB_DBG("TOTAL_LENGTH: %d \t NUM_INTERF: %d", total_conf_descr_length, buf[4]);
+
+ return controlRead( dev,
+ USB_DEVICE_TO_HOST | USB_RECIPIENT_DEVICE,
+ GET_DESCRIPTOR,
+ (CONFIGURATION_DESCRIPTOR << 8) | (0),
+ 0, buf, total_conf_descr_length);
+}
+
+
+USB_TYPE USBHost::setAddress(USBDeviceConnected * dev, uint8_t address) {
+ return controlWrite( dev,
+ USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE,
+ SET_ADDRESS,
+ address,
+ 0, NULL, 0);
+
+}
+
+USB_TYPE USBHost::setConfiguration(USBDeviceConnected * dev, uint8_t conf)
+{
+ return controlWrite( dev,
+ USB_HOST_TO_DEVICE | USB_RECIPIENT_DEVICE,
+ SET_CONFIGURATION,
+ conf,
+ 0, NULL, 0);
+}
+
+uint8_t USBHost::numberDriverAttached(USBDeviceConnected * dev) {
+ int index = findDevice(dev);
+ uint8_t cnt = 0;
+ if (index == -1)
+ return 0;
+ for (uint8_t i = 0; i < MAX_INTF; i++) {
+ if (deviceAttachedDriver[index][i])
+ cnt++;
+ }
+ return cnt;
+}
+
+// enumerate a device with the control USBEndpoint
+USB_TYPE USBHost::enumerate(USBDeviceConnected * dev, IUSBEnumerator* pEnumerator)
+{
+ uint16_t total_conf_descr_length = 0;
+ USB_TYPE res;
+
+ do
+ {
+ Lock lock(this);
+
+ // don't enumerate a device which all interfaces are registered to a specific driver
+ int index = findDevice(dev);
+
+ if (index == -1) {
+ return USB_TYPE_ERROR;
+ }
+
+ uint8_t nb_intf_attached = numberDriverAttached(dev);
+ USB_DBG("dev: %p nb_intf: %d", dev, dev->getNbIntf());
+ USB_DBG("dev: %p nb_intf_attached: %d", dev, nb_intf_attached);
+ if ((nb_intf_attached != 0) && (dev->getNbIntf() == nb_intf_attached)) {
+ USB_DBG("Don't enumerate dev: %p because all intf are registered with a driver", dev);
+ return USB_TYPE_OK;
+ }
+
+ USB_DBG("Enumerate dev: %p", dev);
+
+ // third step: get the whole device descriptor to see vid, pid
+ res = getDeviceDescriptor(dev, data, DEVICE_DESCRIPTOR_LENGTH);
+
+ if (res != USB_TYPE_OK) {
+ USB_DBG("GET DEV DESCR FAILED");
+ return res;
+ }
+
+ dev->setClass(data[4]);
+ dev->setSubClass(data[5]);
+ dev->setProtocol(data[6]);
+ dev->setVid(data[8] | (data[9] << 8));
+ dev->setPid(data[10] | (data[11] << 8));
+ USB_DBG("CLASS: %02X \t VID: %04X \t PID: %04X", data[4], data[8] | (data[9] << 8), data[10] | (data[11] << 8));
+
+ pEnumerator->setVidPid( data[8] | (data[9] << 8), data[10] | (data[11] << 8) );
+
+ res = getConfigurationDescriptor(dev, data, sizeof(data), &total_conf_descr_length);
+ if (res != USB_TYPE_OK) {
+ return res;
+ }
+
+ #if (DEBUG > 3)
+ USB_DBG("CONFIGURATION DESCRIPTOR:\r\n");
+ for (int i = 0; i < total_conf_descr_length; i++)
+ printf("%02X ", data[i]);
+ printf("\r\n\r\n");
+ #endif
+
+ // Parse the configuration descriptor
+ parseConfDescr(dev, data, total_conf_descr_length, pEnumerator);
+
+ // only set configuration if not enumerated before
+ if (!dev->isEnumerated()) {
+
+ USB_DBG("Set configuration 1 on dev: %p", dev);
+ // sixth step: set configuration (only 1 supported)
+ res = setConfiguration(dev, 1);
+
+ if (res != USB_TYPE_OK) {
+ USB_DBG("SET CONF FAILED");
+ return res;
+ }
+ }
+
+ dev->setEnumerated();
+
+ // Now the device is enumerated!
+ USB_DBG("dev %p is enumerated\r\n", dev);
+
+ } while(0);
+
+ // Some devices may require this delay
+ Thread::wait(100);
+
+ return USB_TYPE_OK;
+}
+// this method fills the USBDeviceConnected object: class,.... . It also add endpoints found in the descriptor.
+void USBHost::parseConfDescr(USBDeviceConnected * dev, uint8_t * conf_descr, uint32_t len, IUSBEnumerator* pEnumerator)
+{
+ uint32_t index = 0;
+ uint32_t len_desc = 0;
+ uint8_t id = 0;
+ int nb_endpoints_used = 0;
+ USBEndpoint * ep = NULL;
+ uint8_t intf_nb = 0;
+ bool parsing_intf = false;
+ uint8_t current_intf = 0;
+
+ while (index < len) {
+ len_desc = conf_descr[index];
+ id = conf_descr[index+1];
+ switch (id) {
+ case CONFIGURATION_DESCRIPTOR:
+ USB_DBG("dev: %p has %d intf", dev, conf_descr[4]);
+ dev->setNbIntf(conf_descr[4]);
+ break;
+ case INTERFACE_DESCRIPTOR:
+ if(pEnumerator->parseInterface(conf_descr[index + 2], conf_descr[index + 5], conf_descr[index + 6], conf_descr[index + 7])) {
+ if (intf_nb++ <= MAX_INTF) {
+ current_intf = conf_descr[index + 2];
+ dev->addInterface(current_intf, conf_descr[index + 5], conf_descr[index + 6], conf_descr[index + 7]);
+ nb_endpoints_used = 0;
+ USB_DBG("ADD INTF %d on device %p: class: %d, subclass: %d, proto: %d", current_intf, dev, conf_descr[index + 5],conf_descr[index + 6],conf_descr[index + 7]);
+ } else {
+ USB_DBG("Drop intf...");
+ }
+ parsing_intf = true;
+ } else {
+ parsing_intf = false;
+ }
+ break;
+ case ENDPOINT_DESCRIPTOR:
+ if (parsing_intf && (intf_nb <= MAX_INTF) ) {
+ if (nb_endpoints_used < MAX_ENDPOINT_PER_INTERFACE) {
+ if( pEnumerator->useEndpoint(current_intf, (ENDPOINT_TYPE)(conf_descr[index + 3] & 0x03), (ENDPOINT_DIRECTION)((conf_descr[index + 2] >> 7) + 1)) ) {
+ // if the USBEndpoint is isochronous -> skip it (TODO: fix this)
+ if ((conf_descr[index + 3] & 0x03) != ISOCHRONOUS_ENDPOINT) {
+ ep = newEndpoint((ENDPOINT_TYPE)(conf_descr[index+3] & 0x03),
+ (ENDPOINT_DIRECTION)((conf_descr[index + 2] >> 7) + 1),
+ conf_descr[index + 4] | (conf_descr[index + 5] << 8),
+ conf_descr[index + 2] & 0x0f);
+ USB_DBG("ADD USBEndpoint %p, on interf %d on device %p", ep, current_intf, dev);
+ if (ep != NULL && dev != NULL) {
+ addEndpoint(dev, current_intf, ep);
+ } else {
+ USB_DBG("EP NULL");
+ }
+ nb_endpoints_used++;
+ } else {
+ USB_DBG("ISO USBEndpoint NOT SUPPORTED");
+ }
+ }
+ }
+ }
+ break;
+ case HID_DESCRIPTOR:
+ lenReportDescr = conf_descr[index + 7] | (conf_descr[index + 8] << 8);
+ break;
+ default:
+ break;
+ }
+ index += len_desc;
+ }
+}
+
+
+USB_TYPE USBHost::bulkWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+ return generalTransfer(dev, ep, buf, len, blocking, BULK_ENDPOINT, true);
+}
+
+USB_TYPE USBHost::bulkRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+ return generalTransfer(dev, ep, buf, len, blocking, BULK_ENDPOINT, false);
+}
+
+USB_TYPE USBHost::interruptWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+ return generalTransfer(dev, ep, buf, len, blocking, INTERRUPT_ENDPOINT, true);
+}
+
+USB_TYPE USBHost::interruptRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking)
+{
+ return generalTransfer(dev, ep, buf, len, blocking, INTERRUPT_ENDPOINT, false);
+}
+
+USB_TYPE USBHost::generalTransfer(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking, ENDPOINT_TYPE type, bool write) {
+
+#if DEBUG_TRANSFER
+ const char * type_str = (type == BULK_ENDPOINT) ? "BULK" : ((type == INTERRUPT_ENDPOINT) ? "INTERRUPT" : "ISOCHRONOUS");
+ USB_DBG_TRANSFER("----- %s %s [dev: %p - %s - hub: %d - port: %d - addr: %d - ep: %02X]------", type_str, (write) ? "WRITE" : "READ", dev, dev->getName(ep->getIntfNb()), dev->getHub(), dev->getPort(), dev->getAddress(), ep->getAddress());
+#endif
+
+ Lock lock(this);
+
+ USB_TYPE res;
+ ENDPOINT_DIRECTION dir = (write) ? OUT : IN;
+
+ if (dev == NULL) {
+ USB_ERR("dev NULL");
+ return USB_TYPE_ERROR;
+ }
+
+ if (ep == NULL) {
+ USB_ERR("ep NULL");
+ return USB_TYPE_ERROR;
+ }
+
+ if (ep->getState() != USB_TYPE_IDLE) {
+ USB_WARN("[ep: %p - dev: %p - %s] NOT IDLE: %s", ep, ep->dev, ep->dev->getName(ep->getIntfNb()), ep->getStateString());
+ return ep->getState();
+ }
+
+ if ((ep->getDir() != dir) || (ep->getType() != type)) {
+ USB_ERR("[ep: %p - dev: %p] wrong dir or bad USBEndpoint type", ep, ep->dev);
+ return USB_TYPE_ERROR;
+ }
+
+ if (dev->getAddress() != ep->getDeviceAddress()) {
+ USB_ERR("[ep: %p - dev: %p] USBEndpoint addr and device addr don't match", ep, ep->dev);
+ return USB_TYPE_ERROR;
+ }
+
+#if DEBUG_TRANSFER
+ if (write) {
+ USB_DBG_TRANSFER("%s WRITE buffer", type_str);
+ for (int i = 0; i < ep->getLengthTransferred(); i++)
+ printf("%02X ", buf[i]);
+ printf("\r\n\r\n");
+ }
+#endif
+ addTransfer(ep, buf, len);
+
+ if (blocking) {
+
+ ep->ep_queue.get();
+ res = ep->getState();
+
+ USB_DBG_TRANSFER("%s TRANSFER res: %s on ep: %p\r\n", type_str, ep->getStateString(), ep);
+
+ if (res != USB_TYPE_IDLE) {
+ return res;
+ }
+
+ return USB_TYPE_OK;
+ }
+
+ return USB_TYPE_PROCESSING;
+
+}
+
+
+USB_TYPE USBHost::controlRead(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len) {
+ return controlTransfer(dev, requestType, request, value, index, buf, len, false);
+}
+
+USB_TYPE USBHost::controlWrite(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len) {
+ return controlTransfer(dev, requestType, request, value, index, buf, len, true);
+}
+
+USB_TYPE USBHost::controlTransfer(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len, bool write)
+{
+ Lock lock(this);
+ USB_DBG_TRANSFER("----- CONTROL %s [dev: %p - hub: %d - port: %d] ------", (write) ? "WRITE" : "READ", dev, dev->getHub(), dev->getPort());
+
+ int length_transfer = len;
+ USB_TYPE res;
+ uint32_t token;
+
+ control->setSpeed(dev->getSpeed());
+ control->setSize(dev->getSizeControlEndpoint());
+ if (dev->isActiveAddress()) {
+ control->setDeviceAddress(dev->getAddress());
+ } else {
+ control->setDeviceAddress(0);
+ }
+
+ USB_DBG_TRANSFER("Control transfer on device: %d\r\n", control->getDeviceAddress());
+ fillControlBuf(requestType, request, value, index, len);
+
+#if DEBUG_TRANSFER
+ USB_DBG_TRANSFER("SETUP PACKET: ");
+ for (int i = 0; i < 8; i++)
+ printf("%01X ", setupPacket[i]);
+ printf("\r\n");
+#endif
+
+ control->setNextToken(TD_SETUP);
+ addTransfer(control, (uint8_t*)setupPacket, 8);
+
+ control->ep_queue.get();
+ res = control->getState();
+
+ USB_DBG_TRANSFER("CONTROL setup stage %s", control->getStateString());
+
+ if (res != USB_TYPE_IDLE) {
+ return res;
+ }
+
+ if (length_transfer) {
+ token = (write) ? TD_OUT : TD_IN;
+ control->setNextToken(token);
+ addTransfer(control, (uint8_t *)buf, length_transfer);
+
+ control->ep_queue.get();
+ res = control->getState();
+
+#if DEBUG_TRANSFER
+ USB_DBG_TRANSFER("CONTROL %s stage %s", (write) ? "WRITE" : "READ", control->getStateString());
+ if (write) {
+ USB_DBG_TRANSFER("CONTROL WRITE buffer");
+ for (int i = 0; i < control->getLengthTransferred(); i++)
+ printf("%02X ", buf[i]);
+ printf("\r\n\r\n");
+ } else {
+ USB_DBG_TRANSFER("CONTROL READ SUCCESS [%d bytes transferred]", control->getLengthTransferred());
+ for (int i = 0; i < control->getLengthTransferred(); i++)
+ printf("%02X ", buf[i]);
+ printf("\r\n\r\n");
+ }
+#endif
+
+ if (res != USB_TYPE_IDLE) {
+ return res;
+ }
+ }
+
+ token = (write) ? TD_IN : TD_OUT;
+ control->setNextToken(token);
+ addTransfer(control, NULL, 0);
+
+ control->ep_queue.get();
+ res = control->getState();
+
+ USB_DBG_TRANSFER("CONTROL ack stage %s", control->getStateString());
+
+ if (res != USB_TYPE_IDLE)
+ return res;
+
+ return USB_TYPE_OK;
+}
+
+
+void USBHost::fillControlBuf(uint8_t requestType, uint8_t request, uint16_t value, uint16_t index, int len)
+{
+ setupPacket[0] = requestType;
+ setupPacket[1] = request;
+ setupPacket[2] = (uint8_t) value;
+ setupPacket[3] = (uint8_t) (value >> 8);
+ setupPacket[4] = (uint8_t) index;
+ setupPacket[5] = (uint8_t) (index >> 8);
+ setupPacket[6] = (uint8_t) len;
+ setupPacket[7] = (uint8_t) (len >> 8);
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHost.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHost.h
new file mode 100644
index 000000000..802ae9931
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHost.h
@@ -0,0 +1,395 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOST_H
+#define USBHOST_H
+
+#include "USBHALHost.h"
+#include "USBDeviceConnected.h"
+#include "IUSBEnumerator.h"
+#include "USBHostConf.h"
+#include "rtos.h"
+#include "dbg.h"
+#include "USBHostHub.h"
+
+/**
+* USBHost class
+* This class is a singleton. All drivers have a reference on the static USBHost instance
+*/
+class USBHost : public USBHALHost {
+public:
+ /**
+ * Static method to create or retrieve the single USBHost instance
+ */
+ static USBHost * getHostInst();
+
+ /**
+ * Control read: setup stage, data stage and status stage
+ *
+ * @param dev the control read will be done for this device
+ * @param requestType request type
+ * @param request request
+ * @param value value
+ * @param index index
+ * @param buf pointer on a buffer where will be store the data received
+ * @param len length of the transfer
+ *
+ * @returns status of the control read
+ */
+ USB_TYPE controlRead(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len);
+
+ /**
+ * Control write: setup stage, data stage and status stage
+ *
+ * @param dev the control write will be done for this device
+ * @param requestType request type
+ * @param request request
+ * @param value value
+ * @param index index
+ * @param buf pointer on a buffer which will be written
+ * @param len length of the transfer
+ *
+ * @returns status of the control write
+ */
+ USB_TYPE controlWrite(USBDeviceConnected * dev, uint8_t requestType, uint8_t request, uint32_t value, uint32_t index, uint8_t * buf, uint32_t len);
+
+ /**
+ * Bulk read
+ *
+ * @param dev the bulk transfer will be done for this device
+ * @param ep USBEndpoint which will be used to read a packet
+ * @param buf pointer on a buffer where will be store the data received
+ * @param len length of the transfer
+ * @param blocking if true, the read is blocking (wait for completion)
+ *
+ * @returns status of the bulk read
+ */
+ USB_TYPE bulkRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+ /**
+ * Bulk write
+ *
+ * @param dev the bulk transfer will be done for this device
+ * @param ep USBEndpoint which will be used to write a packet
+ * @param buf pointer on a buffer which will be written
+ * @param len length of the transfer
+ * @param blocking if true, the write is blocking (wait for completion)
+ *
+ * @returns status of the bulk write
+ */
+ USB_TYPE bulkWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+ /**
+ * Interrupt read
+ *
+ * @param dev the bulk transfer will be done for this device
+ * @param ep USBEndpoint which will be used to write a packet
+ * @param buf pointer on a buffer which will be written
+ * @param len length of the transfer
+ * @param blocking if true, the read is blocking (wait for completion)
+ *
+ * @returns status of the interrupt read
+ */
+ USB_TYPE interruptRead(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+ /**
+ * Interrupt write
+ *
+ * @param dev the bulk transfer will be done for this device
+ * @param ep USBEndpoint which will be used to write a packet
+ * @param buf pointer on a buffer which will be written
+ * @param len length of the transfer
+ * @param blocking if true, the write is blocking (wait for completion)
+ *
+ * @returns status of the interrupt write
+ */
+ USB_TYPE interruptWrite(USBDeviceConnected * dev, USBEndpoint * ep, uint8_t * buf, uint32_t len, bool blocking = true);
+
+ /**
+ * Enumerate a device.
+ *
+ * @param dev device which will be enumerated
+ *
+ * @returns status of the enumeration
+ */
+ USB_TYPE enumerate(USBDeviceConnected * dev, IUSBEnumerator* pEnumerator);
+
+ /**
+ * reset a specific device
+ *
+ * @param dev device which will be resetted
+ */
+ USB_TYPE resetDevice(USBDeviceConnected * dev);
+
+ /**
+ * Get a device
+ *
+ * @param index index of the device which will be returned
+ *
+ * @returns pointer on the "index" device
+ */
+ USBDeviceConnected * getDevice(uint8_t index);
+
+ /*
+ * If there is a HID device connected, the host stores the length of the report descriptor.
+ * This avoid to the driver to re-ask the configuration descriptor to request the report descriptor
+ *
+ * @returns length of the report descriptor
+ */
+ inline uint16_t getLengthReportDescr() {
+ return lenReportDescr;
+ };
+
+ /**
+ * register a driver into the host associated with a callback function called when the device is disconnected
+ *
+ * @param dev device
+ * @param intf interface number
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ */
+ template<typename T>
+ inline void registerDriver(USBDeviceConnected * dev, uint8_t intf, T* tptr, void (T::*mptr)(void)) {
+ int index = findDevice(dev);
+ if ((index != -1) && (mptr != NULL) && (tptr != NULL)) {
+ USB_DBG("register driver for dev: %p on intf: %d", dev, intf);
+ deviceAttachedDriver[index][intf] = true;
+ dev->onDisconnect(intf, tptr, mptr);
+ }
+ }
+
+ /**
+ * register a driver into the host associated with a callback function called when the device is disconnected
+ *
+ * @param dev device
+ * @param intf interface number
+ * @param fn callback called when the specified device has been disconnected
+ */
+ inline void registerDriver(USBDeviceConnected * dev, uint8_t intf, void (*fn)(void)) {
+ int index = findDevice(dev);
+ if ((index != -1) && (fn != NULL)) {
+ USB_DBG("register driver for dev: %p on intf: %d", dev, intf);
+ deviceAttachedDriver[index][intf] = true;
+ dev->onDisconnect(intf, fn);
+ }
+ }
+
+ /**
+ * Instantiate to protect USB thread from accessing shared objects (USBConnectedDevices and Interfaces)
+ */
+ class Lock
+ {
+ public:
+ Lock(USBHost* pHost);
+ ~Lock();
+ private:
+ USBHost* m_pHost;
+ };
+
+ friend class USBHostHub;
+
+protected:
+
+ /**
+ * Virtual method called when a transfer has been completed
+ *
+ * @param addr list of the TDs which have been completed
+ */
+ virtual void transferCompleted(volatile uint32_t addr);
+
+ /**
+ * Virtual method called when a device has been connected
+ *
+ * @param hub hub number of the device
+ * @param port port number of the device
+ * @param lowSpeed 1 if low speed, 0 otherwise
+ * @param hub_parent reference on the parent hub
+ */
+ virtual void deviceConnected(int hub, int port, bool lowSpeed, USBHostHub * hub_parent = NULL);
+
+ /**
+ * Virtuel method called when a device has been disconnected
+ *
+ * @param hub hub number of the device
+ * @param port port number of the device
+ * @param addr list of the TDs which have been completed to dequeue freed TDs
+ */
+ virtual void deviceDisconnected(int hub, int port, USBHostHub * hub_parent, volatile uint32_t addr);
+
+
+private:
+ // singleton class -> constructor is private
+ USBHost();
+ static USBHost * instHost;
+ uint16_t lenReportDescr;
+
+ // endpoints
+ void unqueueEndpoint(USBEndpoint * ep) ;
+ USBEndpoint endpoints[MAX_ENDPOINT];
+ USBEndpoint* volatile control;
+
+ USBEndpoint* volatile headControlEndpoint;
+ USBEndpoint* volatile headBulkEndpoint;
+ USBEndpoint* volatile headInterruptEndpoint;
+
+ USBEndpoint* volatile tailControlEndpoint;
+ USBEndpoint* volatile tailBulkEndpoint;
+ USBEndpoint* volatile tailInterruptEndpoint;
+
+ bool controlEndpointAllocated;
+
+ // devices connected
+ USBDeviceConnected devices[MAX_DEVICE_CONNECTED];
+ bool deviceInUse[MAX_DEVICE_CONNECTED];
+ bool deviceAttachedDriver[MAX_DEVICE_CONNECTED][MAX_INTF];
+ bool deviceReset[MAX_DEVICE_CONNECTED];
+ bool deviceInited[MAX_DEVICE_CONNECTED];
+
+#if MAX_HUB_NB
+ USBHostHub hubs[MAX_HUB_NB];
+ bool hub_in_use[MAX_HUB_NB];
+#endif
+
+ // to store a setup packet
+ uint8_t setupPacket[8];
+
+ typedef struct {
+ uint8_t event_id;
+ void * td_addr;
+ uint8_t hub;
+ uint8_t port;
+ uint8_t lowSpeed;
+ uint8_t td_state;
+ void * hub_parent;
+ } message_t;
+
+ Thread usbThread;
+ void usb_process();
+ static void usb_process_static(void const * arg);
+ Mail<message_t, 10> mail_usb_event;
+ Mutex usb_mutex;
+ Mutex td_mutex;
+
+ // buffer for conf descriptor
+ uint8_t data[415];
+
+ /**
+ * Add a transfer on the TD linked list associated to an ED
+ *
+ * @param ed the transfer is associated to this ed
+ * @param buf pointer on a buffer where will be read/write data to send or receive
+ * @param len transfer length
+ *
+ * @return status of the transfer
+ */
+ USB_TYPE addTransfer(USBEndpoint * ed, uint8_t * buf, uint32_t len) ;
+
+ /**
+ * Link the USBEndpoint to the linked list and attach an USBEndpoint this USBEndpoint to a device
+ *
+ * @param dev pointer on a USBDeviceConnected object
+ * @param ep pointer on the USBEndpoint which will be added
+ *
+ * return true if successful
+ */
+ bool addEndpoint(USBDeviceConnected * dev, uint8_t intf_nb, USBEndpoint * ep) ;
+
+ /**
+ * Create an USBEndpoint descriptor. Warning: the USBEndpoint is not linked.
+ *
+ * @param type USBEndpoint type (CONTROL_ENDPOINT, BULK_ENDPOINT, INTERRUPT_ENDPOINT)
+ * @param dir USBEndpoint direction (no meaning for CONTROL_ENDPOINT)
+ * @param size USBEndpoint max packet size
+ * @param addr USBEndpoint address
+ *
+ * @returns pointer on the USBEndpoint created
+ */
+ USBEndpoint * newEndpoint(ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir, uint32_t size, uint8_t addr) ;
+
+ /**
+ * Request the device descriptor
+ *
+ * @param dev request the device descriptor on this device
+ * @param buf buffer to store the device descriptor
+ * @param max_len_buf maximum size of buf
+ * @param len_dev_descr pointer to store the length of the packet transferred
+ */
+ USB_TYPE getDeviceDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_dev_descr = NULL);
+
+ /**
+ * Request the configuration descriptor
+ *
+ * @param dev request the configuration descriptor on this device
+ * @param buf buffer to store the configuration descriptor
+ * @param max_len_buf maximum size of buf
+ * @param len_conf_descr pointer to store the length of the packet transferred
+ */
+ USB_TYPE getConfigurationDescriptor(USBDeviceConnected * dev, uint8_t * buf, uint16_t max_len_buf, uint16_t * len_conf_descr = NULL);
+
+ /**
+ * Set the address of a specific device
+ *
+ * @param dev device to set the address
+ * @param address address
+ */
+ USB_TYPE setAddress(USBDeviceConnected * dev, uint8_t address);
+
+ /**
+ * Set the configuration of a device
+ *
+ * @param dev device on which the specified configuration will be activated
+ * @param conf configuration number to activate (usually 1)
+ */
+ USB_TYPE setConfiguration(USBDeviceConnected * dev, uint8_t conf);
+
+ /**
+ * Free a specific device
+ *
+ * @param dev device to be freed
+ */
+ void freeDevice(USBDeviceConnected * dev);
+
+ USB_TYPE controlTransfer( USBDeviceConnected * dev,
+ uint8_t requestType,
+ uint8_t request,
+ uint32_t value,
+ uint32_t index,
+ uint8_t * buf,
+ uint32_t len,
+ bool write);
+
+ USB_TYPE generalTransfer( USBDeviceConnected * dev,
+ USBEndpoint * ep,
+ uint8_t * buf,
+ uint32_t len,
+ bool blocking,
+ ENDPOINT_TYPE type,
+ bool write) ;
+
+ void fillControlBuf(uint8_t requestType, uint8_t request, uint16_t value, uint16_t index, int len) ;
+ void parseConfDescr(USBDeviceConnected * dev, uint8_t * conf_descr, uint32_t len, IUSBEnumerator* pEnumerator) ;
+ int findDevice(USBDeviceConnected * dev) ;
+ int findDevice(uint8_t hub, uint8_t port, USBHostHub * hub_parent = NULL) ;
+ uint8_t numberDriverAttached(USBDeviceConnected * dev);
+
+ /////////////////////////
+ /// FOR DEBUG
+ /////////////////////////
+ void printList(ENDPOINT_TYPE type);
+
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHostConf.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHostConf.h
new file mode 100644
index 000000000..3a93b30bf
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHostConf.h
@@ -0,0 +1,91 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOST_CONF_H
+#define USBHOST_CONF_H
+
+/*
+* Maximum number of devices that can be connected
+* to the usb host
+*/
+#define MAX_DEVICE_CONNECTED 5
+
+/*
+* Maximum of Hub connected to the usb host
+*/
+#define MAX_HUB_NB 2
+
+/*
+* Maximum number of ports on a USB hub
+*/
+#define MAX_HUB_PORT 4
+
+/*
+* Enable USBHostMSD
+*/
+#define USBHOST_MSD 1
+
+/*
+* Enable USBHostKeyboard
+*/
+#define USBHOST_KEYBOARD 1
+
+/*
+* Enable USBHostMouse
+*/
+#define USBHOST_MOUSE 1
+
+/*
+* Enable USBHostSerial or USBHostMultiSerial (if set > 1)
+*/
+#define USBHOST_SERIAL 1
+
+/*
+* Enable USB3Gmodule
+*/
+#define USBHOST_3GMODULE 1
+
+/*
+* Enable USB MIDI
+*/
+#define USBHOST_MIDI 1
+
+/*
+* Maximum number of interfaces of a usb device
+*/
+#define MAX_INTF 4
+
+/*
+* Maximum number of endpoints on each interface
+*/
+#define MAX_ENDPOINT_PER_INTERFACE 3
+
+/*
+* Maximum number of endpoint descriptors that can be allocated
+*/
+#define MAX_ENDPOINT (MAX_DEVICE_CONNECTED * MAX_INTF * MAX_ENDPOINT_PER_INTERFACE)
+
+/*
+* Maximum number of transfer descriptors that can be allocated
+*/
+#define MAX_TD (MAX_ENDPOINT*2)
+
+/*
+* usb_thread stack size
+*/
+#define USB_THREAD_STACK (256*4 + MAX_HUB_NB*256*4)
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHostTypes.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHostTypes.h
new file mode 100644
index 000000000..c4462aa05
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHostTypes.h
@@ -0,0 +1,226 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USB_INC_H
+#define USB_INC_H
+
+#include "mbed.h"
+#include "toolchain.h"
+
+enum USB_TYPE {
+ USB_TYPE_OK = 0,
+
+ // completion code
+ USB_TYPE_CRC_ERROR = 1,
+ USB_TYPE_BIT_STUFFING_ERROR = 2,
+ USB_TYPE_DATA_TOGGLE_MISMATCH_ERROR = 3,
+ USB_TYPE_STALL_ERROR = 4,
+ USB_TYPE_DEVICE_NOT_RESPONDING_ERROR = 5,
+ USB_TYPE_PID_CHECK_FAILURE_ERROR = 6,
+ USB_TYPE_UNEXPECTED_PID_ERROR = 7,
+ USB_TYPE_DATA_OVERRUN_ERROR = 8,
+ USB_TYPE_DATA_UNDERRUN_ERROR = 9,
+ USB_TYPE_RESERVED = 9,
+ USB_TYPE_RESERVED_ = 10,
+ USB_TYPE_BUFFER_OVERRUN_ERROR = 12,
+ USB_TYPE_BUFFER_UNDERRUN_ERROR = 13,
+
+ // general usb state
+ USB_TYPE_DISCONNECTED = 14,
+ USB_TYPE_FREE = 15,
+ USB_TYPE_IDLE = 16,
+ USB_TYPE_PROCESSING = 17,
+
+ USB_TYPE_ERROR = 18,
+};
+
+
+enum ENDPOINT_DIRECTION {
+ OUT = 1,
+ IN
+};
+
+enum ENDPOINT_TYPE {
+ CONTROL_ENDPOINT = 0,
+ ISOCHRONOUS_ENDPOINT,
+ BULK_ENDPOINT,
+ INTERRUPT_ENDPOINT
+};
+
+#define AUDIO_CLASS 0x01
+#define CDC_CLASS 0x02
+#define HID_CLASS 0x03
+#define MSD_CLASS 0x08
+#define HUB_CLASS 0x09
+#define SERIAL_CLASS 0x0A
+
+// ------------------ HcControl Register ---------------------
+#define OR_CONTROL_PLE 0x00000004
+#define OR_CONTROL_CLE 0x00000010
+#define OR_CONTROL_BLE 0x00000020
+#define OR_CONTROL_HCFS 0x000000C0
+#define OR_CONTROL_HC_OPER 0x00000080
+// ----------------- HcCommandStatus Register -----------------
+#define OR_CMD_STATUS_HCR 0x00000001
+#define OR_CMD_STATUS_CLF 0x00000002
+#define OR_CMD_STATUS_BLF 0x00000004
+// --------------- HcInterruptStatus Register -----------------
+#define OR_INTR_STATUS_WDH 0x00000002
+#define OR_INTR_STATUS_RHSC 0x00000040
+#define OR_INTR_STATUS_UE 0x00000010
+// --------------- HcInterruptEnable Register -----------------
+#define OR_INTR_ENABLE_WDH 0x00000002
+#define OR_INTR_ENABLE_RHSC 0x00000040
+#define OR_INTR_ENABLE_MIE 0x80000000
+// ---------------- HcRhDescriptorA Register ------------------
+#define OR_RH_STATUS_LPSC 0x00010000
+#define OR_RH_STATUS_DRWE 0x00008000
+// -------------- HcRhPortStatus[1:NDP] Register --------------
+#define OR_RH_PORT_CCS 0x00000001
+#define OR_RH_PORT_PRS 0x00000010
+#define OR_RH_PORT_CSC 0x00010000
+#define OR_RH_PORT_PRSC 0x00100000
+#define OR_RH_PORT_LSDA 0x00000200
+
+#define FI 0x2EDF // 12000 bits per frame (-1)
+#define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
+
+#define ED_SKIP (uint32_t) (0x00001000) // Skip this ep in queue
+
+#define TD_ROUNDING (uint32_t) (0x00040000) // Buffer Rounding
+#define TD_SETUP (uint32_t)(0) // Direction of Setup Packet
+#define TD_IN (uint32_t)(0x00100000) // Direction In
+#define TD_OUT (uint32_t)(0x00080000) // Direction Out
+#define TD_DELAY_INT(x) (uint32_t)((x) << 21) // Delay Interrupt
+#define TD_TOGGLE_0 (uint32_t)(0x02000000) // Toggle 0
+#define TD_TOGGLE_1 (uint32_t)(0x03000000) // Toggle 1
+#define TD_CC (uint32_t)(0xF0000000) // Completion Code
+
+#define DEVICE_DESCRIPTOR (1)
+#define CONFIGURATION_DESCRIPTOR (2)
+#define INTERFACE_DESCRIPTOR (4)
+#define ENDPOINT_DESCRIPTOR (5)
+#define HID_DESCRIPTOR (33)
+
+// ----------- Control RequestType Fields -----------
+#define USB_DEVICE_TO_HOST 0x80
+#define USB_HOST_TO_DEVICE 0x00
+#define USB_REQUEST_TYPE_CLASS 0x20
+#define USB_REQUEST_TYPE_STANDARD 0x00
+#define USB_RECIPIENT_DEVICE 0x00
+#define USB_RECIPIENT_INTERFACE 0x01
+#define USB_RECIPIENT_ENDPOINT 0x02
+
+// -------------- USB Standard Requests --------------
+#define SET_ADDRESS 0x05
+#define GET_DESCRIPTOR 0x06
+#define SET_CONFIGURATION 0x09
+#define SET_INTERFACE 0x0b
+#define CLEAR_FEATURE 0x01
+
+// -------------- USB Descriptor Length --------------
+#define DEVICE_DESCRIPTOR_LENGTH 0x12
+#define CONFIGURATION_DESCRIPTOR_LENGTH 0x09
+
+// ------------ HostController Transfer Descriptor ------------
+typedef struct HCTD {
+ __IO uint32_t control; // Transfer descriptor control
+ __IO uint8_t * currBufPtr; // Physical address of current buffer pointer
+ __IO HCTD * nextTD; // Physical pointer to next Transfer Descriptor
+ __IO uint8_t * bufEnd; // Physical address of end of buffer
+ void * ep; // ep address where a td is linked in
+ uint32_t dummy[3]; // padding
+} PACKED HCTD;
+
+// ----------- HostController EndPoint Descriptor -------------
+typedef struct hcEd {
+ __IO uint32_t control; // Endpoint descriptor control
+ __IO HCTD * tailTD; // Physical address of tail in Transfer descriptor list
+ __IO HCTD * headTD; // Physcial address of head in Transfer descriptor list
+ __IO hcEd * nextED; // Physical address of next Endpoint descriptor
+} PACKED HCED;
+
+
+// ----------- Host Controller Communication Area ------------
+typedef struct hcca {
+ __IO uint32_t IntTable[32]; // Interrupt Table
+ __IO uint32_t FrameNumber; // Frame Number
+ __IO uint32_t DoneHead; // Done Head
+ volatile uint8_t Reserved[116]; // Reserved for future use
+ volatile uint8_t Unknown[4]; // Unused
+} PACKED HCCA;
+
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint16_t bcdUSB;
+ uint8_t bDeviceClass;
+ uint8_t bDeviceSubClass;
+ uint8_t bDeviceProtocol;
+ uint8_t bMaxPacketSize;
+ uint16_t idVendor;
+ uint16_t idProduct;
+ uint16_t bcdDevice;
+ uint8_t iManufacturer;
+ uint8_t iProduct;
+ uint8_t iSerialNumber;
+ uint8_t bNumConfigurations;
+} PACKED DeviceDescriptor;
+
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint16_t wTotalLength;
+ uint8_t bNumInterfaces;
+ uint8_t bConfigurationValue;
+ uint8_t iConfiguration;
+ uint8_t bmAttributes;
+ uint8_t bMaxPower;
+} PACKED ConfigurationDescriptor;
+
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bInterfaceNumber;
+ uint8_t bAlternateSetting;
+ uint8_t bNumEndpoints;
+ uint8_t bInterfaceClass;
+ uint8_t bInterfaceSubClass;
+ uint8_t bInterfaceProtocol;
+ uint8_t iInterface;
+} InterfaceDescriptor;
+
+typedef struct {
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bEndpointAddress;
+ uint8_t bmAttributes;
+ uint16_t wMaxPacketSize;
+ uint8_t bInterval;
+} EndpointDescriptor;
+
+typedef struct {
+ uint8_t bDescLength;
+ uint8_t bDescriptorType;
+ uint8_t bNbrPorts;
+ uint16_t wHubCharacteristics;
+ uint8_t bPwrOn2PwrGood;
+ uint8_t bHubContrCurrent;
+ uint8_t DeviceRemovable;
+ uint8_t PortPweCtrlMak;
+} HubDescriptor;
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/dbg.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/dbg.h
new file mode 100644
index 000000000..33deb4843
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/dbg.h
@@ -0,0 +1,66 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USB_DEBUG_H
+#define USB_DEBUG_H
+
+//Debug is disabled by default
+#define DEBUG 3 /*INFO,ERR,WARN*/
+#define DEBUG_TRANSFER 0
+#define DEBUG_EP_STATE 0
+#define DEBUG_EVENT 0
+
+#if (DEBUG > 3)
+#define USB_DBG(x, ...) std::printf("[USB_DBG: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_DBG(x, ...)
+#endif
+
+#if (DEBUG > 2)
+#define USB_INFO(x, ...) std::printf("[USB_INFO: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_INFO(x, ...)
+#endif
+
+#if (DEBUG > 1)
+#define USB_WARN(x, ...) std::printf("[USB_WARNING: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_WARN(x, ...)
+#endif
+
+#if (DEBUG > 0)
+#define USB_ERR(x, ...) std::printf("[USB_ERR: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_ERR(x, ...)
+#endif
+
+#if (DEBUG_TRANSFER)
+#define USB_DBG_TRANSFER(x, ...) std::printf("[USB_TRANSFER: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_DBG_TRANSFER(x, ...)
+#endif
+
+#if (DEBUG_EVENT)
+#define USB_DBG_EVENT(x, ...) std::printf("[USB_EVENT: %s:%d]" x "\r\n", __FILE__, __LINE__, ##__VA_ARGS__);
+#else
+#define USB_DBG_EVENT(x, ...)
+#endif
+
+
+#endif
+
+
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/IUSBHostSerial.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/IUSBHostSerial.h
new file mode 100644
index 000000000..5814fdd88
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/IUSBHostSerial.h
@@ -0,0 +1,95 @@
+/* IUSBHostSerial.h */
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef IUSBHOSTSERIAL_H_
+#define IUSBHOSTSERIAL_H_
+
+/**
+ * Generic interface to abstract 3G dongles' impl
+ */
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include "IUSBHostSerialListener.h"
+
+// This is needed by some versions of GCC
+#undef putc
+#undef getc
+
+class IUSBHostSerial {
+public:
+
+ enum IrqType {
+ RxIrq,
+ TxIrq
+ };
+
+ /*
+ * Get a char from the dongle's serial interface
+ */
+ virtual int getc() = 0;
+
+ /*
+ * Put a char to the dongle's serial interface
+ */
+ virtual int putc(int c) = 0;
+
+ /*
+ * Read a packet from the dongle's serial interface, to be called after multiple getc() calls
+ */
+ virtual int readPacket() = 0;
+
+ /*
+ * Write a packet to the dongle's serial interface, to be called after multiple putc() calls
+ */
+ virtual int writePacket() = 0;
+
+ /**
+ * Check the number of bytes available.
+ *
+ * @returns the number of bytes available
+ */
+ virtual int readable() = 0;
+
+ /**
+ * Check the free space in output.
+ *
+ * @returns the number of bytes available
+ */
+ virtual int writeable() = 0;
+
+ /**
+ * Attach a handler to call when a packet is received / when a packet has been transmitted.
+ *
+ * @param pListener instance of the listener deriving from the IUSBHostSerialListener
+ */
+ virtual void attach(IUSBHostSerialListener* pListener) = 0;
+
+ /**
+ * Enable or disable readable/writeable callbacks
+ */
+ virtual void setupIrq(bool en, IrqType irq = RxIrq) = 0;
+
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif /* IUSBHOSTSERIAL_H_ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/IUSBHostSerialListener.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/IUSBHostSerialListener.h
new file mode 100644
index 000000000..525b73463
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/IUSBHostSerialListener.h
@@ -0,0 +1,37 @@
+/* IUSBHostSerialListener.h */
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+
+#ifndef IUSBHOSTSERIALLISTENER_H_
+#define IUSBHOSTSERIALLISTENER_H_
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+class IUSBHostSerialListener
+{
+public:
+ virtual void readable() = 0; //Called when new data is available
+ virtual void writeable() = 0; //Called when new space is available
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif /* IUSBHOSTSERIALLISTENER_H_ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongle.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongle.cpp
new file mode 100644
index 000000000..49cafb7cc
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongle.cpp
@@ -0,0 +1,235 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include "dbg.h"
+#include <stdint.h>
+#include "rtos.h"
+
+#include "WANDongle.h"
+#include "WANDongleInitializer.h"
+
+WANDongle::WANDongle() : m_pInitializer(NULL), m_serialCount(0), m_totalInitializers(0)
+{
+ host = USBHost::getHostInst();
+ init();
+}
+
+
+bool WANDongle::connected() {
+ return dev_connected;
+}
+
+bool WANDongle::tryConnect()
+{
+ //FIXME should run on USB thread
+
+ USB_DBG("Trying to connect device");
+
+ if (dev_connected) {
+ USB_DBG("Device is already connected!");
+ return true;
+ }
+
+ m_pInitializer = NULL;
+
+ //Protect from concurrent access from USB thread
+ USBHost::Lock lock(host);
+
+ for (int i = 0; i < MAX_DEVICE_CONNECTED; i++)
+ {
+ if ((dev = host->getDevice(i)) != NULL)
+ {
+ m_pInitializer = NULL; //Will be set in setVidPid callback
+
+ USB_DBG("Enumerate");
+ int ret = host->enumerate(dev, this);
+ if(ret)
+ {
+ return false;
+ }
+
+ USB_DBG("Device has VID:%04x PID:%04x", dev->getVid(), dev->getPid());
+
+ if(m_pInitializer) //If an initializer has been found
+ {
+ USB_DBG("m_pInitializer=%p", m_pInitializer);
+ USB_DBG("m_pInitializer->getSerialVid()=%04x", m_pInitializer->getSerialVid());
+ USB_DBG("m_pInitializer->getSerialPid()=%04x", m_pInitializer->getSerialPid());
+ if ((dev->getVid() == m_pInitializer->getSerialVid()) && (dev->getPid() == m_pInitializer->getSerialPid()))
+ {
+ USB_DBG("The dongle is in virtual serial mode");
+ host->registerDriver(dev, 0, this, &WANDongle::init);
+ m_serialCount = m_pInitializer->getSerialPortCount();
+ if( m_serialCount > WANDONGLE_MAX_SERIAL_PORTS )
+ {
+ m_serialCount = WANDONGLE_MAX_SERIAL_PORTS;
+ }
+ for(int j = 0; j < m_serialCount; j++)
+ {
+ USB_DBG("Connecting serial port #%d", j+1);
+ USB_DBG("Ep %p", m_pInitializer->getEp(dev, j, false));
+ USB_DBG("Ep %p", m_pInitializer->getEp(dev, j, true));
+ m_serial[j].connect( dev, m_pInitializer->getEp(dev, j, false), m_pInitializer->getEp(dev, j, true) );
+ }
+
+ USB_DBG("Device connected");
+
+ dev_connected = true;
+
+
+ return true;
+ }
+ else if ((dev->getVid() == m_pInitializer->getMSDVid()) && (dev->getPid() == m_pInitializer->getMSDPid()))
+ {
+ USB_DBG("Vodafone K3370 dongle detected in MSD mode");
+ //Try to switch
+ if( m_pInitializer->switchMode(dev) )
+ {
+ USB_DBG("Switched OK");
+ return false; //Will be connected on a next iteration
+ }
+ else
+ {
+ USB_ERR("Could not switch mode");
+ return false;
+ }
+ }
+ } //if()
+ } //if()
+ } //for()
+ return false;
+}
+
+bool WANDongle::disconnect()
+{
+ dev_connected = false;
+ for(int i = 0; i < WANDONGLE_MAX_SERIAL_PORTS; i++)
+ {
+ m_serial[i].disconnect();
+ }
+ return true;
+}
+
+int WANDongle::getDongleType()
+{
+ if( m_pInitializer != NULL )
+ {
+ return m_pInitializer->getType();
+ }
+ else
+ {
+ return WAN_DONGLE_TYPE_UNKNOWN;
+ }
+}
+
+IUSBHostSerial& WANDongle::getSerial(int index)
+{
+ return m_serial[index];
+}
+
+int WANDongle::getSerialCount()
+{
+ return m_serialCount;
+}
+
+//Private methods
+void WANDongle::init()
+{
+ m_pInitializer = NULL;
+ dev_connected = false;
+ for(int i = 0; i < WANDONGLE_MAX_SERIAL_PORTS; i++)
+ {
+ m_serial[i].init(host);
+ }
+}
+
+
+/*virtual*/ void WANDongle::setVidPid(uint16_t vid, uint16_t pid)
+{
+ WANDongleInitializer* initializer;
+
+ for(int i = 0; i < m_totalInitializers; i++)
+ {
+ initializer = m_Initializers[i];
+ USB_DBG("initializer=%p", initializer);
+ USB_DBG("initializer->getSerialVid()=%04x", initializer->getSerialVid());
+ USB_DBG("initializer->getSerialPid()=%04x", initializer->getSerialPid());
+ if ((dev->getVid() == initializer->getSerialVid()) && (dev->getPid() == initializer->getSerialPid()))
+ {
+ USB_DBG("The dongle is in virtual serial mode");
+ m_pInitializer = initializer;
+ break;
+ }
+ else if ((dev->getVid() == initializer->getMSDVid()) && (dev->getPid() == initializer->getMSDPid()))
+ {
+ USB_DBG("Dongle detected in MSD mode");
+ m_pInitializer = initializer;
+ break;
+ }
+ initializer++;
+ } //for
+ if(m_pInitializer)
+ {
+ m_pInitializer->setVidPid(vid, pid);
+ }
+}
+
+/*virtual*/ bool WANDongle::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ if(m_pInitializer)
+ {
+ return m_pInitializer->parseInterface(intf_nb, intf_class, intf_subclass, intf_protocol);
+ }
+ else
+ {
+ return false;
+ }
+}
+
+/*virtual*/ bool WANDongle::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if(m_pInitializer)
+ {
+ return m_pInitializer->useEndpoint(intf_nb, type, dir);
+ }
+ else
+ {
+ return false;
+ }
+}
+
+
+bool WANDongle::addInitializer(WANDongleInitializer* pInitializer)
+{
+ if (m_totalInitializers >= WANDONGLE_MAX_INITIALIZERS)
+ return false;
+ m_Initializers[m_totalInitializers++] = pInitializer;
+ return true;
+}
+
+WANDongle::~WANDongle()
+{
+ for(int i = 0; i < m_totalInitializers; i++)
+ delete m_Initializers[i];
+}
+
+#endif /* USBHOST_3GMODULE */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongle.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongle.h
new file mode 100644
index 000000000..960b8bcfb
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongle.h
@@ -0,0 +1,108 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef WANDONGLE_H
+#define WANDONGLE_H
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include "USBHost.h"
+#include "IUSBHostSerial.h"
+
+#include "rtos.h"
+
+#include "WANDongleSerialPort.h"
+#include "WANDongleInitializer.h"
+#include "IUSBEnumerator.h"
+
+#define WANDONGLE_MAX_OUTEP_SIZE 64
+#define WANDONGLE_MAX_INEP_SIZE 64
+
+/** A class to use a WAN (3G/LTE) access dongle
+ *
+ */
+class WANDongle : public IUSBEnumerator {
+public:
+ /*
+ * Constructor
+ *
+ * @param rootdir mount name
+ */
+ WANDongle();
+
+ /*
+ * Destructor
+ */
+ virtual ~WANDongle();
+
+ /*
+ * Check if a serial port device is connected
+ *
+ * @return true if a serial device is connected
+ */
+ bool connected();
+
+ /*
+ * Try to connect device
+ *
+ * * @return true if connection was successful
+ */
+ bool tryConnect();
+
+ /*
+ * Disconnect device
+ *
+ * * @return true if disconnection was successful
+ */
+ bool disconnect();
+
+ int getDongleType();
+
+ IUSBHostSerial& getSerial(int index);
+ int getSerialCount();
+ bool addInitializer(WANDongleInitializer* pInitializer);
+
+ //From IUSBEnumerator
+
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+protected:
+ USBHost * host;
+ USBDeviceConnected * dev;
+ bool dev_connected;
+
+ WANDongleInitializer* m_pInitializer;
+
+ void init();
+
+ WANDongleSerialPort m_serial[WANDONGLE_MAX_SERIAL_PORTS];
+ int m_serialCount;
+
+ int m_totalInitializers;
+ WANDongleInitializer* m_Initializers[WANDONGLE_MAX_INITIALIZERS];
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleInitializer.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleInitializer.h
new file mode 100644
index 000000000..2f0a4a37c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleInitializer.h
@@ -0,0 +1,73 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef WANDONGLEINITIALIZER_H
+#define WANDONGLEINITIALIZER_H
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include <stdint.h>
+
+#include "USBHost.h"
+#include "IUSBEnumerator.h"
+
+// [TODO] move these declarations to a proper place
+#define WANDONGLE_MAX_SERIAL_PORTS 2
+#define WANDONGLE_MAX_INITIALIZERS 6
+
+#define WAN_DONGLE_TYPE_UNKNOWN (-1)
+
+class WANDongleInitializer : public IUSBEnumerator
+{
+protected:
+ WANDongleInitializer(USBHost* pHost) { m_pHost = pHost; }
+ USBHost* m_pHost;
+ uint8_t m_serialIntfMap[WANDONGLE_MAX_SERIAL_PORTS];
+
+public:
+ virtual ~WANDongleInitializer() {}
+ virtual uint16_t getMSDVid() = 0;
+ virtual uint16_t getMSDPid() = 0;
+
+ virtual uint16_t getSerialVid() = 0;
+ virtual uint16_t getSerialPid() = 0;
+
+ virtual bool switchMode(USBDeviceConnected* pDev) = 0;
+
+ virtual USBEndpoint* getEp(USBDeviceConnected* pDev, int serialPortNumber, bool tx) {
+ return pDev->getEndpoint(m_serialIntfMap[serialPortNumber], BULK_ENDPOINT, tx ? OUT : IN, 0);
+ }
+
+ virtual int getSerialPortCount() = 0;
+
+ virtual void setVidPid(uint16_t vid, uint16_t pid) = 0;
+
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) = 0; //Must return true if the interface should be parsed
+
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) = 0; //Must return true if the endpoint will be used
+
+ virtual int getType() = 0;
+
+ virtual uint8_t getSerialIntf(int index) { return m_serialIntfMap[index]; }
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleSerialPort.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleSerialPort.cpp
new file mode 100644
index 000000000..96343f15c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleSerialPort.cpp
@@ -0,0 +1,340 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#define __DEBUG__ 0
+#ifndef __MODULE__
+#define __MODULE__ "WANDongleSerialPort.cpp"
+#endif
+
+#include "dbg.h"
+#include <stdint.h>
+#include "rtos.h"
+
+#include "WANDongleSerialPort.h"
+
+WANDongleSerialPort::WANDongleSerialPort() : cb_tx_en(false), cb_rx_en(false), listener(NULL)
+{
+ reset();
+}
+
+void WANDongleSerialPort::init(USBHost* pHost)
+{
+ host = pHost;
+}
+
+void WANDongleSerialPort::reset()
+{
+ tx_mtx.lock();
+ rx_mtx.lock();
+
+ bulk_in = NULL;
+ bulk_out = NULL;
+
+ buf_out_len = 0;
+ max_out_size = 0;
+ lock_tx = false;
+ cb_tx_pending = false;
+
+ buf_in_len = 0;
+ buf_in_read_pos = 0;
+ lock_rx = false;
+ cb_rx_pending = false;
+
+ tx_mtx.unlock();
+ rx_mtx.unlock();
+}
+
+int WANDongleSerialPort::readPacket()
+{
+ USB_DBG("Read packet on %p", this);
+ rx_mtx.lock();
+ if(lock_rx)
+ {
+ USB_ERR("Fail");
+ rx_mtx.unlock();
+ return -1;
+ }
+
+ if( bulk_in == NULL )
+ {
+ USB_WARN("Port is disconnected");
+ rx_mtx.unlock();
+ return -1;
+ }
+
+ lock_rx = true; //Receiving
+ rx_mtx.unlock();
+// USB_DBG("readPacket");
+ //lock_rx.lock();
+ USB_TYPE res = host->bulkRead(dev, (USBEndpoint *)bulk_in, buf_in, ((USBEndpoint *)bulk_in)->getSize(), false); //Queue transfer
+ if(res != USB_TYPE_PROCESSING)
+ {
+ //lock_rx.unlock();
+ USB_ERR("host->bulkRead() returned %d", res);
+ Thread::wait(100);
+ return -1;
+ }
+ return 0;
+}
+
+int WANDongleSerialPort::writePacket()
+{
+ tx_mtx.lock();
+ if(lock_tx)
+ {
+ USB_ERR("Fail");
+ tx_mtx.unlock();
+ return -1;
+ }
+
+ if( bulk_out == NULL )
+ {
+ USB_WARN("Port is disconnected");
+ tx_mtx.unlock();
+ return -1;
+ }
+
+ lock_tx = true; //Transmitting
+ tx_mtx.unlock();
+// USB_DBG("writePacket");
+
+ //lock_tx.lock();
+ USB_TYPE res = host->bulkWrite(dev, (USBEndpoint *)bulk_out, buf_out, buf_out_len, false); //Queue transfer
+ if(res != USB_TYPE_PROCESSING)
+ {
+ //lock_tx.unlock();
+ USB_ERR("host->bulkWrite() returned %d", res);
+ Thread::wait(100);
+ return -1;
+ }
+ return 0;
+}
+
+int WANDongleSerialPort::putc(int c)
+{
+ tx_mtx.lock();
+ if(!lock_tx)
+ {
+ if(buf_out_len < max_out_size)
+ {
+ buf_out[buf_out_len] = (uint8_t)c;
+ buf_out_len++;
+ }
+ }
+ else
+ {
+ USB_ERR("CAN'T WRITE!");
+ }
+ tx_mtx.unlock();
+ return c;
+}
+
+int WANDongleSerialPort::getc()
+{
+ rx_mtx.lock();
+ int c = 0;
+ if(!lock_rx)
+ {
+ if(buf_in_read_pos < buf_in_len)
+ {
+ c = (int)buf_in[buf_in_read_pos];
+ buf_in_read_pos++;
+ }
+ }
+ else
+ {
+ USB_ERR("CAN'T READ!");
+ }
+ rx_mtx.unlock();
+ return c;
+}
+
+int WANDongleSerialPort::readable()
+{
+ rx_mtx.lock();
+ if (lock_rx)
+ {
+ rx_mtx.unlock();
+ return 0;
+ }
+
+ /* if( !lock_rx.trylock() )
+ {
+ return 0;
+ }*/
+ int res = buf_in_len - buf_in_read_pos;
+ //lock_rx.unlock();
+ rx_mtx.unlock();
+ return res;
+}
+
+int WANDongleSerialPort::writeable()
+{
+ tx_mtx.lock();
+ if (lock_tx)
+ {
+ tx_mtx.unlock();
+ return 0;
+ }
+
+ /*if( !lock_tx.trylock() )
+ {
+ return 0;
+ }*/
+ int res = max_out_size - buf_out_len;
+ tx_mtx.unlock();
+ //lock_tx.unlock();
+ return res;
+}
+
+void WANDongleSerialPort::attach(IUSBHostSerialListener* pListener)
+{
+ if(pListener == NULL)
+ {
+ setupIrq(false, RxIrq);
+ setupIrq(false, TxIrq);
+ }
+ listener = pListener;
+ if(pListener != NULL)
+ {
+ setupIrq(true, RxIrq);
+ setupIrq(true, TxIrq);
+ }
+}
+
+void WANDongleSerialPort::setupIrq(bool en, IrqType irq /*= RxIrq*/)
+{
+ switch(irq)
+ {
+ case RxIrq:
+ rx_mtx.lock();
+ cb_rx_en = en;
+ if(en && cb_rx_pending)
+ {
+ cb_rx_pending = false;
+ rx_mtx.unlock();
+ listener->readable(); //Process the interrupt that was raised
+ }
+ else
+ {
+ rx_mtx.unlock();
+ }
+ break;
+ case TxIrq:
+ tx_mtx.lock();
+ cb_tx_en = en;
+ if(en && cb_tx_pending)
+ {
+ cb_tx_pending = false;
+ tx_mtx.unlock();
+ listener->writeable(); //Process the interrupt that was raised
+ }
+ else
+ {
+ tx_mtx.unlock();
+ }
+ break;
+ }
+}
+
+
+void WANDongleSerialPort::connect( USBDeviceConnected* pDev, USBEndpoint* pInEp, USBEndpoint* pOutEp )
+{
+ dev = pDev;
+ bulk_in = pInEp;
+ bulk_out = pOutEp;
+ max_out_size = bulk_out->getSize();
+ if( max_out_size > WANDONGLE_MAX_OUTEP_SIZE )
+ {
+ max_out_size = WANDONGLE_MAX_OUTEP_SIZE;
+ }
+ bulk_in->attach(this, &WANDongleSerialPort::rxHandler);
+ bulk_out->attach(this, &WANDongleSerialPort::txHandler);
+ readPacket(); //Start receiving data
+}
+
+void WANDongleSerialPort::disconnect( )
+{
+ reset();
+}
+
+//Private methods
+
+
+void WANDongleSerialPort::rxHandler()
+{
+ if (((USBEndpoint *) bulk_in)->getState() == USB_TYPE_IDLE) //Success
+ {
+ buf_in_read_pos = 0;
+ buf_in_len = ((USBEndpoint *) bulk_in)->getLengthTransferred(); //Update length
+ //lock_rx.unlock();
+ rx_mtx.lock();
+ lock_rx = false; //Transmission complete
+ if(cb_rx_en)
+ {
+ rx_mtx.unlock();
+ listener->readable(); //Call handler from the IRQ context
+ //readPacket() should be called by the handler subsequently once the buffer has been emptied
+ }
+ else
+ {
+ cb_rx_pending = true; //Queue the callback
+ rx_mtx.unlock();
+ }
+
+ }
+ else //Error, try reading again
+ {
+ //lock_rx.unlock();
+ USB_DBG("Trying again");
+ readPacket();
+ }
+}
+
+void WANDongleSerialPort::txHandler()
+{
+ if (((USBEndpoint *) bulk_out)->getState() == USB_TYPE_IDLE) //Success
+ {
+ tx_mtx.lock();
+ buf_out_len = 0; //Reset length
+ lock_tx = false; //Transmission complete
+ //lock_tx.unlock();
+ if(cb_tx_en)
+ {
+ tx_mtx.unlock();
+ listener->writeable(); //Call handler from the IRQ context
+ //writePacket() should be called by the handler subsequently once the buffer has been filled
+ }
+ else
+ {
+ cb_tx_pending = true; //Queue the callback
+ tx_mtx.unlock();
+ }
+ }
+ else //Error, try reading again
+ {
+ //lock_tx.unlock();
+ writePacket();
+ }
+}
+
+#endif /* USBHOST_3GMODULE */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleSerialPort.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleSerialPort.h
new file mode 100644
index 000000000..7c79d1734
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost3GModule/WANDongleSerialPort.h
@@ -0,0 +1,133 @@
+/* Copyright (c) 2010-2012 mbed.org, MIT License
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+* and associated documentation files (the "Software"), to deal in the Software without
+* restriction, including without limitation the rights to use, copy, modify, merge, publish,
+* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in all copies or
+* substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*/
+
+#ifndef WANDONGLESERIALPORT_H
+#define WANDONGLESERIALPORT_H
+
+#include "USBHostConf.h"
+
+#ifdef USBHOST_3GMODULE
+
+#include "USBHost.h"
+#include "IUSBHostSerial.h"
+
+#include "rtos.h"
+
+
+#define WANDONGLE_MAX_OUTEP_SIZE 64
+#define WANDONGLE_MAX_INEP_SIZE 64
+
+/** A class to use a WAN (3G/LTE) access dongle
+ *
+ */
+class WANDongleSerialPort : public IUSBHostSerial {
+public:
+ /*
+ * Constructor
+ *
+ */
+ WANDongleSerialPort();
+
+ void init( USBHost* pHost );
+
+ void connect( USBDeviceConnected* pDev, USBEndpoint* pInEp, USBEndpoint* pOutEp );
+
+ void disconnect( );
+
+ /*
+ * Get a char from the dongle's serial interface
+ */
+ virtual int getc();
+
+ /*
+ * Put a char to the dongle's serial interface
+ */
+ virtual int putc(int c);
+
+ /*
+ * Read a packet from the dongle's serial interface, to be called after multiple getc() calls
+ */
+ virtual int readPacket();
+
+ /*
+ * Write a packet to the dongle's serial interface, to be called after multiple putc() calls
+ */
+ virtual int writePacket();
+
+ /**
+ * Check the number of bytes available.
+ *
+ * @returns the number of bytes available
+ */
+ virtual int readable();
+
+ /**
+ * Check the free space in output.
+ *
+ * @returns the number of bytes available
+ */
+ virtual int writeable();
+
+ /**
+ * Attach a handler to call when a packet is received / when a packet has been transmitted.
+ *
+ * @param pListener instance of the listener deriving from the IUSBHostSerialListener
+ */
+ virtual void attach(IUSBHostSerialListener* pListener);
+
+ /**
+ * Enable or disable readable/writeable callbacks
+ */
+ virtual void setupIrq(bool en, IrqType irq = RxIrq);
+
+
+protected:
+ USBEndpoint * bulk_in;
+ USBEndpoint * bulk_out;
+ USBHost * host;
+ USBDeviceConnected * dev;
+
+ uint8_t buf_out[WANDONGLE_MAX_OUTEP_SIZE];
+ volatile uint32_t buf_out_len;
+ uint32_t max_out_size;
+ volatile bool lock_tx;
+ volatile bool cb_tx_en;
+ volatile bool cb_tx_pending;
+ Mutex tx_mtx;
+
+ uint8_t buf_in[WANDONGLE_MAX_INEP_SIZE];
+ volatile uint32_t buf_in_len;
+ volatile uint32_t buf_in_read_pos;
+ volatile bool lock_rx;
+ volatile bool cb_rx_en;
+ volatile bool cb_rx_pending;
+ Mutex rx_mtx;
+
+ IUSBHostSerialListener* listener;
+
+ void reset();
+
+ void rxHandler();
+ void txHandler();
+
+};
+
+#endif /* USBHOST_3GMODULE */
+
+#endif
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostKeyboard.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostKeyboard.cpp
new file mode 100644
index 000000000..dbb2cda53
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostKeyboard.cpp
@@ -0,0 +1,184 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBHostKeyboard.h"
+
+#if USBHOST_KEYBOARD
+
+static uint8_t keymap[4][0x39] = {
+ { 0, 0, 0, 0, 'a', 'b' /*0x05*/,
+ 'c', 'd', 'e', 'f', 'g' /*0x0a*/,
+ 'h', 'i', 'j', 'k', 'l'/*0x0f*/,
+ 'm', 'n', 'o', 'p', 'q'/*0x14*/,
+ 'r', 's', 't', 'u', 'v'/*0x19*/,
+ 'w', 'x', 'y', 'z', '1'/*0x1E*/,
+ '2', '3', '4', '5', '6'/*0x23*/,
+ '7', '8', '9', '0', 0x0A /*enter*/, /*0x28*/
+ 0x1B /*escape*/, 0x08 /*backspace*/, 0x09/*tab*/, 0x20/*space*/, '-', /*0x2d*/
+ '=', '[', ']', '\\', '#', /*0x32*/
+ ';', '\'', 0, ',', '.', /*0x37*/
+ '/'},
+
+ /* CTRL MODIFIER */
+ { 0, 0, 0, 0, 0, 0 /*0x05*/,
+ 0, 0, 0, 0, 0 /*0x0a*/,
+ 0, 0, 0, 0, 0/*0x0f*/,
+ 0, 0, 0, 0, 0/*0x14*/,
+ 0, 0, 0, 0, 0/*0x19*/,
+ 0, 0, 0, 0, 0/*0x1E*/,
+ 0, 0, 0, 0, 0/*0x23*/,
+ 0, 0, 0, 0, 0 /*enter*/, /*0x28*/
+ 0, 0, 0, 0, 0, /*0x2d*/
+ 0, 0, 0, 0, 0, /*0x32*/
+ 0, 0, 0, 0, 0, /*0x37*/
+ 0},
+
+ /* SHIFT MODIFIER */
+ { 0, 0, 0, 0, 'A', 'B' /*0x05*/,
+ 'C', 'D', 'E', 'F', 'G' /*0x0a*/,
+ 'H', 'I', 'J', 'K', 'L'/*0x0f*/,
+ 'M', 'N', 'O', 'P', 'Q'/*0x14*/,
+ 'R', 'S', 'T', 'U', 'V'/*0x19*/,
+ 'W', 'X', 'Y', 'Z', '!'/*0x1E*/,
+ '@', '#', '$', '%', '^'/*0x23*/,
+ '&', '*', '(', ')', 0, /*0x28*/
+ 0, 0, 0, 0, 0, /*0x2d*/
+ '+', '{', '}', '|', '~', /*0x32*/
+ ':', '"', 0, '<', '>', /*0x37*/
+ '?'},
+
+ /* ALT MODIFIER */
+ { 0, 0, 0, 0, 0, 0 /*0x05*/,
+ 0, 0, 0, 0, 0 /*0x0a*/,
+ 0, 0, 0, 0, 0/*0x0f*/,
+ 0, 0, 0, 0, 0/*0x14*/,
+ 0, 0, 0, 0, 0/*0x19*/,
+ 0, 0, 0, 0, 0/*0x1E*/,
+ 0, 0, 0, 0, 0/*0x23*/,
+ 0, 0, 0, 0, 0 /*enter*/, /*0x28*/
+ 0, 0, 0, 0, 0, /*0x2d*/
+ 0, 0, 0, 0, 0, /*0x32*/
+ 0, 0, 0, 0, 0, /*0x37*/
+ 0}
+
+};
+
+
+USBHostKeyboard::USBHostKeyboard() {
+ host = USBHost::getHostInst();
+ init();
+}
+
+
+void USBHostKeyboard::init() {
+ dev = NULL;
+ int_in = NULL;
+ report_id = 0;
+ onKey = NULL;
+ onKeyCode = NULL;
+ dev_connected = false;
+ keyboard_intf = -1;
+ keyboard_device_found = false;
+}
+
+bool USBHostKeyboard::connected() {
+ return dev_connected;
+}
+
+
+bool USBHostKeyboard::connect() {
+
+ if (dev_connected) {
+ return true;
+ }
+
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ if ((dev = host->getDevice(i)) != NULL) {
+
+ if (host->enumerate(dev, this))
+ break;
+
+ if (keyboard_device_found) {
+ int_in = dev->getEndpoint(keyboard_intf, INTERRUPT_ENDPOINT, IN);
+
+ if (!int_in)
+ break;
+
+ USB_INFO("New Keyboard device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, keyboard_intf);
+ dev->setName("Keyboard", keyboard_intf);
+ host->registerDriver(dev, keyboard_intf, this, &USBHostKeyboard::init);
+
+ int_in->attach(this, &USBHostKeyboard::rxHandler);
+ host->interruptRead(dev, int_in, report, int_in->getSize(), false);
+
+ dev_connected = true;
+ return true;
+ }
+ }
+ }
+ init();
+ return false;
+}
+
+void USBHostKeyboard::rxHandler() {
+ int len = int_in->getLengthTransferred();
+ int index = (len == 9) ? 1 : 0;
+ int len_listen = int_in->getSize();
+ uint8_t key = 0;
+ if (len == 8 || len == 9) {
+ uint8_t modifier = (report[index] == 4) ? 3 : report[index];
+ len_listen = len;
+ key = keymap[modifier][report[index + 2]];
+ if (key && onKey) {
+ (*onKey)(key);
+ }
+ if ((report[index + 2] || modifier) && onKeyCode) {
+ (*onKeyCode)(report[index + 2], modifier);
+ }
+ }
+ if (dev && int_in)
+ host->interruptRead(dev, int_in, report, len_listen, false);
+}
+
+/*virtual*/ void USBHostKeyboard::setVidPid(uint16_t vid, uint16_t pid)
+{
+ // we don't check VID/PID for keyboard driver
+}
+
+/*virtual*/ bool USBHostKeyboard::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ if ((keyboard_intf == -1) &&
+ (intf_class == HID_CLASS) &&
+ (intf_subclass == 0x01) &&
+ (intf_protocol == 0x01)) {
+ keyboard_intf = intf_nb;
+ return true;
+ }
+ return false;
+}
+
+/*virtual*/ bool USBHostKeyboard::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if (intf_nb == keyboard_intf) {
+ if (type == INTERRUPT_ENDPOINT && dir == IN) {
+ keyboard_device_found = true;
+ return true;
+ }
+ }
+ return false;
+}
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostKeyboard.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostKeyboard.h
new file mode 100644
index 000000000..93730061c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostKeyboard.h
@@ -0,0 +1,102 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOSTKEYBOARD_H
+#define USBHOSTKEYBOARD_H
+
+#include "USBHostConf.h"
+
+#if USBHOST_KEYBOARD
+
+#include "USBHost.h"
+
+/**
+ * A class to communicate a USB keyboard
+ */
+class USBHostKeyboard : public IUSBEnumerator {
+public:
+
+ /**
+ * Constructor
+ */
+ USBHostKeyboard();
+
+ /**
+ * Try to connect a keyboard device
+ *
+ * @return true if connection was successful
+ */
+ bool connect();
+
+ /**
+ * Check if a keyboard is connected
+ *
+ * @returns true if a keyboard is connected
+ */
+ bool connected();
+
+ /**
+ * Attach a callback called when a keyboard event is received
+ *
+ * @param ptr function pointer
+ */
+ inline void attach(void (*ptr)(uint8_t key)) {
+ if (ptr != NULL) {
+ onKey = ptr;
+ }
+ }
+
+ /**
+ * Attach a callback called when a keyboard event is received
+ *
+ * @param ptr function pointer
+ */
+ inline void attach(void (*ptr)(uint8_t keyCode, uint8_t modifier)) {
+ if (ptr != NULL) {
+ onKeyCode = ptr;
+ }
+ }
+
+protected:
+ //From IUSBEnumerator
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+ USBHost * host;
+ USBDeviceConnected * dev;
+ USBEndpoint * int_in;
+ uint8_t report[9];
+ int keyboard_intf;
+ bool keyboard_device_found;
+
+ bool dev_connected;
+
+ void rxHandler();
+
+ void (*onKey)(uint8_t key);
+ void (*onKeyCode)(uint8_t key, uint8_t modifier);
+
+ int report_id;
+
+ void init();
+
+};
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostMouse.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostMouse.cpp
new file mode 100644
index 000000000..52fcf8c5b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostMouse.cpp
@@ -0,0 +1,153 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBHostMouse.h"
+
+#if USBHOST_MOUSE
+
+USBHostMouse::USBHostMouse() {
+ host = USBHost::getHostInst();
+ init();
+}
+
+void USBHostMouse::init() {
+ dev = NULL;
+ int_in = NULL;
+ onUpdate = NULL;
+ onButtonUpdate = NULL;
+ onXUpdate = NULL;
+ onYUpdate = NULL;
+ onZUpdate = NULL;
+ report_id = 0;
+ dev_connected = false;
+ mouse_device_found = false;
+ mouse_intf = -1;
+
+ buttons = 0;
+ x = 0;
+ y = 0;
+ z = 0;
+}
+
+bool USBHostMouse::connected() {
+ return dev_connected;
+}
+
+bool USBHostMouse::connect() {
+ int len_listen;
+
+ if (dev_connected) {
+ return true;
+ }
+
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ if ((dev = host->getDevice(i)) != NULL) {
+
+ if(host->enumerate(dev, this))
+ break;
+
+ if (mouse_device_found) {
+
+ int_in = dev->getEndpoint(mouse_intf, INTERRUPT_ENDPOINT, IN);
+ if (!int_in)
+ break;
+
+ USB_INFO("New Mouse device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, mouse_intf);
+ dev->setName("Mouse", mouse_intf);
+ host->registerDriver(dev, mouse_intf, this, &USBHostMouse::init);
+
+ int_in->attach(this, &USBHostMouse::rxHandler);
+ len_listen = int_in->getSize();
+ if (len_listen > sizeof(report)) {
+ len_listen = sizeof(report);
+ }
+ host->interruptRead(dev, int_in, report, len_listen, false);
+
+ dev_connected = true;
+ return true;
+ }
+ }
+ }
+ init();
+ return false;
+}
+
+void USBHostMouse::rxHandler() {
+ int len_listen = int_in->getSize();
+
+ if (onUpdate) {
+ (*onUpdate)(report[0] & 0x07, report[1], report[2], report[3]);
+ }
+
+ if (onButtonUpdate && (buttons != (report[0] & 0x07))) {
+ (*onButtonUpdate)(report[0] & 0x07);
+ }
+
+ if (onXUpdate && (x != report[1])) {
+ (*onXUpdate)(report[1]);
+ }
+
+ if (onYUpdate && (y != report[2])) {
+ (*onYUpdate)(report[2]);
+ }
+
+ if (onZUpdate && (z != report[3])) {
+ (*onZUpdate)(report[3]);
+ }
+
+ // update mouse state
+ buttons = report[0] & 0x07;
+ x = report[1];
+ y = report[2];
+ z = report[3];
+
+ if (len_listen > sizeof(report)) {
+ len_listen = sizeof(report);
+ }
+
+ if (dev)
+ host->interruptRead(dev, int_in, report, len_listen, false);
+}
+
+/*virtual*/ void USBHostMouse::setVidPid(uint16_t vid, uint16_t pid)
+{
+ // we don't check VID/PID for mouse driver
+}
+
+/*virtual*/ bool USBHostMouse::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ if ((mouse_intf == -1) &&
+ (intf_class == HID_CLASS) &&
+ (intf_subclass == 0x01) &&
+ (intf_protocol == 0x02)) {
+ mouse_intf = intf_nb;
+ return true;
+ }
+ return false;
+}
+
+/*virtual*/ bool USBHostMouse::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if (intf_nb == mouse_intf) {
+ if (type == INTERRUPT_ENDPOINT && dir == IN) {
+ mouse_device_found = true;
+ return true;
+ }
+ }
+ return false;
+}
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostMouse.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostMouse.h
new file mode 100644
index 000000000..03e099448
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHID/USBHostMouse.h
@@ -0,0 +1,139 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOSTMOUSE_H
+#define USBHOSTMOUSE_H
+
+#include "USBHostConf.h"
+
+#if USBHOST_MOUSE
+
+#include "USBHost.h"
+
+/**
+ * A class to communicate a USB mouse
+ */
+class USBHostMouse : public IUSBEnumerator {
+public:
+
+ /**
+ * Constructor
+ */
+ USBHostMouse();
+
+ /**
+ * Try to connect a mouse device
+ *
+ * @return true if connection was successful
+ */
+ bool connect();
+
+ /**
+ * Check if a mouse is connected
+ *
+ * @returns true if a mouse is connected
+ */
+ bool connected();
+
+ /**
+ * Attach a callback called when a mouse event is received
+ *
+ * @param ptr function pointer
+ */
+ inline void attachEvent(void (*ptr)(uint8_t buttons, int8_t x, int8_t y, int8_t z)) {
+ if (ptr != NULL) {
+ onUpdate = ptr;
+ }
+ }
+
+ /**
+ * Attach a callback called when the button state changes
+ *
+ * @param ptr function pointer
+ */
+ inline void attachButtonEvent(void (*ptr)(uint8_t buttons)) {
+ if (ptr != NULL) {
+ onButtonUpdate = ptr;
+ }
+ }
+
+ /**
+ * Attach a callback called when the X axis value changes
+ *
+ * @param ptr function pointer
+ */
+ inline void attachXEvent(void (*ptr)(int8_t x)) {
+ if (ptr != NULL) {
+ onXUpdate = ptr;
+ }
+ }
+
+ /**
+ * Attach a callback called when the Y axis value changes
+ *
+ * @param ptr function pointer
+ */
+ inline void attachYEvent(void (*ptr)(int8_t y)) {
+ if (ptr != NULL) {
+ onYUpdate = ptr;
+ }
+ }
+
+ /**
+ * Attach a callback called when the Z axis value changes (scrolling)
+ *
+ * @param ptr function pointer
+ */
+ inline void attachZEvent(void (*ptr)(int8_t z)) {
+ if (ptr != NULL) {
+ onZUpdate = ptr;
+ }
+ }
+
+protected:
+ //From IUSBEnumerator
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+ USBHost * host;
+ USBDeviceConnected * dev;
+ USBEndpoint * int_in;
+ uint8_t report[4];
+
+ bool dev_connected;
+ bool mouse_device_found;
+ int mouse_intf;
+
+ uint8_t buttons;
+ int8_t x;
+ int8_t y;
+ int8_t z;
+
+ void rxHandler();
+ void (*onUpdate)(uint8_t buttons, int8_t x, int8_t y, int8_t z);
+ void (*onButtonUpdate)(uint8_t buttons);
+ void (*onXUpdate)(int8_t x);
+ void (*onYUpdate)(int8_t y);
+ void (*onZUpdate)(int8_t z);
+ int report_id;
+ void init();
+};
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHub/USBHostHub.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHub/USBHostHub.cpp
new file mode 100644
index 000000000..75c57f3ea
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHub/USBHostHub.cpp
@@ -0,0 +1,274 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBHostHub.h"
+
+#if MAX_HUB_NB
+
+#include "USBHost.h"
+#include "dbg.h"
+
+#define GET_STATUS 0x00
+#define CLEAR_FEATURE 0x01
+#define GET_STATE 0x02
+#define SET_FEATURE 0x03
+#define GET_DESCRIPTOR 0x06
+
+#define PORT_CONNECTION_FEATURE (0x00)
+#define PORT_ENABLE_FEATURE (0x01)
+#define PORT_RESET_FEATURE (0x04)
+#define PORT_POWER_FEATURE (0x08)
+
+#define C_PORT_CONNECTION_FEATURE (16)
+#define C_PORT_ENABLE_FEATURE (17)
+#define C_PORT_RESET_FEATURE (20)
+
+#define PORT_CONNECTION (1 << 0)
+#define PORT_ENABLE (1 << 1)
+#define PORT_SUSPEND (1 << 2)
+#define PORT_OVER_CURRENT (1 << 3)
+#define PORT_RESET (1 << 4)
+#define PORT_POWER (1 << 8)
+#define PORT_LOW_SPEED (1 << 9)
+
+#define C_PORT_CONNECTION (1 << 16)
+#define C_PORT_ENABLE (1 << 17)
+#define C_PORT_SUSPEND (1 << 18)
+#define C_PORT_OVER_CURRENT (1 << 19)
+#define C_PORT_RESET (1 << 20)
+
+USBHostHub::USBHostHub() {
+ host = NULL;
+ init();
+}
+
+void USBHostHub::init() {
+ dev_connected = false;
+ dev = NULL;
+ int_in = NULL;
+ dev_connected = false;
+ hub_intf = -1;
+ hub_device_found = false;
+ nb_port = 0;
+ hub_characteristics = 0;
+
+ for (int i = 0; i < MAX_HUB_PORT; i++) {
+ device_children[i] = NULL;
+ }
+}
+
+void USBHostHub::setHost(USBHost * host_) {
+ host = host_;
+}
+
+bool USBHostHub::connected()
+{
+ return dev_connected;
+}
+
+bool USBHostHub::connect(USBDeviceConnected * dev)
+{
+ if (dev_connected) {
+ return true;
+ }
+
+ if(host->enumerate(dev, this)) {
+ init();
+ return false;
+ }
+
+ if (hub_device_found) {
+ this->dev = dev;
+
+ int_in = dev->getEndpoint(hub_intf, INTERRUPT_ENDPOINT, IN);
+
+ if (!int_in) {
+ init();
+ return false;
+ }
+
+ USB_INFO("New HUB: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, hub_intf);
+ dev->setName("Hub", hub_intf);
+ host->registerDriver(dev, hub_intf, this, &USBHostHub::disconnect);
+
+ int_in->attach(this, &USBHostHub::rxHandler);
+
+ // get HUB descriptor
+ host->controlRead( dev,
+ USB_DEVICE_TO_HOST | USB_REQUEST_TYPE_CLASS,
+ GET_DESCRIPTOR,
+ 0x29 << 8, 0, buf, sizeof(HubDescriptor));
+ nb_port = buf[2];
+ hub_characteristics = buf[3];
+
+ USB_DBG("Hub has %d port", nb_port);
+
+ for (uint8_t j = 1; j <= nb_port; j++) {
+ setPortFeature(PORT_POWER_FEATURE, j);
+ }
+ wait_ms(buf[5]*2);
+
+ host->interruptRead(dev, int_in, buf, 1, false);
+ dev_connected = true;
+ return true;
+ }
+
+ return false;
+}
+
+void USBHostHub::disconnect() {
+ init();
+}
+
+/*virtual*/ void USBHostHub::setVidPid(uint16_t vid, uint16_t pid)
+{
+ // we don't check VID/PID for MSD driver
+}
+
+/*virtual*/ bool USBHostHub::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ if ((hub_intf == -1) &&
+ (intf_class == HUB_CLASS) &&
+ (intf_subclass == 0) &&
+ (intf_protocol == 0)) {
+ hub_intf = intf_nb;
+ return true;
+ }
+ return false;
+}
+
+/*virtual*/ bool USBHostHub::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if (intf_nb == hub_intf) {
+ if ((type == INTERRUPT_ENDPOINT) && (dir == IN)) {
+ hub_device_found = true;
+ return true;
+ }
+ }
+ return false;
+}
+
+void USBHostHub::deviceConnected(USBDeviceConnected * dev) {
+ device_children[dev->getPort() - 1] = dev;
+}
+
+void USBHostHub::deviceDisconnected(USBDeviceConnected * dev) {
+ device_children[dev->getPort() - 1] = NULL;
+}
+
+void USBHostHub::hubDisconnected() {
+ for (uint8_t i = 0; i < MAX_HUB_PORT; i++) {
+ if (device_children[i] != NULL) {
+ host->freeDevice(device_children[i]);
+ }
+ }
+}
+
+void USBHostHub::rxHandler() {
+ uint32_t status;
+ if (int_in) {
+ if (int_in->getState() == USB_TYPE_IDLE) {
+ for (int port = 1; port <= nb_port; port++) {
+ status = getPortStatus(port);
+ USB_DBG("[hub handler hub: %d] status port %d [hub: %p]: 0x%X", dev->getHub(), port, dev, status);
+
+ // if connection status has changed
+ if (status & C_PORT_CONNECTION) {
+ if (status & PORT_CONNECTION) {
+ USB_DBG("[hub handler hub: %d - port: %d] new device connected", dev->getHub(), port);
+ host->deviceConnected(dev->getHub() + 1, port, status & PORT_LOW_SPEED, this);
+ } else {
+ USB_DBG("[hub handler hub: %d - port: %d] device disconnected", dev->getHub(), port);
+ host->deviceDisconnected(dev->getHub() + 1, port, this, 0);
+ }
+
+ clearPortFeature(C_PORT_CONNECTION_FEATURE, port);
+ }
+
+ if (status & C_PORT_RESET) {
+ clearPortFeature(C_PORT_RESET_FEATURE, port);
+ }
+
+ if (status & C_PORT_ENABLE) {
+ clearPortFeature(C_PORT_ENABLE_FEATURE, port);
+ }
+
+ if ((status & PORT_OVER_CURRENT)) {
+ USB_ERR("OVER CURRENT DETECTED\r\n");
+ clearPortFeature(PORT_OVER_CURRENT, port);
+ host->deviceDisconnected(dev->getHub() + 1, port, this, 0);
+ }
+ }
+ }
+ host->interruptRead(dev, int_in, buf, 1, false);
+ }
+}
+
+void USBHostHub::portReset(uint8_t port) {
+ // reset port
+ uint32_t status;
+ USB_DBG("reset port %d on hub: %p [this: %p]", port, dev, this)
+ setPortFeature(PORT_RESET_FEATURE, port);
+#if defined(TARGET_RZ_A1H)
+ Thread::wait(50); // Reset release waiting for Hi-Speed check.
+#endif
+ while(1) {
+ status = getPortStatus(port);
+ if (status & (PORT_ENABLE | PORT_RESET))
+ break;
+ if (status & PORT_OVER_CURRENT) {
+ USB_ERR("OVER CURRENT DETECTED\r\n");
+ clearPortFeature(PORT_OVER_CURRENT, port);
+ host->deviceDisconnected(dev->getHub() + 1, port, this, 0);
+ break;
+ }
+ Thread::wait(10);
+ }
+}
+
+void USBHostHub::setPortFeature(uint32_t feature, uint8_t port) {
+ host->controlWrite( dev,
+ USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_CLASS | USB_RECIPIENT_INTERFACE | USB_RECIPIENT_ENDPOINT,
+ SET_FEATURE,
+ feature,
+ port,
+ NULL,
+ 0);
+}
+
+void USBHostHub::clearPortFeature(uint32_t feature, uint8_t port) {
+ host->controlWrite( dev,
+ USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_CLASS | USB_RECIPIENT_INTERFACE | USB_RECIPIENT_ENDPOINT,
+ CLEAR_FEATURE,
+ feature,
+ port,
+ NULL,
+ 0);
+}
+
+uint32_t USBHostHub::getPortStatus(uint8_t port) {
+ uint32_t st;
+ host->controlRead( dev,
+ USB_DEVICE_TO_HOST | USB_REQUEST_TYPE_CLASS | USB_RECIPIENT_INTERFACE | USB_RECIPIENT_ENDPOINT,
+ GET_STATUS,
+ 0,
+ port,
+ (uint8_t *)&st,
+ 4);
+ return st;
+}
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHub/USBHostHub.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHub/USBHostHub.h
new file mode 100644
index 000000000..e199c369e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostHub/USBHostHub.h
@@ -0,0 +1,125 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOSTHUB_H
+#define USBHOSTHUB_H
+
+#include "USBHostConf.h"
+
+#if MAX_HUB_NB
+
+#include "USBHostTypes.h"
+#include "IUSBEnumerator.h"
+
+class USBHost;
+class USBDeviceConnected;
+class USBEndpoint;
+
+/**
+ * A class to use a USB Hub
+ */
+class USBHostHub : public IUSBEnumerator {
+public:
+ /**
+ * Constructor
+ */
+ USBHostHub();
+
+ /**
+ * Check if a USB Hub is connected
+ *
+ * @return true if a serial device is connected
+ */
+ bool connected();
+
+ /**
+ * Try to connect device
+ *
+ * @param dev device to connect
+ * @return true if connection was successful
+ */
+ bool connect(USBDeviceConnected * dev);
+
+ /**
+ * Automatically called by USBHost when a device
+ * has been enumerated by usb_thread
+ *
+ * @param dev device connected
+ */
+ void deviceConnected(USBDeviceConnected * dev);
+
+ /**
+ * Automatically called by USBHost when a device
+ * has been disconnected from this hub
+ *
+ * @param dev device disconnected
+ */
+ void deviceDisconnected(USBDeviceConnected * dev);
+
+ /**
+ * Rest a specific port
+ *
+ * @param port port number
+ */
+ void portReset(uint8_t port);
+
+ /*
+ * Called by USBHost to set the instance of USBHost
+ *
+ * @param host host instance
+ */
+ void setHost(USBHost * host);
+
+ /**
+ * Called by USBhost when a hub has been disconnected
+ */
+ void hubDisconnected();
+
+protected:
+ //From IUSBEnumerator
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+ USBHost * host;
+ USBDeviceConnected * dev;
+ bool dev_connected;
+ USBEndpoint * int_in;
+ uint8_t nb_port;
+ uint8_t hub_characteristics;
+
+ void rxHandler();
+
+ uint8_t buf[sizeof(HubDescriptor)];
+
+ int hub_intf;
+ bool hub_device_found;
+
+ void setPortFeature(uint32_t feature, uint8_t port);
+ void clearPortFeature(uint32_t feature, uint8_t port);
+ uint32_t getPortStatus(uint8_t port);
+
+ USBDeviceConnected * device_children[MAX_HUB_PORT];
+
+ void init();
+ void disconnect();
+
+};
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMIDI/USBHostMIDI.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMIDI/USBHostMIDI.cpp
new file mode 100644
index 000000000..3e98f88b5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMIDI/USBHostMIDI.cpp
@@ -0,0 +1,362 @@
+/* Copyright (c) 2014 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "USBHostMIDI.h"
+
+#if USBHOST_MIDI
+
+#include "dbg.h"
+
+#define SET_LINE_CODING 0x20
+
+USBHostMIDI::USBHostMIDI() {
+ host = USBHost::getHostInst();
+ size_bulk_in = 0;
+ size_bulk_out = 0;
+ init();
+}
+
+void USBHostMIDI::init() {
+ dev = NULL;
+ bulk_in = NULL;
+ bulk_out = NULL;
+ dev_connected = false;
+ midi_intf = -1;
+ midi_device_found = false;
+ sysExBufferPos = 0;
+}
+
+bool USBHostMIDI::connected() {
+ return dev_connected;
+}
+
+bool USBHostMIDI::connect() {
+ if (dev_connected) {
+ return true;
+ }
+
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ if ((dev = host->getDevice(i)) != NULL) {
+
+ USB_DBG("Trying to connect MIDI device\r\n");
+
+ if (host->enumerate(dev, this)) {
+ break;
+ }
+
+ if (midi_device_found) {
+ bulk_in = dev->getEndpoint(midi_intf, BULK_ENDPOINT, IN);
+ bulk_out = dev->getEndpoint(midi_intf, BULK_ENDPOINT, OUT);
+
+ if (!bulk_in || !bulk_out) {
+ break;
+ }
+
+ USB_INFO("New MIDI device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, midi_intf);
+ dev->setName("MIDI", midi_intf);
+ host->registerDriver(dev, midi_intf, this, &USBHostMIDI::init);
+
+ size_bulk_in = bulk_in->getSize();
+ size_bulk_out = bulk_out->getSize();
+
+ bulk_in->attach(this, &USBHostMIDI::rxHandler);
+
+ host->bulkRead(dev, bulk_in, buf, size_bulk_in, false);
+ dev_connected = true;
+ return true;
+ }
+ }
+ }
+
+ init();
+ return false;
+}
+
+void USBHostMIDI::rxHandler() {
+ uint8_t *midi;
+ if (bulk_in) {
+ int length = bulk_in->getLengthTransferred();
+ if (bulk_in->getState() == USB_TYPE_IDLE || bulk_in->getState() == USB_TYPE_FREE) {
+ // MIDI event handling
+ for (int i = 0; i < length; i += 4) {
+ if (i + 4 > length) {
+ // length shortage, ignored.
+ break;
+ }
+
+ // read each four bytes
+ midi = &buf[i];
+ // process MIDI message
+ // switch by code index number
+ switch (midi[0] & 0xf) {
+ case 0: // miscellaneous function codes
+ miscellaneousFunctionCode(midi[1], midi[2], midi[3]);
+ break;
+ case 1: // cable events
+ cableEvent(midi[1], midi[2], midi[3]);
+ break;
+ case 2: // two bytes system common messages
+ systemCommonTwoBytes(midi[1], midi[2]);
+ break;
+ case 3: // three bytes system common messages
+ systemCommonThreeBytes(midi[1], midi[2], midi[3]);
+ break;
+ case 4: // SysEx starts or continues
+ sysExBuffer[sysExBufferPos++] = midi[1];
+ if (sysExBufferPos >= 64) {
+ systemExclusive(sysExBuffer, sysExBufferPos, true);
+ sysExBufferPos = 0;
+ }
+ sysExBuffer[sysExBufferPos++] = midi[2];
+ if (sysExBufferPos >= 64) {
+ systemExclusive(sysExBuffer, sysExBufferPos, true);
+ sysExBufferPos = 0;
+ }
+ sysExBuffer[sysExBufferPos++] = midi[3];
+ // SysEx continues. don't send
+ break;
+ case 5: // SysEx ends with single byte
+ sysExBuffer[sysExBufferPos++] = midi[1];
+ systemExclusive(sysExBuffer, sysExBufferPos, false);
+ sysExBufferPos = 0;
+ break;
+ case 6: // SysEx ends with two bytes
+ sysExBuffer[sysExBufferPos++] = midi[1];
+ if (sysExBufferPos >= 64) {
+ systemExclusive(sysExBuffer, sysExBufferPos, true);
+ sysExBufferPos = 0;
+ }
+ sysExBuffer[sysExBufferPos++] = midi[2];
+ systemExclusive(sysExBuffer, sysExBufferPos, false);
+ sysExBufferPos = 0;
+ break;
+ case 7: // SysEx ends with three bytes
+ sysExBuffer[sysExBufferPos++] = midi[1];
+ if (sysExBufferPos >= 64) {
+ systemExclusive(sysExBuffer, sysExBufferPos, true);
+ sysExBufferPos = 0;
+ }
+ sysExBuffer[sysExBufferPos++] = midi[2];
+ if (sysExBufferPos >= 64) {
+ systemExclusive(sysExBuffer, sysExBufferPos, true);
+ sysExBufferPos = 0;
+ }
+ sysExBuffer[sysExBufferPos++] = midi[3];
+ systemExclusive(sysExBuffer, sysExBufferPos, false);
+ sysExBufferPos = 0;
+ break;
+ case 8:
+ noteOff(midi[1] & 0xf, midi[2], midi[3]);
+ break;
+ case 9:
+ if (midi[3]) {
+ noteOn(midi[1] & 0xf, midi[2], midi[3]);
+ } else {
+ noteOff(midi[1] & 0xf, midi[2], midi[3]);
+ }
+ break;
+ case 10:
+ polyKeyPress(midi[1] & 0xf, midi[2], midi[3]);
+ break;
+ case 11:
+ controlChange(midi[1] & 0xf, midi[2], midi[3]);
+ break;
+ case 12:
+ programChange(midi[1] & 0xf, midi[2]);
+ break;
+ case 13:
+ channelPressure(midi[1] & 0xf, midi[2]);
+ break;
+ case 14:
+ pitchBend(midi[1] & 0xf, midi[2] | (midi[3] << 7));
+ break;
+ case 15:
+ singleByte(midi[1]);
+ break;
+ }
+ }
+
+ // read another message
+ host->bulkRead(dev, bulk_in, buf, size_bulk_in, false);
+ }
+ }
+}
+
+bool USBHostMIDI::sendMidiBuffer(uint8_t data0, uint8_t data1, uint8_t data2, uint8_t data3) {
+ if (bulk_out) {
+ uint8_t midi[4];
+
+ midi[0] = data0;
+ midi[1] = data1;
+ midi[2] = data2;
+ midi[3] = data3;
+ if (host->bulkWrite(dev, bulk_out, (uint8_t *)midi, 4) == USB_TYPE_OK) {
+ return true;
+ }
+ }
+ return false;
+}
+
+bool USBHostMIDI::sendMiscellaneousFunctionCode(uint8_t data1, uint8_t data2, uint8_t data3) {
+ return sendMidiBuffer(0, data1, data2, data3);
+}
+
+bool USBHostMIDI::sendCableEvent(uint8_t data1, uint8_t data2, uint8_t data3) {
+ return sendMidiBuffer(1, data1, data2, data3);
+}
+
+bool USBHostMIDI::sendSystemCommmonTwoBytes(uint8_t data1, uint8_t data2) {
+ return sendMidiBuffer(2, data1, data2, 0);
+}
+
+bool USBHostMIDI::sendSystemCommmonThreeBytes(uint8_t data1, uint8_t data2, uint8_t data3) {
+ return sendMidiBuffer(3, data1, data2, 0);
+}
+
+bool USBHostMIDI::sendSystemExclusive(uint8_t *buffer, int length) {
+ uint8_t midi[64];
+ int midiLength;
+ int midiPos;
+ if (bulk_out) {
+ for (int i = 0; i < length; i += 48) {
+ if (i + 48 >= length) {
+ // contains last data
+ midiLength = (((length - i) + 2) / 3) * 4;
+ for (int pos = i; pos < length; pos += 3) {
+ midiPos = (pos + 2) / 3 * 4;
+ if (pos + 3 >= length) {
+ // last data
+ switch (pos % 3) {
+ case 0:
+ midi[midiPos ] = 7;
+ midi[midiPos + 1] = buffer[pos ];
+ midi[midiPos + 2] = buffer[pos + 1];
+ midi[midiPos + 3] = buffer[pos + 2];
+ break;
+ case 1:
+ midi[midiPos ] = 5;
+ midi[midiPos + 1] = buffer[pos ];
+ midi[midiPos + 2] = 0;
+ midi[midiPos + 3] = 0;
+ break;
+ case 2:
+ midi[midiPos ] = 6;
+ midi[midiPos + 1] = buffer[pos ];
+ midi[midiPos + 2] = buffer[pos + 1];
+ midi[midiPos + 3] = 0;
+ break;
+ }
+ } else {
+ // has more data
+ midi[midiPos ] = 4;
+ midi[midiPos + 1] = buffer[pos ];
+ midi[midiPos + 2] = buffer[pos + 1];
+ midi[midiPos + 3] = buffer[pos + 2];
+ }
+ }
+ } else {
+ // has more data
+ midiLength = 64;
+ for (int pos = i; pos < length; pos += 3) {
+ midiPos = (pos + 2) / 3 * 4;
+ midi[midiPos ] = 4;
+ midi[midiPos + 1] = buffer[pos ];
+ midi[midiPos + 2] = buffer[pos + 1];
+ midi[midiPos + 3] = buffer[pos + 2];
+ }
+ }
+
+ if (host->bulkWrite(dev, bulk_out, (uint8_t *)midi, midiLength) != USB_TYPE_OK) {
+ return false;
+ }
+ }
+ return true;
+ }
+ return false;
+}
+
+bool USBHostMIDI::sendNoteOff(uint8_t channel, uint8_t note, uint8_t velocity) {
+ return sendMidiBuffer(8, channel & 0xf | 0x80, note & 0x7f, velocity & 0x7f);
+}
+
+bool USBHostMIDI::sendNoteOn(uint8_t channel, uint8_t note, uint8_t velocity) {
+ return sendMidiBuffer(9, channel & 0xf | 0x90, note & 0x7f, velocity & 0x7f);
+}
+
+bool USBHostMIDI::sendPolyKeyPress(uint8_t channel, uint8_t note, uint8_t pressure) {
+ return sendMidiBuffer(10, channel & 0xf | 0xa0, note & 0x7f, pressure & 0x7f);
+}
+
+bool USBHostMIDI::sendControlChange(uint8_t channel, uint8_t key, uint8_t value) {
+ return sendMidiBuffer(11, channel & 0xf | 0xb0, key & 0x7f, value & 0x7f);
+}
+
+bool USBHostMIDI::sendProgramChange(uint8_t channel, uint8_t program) {
+ return sendMidiBuffer(12, channel & 0xf | 0xc0, program & 0x7f, 0);
+}
+
+bool USBHostMIDI::sendChannelPressure(uint8_t channel, uint8_t pressure) {
+ return sendMidiBuffer(13, channel & 0xf | 0xd0, pressure & 0x7f, 0);
+}
+
+bool USBHostMIDI::sendPitchBend(uint8_t channel, uint16_t value) {
+ return sendMidiBuffer(14, channel & 0xf | 0xe0, value & 0x7f, (value >> 7) & 0x7f);
+}
+
+bool USBHostMIDI::sendSingleByte(uint8_t data) {
+ return sendMidiBuffer(15, data, 0, 0);
+}
+
+/*virtual*/ void USBHostMIDI::setVidPid(uint16_t vid, uint16_t pid)
+{
+ // we don't check VID/PID for this driver
+}
+
+/*virtual*/ bool USBHostMIDI::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ // USB MIDI class/subclass
+ if ((midi_intf == -1) &&
+ (intf_class == AUDIO_CLASS) &&
+ (intf_subclass == 0x03)) {
+ midi_intf = intf_nb;
+ return true;
+ }
+
+ // vendor specific device
+ if ((midi_intf == -1) &&
+ (intf_class == 0xff) &&
+ (intf_subclass == 0x03)) {
+ midi_intf = intf_nb;
+ return true;
+ }
+
+ return false;
+}
+
+/*virtual*/ bool USBHostMIDI::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if (intf_nb == midi_intf) {
+ if (type == BULK_ENDPOINT) {
+ midi_device_found = true;
+ return true;
+ }
+ }
+ return false;
+}
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMIDI/USBHostMIDI.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMIDI/USBHostMIDI.h
new file mode 100644
index 000000000..e124e9b7f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMIDI/USBHostMIDI.h
@@ -0,0 +1,353 @@
+/* Copyright (c) 2014 mbed.org, MIT License
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
+ * and associated documentation files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all copies or
+ * substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
+ * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef USBHOSTMIDI_H
+#define USBHOSTMIDI_H
+
+#include "USBHostConf.h"
+
+#if USBHOST_MIDI
+
+#include "USBHost.h"
+
+/**
+ * A class to communicate a USB MIDI device
+ */
+class USBHostMIDI : public IUSBEnumerator {
+public:
+ /**
+ * Constructor
+ */
+ USBHostMIDI();
+
+ /**
+ * Check if a USB MIDI device is connected
+ *
+ * @returns true if a midi device is connected
+ */
+ bool connected();
+
+ /**
+ * Try to connect a midi device
+ *
+ * @return true if connection was successful
+ */
+ bool connect();
+
+ /**
+ * Attach a callback called when miscellaneous function code is received
+ *
+ * @param ptr function pointer
+ * prototype: void onMiscellaneousFunctionCode(uint8_t data1, uint8_t data2, uint8_t data3);
+ */
+ inline void attachMiscellaneousFunctionCode(void (*fn)(uint8_t, uint8_t, uint8_t)) {
+ miscellaneousFunctionCode = fn;
+ }
+
+ /**
+ * Attach a callback called when cable event is received
+ *
+ * @param ptr function pointer
+ * prototype: void onCableEvent(uint8_t data1, uint8_t data2, uint8_t data3);
+ */
+ inline void attachCableEvent(void (*fn)(uint8_t, uint8_t, uint8_t)) {
+ cableEvent = fn;
+ }
+
+ /**
+ * Attach a callback called when system exclusive is received
+ *
+ * @param ptr function pointer
+ * prototype: void onSystemCommonTwoBytes(uint8_t data1, uint8_t data2);
+ */
+ inline void attachSystemCommonTwoBytes(void (*fn)(uint8_t, uint8_t)) {
+ systemCommonTwoBytes = fn;
+ }
+
+ /**
+ * Attach a callback called when system exclusive is received
+ *
+ * @param ptr function pointer
+ * prototype: void onSystemCommonThreeBytes(uint8_t data1, uint8_t data2, uint8_t data3);
+ */
+ inline void attachSystemCommonThreeBytes(void (*fn)(uint8_t, uint8_t, uint8_t)) {
+ systemCommonThreeBytes = fn;
+ }
+
+ /**
+ * Attach a callback called when system exclusive is received
+ *
+ * @param ptr function pointer
+ * prototype: void onSystemExclusive(uint8_t *data, uint16_t length, bool hasNextData);
+ */
+ inline void attachSystemExclusive(void (*fn)(uint8_t *, uint16_t, bool)) {
+ systemExclusive = fn;
+ }
+
+ /**
+ * Attach a callback called when note on is received
+ *
+ * @param ptr function pointer
+ * prototype: void onNoteOn(uint8_t channel, uint8_t note, uint8_t velocity);
+ */
+ inline void attachNoteOn(void (*fn)(uint8_t, uint8_t, uint8_t)) {
+ noteOn = fn;
+ }
+
+ /**
+ * Attach a callback called when note off is received
+ *
+ * @param ptr function pointer
+ * prototype: void onNoteOff(uint8_t channel, uint8_t note, uint8_t velocity);
+ */
+ inline void attachNoteOff(void (*fn)(uint8_t, uint8_t, uint8_t)) {
+ noteOff = fn;
+ }
+
+ /**
+ * Attach a callback called when poly keypress is received
+ *
+ * @param ptr function pointer
+ * prototype: void onPolyKeyPress(uint8_t channel, uint8_t note, uint8_t pressure);
+ */
+ inline void attachPolyKeyPress(void (*fn)(uint8_t, uint8_t, uint8_t)) {
+ polyKeyPress = fn;
+ }
+
+ /**
+ * Attach a callback called when control change is received
+ *
+ * @param ptr function pointer
+ * prototype: void onControlChange(uint8_t channel, uint8_t key, uint8_t value);
+ */
+ inline void attachControlChange(void (*fn)(uint8_t, uint8_t, uint8_t)) {
+ controlChange = fn;
+ }
+
+ /**
+ * Attach a callback called when program change is received
+ *
+ * @param ptr function pointer
+ * prototype: void onProgramChange(uint8_t channel, uint8_t program);
+ */
+ inline void attachProgramChange(void (*fn)(uint8_t, uint8_t)) {
+ programChange = fn;
+ }
+
+ /**
+ * Attach a callback called when channel pressure is received
+ *
+ * @param ptr function pointer
+ * prototype: void onChannelPressure(uint8_t channel, uint8_t pressure);
+ */
+ inline void attachChannelPressure(void (*fn)(uint8_t, uint8_t)) {
+ channelPressure = fn;
+ }
+
+ /**
+ * Attach a callback called when pitch bend is received
+ *
+ * @param ptr function pointer
+ * prototype: void onPitchBend(uint8_t channel, uint16_t value);
+ */
+ inline void attachPitchBend(void (*fn)(uint8_t, uint16_t)) {
+ pitchBend = fn;
+ }
+
+ /**
+ * Attach a callback called when single byte is received
+ *
+ * @param ptr function pointer
+ * prototype: void onSingleByte(uint8_t value);
+ */
+ inline void attachSingleByte(void (*fn)(uint8_t)) {
+ singleByte = fn;
+ }
+
+ /**
+ * Send a cable event with 3 bytes event
+ *
+ * @param data1 0-255
+ * @param data2 0-255
+ * @param data3 0-255
+ * @return true if message sent successfully
+ */
+ bool sendMiscellaneousFunctionCode(uint8_t data1, uint8_t data2, uint8_t data3);
+
+ /**
+ * Send a cable event with 3 bytes event
+ *
+ * @param data1 0-255
+ * @param data2 0-255
+ * @param data3 0-255
+ * @return true if message sent successfully
+ */
+ bool sendCableEvent(uint8_t data1, uint8_t data2, uint8_t data3);
+
+ /**
+ * Send a system common message with 2 bytes event
+ *
+ * @param data1 0-255
+ * @param data2 0-255
+ * @return true if message sent successfully
+ */
+ bool sendSystemCommmonTwoBytes(uint8_t data1, uint8_t data2);
+
+ /**
+ * Send a system common message with 3 bytes event
+ *
+ * @param data1 0-255
+ * @param data2 0-255
+ * @param data3 0-255
+ * @return true if message sent successfully
+ */
+ bool sendSystemCommmonThreeBytes(uint8_t data1, uint8_t data2, uint8_t data3);
+
+ /**
+ * Send a system exclusive event
+ *
+ * @param buffer, starts with 0xF0, and end with 0xf7
+ * @param length
+ * @return true if message sent successfully
+ */
+ bool sendSystemExclusive(uint8_t *buffer, int length);
+
+ /**
+ * Send a note off event
+ *
+ * @param channel 0-15
+ * @param note 0-127
+ * @param velocity 0-127
+ * @return true if message sent successfully
+ */
+ bool sendNoteOff(uint8_t channel, uint8_t note, uint8_t velocity);
+
+ /**
+ * Send a note on event
+ *
+ * @param channel 0-15
+ * @param note 0-127
+ * @param velocity 0-127 (0 means note off)
+ * @return true if message sent successfully
+ */
+ bool sendNoteOn(uint8_t channel, uint8_t note, uint8_t velocity);
+
+ /**
+ * Send a poly keypress event
+ *
+ * @param channel 0-15
+ * @param note 0-127
+ * @param pressure 0-127
+ * @return true if message sent successfully
+ */
+ bool sendPolyKeyPress(uint8_t channel, uint8_t note, uint8_t pressure);
+
+ /**
+ * Send a control change event
+ *
+ * @param channel 0-15
+ * @param key 0-127
+ * @param value 0-127
+ * @return true if message sent successfully
+ */
+ bool sendControlChange(uint8_t channel, uint8_t key, uint8_t value);
+
+ /**
+ * Send a program change event
+ *
+ * @param channel 0-15
+ * @param program 0-127
+ * @return true if message sent successfully
+ */
+ bool sendProgramChange(uint8_t channel, uint8_t program);
+
+ /**
+ * Send a channel pressure event
+ *
+ * @param channel 0-15
+ * @param pressure 0-127
+ * @return true if message sent successfully
+ */
+ bool sendChannelPressure(uint8_t channel, uint8_t pressure);
+
+ /**
+ * Send a control change event
+ *
+ * @param channel 0-15
+ * @param key 0(lower)-8191(center)-16383(higher)
+ * @return true if message sent successfully
+ */
+ bool sendPitchBend(uint8_t channel, uint16_t value);
+
+ /**
+ * Send a single byte event
+ *
+ * @param data 0-255
+ * @return true if message sent successfully
+ */
+ bool sendSingleByte(uint8_t data);
+
+protected:
+ //From IUSBEnumerator
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+ USBHost * host;
+ USBDeviceConnected * dev;
+ USBEndpoint * bulk_in;
+ USBEndpoint * bulk_out;
+ uint32_t size_bulk_in;
+ uint32_t size_bulk_out;
+
+ bool dev_connected;
+
+ void init();
+
+ uint8_t buf[64];
+
+ void rxHandler();
+
+ uint16_t sysExBufferPos;
+ uint8_t sysExBuffer[64];
+
+ void (*miscellaneousFunctionCode)(uint8_t, uint8_t, uint8_t);
+ void (*cableEvent)(uint8_t, uint8_t, uint8_t);
+ void (*systemCommonTwoBytes)(uint8_t, uint8_t);
+ void (*systemCommonThreeBytes)(uint8_t, uint8_t, uint8_t);
+ void (*systemExclusive)(uint8_t *, uint16_t, bool);
+ void (*noteOff)(uint8_t, uint8_t, uint8_t);
+ void (*noteOn)(uint8_t, uint8_t, uint8_t);
+ void (*polyKeyPress)(uint8_t, uint8_t, uint8_t);
+ void (*controlChange)(uint8_t, uint8_t, uint8_t);
+ void (*programChange)(uint8_t, uint8_t);
+ void (*channelPressure)(uint8_t, uint8_t);
+ void (*pitchBend)(uint8_t, uint16_t);
+ void (*singleByte)(uint8_t);
+
+ bool sendMidiBuffer(uint8_t data0, uint8_t data1, uint8_t data2, uint8_t data3);
+
+ int midi_intf;
+ bool midi_device_found;
+
+};
+
+#endif /* USBHOST_MIDI */
+
+#endif /* USBHOSTMIDI_H */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMSD/USBHostMSD.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMSD/USBHostMSD.cpp
new file mode 100644
index 000000000..1fcb54abf
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMSD/USBHostMSD.cpp
@@ -0,0 +1,366 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBHostMSD.h"
+
+#if USBHOST_MSD
+
+#include "dbg.h"
+
+#define CBW_SIGNATURE 0x43425355
+#define CSW_SIGNATURE 0x53425355
+
+#define DEVICE_TO_HOST 0x80
+#define HOST_TO_DEVICE 0x00
+
+#define GET_MAX_LUN (0xFE)
+#define BO_MASS_STORAGE_RESET (0xFF)
+
+USBHostMSD::USBHostMSD(const char * rootdir) : FATFileSystem(rootdir)
+{
+ host = USBHost::getHostInst();
+ init();
+}
+
+void USBHostMSD::init() {
+ dev_connected = false;
+ dev = NULL;
+ bulk_in = NULL;
+ bulk_out = NULL;
+ dev_connected = false;
+ blockSize = 0;
+ blockCount = 0;
+ msd_intf = -1;
+ msd_device_found = false;
+ disk_init = false;
+ dev_connected = false;
+ nb_ep = 0;
+}
+
+
+bool USBHostMSD::connected()
+{
+ return dev_connected;
+}
+
+bool USBHostMSD::connect()
+{
+
+ if (dev_connected) {
+ return true;
+ }
+
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++) {
+ if ((dev = host->getDevice(i)) != NULL) {
+
+ USB_DBG("Trying to connect MSD device\r\n");
+
+ if(host->enumerate(dev, this))
+ break;
+
+ if (msd_device_found) {
+ bulk_in = dev->getEndpoint(msd_intf, BULK_ENDPOINT, IN);
+ bulk_out = dev->getEndpoint(msd_intf, BULK_ENDPOINT, OUT);
+
+ if (!bulk_in || !bulk_out)
+ continue;
+
+ USB_INFO("New MSD device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, msd_intf);
+ dev->setName("MSD", msd_intf);
+ host->registerDriver(dev, msd_intf, this, &USBHostMSD::init);
+
+ dev_connected = true;
+ return true;
+ }
+ } //if()
+ } //for()
+ init();
+ return false;
+}
+
+/*virtual*/ void USBHostMSD::setVidPid(uint16_t vid, uint16_t pid)
+{
+ // we don't check VID/PID for MSD driver
+}
+
+/*virtual*/ bool USBHostMSD::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ if ((msd_intf == -1) &&
+ (intf_class == MSD_CLASS) &&
+ (intf_subclass == 0x06) &&
+ (intf_protocol == 0x50)) {
+ msd_intf = intf_nb;
+ return true;
+ }
+ return false;
+}
+
+/*virtual*/ bool USBHostMSD::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if (intf_nb == msd_intf) {
+ if (type == BULK_ENDPOINT) {
+ nb_ep++;
+ if (nb_ep == 2)
+ msd_device_found = true;
+ return true;
+ }
+ }
+ return false;
+}
+
+
+int USBHostMSD::testUnitReady() {
+ USB_DBG("Test unit ready");
+ return SCSITransfer(NULL, 6, DEVICE_TO_HOST, 0, 0);
+}
+
+
+int USBHostMSD::readCapacity() {
+ USB_DBG("Read capacity");
+ uint8_t cmd[10] = {0x25,0,0,0,0,0,0,0,0,0};
+ uint8_t result[8];
+ int status = SCSITransfer(cmd, 10, DEVICE_TO_HOST, result, 8);
+ if (status == 0) {
+ blockCount = (result[0] << 24) | (result[1] << 16) | (result[2] << 8) | result[3];
+ blockSize = (result[4] << 24) | (result[5] << 16) | (result[6] << 8) | result[7];
+ USB_INFO("MSD [dev: %p] - blockCount: %lld, blockSize: %d, Capacity: %lld\r\n", dev, blockCount, blockSize, blockCount*blockSize);
+ }
+ return status;
+}
+
+
+int USBHostMSD::SCSIRequestSense() {
+ USB_DBG("Request sense");
+ uint8_t cmd[6] = {0x03,0,0,0,18,0};
+ uint8_t result[18];
+ int status = SCSITransfer(cmd, 6, DEVICE_TO_HOST, result, 18);
+ return status;
+}
+
+
+int USBHostMSD::inquiry(uint8_t lun, uint8_t page_code) {
+ USB_DBG("Inquiry");
+ uint8_t evpd = (page_code == 0) ? 0 : 1;
+ uint8_t cmd[6] = {0x12, uint8_t((lun << 5) | evpd), page_code, 0, 36, 0};
+ uint8_t result[36];
+ int status = SCSITransfer(cmd, 6, DEVICE_TO_HOST, result, 36);
+ if (status == 0) {
+ char vid_pid[17];
+ memcpy(vid_pid, &result[8], 8);
+ vid_pid[8] = 0;
+ USB_INFO("MSD [dev: %p] - Vendor ID: %s", dev, vid_pid);
+
+ memcpy(vid_pid, &result[16], 16);
+ vid_pid[16] = 0;
+ USB_INFO("MSD [dev: %p] - Product ID: %s", dev, vid_pid);
+
+ memcpy(vid_pid, &result[32], 4);
+ vid_pid[4] = 0;
+ USB_INFO("MSD [dev: %p] - Product rev: %s", dev, vid_pid);
+ }
+ return status;
+}
+
+int USBHostMSD::checkResult(uint8_t res, USBEndpoint * ep) {
+ // if ep stalled: send clear feature
+ if (res == USB_TYPE_STALL_ERROR) {
+ res = host->controlWrite( dev,
+ USB_RECIPIENT_ENDPOINT | USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_STANDARD,
+ CLEAR_FEATURE,
+ 0, ep->getAddress(), NULL, 0);
+ // set state to IDLE if clear feature successful
+ if (res == USB_TYPE_OK) {
+ ep->setState(USB_TYPE_IDLE);
+ }
+ }
+
+ if (res != USB_TYPE_OK)
+ return -1;
+
+ return 0;
+}
+
+
+int USBHostMSD::SCSITransfer(uint8_t * cmd, uint8_t cmd_len, int flags, uint8_t * data, uint32_t transfer_len) {
+
+ int res = 0;
+
+ cbw.Signature = CBW_SIGNATURE;
+ cbw.Tag = 0;
+ cbw.DataLength = transfer_len;
+ cbw.Flags = flags;
+ cbw.LUN = 0;
+ cbw.CBLength = cmd_len;
+ memset(cbw.CB,0,sizeof(cbw.CB));
+ if (cmd) {
+ memcpy(cbw.CB,cmd,cmd_len);
+ }
+
+ // send the cbw
+ USB_DBG("Send CBW");
+ res = host->bulkWrite(dev, bulk_out,(uint8_t *)&cbw, 31);
+ if (checkResult(res, bulk_out))
+ return -1;
+
+ // data stage if needed
+ if (data) {
+ USB_DBG("data stage");
+ if (flags == HOST_TO_DEVICE) {
+
+ res = host->bulkWrite(dev, bulk_out, data, transfer_len);
+ if (checkResult(res, bulk_out))
+ return -1;
+
+ } else if (flags == DEVICE_TO_HOST) {
+
+ res = host->bulkRead(dev, bulk_in, data, transfer_len);
+ if (checkResult(res, bulk_in))
+ return -1;
+ }
+ }
+
+ // status stage
+ csw.Signature = 0;
+ USB_DBG("Read CSW");
+ res = host->bulkRead(dev, bulk_in,(uint8_t *)&csw, 13);
+ if (checkResult(res, bulk_in))
+ return -1;
+
+ if (csw.Signature != CSW_SIGNATURE) {
+ return -1;
+ }
+
+ USB_DBG("recv csw: status: %d", csw.Status);
+
+ // ModeSense?
+ if ((csw.Status == 1) && (cmd[0] != 0x03)) {
+ USB_DBG("request mode sense");
+ return SCSIRequestSense();
+ }
+
+ // perform reset recovery
+ if ((csw.Status == 2) && (cmd[0] != 0x03)) {
+
+ // send Bulk-Only Mass Storage Reset request
+ res = host->controlWrite( dev,
+ USB_RECIPIENT_INTERFACE | USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_CLASS,
+ BO_MASS_STORAGE_RESET,
+ 0, msd_intf, NULL, 0);
+
+ // unstall both endpoints
+ res = host->controlWrite( dev,
+ USB_RECIPIENT_ENDPOINT | USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_STANDARD,
+ CLEAR_FEATURE,
+ 0, bulk_in->getAddress(), NULL, 0);
+
+ res = host->controlWrite( dev,
+ USB_RECIPIENT_ENDPOINT | USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_STANDARD,
+ CLEAR_FEATURE,
+ 0, bulk_out->getAddress(), NULL, 0);
+
+ }
+
+ return csw.Status;
+}
+
+
+int USBHostMSD::dataTransfer(uint8_t * buf, uint32_t block, uint8_t nbBlock, int direction) {
+ uint8_t cmd[10];
+ memset(cmd,0,10);
+ cmd[0] = (direction == DEVICE_TO_HOST) ? 0x28 : 0x2A;
+
+ cmd[2] = (block >> 24) & 0xff;
+ cmd[3] = (block >> 16) & 0xff;
+ cmd[4] = (block >> 8) & 0xff;
+ cmd[5] = block & 0xff;
+
+ cmd[7] = (nbBlock >> 8) & 0xff;
+ cmd[8] = nbBlock & 0xff;
+
+ return SCSITransfer(cmd, 10, direction, buf, blockSize*nbBlock);
+}
+
+int USBHostMSD::getMaxLun() {
+ uint8_t buf[1], res;
+ res = host->controlRead( dev, USB_RECIPIENT_INTERFACE | USB_DEVICE_TO_HOST | USB_REQUEST_TYPE_CLASS,
+ 0xfe, 0, msd_intf, buf, 1);
+ USB_DBG("max lun: %d", buf[0]);
+ return res;
+}
+
+int USBHostMSD::disk_initialize() {
+ USB_DBG("FILESYSTEM: init");
+ uint16_t i, timeout = 10;
+
+ getMaxLun();
+
+ for (i = 0; i < timeout; i++) {
+ Thread::wait(100);
+ if (!testUnitReady())
+ break;
+ }
+
+ if (i == timeout) {
+ disk_init = false;
+ return -1;
+ }
+
+ inquiry(0, 0);
+ disk_init = 1;
+ return readCapacity();
+}
+
+int USBHostMSD::disk_write(const uint8_t* buffer, uint64_t block_number, uint8_t count) {
+ USB_DBG("FILESYSTEM: write block: %lld, count: %d", block_number, count);
+ if (!disk_init) {
+ disk_initialize();
+ }
+ if (!disk_init)
+ return -1;
+ for (uint64_t b = block_number; b < block_number + count; b++) {
+ if (dataTransfer((uint8_t*)buffer, b, 1, HOST_TO_DEVICE))
+ return -1;
+ buffer += 512;
+ }
+ return 0;
+}
+
+int USBHostMSD::disk_read(uint8_t* buffer, uint64_t block_number, uint8_t count) {
+ USB_DBG("FILESYSTEM: read block: %lld, count: %d", block_number, count);
+ if (!disk_init) {
+ disk_initialize();
+ }
+ if (!disk_init)
+ return -1;
+ for (uint64_t b = block_number; b < block_number + count; b++) {
+ if (dataTransfer((uint8_t*)buffer, b, 1, DEVICE_TO_HOST))
+ return -1;
+ buffer += 512;
+ }
+ return 0;
+}
+
+uint64_t USBHostMSD::disk_sectors() {
+ USB_DBG("FILESYSTEM: sectors");
+ if (!disk_init) {
+ disk_initialize();
+ }
+ if (!disk_init)
+ return 0;
+ return blockCount;
+}
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMSD/USBHostMSD.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMSD/USBHostMSD.h
new file mode 100644
index 000000000..10c602585
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostMSD/USBHostMSD.h
@@ -0,0 +1,119 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOSTMSD_H
+#define USBHOSTMSD_H
+
+#include "USBHostConf.h"
+
+#if USBHOST_MSD
+
+#include "USBHost.h"
+#include "FATFileSystem.h"
+
+/**
+ * A class to communicate a USB flash disk
+ */
+class USBHostMSD : public IUSBEnumerator, public FATFileSystem {
+public:
+ /**
+ * Constructor
+ *
+ * @param rootdir mount name
+ */
+ USBHostMSD(const char * rootdir);
+
+ /**
+ * Check if a MSD device is connected
+ *
+ * @return true if a MSD device is connected
+ */
+ bool connected();
+
+ /**
+ * Try to connect to a MSD device
+ *
+ * @return true if connection was successful
+ */
+ bool connect();
+
+protected:
+ //From IUSBEnumerator
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+ // From FATFileSystem
+ virtual int disk_initialize();
+ virtual int disk_status() {return 0;};
+ virtual int disk_read(uint8_t* buffer, uint64_t sector, uint8_t count);
+ virtual int disk_write(const uint8_t* buffer, uint64_t sector, uint8_t count);
+ virtual int disk_sync() {return 0;};
+ virtual uint64_t disk_sectors();
+
+private:
+ USBHost * host;
+ USBDeviceConnected * dev;
+ bool dev_connected;
+ USBEndpoint * bulk_in;
+ USBEndpoint * bulk_out;
+ uint8_t nb_ep;
+
+ // Bulk-only CBW
+ typedef struct {
+ uint32_t Signature;
+ uint32_t Tag;
+ uint32_t DataLength;
+ uint8_t Flags;
+ uint8_t LUN;
+ uint8_t CBLength;
+ uint8_t CB[16];
+ } PACKED CBW;
+
+ // Bulk-only CSW
+ typedef struct {
+ uint32_t Signature;
+ uint32_t Tag;
+ uint32_t DataResidue;
+ uint8_t Status;
+ } PACKED CSW;
+
+ CBW cbw;
+ CSW csw;
+
+ int SCSITransfer(uint8_t * cmd, uint8_t cmd_len, int flags, uint8_t * data, uint32_t transfer_len);
+ int testUnitReady();
+ int readCapacity();
+ int inquiry(uint8_t lun, uint8_t page_code);
+ int SCSIRequestSense();
+ int dataTransfer(uint8_t * buf, uint32_t block, uint8_t nbBlock, int direction);
+ int checkResult(uint8_t res, USBEndpoint * ep);
+ int getMaxLun();
+
+ int blockSize;
+ uint64_t blockCount;
+
+ int msd_intf;
+ bool msd_device_found;
+ bool disk_init;
+
+ void init();
+
+};
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/MtxCircBuffer.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/MtxCircBuffer.h
new file mode 100644
index 000000000..ff79affad
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/MtxCircBuffer.h
@@ -0,0 +1,89 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MTXCIRCBUFFER_H
+#define MTXCIRCBUFFER_H
+
+#include "stdint.h"
+#include "rtos.h"
+
+//Mutex protected circular buffer
+template<typename T, int size>
+class MtxCircBuffer {
+public:
+
+ MtxCircBuffer() {
+ write = 0;
+ read = 0;
+ }
+
+ bool isFull() {
+ mtx.lock();
+ bool r = (((write + 1) % size) == read);
+ mtx.unlock();
+ return r;
+ }
+
+ bool isEmpty() {
+ mtx.lock();
+ bool r = (read == write);
+ mtx.unlock();
+ return r;
+ }
+
+ void flush() {
+ write = 0;
+ read = 0;
+ }
+
+ void queue(T k) {
+ mtx.lock();
+ while (((write + 1) % size) == read) {
+ mtx.unlock();
+ Thread::wait(10);
+ mtx.lock();
+ }
+ buf[write++] = k;
+ write %= size;
+ mtx.unlock();
+ }
+
+ uint16_t available() {
+ mtx.lock();
+ uint16_t a = (write >= read) ? (write - read) : (size - read + write);
+ mtx.unlock();
+ return a;
+ }
+
+ bool dequeue(T * c) {
+ mtx.lock();
+ bool empty = (read == write);
+ if (!empty) {
+ *c = buf[read++];
+ read %= size;
+ }
+ mtx.unlock();
+ return (!empty);
+ }
+
+private:
+ volatile uint16_t write;
+ volatile uint16_t read;
+ volatile T buf[size];
+ Mutex mtx;
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/USBHostSerial.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/USBHostSerial.cpp
new file mode 100644
index 000000000..428026ff5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/USBHostSerial.cpp
@@ -0,0 +1,345 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "USBHostSerial.h"
+
+#if USBHOST_SERIAL
+
+#include "dbg.h"
+
+#define CHECK_INTERFACE(cls,subcls,proto) \
+ (((cls == 0xFF) && (subcls == 0xFF) && (proto == 0xFF)) /* QUALCOM CDC */ || \
+ ((cls == SERIAL_CLASS) && (subcls == 0x00) && (proto == 0x00)) /* STANDARD CDC */ )
+
+#if (USBHOST_SERIAL <= 1)
+
+USBHostSerial::USBHostSerial()
+{
+ host = USBHost::getHostInst();
+ ports_found = 0;
+ dev_connected = false;
+}
+
+bool USBHostSerial::connected()
+{
+ return dev_connected;
+}
+
+void USBHostSerial::disconnect(void)
+{
+ ports_found = 0;
+ dev = NULL;
+}
+
+bool USBHostSerial::connect() {
+
+ if (dev)
+ {
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++)
+ {
+ USBDeviceConnected* d = host->getDevice(i);
+ if (dev == d)
+ return true;
+ }
+ disconnect();
+ }
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++)
+ {
+ USBDeviceConnected* d = host->getDevice(i);
+ if (d != NULL) {
+
+ USB_DBG("Trying to connect serial device \r\n");
+ if(host->enumerate(d, this))
+ break;
+
+ USBEndpoint* bulk_in = d->getEndpoint(port_intf, BULK_ENDPOINT, IN);
+ USBEndpoint* bulk_out = d->getEndpoint(port_intf, BULK_ENDPOINT, OUT);
+ if (bulk_in && bulk_out)
+ {
+ USBHostSerialPort::connect(host,d,port_intf,bulk_in, bulk_out);
+ dev = d;
+ dev_connected = true;
+ }
+ }
+ }
+ return dev != NULL;
+}
+
+/*virtual*/ void USBHostSerial::setVidPid(uint16_t vid, uint16_t pid)
+{
+ // we don't check VID/PID for MSD driver
+}
+
+/*virtual*/ bool USBHostSerial::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ if (!ports_found &&
+ CHECK_INTERFACE(intf_class, intf_subclass, intf_protocol)) {
+ port_intf = intf_nb;
+ ports_found = true;
+ return true;
+ }
+ return false;
+}
+
+/*virtual*/ bool USBHostSerial::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if (ports_found && (intf_nb == port_intf)) {
+ if (type == BULK_ENDPOINT)
+ return true;
+ }
+ return false;
+}
+
+#else // (USBHOST_SERIAL > 1)
+
+//------------------------------------------------------------------------------
+
+USBHostMultiSerial::USBHostMultiSerial()
+{
+ host = USBHost::getHostInst();
+ dev = NULL;
+ memset(ports, NULL, sizeof(ports));
+ ports_found = 0;
+ dev_connected = false;
+}
+
+USBHostMultiSerial::~USBHostMultiSerial()
+{
+ disconnect();
+}
+
+bool USBHostMultiSerial::connected()
+{
+ return dev_connected;
+}
+
+void USBHostMultiSerial::disconnect(void)
+{
+ for (int port = 0; port < USBHOST_SERIAL; port ++)
+ {
+ if (ports[port])
+ {
+ delete ports[port];
+ ports[port] = NULL;
+ }
+ }
+ ports_found = 0;
+ dev = NULL;
+}
+
+bool USBHostMultiSerial::connect() {
+
+ if (dev)
+ {
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++)
+ {
+ USBDeviceConnected* d = host->getDevice(i);
+ if (dev == d)
+ return true;
+ }
+ disconnect();
+ }
+ for (uint8_t i = 0; i < MAX_DEVICE_CONNECTED; i++)
+ {
+ USBDeviceConnected* d = host->getDevice(i);
+ if (d != NULL) {
+
+ USB_DBG("Trying to connect serial device \r\n");
+ if(host->enumerate(d, this))
+ break;
+
+ for (int port = 0; port < ports_found; port ++)
+ {
+ USBEndpoint* bulk_in = d->getEndpoint(port_intf[port], BULK_ENDPOINT, IN);
+ USBEndpoint* bulk_out = d->getEndpoint(port_intf[port], BULK_ENDPOINT, OUT);
+ if (bulk_in && bulk_out)
+ {
+ ports[port] = new USBHostSerialPort();
+ if (ports[port])
+ {
+ ports[port]->connect(host,d,port_intf[port],bulk_in, bulk_out);
+ dev = d;
+ dev_connected = true;
+ }
+ }
+ }
+ }
+ }
+ return dev != NULL;
+}
+
+/*virtual*/ void USBHostMultiSerial::setVidPid(uint16_t vid, uint16_t pid)
+{
+ // we don't check VID/PID for MSD driver
+}
+
+/*virtual*/ bool USBHostMultiSerial::parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol) //Must return true if the interface should be parsed
+{
+ if ((ports_found < USBHOST_SERIAL) &&
+ CHECK_INTERFACE(intf_class, intf_subclass, intf_protocol)) {
+ port_intf[ports_found++] = intf_nb;
+ return true;
+ }
+ return false;
+}
+
+/*virtual*/ bool USBHostMultiSerial::useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir) //Must return true if the endpoint will be used
+{
+ if ((ports_found > 0) && (intf_nb == port_intf[ports_found-1])) {
+ if (type == BULK_ENDPOINT)
+ return true;
+ }
+ return false;
+}
+
+#endif
+
+//------------------------------------------------------------------------------
+
+#define SET_LINE_CODING 0x20
+
+USBHostSerialPort::USBHostSerialPort(): circ_buf()
+{
+ init();
+}
+
+void USBHostSerialPort::init(void)
+{
+ host = NULL;
+ dev = NULL;
+ serial_intf = NULL;
+ size_bulk_in = 0;
+ size_bulk_out = 0;
+ bulk_in = NULL;
+ bulk_out = NULL;
+ line_coding.baudrate = 9600;
+ line_coding.data_bits = 8;
+ line_coding.parity = None;
+ line_coding.stop_bits = 1;
+ circ_buf.flush();
+}
+
+void USBHostSerialPort::connect(USBHost* _host, USBDeviceConnected * _dev,
+ uint8_t _serial_intf, USBEndpoint* _bulk_in, USBEndpoint* _bulk_out)
+{
+ host = _host;
+ dev = _dev;
+ serial_intf = _serial_intf;
+ bulk_in = _bulk_in;
+ bulk_out = _bulk_out;
+
+ USB_INFO("New Serial device: VID:%04x PID:%04x [dev: %p - intf: %d]", dev->getVid(), dev->getPid(), dev, serial_intf);
+ dev->setName("Serial", serial_intf);
+ host->registerDriver(dev, serial_intf, this, &USBHostSerialPort::init);
+ baud(9600);
+ size_bulk_in = bulk_in->getSize();
+ size_bulk_out = bulk_out->getSize();
+ bulk_in->attach(this, &USBHostSerialPort::rxHandler);
+ bulk_out->attach(this, &USBHostSerialPort::txHandler);
+ host->bulkRead(dev, bulk_in, buf, size_bulk_in, false);
+}
+
+void USBHostSerialPort::rxHandler() {
+ if (bulk_in) {
+ int len = bulk_in->getLengthTransferred();
+ if (bulk_in->getState() == USB_TYPE_IDLE) {
+ for (int i = 0; i < len; i++) {
+ circ_buf.queue(buf[i]);
+ }
+ rx.call();
+ host->bulkRead(dev, bulk_in, buf, size_bulk_in, false);
+ }
+ }
+}
+
+void USBHostSerialPort::txHandler() {
+ if (bulk_out) {
+ if (bulk_out->getState() == USB_TYPE_IDLE) {
+ tx.call();
+ }
+ }
+}
+
+int USBHostSerialPort::_putc(int c) {
+ if (bulk_out) {
+ if (host->bulkWrite(dev, bulk_out, (uint8_t *)&c, 1) == USB_TYPE_OK) {
+ return 1;
+ }
+ }
+ return -1;
+}
+
+void USBHostSerialPort::baud(int baudrate) {
+ line_coding.baudrate = baudrate;
+ format(line_coding.data_bits, (Parity)line_coding.parity, line_coding.stop_bits);
+}
+
+void USBHostSerialPort::format(int bits, Parity parity, int stop_bits) {
+ line_coding.data_bits = bits;
+ line_coding.parity = parity;
+ line_coding.stop_bits = (stop_bits == 1) ? 0 : 2;
+
+ // set line coding
+ host->controlWrite( dev,
+ USB_RECIPIENT_INTERFACE | USB_HOST_TO_DEVICE | USB_REQUEST_TYPE_CLASS,
+ SET_LINE_CODING,
+ 0, serial_intf, (uint8_t *)&line_coding, 7);
+}
+
+int USBHostSerialPort::_getc() {
+ uint8_t c = 0;
+ if (bulk_in == NULL) {
+ init();
+ return -1;
+ }
+ while (circ_buf.isEmpty());
+ circ_buf.dequeue(&c);
+ return c;
+}
+
+int USBHostSerialPort::writeBuf(const char* b, int s)
+{
+ int c = 0;
+ if (bulk_out)
+ {
+ while (c < s)
+ {
+ int i = (s < size_bulk_out) ? s : size_bulk_out;
+ if (host->bulkWrite(dev, bulk_out, (uint8_t *)(b+c), i) == USB_TYPE_OK)
+ c += i;
+ }
+ }
+ return s;
+}
+
+int USBHostSerialPort::readBuf(char* b, int s)
+{
+ int i = 0;
+ if (bulk_in)
+ {
+ for (i = 0; i < s; )
+ b[i++] = getc();
+ }
+ return i;
+}
+
+uint8_t USBHostSerialPort::available() {
+ return circ_buf.available();
+}
+
+
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/USBHostSerial.h b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/USBHostSerial.h
new file mode 100644
index 000000000..94fc8ad7c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHostSerial/USBHostSerial.h
@@ -0,0 +1,231 @@
+/* mbed USBHost Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef USBHOSTSERIAL_H
+#define USBHOSTSERIAL_H
+
+#include "USBHostConf.h"
+
+#if USBHOST_SERIAL
+
+#include "USBHost.h"
+#include "Stream.h"
+#include "MtxCircBuffer.h"
+
+/**
+ * A class to communicate a USB virtual serial port
+ */
+class USBHostSerialPort : public Stream {
+public:
+ /**
+ * Constructor
+ */
+ USBHostSerialPort();
+
+ enum IrqType {
+ RxIrq,
+ TxIrq
+ };
+
+ enum Parity {
+ None = 0,
+ Odd,
+ Even,
+ Mark,
+ Space
+ };
+
+ void connect(USBHost* _host, USBDeviceConnected * _dev,
+ uint8_t _serial_intf, USBEndpoint* _bulk_in, USBEndpoint* _bulk_out);
+
+ /**
+ * Check the number of bytes available.
+ *
+ * @returns the number of bytes available
+ */
+ uint8_t available();
+
+ /**
+ * Attach a member function to call when a packet is received.
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param irq irq type
+ */
+ template<typename T>
+ inline void attach(T* tptr, void (T::*mptr)(void), IrqType irq = RxIrq) {
+ if ((mptr != NULL) && (tptr != NULL)) {
+ if (irq == RxIrq) {
+ rx.attach(tptr, mptr);
+ } else {
+ tx.attach(tptr, mptr);
+ }
+ }
+ }
+
+ /**
+ * Attach a callback called when a packet is received
+ *
+ * @param ptr function pointer
+ */
+ inline void attach(void (*fn)(void), IrqType irq = RxIrq) {
+ if (fn != NULL) {
+ if (irq == RxIrq) {
+ rx.attach(fn);
+ } else {
+ tx.attach(fn);
+ }
+ }
+ }
+
+ /** Set the baud rate of the serial port
+ *
+ * @param baudrate The baudrate of the serial port (default = 9600).
+ */
+ void baud(int baudrate = 9600);
+
+ /** Set the transmission format used by the Serial port
+ *
+ * @param bits The number of bits in a word (default = 8)
+ * @param parity The parity used (USBHostSerialPort::None, USBHostSerialPort::Odd, USBHostSerialPort::Even, USBHostSerialPort::Mark, USBHostSerialPort::Space; default = USBHostSerialPort::None)
+ * @param stop The number of stop bits (1 or 2; default = 1)
+ */
+ void format(int bits = 8, Parity parity = USBHostSerialPort::None, int stop_bits = 1);
+ virtual int writeBuf(const char* b, int s);
+ virtual int readBuf(char* b, int s);
+
+protected:
+ virtual int _getc();
+ virtual int _putc(int c);
+
+private:
+ USBHost * host;
+ USBDeviceConnected * dev;
+
+ USBEndpoint * bulk_in;
+ USBEndpoint * bulk_out;
+ uint32_t size_bulk_in;
+ uint32_t size_bulk_out;
+
+ void init();
+
+ MtxCircBuffer<uint8_t, 128> circ_buf;
+
+ uint8_t buf[64];
+
+ typedef struct {
+ uint32_t baudrate;
+ uint8_t stop_bits;
+ uint8_t parity;
+ uint8_t data_bits;
+ } PACKED LINE_CODING;
+
+ LINE_CODING line_coding;
+
+ void rxHandler();
+ void txHandler();
+ FunctionPointer rx;
+ FunctionPointer tx;
+
+ uint8_t serial_intf;
+};
+
+#if (USBHOST_SERIAL <= 1)
+
+class USBHostSerial : public IUSBEnumerator, public USBHostSerialPort
+{
+public:
+ USBHostSerial();
+
+ /**
+ * Try to connect a serial device
+ *
+ * @return true if connection was successful
+ */
+ bool connect();
+
+ void disconnect();
+
+ /**
+ * Check if a any serial port is connected
+ *
+ * @returns true if a serial device is connected
+ */
+ bool connected();
+
+protected:
+ USBHost* host;
+ USBDeviceConnected* dev;
+ uint8_t port_intf;
+ int ports_found;
+
+ //From IUSBEnumerator
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+ bool dev_connected;
+};
+
+#else // (USBHOST_SERIAL > 1)
+
+class USBHostMultiSerial : public IUSBEnumerator {
+public:
+ USBHostMultiSerial();
+ virtual ~USBHostMultiSerial();
+
+ USBHostSerialPort* getPort(int port)
+ {
+ return port < USBHOST_SERIAL ? ports[port] : NULL;
+ }
+
+ /**
+ * Try to connect a serial device
+ *
+ * @return true if connection was successful
+ */
+ bool connect();
+
+ void disconnect();
+
+ /**
+ * Check if a any serial port is connected
+ *
+ * @returns true if a serial device is connected
+ */
+ bool connected();
+
+protected:
+ USBHost* host;
+ USBDeviceConnected* dev;
+ USBHostSerialPort* ports[USBHOST_SERIAL];
+ uint8_t port_intf[USBHOST_SERIAL];
+ int ports_found;
+
+ //From IUSBEnumerator
+ virtual void setVidPid(uint16_t vid, uint16_t pid);
+ virtual bool parseInterface(uint8_t intf_nb, uint8_t intf_class, uint8_t intf_subclass, uint8_t intf_protocol); //Must return true if the interface should be parsed
+ virtual bool useEndpoint(uint8_t intf_nb, ENDPOINT_TYPE type, ENDPOINT_DIRECTION dir); //Must return true if the endpoint will be used
+
+private:
+ bool dev_connected;
+};
+#endif // (USBHOST_SERIAL <= 1)
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/doc/mbed.dia b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/mbed.dia
new file mode 100644
index 000000000..af850e842
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/mbed.dia
Binary files differ
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/doc.txt b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/doc.txt
new file mode 100644
index 000000000..270c64c06
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/doc.txt
@@ -0,0 +1,35 @@
+lwip/api/tcpip.c: tcpip_init -> tcpip_thread
+
+lwip/core/netif.c: netif_add
+lwip/arch/lpc17_emac.c: lpc_enetif_init -> packet_rx, packet_tx
+
+=== tcpip_thread ===
+ while (true):
+ sys_timeouts_mbox_fetch(&mbox, (void **)&msg)
+ ...
+
+Feeding the tcpip_thread mbox:
+ tcpip_input
+ tcpip_callback_with_block
+ tcpip_timeout
+ tcpip_untimeout
+ tcpip_apimsg
+ tcpip_netifapi
+
+
+=== packet_rx ===
+ while (true):
+ sys_arch_sem_wait(&lpc_enetif->RxSem, osWaitForever)
+ ...
+
+Feeding the RX semaphore:
+ ENET_IRQHandler
+
+
+=== packet_tx ===
+ while (true):
+ sys_arch_sem_wait(&lpc_enetif->TxCleanSem, osWaitForever)
+ ...
+
+Feeding the TX semaphore:
+ ENET_IRQHandler
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/layers.dia b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/layers.dia
new file mode 100644
index 000000000..ff427c818
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/layers.dia
Binary files differ
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/source.txt b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/source.txt
new file mode 100644
index 000000000..9300ad3a6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/source.txt
@@ -0,0 +1,32 @@
+lwip-1.4.0:
+ http://download.savannah.gnu.org/releases/lwip/lwip-1.4.0.zip
+
+NXP lwIP port:
+ http://sw.lpcware.com/index.php?p=lwip_lpc.git&a=snapshot&h=7b84446afe97af955acad1d720696a0de73ab7cf&fmt=zip
+
+NXP Driver Library (needed for Ethernet defines)
+ http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip
+
+# lwip library
+ lwip-1.4.0\src
+ api
+ core
+ include
+ netif
+
+# lwip-eth library
+ lwip_lpc\nxpcommon\
+ examples/lpc177x_8x/ea1788/ea1788_tcpecho_freertos/source/configs/flash/lpc_emac_config.h
+ lpc_phy_dp83848.c
+ lpc_phy.h
+ arch\lpc177x_8x\lpc17_emac.c
+ arch\lpc177x_8x\lpc17_emac.h
+ lpc17xx.cmsis.driver.library\Drivers\include
+ lpc17xx_emac.h
+
+# lwip-sys library
+ lwip_lpc\nxpcommon\arch
+ cc.h
+ perf.h
+ touch sys_arch.c
+ touch sys_arch.h
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/sys_arch.txt b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/sys_arch.txt
new file mode 100644
index 000000000..38377b665
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/sys_arch.txt
@@ -0,0 +1,216 @@
+sys_arch interface for lwIP 0.6++
+
+Author: Adam Dunkels
+
+The operating system emulation layer provides a common interface
+between the lwIP code and the underlying operating system kernel. The
+general idea is that porting lwIP to new architectures requires only
+small changes to a few header files and a new sys_arch
+implementation. It is also possible to do a sys_arch implementation
+that does not rely on any underlying operating system.
+
+The sys_arch provides semaphores and mailboxes to lwIP. For the full
+lwIP functionality, multiple threads support can be implemented in the
+sys_arch, but this is not required for the basic lwIP
+functionality. Previous versions of lwIP required the sys_arch to
+implement timer scheduling as well but as of lwIP 0.5 this is
+implemented in a higher layer.
+
+In addition to the source file providing the functionality of sys_arch,
+the OS emulation layer must provide several header files defining
+macros used throughout lwip. The files required and the macros they
+must define are listed below the sys_arch description.
+
+Semaphores can be either counting or binary - lwIP works with both
+kinds. Mailboxes are used for message passing and can be implemented
+either as a queue which allows multiple messages to be posted to a
+mailbox, or as a rendez-vous point where only one message can be
+posted at a time. lwIP works with both kinds, but the former type will
+be more efficient. A message in a mailbox is just a pointer, nothing
+more.
+
+Semaphores are represented by the type "sys_sem_t" which is typedef'd
+in the sys_arch.h file. Mailboxes are equivalently represented by the
+type "sys_mbox_t". lwIP does not place any restrictions on how
+sys_sem_t or sys_mbox_t are represented internally.
+
+The following functions must be implemented by the sys_arch:
+
+- void sys_init(void)
+
+ Is called to initialize the sys_arch layer.
+
+- sys_sem_t sys_sem_new(u8_t count)
+
+ Creates and returns a new semaphore. The "count" argument specifies
+ the initial state of the semaphore.
+
+- void sys_sem_free(sys_sem_t sem)
+
+ Deallocates a semaphore.
+
+- void sys_sem_signal(sys_sem_t sem)
+
+ Signals a semaphore.
+
+- u32_t sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
+
+ Blocks the thread while waiting for the semaphore to be
+ signaled. If the "timeout" argument is non-zero, the thread should
+ only be blocked for the specified time (measured in
+ milliseconds). If the "timeout" argument is zero, the thread should be
+ blocked until the semaphore is signalled.
+
+ If the timeout argument is non-zero, the return value is the number of
+ milliseconds spent waiting for the semaphore to be signaled. If the
+ semaphore wasn't signaled within the specified time, the return value is
+ SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+ (i.e., it was already signaled), the function may return zero.
+
+ Notice that lwIP implements a function with a similar name,
+ sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+
+- sys_mbox_t sys_mbox_new(int size)
+
+ Creates an empty mailbox for maximum "size" elements. Elements stored
+ in mailboxes are pointers. You have to define macros "_MBOX_SIZE"
+ in your lwipopts.h, or ignore this parameter in your implementation
+ and use a default size.
+
+- void sys_mbox_free(sys_mbox_t mbox)
+
+ Deallocates a mailbox. If there are messages still present in the
+ mailbox when the mailbox is deallocated, it is an indication of a
+ programming error in lwIP and the developer should be notified.
+
+- void sys_mbox_post(sys_mbox_t mbox, void *msg)
+
+ Posts the "msg" to the mailbox. This function have to block until
+ the "msg" is really posted.
+
+- err_t sys_mbox_trypost(sys_mbox_t mbox, void *msg)
+
+ Try to post the "msg" to the mailbox. Returns ERR_MEM if this one
+ is full, else, ERR_OK if the "msg" is posted.
+
+- u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
+
+ Blocks the thread until a message arrives in the mailbox, but does
+ not block the thread longer than "timeout" milliseconds (similar to
+ the sys_arch_sem_wait() function). If "timeout" is 0, the thread should
+ be blocked until a message arrives. The "msg" argument is a result
+ parameter that is set by the function (i.e., by doing "*msg =
+ ptr"). The "msg" parameter maybe NULL to indicate that the message
+ should be dropped.
+
+ The return values are the same as for the sys_arch_sem_wait() function:
+ Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+ timeout.
+
+ Note that a function with a similar name, sys_mbox_fetch(), is
+ implemented by lwIP.
+
+- u32_t sys_arch_mbox_tryfetch(sys_mbox_t mbox, void **msg)
+
+ This is similar to sys_arch_mbox_fetch, however if a message is not
+ present in the mailbox, it immediately returns with the code
+ SYS_MBOX_EMPTY. On success 0 is returned.
+
+ To allow for efficient implementations, this can be defined as a
+ function-like macro in sys_arch.h instead of a normal function. For
+ example, a naive implementation could be:
+ #define sys_arch_mbox_tryfetch(mbox,msg) \
+ sys_arch_mbox_fetch(mbox,msg,1)
+ although this would introduce unnecessary delays.
+
+If threads are supported by the underlying operating system and if
+such functionality is needed in lwIP, the following function will have
+to be implemented as well:
+
+- sys_thread_t sys_thread_new(char *name, void (* thread)(void *arg), void *arg, int stacksize, int prio)
+
+ Starts a new thread named "name" with priority "prio" that will begin its
+ execution in the function "thread()". The "arg" argument will be passed as an
+ argument to the thread() function. The stack size to used for this thread is
+ the "stacksize" parameter. The id of the new thread is returned. Both the id
+ and the priority are system dependent.
+
+- sys_prot_t sys_arch_protect(void)
+
+ This optional function does a "fast" critical region protection and returns
+ the previous protection level. This function is only called during very short
+ critical regions. An embedded system which supports ISR-based drivers might
+ want to implement this function by disabling interrupts. Task-based systems
+ might want to implement this by using a mutex or disabling tasking. This
+ function should support recursive calls from the same task or interrupt. In
+ other words, sys_arch_protect() could be called while already protected. In
+ that case the return value indicates that it is already protected.
+
+ sys_arch_protect() is only required if your port is supporting an operating
+ system.
+
+- void sys_arch_unprotect(sys_prot_t pval)
+
+ This optional function does a "fast" set of critical region protection to the
+ value specified by pval. See the documentation for sys_arch_protect() for
+ more information. This function is only required if your port is supporting
+ an operating system.
+
+Note:
+
+Be carefull with using mem_malloc() in sys_arch. When malloc() refers to
+mem_malloc() you can run into a circular function call problem. In mem.c
+mem_init() tries to allcate a semaphore using mem_malloc, which of course
+can't be performed when sys_arch uses mem_malloc.
+
+-------------------------------------------------------------------------------
+Additional files required for the "OS support" emulation layer:
+-------------------------------------------------------------------------------
+
+cc.h - Architecture environment, some compiler specific, some
+ environment specific (probably should move env stuff
+ to sys_arch.h.)
+
+ Typedefs for the types used by lwip -
+ u8_t, s8_t, u16_t, s16_t, u32_t, s32_t, mem_ptr_t
+
+ Compiler hints for packing lwip's structures -
+ PACK_STRUCT_FIELD(x)
+ PACK_STRUCT_STRUCT
+ PACK_STRUCT_BEGIN
+ PACK_STRUCT_END
+
+ Platform specific diagnostic output -
+ LWIP_PLATFORM_DIAG(x) - non-fatal, print a message.
+ LWIP_PLATFORM_ASSERT(x) - fatal, print message and abandon execution.
+ Portability defines for printf formatters:
+ U16_F, S16_F, X16_F, U32_F, S32_F, X32_F, SZT_F
+
+ "lightweight" synchronization mechanisms -
+ SYS_ARCH_DECL_PROTECT(x) - declare a protection state variable.
+ SYS_ARCH_PROTECT(x) - enter protection mode.
+ SYS_ARCH_UNPROTECT(x) - leave protection mode.
+
+ If the compiler does not provide memset() this file must include a
+ definition of it, or include a file which defines it.
+
+ This file must either include a system-local <errno.h> which defines
+ the standard *nix error codes, or it should #define LWIP_PROVIDE_ERRNO
+ to make lwip/arch.h define the codes which are used throughout.
+
+
+perf.h - Architecture specific performance measurement.
+ Measurement calls made throughout lwip, these can be defined to nothing.
+ PERF_START - start measuring something.
+ PERF_STOP(x) - stop measuring something, and record the result.
+
+sys_arch.h - Tied to sys_arch.c
+
+ Arch dependent types for the following objects:
+ sys_sem_t, sys_mbox_t, sys_thread_t,
+ And, optionally:
+ sys_prot_t
+
+ Defines to set vars of sys_mbox_t and sys_sem_t to NULL.
+ SYS_MBOX_NULL NULL
+ SYS_SEM_NULL NULL
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/tcp.dia b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/tcp.dia
new file mode 100644
index 000000000..7c79fabff
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/tcp.dia
Binary files differ
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/udp.dia b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/udp.dia
new file mode 100644
index 000000000..cbffd7c93
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/net/udp.dia
Binary files differ
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/doc/rtos.txt b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/rtos.txt
new file mode 100644
index 000000000..2afdc6a51
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/rtos.txt
@@ -0,0 +1,37 @@
+=== Tasks ===
+
+^ os_tsk.new->task_id ^ Tasks ^ Stack Size ^
+| 0x01 | Main | 4*OS_MAINSTKSIZE |
+| 0x02 | Timer | 4*OS_TIMERSTKSZ |
+| 0xFF | Idle | 4*OS_STKSIZE |
+
+----------
+ |
+ V os_tsk.run->tsk_stack
+
+
+MAGIC_WORD os_tsk.run->stack[0]
+----------
+
+The current task structure is always pointed by:
+ struct OS_TSK os_tsk;
+
+=== Init Sequence ===
+OS:
+ * osKernelInitialize
+ * rt_sys_init
+ * rt_init_context
+ * rt_init_stack
+ * rt_set_PSP
+ * rt_init_robin
+ * rt_svc_init
+
+ * set_main_stack
+
+ * osThreadCreate(os_thread_def_main)
+ * rt_tsk_create
+ * rt_init_context
+ * rt_init_stack
+ * rt_dispatch
+
+ * osKernelStart
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/doc/style.xml b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/style.xml
new file mode 100644
index 000000000..c991069fc
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/doc/style.xml
@@ -0,0 +1,166 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<profiles version="1">
+<profile kind="CodeFormatterProfile" name="mbed K&amp;R" version="1">
+<setting id="org.eclipse.cdt.core.formatter.insert_space_before_opening_paren_in_method_declaration" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_for" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_new_line_in_empty_block" value="insert"/>
+<setting id="org.eclipse.cdt.core.formatter.lineSplit" value="80"/>
+<setting id="org.eclipse.cdt.core.formatter.alignment_for_member_access" value="2"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_before_comma_in_base_types" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.keep_else_statement_on_same_line" value="false"/>
+<setting id="org.eclipse.cdt.core.formatter.indent_switchstatements_compare_to_switch" value="true"/>
+<setting id="org.eclipse.cdt.core.formatter.alignment_for_constructor_initializer_list" value="2"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_opening_brace_in_array_initializer" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_before_comma_in_method_declaration_parameters" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_if" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_parenthesized_expression" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_opening_paren_in_exception_specification" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_comma_in_base_types" value="insert"/>
+<setting id="org.eclipse.cdt.core.formatter.indent_body_declarations_compare_to_access_specifier" value="true"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_exception_specification" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_comma_in_template_arguments" value="insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_before_opening_brace_in_block" value="insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_before_closing_paren_in_method_declaration" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.use_tabs_only_for_leading_indentations" value="false"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_before_colon_in_labeled_statement" value="do not insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_colon_in_case" value="insert"/>
+<setting id="org.eclipse.cdt.core.formatter.comment.min_distance_between_code_and_line_comment" value="1"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_comma_in_array_initializer" value="insert"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_comma_in_enum_declarations" value="insert"/>
+<setting id="org.eclipse.cdt.core.formatter.alignment_for_expressions_in_array_initializer" value="2"/>
+<setting id="org.eclipse.cdt.core.formatter.insert_space_after_comma_in_declarator_list" value="insert"/>
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+<setting id="org.eclipse.cdt.core.formatter.tabulation.size" value="4"/>
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+<setting id="org.eclipse.cdt.core.formatter.alignment_for_declarator_list" value="16"/>
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+<setting id="org.eclipse.cdt.core.formatter.brace_position_for_type_declaration" value="end_of_line"/>
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diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_f32.c
new file mode 100644
index 000000000..90613e712
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_abs_f32.c
+*
+* Description: Vector absolute value.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include <math.h>
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicAbs Vector Absolute Value
+ *
+ * Computes the absolute value of a vector on an element-by-element basis.
+ *
+ * <pre>
+ * pDst[n] = abs(pSrc[n]), 0 <= n < blockSize.
+ * </pre>
+ *
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+/**
+ * @brief Floating-point vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4; /* temporary variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Calculate absolute and then store the results in the destination buffer. */
+ /* read sample from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+
+ /* find absolute value */
+ in1 = fabsf(in1);
+
+ /* read sample from source */
+ in4 = *(pSrc + 3);
+
+ /* find absolute value */
+ in2 = fabsf(in2);
+
+ /* read sample from source */
+ *pDst = in1;
+
+ /* find absolute value */
+ in3 = fabsf(in3);
+
+ /* find absolute value */
+ in4 = fabsf(in4);
+
+ /* store result to destination */
+ *(pDst + 1) = in2;
+
+ /* store result to destination */
+ *(pDst + 2) = in3;
+
+ /* store result to destination */
+ *(pDst + 3) = in4;
+
+
+ /* Update source pointer to process next sampels */
+ pSrc += 4u;
+
+ /* Update destination pointer to process next sampels */
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Calculate absolute and then store the results in the destination buffer. */
+ *pDst++ = fabsf(*pSrc++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q15.c
new file mode 100644
index 000000000..c7822da51
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q15.c
@@ -0,0 +1,179 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_abs_q15.c
+*
+* Description: Q15 vector absolute value.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+/**
+ * @brief Q15 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+ __SIMD32_TYPE *simd;
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t in1; /* Input value1 */
+ q15_t in2; /* Input value2 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ simd = __SIMD32_CONST(pDst);
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read two inputs */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+
+ /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */
+#ifndef ARM_MATH_BIG_ENDIAN
+ *simd++ =
+ __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
+ ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
+
+#else
+
+
+ *simd++ =
+ __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
+ ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *simd++ =
+ __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
+ ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
+
+#else
+
+
+ *simd++ =
+ __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
+ ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ pDst = (q15_t *)simd;
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read the input */
+ in1 = *pSrc++;
+
+ /* Calculate absolute value of input and then store the result in the destination buffer. */
+ *pDst++ = (in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t in; /* Temporary input variable */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read the input */
+ in = *pSrc++;
+
+ /* Calculate absolute value of input and then store the result in the destination buffer. */
+ *pDst++ = (in > 0) ? in : ((in == (q15_t) 0x8000) ? 0x7fff : -in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q31.c
new file mode 100644
index 000000000..f375bf182
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q31.c
@@ -0,0 +1,130 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_abs_q31.c
+*
+* Description: Q31 vector absolute value.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+
+/**
+ * @brief Q31 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q31_t in; /* Input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = (in1 > 0) ? in1 : (q31_t)__QSUB(0, in1);
+ *pDst++ = (in2 > 0) ? in2 : (q31_t)__QSUB(0, in2);
+ *pDst++ = (in3 > 0) ? in3 : (q31_t)__QSUB(0, in3);
+ *pDst++ = (in4 > 0) ? in4 : (q31_t)__QSUB(0, in4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
+ in = *pSrc++;
+ *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q7.c
new file mode 100644
index 000000000..125374c0c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q7.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_abs_q7.c
+*
+* Description: Q7 vector absolute value.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAbs
+ * @{
+ */
+
+/**
+ * @brief Q7 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * \par Conditions for optimum performance
+ * Input and output buffers should be aligned by 32-bit
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.
+ */
+
+void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q7_t in; /* Input value1 */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4; /* temporary input variables */
+ q31_t out1, out2, out3, out4; /* temporary output variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read inputs */
+ in1 = (q31_t) * pSrc;
+ in2 = (q31_t) * (pSrc + 1);
+ in3 = (q31_t) * (pSrc + 2);
+
+ /* find absolute value */
+ out1 = (in1 > 0) ? in1 : (q31_t)__QSUB8(0, in1);
+
+ /* read input */
+ in4 = (q31_t) * (pSrc + 3);
+
+ /* find absolute value */
+ out2 = (in2 > 0) ? in2 : (q31_t)__QSUB8(0, in2);
+
+ /* store result to destination */
+ *pDst = (q7_t) out1;
+
+ /* find absolute value */
+ out3 = (in3 > 0) ? in3 : (q31_t)__QSUB8(0, in3);
+
+ /* find absolute value */
+ out4 = (in4 > 0) ? in4 : (q31_t)__QSUB8(0, in4);
+
+ /* store result to destination */
+ *(pDst + 1) = (q7_t) out2;
+
+ /* store result to destination */
+ *(pDst + 2) = (q7_t) out3;
+
+ /* store result to destination */
+ *(pDst + 3) = (q7_t) out4;
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = blockSize;
+
+#endif // #define ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0u)
+ {
+ /* C = |A| */
+ /* Read the input */
+ in = *pSrc++;
+
+ /* Store the Absolute result in the destination buffer */
+ *pDst++ = (in > 0) ? in : ((in == (q7_t) 0x80) ? 0x7f : -in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicAbs group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_f32.c
new file mode 100644
index 000000000..7ae25d833
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_f32.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_add_f32.c
+*
+* Description: Floating-point vector addition.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicAdd Vector Addition
+ *
+ * Element-by-element addition of two vectors.
+ *
+ * <pre>
+ * pDst[n] = pSrcA[n] + pSrcB[n], 0 <= n < blockSize.
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+/**
+ * @brief Floating-point vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */
+ float32_t inB1, inB2, inB3, inB4; /* temporary input variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+
+ /* read four inputs from sourceA and four inputs from sourceB */
+ inA1 = *pSrcA;
+ inB1 = *pSrcB;
+ inA2 = *(pSrcA + 1);
+ inB2 = *(pSrcB + 1);
+ inA3 = *(pSrcA + 2);
+ inB3 = *(pSrcB + 2);
+ inA4 = *(pSrcA + 3);
+ inB4 = *(pSrcB + 3);
+
+ /* C = A + B */
+ /* add and store result to destination */
+ *pDst = inA1 + inB1;
+ *(pDst + 1) = inA2 + inB2;
+ *(pDst + 2) = inA3 + inB3;
+ *(pDst + 3) = inA4 + inB4;
+
+ /* update pointers to process next samples */
+ pSrcA += 4u;
+ pSrcB += 4u;
+ pDst += 4u;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (*pSrcA++) + (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q15.c
new file mode 100644
index 000000000..7af88664e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_add_q15.c
+*
+* Description: Q15 vector addition
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+/**
+ * @brief Q15 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inB1, inB2;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ inA1 = *__SIMD32(pSrcA)++;
+ inA2 = *__SIMD32(pSrcA)++;
+ inB1 = *__SIMD32(pSrcB)++;
+ inB2 = *__SIMD32(pSrcB)++;
+
+ *__SIMD32(pDst)++ = __QADD16(inA1, inB1);
+ *__SIMD32(pDst)++ = __QADD16(inA2, inB2);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q31.c
new file mode 100644
index 000000000..c5b9ac262
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q31.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_add_q31.c
+*
+* Description: Q31 vector addition.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+
+/**
+ * @brief Q31 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4;
+ q31_t inB1, inB2, inB3, inB4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ *pDst++ = __QADD(inA1, inB1);
+ *pDst++ = __QADD(inA2, inB2);
+ *pDst++ = __QADD(inA3, inB3);
+ *pDst++ = __QADD(inA4, inB4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = __QADD(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ + *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q7.c
new file mode 100644
index 000000000..a5bb07fc0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q7.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_add_q7.c
+*
+* Description: Q7 vector addition.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicAdd
+ * @{
+ */
+
+/**
+ * @brief Q7 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + B */
+ /* Add and then store the results in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of BasicAdd group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_f32.c
new file mode 100644
index 000000000..870672ba3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_f32.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dot_prod_f32.c
+*
+* Description: Floating-point dot product.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup dot_prod Vector Dot Product
+ *
+ * Computes the dot product of two vectors.
+ * The vectors are multiplied element-by-element and then summed.
+ *
+ * <pre>
+ * sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+
+void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result)
+{
+ float32_t sum = 0.0f; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer */
+ sum += (*pSrcA++) * (*pSrcB++);
+ sum += (*pSrcA++) * (*pSrcB++);
+ sum += (*pSrcA++) * (*pSrcB++);
+ sum += (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ sum += (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ /* Store the result back in the destination buffer */
+ *result = sum;
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q15.c
new file mode 100644
index 000000000..3eb0a10ef
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dot_prod_q15.c
+*
+* Description: Q15 dot product.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these
+ * results are added to a 64-bit accumulator in 34.30 format.
+ * Nonsaturating additions are used and given that there are 33 guard bits in the accumulator
+ * there is no risk of overflow.
+ * The return result is in 34.30 format.
+ */
+
+void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result)
+{
+ q63_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);
+ sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the results in a temporary buffer. */
+ sum = __SMLALD(*pSrcA++, *pSrcB++, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the results in a temporary buffer. */
+ sum += (q63_t) ((q31_t) * pSrcA++ * *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the result in the destination buffer in 34.30 format */
+ *result = sum;
+
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q31.c
new file mode 100644
index 000000000..3712a0a90
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q31.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dot_prod_q31.c
+*
+* Description: Q31 dot product.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these
+ * are truncated to 2.48 format by discarding the lower 14 bits.
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
+ * There are 15 guard bits in the accumulator and there is no risk of overflow as long as
+ * the length of the vectors is less than 2^16 elements.
+ * The return result is in 16.48 format.
+ */
+
+void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result)
+{
+ q63_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4;
+ q31_t inB1, inB2, inB3, inB4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ sum += ((q63_t) inA1 * inB1) >> 14u;
+ sum += ((q63_t) inA2 * inB2) >> 14u;
+ sum += ((q63_t) inA3 * inB3) >> 14u;
+ sum += ((q63_t) inA4 * inB4) >> 14u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Calculate dot product and then store the result in a temporary buffer. */
+ sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Store the result in the destination buffer in 16.48 format */
+ *result = sum;
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q7.c
new file mode 100644
index 000000000..bbf4dd61a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q7.c
@@ -0,0 +1,159 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dot_prod_q7.c
+*
+* Description: Q7 dot product.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup dot_prod
+ * @{
+ */
+
+/**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these
+ * results are added to an accumulator in 18.14 format.
+ * Nonsaturating additions are used and there is no danger of wrap around as long as
+ * the vectors are less than 2^18 elements long.
+ * The return result is in 18.14 format.
+ */
+
+void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result)
+{
+ uint32_t blkCnt; /* loop counter */
+
+ q31_t sum = 0; /* Temporary variables to store output */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t input1, input2; /* Temporary variables to store input */
+ q31_t inA1, inA2, inB1, inB2; /* Temporary variables to store input */
+
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read 4 samples at a time from sourceA */
+ input1 = *__SIMD32(pSrcA)++;
+ /* read 4 samples at a time from sourceB */
+ input2 = *__SIMD32(pSrcB)++;
+
+ /* extract two q7_t samples to q15_t samples */
+ inA1 = __SXTB16(__ROR(input1, 8));
+ /* extract reminaing two samples */
+ inA2 = __SXTB16(input1);
+ /* extract two q7_t samples to q15_t samples */
+ inB1 = __SXTB16(__ROR(input2, 8));
+ /* extract reminaing two samples */
+ inB2 = __SXTB16(input2);
+
+ /* multiply and accumulate two samples at a time */
+ sum = __SMLAD(inA1, inB1, sum);
+ sum = __SMLAD(inA2, inB2, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Dot product and then store the results in a temporary buffer. */
+ sum = __SMLAD(*pSrcA++, *pSrcB++, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
+ /* Dot product and then store the results in a temporary buffer. */
+ sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ /* Store the result in the destination buffer in 18.14 format */
+ *result = sum;
+}
+
+/**
+ * @} end of dot_prod group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_f32.c
new file mode 100644
index 000000000..32532e15c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_f32.c
@@ -0,0 +1,174 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mult_f32.c
+*
+* Description: Floating-point vector multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicMult Vector Multiplication
+ *
+ * Element-by-element multiplication of two vectors.
+ *
+ * <pre>
+ * pDst[n] = pSrcA[n] * pSrcB[n], 0 <= n < blockSize.
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+/**
+ * @brief Floating-point vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* temporary input variables */
+ float32_t inB1, inB2, inB3, inB4; /* temporary input variables */
+ float32_t out1, out2, out3, out4; /* temporary output variables */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the results in output buffer */
+ /* read sample from sourceA */
+ inA1 = *pSrcA;
+ /* read sample from sourceB */
+ inB1 = *pSrcB;
+ /* read sample from sourceA */
+ inA2 = *(pSrcA + 1);
+ /* read sample from sourceB */
+ inB2 = *(pSrcB + 1);
+
+ /* out = sourceA * sourceB */
+ out1 = inA1 * inB1;
+
+ /* read sample from sourceA */
+ inA3 = *(pSrcA + 2);
+ /* read sample from sourceB */
+ inB3 = *(pSrcB + 2);
+
+ /* out = sourceA * sourceB */
+ out2 = inA2 * inB2;
+
+ /* read sample from sourceA */
+ inA4 = *(pSrcA + 3);
+
+ /* store result to destination buffer */
+ *pDst = out1;
+
+ /* read sample from sourceB */
+ inB4 = *(pSrcB + 3);
+
+ /* out = sourceA * sourceB */
+ out3 = inA3 * inB3;
+
+ /* store result to destination buffer */
+ *(pDst + 1) = out2;
+
+ /* out = sourceA * sourceB */
+ out4 = inA4 * inB4;
+ /* store result to destination buffer */
+ *(pDst + 2) = out3;
+ /* store result to destination buffer */
+ *(pDst + 3) = out4;
+
+
+ /* update pointers to process next samples */
+ pSrcA += 4u;
+ pSrcB += 4u;
+ pDst += 4u;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the results in output buffer */
+ *pDst++ = (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q15.c
new file mode 100644
index 000000000..ac4266ca6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q15.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mult_q15.c
+*
+* Description: Q15 vector multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 vector multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inB1, inB2; /* temporary input variables */
+ q15_t out1, out2, out3, out4; /* temporary output variables */
+ q31_t mul1, mul2, mul3, mul4; /* temporary variables */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read two samples at a time from sourceA */
+ inA1 = *__SIMD32(pSrcA)++;
+ /* read two samples at a time from sourceB */
+ inB1 = *__SIMD32(pSrcB)++;
+ /* read two samples at a time from sourceA */
+ inA2 = *__SIMD32(pSrcA)++;
+ /* read two samples at a time from sourceB */
+ inB2 = *__SIMD32(pSrcB)++;
+
+ /* multiply mul = sourceA * sourceB */
+ mul1 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+ mul2 = (q31_t) ((q15_t) inA1 * (q15_t) inB1);
+ mul3 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB2 >> 16));
+ mul4 = (q31_t) ((q15_t) inA2 * (q15_t) inB2);
+
+ /* saturate result to 16 bit */
+ out1 = (q15_t) __SSAT(mul1 >> 15, 16);
+ out2 = (q15_t) __SSAT(mul2 >> 15, 16);
+ out3 = (q15_t) __SSAT(mul3 >> 15, 16);
+ out4 = (q15_t) __SSAT(mul4 >> 15, 16);
+
+ /* store the result */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(out2, out1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(out4, out3, 16);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the result in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q31.c
new file mode 100644
index 000000000..9210c337e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q31.c
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mult_q31.c
+*
+* Description: Q31 vector multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+/**
+ * @brief Q31 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4; /* temporary input variables */
+ q31_t inB1, inB2, inB3, inB4; /* temporary input variables */
+ q31_t out1, out2, out3, out4; /* temporary output variables */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and then store the results in the destination buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB2) >> 32;
+ out3 = ((q63_t) inA3 * inB3) >> 32;
+ out4 = ((q63_t) inA4 * inB4) >> 32;
+
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+ out3 = __SSAT(out3, 31);
+ out4 = __SSAT(out4, 31);
+
+ *pDst++ = out1 << 1u;
+ *pDst++ = out2 << 1u;
+ *pDst++ = out3 << 1u;
+ *pDst++ = out4 << 1u;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and then store the results in the destination buffer. */
+ *pDst++ =
+ (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q7.c
new file mode 100644
index 000000000..b8cb2002a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q7.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mult_q7.c
+*
+* Description: Q7 vector multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicMult
+ * @{
+ */
+
+/**
+ * @brief Q7 vector multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q7_t out1, out2, out3, out4; /* Temporary variables to store the product */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the results in temporary variables */
+ out1 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out2 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out3 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+ out4 = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+
+ /* Store the results of 4 inputs in the destination buffer in single cycle by packing */
+ *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * B */
+ /* Multiply the inputs and store the result in the destination buffer */
+ *pDst++ = (q7_t) __SSAT((((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7), 8);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_f32.c
new file mode 100644
index 000000000..d887b8cdc
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_f32.c
@@ -0,0 +1,146 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_negate_f32.c
+*
+* Description: Negates floating-point vectors.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup negate Vector Negate
+ *
+ * Negates the elements of a vector.
+ *
+ * <pre>
+ * pDst[n] = -pSrc[n], 0 <= n < blockSize.
+ * </pre>
+ *
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4; /* temporary variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read inputs from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* negate the input */
+ in1 = -in1;
+ in2 = -in2;
+ in3 = -in3;
+ in4 = -in4;
+
+ /* store the result to destination */
+ *pDst = in1;
+ *(pDst + 1) = in2;
+ *(pDst + 2) = in3;
+ *(pDst + 3) = in4;
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the results in the destination buffer. */
+ *pDst++ = -*pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q15.c
new file mode 100644
index 000000000..b55e0cd60
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q15.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_negate_q15.c
+*
+* Description: Negates Q15 vectors.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * \par Conditions for optimum performance
+ * Input and output buffers should be aligned by 32-bit
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q15_t in;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in1, in2; /* Temporary variables */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Read two inputs at a time */
+ in1 = _SIMD32_OFFSET(pSrc);
+ in2 = _SIMD32_OFFSET(pSrc + 2);
+
+ /* negate two samples at a time */
+ in1 = __QSUB16(0, in1);
+
+ /* negate two samples at a time */
+ in2 = __QSUB16(0, in2);
+
+ /* store the result to destination 2 samples at a time */
+ _SIMD32_OFFSET(pDst) = in1;
+ /* store the result to destination 2 samples at a time */
+ _SIMD32_OFFSET(pDst + 2) = in2;
+
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the result in the destination buffer. */
+ in = *pSrc++;
+ *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q31.c
new file mode 100644
index 000000000..b0332e0cf
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q31.c
@@ -0,0 +1,129 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_negate_q31.c
+*
+* Description: Negates Q31 vectors.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t in; /* Temporary variable */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the results in the destination buffer. */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = __QSUB(0, in1);
+ *pDst++ = __QSUB(0, in2);
+ *pDst++ = __QSUB(0, in3);
+ *pDst++ = __QSUB(0, in4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the result in the destination buffer. */
+ in = *pSrc++;
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q7.c
new file mode 100644
index 000000000..9786c20d0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q7.c
@@ -0,0 +1,125 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_negate_q7.c
+*
+* Description: Negates Q7 vectors.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup negate
+ * @{
+ */
+
+/**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F.
+ */
+
+void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ q7_t in;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t input; /* Input values1-4 */
+ q31_t zero = 0x00000000;
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Read four inputs */
+ input = *__SIMD32(pSrc)++;
+
+ /* Store the Negated results in the destination buffer in a single cycle by packing the results */
+ *__SIMD32(pDst)++ = __QSUB8(zero, input);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = -A */
+ /* Negate and then store the results in the destination buffer. */ \
+ in = *pSrc++;
+ *pDst++ = (in == (q7_t) 0x80) ? 0x7f : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of negate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_f32.c
new file mode 100644
index 000000000..5efb45290
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_offset_f32.c
+*
+* Description: Floating-point vector offset.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup offset Vector Offset
+ *
+ * Adds a constant offset to each element of a vector.
+ *
+ * <pre>
+ * pDst[n] = pSrc[n] + offset, 0 <= n < blockSize.
+ * </pre>
+ *
+ * The functions support in-place computation allowing the source and
+ * destination pointers to reference the same memory buffer.
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+
+void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ /* read samples from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+
+ /* add offset to input */
+ in1 = in1 + offset;
+
+ /* read samples from source */
+ in3 = *(pSrc + 2);
+
+ /* add offset to input */
+ in2 = in2 + offset;
+
+ /* read samples from source */
+ in4 = *(pSrc + 3);
+
+ /* add offset to input */
+ in3 = in3 + offset;
+
+ /* store result to destination */
+ *pDst = in1;
+
+ /* add offset to input */
+ in4 = in4 + offset;
+
+ /* store result to destination */
+ *(pDst + 1) = in2;
+
+ /* store result to destination */
+ *(pDst + 2) = in3;
+
+ /* store result to destination */
+ *(pDst + 3) = in4;
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (*pSrc++) + offset;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q15.c
new file mode 100644
index 000000000..d64ae4962
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q15.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_offset_q15.c
+*
+* Description: Q15 vector offset.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.
+ */
+
+void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t offset_packed; /* Offset packed to 32 bit */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Offset is packed to 32 bit in order to use SIMD32 for addition */
+ offset_packed = __PKHBT(offset, offset, 16);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer, 2 samples at a time. */
+ *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
+ *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __QADD16(*pSrc++, offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q31.c
new file mode 100644
index 000000000..996241969
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q31.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_offset_q31.c
+*
+* Description: Q31 vector offset.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated.
+ */
+
+void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination buffer. */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = __QADD(in1, offset);
+ *pDst++ = __QADD(in2, offset);
+ *pDst++ = __QADD(in3, offset);
+ *pDst++ = __QADD(in4, offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = __QADD(*pSrc++, offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q7.c
new file mode 100644
index 000000000..1e68841d5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q7.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_offset_q7.c
+*
+* Description: Q7 vector offset.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup offset
+ * @{
+ */
+
+/**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] are saturated.
+ */
+
+void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t offset_packed; /* Offset packed to 32 bit */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Offset is packed to 32 bit in order to use SIMD32 for addition */
+ offset_packed = __PACKq7(offset, offset, offset, offset);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the results in the destination bufferfor 4 samples at a time. */
+ *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrc)++, offset_packed);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A + offset */
+ /* Add offset and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) * pSrc++ + offset, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of offset group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_f32.c
new file mode 100644
index 000000000..3e61ce563
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_f32.c
@@ -0,0 +1,169 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_scale_f32.c
+*
+* Description: Multiplies a floating-point vector by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup scale Vector Scale
+ *
+ * Multiply a vector by a scalar value. For floating-point data, the algorithm used is:
+ *
+ * <pre>
+ * pDst[n] = pSrc[n] * scale, 0 <= n < blockSize.
+ * </pre>
+ *
+ * In the fixed-point Q7, Q15, and Q31 functions, <code>scale</code> is represented by
+ * a fractional multiplication <code>scaleFract</code> and an arithmetic shift <code>shift</code>.
+ * The shift allows the gain of the scaling operation to exceed 1.0.
+ * The algorithm used with fixed-point data is:
+ *
+ * <pre>
+ * pDst[n] = (pSrc[n] * scaleFract) << shift, 0 <= n < blockSize.
+ * </pre>
+ *
+ * The overall scale factor applied to the fixed-point data is
+ * <pre>
+ * scale = scaleFract * 2^shift.
+ * </pre>
+ *
+ * The functions support in-place computation allowing the source and destination
+ * pointers to reference the same memory buffer.
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+
+void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4; /* temporary variabels */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the results in the destination buffer. */
+ /* read input samples from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+
+ /* multiply with scaling factor */
+ in1 = in1 * scale;
+
+ /* read input sample from source */
+ in3 = *(pSrc + 2);
+
+ /* multiply with scaling factor */
+ in2 = in2 * scale;
+
+ /* read input sample from source */
+ in4 = *(pSrc + 3);
+
+ /* multiply with scaling factor */
+ in3 = in3 * scale;
+ in4 = in4 * scale;
+ /* store the result to destination */
+ *pDst = in1;
+ *(pDst + 1) = in2;
+ *(pDst + 2) = in3;
+ *(pDst + 3) = in4;
+
+ /* update pointers to process next samples */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (*pSrc++) * scale;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q15.c
new file mode 100644
index 000000000..9b60a02c8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q15.c
@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_scale_q15.c
+*
+* Description: Multiplies a Q15 vector by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.15 format.
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.
+ */
+
+
+void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ int8_t kShift = 15 - shift; /* shift to apply after scaling */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q15_t in1, in2, in3, in4;
+ q31_t inA1, inA2; /* Temporary variables */
+ q31_t out1, out2, out3, out4;
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Reading 2 inputs from memory */
+ inA1 = *__SIMD32(pSrc)++;
+ inA2 = *__SIMD32(pSrc)++;
+
+ /* C = A * scale */
+ /* Scale the inputs and then store the 2 results in the destination buffer
+ * in single cycle by packing the outputs */
+ out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
+ out2 = (q31_t) ((q15_t) inA1 * scaleFract);
+ out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
+ out4 = (q31_t) ((q15_t) inA2 * scaleFract);
+
+ /* apply shifting */
+ out1 = out1 >> kShift;
+ out2 = out2 >> kShift;
+ out3 = out3 >> kShift;
+ out4 = out4 >> kShift;
+
+ /* saturate the output */
+ in1 = (q15_t) (__SSAT(out1, 16));
+ in2 = (q15_t) (__SSAT(out2, 16));
+ in3 = (q15_t) (__SSAT(out3, 16));
+ in4 = (q15_t) (__SSAT(out4, 16));
+
+ /* store the result to destination */
+ *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(in4, in3, 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q31.c
new file mode 100644
index 000000000..dec26f337
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q31.c
@@ -0,0 +1,239 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_scale_q31.c
+*
+* Description: Multiplies a Q31 vector by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.31 format.
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.
+ */
+
+void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ int8_t kShift = shift + 1; /* Shift to apply after scaling */
+ int8_t sign = (kShift & 0x80);
+ uint32_t blkCnt; /* loop counter */
+ q31_t in, out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in1, in2, in3, in4; /* temporary input variables */
+ q31_t out1, out2, out3, out4; /* temporary output variabels */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ if(sign == 0u)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read four inputs from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* multiply input with scaler value */
+ in1 = ((q63_t) in1 * scaleFract) >> 32;
+ in2 = ((q63_t) in2 * scaleFract) >> 32;
+ in3 = ((q63_t) in3 * scaleFract) >> 32;
+ in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+ /* apply shifting */
+ out1 = in1 << kShift;
+ out2 = in2 << kShift;
+
+ /* saturate the results. */
+ if(in1 != (out1 >> kShift))
+ out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+ if(in2 != (out2 >> kShift))
+ out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+ out3 = in3 << kShift;
+ out4 = in4 << kShift;
+
+ *pDst = out1;
+ *(pDst + 1) = out2;
+
+ if(in3 != (out3 >> kShift))
+ out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+ if(in4 != (out4 >> kShift))
+ out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+ /* Store result destination */
+ *(pDst + 2) = out3;
+ *(pDst + 3) = out4;
+
+ /* Update pointers to process next sampels */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ }
+ else
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read four inputs from source */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* multiply input with scaler value */
+ in1 = ((q63_t) in1 * scaleFract) >> 32;
+ in2 = ((q63_t) in2 * scaleFract) >> 32;
+ in3 = ((q63_t) in3 * scaleFract) >> 32;
+ in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+ /* apply shifting */
+ out1 = in1 >> -kShift;
+ out2 = in2 >> -kShift;
+
+ out3 = in3 >> -kShift;
+ out4 = in4 >> -kShift;
+
+ /* Store result destination */
+ *pDst = out1;
+ *(pDst + 1) = out2;
+
+ *(pDst + 2) = out3;
+ *(pDst + 3) = out4;
+
+ /* Update pointers to process next sampels */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ if(sign == 0)
+ {
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+
+ out = in << kShift;
+
+ if(in != (out >> kShift))
+ out = 0x7FFFFFFF ^ (in >> 31);
+
+ *pDst++ = out;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ in = *pSrc++;
+ in = ((q63_t) in * scaleFract) >> 32;
+
+ out = in >> -kShift;
+
+ *pDst++ = out;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ }
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q7.c
new file mode 100644
index 000000000..04e61b2e0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q7.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_scale_q7.c
+*
+* Description: Multiplies a Q7 vector by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup scale
+ * @{
+ */
+
+/**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.7 format.
+ * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format.
+ */
+
+void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ int8_t kShift = 7 - shift; /* shift to apply after scaling */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Reading 4 inputs from memory */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ /* C = A * scale */
+ /* Scale the inputs and then store the results in the temporary variables. */
+ out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8));
+ out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8));
+ out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8));
+ out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8));
+
+ /* Packing the individual outputs into 32bit and storing in
+ * destination buffer in single write */
+ *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A * scale */
+ /* Scale the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of scale group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q15.c
new file mode 100644
index 000000000..d04d79d59
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q15.c
@@ -0,0 +1,248 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_shift_q15.c
+*
+* Description: Shifts the elements of a Q15 vector by a specified number of bits.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup shift
+ * @{
+ */
+
+/**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ uint8_t sign; /* Sign of shiftBits */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t in1, in2; /* Temporary variables */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if(sign == 0u)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Read 2 inputs */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ /* C = A << shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
+ __SSAT((in2 << shiftBits), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
+ __SSAT((in1 << shiftBits), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16),
+ __SSAT((in2 << shiftBits), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16),
+ __SSAT((in1 << shiftBits), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift and then store the results in the destination buffer. */
+ *pDst++ = __SSAT((*pSrc++ << shiftBits), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Read 2 inputs */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+ /* C = A >> shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
+ (in2 >> -shiftBits), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
+ (in1 >> -shiftBits), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits),
+ (in2 >> -shiftBits), 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits),
+ (in1 >> -shiftBits), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+ *pDst++ = (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if(sign == 0u)
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift and then store the results in the destination buffer. */
+ *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the inputs and then store the results in the destination buffer. */
+ *pDst++ = (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of shift group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q31.c
new file mode 100644
index 000000000..bf7d6006e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q31.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_shift_q31.c
+*
+* Description: Shifts the elements of a Q31 vector by a specified number of bits.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+/**
+ * @defgroup shift Vector Shift
+ *
+ * Shifts the elements of a fixed-point vector by a specified number of bits.
+ * There are separate functions for Q7, Q15, and Q31 data types.
+ * The underlying algorithm used is:
+ *
+ * <pre>
+ * pDst[n] = pSrc[n] << shift, 0 <= n < blockSize.
+ * </pre>
+ *
+ * If <code>shift</code> is positive then the elements of the vector are shifted to the left.
+ * If <code>shift</code> is negative then the elements of the vector are shifted to the right.
+ *
+ * The functions support in-place computation allowing the source and destination
+ * pointers to reference the same memory buffer.
+ */
+
+/**
+ * @addtogroup shift
+ * @{
+ */
+
+/**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t in1, in2, in3, in4; /* Temporary input variables */
+ q31_t out1, out2, out3, out4; /* Temporary output variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+
+ if(sign == 0u)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift the input and then store the results in the destination buffer. */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ out1 = in1 << shiftBits;
+ in3 = *(pSrc + 2);
+ out2 = in2 << shiftBits;
+ in4 = *(pSrc + 3);
+ if(in1 != (out1 >> shiftBits))
+ out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+ if(in2 != (out2 >> shiftBits))
+ out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+ *pDst = out1;
+ out3 = in3 << shiftBits;
+ *(pDst + 1) = out2;
+ out4 = in4 << shiftBits;
+
+ if(in3 != (out3 >> shiftBits))
+ out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+ if(in4 != (out4 >> shiftBits))
+ out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+ *(pDst + 2) = out3;
+ *(pDst + 3) = out4;
+
+ /* Update destination pointer to process next sampels */
+ pSrc += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the input and then store the results in the destination buffer. */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ *pDst = (in1 >> -shiftBits);
+ *(pDst + 1) = (in2 >> -shiftBits);
+ *(pDst + 2) = (in3 >> -shiftBits);
+ *(pDst + 3) = (in4 >> -shiftBits);
+
+
+ pSrc += 4u;
+ pDst += 4u;
+
+ blkCnt--;
+ }
+
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A (>> or <<) shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) :
+ (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+}
+
+/**
+ * @} end of shift group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q7.c
new file mode 100644
index 000000000..3d7752afa
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q7.c
@@ -0,0 +1,220 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_shift_q7.c
+*
+* Description: Processing function for the Q7 Shifting
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup shift
+ * @{
+ */
+
+
+/**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ *
+ * \par Conditions for optimum performance
+ * Input and output buffers should be aligned by 32-bit
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated.
+ */
+
+void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+ uint8_t sign; /* Sign of shiftBits */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q7_t in1; /* Input value1 */
+ q7_t in2; /* Input value2 */
+ q7_t in3; /* Input value3 */
+ q7_t in4; /* Input value4 */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if(sign == 0u)
+ {
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Read 4 inputs */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
+ *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8),
+ __SSAT((in2 << shiftBits), 8),
+ __SSAT((in3 << shiftBits), 8),
+ __SSAT((in4 << shiftBits), 8));
+ /* Update source pointer to process next sampels */
+ pSrc += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ shiftBits = -shiftBits;
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Read 4 inputs */
+ in1 = *pSrc;
+ in2 = *(pSrc + 1);
+ in3 = *(pSrc + 2);
+ in4 = *(pSrc + 3);
+
+ /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
+ *__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits),
+ (in3 >> shiftBits), (in4 >> shiftBits));
+
+
+ pSrc += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ in1 = *pSrc++;
+ *pDst++ = (in1 >> shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Getting the sign of shiftBits */
+ sign = (shiftBits & 0x80);
+
+ /* If the shift value is positive then do right shift else left shift */
+ if(sign == 0u)
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A << shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A >> shiftBits */
+ /* Shift the input and then store the result in the destination buffer. */
+ *pDst++ = (*pSrc++ >> -shiftBits);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
+
+/**
+ * @} end of shift group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_f32.c
new file mode 100644
index 000000000..b981f4e48
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_f32.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sub_f32.c
+*
+* Description: Floating-point vector subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @defgroup BasicSub Vector Subtraction
+ *
+ * Element-by-element subtraction of two vectors.
+ *
+ * <pre>
+ * pDst[n] = pSrcA[n] - pSrcB[n], 0 <= n < blockSize.
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* temporary variables */
+ float32_t inB1, inB2, inB3, inB4; /* temporary variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer. */
+ /* Read 4 input samples from sourceA and sourceB */
+ inA1 = *pSrcA;
+ inB1 = *pSrcB;
+ inA2 = *(pSrcA + 1);
+ inB2 = *(pSrcB + 1);
+ inA3 = *(pSrcA + 2);
+ inB3 = *(pSrcB + 2);
+ inA4 = *(pSrcA + 3);
+ inB4 = *(pSrcB + 3);
+
+ /* dst = srcA - srcB */
+ /* subtract and store the result */
+ *pDst = inA1 - inB1;
+ *(pDst + 1) = inA2 - inB2;
+ *(pDst + 2) = inA3 - inB3;
+ *(pDst + 3) = inA4 - inB4;
+
+
+ /* Update pointers to process next sampels */
+ pSrcA += 4u;
+ pSrcB += 4u;
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer. */
+ *pDst++ = (*pSrcA++) - (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q15.c
new file mode 100644
index 000000000..76f418368
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q15.c
@@ -0,0 +1,140 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sub_q15.c
+*
+* Description: Q15 vector subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+/**
+ * @brief Q15 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2;
+ q31_t inB1, inB2;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer two samples at a time. */
+ inA1 = *__SIMD32(pSrcA)++;
+ inA2 = *__SIMD32(pSrcA)++;
+ inB1 = *__SIMD32(pSrcB)++;
+ inB2 = *__SIMD32(pSrcB)++;
+
+ *__SIMD32(pDst)++ = __QSUB16(inA1, inB1);
+ *__SIMD32(pDst)++ = __QSUB16(inA2, inB2);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q31.c
new file mode 100644
index 000000000..62e1d4f9b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q31.c
@@ -0,0 +1,146 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sub_q31.c
+*
+* Description: Q31 vector subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+/**
+ * @brief Q31 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inA1, inA2, inA3, inA4;
+ q31_t inB1, inB2, inB3, inB4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer. */
+ inA1 = *pSrcA++;
+ inA2 = *pSrcA++;
+ inB1 = *pSrcB++;
+ inB2 = *pSrcB++;
+
+ inA3 = *pSrcA++;
+ inA4 = *pSrcA++;
+ inB3 = *pSrcB++;
+ inB4 = *pSrcB++;
+
+ *pDst++ = __QSUB(inA1, inB1);
+ *pDst++ = __QSUB(inA2, inB2);
+ *pDst++ = __QSUB(inA3, inB3);
+ *pDst++ = __QSUB(inA4, inB4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = __QSUB(*pSrcA++, *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ - *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q7.c
new file mode 100644
index 000000000..c24fd8691
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q7.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sub_q7.c
+*
+* Description: Q7 vector subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMath
+ */
+
+/**
+ * @addtogroup BasicSub
+ * @{
+ */
+
+/**
+ * @brief Q7 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ */
+
+void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the results in the destination buffer 4 samples at a time. */
+ *__SIMD32(pDst)++ = __QSUB8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = __SSAT(*pSrcA++ - *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A - B */
+ /* Subtract and then store the result in the destination buffer. */
+ *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ - *pSrcB++, 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of BasicSub group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/CommonTables/arm_common_tables.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/CommonTables/arm_common_tables.c
new file mode 100644
index 000000000..a4e784d18
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/CommonTables/arm_common_tables.c
@@ -0,0 +1,16065 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.c
+*
+* Description: This file has common tables like fft twiddle factors, Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup CFFT_CIFFT Complex FFT Tables
+ * @{
+ */
+
+/**
+* \par
+* Pseudo code for Generation of Bit reversal Table is
+* \par
+* <pre>for(l=1;l <= N/4;l++)
+* {
+* for(i=0;i<logN2;i++)
+* {
+* a[i]=l&(1<<i);
+* }
+* for(j=0; j<logN2; j++)
+* {
+* if (a[j]!=0)
+* y[l]+=(1<<((logN2-1)-j));
+* }
+* y[l] = y[l] >> 1;
+* } </pre>
+* \par
+* where N = 4096 logN2 = 12
+* \par
+* N is the maximum FFT Size supported
+*/
+
+/*
+* @brief Table for bit reversal process
+*/
+const uint16_t armBitRevTable[1024] = {
+ 0x400, 0x200, 0x600, 0x100, 0x500, 0x300, 0x700,
+ 0x80, 0x480, 0x280, 0x680, 0x180, 0x580, 0x380,
+ 0x780, 0x40, 0x440, 0x240, 0x640, 0x140, 0x540,
+ 0x340, 0x740, 0xc0, 0x4c0, 0x2c0, 0x6c0, 0x1c0,
+ 0x5c0, 0x3c0, 0x7c0, 0x20, 0x420, 0x220, 0x620,
+ 0x120, 0x520, 0x320, 0x720, 0xa0, 0x4a0, 0x2a0,
+ 0x6a0, 0x1a0, 0x5a0, 0x3a0, 0x7a0, 0x60, 0x460,
+ 0x260, 0x660, 0x160, 0x560, 0x360, 0x760, 0xe0,
+ 0x4e0, 0x2e0, 0x6e0, 0x1e0, 0x5e0, 0x3e0, 0x7e0,
+ 0x10, 0x410, 0x210, 0x610, 0x110, 0x510, 0x310,
+ 0x710, 0x90, 0x490, 0x290, 0x690, 0x190, 0x590,
+ 0x390, 0x790, 0x50, 0x450, 0x250, 0x650, 0x150,
+ 0x550, 0x350, 0x750, 0xd0, 0x4d0, 0x2d0, 0x6d0,
+ 0x1d0, 0x5d0, 0x3d0, 0x7d0, 0x30, 0x430, 0x230,
+ 0x630, 0x130, 0x530, 0x330, 0x730, 0xb0, 0x4b0,
+ 0x2b0, 0x6b0, 0x1b0, 0x5b0, 0x3b0, 0x7b0, 0x70,
+ 0x470, 0x270, 0x670, 0x170, 0x570, 0x370, 0x770,
+ 0xf0, 0x4f0, 0x2f0, 0x6f0, 0x1f0, 0x5f0, 0x3f0,
+ 0x7f0, 0x8, 0x408, 0x208, 0x608, 0x108, 0x508,
+ 0x308, 0x708, 0x88, 0x488, 0x288, 0x688, 0x188,
+ 0x588, 0x388, 0x788, 0x48, 0x448, 0x248, 0x648,
+ 0x148, 0x548, 0x348, 0x748, 0xc8, 0x4c8, 0x2c8,
+ 0x6c8, 0x1c8, 0x5c8, 0x3c8, 0x7c8, 0x28, 0x428,
+ 0x228, 0x628, 0x128, 0x528, 0x328, 0x728, 0xa8,
+ 0x4a8, 0x2a8, 0x6a8, 0x1a8, 0x5a8, 0x3a8, 0x7a8,
+ 0x68, 0x468, 0x268, 0x668, 0x168, 0x568, 0x368,
+ 0x768, 0xe8, 0x4e8, 0x2e8, 0x6e8, 0x1e8, 0x5e8,
+ 0x3e8, 0x7e8, 0x18, 0x418, 0x218, 0x618, 0x118,
+ 0x518, 0x318, 0x718, 0x98, 0x498, 0x298, 0x698,
+ 0x198, 0x598, 0x398, 0x798, 0x58, 0x458, 0x258,
+ 0x658, 0x158, 0x558, 0x358, 0x758, 0xd8, 0x4d8,
+ 0x2d8, 0x6d8, 0x1d8, 0x5d8, 0x3d8, 0x7d8, 0x38,
+ 0x438, 0x238, 0x638, 0x138, 0x538, 0x338, 0x738,
+ 0xb8, 0x4b8, 0x2b8, 0x6b8, 0x1b8, 0x5b8, 0x3b8,
+ 0x7b8, 0x78, 0x478, 0x278, 0x678, 0x178, 0x578,
+ 0x378, 0x778, 0xf8, 0x4f8, 0x2f8, 0x6f8, 0x1f8,
+ 0x5f8, 0x3f8, 0x7f8, 0x4, 0x404, 0x204, 0x604,
+ 0x104, 0x504, 0x304, 0x704, 0x84, 0x484, 0x284,
+ 0x684, 0x184, 0x584, 0x384, 0x784, 0x44, 0x444,
+ 0x244, 0x644, 0x144, 0x544, 0x344, 0x744, 0xc4,
+ 0x4c4, 0x2c4, 0x6c4, 0x1c4, 0x5c4, 0x3c4, 0x7c4,
+ 0x24, 0x424, 0x224, 0x624, 0x124, 0x524, 0x324,
+ 0x724, 0xa4, 0x4a4, 0x2a4, 0x6a4, 0x1a4, 0x5a4,
+ 0x3a4, 0x7a4, 0x64, 0x464, 0x264, 0x664, 0x164,
+ 0x564, 0x364, 0x764, 0xe4, 0x4e4, 0x2e4, 0x6e4,
+ 0x1e4, 0x5e4, 0x3e4, 0x7e4, 0x14, 0x414, 0x214,
+ 0x614, 0x114, 0x514, 0x314, 0x714, 0x94, 0x494,
+ 0x294, 0x694, 0x194, 0x594, 0x394, 0x794, 0x54,
+ 0x454, 0x254, 0x654, 0x154, 0x554, 0x354, 0x754,
+ 0xd4, 0x4d4, 0x2d4, 0x6d4, 0x1d4, 0x5d4, 0x3d4,
+ 0x7d4, 0x34, 0x434, 0x234, 0x634, 0x134, 0x534,
+ 0x334, 0x734, 0xb4, 0x4b4, 0x2b4, 0x6b4, 0x1b4,
+ 0x5b4, 0x3b4, 0x7b4, 0x74, 0x474, 0x274, 0x674,
+ 0x174, 0x574, 0x374, 0x774, 0xf4, 0x4f4, 0x2f4,
+ 0x6f4, 0x1f4, 0x5f4, 0x3f4, 0x7f4, 0xc, 0x40c,
+ 0x20c, 0x60c, 0x10c, 0x50c, 0x30c, 0x70c, 0x8c,
+ 0x48c, 0x28c, 0x68c, 0x18c, 0x58c, 0x38c, 0x78c,
+ 0x4c, 0x44c, 0x24c, 0x64c, 0x14c, 0x54c, 0x34c,
+ 0x74c, 0xcc, 0x4cc, 0x2cc, 0x6cc, 0x1cc, 0x5cc,
+ 0x3cc, 0x7cc, 0x2c, 0x42c, 0x22c, 0x62c, 0x12c,
+ 0x52c, 0x32c, 0x72c, 0xac, 0x4ac, 0x2ac, 0x6ac,
+ 0x1ac, 0x5ac, 0x3ac, 0x7ac, 0x6c, 0x46c, 0x26c,
+ 0x66c, 0x16c, 0x56c, 0x36c, 0x76c, 0xec, 0x4ec,
+ 0x2ec, 0x6ec, 0x1ec, 0x5ec, 0x3ec, 0x7ec, 0x1c,
+ 0x41c, 0x21c, 0x61c, 0x11c, 0x51c, 0x31c, 0x71c,
+ 0x9c, 0x49c, 0x29c, 0x69c, 0x19c, 0x59c, 0x39c,
+ 0x79c, 0x5c, 0x45c, 0x25c, 0x65c, 0x15c, 0x55c,
+ 0x35c, 0x75c, 0xdc, 0x4dc, 0x2dc, 0x6dc, 0x1dc,
+ 0x5dc, 0x3dc, 0x7dc, 0x3c, 0x43c, 0x23c, 0x63c,
+ 0x13c, 0x53c, 0x33c, 0x73c, 0xbc, 0x4bc, 0x2bc,
+ 0x6bc, 0x1bc, 0x5bc, 0x3bc, 0x7bc, 0x7c, 0x47c,
+ 0x27c, 0x67c, 0x17c, 0x57c, 0x37c, 0x77c, 0xfc,
+ 0x4fc, 0x2fc, 0x6fc, 0x1fc, 0x5fc, 0x3fc, 0x7fc,
+ 0x2, 0x402, 0x202, 0x602, 0x102, 0x502, 0x302,
+ 0x702, 0x82, 0x482, 0x282, 0x682, 0x182, 0x582,
+ 0x382, 0x782, 0x42, 0x442, 0x242, 0x642, 0x142,
+ 0x542, 0x342, 0x742, 0xc2, 0x4c2, 0x2c2, 0x6c2,
+ 0x1c2, 0x5c2, 0x3c2, 0x7c2, 0x22, 0x422, 0x222,
+ 0x622, 0x122, 0x522, 0x322, 0x722, 0xa2, 0x4a2,
+ 0x2a2, 0x6a2, 0x1a2, 0x5a2, 0x3a2, 0x7a2, 0x62,
+ 0x462, 0x262, 0x662, 0x162, 0x562, 0x362, 0x762,
+ 0xe2, 0x4e2, 0x2e2, 0x6e2, 0x1e2, 0x5e2, 0x3e2,
+ 0x7e2, 0x12, 0x412, 0x212, 0x612, 0x112, 0x512,
+ 0x312, 0x712, 0x92, 0x492, 0x292, 0x692, 0x192,
+ 0x592, 0x392, 0x792, 0x52, 0x452, 0x252, 0x652,
+ 0x152, 0x552, 0x352, 0x752, 0xd2, 0x4d2, 0x2d2,
+ 0x6d2, 0x1d2, 0x5d2, 0x3d2, 0x7d2, 0x32, 0x432,
+ 0x232, 0x632, 0x132, 0x532, 0x332, 0x732, 0xb2,
+ 0x4b2, 0x2b2, 0x6b2, 0x1b2, 0x5b2, 0x3b2, 0x7b2,
+ 0x72, 0x472, 0x272, 0x672, 0x172, 0x572, 0x372,
+ 0x772, 0xf2, 0x4f2, 0x2f2, 0x6f2, 0x1f2, 0x5f2,
+ 0x3f2, 0x7f2, 0xa, 0x40a, 0x20a, 0x60a, 0x10a,
+ 0x50a, 0x30a, 0x70a, 0x8a, 0x48a, 0x28a, 0x68a,
+ 0x18a, 0x58a, 0x38a, 0x78a, 0x4a, 0x44a, 0x24a,
+ 0x64a, 0x14a, 0x54a, 0x34a, 0x74a, 0xca, 0x4ca,
+ 0x2ca, 0x6ca, 0x1ca, 0x5ca, 0x3ca, 0x7ca, 0x2a,
+ 0x42a, 0x22a, 0x62a, 0x12a, 0x52a, 0x32a, 0x72a,
+ 0xaa, 0x4aa, 0x2aa, 0x6aa, 0x1aa, 0x5aa, 0x3aa,
+ 0x7aa, 0x6a, 0x46a, 0x26a, 0x66a, 0x16a, 0x56a,
+ 0x36a, 0x76a, 0xea, 0x4ea, 0x2ea, 0x6ea, 0x1ea,
+ 0x5ea, 0x3ea, 0x7ea, 0x1a, 0x41a, 0x21a, 0x61a,
+ 0x11a, 0x51a, 0x31a, 0x71a, 0x9a, 0x49a, 0x29a,
+ 0x69a, 0x19a, 0x59a, 0x39a, 0x79a, 0x5a, 0x45a,
+ 0x25a, 0x65a, 0x15a, 0x55a, 0x35a, 0x75a, 0xda,
+ 0x4da, 0x2da, 0x6da, 0x1da, 0x5da, 0x3da, 0x7da,
+ 0x3a, 0x43a, 0x23a, 0x63a, 0x13a, 0x53a, 0x33a,
+ 0x73a, 0xba, 0x4ba, 0x2ba, 0x6ba, 0x1ba, 0x5ba,
+ 0x3ba, 0x7ba, 0x7a, 0x47a, 0x27a, 0x67a, 0x17a,
+ 0x57a, 0x37a, 0x77a, 0xfa, 0x4fa, 0x2fa, 0x6fa,
+ 0x1fa, 0x5fa, 0x3fa, 0x7fa, 0x6, 0x406, 0x206,
+ 0x606, 0x106, 0x506, 0x306, 0x706, 0x86, 0x486,
+ 0x286, 0x686, 0x186, 0x586, 0x386, 0x786, 0x46,
+ 0x446, 0x246, 0x646, 0x146, 0x546, 0x346, 0x746,
+ 0xc6, 0x4c6, 0x2c6, 0x6c6, 0x1c6, 0x5c6, 0x3c6,
+ 0x7c6, 0x26, 0x426, 0x226, 0x626, 0x126, 0x526,
+ 0x326, 0x726, 0xa6, 0x4a6, 0x2a6, 0x6a6, 0x1a6,
+ 0x5a6, 0x3a6, 0x7a6, 0x66, 0x466, 0x266, 0x666,
+ 0x166, 0x566, 0x366, 0x766, 0xe6, 0x4e6, 0x2e6,
+ 0x6e6, 0x1e6, 0x5e6, 0x3e6, 0x7e6, 0x16, 0x416,
+ 0x216, 0x616, 0x116, 0x516, 0x316, 0x716, 0x96,
+ 0x496, 0x296, 0x696, 0x196, 0x596, 0x396, 0x796,
+ 0x56, 0x456, 0x256, 0x656, 0x156, 0x556, 0x356,
+ 0x756, 0xd6, 0x4d6, 0x2d6, 0x6d6, 0x1d6, 0x5d6,
+ 0x3d6, 0x7d6, 0x36, 0x436, 0x236, 0x636, 0x136,
+ 0x536, 0x336, 0x736, 0xb6, 0x4b6, 0x2b6, 0x6b6,
+ 0x1b6, 0x5b6, 0x3b6, 0x7b6, 0x76, 0x476, 0x276,
+ 0x676, 0x176, 0x576, 0x376, 0x776, 0xf6, 0x4f6,
+ 0x2f6, 0x6f6, 0x1f6, 0x5f6, 0x3f6, 0x7f6, 0xe,
+ 0x40e, 0x20e, 0x60e, 0x10e, 0x50e, 0x30e, 0x70e,
+ 0x8e, 0x48e, 0x28e, 0x68e, 0x18e, 0x58e, 0x38e,
+ 0x78e, 0x4e, 0x44e, 0x24e, 0x64e, 0x14e, 0x54e,
+ 0x34e, 0x74e, 0xce, 0x4ce, 0x2ce, 0x6ce, 0x1ce,
+ 0x5ce, 0x3ce, 0x7ce, 0x2e, 0x42e, 0x22e, 0x62e,
+ 0x12e, 0x52e, 0x32e, 0x72e, 0xae, 0x4ae, 0x2ae,
+ 0x6ae, 0x1ae, 0x5ae, 0x3ae, 0x7ae, 0x6e, 0x46e,
+ 0x26e, 0x66e, 0x16e, 0x56e, 0x36e, 0x76e, 0xee,
+ 0x4ee, 0x2ee, 0x6ee, 0x1ee, 0x5ee, 0x3ee, 0x7ee,
+ 0x1e, 0x41e, 0x21e, 0x61e, 0x11e, 0x51e, 0x31e,
+ 0x71e, 0x9e, 0x49e, 0x29e, 0x69e, 0x19e, 0x59e,
+ 0x39e, 0x79e, 0x5e, 0x45e, 0x25e, 0x65e, 0x15e,
+ 0x55e, 0x35e, 0x75e, 0xde, 0x4de, 0x2de, 0x6de,
+ 0x1de, 0x5de, 0x3de, 0x7de, 0x3e, 0x43e, 0x23e,
+ 0x63e, 0x13e, 0x53e, 0x33e, 0x73e, 0xbe, 0x4be,
+ 0x2be, 0x6be, 0x1be, 0x5be, 0x3be, 0x7be, 0x7e,
+ 0x47e, 0x27e, 0x67e, 0x17e, 0x57e, 0x37e, 0x77e,
+ 0xfe, 0x4fe, 0x2fe, 0x6fe, 0x1fe, 0x5fe, 0x3fe,
+ 0x7fe, 0x1
+};
+
+
+/*
+* @brief Floating-point Twiddle factors Table Generation
+*/
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_16[32] = {
+ 1.000000000f, 0.000000000f,
+ 0.923879533f, 0.382683432f,
+ 0.707106781f, 0.707106781f,
+ 0.382683432f, 0.923879533f,
+ 0.000000000f, 1.000000000f,
+ -0.382683432f, 0.923879533f,
+ -0.707106781f, 0.707106781f,
+ -0.923879533f, 0.382683432f,
+ -1.000000000f, 0.000000000f,
+ -0.923879533f, -0.382683432f,
+ -0.707106781f, -0.707106781f,
+ -0.382683432f, -0.923879533f,
+ -0.000000000f, -1.000000000f,
+ 0.382683432f, -0.923879533f,
+ 0.707106781f, -0.707106781f,
+ 0.923879533f, -0.382683432f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_32[64] = {
+ 1.000000000f, 0.000000000f,
+ 0.980785280f, 0.195090322f,
+ 0.923879533f, 0.382683432f,
+ 0.831469612f, 0.555570233f,
+ 0.707106781f, 0.707106781f,
+ 0.555570233f, 0.831469612f,
+ 0.382683432f, 0.923879533f,
+ 0.195090322f, 0.980785280f,
+ 0.000000000f, 1.000000000f,
+ -0.195090322f, 0.980785280f,
+ -0.382683432f, 0.923879533f,
+ -0.555570233f, 0.831469612f,
+ -0.707106781f, 0.707106781f,
+ -0.831469612f, 0.555570233f,
+ -0.923879533f, 0.382683432f,
+ -0.980785280f, 0.195090322f,
+ -1.000000000f, 0.000000000f,
+ -0.980785280f, -0.195090322f,
+ -0.923879533f, -0.382683432f,
+ -0.831469612f, -0.555570233f,
+ -0.707106781f, -0.707106781f,
+ -0.555570233f, -0.831469612f,
+ -0.382683432f, -0.923879533f,
+ -0.195090322f, -0.980785280f,
+ -0.000000000f, -1.000000000f,
+ 0.195090322f, -0.980785280f,
+ 0.382683432f, -0.923879533f,
+ 0.555570233f, -0.831469612f,
+ 0.707106781f, -0.707106781f,
+ 0.831469612f, -0.555570233f,
+ 0.923879533f, -0.382683432f,
+ 0.980785280f, -0.195090322f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_64[128] = {
+ 1.000000000f, 0.000000000f,
+ 0.995184727f, 0.098017140f,
+ 0.980785280f, 0.195090322f,
+ 0.956940336f, 0.290284677f,
+ 0.923879533f, 0.382683432f,
+ 0.881921264f, 0.471396737f,
+ 0.831469612f, 0.555570233f,
+ 0.773010453f, 0.634393284f,
+ 0.707106781f, 0.707106781f,
+ 0.634393284f, 0.773010453f,
+ 0.555570233f, 0.831469612f,
+ 0.471396737f, 0.881921264f,
+ 0.382683432f, 0.923879533f,
+ 0.290284677f, 0.956940336f,
+ 0.195090322f, 0.980785280f,
+ 0.098017140f, 0.995184727f,
+ 0.000000000f, 1.000000000f,
+ -0.098017140f, 0.995184727f,
+ -0.195090322f, 0.980785280f,
+ -0.290284677f, 0.956940336f,
+ -0.382683432f, 0.923879533f,
+ -0.471396737f, 0.881921264f,
+ -0.555570233f, 0.831469612f,
+ -0.634393284f, 0.773010453f,
+ -0.707106781f, 0.707106781f,
+ -0.773010453f, 0.634393284f,
+ -0.831469612f, 0.555570233f,
+ -0.881921264f, 0.471396737f,
+ -0.923879533f, 0.382683432f,
+ -0.956940336f, 0.290284677f,
+ -0.980785280f, 0.195090322f,
+ -0.995184727f, 0.098017140f,
+ -1.000000000f, 0.000000000f,
+ -0.995184727f, -0.098017140f,
+ -0.980785280f, -0.195090322f,
+ -0.956940336f, -0.290284677f,
+ -0.923879533f, -0.382683432f,
+ -0.881921264f, -0.471396737f,
+ -0.831469612f, -0.555570233f,
+ -0.773010453f, -0.634393284f,
+ -0.707106781f, -0.707106781f,
+ -0.634393284f, -0.773010453f,
+ -0.555570233f, -0.831469612f,
+ -0.471396737f, -0.881921264f,
+ -0.382683432f, -0.923879533f,
+ -0.290284677f, -0.956940336f,
+ -0.195090322f, -0.980785280f,
+ -0.098017140f, -0.995184727f,
+ -0.000000000f, -1.000000000f,
+ 0.098017140f, -0.995184727f,
+ 0.195090322f, -0.980785280f,
+ 0.290284677f, -0.956940336f,
+ 0.382683432f, -0.923879533f,
+ 0.471396737f, -0.881921264f,
+ 0.555570233f, -0.831469612f,
+ 0.634393284f, -0.773010453f,
+ 0.707106781f, -0.707106781f,
+ 0.773010453f, -0.634393284f,
+ 0.831469612f, -0.555570233f,
+ 0.881921264f, -0.471396737f,
+ 0.923879533f, -0.382683432f,
+ 0.956940336f, -0.290284677f,
+ 0.980785280f, -0.195090322f,
+ 0.995184727f, -0.098017140f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+
+const float32_t twiddleCoef_128[256] = {
+1.000000000f , 0.000000000f ,
+0.998795456f , 0.049067674f ,
+0.995184727f , 0.098017140f ,
+0.989176510f , 0.146730474f ,
+0.980785280f , 0.195090322f ,
+0.970031253f , 0.242980180f ,
+0.956940336f , 0.290284677f ,
+0.941544065f , 0.336889853f ,
+0.923879533f , 0.382683432f ,
+0.903989293f , 0.427555093f ,
+0.881921264f , 0.471396737f ,
+0.857728610f , 0.514102744f ,
+0.831469612f , 0.555570233f ,
+0.803207531f , 0.595699304f ,
+0.773010453f , 0.634393284f ,
+0.740951125f , 0.671558955f ,
+0.707106781f , 0.707106781f ,
+0.671558955f , 0.740951125f ,
+0.634393284f , 0.773010453f ,
+0.595699304f , 0.803207531f ,
+0.555570233f , 0.831469612f ,
+0.514102744f , 0.857728610f ,
+0.471396737f , 0.881921264f ,
+0.427555093f , 0.903989293f ,
+0.382683432f , 0.923879533f ,
+0.336889853f , 0.941544065f ,
+0.290284677f , 0.956940336f ,
+0.242980180f , 0.970031253f ,
+0.195090322f , 0.980785280f ,
+0.146730474f , 0.989176510f ,
+0.098017140f , 0.995184727f ,
+0.049067674f , 0.998795456f ,
+0.000000000f , 1.000000000f ,
+-0.049067674f , 0.998795456f ,
+-0.098017140f , 0.995184727f ,
+-0.146730474f , 0.989176510f ,
+-0.195090322f , 0.980785280f ,
+-0.242980180f , 0.970031253f ,
+-0.290284677f , 0.956940336f ,
+-0.336889853f , 0.941544065f ,
+-0.382683432f , 0.923879533f ,
+-0.427555093f , 0.903989293f ,
+-0.471396737f , 0.881921264f ,
+-0.514102744f , 0.857728610f ,
+-0.555570233f , 0.831469612f ,
+-0.595699304f , 0.803207531f ,
+-0.634393284f , 0.773010453f ,
+-0.671558955f , 0.740951125f ,
+-0.707106781f , 0.707106781f ,
+-0.740951125f , 0.671558955f ,
+-0.773010453f , 0.634393284f ,
+-0.803207531f , 0.595699304f ,
+-0.831469612f , 0.555570233f ,
+-0.857728610f , 0.514102744f ,
+-0.881921264f , 0.471396737f ,
+-0.903989293f , 0.427555093f ,
+-0.923879533f , 0.382683432f ,
+-0.941544065f , 0.336889853f ,
+-0.956940336f , 0.290284677f ,
+-0.970031253f , 0.242980180f ,
+-0.980785280f , 0.195090322f ,
+-0.989176510f , 0.146730474f ,
+-0.995184727f , 0.098017140f ,
+-0.998795456f , 0.049067674f ,
+-1.000000000f , 0.000000000f ,
+-0.998795456f , -0.049067674f ,
+-0.995184727f , -0.098017140f ,
+-0.989176510f , -0.146730474f ,
+-0.980785280f , -0.195090322f ,
+-0.970031253f , -0.242980180f ,
+-0.956940336f , -0.290284677f ,
+-0.941544065f , -0.336889853f ,
+-0.923879533f , -0.382683432f ,
+-0.903989293f , -0.427555093f ,
+-0.881921264f , -0.471396737f ,
+-0.857728610f , -0.514102744f ,
+-0.831469612f , -0.555570233f ,
+-0.803207531f , -0.595699304f ,
+-0.773010453f , -0.634393284f ,
+-0.740951125f , -0.671558955f ,
+-0.707106781f , -0.707106781f ,
+-0.671558955f , -0.740951125f ,
+-0.634393284f , -0.773010453f ,
+-0.595699304f , -0.803207531f ,
+-0.555570233f , -0.831469612f ,
+-0.514102744f , -0.857728610f ,
+-0.471396737f , -0.881921264f ,
+-0.427555093f , -0.903989293f ,
+-0.382683432f , -0.923879533f ,
+-0.336889853f , -0.941544065f ,
+-0.290284677f , -0.956940336f ,
+-0.242980180f , -0.970031253f ,
+-0.195090322f , -0.980785280f ,
+-0.146730474f , -0.989176510f ,
+-0.098017140f , -0.995184727f ,
+-0.049067674f , -0.998795456f ,
+-0.000000000f , -1.000000000f ,
+0.049067674f , -0.998795456f ,
+0.098017140f , -0.995184727f ,
+0.146730474f , -0.989176510f ,
+0.195090322f , -0.980785280f ,
+0.242980180f , -0.970031253f ,
+0.290284677f , -0.956940336f ,
+0.336889853f , -0.941544065f ,
+0.382683432f , -0.923879533f ,
+0.427555093f , -0.903989293f ,
+0.471396737f , -0.881921264f ,
+0.514102744f , -0.857728610f ,
+0.555570233f , -0.831469612f ,
+0.595699304f , -0.803207531f ,
+0.634393284f , -0.773010453f ,
+0.671558955f , -0.740951125f ,
+0.707106781f , -0.707106781f ,
+0.740951125f , -0.671558955f ,
+0.773010453f , -0.634393284f ,
+0.803207531f , -0.595699304f ,
+0.831469612f , -0.555570233f ,
+0.857728610f , -0.514102744f ,
+0.881921264f , -0.471396737f ,
+0.903989293f , -0.427555093f ,
+0.923879533f , -0.382683432f ,
+0.941544065f , -0.336889853f ,
+0.956940336f , -0.290284677f ,
+0.970031253f , -0.242980180f ,
+0.980785280f , -0.195090322f ,
+0.989176510f , -0.146730474f ,
+0.995184727f , -0.098017140f ,
+0.998795456f , -0.049067674f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_256[512] = {
+ 1.000000000f, 0.000000000f,
+ 0.999698819f, 0.024541229f,
+ 0.998795456f, 0.049067674f,
+ 0.997290457f, 0.073564564f,
+ 0.995184727f, 0.098017140f,
+ 0.992479535f, 0.122410675f,
+ 0.989176510f, 0.146730474f,
+ 0.985277642f, 0.170961889f,
+ 0.980785280f, 0.195090322f,
+ 0.975702130f, 0.219101240f,
+ 0.970031253f, 0.242980180f,
+ 0.963776066f, 0.266712757f,
+ 0.956940336f, 0.290284677f,
+ 0.949528181f, 0.313681740f,
+ 0.941544065f, 0.336889853f,
+ 0.932992799f, 0.359895037f,
+ 0.923879533f, 0.382683432f,
+ 0.914209756f, 0.405241314f,
+ 0.903989293f, 0.427555093f,
+ 0.893224301f, 0.449611330f,
+ 0.881921264f, 0.471396737f,
+ 0.870086991f, 0.492898192f,
+ 0.857728610f, 0.514102744f,
+ 0.844853565f, 0.534997620f,
+ 0.831469612f, 0.555570233f,
+ 0.817584813f, 0.575808191f,
+ 0.803207531f, 0.595699304f,
+ 0.788346428f, 0.615231591f,
+ 0.773010453f, 0.634393284f,
+ 0.757208847f, 0.653172843f,
+ 0.740951125f, 0.671558955f,
+ 0.724247083f, 0.689540545f,
+ 0.707106781f, 0.707106781f,
+ 0.689540545f, 0.724247083f,
+ 0.671558955f, 0.740951125f,
+ 0.653172843f, 0.757208847f,
+ 0.634393284f, 0.773010453f,
+ 0.615231591f, 0.788346428f,
+ 0.595699304f, 0.803207531f,
+ 0.575808191f, 0.817584813f,
+ 0.555570233f, 0.831469612f,
+ 0.534997620f, 0.844853565f,
+ 0.514102744f, 0.857728610f,
+ 0.492898192f, 0.870086991f,
+ 0.471396737f, 0.881921264f,
+ 0.449611330f, 0.893224301f,
+ 0.427555093f, 0.903989293f,
+ 0.405241314f, 0.914209756f,
+ 0.382683432f, 0.923879533f,
+ 0.359895037f, 0.932992799f,
+ 0.336889853f, 0.941544065f,
+ 0.313681740f, 0.949528181f,
+ 0.290284677f, 0.956940336f,
+ 0.266712757f, 0.963776066f,
+ 0.242980180f, 0.970031253f,
+ 0.219101240f, 0.975702130f,
+ 0.195090322f, 0.980785280f,
+ 0.170961889f, 0.985277642f,
+ 0.146730474f, 0.989176510f,
+ 0.122410675f, 0.992479535f,
+ 0.098017140f, 0.995184727f,
+ 0.073564564f, 0.997290457f,
+ 0.049067674f, 0.998795456f,
+ 0.024541229f, 0.999698819f,
+ 0.000000000f, 1.000000000f,
+ -0.024541229f, 0.999698819f,
+ -0.049067674f, 0.998795456f,
+ -0.073564564f, 0.997290457f,
+ -0.098017140f, 0.995184727f,
+ -0.122410675f, 0.992479535f,
+ -0.146730474f, 0.989176510f,
+ -0.170961889f, 0.985277642f,
+ -0.195090322f, 0.980785280f,
+ -0.219101240f, 0.975702130f,
+ -0.242980180f, 0.970031253f,
+ -0.266712757f, 0.963776066f,
+ -0.290284677f, 0.956940336f,
+ -0.313681740f, 0.949528181f,
+ -0.336889853f, 0.941544065f,
+ -0.359895037f, 0.932992799f,
+ -0.382683432f, 0.923879533f,
+ -0.405241314f, 0.914209756f,
+ -0.427555093f, 0.903989293f,
+ -0.449611330f, 0.893224301f,
+ -0.471396737f, 0.881921264f,
+ -0.492898192f, 0.870086991f,
+ -0.514102744f, 0.857728610f,
+ -0.534997620f, 0.844853565f,
+ -0.555570233f, 0.831469612f,
+ -0.575808191f, 0.817584813f,
+ -0.595699304f, 0.803207531f,
+ -0.615231591f, 0.788346428f,
+ -0.634393284f, 0.773010453f,
+ -0.653172843f, 0.757208847f,
+ -0.671558955f, 0.740951125f,
+ -0.689540545f, 0.724247083f,
+ -0.707106781f, 0.707106781f,
+ -0.724247083f, 0.689540545f,
+ -0.740951125f, 0.671558955f,
+ -0.757208847f, 0.653172843f,
+ -0.773010453f, 0.634393284f,
+ -0.788346428f, 0.615231591f,
+ -0.803207531f, 0.595699304f,
+ -0.817584813f, 0.575808191f,
+ -0.831469612f, 0.555570233f,
+ -0.844853565f, 0.534997620f,
+ -0.857728610f, 0.514102744f,
+ -0.870086991f, 0.492898192f,
+ -0.881921264f, 0.471396737f,
+ -0.893224301f, 0.449611330f,
+ -0.903989293f, 0.427555093f,
+ -0.914209756f, 0.405241314f,
+ -0.923879533f, 0.382683432f,
+ -0.932992799f, 0.359895037f,
+ -0.941544065f, 0.336889853f,
+ -0.949528181f, 0.313681740f,
+ -0.956940336f, 0.290284677f,
+ -0.963776066f, 0.266712757f,
+ -0.970031253f, 0.242980180f,
+ -0.975702130f, 0.219101240f,
+ -0.980785280f, 0.195090322f,
+ -0.985277642f, 0.170961889f,
+ -0.989176510f, 0.146730474f,
+ -0.992479535f, 0.122410675f,
+ -0.995184727f, 0.098017140f,
+ -0.997290457f, 0.073564564f,
+ -0.998795456f, 0.049067674f,
+ -0.999698819f, 0.024541229f,
+ -1.000000000f, 0.000000000f,
+ -0.999698819f, -0.024541229f,
+ -0.998795456f, -0.049067674f,
+ -0.997290457f, -0.073564564f,
+ -0.995184727f, -0.098017140f,
+ -0.992479535f, -0.122410675f,
+ -0.989176510f, -0.146730474f,
+ -0.985277642f, -0.170961889f,
+ -0.980785280f, -0.195090322f,
+ -0.975702130f, -0.219101240f,
+ -0.970031253f, -0.242980180f,
+ -0.963776066f, -0.266712757f,
+ -0.956940336f, -0.290284677f,
+ -0.949528181f, -0.313681740f,
+ -0.941544065f, -0.336889853f,
+ -0.932992799f, -0.359895037f,
+ -0.923879533f, -0.382683432f,
+ -0.914209756f, -0.405241314f,
+ -0.903989293f, -0.427555093f,
+ -0.893224301f, -0.449611330f,
+ -0.881921264f, -0.471396737f,
+ -0.870086991f, -0.492898192f,
+ -0.857728610f, -0.514102744f,
+ -0.844853565f, -0.534997620f,
+ -0.831469612f, -0.555570233f,
+ -0.817584813f, -0.575808191f,
+ -0.803207531f, -0.595699304f,
+ -0.788346428f, -0.615231591f,
+ -0.773010453f, -0.634393284f,
+ -0.757208847f, -0.653172843f,
+ -0.740951125f, -0.671558955f,
+ -0.724247083f, -0.689540545f,
+ -0.707106781f, -0.707106781f,
+ -0.689540545f, -0.724247083f,
+ -0.671558955f, -0.740951125f,
+ -0.653172843f, -0.757208847f,
+ -0.634393284f, -0.773010453f,
+ -0.615231591f, -0.788346428f,
+ -0.595699304f, -0.803207531f,
+ -0.575808191f, -0.817584813f,
+ -0.555570233f, -0.831469612f,
+ -0.534997620f, -0.844853565f,
+ -0.514102744f, -0.857728610f,
+ -0.492898192f, -0.870086991f,
+ -0.471396737f, -0.881921264f,
+ -0.449611330f, -0.893224301f,
+ -0.427555093f, -0.903989293f,
+ -0.405241314f, -0.914209756f,
+ -0.382683432f, -0.923879533f,
+ -0.359895037f, -0.932992799f,
+ -0.336889853f, -0.941544065f,
+ -0.313681740f, -0.949528181f,
+ -0.290284677f, -0.956940336f,
+ -0.266712757f, -0.963776066f,
+ -0.242980180f, -0.970031253f,
+ -0.219101240f, -0.975702130f,
+ -0.195090322f, -0.980785280f,
+ -0.170961889f, -0.985277642f,
+ -0.146730474f, -0.989176510f,
+ -0.122410675f, -0.992479535f,
+ -0.098017140f, -0.995184727f,
+ -0.073564564f, -0.997290457f,
+ -0.049067674f, -0.998795456f,
+ -0.024541229f, -0.999698819f,
+ -0.000000000f, -1.000000000f,
+ 0.024541229f, -0.999698819f,
+ 0.049067674f, -0.998795456f,
+ 0.073564564f, -0.997290457f,
+ 0.098017140f, -0.995184727f,
+ 0.122410675f, -0.992479535f,
+ 0.146730474f, -0.989176510f,
+ 0.170961889f, -0.985277642f,
+ 0.195090322f, -0.980785280f,
+ 0.219101240f, -0.975702130f,
+ 0.242980180f, -0.970031253f,
+ 0.266712757f, -0.963776066f,
+ 0.290284677f, -0.956940336f,
+ 0.313681740f, -0.949528181f,
+ 0.336889853f, -0.941544065f,
+ 0.359895037f, -0.932992799f,
+ 0.382683432f, -0.923879533f,
+ 0.405241314f, -0.914209756f,
+ 0.427555093f, -0.903989293f,
+ 0.449611330f, -0.893224301f,
+ 0.471396737f, -0.881921264f,
+ 0.492898192f, -0.870086991f,
+ 0.514102744f, -0.857728610f,
+ 0.534997620f, -0.844853565f,
+ 0.555570233f, -0.831469612f,
+ 0.575808191f, -0.817584813f,
+ 0.595699304f, -0.803207531f,
+ 0.615231591f, -0.788346428f,
+ 0.634393284f, -0.773010453f,
+ 0.653172843f, -0.757208847f,
+ 0.671558955f, -0.740951125f,
+ 0.689540545f, -0.724247083f,
+ 0.707106781f, -0.707106781f,
+ 0.724247083f, -0.689540545f,
+ 0.740951125f, -0.671558955f,
+ 0.757208847f, -0.653172843f,
+ 0.773010453f, -0.634393284f,
+ 0.788346428f, -0.615231591f,
+ 0.803207531f, -0.595699304f,
+ 0.817584813f, -0.575808191f,
+ 0.831469612f, -0.555570233f,
+ 0.844853565f, -0.534997620f,
+ 0.857728610f, -0.514102744f,
+ 0.870086991f, -0.492898192f,
+ 0.881921264f, -0.471396737f,
+ 0.893224301f, -0.449611330f,
+ 0.903989293f, -0.427555093f,
+ 0.914209756f, -0.405241314f,
+ 0.923879533f, -0.382683432f,
+ 0.932992799f, -0.359895037f,
+ 0.941544065f, -0.336889853f,
+ 0.949528181f, -0.313681740f,
+ 0.956940336f, -0.290284677f,
+ 0.963776066f, -0.266712757f,
+ 0.970031253f, -0.242980180f,
+ 0.975702130f, -0.219101240f,
+ 0.980785280f, -0.195090322f,
+ 0.985277642f, -0.170961889f,
+ 0.989176510f, -0.146730474f,
+ 0.992479535f, -0.122410675f,
+ 0.995184727f, -0.098017140f,
+ 0.997290457f, -0.073564564f,
+ 0.998795456f, -0.049067674f,
+ 0.999698819f, -0.024541229f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_512[1024] = {
+ 1.000000000f, 0.000000000f,
+ 0.999924702f, 0.012271538f,
+ 0.999698819f, 0.024541229f,
+ 0.999322385f, 0.036807223f,
+ 0.998795456f, 0.049067674f,
+ 0.998118113f, 0.061320736f,
+ 0.997290457f, 0.073564564f,
+ 0.996312612f, 0.085797312f,
+ 0.995184727f, 0.098017140f,
+ 0.993906970f, 0.110222207f,
+ 0.992479535f, 0.122410675f,
+ 0.990902635f, 0.134580709f,
+ 0.989176510f, 0.146730474f,
+ 0.987301418f, 0.158858143f,
+ 0.985277642f, 0.170961889f,
+ 0.983105487f, 0.183039888f,
+ 0.980785280f, 0.195090322f,
+ 0.978317371f, 0.207111376f,
+ 0.975702130f, 0.219101240f,
+ 0.972939952f, 0.231058108f,
+ 0.970031253f, 0.242980180f,
+ 0.966976471f, 0.254865660f,
+ 0.963776066f, 0.266712757f,
+ 0.960430519f, 0.278519689f,
+ 0.956940336f, 0.290284677f,
+ 0.953306040f, 0.302005949f,
+ 0.949528181f, 0.313681740f,
+ 0.945607325f, 0.325310292f,
+ 0.941544065f, 0.336889853f,
+ 0.937339012f, 0.348418680f,
+ 0.932992799f, 0.359895037f,
+ 0.928506080f, 0.371317194f,
+ 0.923879533f, 0.382683432f,
+ 0.919113852f, 0.393992040f,
+ 0.914209756f, 0.405241314f,
+ 0.909167983f, 0.416429560f,
+ 0.903989293f, 0.427555093f,
+ 0.898674466f, 0.438616239f,
+ 0.893224301f, 0.449611330f,
+ 0.887639620f, 0.460538711f,
+ 0.881921264f, 0.471396737f,
+ 0.876070094f, 0.482183772f,
+ 0.870086991f, 0.492898192f,
+ 0.863972856f, 0.503538384f,
+ 0.857728610f, 0.514102744f,
+ 0.851355193f, 0.524589683f,
+ 0.844853565f, 0.534997620f,
+ 0.838224706f, 0.545324988f,
+ 0.831469612f, 0.555570233f,
+ 0.824589303f, 0.565731811f,
+ 0.817584813f, 0.575808191f,
+ 0.810457198f, 0.585797857f,
+ 0.803207531f, 0.595699304f,
+ 0.795836905f, 0.605511041f,
+ 0.788346428f, 0.615231591f,
+ 0.780737229f, 0.624859488f,
+ 0.773010453f, 0.634393284f,
+ 0.765167266f, 0.643831543f,
+ 0.757208847f, 0.653172843f,
+ 0.749136395f, 0.662415778f,
+ 0.740951125f, 0.671558955f,
+ 0.732654272f, 0.680600998f,
+ 0.724247083f, 0.689540545f,
+ 0.715730825f, 0.698376249f,
+ 0.707106781f, 0.707106781f,
+ 0.698376249f, 0.715730825f,
+ 0.689540545f, 0.724247083f,
+ 0.680600998f, 0.732654272f,
+ 0.671558955f, 0.740951125f,
+ 0.662415778f, 0.749136395f,
+ 0.653172843f, 0.757208847f,
+ 0.643831543f, 0.765167266f,
+ 0.634393284f, 0.773010453f,
+ 0.624859488f, 0.780737229f,
+ 0.615231591f, 0.788346428f,
+ 0.605511041f, 0.795836905f,
+ 0.595699304f, 0.803207531f,
+ 0.585797857f, 0.810457198f,
+ 0.575808191f, 0.817584813f,
+ 0.565731811f, 0.824589303f,
+ 0.555570233f, 0.831469612f,
+ 0.545324988f, 0.838224706f,
+ 0.534997620f, 0.844853565f,
+ 0.524589683f, 0.851355193f,
+ 0.514102744f, 0.857728610f,
+ 0.503538384f, 0.863972856f,
+ 0.492898192f, 0.870086991f,
+ 0.482183772f, 0.876070094f,
+ 0.471396737f, 0.881921264f,
+ 0.460538711f, 0.887639620f,
+ 0.449611330f, 0.893224301f,
+ 0.438616239f, 0.898674466f,
+ 0.427555093f, 0.903989293f,
+ 0.416429560f, 0.909167983f,
+ 0.405241314f, 0.914209756f,
+ 0.393992040f, 0.919113852f,
+ 0.382683432f, 0.923879533f,
+ 0.371317194f, 0.928506080f,
+ 0.359895037f, 0.932992799f,
+ 0.348418680f, 0.937339012f,
+ 0.336889853f, 0.941544065f,
+ 0.325310292f, 0.945607325f,
+ 0.313681740f, 0.949528181f,
+ 0.302005949f, 0.953306040f,
+ 0.290284677f, 0.956940336f,
+ 0.278519689f, 0.960430519f,
+ 0.266712757f, 0.963776066f,
+ 0.254865660f, 0.966976471f,
+ 0.242980180f, 0.970031253f,
+ 0.231058108f, 0.972939952f,
+ 0.219101240f, 0.975702130f,
+ 0.207111376f, 0.978317371f,
+ 0.195090322f, 0.980785280f,
+ 0.183039888f, 0.983105487f,
+ 0.170961889f, 0.985277642f,
+ 0.158858143f, 0.987301418f,
+ 0.146730474f, 0.989176510f,
+ 0.134580709f, 0.990902635f,
+ 0.122410675f, 0.992479535f,
+ 0.110222207f, 0.993906970f,
+ 0.098017140f, 0.995184727f,
+ 0.085797312f, 0.996312612f,
+ 0.073564564f, 0.997290457f,
+ 0.061320736f, 0.998118113f,
+ 0.049067674f, 0.998795456f,
+ 0.036807223f, 0.999322385f,
+ 0.024541229f, 0.999698819f,
+ 0.012271538f, 0.999924702f,
+ 0.000000000f, 1.000000000f,
+ -0.012271538f, 0.999924702f,
+ -0.024541229f, 0.999698819f,
+ -0.036807223f, 0.999322385f,
+ -0.049067674f, 0.998795456f,
+ -0.061320736f, 0.998118113f,
+ -0.073564564f, 0.997290457f,
+ -0.085797312f, 0.996312612f,
+ -0.098017140f, 0.995184727f,
+ -0.110222207f, 0.993906970f,
+ -0.122410675f, 0.992479535f,
+ -0.134580709f, 0.990902635f,
+ -0.146730474f, 0.989176510f,
+ -0.158858143f, 0.987301418f,
+ -0.170961889f, 0.985277642f,
+ -0.183039888f, 0.983105487f,
+ -0.195090322f, 0.980785280f,
+ -0.207111376f, 0.978317371f,
+ -0.219101240f, 0.975702130f,
+ -0.231058108f, 0.972939952f,
+ -0.242980180f, 0.970031253f,
+ -0.254865660f, 0.966976471f,
+ -0.266712757f, 0.963776066f,
+ -0.278519689f, 0.960430519f,
+ -0.290284677f, 0.956940336f,
+ -0.302005949f, 0.953306040f,
+ -0.313681740f, 0.949528181f,
+ -0.325310292f, 0.945607325f,
+ -0.336889853f, 0.941544065f,
+ -0.348418680f, 0.937339012f,
+ -0.359895037f, 0.932992799f,
+ -0.371317194f, 0.928506080f,
+ -0.382683432f, 0.923879533f,
+ -0.393992040f, 0.919113852f,
+ -0.405241314f, 0.914209756f,
+ -0.416429560f, 0.909167983f,
+ -0.427555093f, 0.903989293f,
+ -0.438616239f, 0.898674466f,
+ -0.449611330f, 0.893224301f,
+ -0.460538711f, 0.887639620f,
+ -0.471396737f, 0.881921264f,
+ -0.482183772f, 0.876070094f,
+ -0.492898192f, 0.870086991f,
+ -0.503538384f, 0.863972856f,
+ -0.514102744f, 0.857728610f,
+ -0.524589683f, 0.851355193f,
+ -0.534997620f, 0.844853565f,
+ -0.545324988f, 0.838224706f,
+ -0.555570233f, 0.831469612f,
+ -0.565731811f, 0.824589303f,
+ -0.575808191f, 0.817584813f,
+ -0.585797857f, 0.810457198f,
+ -0.595699304f, 0.803207531f,
+ -0.605511041f, 0.795836905f,
+ -0.615231591f, 0.788346428f,
+ -0.624859488f, 0.780737229f,
+ -0.634393284f, 0.773010453f,
+ -0.643831543f, 0.765167266f,
+ -0.653172843f, 0.757208847f,
+ -0.662415778f, 0.749136395f,
+ -0.671558955f, 0.740951125f,
+ -0.680600998f, 0.732654272f,
+ -0.689540545f, 0.724247083f,
+ -0.698376249f, 0.715730825f,
+ -0.707106781f, 0.707106781f,
+ -0.715730825f, 0.698376249f,
+ -0.724247083f, 0.689540545f,
+ -0.732654272f, 0.680600998f,
+ -0.740951125f, 0.671558955f,
+ -0.749136395f, 0.662415778f,
+ -0.757208847f, 0.653172843f,
+ -0.765167266f, 0.643831543f,
+ -0.773010453f, 0.634393284f,
+ -0.780737229f, 0.624859488f,
+ -0.788346428f, 0.615231591f,
+ -0.795836905f, 0.605511041f,
+ -0.803207531f, 0.595699304f,
+ -0.810457198f, 0.585797857f,
+ -0.817584813f, 0.575808191f,
+ -0.824589303f, 0.565731811f,
+ -0.831469612f, 0.555570233f,
+ -0.838224706f, 0.545324988f,
+ -0.844853565f, 0.534997620f,
+ -0.851355193f, 0.524589683f,
+ -0.857728610f, 0.514102744f,
+ -0.863972856f, 0.503538384f,
+ -0.870086991f, 0.492898192f,
+ -0.876070094f, 0.482183772f,
+ -0.881921264f, 0.471396737f,
+ -0.887639620f, 0.460538711f,
+ -0.893224301f, 0.449611330f,
+ -0.898674466f, 0.438616239f,
+ -0.903989293f, 0.427555093f,
+ -0.909167983f, 0.416429560f,
+ -0.914209756f, 0.405241314f,
+ -0.919113852f, 0.393992040f,
+ -0.923879533f, 0.382683432f,
+ -0.928506080f, 0.371317194f,
+ -0.932992799f, 0.359895037f,
+ -0.937339012f, 0.348418680f,
+ -0.941544065f, 0.336889853f,
+ -0.945607325f, 0.325310292f,
+ -0.949528181f, 0.313681740f,
+ -0.953306040f, 0.302005949f,
+ -0.956940336f, 0.290284677f,
+ -0.960430519f, 0.278519689f,
+ -0.963776066f, 0.266712757f,
+ -0.966976471f, 0.254865660f,
+ -0.970031253f, 0.242980180f,
+ -0.972939952f, 0.231058108f,
+ -0.975702130f, 0.219101240f,
+ -0.978317371f, 0.207111376f,
+ -0.980785280f, 0.195090322f,
+ -0.983105487f, 0.183039888f,
+ -0.985277642f, 0.170961889f,
+ -0.987301418f, 0.158858143f,
+ -0.989176510f, 0.146730474f,
+ -0.990902635f, 0.134580709f,
+ -0.992479535f, 0.122410675f,
+ -0.993906970f, 0.110222207f,
+ -0.995184727f, 0.098017140f,
+ -0.996312612f, 0.085797312f,
+ -0.997290457f, 0.073564564f,
+ -0.998118113f, 0.061320736f,
+ -0.998795456f, 0.049067674f,
+ -0.999322385f, 0.036807223f,
+ -0.999698819f, 0.024541229f,
+ -0.999924702f, 0.012271538f,
+ -1.000000000f, 0.000000000f,
+ -0.999924702f, -0.012271538f,
+ -0.999698819f, -0.024541229f,
+ -0.999322385f, -0.036807223f,
+ -0.998795456f, -0.049067674f,
+ -0.998118113f, -0.061320736f,
+ -0.997290457f, -0.073564564f,
+ -0.996312612f, -0.085797312f,
+ -0.995184727f, -0.098017140f,
+ -0.993906970f, -0.110222207f,
+ -0.992479535f, -0.122410675f,
+ -0.990902635f, -0.134580709f,
+ -0.989176510f, -0.146730474f,
+ -0.987301418f, -0.158858143f,
+ -0.985277642f, -0.170961889f,
+ -0.983105487f, -0.183039888f,
+ -0.980785280f, -0.195090322f,
+ -0.978317371f, -0.207111376f,
+ -0.975702130f, -0.219101240f,
+ -0.972939952f, -0.231058108f,
+ -0.970031253f, -0.242980180f,
+ -0.966976471f, -0.254865660f,
+ -0.963776066f, -0.266712757f,
+ -0.960430519f, -0.278519689f,
+ -0.956940336f, -0.290284677f,
+ -0.953306040f, -0.302005949f,
+ -0.949528181f, -0.313681740f,
+ -0.945607325f, -0.325310292f,
+ -0.941544065f, -0.336889853f,
+ -0.937339012f, -0.348418680f,
+ -0.932992799f, -0.359895037f,
+ -0.928506080f, -0.371317194f,
+ -0.923879533f, -0.382683432f,
+ -0.919113852f, -0.393992040f,
+ -0.914209756f, -0.405241314f,
+ -0.909167983f, -0.416429560f,
+ -0.903989293f, -0.427555093f,
+ -0.898674466f, -0.438616239f,
+ -0.893224301f, -0.449611330f,
+ -0.887639620f, -0.460538711f,
+ -0.881921264f, -0.471396737f,
+ -0.876070094f, -0.482183772f,
+ -0.870086991f, -0.492898192f,
+ -0.863972856f, -0.503538384f,
+ -0.857728610f, -0.514102744f,
+ -0.851355193f, -0.524589683f,
+ -0.844853565f, -0.534997620f,
+ -0.838224706f, -0.545324988f,
+ -0.831469612f, -0.555570233f,
+ -0.824589303f, -0.565731811f,
+ -0.817584813f, -0.575808191f,
+ -0.810457198f, -0.585797857f,
+ -0.803207531f, -0.595699304f,
+ -0.795836905f, -0.605511041f,
+ -0.788346428f, -0.615231591f,
+ -0.780737229f, -0.624859488f,
+ -0.773010453f, -0.634393284f,
+ -0.765167266f, -0.643831543f,
+ -0.757208847f, -0.653172843f,
+ -0.749136395f, -0.662415778f,
+ -0.740951125f, -0.671558955f,
+ -0.732654272f, -0.680600998f,
+ -0.724247083f, -0.689540545f,
+ -0.715730825f, -0.698376249f,
+ -0.707106781f, -0.707106781f,
+ -0.698376249f, -0.715730825f,
+ -0.689540545f, -0.724247083f,
+ -0.680600998f, -0.732654272f,
+ -0.671558955f, -0.740951125f,
+ -0.662415778f, -0.749136395f,
+ -0.653172843f, -0.757208847f,
+ -0.643831543f, -0.765167266f,
+ -0.634393284f, -0.773010453f,
+ -0.624859488f, -0.780737229f,
+ -0.615231591f, -0.788346428f,
+ -0.605511041f, -0.795836905f,
+ -0.595699304f, -0.803207531f,
+ -0.585797857f, -0.810457198f,
+ -0.575808191f, -0.817584813f,
+ -0.565731811f, -0.824589303f,
+ -0.555570233f, -0.831469612f,
+ -0.545324988f, -0.838224706f,
+ -0.534997620f, -0.844853565f,
+ -0.524589683f, -0.851355193f,
+ -0.514102744f, -0.857728610f,
+ -0.503538384f, -0.863972856f,
+ -0.492898192f, -0.870086991f,
+ -0.482183772f, -0.876070094f,
+ -0.471396737f, -0.881921264f,
+ -0.460538711f, -0.887639620f,
+ -0.449611330f, -0.893224301f,
+ -0.438616239f, -0.898674466f,
+ -0.427555093f, -0.903989293f,
+ -0.416429560f, -0.909167983f,
+ -0.405241314f, -0.914209756f,
+ -0.393992040f, -0.919113852f,
+ -0.382683432f, -0.923879533f,
+ -0.371317194f, -0.928506080f,
+ -0.359895037f, -0.932992799f,
+ -0.348418680f, -0.937339012f,
+ -0.336889853f, -0.941544065f,
+ -0.325310292f, -0.945607325f,
+ -0.313681740f, -0.949528181f,
+ -0.302005949f, -0.953306040f,
+ -0.290284677f, -0.956940336f,
+ -0.278519689f, -0.960430519f,
+ -0.266712757f, -0.963776066f,
+ -0.254865660f, -0.966976471f,
+ -0.242980180f, -0.970031253f,
+ -0.231058108f, -0.972939952f,
+ -0.219101240f, -0.975702130f,
+ -0.207111376f, -0.978317371f,
+ -0.195090322f, -0.980785280f,
+ -0.183039888f, -0.983105487f,
+ -0.170961889f, -0.985277642f,
+ -0.158858143f, -0.987301418f,
+ -0.146730474f, -0.989176510f,
+ -0.134580709f, -0.990902635f,
+ -0.122410675f, -0.992479535f,
+ -0.110222207f, -0.993906970f,
+ -0.098017140f, -0.995184727f,
+ -0.085797312f, -0.996312612f,
+ -0.073564564f, -0.997290457f,
+ -0.061320736f, -0.998118113f,
+ -0.049067674f, -0.998795456f,
+ -0.036807223f, -0.999322385f,
+ -0.024541229f, -0.999698819f,
+ -0.012271538f, -0.999924702f,
+ -0.000000000f, -1.000000000f,
+ 0.012271538f, -0.999924702f,
+ 0.024541229f, -0.999698819f,
+ 0.036807223f, -0.999322385f,
+ 0.049067674f, -0.998795456f,
+ 0.061320736f, -0.998118113f,
+ 0.073564564f, -0.997290457f,
+ 0.085797312f, -0.996312612f,
+ 0.098017140f, -0.995184727f,
+ 0.110222207f, -0.993906970f,
+ 0.122410675f, -0.992479535f,
+ 0.134580709f, -0.990902635f,
+ 0.146730474f, -0.989176510f,
+ 0.158858143f, -0.987301418f,
+ 0.170961889f, -0.985277642f,
+ 0.183039888f, -0.983105487f,
+ 0.195090322f, -0.980785280f,
+ 0.207111376f, -0.978317371f,
+ 0.219101240f, -0.975702130f,
+ 0.231058108f, -0.972939952f,
+ 0.242980180f, -0.970031253f,
+ 0.254865660f, -0.966976471f,
+ 0.266712757f, -0.963776066f,
+ 0.278519689f, -0.960430519f,
+ 0.290284677f, -0.956940336f,
+ 0.302005949f, -0.953306040f,
+ 0.313681740f, -0.949528181f,
+ 0.325310292f, -0.945607325f,
+ 0.336889853f, -0.941544065f,
+ 0.348418680f, -0.937339012f,
+ 0.359895037f, -0.932992799f,
+ 0.371317194f, -0.928506080f,
+ 0.382683432f, -0.923879533f,
+ 0.393992040f, -0.919113852f,
+ 0.405241314f, -0.914209756f,
+ 0.416429560f, -0.909167983f,
+ 0.427555093f, -0.903989293f,
+ 0.438616239f, -0.898674466f,
+ 0.449611330f, -0.893224301f,
+ 0.460538711f, -0.887639620f,
+ 0.471396737f, -0.881921264f,
+ 0.482183772f, -0.876070094f,
+ 0.492898192f, -0.870086991f,
+ 0.503538384f, -0.863972856f,
+ 0.514102744f, -0.857728610f,
+ 0.524589683f, -0.851355193f,
+ 0.534997620f, -0.844853565f,
+ 0.545324988f, -0.838224706f,
+ 0.555570233f, -0.831469612f,
+ 0.565731811f, -0.824589303f,
+ 0.575808191f, -0.817584813f,
+ 0.585797857f, -0.810457198f,
+ 0.595699304f, -0.803207531f,
+ 0.605511041f, -0.795836905f,
+ 0.615231591f, -0.788346428f,
+ 0.624859488f, -0.780737229f,
+ 0.634393284f, -0.773010453f,
+ 0.643831543f, -0.765167266f,
+ 0.653172843f, -0.757208847f,
+ 0.662415778f, -0.749136395f,
+ 0.671558955f, -0.740951125f,
+ 0.680600998f, -0.732654272f,
+ 0.689540545f, -0.724247083f,
+ 0.698376249f, -0.715730825f,
+ 0.707106781f, -0.707106781f,
+ 0.715730825f, -0.698376249f,
+ 0.724247083f, -0.689540545f,
+ 0.732654272f, -0.680600998f,
+ 0.740951125f, -0.671558955f,
+ 0.749136395f, -0.662415778f,
+ 0.757208847f, -0.653172843f,
+ 0.765167266f, -0.643831543f,
+ 0.773010453f, -0.634393284f,
+ 0.780737229f, -0.624859488f,
+ 0.788346428f, -0.615231591f,
+ 0.795836905f, -0.605511041f,
+ 0.803207531f, -0.595699304f,
+ 0.810457198f, -0.585797857f,
+ 0.817584813f, -0.575808191f,
+ 0.824589303f, -0.565731811f,
+ 0.831469612f, -0.555570233f,
+ 0.838224706f, -0.545324988f,
+ 0.844853565f, -0.534997620f,
+ 0.851355193f, -0.524589683f,
+ 0.857728610f, -0.514102744f,
+ 0.863972856f, -0.503538384f,
+ 0.870086991f, -0.492898192f,
+ 0.876070094f, -0.482183772f,
+ 0.881921264f, -0.471396737f,
+ 0.887639620f, -0.460538711f,
+ 0.893224301f, -0.449611330f,
+ 0.898674466f, -0.438616239f,
+ 0.903989293f, -0.427555093f,
+ 0.909167983f, -0.416429560f,
+ 0.914209756f, -0.405241314f,
+ 0.919113852f, -0.393992040f,
+ 0.923879533f, -0.382683432f,
+ 0.928506080f, -0.371317194f,
+ 0.932992799f, -0.359895037f,
+ 0.937339012f, -0.348418680f,
+ 0.941544065f, -0.336889853f,
+ 0.945607325f, -0.325310292f,
+ 0.949528181f, -0.313681740f,
+ 0.953306040f, -0.302005949f,
+ 0.956940336f, -0.290284677f,
+ 0.960430519f, -0.278519689f,
+ 0.963776066f, -0.266712757f,
+ 0.966976471f, -0.254865660f,
+ 0.970031253f, -0.242980180f,
+ 0.972939952f, -0.231058108f,
+ 0.975702130f, -0.219101240f,
+ 0.978317371f, -0.207111376f,
+ 0.980785280f, -0.195090322f,
+ 0.983105487f, -0.183039888f,
+ 0.985277642f, -0.170961889f,
+ 0.987301418f, -0.158858143f,
+ 0.989176510f, -0.146730474f,
+ 0.990902635f, -0.134580709f,
+ 0.992479535f, -0.122410675f,
+ 0.993906970f, -0.110222207f,
+ 0.995184727f, -0.098017140f,
+ 0.996312612f, -0.085797312f,
+ 0.997290457f, -0.073564564f,
+ 0.998118113f, -0.061320736f,
+ 0.998795456f, -0.049067674f,
+ 0.999322385f, -0.036807223f,
+ 0.999698819f, -0.024541229f,
+ 0.999924702f, -0.012271538f
+};
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_1024[2048] = {
+1.000000000f , 0.000000000f ,
+0.999981175f , 0.006135885f ,
+0.999924702f , 0.012271538f ,
+0.999830582f , 0.018406730f ,
+0.999698819f , 0.024541229f ,
+0.999529418f , 0.030674803f ,
+0.999322385f , 0.036807223f ,
+0.999077728f , 0.042938257f ,
+0.998795456f , 0.049067674f ,
+0.998475581f , 0.055195244f ,
+0.998118113f , 0.061320736f ,
+0.997723067f , 0.067443920f ,
+0.997290457f , 0.073564564f ,
+0.996820299f , 0.079682438f ,
+0.996312612f , 0.085797312f ,
+0.995767414f , 0.091908956f ,
+0.995184727f , 0.098017140f ,
+0.994564571f , 0.104121634f ,
+0.993906970f , 0.110222207f ,
+0.993211949f , 0.116318631f ,
+0.992479535f , 0.122410675f ,
+0.991709754f , 0.128498111f ,
+0.990902635f , 0.134580709f ,
+0.990058210f , 0.140658239f ,
+0.989176510f , 0.146730474f ,
+0.988257568f , 0.152797185f ,
+0.987301418f , 0.158858143f ,
+0.986308097f , 0.164913120f ,
+0.985277642f , 0.170961889f ,
+0.984210092f , 0.177004220f ,
+0.983105487f , 0.183039888f ,
+0.981963869f , 0.189068664f ,
+0.980785280f , 0.195090322f ,
+0.979569766f , 0.201104635f ,
+0.978317371f , 0.207111376f ,
+0.977028143f , 0.213110320f ,
+0.975702130f , 0.219101240f ,
+0.974339383f , 0.225083911f ,
+0.972939952f , 0.231058108f ,
+0.971503891f , 0.237023606f ,
+0.970031253f , 0.242980180f ,
+0.968522094f , 0.248927606f ,
+0.966976471f , 0.254865660f ,
+0.965394442f , 0.260794118f ,
+0.963776066f , 0.266712757f ,
+0.962121404f , 0.272621355f ,
+0.960430519f , 0.278519689f ,
+0.958703475f , 0.284407537f ,
+0.956940336f , 0.290284677f ,
+0.955141168f , 0.296150888f ,
+0.953306040f , 0.302005949f ,
+0.951435021f , 0.307849640f ,
+0.949528181f , 0.313681740f ,
+0.947585591f , 0.319502031f ,
+0.945607325f , 0.325310292f ,
+0.943593458f , 0.331106306f ,
+0.941544065f , 0.336889853f ,
+0.939459224f , 0.342660717f ,
+0.937339012f , 0.348418680f ,
+0.935183510f , 0.354163525f ,
+0.932992799f , 0.359895037f ,
+0.930766961f , 0.365612998f ,
+0.928506080f , 0.371317194f ,
+0.926210242f , 0.377007410f ,
+0.923879533f , 0.382683432f ,
+0.921514039f , 0.388345047f ,
+0.919113852f , 0.393992040f ,
+0.916679060f , 0.399624200f ,
+0.914209756f , 0.405241314f ,
+0.911706032f , 0.410843171f ,
+0.909167983f , 0.416429560f ,
+0.906595705f , 0.422000271f ,
+0.903989293f , 0.427555093f ,
+0.901348847f , 0.433093819f ,
+0.898674466f , 0.438616239f ,
+0.895966250f , 0.444122145f ,
+0.893224301f , 0.449611330f ,
+0.890448723f , 0.455083587f ,
+0.887639620f , 0.460538711f ,
+0.884797098f , 0.465976496f ,
+0.881921264f , 0.471396737f ,
+0.879012226f , 0.476799230f ,
+0.876070094f , 0.482183772f ,
+0.873094978f , 0.487550160f ,
+0.870086991f , 0.492898192f ,
+0.867046246f , 0.498227667f ,
+0.863972856f , 0.503538384f ,
+0.860866939f , 0.508830143f ,
+0.857728610f , 0.514102744f ,
+0.854557988f , 0.519355990f ,
+0.851355193f , 0.524589683f ,
+0.848120345f , 0.529803625f ,
+0.844853565f , 0.534997620f ,
+0.841554977f , 0.540171473f ,
+0.838224706f , 0.545324988f ,
+0.834862875f , 0.550457973f ,
+0.831469612f , 0.555570233f ,
+0.828045045f , 0.560661576f ,
+0.824589303f , 0.565731811f ,
+0.821102515f , 0.570780746f ,
+0.817584813f , 0.575808191f ,
+0.814036330f , 0.580813958f ,
+0.810457198f , 0.585797857f ,
+0.806847554f , 0.590759702f ,
+0.803207531f , 0.595699304f ,
+0.799537269f , 0.600616479f ,
+0.795836905f , 0.605511041f ,
+0.792106577f , 0.610382806f ,
+0.788346428f , 0.615231591f ,
+0.784556597f , 0.620057212f ,
+0.780737229f , 0.624859488f ,
+0.776888466f , 0.629638239f ,
+0.773010453f , 0.634393284f ,
+0.769103338f , 0.639124445f ,
+0.765167266f , 0.643831543f ,
+0.761202385f , 0.648514401f ,
+0.757208847f , 0.653172843f ,
+0.753186799f , 0.657806693f ,
+0.749136395f , 0.662415778f ,
+0.745057785f , 0.666999922f ,
+0.740951125f , 0.671558955f ,
+0.736816569f , 0.676092704f ,
+0.732654272f , 0.680600998f ,
+0.728464390f , 0.685083668f ,
+0.724247083f , 0.689540545f ,
+0.720002508f , 0.693971461f ,
+0.715730825f , 0.698376249f ,
+0.711432196f , 0.702754744f ,
+0.707106781f , 0.707106781f ,
+0.702754744f , 0.711432196f ,
+0.698376249f , 0.715730825f ,
+0.693971461f , 0.720002508f ,
+0.689540545f , 0.724247083f ,
+0.685083668f , 0.728464390f ,
+0.680600998f , 0.732654272f ,
+0.676092704f , 0.736816569f ,
+0.671558955f , 0.740951125f ,
+0.666999922f , 0.745057785f ,
+0.662415778f , 0.749136395f ,
+0.657806693f , 0.753186799f ,
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+0.965394442f , -0.260794118f ,
+0.966976471f , -0.254865660f ,
+0.968522094f , -0.248927606f ,
+0.970031253f , -0.242980180f ,
+0.971503891f , -0.237023606f ,
+0.972939952f , -0.231058108f ,
+0.974339383f , -0.225083911f ,
+0.975702130f , -0.219101240f ,
+0.977028143f , -0.213110320f ,
+0.978317371f , -0.207111376f ,
+0.979569766f , -0.201104635f ,
+0.980785280f , -0.195090322f ,
+0.981963869f , -0.189068664f ,
+0.983105487f , -0.183039888f ,
+0.984210092f , -0.177004220f ,
+0.985277642f , -0.170961889f ,
+0.986308097f , -0.164913120f ,
+0.987301418f , -0.158858143f ,
+0.988257568f , -0.152797185f ,
+0.989176510f , -0.146730474f ,
+0.990058210f , -0.140658239f ,
+0.990902635f , -0.134580709f ,
+0.991709754f , -0.128498111f ,
+0.992479535f , -0.122410675f ,
+0.993211949f , -0.116318631f ,
+0.993906970f , -0.110222207f ,
+0.994564571f , -0.104121634f ,
+0.995184727f , -0.098017140f ,
+0.995767414f , -0.091908956f ,
+0.996312612f , -0.085797312f ,
+0.996820299f , -0.079682438f ,
+0.997290457f , -0.073564564f ,
+0.997723067f , -0.067443920f ,
+0.998118113f , -0.061320736f ,
+0.998475581f , -0.055195244f ,
+0.998795456f , -0.049067674f ,
+0.999077728f , -0.042938257f ,
+0.999322385f , -0.036807223f ,
+0.999529418f , -0.030674803f ,
+0.999698819f , -0.024541229f ,
+0.999830582f , -0.018406730f ,
+0.999924702f , -0.012271538f ,
+0.999981175f , -0.006135885f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_2048[4096] = {
+ 1.000000000f, 0.000000000f,
+ 0.999995294f, 0.003067957f,
+ 0.999981175f, 0.006135885f,
+ 0.999957645f, 0.009203755f,
+ 0.999924702f, 0.012271538f,
+ 0.999882347f, 0.015339206f,
+ 0.999830582f, 0.018406730f,
+ 0.999769405f, 0.021474080f,
+ 0.999698819f, 0.024541229f,
+ 0.999618822f, 0.027608146f,
+ 0.999529418f, 0.030674803f,
+ 0.999430605f, 0.033741172f,
+ 0.999322385f, 0.036807223f,
+ 0.999204759f, 0.039872928f,
+ 0.999077728f, 0.042938257f,
+ 0.998941293f, 0.046003182f,
+ 0.998795456f, 0.049067674f,
+ 0.998640218f, 0.052131705f,
+ 0.998475581f, 0.055195244f,
+ 0.998301545f, 0.058258265f,
+ 0.998118113f, 0.061320736f,
+ 0.997925286f, 0.064382631f,
+ 0.997723067f, 0.067443920f,
+ 0.997511456f, 0.070504573f,
+ 0.997290457f, 0.073564564f,
+ 0.997060070f, 0.076623861f,
+ 0.996820299f, 0.079682438f,
+ 0.996571146f, 0.082740265f,
+ 0.996312612f, 0.085797312f,
+ 0.996044701f, 0.088853553f,
+ 0.995767414f, 0.091908956f,
+ 0.995480755f, 0.094963495f,
+ 0.995184727f, 0.098017140f,
+ 0.994879331f, 0.101069863f,
+ 0.994564571f, 0.104121634f,
+ 0.994240449f, 0.107172425f,
+ 0.993906970f, 0.110222207f,
+ 0.993564136f, 0.113270952f,
+ 0.993211949f, 0.116318631f,
+ 0.992850414f, 0.119365215f,
+ 0.992479535f, 0.122410675f,
+ 0.992099313f, 0.125454983f,
+ 0.991709754f, 0.128498111f,
+ 0.991310860f, 0.131540029f,
+ 0.990902635f, 0.134580709f,
+ 0.990485084f, 0.137620122f,
+ 0.990058210f, 0.140658239f,
+ 0.989622017f, 0.143695033f,
+ 0.989176510f, 0.146730474f,
+ 0.988721692f, 0.149764535f,
+ 0.988257568f, 0.152797185f,
+ 0.987784142f, 0.155828398f,
+ 0.987301418f, 0.158858143f,
+ 0.986809402f, 0.161886394f,
+ 0.986308097f, 0.164913120f,
+ 0.985797509f, 0.167938295f,
+ 0.985277642f, 0.170961889f,
+ 0.984748502f, 0.173983873f,
+ 0.984210092f, 0.177004220f,
+ 0.983662419f, 0.180022901f,
+ 0.983105487f, 0.183039888f,
+ 0.982539302f, 0.186055152f,
+ 0.981963869f, 0.189068664f,
+ 0.981379193f, 0.192080397f,
+ 0.980785280f, 0.195090322f,
+ 0.980182136f, 0.198098411f,
+ 0.979569766f, 0.201104635f,
+ 0.978948175f, 0.204108966f,
+ 0.978317371f, 0.207111376f,
+ 0.977677358f, 0.210111837f,
+ 0.977028143f, 0.213110320f,
+ 0.976369731f, 0.216106797f,
+ 0.975702130f, 0.219101240f,
+ 0.975025345f, 0.222093621f,
+ 0.974339383f, 0.225083911f,
+ 0.973644250f, 0.228072083f,
+ 0.972939952f, 0.231058108f,
+ 0.972226497f, 0.234041959f,
+ 0.971503891f, 0.237023606f,
+ 0.970772141f, 0.240003022f,
+ 0.970031253f, 0.242980180f,
+ 0.969281235f, 0.245955050f,
+ 0.968522094f, 0.248927606f,
+ 0.967753837f, 0.251897818f,
+ 0.966976471f, 0.254865660f,
+ 0.966190003f, 0.257831102f,
+ 0.965394442f, 0.260794118f,
+ 0.964589793f, 0.263754679f,
+ 0.963776066f, 0.266712757f,
+ 0.962953267f, 0.269668326f,
+ 0.962121404f, 0.272621355f,
+ 0.961280486f, 0.275571819f,
+ 0.960430519f, 0.278519689f,
+ 0.959571513f, 0.281464938f,
+ 0.958703475f, 0.284407537f,
+ 0.957826413f, 0.287347460f,
+ 0.956940336f, 0.290284677f,
+ 0.956045251f, 0.293219163f,
+ 0.955141168f, 0.296150888f,
+ 0.954228095f, 0.299079826f,
+ 0.953306040f, 0.302005949f,
+ 0.952375013f, 0.304929230f,
+ 0.951435021f, 0.307849640f,
+ 0.950486074f, 0.310767153f,
+ 0.949528181f, 0.313681740f,
+ 0.948561350f, 0.316593376f,
+ 0.947585591f, 0.319502031f,
+ 0.946600913f, 0.322407679f,
+ 0.945607325f, 0.325310292f,
+ 0.944604837f, 0.328209844f,
+ 0.943593458f, 0.331106306f,
+ 0.942573198f, 0.333999651f,
+ 0.941544065f, 0.336889853f,
+ 0.940506071f, 0.339776884f,
+ 0.939459224f, 0.342660717f,
+ 0.938403534f, 0.345541325f,
+ 0.937339012f, 0.348418680f,
+ 0.936265667f, 0.351292756f,
+ 0.935183510f, 0.354163525f,
+ 0.934092550f, 0.357030961f,
+ 0.932992799f, 0.359895037f,
+ 0.931884266f, 0.362755724f,
+ 0.930766961f, 0.365612998f,
+ 0.929640896f, 0.368466830f,
+ 0.928506080f, 0.371317194f,
+ 0.927362526f, 0.374164063f,
+ 0.926210242f, 0.377007410f,
+ 0.925049241f, 0.379847209f,
+ 0.923879533f, 0.382683432f,
+ 0.922701128f, 0.385516054f,
+ 0.921514039f, 0.388345047f,
+ 0.920318277f, 0.391170384f,
+ 0.919113852f, 0.393992040f,
+ 0.917900776f, 0.396809987f,
+ 0.916679060f, 0.399624200f,
+ 0.915448716f, 0.402434651f,
+ 0.914209756f, 0.405241314f,
+ 0.912962190f, 0.408044163f,
+ 0.911706032f, 0.410843171f,
+ 0.910441292f, 0.413638312f,
+ 0.909167983f, 0.416429560f,
+ 0.907886116f, 0.419216888f,
+ 0.906595705f, 0.422000271f,
+ 0.905296759f, 0.424779681f,
+ 0.903989293f, 0.427555093f,
+ 0.902673318f, 0.430326481f,
+ 0.901348847f, 0.433093819f,
+ 0.900015892f, 0.435857080f,
+ 0.898674466f, 0.438616239f,
+ 0.897324581f, 0.441371269f,
+ 0.895966250f, 0.444122145f,
+ 0.894599486f, 0.446868840f,
+ 0.893224301f, 0.449611330f,
+ 0.891840709f, 0.452349587f,
+ 0.890448723f, 0.455083587f,
+ 0.889048356f, 0.457813304f,
+ 0.887639620f, 0.460538711f,
+ 0.886222530f, 0.463259784f,
+ 0.884797098f, 0.465976496f,
+ 0.883363339f, 0.468688822f,
+ 0.881921264f, 0.471396737f,
+ 0.880470889f, 0.474100215f,
+ 0.879012226f, 0.476799230f,
+ 0.877545290f, 0.479493758f,
+ 0.876070094f, 0.482183772f,
+ 0.874586652f, 0.484869248f,
+ 0.873094978f, 0.487550160f,
+ 0.871595087f, 0.490226483f,
+ 0.870086991f, 0.492898192f,
+ 0.868570706f, 0.495565262f,
+ 0.867046246f, 0.498227667f,
+ 0.865513624f, 0.500885383f,
+ 0.863972856f, 0.503538384f,
+ 0.862423956f, 0.506186645f,
+ 0.860866939f, 0.508830143f,
+ 0.859301818f, 0.511468850f,
+ 0.857728610f, 0.514102744f,
+ 0.856147328f, 0.516731799f,
+ 0.854557988f, 0.519355990f,
+ 0.852960605f, 0.521975293f,
+ 0.851355193f, 0.524589683f,
+ 0.849741768f, 0.527199135f,
+ 0.848120345f, 0.529803625f,
+ 0.846490939f, 0.532403128f,
+ 0.844853565f, 0.534997620f,
+ 0.843208240f, 0.537587076f,
+ 0.841554977f, 0.540171473f,
+ 0.839893794f, 0.542750785f,
+ 0.838224706f, 0.545324988f,
+ 0.836547727f, 0.547894059f,
+ 0.834862875f, 0.550457973f,
+ 0.833170165f, 0.553016706f,
+ 0.831469612f, 0.555570233f,
+ 0.829761234f, 0.558118531f,
+ 0.828045045f, 0.560661576f,
+ 0.826321063f, 0.563199344f,
+ 0.824589303f, 0.565731811f,
+ 0.822849781f, 0.568258953f,
+ 0.821102515f, 0.570780746f,
+ 0.819347520f, 0.573297167f,
+ 0.817584813f, 0.575808191f,
+ 0.815814411f, 0.578313796f,
+ 0.814036330f, 0.580813958f,
+ 0.812250587f, 0.583308653f,
+ 0.810457198f, 0.585797857f,
+ 0.808656182f, 0.588281548f,
+ 0.806847554f, 0.590759702f,
+ 0.805031331f, 0.593232295f,
+ 0.803207531f, 0.595699304f,
+ 0.801376172f, 0.598160707f,
+ 0.799537269f, 0.600616479f,
+ 0.797690841f, 0.603066599f,
+ 0.795836905f, 0.605511041f,
+ 0.793975478f, 0.607949785f,
+ 0.792106577f, 0.610382806f,
+ 0.790230221f, 0.612810082f,
+ 0.788346428f, 0.615231591f,
+ 0.786455214f, 0.617647308f,
+ 0.784556597f, 0.620057212f,
+ 0.782650596f, 0.622461279f,
+ 0.780737229f, 0.624859488f,
+ 0.778816512f, 0.627251815f,
+ 0.776888466f, 0.629638239f,
+ 0.774953107f, 0.632018736f,
+ 0.773010453f, 0.634393284f,
+ 0.771060524f, 0.636761861f,
+ 0.769103338f, 0.639124445f,
+ 0.767138912f, 0.641481013f,
+ 0.765167266f, 0.643831543f,
+ 0.763188417f, 0.646176013f,
+ 0.761202385f, 0.648514401f,
+ 0.759209189f, 0.650846685f,
+ 0.757208847f, 0.653172843f,
+ 0.755201377f, 0.655492853f,
+ 0.753186799f, 0.657806693f,
+ 0.751165132f, 0.660114342f,
+ 0.749136395f, 0.662415778f,
+ 0.747100606f, 0.664710978f,
+ 0.745057785f, 0.666999922f,
+ 0.743007952f, 0.669282588f,
+ 0.740951125f, 0.671558955f,
+ 0.738887324f, 0.673829000f,
+ 0.736816569f, 0.676092704f,
+ 0.734738878f, 0.678350043f,
+ 0.732654272f, 0.680600998f,
+ 0.730562769f, 0.682845546f,
+ 0.728464390f, 0.685083668f,
+ 0.726359155f, 0.687315341f,
+ 0.724247083f, 0.689540545f,
+ 0.722128194f, 0.691759258f,
+ 0.720002508f, 0.693971461f,
+ 0.717870045f, 0.696177131f,
+ 0.715730825f, 0.698376249f,
+ 0.713584869f, 0.700568794f,
+ 0.711432196f, 0.702754744f,
+ 0.709272826f, 0.704934080f,
+ 0.707106781f, 0.707106781f,
+ 0.704934080f, 0.709272826f,
+ 0.702754744f, 0.711432196f,
+ 0.700568794f, 0.713584869f,
+ 0.698376249f, 0.715730825f,
+ 0.696177131f, 0.717870045f,
+ 0.693971461f, 0.720002508f,
+ 0.691759258f, 0.722128194f,
+ 0.689540545f, 0.724247083f,
+ 0.687315341f, 0.726359155f,
+ 0.685083668f, 0.728464390f,
+ 0.682845546f, 0.730562769f,
+ 0.680600998f, 0.732654272f,
+ 0.678350043f, 0.734738878f,
+ 0.676092704f, 0.736816569f,
+ 0.673829000f, 0.738887324f,
+ 0.671558955f, 0.740951125f,
+ 0.669282588f, 0.743007952f,
+ 0.666999922f, 0.745057785f,
+ 0.664710978f, 0.747100606f,
+ 0.662415778f, 0.749136395f,
+ 0.660114342f, 0.751165132f,
+ 0.657806693f, 0.753186799f,
+ 0.655492853f, 0.755201377f,
+ 0.653172843f, 0.757208847f,
+ 0.650846685f, 0.759209189f,
+ 0.648514401f, 0.761202385f,
+ 0.646176013f, 0.763188417f,
+ 0.643831543f, 0.765167266f,
+ 0.641481013f, 0.767138912f,
+ 0.639124445f, 0.769103338f,
+ 0.636761861f, 0.771060524f,
+ 0.634393284f, 0.773010453f,
+ 0.632018736f, 0.774953107f,
+ 0.629638239f, 0.776888466f,
+ 0.627251815f, 0.778816512f,
+ 0.624859488f, 0.780737229f,
+ 0.622461279f, 0.782650596f,
+ 0.620057212f, 0.784556597f,
+ 0.617647308f, 0.786455214f,
+ 0.615231591f, 0.788346428f,
+ 0.612810082f, 0.790230221f,
+ 0.610382806f, 0.792106577f,
+ 0.607949785f, 0.793975478f,
+ 0.605511041f, 0.795836905f,
+ 0.603066599f, 0.797690841f,
+ 0.600616479f, 0.799537269f,
+ 0.598160707f, 0.801376172f,
+ 0.595699304f, 0.803207531f,
+ 0.593232295f, 0.805031331f,
+ 0.590759702f, 0.806847554f,
+ 0.588281548f, 0.808656182f,
+ 0.585797857f, 0.810457198f,
+ 0.583308653f, 0.812250587f,
+ 0.580813958f, 0.814036330f,
+ 0.578313796f, 0.815814411f,
+ 0.575808191f, 0.817584813f,
+ 0.573297167f, 0.819347520f,
+ 0.570780746f, 0.821102515f,
+ 0.568258953f, 0.822849781f,
+ 0.565731811f, 0.824589303f,
+ 0.563199344f, 0.826321063f,
+ 0.560661576f, 0.828045045f,
+ 0.558118531f, 0.829761234f,
+ 0.555570233f, 0.831469612f,
+ 0.553016706f, 0.833170165f,
+ 0.550457973f, 0.834862875f,
+ 0.547894059f, 0.836547727f,
+ 0.545324988f, 0.838224706f,
+ 0.542750785f, 0.839893794f,
+ 0.540171473f, 0.841554977f,
+ 0.537587076f, 0.843208240f,
+ 0.534997620f, 0.844853565f,
+ 0.532403128f, 0.846490939f,
+ 0.529803625f, 0.848120345f,
+ 0.527199135f, 0.849741768f,
+ 0.524589683f, 0.851355193f,
+ 0.521975293f, 0.852960605f,
+ 0.519355990f, 0.854557988f,
+ 0.516731799f, 0.856147328f,
+ 0.514102744f, 0.857728610f,
+ 0.511468850f, 0.859301818f,
+ 0.508830143f, 0.860866939f,
+ 0.506186645f, 0.862423956f,
+ 0.503538384f, 0.863972856f,
+ 0.500885383f, 0.865513624f,
+ 0.498227667f, 0.867046246f,
+ 0.495565262f, 0.868570706f,
+ 0.492898192f, 0.870086991f,
+ 0.490226483f, 0.871595087f,
+ 0.487550160f, 0.873094978f,
+ 0.484869248f, 0.874586652f,
+ 0.482183772f, 0.876070094f,
+ 0.479493758f, 0.877545290f,
+ 0.476799230f, 0.879012226f,
+ 0.474100215f, 0.880470889f,
+ 0.471396737f, 0.881921264f,
+ 0.468688822f, 0.883363339f,
+ 0.465976496f, 0.884797098f,
+ 0.463259784f, 0.886222530f,
+ 0.460538711f, 0.887639620f,
+ 0.457813304f, 0.889048356f,
+ 0.455083587f, 0.890448723f,
+ 0.452349587f, 0.891840709f,
+ 0.449611330f, 0.893224301f,
+ 0.446868840f, 0.894599486f,
+ 0.444122145f, 0.895966250f,
+ 0.441371269f, 0.897324581f,
+ 0.438616239f, 0.898674466f,
+ 0.435857080f, 0.900015892f,
+ 0.433093819f, 0.901348847f,
+ 0.430326481f, 0.902673318f,
+ 0.427555093f, 0.903989293f,
+ 0.424779681f, 0.905296759f,
+ 0.422000271f, 0.906595705f,
+ 0.419216888f, 0.907886116f,
+ 0.416429560f, 0.909167983f,
+ 0.413638312f, 0.910441292f,
+ 0.410843171f, 0.911706032f,
+ 0.408044163f, 0.912962190f,
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+ 0.990902635f, -0.134580709f,
+ 0.991310860f, -0.131540029f,
+ 0.991709754f, -0.128498111f,
+ 0.992099313f, -0.125454983f,
+ 0.992479535f, -0.122410675f,
+ 0.992850414f, -0.119365215f,
+ 0.993211949f, -0.116318631f,
+ 0.993564136f, -0.113270952f,
+ 0.993906970f, -0.110222207f,
+ 0.994240449f, -0.107172425f,
+ 0.994564571f, -0.104121634f,
+ 0.994879331f, -0.101069863f,
+ 0.995184727f, -0.098017140f,
+ 0.995480755f, -0.094963495f,
+ 0.995767414f, -0.091908956f,
+ 0.996044701f, -0.088853553f,
+ 0.996312612f, -0.085797312f,
+ 0.996571146f, -0.082740265f,
+ 0.996820299f, -0.079682438f,
+ 0.997060070f, -0.076623861f,
+ 0.997290457f, -0.073564564f,
+ 0.997511456f, -0.070504573f,
+ 0.997723067f, -0.067443920f,
+ 0.997925286f, -0.064382631f,
+ 0.998118113f, -0.061320736f,
+ 0.998301545f, -0.058258265f,
+ 0.998475581f, -0.055195244f,
+ 0.998640218f, -0.052131705f,
+ 0.998795456f, -0.049067674f,
+ 0.998941293f, -0.046003182f,
+ 0.999077728f, -0.042938257f,
+ 0.999204759f, -0.039872928f,
+ 0.999322385f, -0.036807223f,
+ 0.999430605f, -0.033741172f,
+ 0.999529418f, -0.030674803f,
+ 0.999618822f, -0.027608146f,
+ 0.999698819f, -0.024541229f,
+ 0.999769405f, -0.021474080f,
+ 0.999830582f, -0.018406730f,
+ 0.999882347f, -0.015339206f,
+ 0.999924702f, -0.012271538f,
+ 0.999957645f, -0.009203755f,
+ 0.999981175f, -0.006135885f,
+ 0.999995294f, -0.003067957f
+};
+
+/**
+* \par
+* Example code for Floating-point Twiddle factors Generation:
+* \par
+* <pre>for(i = 0; i< N/; i++)
+* {
+* twiddleCoef[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are in interleaved fashion
+*
+*/
+const float32_t twiddleCoef_4096[8192] = {
+ 1.000000000f, 0.000000000f,
+ 0.999998823f, 0.001533980f,
+ 0.999995294f, 0.003067957f,
+ 0.999989411f, 0.004601926f,
+ 0.999981175f, 0.006135885f,
+ 0.999970586f, 0.007669829f,
+ 0.999957645f, 0.009203755f,
+ 0.999942350f, 0.010737659f,
+ 0.999924702f, 0.012271538f,
+ 0.999904701f, 0.013805389f,
+ 0.999882347f, 0.015339206f,
+ 0.999857641f, 0.016872988f,
+ 0.999830582f, 0.018406730f,
+ 0.999801170f, 0.019940429f,
+ 0.999769405f, 0.021474080f,
+ 0.999735288f, 0.023007681f,
+ 0.999698819f, 0.024541229f,
+ 0.999659997f, 0.026074718f,
+ 0.999618822f, 0.027608146f,
+ 0.999575296f, 0.029141509f,
+ 0.999529418f, 0.030674803f,
+ 0.999481187f, 0.032208025f,
+ 0.999430605f, 0.033741172f,
+ 0.999377670f, 0.035274239f,
+ 0.999322385f, 0.036807223f,
+ 0.999264747f, 0.038340120f,
+ 0.999204759f, 0.039872928f,
+ 0.999142419f, 0.041405641f,
+ 0.999077728f, 0.042938257f,
+ 0.999010686f, 0.044470772f,
+ 0.998941293f, 0.046003182f,
+ 0.998869550f, 0.047535484f,
+ 0.998795456f, 0.049067674f,
+ 0.998719012f, 0.050599749f,
+ 0.998640218f, 0.052131705f,
+ 0.998559074f, 0.053663538f,
+ 0.998475581f, 0.055195244f,
+ 0.998389737f, 0.056726821f,
+ 0.998301545f, 0.058258265f,
+ 0.998211003f, 0.059789571f,
+ 0.998118113f, 0.061320736f,
+ 0.998022874f, 0.062851758f,
+ 0.997925286f, 0.064382631f,
+ 0.997825350f, 0.065913353f,
+ 0.997723067f, 0.067443920f,
+ 0.997618435f, 0.068974328f,
+ 0.997511456f, 0.070504573f,
+ 0.997402130f, 0.072034653f,
+ 0.997290457f, 0.073564564f,
+ 0.997176437f, 0.075094301f,
+ 0.997060070f, 0.076623861f,
+ 0.996941358f, 0.078153242f,
+ 0.996820299f, 0.079682438f,
+ 0.996696895f, 0.081211447f,
+ 0.996571146f, 0.082740265f,
+ 0.996443051f, 0.084268888f,
+ 0.996312612f, 0.085797312f,
+ 0.996179829f, 0.087325535f,
+ 0.996044701f, 0.088853553f,
+ 0.995907229f, 0.090381361f,
+ 0.995767414f, 0.091908956f,
+ 0.995625256f, 0.093436336f,
+ 0.995480755f, 0.094963495f,
+ 0.995333912f, 0.096490431f,
+ 0.995184727f, 0.098017140f,
+ 0.995033199f, 0.099543619f,
+ 0.994879331f, 0.101069863f,
+ 0.994723121f, 0.102595869f,
+ 0.994564571f, 0.104121634f,
+ 0.994403680f, 0.105647154f,
+ 0.994240449f, 0.107172425f,
+ 0.994074879f, 0.108697444f,
+ 0.993906970f, 0.110222207f,
+ 0.993736722f, 0.111746711f,
+ 0.993564136f, 0.113270952f,
+ 0.993389211f, 0.114794927f,
+ 0.993211949f, 0.116318631f,
+ 0.993032350f, 0.117842062f,
+ 0.992850414f, 0.119365215f,
+ 0.992666142f, 0.120888087f,
+ 0.992479535f, 0.122410675f,
+ 0.992290591f, 0.123932975f,
+ 0.992099313f, 0.125454983f,
+ 0.991905700f, 0.126976696f,
+ 0.991709754f, 0.128498111f,
+ 0.991511473f, 0.130019223f,
+ 0.991310860f, 0.131540029f,
+ 0.991107914f, 0.133060525f,
+ 0.990902635f, 0.134580709f,
+ 0.990695025f, 0.136100575f,
+ 0.990485084f, 0.137620122f,
+ 0.990272812f, 0.139139344f,
+ 0.990058210f, 0.140658239f,
+ 0.989841278f, 0.142176804f,
+ 0.989622017f, 0.143695033f,
+ 0.989400428f, 0.145212925f,
+ 0.989176510f, 0.146730474f,
+ 0.988950265f, 0.148247679f,
+ 0.988721692f, 0.149764535f,
+ 0.988490793f, 0.151281038f,
+ 0.988257568f, 0.152797185f,
+ 0.988022017f, 0.154312973f,
+ 0.987784142f, 0.155828398f,
+ 0.987543942f, 0.157343456f,
+ 0.987301418f, 0.158858143f,
+ 0.987056571f, 0.160372457f,
+ 0.986809402f, 0.161886394f,
+ 0.986559910f, 0.163399949f,
+ 0.986308097f, 0.164913120f,
+ 0.986053963f, 0.166425904f,
+ 0.985797509f, 0.167938295f,
+ 0.985538735f, 0.169450291f,
+ 0.985277642f, 0.170961889f,
+ 0.985014231f, 0.172473084f,
+ 0.984748502f, 0.173983873f,
+ 0.984480455f, 0.175494253f,
+ 0.984210092f, 0.177004220f,
+ 0.983937413f, 0.178513771f,
+ 0.983662419f, 0.180022901f,
+ 0.983385110f, 0.181531608f,
+ 0.983105487f, 0.183039888f,
+ 0.982823551f, 0.184547737f,
+ 0.982539302f, 0.186055152f,
+ 0.982252741f, 0.187562129f,
+ 0.981963869f, 0.189068664f,
+ 0.981672686f, 0.190574755f,
+ 0.981379193f, 0.192080397f,
+ 0.981083391f, 0.193585587f,
+ 0.980785280f, 0.195090322f,
+ 0.980484862f, 0.196594598f,
+ 0.980182136f, 0.198098411f,
+ 0.979877104f, 0.199601758f,
+ 0.979569766f, 0.201104635f,
+ 0.979260123f, 0.202607039f,
+ 0.978948175f, 0.204108966f,
+ 0.978633924f, 0.205610413f,
+ 0.978317371f, 0.207111376f,
+ 0.977998515f, 0.208611852f,
+ 0.977677358f, 0.210111837f,
+ 0.977353900f, 0.211611327f,
+ 0.977028143f, 0.213110320f,
+ 0.976700086f, 0.214608811f,
+ 0.976369731f, 0.216106797f,
+ 0.976037079f, 0.217604275f,
+ 0.975702130f, 0.219101240f,
+ 0.975364885f, 0.220597690f,
+ 0.975025345f, 0.222093621f,
+ 0.974683511f, 0.223589029f,
+ 0.974339383f, 0.225083911f,
+ 0.973992962f, 0.226578264f,
+ 0.973644250f, 0.228072083f,
+ 0.973293246f, 0.229565366f,
+ 0.972939952f, 0.231058108f,
+ 0.972584369f, 0.232550307f,
+ 0.972226497f, 0.234041959f,
+ 0.971866337f, 0.235533059f,
+ 0.971503891f, 0.237023606f,
+ 0.971139158f, 0.238513595f,
+ 0.970772141f, 0.240003022f,
+ 0.970402839f, 0.241491885f,
+ 0.970031253f, 0.242980180f,
+ 0.969657385f, 0.244467903f,
+ 0.969281235f, 0.245955050f,
+ 0.968902805f, 0.247441619f,
+ 0.968522094f, 0.248927606f,
+ 0.968139105f, 0.250413007f,
+ 0.967753837f, 0.251897818f,
+ 0.967366292f, 0.253382037f,
+ 0.966976471f, 0.254865660f,
+ 0.966584374f, 0.256348682f,
+ 0.966190003f, 0.257831102f,
+ 0.965793359f, 0.259312915f,
+ 0.965394442f, 0.260794118f,
+ 0.964993253f, 0.262274707f,
+ 0.964589793f, 0.263754679f,
+ 0.964184064f, 0.265234030f,
+ 0.963776066f, 0.266712757f,
+ 0.963365800f, 0.268190857f,
+ 0.962953267f, 0.269668326f,
+ 0.962538468f, 0.271145160f,
+ 0.962121404f, 0.272621355f,
+ 0.961702077f, 0.274096910f,
+ 0.961280486f, 0.275571819f,
+ 0.960856633f, 0.277046080f,
+ 0.960430519f, 0.278519689f,
+ 0.960002146f, 0.279992643f,
+ 0.959571513f, 0.281464938f,
+ 0.959138622f, 0.282936570f,
+ 0.958703475f, 0.284407537f,
+ 0.958266071f, 0.285877835f,
+ 0.957826413f, 0.287347460f,
+ 0.957384501f, 0.288816408f,
+ 0.956940336f, 0.290284677f,
+ 0.956493919f, 0.291752263f,
+ 0.956045251f, 0.293219163f,
+ 0.955594334f, 0.294685372f,
+ 0.955141168f, 0.296150888f,
+ 0.954685755f, 0.297615707f,
+ 0.954228095f, 0.299079826f,
+ 0.953768190f, 0.300543241f,
+ 0.953306040f, 0.302005949f,
+ 0.952841648f, 0.303467947f,
+ 0.952375013f, 0.304929230f,
+ 0.951906137f, 0.306389795f,
+ 0.951435021f, 0.307849640f,
+ 0.950961666f, 0.309308760f,
+ 0.950486074f, 0.310767153f,
+ 0.950008245f, 0.312224814f,
+ 0.949528181f, 0.313681740f,
+ 0.949045882f, 0.315137929f,
+ 0.948561350f, 0.316593376f,
+ 0.948074586f, 0.318048077f,
+ 0.947585591f, 0.319502031f,
+ 0.947094366f, 0.320955232f,
+ 0.946600913f, 0.322407679f,
+ 0.946105232f, 0.323859367f,
+ 0.945607325f, 0.325310292f,
+ 0.945107193f, 0.326760452f,
+ 0.944604837f, 0.328209844f,
+ 0.944100258f, 0.329658463f,
+ 0.943593458f, 0.331106306f,
+ 0.943084437f, 0.332553370f,
+ 0.942573198f, 0.333999651f,
+ 0.942059740f, 0.335445147f,
+ 0.941544065f, 0.336889853f,
+ 0.941026175f, 0.338333767f,
+ 0.940506071f, 0.339776884f,
+ 0.939983753f, 0.341219202f,
+ 0.939459224f, 0.342660717f,
+ 0.938932484f, 0.344101426f,
+ 0.938403534f, 0.345541325f,
+ 0.937872376f, 0.346980411f,
+ 0.937339012f, 0.348418680f,
+ 0.936803442f, 0.349856130f,
+ 0.936265667f, 0.351292756f,
+ 0.935725689f, 0.352728556f,
+ 0.935183510f, 0.354163525f,
+ 0.934639130f, 0.355597662f,
+ 0.934092550f, 0.357030961f,
+ 0.933543773f, 0.358463421f,
+ 0.932992799f, 0.359895037f,
+ 0.932439629f, 0.361325806f,
+ 0.931884266f, 0.362755724f,
+ 0.931326709f, 0.364184790f,
+ 0.930766961f, 0.365612998f,
+ 0.930205023f, 0.367040346f,
+ 0.929640896f, 0.368466830f,
+ 0.929074581f, 0.369892447f,
+ 0.928506080f, 0.371317194f,
+ 0.927935395f, 0.372741067f,
+ 0.927362526f, 0.374164063f,
+ 0.926787474f, 0.375586178f,
+ 0.926210242f, 0.377007410f,
+ 0.925630831f, 0.378427755f,
+ 0.925049241f, 0.379847209f,
+ 0.924465474f, 0.381265769f,
+ 0.923879533f, 0.382683432f,
+ 0.923291417f, 0.384100195f,
+ 0.922701128f, 0.385516054f,
+ 0.922108669f, 0.386931006f,
+ 0.921514039f, 0.388345047f,
+ 0.920917242f, 0.389758174f,
+ 0.920318277f, 0.391170384f,
+ 0.919717146f, 0.392581674f,
+ 0.919113852f, 0.393992040f,
+ 0.918508394f, 0.395401479f,
+ 0.917900776f, 0.396809987f,
+ 0.917290997f, 0.398217562f,
+ 0.916679060f, 0.399624200f,
+ 0.916064966f, 0.401029897f,
+ 0.915448716f, 0.402434651f,
+ 0.914830312f, 0.403838458f,
+ 0.914209756f, 0.405241314f,
+ 0.913587048f, 0.406643217f,
+ 0.912962190f, 0.408044163f,
+ 0.912335185f, 0.409444149f,
+ 0.911706032f, 0.410843171f,
+ 0.911074734f, 0.412241227f,
+ 0.910441292f, 0.413638312f,
+ 0.909805708f, 0.415034424f,
+ 0.909167983f, 0.416429560f,
+ 0.908528119f, 0.417823716f,
+ 0.907886116f, 0.419216888f,
+ 0.907241978f, 0.420609074f,
+ 0.906595705f, 0.422000271f,
+ 0.905947298f, 0.423390474f,
+ 0.905296759f, 0.424779681f,
+ 0.904644091f, 0.426167889f,
+ 0.903989293f, 0.427555093f,
+ 0.903332368f, 0.428941292f,
+ 0.902673318f, 0.430326481f,
+ 0.902012144f, 0.431710658f,
+ 0.901348847f, 0.433093819f,
+ 0.900683429f, 0.434475961f,
+ 0.900015892f, 0.435857080f,
+ 0.899346237f, 0.437237174f,
+ 0.898674466f, 0.438616239f,
+ 0.898000580f, 0.439994271f,
+ 0.897324581f, 0.441371269f,
+ 0.896646470f, 0.442747228f,
+ 0.895966250f, 0.444122145f,
+ 0.895283921f, 0.445496017f,
+ 0.894599486f, 0.446868840f,
+ 0.893912945f, 0.448240612f,
+ 0.893224301f, 0.449611330f,
+ 0.892533555f, 0.450980989f,
+ 0.891840709f, 0.452349587f,
+ 0.891145765f, 0.453717121f,
+ 0.890448723f, 0.455083587f,
+ 0.889749586f, 0.456448982f,
+ 0.889048356f, 0.457813304f,
+ 0.888345033f, 0.459176548f,
+ 0.887639620f, 0.460538711f,
+ 0.886932119f, 0.461899791f,
+ 0.886222530f, 0.463259784f,
+ 0.885510856f, 0.464618686f,
+ 0.884797098f, 0.465976496f,
+ 0.884081259f, 0.467333209f,
+ 0.883363339f, 0.468688822f,
+ 0.882643340f, 0.470043332f,
+ 0.881921264f, 0.471396737f,
+ 0.881197113f, 0.472749032f,
+ 0.880470889f, 0.474100215f,
+ 0.879742593f, 0.475450282f,
+ 0.879012226f, 0.476799230f,
+ 0.878279792f, 0.478147056f,
+ 0.877545290f, 0.479493758f,
+ 0.876808724f, 0.480839331f,
+ 0.876070094f, 0.482183772f,
+ 0.875329403f, 0.483527079f,
+ 0.874586652f, 0.484869248f,
+ 0.873841843f, 0.486210276f,
+ 0.873094978f, 0.487550160f,
+ 0.872346059f, 0.488888897f,
+ 0.871595087f, 0.490226483f,
+ 0.870842063f, 0.491562916f,
+ 0.870086991f, 0.492898192f,
+ 0.869329871f, 0.494232309f,
+ 0.868570706f, 0.495565262f,
+ 0.867809497f, 0.496897049f,
+ 0.867046246f, 0.498227667f,
+ 0.866280954f, 0.499557113f,
+ 0.865513624f, 0.500885383f,
+ 0.864744258f, 0.502212474f,
+ 0.863972856f, 0.503538384f,
+ 0.863199422f, 0.504863109f,
+ 0.862423956f, 0.506186645f,
+ 0.861646461f, 0.507508991f,
+ 0.860866939f, 0.508830143f,
+ 0.860085390f, 0.510150097f,
+ 0.859301818f, 0.511468850f,
+ 0.858516224f, 0.512786401f,
+ 0.857728610f, 0.514102744f,
+ 0.856938977f, 0.515417878f,
+ 0.856147328f, 0.516731799f,
+ 0.855353665f, 0.518044504f,
+ 0.854557988f, 0.519355990f,
+ 0.853760301f, 0.520666254f,
+ 0.852960605f, 0.521975293f,
+ 0.852158902f, 0.523283103f,
+ 0.851355193f, 0.524589683f,
+ 0.850549481f, 0.525895027f,
+ 0.849741768f, 0.527199135f,
+ 0.848932055f, 0.528502002f,
+ 0.848120345f, 0.529803625f,
+ 0.847306639f, 0.531104001f,
+ 0.846490939f, 0.532403128f,
+ 0.845673247f, 0.533701002f,
+ 0.844853565f, 0.534997620f,
+ 0.844031895f, 0.536292979f,
+ 0.843208240f, 0.537587076f,
+ 0.842382600f, 0.538879909f,
+ 0.841554977f, 0.540171473f,
+ 0.840725375f, 0.541461766f,
+ 0.839893794f, 0.542750785f,
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+ 0.998475581f, -0.055195244f,
+ 0.998559074f, -0.053663538f,
+ 0.998640218f, -0.052131705f,
+ 0.998719012f, -0.050599749f,
+ 0.998795456f, -0.049067674f,
+ 0.998869550f, -0.047535484f,
+ 0.998941293f, -0.046003182f,
+ 0.999010686f, -0.044470772f,
+ 0.999077728f, -0.042938257f,
+ 0.999142419f, -0.041405641f,
+ 0.999204759f, -0.039872928f,
+ 0.999264747f, -0.038340120f,
+ 0.999322385f, -0.036807223f,
+ 0.999377670f, -0.035274239f,
+ 0.999430605f, -0.033741172f,
+ 0.999481187f, -0.032208025f,
+ 0.999529418f, -0.030674803f,
+ 0.999575296f, -0.029141509f,
+ 0.999618822f, -0.027608146f,
+ 0.999659997f, -0.026074718f,
+ 0.999698819f, -0.024541229f,
+ 0.999735288f, -0.023007681f,
+ 0.999769405f, -0.021474080f,
+ 0.999801170f, -0.019940429f,
+ 0.999830582f, -0.018406730f,
+ 0.999857641f, -0.016872988f,
+ 0.999882347f, -0.015339206f,
+ 0.999904701f, -0.013805389f,
+ 0.999924702f, -0.012271538f,
+ 0.999942350f, -0.010737659f,
+ 0.999957645f, -0.009203755f,
+ 0.999970586f, -0.007669829f,
+ 0.999981175f, -0.006135885f,
+ 0.999989411f, -0.004601926f,
+ 0.999995294f, -0.003067957f,
+ 0.999998823f, -0.001533980f
+};
+
+/*
+* @brief Q31 Twiddle factors Table
+*/
+
+/**
+* \par
+* Example code for Q31 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q31(Fixed point 1.31):
+* round(twiddleCoefQ31(i) * pow(2, 31))
+*
+*/
+
+const q31_t twiddleCoefQ31[6144] = {
+ 0x7fffffff, 0x0, 0x7ffff621, 0x3243f5, 0x7fffd886, 0x6487e3, 0x7fffa72c,
+ 0x96cbc1,
+ 0x7fff6216, 0xc90f88, 0x7fff0943, 0xfb5330, 0x7ffe9cb2, 0x12d96b1,
+ 0x7ffe1c65, 0x15fda03,
+ 0x7ffd885a, 0x1921d20, 0x7ffce093, 0x1c45ffe, 0x7ffc250f, 0x1f6a297,
+ 0x7ffb55ce, 0x228e4e2,
+ 0x7ffa72d1, 0x25b26d7, 0x7ff97c18, 0x28d6870, 0x7ff871a2, 0x2bfa9a4,
+ 0x7ff75370, 0x2f1ea6c,
+ 0x7ff62182, 0x3242abf, 0x7ff4dbd9, 0x3566a96, 0x7ff38274, 0x388a9ea,
+ 0x7ff21553, 0x3bae8b2,
+ 0x7ff09478, 0x3ed26e6, 0x7feeffe1, 0x41f6480, 0x7fed5791, 0x451a177,
+ 0x7feb9b85, 0x483ddc3,
+ 0x7fe9cbc0, 0x4b6195d, 0x7fe7e841, 0x4e8543e, 0x7fe5f108, 0x51a8e5c,
+ 0x7fe3e616, 0x54cc7b1,
+ 0x7fe1c76b, 0x57f0035, 0x7fdf9508, 0x5b137df, 0x7fdd4eec, 0x5e36ea9,
+ 0x7fdaf519, 0x615a48b,
+ 0x7fd8878e, 0x647d97c, 0x7fd6064c, 0x67a0d76, 0x7fd37153, 0x6ac406f,
+ 0x7fd0c8a3, 0x6de7262,
+ 0x7fce0c3e, 0x710a345, 0x7fcb3c23, 0x742d311, 0x7fc85854, 0x77501be,
+ 0x7fc560cf, 0x7a72f45,
+ 0x7fc25596, 0x7d95b9e, 0x7fbf36aa, 0x80b86c2, 0x7fbc040a, 0x83db0a7,
+ 0x7fb8bdb8, 0x86fd947,
+ 0x7fb563b3, 0x8a2009a, 0x7fb1f5fc, 0x8d42699, 0x7fae7495, 0x9064b3a,
+ 0x7faadf7c, 0x9386e78,
+ 0x7fa736b4, 0x96a9049, 0x7fa37a3c, 0x99cb0a7, 0x7f9faa15, 0x9cecf89,
+ 0x7f9bc640, 0xa00ece8,
+ 0x7f97cebd, 0xa3308bd, 0x7f93c38c, 0xa6522fe, 0x7f8fa4b0, 0xa973ba5,
+ 0x7f8b7227, 0xac952aa,
+ 0x7f872bf3, 0xafb6805, 0x7f82d214, 0xb2d7baf, 0x7f7e648c, 0xb5f8d9f,
+ 0x7f79e35a, 0xb919dcf,
+ 0x7f754e80, 0xbc3ac35, 0x7f70a5fe, 0xbf5b8cb, 0x7f6be9d4, 0xc27c389,
+ 0x7f671a05, 0xc59cc68,
+ 0x7f62368f, 0xc8bd35e, 0x7f5d3f75, 0xcbdd865, 0x7f5834b7, 0xcefdb76,
+ 0x7f531655, 0xd21dc87,
+ 0x7f4de451, 0xd53db92, 0x7f489eaa, 0xd85d88f, 0x7f434563, 0xdb7d376,
+ 0x7f3dd87c, 0xde9cc40,
+ 0x7f3857f6, 0xe1bc2e4, 0x7f32c3d1, 0xe4db75b, 0x7f2d1c0e, 0xe7fa99e,
+ 0x7f2760af, 0xeb199a4,
+ 0x7f2191b4, 0xee38766, 0x7f1baf1e, 0xf1572dc, 0x7f15b8ee, 0xf475bff,
+ 0x7f0faf25, 0xf7942c7,
+ 0x7f0991c4, 0xfab272b, 0x7f0360cb, 0xfdd0926, 0x7efd1c3c, 0x100ee8ad,
+ 0x7ef6c418, 0x1040c5bb,
+ 0x7ef05860, 0x1072a048, 0x7ee9d914, 0x10a4784b, 0x7ee34636, 0x10d64dbd,
+ 0x7edc9fc6, 0x11082096,
+ 0x7ed5e5c6, 0x1139f0cf, 0x7ecf1837, 0x116bbe60, 0x7ec8371a, 0x119d8941,
+ 0x7ec14270, 0x11cf516a,
+ 0x7eba3a39, 0x120116d5, 0x7eb31e78, 0x1232d979, 0x7eabef2c, 0x1264994e,
+ 0x7ea4ac58, 0x1296564d,
+ 0x7e9d55fc, 0x12c8106f, 0x7e95ec1a, 0x12f9c7aa, 0x7e8e6eb2, 0x132b7bf9,
+ 0x7e86ddc6, 0x135d2d53,
+ 0x7e7f3957, 0x138edbb1, 0x7e778166, 0x13c0870a, 0x7e6fb5f4, 0x13f22f58,
+ 0x7e67d703, 0x1423d492,
+ 0x7e5fe493, 0x145576b1, 0x7e57dea7, 0x148715ae, 0x7e4fc53e, 0x14b8b17f,
+ 0x7e47985b, 0x14ea4a1f,
+ 0x7e3f57ff, 0x151bdf86, 0x7e37042a, 0x154d71aa, 0x7e2e9cdf, 0x157f0086,
+ 0x7e26221f, 0x15b08c12,
+ 0x7e1d93ea, 0x15e21445, 0x7e14f242, 0x16139918, 0x7e0c3d29, 0x16451a83,
+ 0x7e0374a0, 0x1676987f,
+ 0x7dfa98a8, 0x16a81305, 0x7df1a942, 0x16d98a0c, 0x7de8a670, 0x170afd8d,
+ 0x7ddf9034, 0x173c6d80,
+ 0x7dd6668f, 0x176dd9de, 0x7dcd2981, 0x179f429f, 0x7dc3d90d, 0x17d0a7bc,
+ 0x7dba7534, 0x1802092c,
+ 0x7db0fdf8, 0x183366e9, 0x7da77359, 0x1864c0ea, 0x7d9dd55a, 0x18961728,
+ 0x7d9423fc, 0x18c7699b,
+ 0x7d8a5f40, 0x18f8b83c, 0x7d808728, 0x192a0304, 0x7d769bb5, 0x195b49ea,
+ 0x7d6c9ce9, 0x198c8ce7,
+ 0x7d628ac6, 0x19bdcbf3, 0x7d58654d, 0x19ef0707, 0x7d4e2c7f, 0x1a203e1b,
+ 0x7d43e05e, 0x1a517128,
+ 0x7d3980ec, 0x1a82a026, 0x7d2f0e2b, 0x1ab3cb0d, 0x7d24881b, 0x1ae4f1d6,
+ 0x7d19eebf, 0x1b161479,
+ 0x7d0f4218, 0x1b4732ef, 0x7d048228, 0x1b784d30, 0x7cf9aef0, 0x1ba96335,
+ 0x7ceec873, 0x1bda74f6,
+ 0x7ce3ceb2, 0x1c0b826a, 0x7cd8c1ae, 0x1c3c8b8c, 0x7ccda169, 0x1c6d9053,
+ 0x7cc26de5, 0x1c9e90b8,
+ 0x7cb72724, 0x1ccf8cb3, 0x7cabcd28, 0x1d00843d, 0x7ca05ff1, 0x1d31774d,
+ 0x7c94df83, 0x1d6265dd,
+ 0x7c894bde, 0x1d934fe5, 0x7c7da505, 0x1dc4355e, 0x7c71eaf9, 0x1df5163f,
+ 0x7c661dbc, 0x1e25f282,
+ 0x7c5a3d50, 0x1e56ca1e, 0x7c4e49b7, 0x1e879d0d, 0x7c4242f2, 0x1eb86b46,
+ 0x7c362904, 0x1ee934c3,
+ 0x7c29fbee, 0x1f19f97b, 0x7c1dbbb3, 0x1f4ab968, 0x7c116853, 0x1f7b7481,
+ 0x7c0501d2, 0x1fac2abf,
+ 0x7bf88830, 0x1fdcdc1b, 0x7bebfb70, 0x200d888d, 0x7bdf5b94, 0x203e300d,
+ 0x7bd2a89e, 0x206ed295,
+ 0x7bc5e290, 0x209f701c, 0x7bb9096b, 0x20d0089c, 0x7bac1d31, 0x21009c0c,
+ 0x7b9f1de6, 0x21312a65,
+ 0x7b920b89, 0x2161b3a0, 0x7b84e61f, 0x219237b5, 0x7b77ada8, 0x21c2b69c,
+ 0x7b6a6227, 0x21f3304f,
+ 0x7b5d039e, 0x2223a4c5, 0x7b4f920e, 0x225413f8, 0x7b420d7a, 0x22847de0,
+ 0x7b3475e5, 0x22b4e274,
+ 0x7b26cb4f, 0x22e541af, 0x7b190dbc, 0x23159b88, 0x7b0b3d2c, 0x2345eff8,
+ 0x7afd59a4, 0x23763ef7,
+ 0x7aef6323, 0x23a6887f, 0x7ae159ae, 0x23d6cc87, 0x7ad33d45, 0x24070b08,
+ 0x7ac50dec, 0x243743fa,
+ 0x7ab6cba4, 0x24677758, 0x7aa8766f, 0x2497a517, 0x7a9a0e50, 0x24c7cd33,
+ 0x7a8b9348, 0x24f7efa2,
+ 0x7a7d055b, 0x25280c5e, 0x7a6e648a, 0x2558235f, 0x7a5fb0d8, 0x2588349d,
+ 0x7a50ea47, 0x25b84012,
+ 0x7a4210d8, 0x25e845b6, 0x7a332490, 0x26184581, 0x7a24256f, 0x26483f6c,
+ 0x7a151378, 0x26783370,
+ 0x7a05eead, 0x26a82186, 0x79f6b711, 0x26d809a5, 0x79e76ca7, 0x2707ebc7,
+ 0x79d80f6f, 0x2737c7e3,
+ 0x79c89f6e, 0x27679df4, 0x79b91ca4, 0x27976df1, 0x79a98715, 0x27c737d3,
+ 0x7999dec4, 0x27f6fb92,
+ 0x798a23b1, 0x2826b928, 0x797a55e0, 0x2856708d, 0x796a7554, 0x288621b9,
+ 0x795a820e, 0x28b5cca5,
+ 0x794a7c12, 0x28e5714b, 0x793a6361, 0x29150fa1, 0x792a37fe, 0x2944a7a2,
+ 0x7919f9ec, 0x29743946,
+ 0x7909a92d, 0x29a3c485, 0x78f945c3, 0x29d34958, 0x78e8cfb2, 0x2a02c7b8,
+ 0x78d846fb, 0x2a323f9e,
+ 0x78c7aba2, 0x2a61b101, 0x78b6fda8, 0x2a911bdc, 0x78a63d11, 0x2ac08026,
+ 0x789569df, 0x2aefddd8,
+ 0x78848414, 0x2b1f34eb, 0x78738bb3, 0x2b4e8558, 0x786280bf, 0x2b7dcf17,
+ 0x7851633b, 0x2bad1221,
+ 0x78403329, 0x2bdc4e6f, 0x782ef08b, 0x2c0b83fa, 0x781d9b65, 0x2c3ab2b9,
+ 0x780c33b8, 0x2c69daa6,
+ 0x77fab989, 0x2c98fbba, 0x77e92cd9, 0x2cc815ee, 0x77d78daa, 0x2cf72939,
+ 0x77c5dc01, 0x2d263596,
+ 0x77b417df, 0x2d553afc, 0x77a24148, 0x2d843964, 0x7790583e, 0x2db330c7,
+ 0x777e5cc3, 0x2de2211e,
+ 0x776c4edb, 0x2e110a62, 0x775a2e89, 0x2e3fec8b, 0x7747fbce, 0x2e6ec792,
+ 0x7735b6af, 0x2e9d9b70,
+ 0x77235f2d, 0x2ecc681e, 0x7710f54c, 0x2efb2d95, 0x76fe790e, 0x2f29ebcc,
+ 0x76ebea77, 0x2f58a2be,
+ 0x76d94989, 0x2f875262, 0x76c69647, 0x2fb5fab2, 0x76b3d0b4, 0x2fe49ba7,
+ 0x76a0f8d2, 0x30133539,
+ 0x768e0ea6, 0x3041c761, 0x767b1231, 0x30705217, 0x76680376, 0x309ed556,
+ 0x7654e279, 0x30cd5115,
+ 0x7641af3d, 0x30fbc54d, 0x762e69c4, 0x312a31f8, 0x761b1211, 0x3158970e,
+ 0x7607a828, 0x3186f487,
+ 0x75f42c0b, 0x31b54a5e, 0x75e09dbd, 0x31e39889, 0x75ccfd42, 0x3211df04,
+ 0x75b94a9c, 0x32401dc6,
+ 0x75a585cf, 0x326e54c7, 0x7591aedd, 0x329c8402, 0x757dc5ca, 0x32caab6f,
+ 0x7569ca99, 0x32f8cb07,
+ 0x7555bd4c, 0x3326e2c3, 0x75419de7, 0x3354f29b, 0x752d6c6c, 0x3382fa88,
+ 0x751928e0, 0x33b0fa84,
+ 0x7504d345, 0x33def287, 0x74f06b9e, 0x340ce28b, 0x74dbf1ef, 0x343aca87,
+ 0x74c7663a, 0x3468aa76,
+ 0x74b2c884, 0x34968250, 0x749e18cd, 0x34c4520d, 0x7489571c, 0x34f219a8,
+ 0x74748371, 0x351fd918,
+ 0x745f9dd1, 0x354d9057, 0x744aa63f, 0x357b3f5d, 0x74359cbd, 0x35a8e625,
+ 0x74208150, 0x35d684a6,
+ 0x740b53fb, 0x36041ad9, 0x73f614c0, 0x3631a8b8, 0x73e0c3a3, 0x365f2e3b,
+ 0x73cb60a8, 0x368cab5c,
+ 0x73b5ebd1, 0x36ba2014, 0x73a06522, 0x36e78c5b, 0x738acc9e, 0x3714f02a,
+ 0x73752249, 0x37424b7b,
+ 0x735f6626, 0x376f9e46, 0x73499838, 0x379ce885, 0x7333b883, 0x37ca2a30,
+ 0x731dc70a, 0x37f76341,
+ 0x7307c3d0, 0x382493b0, 0x72f1aed9, 0x3851bb77, 0x72db8828, 0x387eda8e,
+ 0x72c54fc1, 0x38abf0ef,
+ 0x72af05a7, 0x38d8fe93, 0x7298a9dd, 0x39060373, 0x72823c67, 0x3932ff87,
+ 0x726bbd48, 0x395ff2c9,
+ 0x72552c85, 0x398cdd32, 0x723e8a20, 0x39b9bebc, 0x7227d61c, 0x39e6975e,
+ 0x7211107e, 0x3a136712,
+ 0x71fa3949, 0x3a402dd2, 0x71e35080, 0x3a6ceb96, 0x71cc5626, 0x3a99a057,
+ 0x71b54a41, 0x3ac64c0f,
+ 0x719e2cd2, 0x3af2eeb7, 0x7186fdde, 0x3b1f8848, 0x716fbd68, 0x3b4c18ba,
+ 0x71586b74, 0x3b78a007,
+ 0x71410805, 0x3ba51e29, 0x7129931f, 0x3bd19318, 0x71120cc5, 0x3bfdfecd,
+ 0x70fa74fc, 0x3c2a6142,
+ 0x70e2cbc6, 0x3c56ba70, 0x70cb1128, 0x3c830a50, 0x70b34525, 0x3caf50da,
+ 0x709b67c0, 0x3cdb8e09,
+ 0x708378ff, 0x3d07c1d6, 0x706b78e3, 0x3d33ec39, 0x70536771, 0x3d600d2c,
+ 0x703b44ad, 0x3d8c24a8,
+ 0x7023109a, 0x3db832a6, 0x700acb3c, 0x3de4371f, 0x6ff27497, 0x3e10320d,
+ 0x6fda0cae, 0x3e3c2369,
+ 0x6fc19385, 0x3e680b2c, 0x6fa90921, 0x3e93e950, 0x6f906d84, 0x3ebfbdcd,
+ 0x6f77c0b3, 0x3eeb889c,
+ 0x6f5f02b2, 0x3f1749b8, 0x6f463383, 0x3f430119, 0x6f2d532c, 0x3f6eaeb8,
+ 0x6f1461b0, 0x3f9a5290,
+ 0x6efb5f12, 0x3fc5ec98, 0x6ee24b57, 0x3ff17cca, 0x6ec92683, 0x401d0321,
+ 0x6eaff099, 0x40487f94,
+ 0x6e96a99d, 0x4073f21d, 0x6e7d5193, 0x409f5ab6, 0x6e63e87f, 0x40cab958,
+ 0x6e4a6e66, 0x40f60dfb,
+ 0x6e30e34a, 0x4121589b, 0x6e174730, 0x414c992f, 0x6dfd9a1c, 0x4177cfb1,
+ 0x6de3dc11, 0x41a2fc1a,
+ 0x6dca0d14, 0x41ce1e65, 0x6db02d29, 0x41f93689, 0x6d963c54, 0x42244481,
+ 0x6d7c3a98, 0x424f4845,
+ 0x6d6227fa, 0x427a41d0, 0x6d48047e, 0x42a5311b, 0x6d2dd027, 0x42d0161e,
+ 0x6d138afb, 0x42faf0d4,
+ 0x6cf934fc, 0x4325c135, 0x6cdece2f, 0x4350873c, 0x6cc45698, 0x437b42e1,
+ 0x6ca9ce3b, 0x43a5f41e,
+ 0x6c8f351c, 0x43d09aed, 0x6c748b3f, 0x43fb3746, 0x6c59d0a9, 0x4425c923,
+ 0x6c3f055d, 0x4450507e,
+ 0x6c242960, 0x447acd50, 0x6c093cb6, 0x44a53f93, 0x6bee3f62, 0x44cfa740,
+ 0x6bd3316a, 0x44fa0450,
+ 0x6bb812d1, 0x452456bd, 0x6b9ce39b, 0x454e9e80, 0x6b81a3cd, 0x4578db93,
+ 0x6b66536b, 0x45a30df0,
+ 0x6b4af279, 0x45cd358f, 0x6b2f80fb, 0x45f7526b, 0x6b13fef5, 0x4621647d,
+ 0x6af86c6c, 0x464b6bbe,
+ 0x6adcc964, 0x46756828, 0x6ac115e2, 0x469f59b4, 0x6aa551e9, 0x46c9405c,
+ 0x6a897d7d, 0x46f31c1a,
+ 0x6a6d98a4, 0x471cece7, 0x6a51a361, 0x4746b2bc, 0x6a359db9, 0x47706d93,
+ 0x6a1987b0, 0x479a1d67,
+ 0x69fd614a, 0x47c3c22f, 0x69e12a8c, 0x47ed5be6, 0x69c4e37a, 0x4816ea86,
+ 0x69a88c19, 0x48406e08,
+ 0x698c246c, 0x4869e665, 0x696fac78, 0x48935397, 0x69532442, 0x48bcb599,
+ 0x69368bce, 0x48e60c62,
+ 0x6919e320, 0x490f57ee, 0x68fd2a3d, 0x49389836, 0x68e06129, 0x4961cd33,
+ 0x68c387e9, 0x498af6df,
+ 0x68a69e81, 0x49b41533, 0x6889a4f6, 0x49dd282a, 0x686c9b4b, 0x4a062fbd,
+ 0x684f8186, 0x4a2f2be6,
+ 0x683257ab, 0x4a581c9e, 0x68151dbe, 0x4a8101de, 0x67f7d3c5, 0x4aa9dba2,
+ 0x67da79c3, 0x4ad2a9e2,
+ 0x67bd0fbd, 0x4afb6c98, 0x679f95b7, 0x4b2423be, 0x67820bb7, 0x4b4ccf4d,
+ 0x676471c0, 0x4b756f40,
+ 0x6746c7d8, 0x4b9e0390, 0x67290e02, 0x4bc68c36, 0x670b4444, 0x4bef092d,
+ 0x66ed6aa1, 0x4c177a6e,
+ 0x66cf8120, 0x4c3fdff4, 0x66b187c3, 0x4c6839b7, 0x66937e91, 0x4c9087b1,
+ 0x6675658c, 0x4cb8c9dd,
+ 0x66573cbb, 0x4ce10034, 0x66390422, 0x4d092ab0, 0x661abbc5, 0x4d31494b,
+ 0x65fc63a9, 0x4d595bfe,
+ 0x65ddfbd3, 0x4d8162c4, 0x65bf8447, 0x4da95d96, 0x65a0fd0b, 0x4dd14c6e,
+ 0x65826622, 0x4df92f46,
+ 0x6563bf92, 0x4e210617, 0x6545095f, 0x4e48d0dd, 0x6526438f, 0x4e708f8f,
+ 0x65076e25, 0x4e984229,
+ 0x64e88926, 0x4ebfe8a5, 0x64c99498, 0x4ee782fb, 0x64aa907f, 0x4f0f1126,
+ 0x648b7ce0, 0x4f369320,
+ 0x646c59bf, 0x4f5e08e3, 0x644d2722, 0x4f857269, 0x642de50d, 0x4faccfab,
+ 0x640e9386, 0x4fd420a4,
+ 0x63ef3290, 0x4ffb654d, 0x63cfc231, 0x50229da1, 0x63b0426d, 0x5049c999,
+ 0x6390b34a, 0x5070e92f,
+ 0x637114cc, 0x5097fc5e, 0x635166f9, 0x50bf031f, 0x6331a9d4, 0x50e5fd6d,
+ 0x6311dd64, 0x510ceb40,
+ 0x62f201ac, 0x5133cc94, 0x62d216b3, 0x515aa162, 0x62b21c7b, 0x518169a5,
+ 0x6292130c, 0x51a82555,
+ 0x6271fa69, 0x51ced46e, 0x6251d298, 0x51f576ea, 0x62319b9d, 0x521c0cc2,
+ 0x6211557e, 0x524295f0,
+ 0x61f1003f, 0x5269126e, 0x61d09be5, 0x528f8238, 0x61b02876, 0x52b5e546,
+ 0x618fa5f7, 0x52dc3b92,
+ 0x616f146c, 0x53028518, 0x614e73da, 0x5328c1d0, 0x612dc447, 0x534ef1b5,
+ 0x610d05b7, 0x537514c2,
+ 0x60ec3830, 0x539b2af0, 0x60cb5bb7, 0x53c13439, 0x60aa7050, 0x53e73097,
+ 0x60897601, 0x540d2005,
+ 0x60686ccf, 0x5433027d, 0x604754bf, 0x5458d7f9, 0x60262dd6, 0x547ea073,
+ 0x6004f819, 0x54a45be6,
+ 0x5fe3b38d, 0x54ca0a4b, 0x5fc26038, 0x54efab9c, 0x5fa0fe1f, 0x55153fd4,
+ 0x5f7f8d46, 0x553ac6ee,
+ 0x5f5e0db3, 0x556040e2, 0x5f3c7f6b, 0x5585adad, 0x5f1ae274, 0x55ab0d46,
+ 0x5ef936d1, 0x55d05faa,
+ 0x5ed77c8a, 0x55f5a4d2, 0x5eb5b3a2, 0x561adcb9, 0x5e93dc1f, 0x56400758,
+ 0x5e71f606, 0x566524aa,
+ 0x5e50015d, 0x568a34a9, 0x5e2dfe29, 0x56af3750, 0x5e0bec6e, 0x56d42c99,
+ 0x5de9cc33, 0x56f9147e,
+ 0x5dc79d7c, 0x571deefa, 0x5da5604f, 0x5742bc06, 0x5d8314b1, 0x57677b9d,
+ 0x5d60baa7, 0x578c2dba,
+ 0x5d3e5237, 0x57b0d256, 0x5d1bdb65, 0x57d5696d, 0x5cf95638, 0x57f9f2f8,
+ 0x5cd6c2b5, 0x581e6ef1,
+ 0x5cb420e0, 0x5842dd54, 0x5c9170bf, 0x58673e1b, 0x5c6eb258, 0x588b9140,
+ 0x5c4be5b0, 0x58afd6bd,
+ 0x5c290acc, 0x58d40e8c, 0x5c0621b2, 0x58f838a9, 0x5be32a67, 0x591c550e,
+ 0x5bc024f0, 0x594063b5,
+ 0x5b9d1154, 0x59646498, 0x5b79ef96, 0x598857b2, 0x5b56bfbd, 0x59ac3cfd,
+ 0x5b3381ce, 0x59d01475,
+ 0x5b1035cf, 0x59f3de12, 0x5aecdbc5, 0x5a1799d1, 0x5ac973b5, 0x5a3b47ab,
+ 0x5aa5fda5, 0x5a5ee79a,
+ 0x5a82799a, 0x5a82799a, 0x5a5ee79a, 0x5aa5fda5, 0x5a3b47ab, 0x5ac973b5,
+ 0x5a1799d1, 0x5aecdbc5,
+ 0x59f3de12, 0x5b1035cf, 0x59d01475, 0x5b3381ce, 0x59ac3cfd, 0x5b56bfbd,
+ 0x598857b2, 0x5b79ef96,
+ 0x59646498, 0x5b9d1154, 0x594063b5, 0x5bc024f0, 0x591c550e, 0x5be32a67,
+ 0x58f838a9, 0x5c0621b2,
+ 0x58d40e8c, 0x5c290acc, 0x58afd6bd, 0x5c4be5b0, 0x588b9140, 0x5c6eb258,
+ 0x58673e1b, 0x5c9170bf,
+ 0x5842dd54, 0x5cb420e0, 0x581e6ef1, 0x5cd6c2b5, 0x57f9f2f8, 0x5cf95638,
+ 0x57d5696d, 0x5d1bdb65,
+ 0x57b0d256, 0x5d3e5237, 0x578c2dba, 0x5d60baa7, 0x57677b9d, 0x5d8314b1,
+ 0x5742bc06, 0x5da5604f,
+ 0x571deefa, 0x5dc79d7c, 0x56f9147e, 0x5de9cc33, 0x56d42c99, 0x5e0bec6e,
+ 0x56af3750, 0x5e2dfe29,
+ 0x568a34a9, 0x5e50015d, 0x566524aa, 0x5e71f606, 0x56400758, 0x5e93dc1f,
+ 0x561adcb9, 0x5eb5b3a2,
+ 0x55f5a4d2, 0x5ed77c8a, 0x55d05faa, 0x5ef936d1, 0x55ab0d46, 0x5f1ae274,
+ 0x5585adad, 0x5f3c7f6b,
+ 0x556040e2, 0x5f5e0db3, 0x553ac6ee, 0x5f7f8d46, 0x55153fd4, 0x5fa0fe1f,
+ 0x54efab9c, 0x5fc26038,
+ 0x54ca0a4b, 0x5fe3b38d, 0x54a45be6, 0x6004f819, 0x547ea073, 0x60262dd6,
+ 0x5458d7f9, 0x604754bf,
+ 0x5433027d, 0x60686ccf, 0x540d2005, 0x60897601, 0x53e73097, 0x60aa7050,
+ 0x53c13439, 0x60cb5bb7,
+ 0x539b2af0, 0x60ec3830, 0x537514c2, 0x610d05b7, 0x534ef1b5, 0x612dc447,
+ 0x5328c1d0, 0x614e73da,
+ 0x53028518, 0x616f146c, 0x52dc3b92, 0x618fa5f7, 0x52b5e546, 0x61b02876,
+ 0x528f8238, 0x61d09be5,
+ 0x5269126e, 0x61f1003f, 0x524295f0, 0x6211557e, 0x521c0cc2, 0x62319b9d,
+ 0x51f576ea, 0x6251d298,
+ 0x51ced46e, 0x6271fa69, 0x51a82555, 0x6292130c, 0x518169a5, 0x62b21c7b,
+ 0x515aa162, 0x62d216b3,
+ 0x5133cc94, 0x62f201ac, 0x510ceb40, 0x6311dd64, 0x50e5fd6d, 0x6331a9d4,
+ 0x50bf031f, 0x635166f9,
+ 0x5097fc5e, 0x637114cc, 0x5070e92f, 0x6390b34a, 0x5049c999, 0x63b0426d,
+ 0x50229da1, 0x63cfc231,
+ 0x4ffb654d, 0x63ef3290, 0x4fd420a4, 0x640e9386, 0x4faccfab, 0x642de50d,
+ 0x4f857269, 0x644d2722,
+ 0x4f5e08e3, 0x646c59bf, 0x4f369320, 0x648b7ce0, 0x4f0f1126, 0x64aa907f,
+ 0x4ee782fb, 0x64c99498,
+ 0x4ebfe8a5, 0x64e88926, 0x4e984229, 0x65076e25, 0x4e708f8f, 0x6526438f,
+ 0x4e48d0dd, 0x6545095f,
+ 0x4e210617, 0x6563bf92, 0x4df92f46, 0x65826622, 0x4dd14c6e, 0x65a0fd0b,
+ 0x4da95d96, 0x65bf8447,
+ 0x4d8162c4, 0x65ddfbd3, 0x4d595bfe, 0x65fc63a9, 0x4d31494b, 0x661abbc5,
+ 0x4d092ab0, 0x66390422,
+ 0x4ce10034, 0x66573cbb, 0x4cb8c9dd, 0x6675658c, 0x4c9087b1, 0x66937e91,
+ 0x4c6839b7, 0x66b187c3,
+ 0x4c3fdff4, 0x66cf8120, 0x4c177a6e, 0x66ed6aa1, 0x4bef092d, 0x670b4444,
+ 0x4bc68c36, 0x67290e02,
+ 0x4b9e0390, 0x6746c7d8, 0x4b756f40, 0x676471c0, 0x4b4ccf4d, 0x67820bb7,
+ 0x4b2423be, 0x679f95b7,
+ 0x4afb6c98, 0x67bd0fbd, 0x4ad2a9e2, 0x67da79c3, 0x4aa9dba2, 0x67f7d3c5,
+ 0x4a8101de, 0x68151dbe,
+ 0x4a581c9e, 0x683257ab, 0x4a2f2be6, 0x684f8186, 0x4a062fbd, 0x686c9b4b,
+ 0x49dd282a, 0x6889a4f6,
+ 0x49b41533, 0x68a69e81, 0x498af6df, 0x68c387e9, 0x4961cd33, 0x68e06129,
+ 0x49389836, 0x68fd2a3d,
+ 0x490f57ee, 0x6919e320, 0x48e60c62, 0x69368bce, 0x48bcb599, 0x69532442,
+ 0x48935397, 0x696fac78,
+ 0x4869e665, 0x698c246c, 0x48406e08, 0x69a88c19, 0x4816ea86, 0x69c4e37a,
+ 0x47ed5be6, 0x69e12a8c,
+ 0x47c3c22f, 0x69fd614a, 0x479a1d67, 0x6a1987b0, 0x47706d93, 0x6a359db9,
+ 0x4746b2bc, 0x6a51a361,
+ 0x471cece7, 0x6a6d98a4, 0x46f31c1a, 0x6a897d7d, 0x46c9405c, 0x6aa551e9,
+ 0x469f59b4, 0x6ac115e2,
+ 0x46756828, 0x6adcc964, 0x464b6bbe, 0x6af86c6c, 0x4621647d, 0x6b13fef5,
+ 0x45f7526b, 0x6b2f80fb,
+ 0x45cd358f, 0x6b4af279, 0x45a30df0, 0x6b66536b, 0x4578db93, 0x6b81a3cd,
+ 0x454e9e80, 0x6b9ce39b,
+ 0x452456bd, 0x6bb812d1, 0x44fa0450, 0x6bd3316a, 0x44cfa740, 0x6bee3f62,
+ 0x44a53f93, 0x6c093cb6,
+ 0x447acd50, 0x6c242960, 0x4450507e, 0x6c3f055d, 0x4425c923, 0x6c59d0a9,
+ 0x43fb3746, 0x6c748b3f,
+ 0x43d09aed, 0x6c8f351c, 0x43a5f41e, 0x6ca9ce3b, 0x437b42e1, 0x6cc45698,
+ 0x4350873c, 0x6cdece2f,
+ 0x4325c135, 0x6cf934fc, 0x42faf0d4, 0x6d138afb, 0x42d0161e, 0x6d2dd027,
+ 0x42a5311b, 0x6d48047e,
+ 0x427a41d0, 0x6d6227fa, 0x424f4845, 0x6d7c3a98, 0x42244481, 0x6d963c54,
+ 0x41f93689, 0x6db02d29,
+ 0x41ce1e65, 0x6dca0d14, 0x41a2fc1a, 0x6de3dc11, 0x4177cfb1, 0x6dfd9a1c,
+ 0x414c992f, 0x6e174730,
+ 0x4121589b, 0x6e30e34a, 0x40f60dfb, 0x6e4a6e66, 0x40cab958, 0x6e63e87f,
+ 0x409f5ab6, 0x6e7d5193,
+ 0x4073f21d, 0x6e96a99d, 0x40487f94, 0x6eaff099, 0x401d0321, 0x6ec92683,
+ 0x3ff17cca, 0x6ee24b57,
+ 0x3fc5ec98, 0x6efb5f12, 0x3f9a5290, 0x6f1461b0, 0x3f6eaeb8, 0x6f2d532c,
+ 0x3f430119, 0x6f463383,
+ 0x3f1749b8, 0x6f5f02b2, 0x3eeb889c, 0x6f77c0b3, 0x3ebfbdcd, 0x6f906d84,
+ 0x3e93e950, 0x6fa90921,
+ 0x3e680b2c, 0x6fc19385, 0x3e3c2369, 0x6fda0cae, 0x3e10320d, 0x6ff27497,
+ 0x3de4371f, 0x700acb3c,
+ 0x3db832a6, 0x7023109a, 0x3d8c24a8, 0x703b44ad, 0x3d600d2c, 0x70536771,
+ 0x3d33ec39, 0x706b78e3,
+ 0x3d07c1d6, 0x708378ff, 0x3cdb8e09, 0x709b67c0, 0x3caf50da, 0x70b34525,
+ 0x3c830a50, 0x70cb1128,
+ 0x3c56ba70, 0x70e2cbc6, 0x3c2a6142, 0x70fa74fc, 0x3bfdfecd, 0x71120cc5,
+ 0x3bd19318, 0x7129931f,
+ 0x3ba51e29, 0x71410805, 0x3b78a007, 0x71586b74, 0x3b4c18ba, 0x716fbd68,
+ 0x3b1f8848, 0x7186fdde,
+ 0x3af2eeb7, 0x719e2cd2, 0x3ac64c0f, 0x71b54a41, 0x3a99a057, 0x71cc5626,
+ 0x3a6ceb96, 0x71e35080,
+ 0x3a402dd2, 0x71fa3949, 0x3a136712, 0x7211107e, 0x39e6975e, 0x7227d61c,
+ 0x39b9bebc, 0x723e8a20,
+ 0x398cdd32, 0x72552c85, 0x395ff2c9, 0x726bbd48, 0x3932ff87, 0x72823c67,
+ 0x39060373, 0x7298a9dd,
+ 0x38d8fe93, 0x72af05a7, 0x38abf0ef, 0x72c54fc1, 0x387eda8e, 0x72db8828,
+ 0x3851bb77, 0x72f1aed9,
+ 0x382493b0, 0x7307c3d0, 0x37f76341, 0x731dc70a, 0x37ca2a30, 0x7333b883,
+ 0x379ce885, 0x73499838,
+ 0x376f9e46, 0x735f6626, 0x37424b7b, 0x73752249, 0x3714f02a, 0x738acc9e,
+ 0x36e78c5b, 0x73a06522,
+ 0x36ba2014, 0x73b5ebd1, 0x368cab5c, 0x73cb60a8, 0x365f2e3b, 0x73e0c3a3,
+ 0x3631a8b8, 0x73f614c0,
+ 0x36041ad9, 0x740b53fb, 0x35d684a6, 0x74208150, 0x35a8e625, 0x74359cbd,
+ 0x357b3f5d, 0x744aa63f,
+ 0x354d9057, 0x745f9dd1, 0x351fd918, 0x74748371, 0x34f219a8, 0x7489571c,
+ 0x34c4520d, 0x749e18cd,
+ 0x34968250, 0x74b2c884, 0x3468aa76, 0x74c7663a, 0x343aca87, 0x74dbf1ef,
+ 0x340ce28b, 0x74f06b9e,
+ 0x33def287, 0x7504d345, 0x33b0fa84, 0x751928e0, 0x3382fa88, 0x752d6c6c,
+ 0x3354f29b, 0x75419de7,
+ 0x3326e2c3, 0x7555bd4c, 0x32f8cb07, 0x7569ca99, 0x32caab6f, 0x757dc5ca,
+ 0x329c8402, 0x7591aedd,
+ 0x326e54c7, 0x75a585cf, 0x32401dc6, 0x75b94a9c, 0x3211df04, 0x75ccfd42,
+ 0x31e39889, 0x75e09dbd,
+ 0x31b54a5e, 0x75f42c0b, 0x3186f487, 0x7607a828, 0x3158970e, 0x761b1211,
+ 0x312a31f8, 0x762e69c4,
+ 0x30fbc54d, 0x7641af3d, 0x30cd5115, 0x7654e279, 0x309ed556, 0x76680376,
+ 0x30705217, 0x767b1231,
+ 0x3041c761, 0x768e0ea6, 0x30133539, 0x76a0f8d2, 0x2fe49ba7, 0x76b3d0b4,
+ 0x2fb5fab2, 0x76c69647,
+ 0x2f875262, 0x76d94989, 0x2f58a2be, 0x76ebea77, 0x2f29ebcc, 0x76fe790e,
+ 0x2efb2d95, 0x7710f54c,
+ 0x2ecc681e, 0x77235f2d, 0x2e9d9b70, 0x7735b6af, 0x2e6ec792, 0x7747fbce,
+ 0x2e3fec8b, 0x775a2e89,
+ 0x2e110a62, 0x776c4edb, 0x2de2211e, 0x777e5cc3, 0x2db330c7, 0x7790583e,
+ 0x2d843964, 0x77a24148,
+ 0x2d553afc, 0x77b417df, 0x2d263596, 0x77c5dc01, 0x2cf72939, 0x77d78daa,
+ 0x2cc815ee, 0x77e92cd9,
+ 0x2c98fbba, 0x77fab989, 0x2c69daa6, 0x780c33b8, 0x2c3ab2b9, 0x781d9b65,
+ 0x2c0b83fa, 0x782ef08b,
+ 0x2bdc4e6f, 0x78403329, 0x2bad1221, 0x7851633b, 0x2b7dcf17, 0x786280bf,
+ 0x2b4e8558, 0x78738bb3,
+ 0x2b1f34eb, 0x78848414, 0x2aefddd8, 0x789569df, 0x2ac08026, 0x78a63d11,
+ 0x2a911bdc, 0x78b6fda8,
+ 0x2a61b101, 0x78c7aba2, 0x2a323f9e, 0x78d846fb, 0x2a02c7b8, 0x78e8cfb2,
+ 0x29d34958, 0x78f945c3,
+ 0x29a3c485, 0x7909a92d, 0x29743946, 0x7919f9ec, 0x2944a7a2, 0x792a37fe,
+ 0x29150fa1, 0x793a6361,
+ 0x28e5714b, 0x794a7c12, 0x28b5cca5, 0x795a820e, 0x288621b9, 0x796a7554,
+ 0x2856708d, 0x797a55e0,
+ 0x2826b928, 0x798a23b1, 0x27f6fb92, 0x7999dec4, 0x27c737d3, 0x79a98715,
+ 0x27976df1, 0x79b91ca4,
+ 0x27679df4, 0x79c89f6e, 0x2737c7e3, 0x79d80f6f, 0x2707ebc7, 0x79e76ca7,
+ 0x26d809a5, 0x79f6b711,
+ 0x26a82186, 0x7a05eead, 0x26783370, 0x7a151378, 0x26483f6c, 0x7a24256f,
+ 0x26184581, 0x7a332490,
+ 0x25e845b6, 0x7a4210d8, 0x25b84012, 0x7a50ea47, 0x2588349d, 0x7a5fb0d8,
+ 0x2558235f, 0x7a6e648a,
+ 0x25280c5e, 0x7a7d055b, 0x24f7efa2, 0x7a8b9348, 0x24c7cd33, 0x7a9a0e50,
+ 0x2497a517, 0x7aa8766f,
+ 0x24677758, 0x7ab6cba4, 0x243743fa, 0x7ac50dec, 0x24070b08, 0x7ad33d45,
+ 0x23d6cc87, 0x7ae159ae,
+ 0x23a6887f, 0x7aef6323, 0x23763ef7, 0x7afd59a4, 0x2345eff8, 0x7b0b3d2c,
+ 0x23159b88, 0x7b190dbc,
+ 0x22e541af, 0x7b26cb4f, 0x22b4e274, 0x7b3475e5, 0x22847de0, 0x7b420d7a,
+ 0x225413f8, 0x7b4f920e,
+ 0x2223a4c5, 0x7b5d039e, 0x21f3304f, 0x7b6a6227, 0x21c2b69c, 0x7b77ada8,
+ 0x219237b5, 0x7b84e61f,
+ 0x2161b3a0, 0x7b920b89, 0x21312a65, 0x7b9f1de6, 0x21009c0c, 0x7bac1d31,
+ 0x20d0089c, 0x7bb9096b,
+ 0x209f701c, 0x7bc5e290, 0x206ed295, 0x7bd2a89e, 0x203e300d, 0x7bdf5b94,
+ 0x200d888d, 0x7bebfb70,
+ 0x1fdcdc1b, 0x7bf88830, 0x1fac2abf, 0x7c0501d2, 0x1f7b7481, 0x7c116853,
+ 0x1f4ab968, 0x7c1dbbb3,
+ 0x1f19f97b, 0x7c29fbee, 0x1ee934c3, 0x7c362904, 0x1eb86b46, 0x7c4242f2,
+ 0x1e879d0d, 0x7c4e49b7,
+ 0x1e56ca1e, 0x7c5a3d50, 0x1e25f282, 0x7c661dbc, 0x1df5163f, 0x7c71eaf9,
+ 0x1dc4355e, 0x7c7da505,
+ 0x1d934fe5, 0x7c894bde, 0x1d6265dd, 0x7c94df83, 0x1d31774d, 0x7ca05ff1,
+ 0x1d00843d, 0x7cabcd28,
+ 0x1ccf8cb3, 0x7cb72724, 0x1c9e90b8, 0x7cc26de5, 0x1c6d9053, 0x7ccda169,
+ 0x1c3c8b8c, 0x7cd8c1ae,
+ 0x1c0b826a, 0x7ce3ceb2, 0x1bda74f6, 0x7ceec873, 0x1ba96335, 0x7cf9aef0,
+ 0x1b784d30, 0x7d048228,
+ 0x1b4732ef, 0x7d0f4218, 0x1b161479, 0x7d19eebf, 0x1ae4f1d6, 0x7d24881b,
+ 0x1ab3cb0d, 0x7d2f0e2b,
+ 0x1a82a026, 0x7d3980ec, 0x1a517128, 0x7d43e05e, 0x1a203e1b, 0x7d4e2c7f,
+ 0x19ef0707, 0x7d58654d,
+ 0x19bdcbf3, 0x7d628ac6, 0x198c8ce7, 0x7d6c9ce9, 0x195b49ea, 0x7d769bb5,
+ 0x192a0304, 0x7d808728,
+ 0x18f8b83c, 0x7d8a5f40, 0x18c7699b, 0x7d9423fc, 0x18961728, 0x7d9dd55a,
+ 0x1864c0ea, 0x7da77359,
+ 0x183366e9, 0x7db0fdf8, 0x1802092c, 0x7dba7534, 0x17d0a7bc, 0x7dc3d90d,
+ 0x179f429f, 0x7dcd2981,
+ 0x176dd9de, 0x7dd6668f, 0x173c6d80, 0x7ddf9034, 0x170afd8d, 0x7de8a670,
+ 0x16d98a0c, 0x7df1a942,
+ 0x16a81305, 0x7dfa98a8, 0x1676987f, 0x7e0374a0, 0x16451a83, 0x7e0c3d29,
+ 0x16139918, 0x7e14f242,
+ 0x15e21445, 0x7e1d93ea, 0x15b08c12, 0x7e26221f, 0x157f0086, 0x7e2e9cdf,
+ 0x154d71aa, 0x7e37042a,
+ 0x151bdf86, 0x7e3f57ff, 0x14ea4a1f, 0x7e47985b, 0x14b8b17f, 0x7e4fc53e,
+ 0x148715ae, 0x7e57dea7,
+ 0x145576b1, 0x7e5fe493, 0x1423d492, 0x7e67d703, 0x13f22f58, 0x7e6fb5f4,
+ 0x13c0870a, 0x7e778166,
+ 0x138edbb1, 0x7e7f3957, 0x135d2d53, 0x7e86ddc6, 0x132b7bf9, 0x7e8e6eb2,
+ 0x12f9c7aa, 0x7e95ec1a,
+ 0x12c8106f, 0x7e9d55fc, 0x1296564d, 0x7ea4ac58, 0x1264994e, 0x7eabef2c,
+ 0x1232d979, 0x7eb31e78,
+ 0x120116d5, 0x7eba3a39, 0x11cf516a, 0x7ec14270, 0x119d8941, 0x7ec8371a,
+ 0x116bbe60, 0x7ecf1837,
+ 0x1139f0cf, 0x7ed5e5c6, 0x11082096, 0x7edc9fc6, 0x10d64dbd, 0x7ee34636,
+ 0x10a4784b, 0x7ee9d914,
+ 0x1072a048, 0x7ef05860, 0x1040c5bb, 0x7ef6c418, 0x100ee8ad, 0x7efd1c3c,
+ 0xfdd0926, 0x7f0360cb,
+ 0xfab272b, 0x7f0991c4, 0xf7942c7, 0x7f0faf25, 0xf475bff, 0x7f15b8ee,
+ 0xf1572dc, 0x7f1baf1e,
+ 0xee38766, 0x7f2191b4, 0xeb199a4, 0x7f2760af, 0xe7fa99e, 0x7f2d1c0e,
+ 0xe4db75b, 0x7f32c3d1,
+ 0xe1bc2e4, 0x7f3857f6, 0xde9cc40, 0x7f3dd87c, 0xdb7d376, 0x7f434563,
+ 0xd85d88f, 0x7f489eaa,
+ 0xd53db92, 0x7f4de451, 0xd21dc87, 0x7f531655, 0xcefdb76, 0x7f5834b7,
+ 0xcbdd865, 0x7f5d3f75,
+ 0xc8bd35e, 0x7f62368f, 0xc59cc68, 0x7f671a05, 0xc27c389, 0x7f6be9d4,
+ 0xbf5b8cb, 0x7f70a5fe,
+ 0xbc3ac35, 0x7f754e80, 0xb919dcf, 0x7f79e35a, 0xb5f8d9f, 0x7f7e648c,
+ 0xb2d7baf, 0x7f82d214,
+ 0xafb6805, 0x7f872bf3, 0xac952aa, 0x7f8b7227, 0xa973ba5, 0x7f8fa4b0,
+ 0xa6522fe, 0x7f93c38c,
+ 0xa3308bd, 0x7f97cebd, 0xa00ece8, 0x7f9bc640, 0x9cecf89, 0x7f9faa15,
+ 0x99cb0a7, 0x7fa37a3c,
+ 0x96a9049, 0x7fa736b4, 0x9386e78, 0x7faadf7c, 0x9064b3a, 0x7fae7495,
+ 0x8d42699, 0x7fb1f5fc,
+ 0x8a2009a, 0x7fb563b3, 0x86fd947, 0x7fb8bdb8, 0x83db0a7, 0x7fbc040a,
+ 0x80b86c2, 0x7fbf36aa,
+ 0x7d95b9e, 0x7fc25596, 0x7a72f45, 0x7fc560cf, 0x77501be, 0x7fc85854,
+ 0x742d311, 0x7fcb3c23,
+ 0x710a345, 0x7fce0c3e, 0x6de7262, 0x7fd0c8a3, 0x6ac406f, 0x7fd37153,
+ 0x67a0d76, 0x7fd6064c,
+ 0x647d97c, 0x7fd8878e, 0x615a48b, 0x7fdaf519, 0x5e36ea9, 0x7fdd4eec,
+ 0x5b137df, 0x7fdf9508,
+ 0x57f0035, 0x7fe1c76b, 0x54cc7b1, 0x7fe3e616, 0x51a8e5c, 0x7fe5f108,
+ 0x4e8543e, 0x7fe7e841,
+ 0x4b6195d, 0x7fe9cbc0, 0x483ddc3, 0x7feb9b85, 0x451a177, 0x7fed5791,
+ 0x41f6480, 0x7feeffe1,
+ 0x3ed26e6, 0x7ff09478, 0x3bae8b2, 0x7ff21553, 0x388a9ea, 0x7ff38274,
+ 0x3566a96, 0x7ff4dbd9,
+ 0x3242abf, 0x7ff62182, 0x2f1ea6c, 0x7ff75370, 0x2bfa9a4, 0x7ff871a2,
+ 0x28d6870, 0x7ff97c18,
+ 0x25b26d7, 0x7ffa72d1, 0x228e4e2, 0x7ffb55ce, 0x1f6a297, 0x7ffc250f,
+ 0x1c45ffe, 0x7ffce093,
+ 0x1921d20, 0x7ffd885a, 0x15fda03, 0x7ffe1c65, 0x12d96b1, 0x7ffe9cb2,
+ 0xfb5330, 0x7fff0943,
+ 0xc90f88, 0x7fff6216, 0x96cbc1, 0x7fffa72c, 0x6487e3, 0x7fffd886, 0x3243f5,
+ 0x7ffff621,
+ 0x0, 0x7fffffff, 0xffcdbc0b, 0x7ffff621, 0xff9b781d, 0x7fffd886, 0xff69343f,
+ 0x7fffa72c,
+ 0xff36f078, 0x7fff6216, 0xff04acd0, 0x7fff0943, 0xfed2694f, 0x7ffe9cb2,
+ 0xfea025fd, 0x7ffe1c65,
+ 0xfe6de2e0, 0x7ffd885a, 0xfe3ba002, 0x7ffce093, 0xfe095d69, 0x7ffc250f,
+ 0xfdd71b1e, 0x7ffb55ce,
+ 0xfda4d929, 0x7ffa72d1, 0xfd729790, 0x7ff97c18, 0xfd40565c, 0x7ff871a2,
+ 0xfd0e1594, 0x7ff75370,
+ 0xfcdbd541, 0x7ff62182, 0xfca9956a, 0x7ff4dbd9, 0xfc775616, 0x7ff38274,
+ 0xfc45174e, 0x7ff21553,
+ 0xfc12d91a, 0x7ff09478, 0xfbe09b80, 0x7feeffe1, 0xfbae5e89, 0x7fed5791,
+ 0xfb7c223d, 0x7feb9b85,
+ 0xfb49e6a3, 0x7fe9cbc0, 0xfb17abc2, 0x7fe7e841, 0xfae571a4, 0x7fe5f108,
+ 0xfab3384f, 0x7fe3e616,
+ 0xfa80ffcb, 0x7fe1c76b, 0xfa4ec821, 0x7fdf9508, 0xfa1c9157, 0x7fdd4eec,
+ 0xf9ea5b75, 0x7fdaf519,
+ 0xf9b82684, 0x7fd8878e, 0xf985f28a, 0x7fd6064c, 0xf953bf91, 0x7fd37153,
+ 0xf9218d9e, 0x7fd0c8a3,
+ 0xf8ef5cbb, 0x7fce0c3e, 0xf8bd2cef, 0x7fcb3c23, 0xf88afe42, 0x7fc85854,
+ 0xf858d0bb, 0x7fc560cf,
+ 0xf826a462, 0x7fc25596, 0xf7f4793e, 0x7fbf36aa, 0xf7c24f59, 0x7fbc040a,
+ 0xf79026b9, 0x7fb8bdb8,
+ 0xf75dff66, 0x7fb563b3, 0xf72bd967, 0x7fb1f5fc, 0xf6f9b4c6, 0x7fae7495,
+ 0xf6c79188, 0x7faadf7c,
+ 0xf6956fb7, 0x7fa736b4, 0xf6634f59, 0x7fa37a3c, 0xf6313077, 0x7f9faa15,
+ 0xf5ff1318, 0x7f9bc640,
+ 0xf5ccf743, 0x7f97cebd, 0xf59add02, 0x7f93c38c, 0xf568c45b, 0x7f8fa4b0,
+ 0xf536ad56, 0x7f8b7227,
+ 0xf50497fb, 0x7f872bf3, 0xf4d28451, 0x7f82d214, 0xf4a07261, 0x7f7e648c,
+ 0xf46e6231, 0x7f79e35a,
+ 0xf43c53cb, 0x7f754e80, 0xf40a4735, 0x7f70a5fe, 0xf3d83c77, 0x7f6be9d4,
+ 0xf3a63398, 0x7f671a05,
+ 0xf3742ca2, 0x7f62368f, 0xf342279b, 0x7f5d3f75, 0xf310248a, 0x7f5834b7,
+ 0xf2de2379, 0x7f531655,
+ 0xf2ac246e, 0x7f4de451, 0xf27a2771, 0x7f489eaa, 0xf2482c8a, 0x7f434563,
+ 0xf21633c0, 0x7f3dd87c,
+ 0xf1e43d1c, 0x7f3857f6, 0xf1b248a5, 0x7f32c3d1, 0xf1805662, 0x7f2d1c0e,
+ 0xf14e665c, 0x7f2760af,
+ 0xf11c789a, 0x7f2191b4, 0xf0ea8d24, 0x7f1baf1e, 0xf0b8a401, 0x7f15b8ee,
+ 0xf086bd39, 0x7f0faf25,
+ 0xf054d8d5, 0x7f0991c4, 0xf022f6da, 0x7f0360cb, 0xeff11753, 0x7efd1c3c,
+ 0xefbf3a45, 0x7ef6c418,
+ 0xef8d5fb8, 0x7ef05860, 0xef5b87b5, 0x7ee9d914, 0xef29b243, 0x7ee34636,
+ 0xeef7df6a, 0x7edc9fc6,
+ 0xeec60f31, 0x7ed5e5c6, 0xee9441a0, 0x7ecf1837, 0xee6276bf, 0x7ec8371a,
+ 0xee30ae96, 0x7ec14270,
+ 0xedfee92b, 0x7eba3a39, 0xedcd2687, 0x7eb31e78, 0xed9b66b2, 0x7eabef2c,
+ 0xed69a9b3, 0x7ea4ac58,
+ 0xed37ef91, 0x7e9d55fc, 0xed063856, 0x7e95ec1a, 0xecd48407, 0x7e8e6eb2,
+ 0xeca2d2ad, 0x7e86ddc6,
+ 0xec71244f, 0x7e7f3957, 0xec3f78f6, 0x7e778166, 0xec0dd0a8, 0x7e6fb5f4,
+ 0xebdc2b6e, 0x7e67d703,
+ 0xebaa894f, 0x7e5fe493, 0xeb78ea52, 0x7e57dea7, 0xeb474e81, 0x7e4fc53e,
+ 0xeb15b5e1, 0x7e47985b,
+ 0xeae4207a, 0x7e3f57ff, 0xeab28e56, 0x7e37042a, 0xea80ff7a, 0x7e2e9cdf,
+ 0xea4f73ee, 0x7e26221f,
+ 0xea1debbb, 0x7e1d93ea, 0xe9ec66e8, 0x7e14f242, 0xe9bae57d, 0x7e0c3d29,
+ 0xe9896781, 0x7e0374a0,
+ 0xe957ecfb, 0x7dfa98a8, 0xe92675f4, 0x7df1a942, 0xe8f50273, 0x7de8a670,
+ 0xe8c39280, 0x7ddf9034,
+ 0xe8922622, 0x7dd6668f, 0xe860bd61, 0x7dcd2981, 0xe82f5844, 0x7dc3d90d,
+ 0xe7fdf6d4, 0x7dba7534,
+ 0xe7cc9917, 0x7db0fdf8, 0xe79b3f16, 0x7da77359, 0xe769e8d8, 0x7d9dd55a,
+ 0xe7389665, 0x7d9423fc,
+ 0xe70747c4, 0x7d8a5f40, 0xe6d5fcfc, 0x7d808728, 0xe6a4b616, 0x7d769bb5,
+ 0xe6737319, 0x7d6c9ce9,
+ 0xe642340d, 0x7d628ac6, 0xe610f8f9, 0x7d58654d, 0xe5dfc1e5, 0x7d4e2c7f,
+ 0xe5ae8ed8, 0x7d43e05e,
+ 0xe57d5fda, 0x7d3980ec, 0xe54c34f3, 0x7d2f0e2b, 0xe51b0e2a, 0x7d24881b,
+ 0xe4e9eb87, 0x7d19eebf,
+ 0xe4b8cd11, 0x7d0f4218, 0xe487b2d0, 0x7d048228, 0xe4569ccb, 0x7cf9aef0,
+ 0xe4258b0a, 0x7ceec873,
+ 0xe3f47d96, 0x7ce3ceb2, 0xe3c37474, 0x7cd8c1ae, 0xe3926fad, 0x7ccda169,
+ 0xe3616f48, 0x7cc26de5,
+ 0xe330734d, 0x7cb72724, 0xe2ff7bc3, 0x7cabcd28, 0xe2ce88b3, 0x7ca05ff1,
+ 0xe29d9a23, 0x7c94df83,
+ 0xe26cb01b, 0x7c894bde, 0xe23bcaa2, 0x7c7da505, 0xe20ae9c1, 0x7c71eaf9,
+ 0xe1da0d7e, 0x7c661dbc,
+ 0xe1a935e2, 0x7c5a3d50, 0xe17862f3, 0x7c4e49b7, 0xe14794ba, 0x7c4242f2,
+ 0xe116cb3d, 0x7c362904,
+ 0xe0e60685, 0x7c29fbee, 0xe0b54698, 0x7c1dbbb3, 0xe0848b7f, 0x7c116853,
+ 0xe053d541, 0x7c0501d2,
+ 0xe02323e5, 0x7bf88830, 0xdff27773, 0x7bebfb70, 0xdfc1cff3, 0x7bdf5b94,
+ 0xdf912d6b, 0x7bd2a89e,
+ 0xdf608fe4, 0x7bc5e290, 0xdf2ff764, 0x7bb9096b, 0xdeff63f4, 0x7bac1d31,
+ 0xdeced59b, 0x7b9f1de6,
+ 0xde9e4c60, 0x7b920b89, 0xde6dc84b, 0x7b84e61f, 0xde3d4964, 0x7b77ada8,
+ 0xde0ccfb1, 0x7b6a6227,
+ 0xdddc5b3b, 0x7b5d039e, 0xddabec08, 0x7b4f920e, 0xdd7b8220, 0x7b420d7a,
+ 0xdd4b1d8c, 0x7b3475e5,
+ 0xdd1abe51, 0x7b26cb4f, 0xdcea6478, 0x7b190dbc, 0xdcba1008, 0x7b0b3d2c,
+ 0xdc89c109, 0x7afd59a4,
+ 0xdc597781, 0x7aef6323, 0xdc293379, 0x7ae159ae, 0xdbf8f4f8, 0x7ad33d45,
+ 0xdbc8bc06, 0x7ac50dec,
+ 0xdb9888a8, 0x7ab6cba4, 0xdb685ae9, 0x7aa8766f, 0xdb3832cd, 0x7a9a0e50,
+ 0xdb08105e, 0x7a8b9348,
+ 0xdad7f3a2, 0x7a7d055b, 0xdaa7dca1, 0x7a6e648a, 0xda77cb63, 0x7a5fb0d8,
+ 0xda47bfee, 0x7a50ea47,
+ 0xda17ba4a, 0x7a4210d8, 0xd9e7ba7f, 0x7a332490, 0xd9b7c094, 0x7a24256f,
+ 0xd987cc90, 0x7a151378,
+ 0xd957de7a, 0x7a05eead, 0xd927f65b, 0x79f6b711, 0xd8f81439, 0x79e76ca7,
+ 0xd8c8381d, 0x79d80f6f,
+ 0xd898620c, 0x79c89f6e, 0xd868920f, 0x79b91ca4, 0xd838c82d, 0x79a98715,
+ 0xd809046e, 0x7999dec4,
+ 0xd7d946d8, 0x798a23b1, 0xd7a98f73, 0x797a55e0, 0xd779de47, 0x796a7554,
+ 0xd74a335b, 0x795a820e,
+ 0xd71a8eb5, 0x794a7c12, 0xd6eaf05f, 0x793a6361, 0xd6bb585e, 0x792a37fe,
+ 0xd68bc6ba, 0x7919f9ec,
+ 0xd65c3b7b, 0x7909a92d, 0xd62cb6a8, 0x78f945c3, 0xd5fd3848, 0x78e8cfb2,
+ 0xd5cdc062, 0x78d846fb,
+ 0xd59e4eff, 0x78c7aba2, 0xd56ee424, 0x78b6fda8, 0xd53f7fda, 0x78a63d11,
+ 0xd5102228, 0x789569df,
+ 0xd4e0cb15, 0x78848414, 0xd4b17aa8, 0x78738bb3, 0xd48230e9, 0x786280bf,
+ 0xd452eddf, 0x7851633b,
+ 0xd423b191, 0x78403329, 0xd3f47c06, 0x782ef08b, 0xd3c54d47, 0x781d9b65,
+ 0xd396255a, 0x780c33b8,
+ 0xd3670446, 0x77fab989, 0xd337ea12, 0x77e92cd9, 0xd308d6c7, 0x77d78daa,
+ 0xd2d9ca6a, 0x77c5dc01,
+ 0xd2aac504, 0x77b417df, 0xd27bc69c, 0x77a24148, 0xd24ccf39, 0x7790583e,
+ 0xd21ddee2, 0x777e5cc3,
+ 0xd1eef59e, 0x776c4edb, 0xd1c01375, 0x775a2e89, 0xd191386e, 0x7747fbce,
+ 0xd1626490, 0x7735b6af,
+ 0xd13397e2, 0x77235f2d, 0xd104d26b, 0x7710f54c, 0xd0d61434, 0x76fe790e,
+ 0xd0a75d42, 0x76ebea77,
+ 0xd078ad9e, 0x76d94989, 0xd04a054e, 0x76c69647, 0xd01b6459, 0x76b3d0b4,
+ 0xcfeccac7, 0x76a0f8d2,
+ 0xcfbe389f, 0x768e0ea6, 0xcf8fade9, 0x767b1231, 0xcf612aaa, 0x76680376,
+ 0xcf32aeeb, 0x7654e279,
+ 0xcf043ab3, 0x7641af3d, 0xced5ce08, 0x762e69c4, 0xcea768f2, 0x761b1211,
+ 0xce790b79, 0x7607a828,
+ 0xce4ab5a2, 0x75f42c0b, 0xce1c6777, 0x75e09dbd, 0xcdee20fc, 0x75ccfd42,
+ 0xcdbfe23a, 0x75b94a9c,
+ 0xcd91ab39, 0x75a585cf, 0xcd637bfe, 0x7591aedd, 0xcd355491, 0x757dc5ca,
+ 0xcd0734f9, 0x7569ca99,
+ 0xccd91d3d, 0x7555bd4c, 0xccab0d65, 0x75419de7, 0xcc7d0578, 0x752d6c6c,
+ 0xcc4f057c, 0x751928e0,
+ 0xcc210d79, 0x7504d345, 0xcbf31d75, 0x74f06b9e, 0xcbc53579, 0x74dbf1ef,
+ 0xcb97558a, 0x74c7663a,
+ 0xcb697db0, 0x74b2c884, 0xcb3badf3, 0x749e18cd, 0xcb0de658, 0x7489571c,
+ 0xcae026e8, 0x74748371,
+ 0xcab26fa9, 0x745f9dd1, 0xca84c0a3, 0x744aa63f, 0xca5719db, 0x74359cbd,
+ 0xca297b5a, 0x74208150,
+ 0xc9fbe527, 0x740b53fb, 0xc9ce5748, 0x73f614c0, 0xc9a0d1c5, 0x73e0c3a3,
+ 0xc97354a4, 0x73cb60a8,
+ 0xc945dfec, 0x73b5ebd1, 0xc91873a5, 0x73a06522, 0xc8eb0fd6, 0x738acc9e,
+ 0xc8bdb485, 0x73752249,
+ 0xc89061ba, 0x735f6626, 0xc863177b, 0x73499838, 0xc835d5d0, 0x7333b883,
+ 0xc8089cbf, 0x731dc70a,
+ 0xc7db6c50, 0x7307c3d0, 0xc7ae4489, 0x72f1aed9, 0xc7812572, 0x72db8828,
+ 0xc7540f11, 0x72c54fc1,
+ 0xc727016d, 0x72af05a7, 0xc6f9fc8d, 0x7298a9dd, 0xc6cd0079, 0x72823c67,
+ 0xc6a00d37, 0x726bbd48,
+ 0xc67322ce, 0x72552c85, 0xc6464144, 0x723e8a20, 0xc61968a2, 0x7227d61c,
+ 0xc5ec98ee, 0x7211107e,
+ 0xc5bfd22e, 0x71fa3949, 0xc593146a, 0x71e35080, 0xc5665fa9, 0x71cc5626,
+ 0xc539b3f1, 0x71b54a41,
+ 0xc50d1149, 0x719e2cd2, 0xc4e077b8, 0x7186fdde, 0xc4b3e746, 0x716fbd68,
+ 0xc4875ff9, 0x71586b74,
+ 0xc45ae1d7, 0x71410805, 0xc42e6ce8, 0x7129931f, 0xc4020133, 0x71120cc5,
+ 0xc3d59ebe, 0x70fa74fc,
+ 0xc3a94590, 0x70e2cbc6, 0xc37cf5b0, 0x70cb1128, 0xc350af26, 0x70b34525,
+ 0xc32471f7, 0x709b67c0,
+ 0xc2f83e2a, 0x708378ff, 0xc2cc13c7, 0x706b78e3, 0xc29ff2d4, 0x70536771,
+ 0xc273db58, 0x703b44ad,
+ 0xc247cd5a, 0x7023109a, 0xc21bc8e1, 0x700acb3c, 0xc1efcdf3, 0x6ff27497,
+ 0xc1c3dc97, 0x6fda0cae,
+ 0xc197f4d4, 0x6fc19385, 0xc16c16b0, 0x6fa90921, 0xc1404233, 0x6f906d84,
+ 0xc1147764, 0x6f77c0b3,
+ 0xc0e8b648, 0x6f5f02b2, 0xc0bcfee7, 0x6f463383, 0xc0915148, 0x6f2d532c,
+ 0xc065ad70, 0x6f1461b0,
+ 0xc03a1368, 0x6efb5f12, 0xc00e8336, 0x6ee24b57, 0xbfe2fcdf, 0x6ec92683,
+ 0xbfb7806c, 0x6eaff099,
+ 0xbf8c0de3, 0x6e96a99d, 0xbf60a54a, 0x6e7d5193, 0xbf3546a8, 0x6e63e87f,
+ 0xbf09f205, 0x6e4a6e66,
+ 0xbedea765, 0x6e30e34a, 0xbeb366d1, 0x6e174730, 0xbe88304f, 0x6dfd9a1c,
+ 0xbe5d03e6, 0x6de3dc11,
+ 0xbe31e19b, 0x6dca0d14, 0xbe06c977, 0x6db02d29, 0xbddbbb7f, 0x6d963c54,
+ 0xbdb0b7bb, 0x6d7c3a98,
+ 0xbd85be30, 0x6d6227fa, 0xbd5acee5, 0x6d48047e, 0xbd2fe9e2, 0x6d2dd027,
+ 0xbd050f2c, 0x6d138afb,
+ 0xbcda3ecb, 0x6cf934fc, 0xbcaf78c4, 0x6cdece2f, 0xbc84bd1f, 0x6cc45698,
+ 0xbc5a0be2, 0x6ca9ce3b,
+ 0xbc2f6513, 0x6c8f351c, 0xbc04c8ba, 0x6c748b3f, 0xbbda36dd, 0x6c59d0a9,
+ 0xbbafaf82, 0x6c3f055d,
+ 0xbb8532b0, 0x6c242960, 0xbb5ac06d, 0x6c093cb6, 0xbb3058c0, 0x6bee3f62,
+ 0xbb05fbb0, 0x6bd3316a,
+ 0xbadba943, 0x6bb812d1, 0xbab16180, 0x6b9ce39b, 0xba87246d, 0x6b81a3cd,
+ 0xba5cf210, 0x6b66536b,
+ 0xba32ca71, 0x6b4af279, 0xba08ad95, 0x6b2f80fb, 0xb9de9b83, 0x6b13fef5,
+ 0xb9b49442, 0x6af86c6c,
+ 0xb98a97d8, 0x6adcc964, 0xb960a64c, 0x6ac115e2, 0xb936bfa4, 0x6aa551e9,
+ 0xb90ce3e6, 0x6a897d7d,
+ 0xb8e31319, 0x6a6d98a4, 0xb8b94d44, 0x6a51a361, 0xb88f926d, 0x6a359db9,
+ 0xb865e299, 0x6a1987b0,
+ 0xb83c3dd1, 0x69fd614a, 0xb812a41a, 0x69e12a8c, 0xb7e9157a, 0x69c4e37a,
+ 0xb7bf91f8, 0x69a88c19,
+ 0xb796199b, 0x698c246c, 0xb76cac69, 0x696fac78, 0xb7434a67, 0x69532442,
+ 0xb719f39e, 0x69368bce,
+ 0xb6f0a812, 0x6919e320, 0xb6c767ca, 0x68fd2a3d, 0xb69e32cd, 0x68e06129,
+ 0xb6750921, 0x68c387e9,
+ 0xb64beacd, 0x68a69e81, 0xb622d7d6, 0x6889a4f6, 0xb5f9d043, 0x686c9b4b,
+ 0xb5d0d41a, 0x684f8186,
+ 0xb5a7e362, 0x683257ab, 0xb57efe22, 0x68151dbe, 0xb556245e, 0x67f7d3c5,
+ 0xb52d561e, 0x67da79c3,
+ 0xb5049368, 0x67bd0fbd, 0xb4dbdc42, 0x679f95b7, 0xb4b330b3, 0x67820bb7,
+ 0xb48a90c0, 0x676471c0,
+ 0xb461fc70, 0x6746c7d8, 0xb43973ca, 0x67290e02, 0xb410f6d3, 0x670b4444,
+ 0xb3e88592, 0x66ed6aa1,
+ 0xb3c0200c, 0x66cf8120, 0xb397c649, 0x66b187c3, 0xb36f784f, 0x66937e91,
+ 0xb3473623, 0x6675658c,
+ 0xb31effcc, 0x66573cbb, 0xb2f6d550, 0x66390422, 0xb2ceb6b5, 0x661abbc5,
+ 0xb2a6a402, 0x65fc63a9,
+ 0xb27e9d3c, 0x65ddfbd3, 0xb256a26a, 0x65bf8447, 0xb22eb392, 0x65a0fd0b,
+ 0xb206d0ba, 0x65826622,
+ 0xb1def9e9, 0x6563bf92, 0xb1b72f23, 0x6545095f, 0xb18f7071, 0x6526438f,
+ 0xb167bdd7, 0x65076e25,
+ 0xb140175b, 0x64e88926, 0xb1187d05, 0x64c99498, 0xb0f0eeda, 0x64aa907f,
+ 0xb0c96ce0, 0x648b7ce0,
+ 0xb0a1f71d, 0x646c59bf, 0xb07a8d97, 0x644d2722, 0xb0533055, 0x642de50d,
+ 0xb02bdf5c, 0x640e9386,
+ 0xb0049ab3, 0x63ef3290, 0xafdd625f, 0x63cfc231, 0xafb63667, 0x63b0426d,
+ 0xaf8f16d1, 0x6390b34a,
+ 0xaf6803a2, 0x637114cc, 0xaf40fce1, 0x635166f9, 0xaf1a0293, 0x6331a9d4,
+ 0xaef314c0, 0x6311dd64,
+ 0xaecc336c, 0x62f201ac, 0xaea55e9e, 0x62d216b3, 0xae7e965b, 0x62b21c7b,
+ 0xae57daab, 0x6292130c,
+ 0xae312b92, 0x6271fa69, 0xae0a8916, 0x6251d298, 0xade3f33e, 0x62319b9d,
+ 0xadbd6a10, 0x6211557e,
+ 0xad96ed92, 0x61f1003f, 0xad707dc8, 0x61d09be5, 0xad4a1aba, 0x61b02876,
+ 0xad23c46e, 0x618fa5f7,
+ 0xacfd7ae8, 0x616f146c, 0xacd73e30, 0x614e73da, 0xacb10e4b, 0x612dc447,
+ 0xac8aeb3e, 0x610d05b7,
+ 0xac64d510, 0x60ec3830, 0xac3ecbc7, 0x60cb5bb7, 0xac18cf69, 0x60aa7050,
+ 0xabf2dffb, 0x60897601,
+ 0xabccfd83, 0x60686ccf, 0xaba72807, 0x604754bf, 0xab815f8d, 0x60262dd6,
+ 0xab5ba41a, 0x6004f819,
+ 0xab35f5b5, 0x5fe3b38d, 0xab105464, 0x5fc26038, 0xaaeac02c, 0x5fa0fe1f,
+ 0xaac53912, 0x5f7f8d46,
+ 0xaa9fbf1e, 0x5f5e0db3, 0xaa7a5253, 0x5f3c7f6b, 0xaa54f2ba, 0x5f1ae274,
+ 0xaa2fa056, 0x5ef936d1,
+ 0xaa0a5b2e, 0x5ed77c8a, 0xa9e52347, 0x5eb5b3a2, 0xa9bff8a8, 0x5e93dc1f,
+ 0xa99adb56, 0x5e71f606,
+ 0xa975cb57, 0x5e50015d, 0xa950c8b0, 0x5e2dfe29, 0xa92bd367, 0x5e0bec6e,
+ 0xa906eb82, 0x5de9cc33,
+ 0xa8e21106, 0x5dc79d7c, 0xa8bd43fa, 0x5da5604f, 0xa8988463, 0x5d8314b1,
+ 0xa873d246, 0x5d60baa7,
+ 0xa84f2daa, 0x5d3e5237, 0xa82a9693, 0x5d1bdb65, 0xa8060d08, 0x5cf95638,
+ 0xa7e1910f, 0x5cd6c2b5,
+ 0xa7bd22ac, 0x5cb420e0, 0xa798c1e5, 0x5c9170bf, 0xa7746ec0, 0x5c6eb258,
+ 0xa7502943, 0x5c4be5b0,
+ 0xa72bf174, 0x5c290acc, 0xa707c757, 0x5c0621b2, 0xa6e3aaf2, 0x5be32a67,
+ 0xa6bf9c4b, 0x5bc024f0,
+ 0xa69b9b68, 0x5b9d1154, 0xa677a84e, 0x5b79ef96, 0xa653c303, 0x5b56bfbd,
+ 0xa62feb8b, 0x5b3381ce,
+ 0xa60c21ee, 0x5b1035cf, 0xa5e8662f, 0x5aecdbc5, 0xa5c4b855, 0x5ac973b5,
+ 0xa5a11866, 0x5aa5fda5,
+ 0xa57d8666, 0x5a82799a, 0xa55a025b, 0x5a5ee79a, 0xa5368c4b, 0x5a3b47ab,
+ 0xa513243b, 0x5a1799d1,
+ 0xa4efca31, 0x59f3de12, 0xa4cc7e32, 0x59d01475, 0xa4a94043, 0x59ac3cfd,
+ 0xa486106a, 0x598857b2,
+ 0xa462eeac, 0x59646498, 0xa43fdb10, 0x594063b5, 0xa41cd599, 0x591c550e,
+ 0xa3f9de4e, 0x58f838a9,
+ 0xa3d6f534, 0x58d40e8c, 0xa3b41a50, 0x58afd6bd, 0xa3914da8, 0x588b9140,
+ 0xa36e8f41, 0x58673e1b,
+ 0xa34bdf20, 0x5842dd54, 0xa3293d4b, 0x581e6ef1, 0xa306a9c8, 0x57f9f2f8,
+ 0xa2e4249b, 0x57d5696d,
+ 0xa2c1adc9, 0x57b0d256, 0xa29f4559, 0x578c2dba, 0xa27ceb4f, 0x57677b9d,
+ 0xa25a9fb1, 0x5742bc06,
+ 0xa2386284, 0x571deefa, 0xa21633cd, 0x56f9147e, 0xa1f41392, 0x56d42c99,
+ 0xa1d201d7, 0x56af3750,
+ 0xa1affea3, 0x568a34a9, 0xa18e09fa, 0x566524aa, 0xa16c23e1, 0x56400758,
+ 0xa14a4c5e, 0x561adcb9,
+ 0xa1288376, 0x55f5a4d2, 0xa106c92f, 0x55d05faa, 0xa0e51d8c, 0x55ab0d46,
+ 0xa0c38095, 0x5585adad,
+ 0xa0a1f24d, 0x556040e2, 0xa08072ba, 0x553ac6ee, 0xa05f01e1, 0x55153fd4,
+ 0xa03d9fc8, 0x54efab9c,
+ 0xa01c4c73, 0x54ca0a4b, 0x9ffb07e7, 0x54a45be6, 0x9fd9d22a, 0x547ea073,
+ 0x9fb8ab41, 0x5458d7f9,
+ 0x9f979331, 0x5433027d, 0x9f7689ff, 0x540d2005, 0x9f558fb0, 0x53e73097,
+ 0x9f34a449, 0x53c13439,
+ 0x9f13c7d0, 0x539b2af0, 0x9ef2fa49, 0x537514c2, 0x9ed23bb9, 0x534ef1b5,
+ 0x9eb18c26, 0x5328c1d0,
+ 0x9e90eb94, 0x53028518, 0x9e705a09, 0x52dc3b92, 0x9e4fd78a, 0x52b5e546,
+ 0x9e2f641b, 0x528f8238,
+ 0x9e0effc1, 0x5269126e, 0x9deeaa82, 0x524295f0, 0x9dce6463, 0x521c0cc2,
+ 0x9dae2d68, 0x51f576ea,
+ 0x9d8e0597, 0x51ced46e, 0x9d6decf4, 0x51a82555, 0x9d4de385, 0x518169a5,
+ 0x9d2de94d, 0x515aa162,
+ 0x9d0dfe54, 0x5133cc94, 0x9cee229c, 0x510ceb40, 0x9cce562c, 0x50e5fd6d,
+ 0x9cae9907, 0x50bf031f,
+ 0x9c8eeb34, 0x5097fc5e, 0x9c6f4cb6, 0x5070e92f, 0x9c4fbd93, 0x5049c999,
+ 0x9c303dcf, 0x50229da1,
+ 0x9c10cd70, 0x4ffb654d, 0x9bf16c7a, 0x4fd420a4, 0x9bd21af3, 0x4faccfab,
+ 0x9bb2d8de, 0x4f857269,
+ 0x9b93a641, 0x4f5e08e3, 0x9b748320, 0x4f369320, 0x9b556f81, 0x4f0f1126,
+ 0x9b366b68, 0x4ee782fb,
+ 0x9b1776da, 0x4ebfe8a5, 0x9af891db, 0x4e984229, 0x9ad9bc71, 0x4e708f8f,
+ 0x9abaf6a1, 0x4e48d0dd,
+ 0x9a9c406e, 0x4e210617, 0x9a7d99de, 0x4df92f46, 0x9a5f02f5, 0x4dd14c6e,
+ 0x9a407bb9, 0x4da95d96,
+ 0x9a22042d, 0x4d8162c4, 0x9a039c57, 0x4d595bfe, 0x99e5443b, 0x4d31494b,
+ 0x99c6fbde, 0x4d092ab0,
+ 0x99a8c345, 0x4ce10034, 0x998a9a74, 0x4cb8c9dd, 0x996c816f, 0x4c9087b1,
+ 0x994e783d, 0x4c6839b7,
+ 0x99307ee0, 0x4c3fdff4, 0x9912955f, 0x4c177a6e, 0x98f4bbbc, 0x4bef092d,
+ 0x98d6f1fe, 0x4bc68c36,
+ 0x98b93828, 0x4b9e0390, 0x989b8e40, 0x4b756f40, 0x987df449, 0x4b4ccf4d,
+ 0x98606a49, 0x4b2423be,
+ 0x9842f043, 0x4afb6c98, 0x9825863d, 0x4ad2a9e2, 0x98082c3b, 0x4aa9dba2,
+ 0x97eae242, 0x4a8101de,
+ 0x97cda855, 0x4a581c9e, 0x97b07e7a, 0x4a2f2be6, 0x979364b5, 0x4a062fbd,
+ 0x97765b0a, 0x49dd282a,
+ 0x9759617f, 0x49b41533, 0x973c7817, 0x498af6df, 0x971f9ed7, 0x4961cd33,
+ 0x9702d5c3, 0x49389836,
+ 0x96e61ce0, 0x490f57ee, 0x96c97432, 0x48e60c62, 0x96acdbbe, 0x48bcb599,
+ 0x96905388, 0x48935397,
+ 0x9673db94, 0x4869e665, 0x965773e7, 0x48406e08, 0x963b1c86, 0x4816ea86,
+ 0x961ed574, 0x47ed5be6,
+ 0x96029eb6, 0x47c3c22f, 0x95e67850, 0x479a1d67, 0x95ca6247, 0x47706d93,
+ 0x95ae5c9f, 0x4746b2bc,
+ 0x9592675c, 0x471cece7, 0x95768283, 0x46f31c1a, 0x955aae17, 0x46c9405c,
+ 0x953eea1e, 0x469f59b4,
+ 0x9523369c, 0x46756828, 0x95079394, 0x464b6bbe, 0x94ec010b, 0x4621647d,
+ 0x94d07f05, 0x45f7526b,
+ 0x94b50d87, 0x45cd358f, 0x9499ac95, 0x45a30df0, 0x947e5c33, 0x4578db93,
+ 0x94631c65, 0x454e9e80,
+ 0x9447ed2f, 0x452456bd, 0x942cce96, 0x44fa0450, 0x9411c09e, 0x44cfa740,
+ 0x93f6c34a, 0x44a53f93,
+ 0x93dbd6a0, 0x447acd50, 0x93c0faa3, 0x4450507e, 0x93a62f57, 0x4425c923,
+ 0x938b74c1, 0x43fb3746,
+ 0x9370cae4, 0x43d09aed, 0x935631c5, 0x43a5f41e, 0x933ba968, 0x437b42e1,
+ 0x932131d1, 0x4350873c,
+ 0x9306cb04, 0x4325c135, 0x92ec7505, 0x42faf0d4, 0x92d22fd9, 0x42d0161e,
+ 0x92b7fb82, 0x42a5311b,
+ 0x929dd806, 0x427a41d0, 0x9283c568, 0x424f4845, 0x9269c3ac, 0x42244481,
+ 0x924fd2d7, 0x41f93689,
+ 0x9235f2ec, 0x41ce1e65, 0x921c23ef, 0x41a2fc1a, 0x920265e4, 0x4177cfb1,
+ 0x91e8b8d0, 0x414c992f,
+ 0x91cf1cb6, 0x4121589b, 0x91b5919a, 0x40f60dfb, 0x919c1781, 0x40cab958,
+ 0x9182ae6d, 0x409f5ab6,
+ 0x91695663, 0x4073f21d, 0x91500f67, 0x40487f94, 0x9136d97d, 0x401d0321,
+ 0x911db4a9, 0x3ff17cca,
+ 0x9104a0ee, 0x3fc5ec98, 0x90eb9e50, 0x3f9a5290, 0x90d2acd4, 0x3f6eaeb8,
+ 0x90b9cc7d, 0x3f430119,
+ 0x90a0fd4e, 0x3f1749b8, 0x90883f4d, 0x3eeb889c, 0x906f927c, 0x3ebfbdcd,
+ 0x9056f6df, 0x3e93e950,
+ 0x903e6c7b, 0x3e680b2c, 0x9025f352, 0x3e3c2369, 0x900d8b69, 0x3e10320d,
+ 0x8ff534c4, 0x3de4371f,
+ 0x8fdcef66, 0x3db832a6, 0x8fc4bb53, 0x3d8c24a8, 0x8fac988f, 0x3d600d2c,
+ 0x8f94871d, 0x3d33ec39,
+ 0x8f7c8701, 0x3d07c1d6, 0x8f649840, 0x3cdb8e09, 0x8f4cbadb, 0x3caf50da,
+ 0x8f34eed8, 0x3c830a50,
+ 0x8f1d343a, 0x3c56ba70, 0x8f058b04, 0x3c2a6142, 0x8eedf33b, 0x3bfdfecd,
+ 0x8ed66ce1, 0x3bd19318,
+ 0x8ebef7fb, 0x3ba51e29, 0x8ea7948c, 0x3b78a007, 0x8e904298, 0x3b4c18ba,
+ 0x8e790222, 0x3b1f8848,
+ 0x8e61d32e, 0x3af2eeb7, 0x8e4ab5bf, 0x3ac64c0f, 0x8e33a9da, 0x3a99a057,
+ 0x8e1caf80, 0x3a6ceb96,
+ 0x8e05c6b7, 0x3a402dd2, 0x8deeef82, 0x3a136712, 0x8dd829e4, 0x39e6975e,
+ 0x8dc175e0, 0x39b9bebc,
+ 0x8daad37b, 0x398cdd32, 0x8d9442b8, 0x395ff2c9, 0x8d7dc399, 0x3932ff87,
+ 0x8d675623, 0x39060373,
+ 0x8d50fa59, 0x38d8fe93, 0x8d3ab03f, 0x38abf0ef, 0x8d2477d8, 0x387eda8e,
+ 0x8d0e5127, 0x3851bb77,
+ 0x8cf83c30, 0x382493b0, 0x8ce238f6, 0x37f76341, 0x8ccc477d, 0x37ca2a30,
+ 0x8cb667c8, 0x379ce885,
+ 0x8ca099da, 0x376f9e46, 0x8c8addb7, 0x37424b7b, 0x8c753362, 0x3714f02a,
+ 0x8c5f9ade, 0x36e78c5b,
+ 0x8c4a142f, 0x36ba2014, 0x8c349f58, 0x368cab5c, 0x8c1f3c5d, 0x365f2e3b,
+ 0x8c09eb40, 0x3631a8b8,
+ 0x8bf4ac05, 0x36041ad9, 0x8bdf7eb0, 0x35d684a6, 0x8bca6343, 0x35a8e625,
+ 0x8bb559c1, 0x357b3f5d,
+ 0x8ba0622f, 0x354d9057, 0x8b8b7c8f, 0x351fd918, 0x8b76a8e4, 0x34f219a8,
+ 0x8b61e733, 0x34c4520d,
+ 0x8b4d377c, 0x34968250, 0x8b3899c6, 0x3468aa76, 0x8b240e11, 0x343aca87,
+ 0x8b0f9462, 0x340ce28b,
+ 0x8afb2cbb, 0x33def287, 0x8ae6d720, 0x33b0fa84, 0x8ad29394, 0x3382fa88,
+ 0x8abe6219, 0x3354f29b,
+ 0x8aaa42b4, 0x3326e2c3, 0x8a963567, 0x32f8cb07, 0x8a823a36, 0x32caab6f,
+ 0x8a6e5123, 0x329c8402,
+ 0x8a5a7a31, 0x326e54c7, 0x8a46b564, 0x32401dc6, 0x8a3302be, 0x3211df04,
+ 0x8a1f6243, 0x31e39889,
+ 0x8a0bd3f5, 0x31b54a5e, 0x89f857d8, 0x3186f487, 0x89e4edef, 0x3158970e,
+ 0x89d1963c, 0x312a31f8,
+ 0x89be50c3, 0x30fbc54d, 0x89ab1d87, 0x30cd5115, 0x8997fc8a, 0x309ed556,
+ 0x8984edcf, 0x30705217,
+ 0x8971f15a, 0x3041c761, 0x895f072e, 0x30133539, 0x894c2f4c, 0x2fe49ba7,
+ 0x893969b9, 0x2fb5fab2,
+ 0x8926b677, 0x2f875262, 0x89141589, 0x2f58a2be, 0x890186f2, 0x2f29ebcc,
+ 0x88ef0ab4, 0x2efb2d95,
+ 0x88dca0d3, 0x2ecc681e, 0x88ca4951, 0x2e9d9b70, 0x88b80432, 0x2e6ec792,
+ 0x88a5d177, 0x2e3fec8b,
+ 0x8893b125, 0x2e110a62, 0x8881a33d, 0x2de2211e, 0x886fa7c2, 0x2db330c7,
+ 0x885dbeb8, 0x2d843964,
+ 0x884be821, 0x2d553afc, 0x883a23ff, 0x2d263596, 0x88287256, 0x2cf72939,
+ 0x8816d327, 0x2cc815ee,
+ 0x88054677, 0x2c98fbba, 0x87f3cc48, 0x2c69daa6, 0x87e2649b, 0x2c3ab2b9,
+ 0x87d10f75, 0x2c0b83fa,
+ 0x87bfccd7, 0x2bdc4e6f, 0x87ae9cc5, 0x2bad1221, 0x879d7f41, 0x2b7dcf17,
+ 0x878c744d, 0x2b4e8558,
+ 0x877b7bec, 0x2b1f34eb, 0x876a9621, 0x2aefddd8, 0x8759c2ef, 0x2ac08026,
+ 0x87490258, 0x2a911bdc,
+ 0x8738545e, 0x2a61b101, 0x8727b905, 0x2a323f9e, 0x8717304e, 0x2a02c7b8,
+ 0x8706ba3d, 0x29d34958,
+ 0x86f656d3, 0x29a3c485, 0x86e60614, 0x29743946, 0x86d5c802, 0x2944a7a2,
+ 0x86c59c9f, 0x29150fa1,
+ 0x86b583ee, 0x28e5714b, 0x86a57df2, 0x28b5cca5, 0x86958aac, 0x288621b9,
+ 0x8685aa20, 0x2856708d,
+ 0x8675dc4f, 0x2826b928, 0x8666213c, 0x27f6fb92, 0x865678eb, 0x27c737d3,
+ 0x8646e35c, 0x27976df1,
+ 0x86376092, 0x27679df4, 0x8627f091, 0x2737c7e3, 0x86189359, 0x2707ebc7,
+ 0x860948ef, 0x26d809a5,
+ 0x85fa1153, 0x26a82186, 0x85eaec88, 0x26783370, 0x85dbda91, 0x26483f6c,
+ 0x85ccdb70, 0x26184581,
+ 0x85bdef28, 0x25e845b6, 0x85af15b9, 0x25b84012, 0x85a04f28, 0x2588349d,
+ 0x85919b76, 0x2558235f,
+ 0x8582faa5, 0x25280c5e, 0x85746cb8, 0x24f7efa2, 0x8565f1b0, 0x24c7cd33,
+ 0x85578991, 0x2497a517,
+ 0x8549345c, 0x24677758, 0x853af214, 0x243743fa, 0x852cc2bb, 0x24070b08,
+ 0x851ea652, 0x23d6cc87,
+ 0x85109cdd, 0x23a6887f, 0x8502a65c, 0x23763ef7, 0x84f4c2d4, 0x2345eff8,
+ 0x84e6f244, 0x23159b88,
+ 0x84d934b1, 0x22e541af, 0x84cb8a1b, 0x22b4e274, 0x84bdf286, 0x22847de0,
+ 0x84b06df2, 0x225413f8,
+ 0x84a2fc62, 0x2223a4c5, 0x84959dd9, 0x21f3304f, 0x84885258, 0x21c2b69c,
+ 0x847b19e1, 0x219237b5,
+ 0x846df477, 0x2161b3a0, 0x8460e21a, 0x21312a65, 0x8453e2cf, 0x21009c0c,
+ 0x8446f695, 0x20d0089c,
+ 0x843a1d70, 0x209f701c, 0x842d5762, 0x206ed295, 0x8420a46c, 0x203e300d,
+ 0x84140490, 0x200d888d,
+ 0x840777d0, 0x1fdcdc1b, 0x83fafe2e, 0x1fac2abf, 0x83ee97ad, 0x1f7b7481,
+ 0x83e2444d, 0x1f4ab968,
+ 0x83d60412, 0x1f19f97b, 0x83c9d6fc, 0x1ee934c3, 0x83bdbd0e, 0x1eb86b46,
+ 0x83b1b649, 0x1e879d0d,
+ 0x83a5c2b0, 0x1e56ca1e, 0x8399e244, 0x1e25f282, 0x838e1507, 0x1df5163f,
+ 0x83825afb, 0x1dc4355e,
+ 0x8376b422, 0x1d934fe5, 0x836b207d, 0x1d6265dd, 0x835fa00f, 0x1d31774d,
+ 0x835432d8, 0x1d00843d,
+ 0x8348d8dc, 0x1ccf8cb3, 0x833d921b, 0x1c9e90b8, 0x83325e97, 0x1c6d9053,
+ 0x83273e52, 0x1c3c8b8c,
+ 0x831c314e, 0x1c0b826a, 0x8311378d, 0x1bda74f6, 0x83065110, 0x1ba96335,
+ 0x82fb7dd8, 0x1b784d30,
+ 0x82f0bde8, 0x1b4732ef, 0x82e61141, 0x1b161479, 0x82db77e5, 0x1ae4f1d6,
+ 0x82d0f1d5, 0x1ab3cb0d,
+ 0x82c67f14, 0x1a82a026, 0x82bc1fa2, 0x1a517128, 0x82b1d381, 0x1a203e1b,
+ 0x82a79ab3, 0x19ef0707,
+ 0x829d753a, 0x19bdcbf3, 0x82936317, 0x198c8ce7, 0x8289644b, 0x195b49ea,
+ 0x827f78d8, 0x192a0304,
+ 0x8275a0c0, 0x18f8b83c, 0x826bdc04, 0x18c7699b, 0x82622aa6, 0x18961728,
+ 0x82588ca7, 0x1864c0ea,
+ 0x824f0208, 0x183366e9, 0x82458acc, 0x1802092c, 0x823c26f3, 0x17d0a7bc,
+ 0x8232d67f, 0x179f429f,
+ 0x82299971, 0x176dd9de, 0x82206fcc, 0x173c6d80, 0x82175990, 0x170afd8d,
+ 0x820e56be, 0x16d98a0c,
+ 0x82056758, 0x16a81305, 0x81fc8b60, 0x1676987f, 0x81f3c2d7, 0x16451a83,
+ 0x81eb0dbe, 0x16139918,
+ 0x81e26c16, 0x15e21445, 0x81d9dde1, 0x15b08c12, 0x81d16321, 0x157f0086,
+ 0x81c8fbd6, 0x154d71aa,
+ 0x81c0a801, 0x151bdf86, 0x81b867a5, 0x14ea4a1f, 0x81b03ac2, 0x14b8b17f,
+ 0x81a82159, 0x148715ae,
+ 0x81a01b6d, 0x145576b1, 0x819828fd, 0x1423d492, 0x81904a0c, 0x13f22f58,
+ 0x81887e9a, 0x13c0870a,
+ 0x8180c6a9, 0x138edbb1, 0x8179223a, 0x135d2d53, 0x8171914e, 0x132b7bf9,
+ 0x816a13e6, 0x12f9c7aa,
+ 0x8162aa04, 0x12c8106f, 0x815b53a8, 0x1296564d, 0x815410d4, 0x1264994e,
+ 0x814ce188, 0x1232d979,
+ 0x8145c5c7, 0x120116d5, 0x813ebd90, 0x11cf516a, 0x8137c8e6, 0x119d8941,
+ 0x8130e7c9, 0x116bbe60,
+ 0x812a1a3a, 0x1139f0cf, 0x8123603a, 0x11082096, 0x811cb9ca, 0x10d64dbd,
+ 0x811626ec, 0x10a4784b,
+ 0x810fa7a0, 0x1072a048, 0x81093be8, 0x1040c5bb, 0x8102e3c4, 0x100ee8ad,
+ 0x80fc9f35, 0xfdd0926,
+ 0x80f66e3c, 0xfab272b, 0x80f050db, 0xf7942c7, 0x80ea4712, 0xf475bff,
+ 0x80e450e2, 0xf1572dc,
+ 0x80de6e4c, 0xee38766, 0x80d89f51, 0xeb199a4, 0x80d2e3f2, 0xe7fa99e,
+ 0x80cd3c2f, 0xe4db75b,
+ 0x80c7a80a, 0xe1bc2e4, 0x80c22784, 0xde9cc40, 0x80bcba9d, 0xdb7d376,
+ 0x80b76156, 0xd85d88f,
+ 0x80b21baf, 0xd53db92, 0x80ace9ab, 0xd21dc87, 0x80a7cb49, 0xcefdb76,
+ 0x80a2c08b, 0xcbdd865,
+ 0x809dc971, 0xc8bd35e, 0x8098e5fb, 0xc59cc68, 0x8094162c, 0xc27c389,
+ 0x808f5a02, 0xbf5b8cb,
+ 0x808ab180, 0xbc3ac35, 0x80861ca6, 0xb919dcf, 0x80819b74, 0xb5f8d9f,
+ 0x807d2dec, 0xb2d7baf,
+ 0x8078d40d, 0xafb6805, 0x80748dd9, 0xac952aa, 0x80705b50, 0xa973ba5,
+ 0x806c3c74, 0xa6522fe,
+ 0x80683143, 0xa3308bd, 0x806439c0, 0xa00ece8, 0x806055eb, 0x9cecf89,
+ 0x805c85c4, 0x99cb0a7,
+ 0x8058c94c, 0x96a9049, 0x80552084, 0x9386e78, 0x80518b6b, 0x9064b3a,
+ 0x804e0a04, 0x8d42699,
+ 0x804a9c4d, 0x8a2009a, 0x80474248, 0x86fd947, 0x8043fbf6, 0x83db0a7,
+ 0x8040c956, 0x80b86c2,
+ 0x803daa6a, 0x7d95b9e, 0x803a9f31, 0x7a72f45, 0x8037a7ac, 0x77501be,
+ 0x8034c3dd, 0x742d311,
+ 0x8031f3c2, 0x710a345, 0x802f375d, 0x6de7262, 0x802c8ead, 0x6ac406f,
+ 0x8029f9b4, 0x67a0d76,
+ 0x80277872, 0x647d97c, 0x80250ae7, 0x615a48b, 0x8022b114, 0x5e36ea9,
+ 0x80206af8, 0x5b137df,
+ 0x801e3895, 0x57f0035, 0x801c19ea, 0x54cc7b1, 0x801a0ef8, 0x51a8e5c,
+ 0x801817bf, 0x4e8543e,
+ 0x80163440, 0x4b6195d, 0x8014647b, 0x483ddc3, 0x8012a86f, 0x451a177,
+ 0x8011001f, 0x41f6480,
+ 0x800f6b88, 0x3ed26e6, 0x800deaad, 0x3bae8b2, 0x800c7d8c, 0x388a9ea,
+ 0x800b2427, 0x3566a96,
+ 0x8009de7e, 0x3242abf, 0x8008ac90, 0x2f1ea6c, 0x80078e5e, 0x2bfa9a4,
+ 0x800683e8, 0x28d6870,
+ 0x80058d2f, 0x25b26d7, 0x8004aa32, 0x228e4e2, 0x8003daf1, 0x1f6a297,
+ 0x80031f6d, 0x1c45ffe,
+ 0x800277a6, 0x1921d20, 0x8001e39b, 0x15fda03, 0x8001634e, 0x12d96b1,
+ 0x8000f6bd, 0xfb5330,
+ 0x80009dea, 0xc90f88, 0x800058d4, 0x96cbc1, 0x8000277a, 0x6487e3,
+ 0x800009df, 0x3243f5,
+ 0x80000000, 0x0, 0x800009df, 0xffcdbc0b, 0x8000277a, 0xff9b781d, 0x800058d4,
+ 0xff69343f,
+ 0x80009dea, 0xff36f078, 0x8000f6bd, 0xff04acd0, 0x8001634e, 0xfed2694f,
+ 0x8001e39b, 0xfea025fd,
+ 0x800277a6, 0xfe6de2e0, 0x80031f6d, 0xfe3ba002, 0x8003daf1, 0xfe095d69,
+ 0x8004aa32, 0xfdd71b1e,
+ 0x80058d2f, 0xfda4d929, 0x800683e8, 0xfd729790, 0x80078e5e, 0xfd40565c,
+ 0x8008ac90, 0xfd0e1594,
+ 0x8009de7e, 0xfcdbd541, 0x800b2427, 0xfca9956a, 0x800c7d8c, 0xfc775616,
+ 0x800deaad, 0xfc45174e,
+ 0x800f6b88, 0xfc12d91a, 0x8011001f, 0xfbe09b80, 0x8012a86f, 0xfbae5e89,
+ 0x8014647b, 0xfb7c223d,
+ 0x80163440, 0xfb49e6a3, 0x801817bf, 0xfb17abc2, 0x801a0ef8, 0xfae571a4,
+ 0x801c19ea, 0xfab3384f,
+ 0x801e3895, 0xfa80ffcb, 0x80206af8, 0xfa4ec821, 0x8022b114, 0xfa1c9157,
+ 0x80250ae7, 0xf9ea5b75,
+ 0x80277872, 0xf9b82684, 0x8029f9b4, 0xf985f28a, 0x802c8ead, 0xf953bf91,
+ 0x802f375d, 0xf9218d9e,
+ 0x8031f3c2, 0xf8ef5cbb, 0x8034c3dd, 0xf8bd2cef, 0x8037a7ac, 0xf88afe42,
+ 0x803a9f31, 0xf858d0bb,
+ 0x803daa6a, 0xf826a462, 0x8040c956, 0xf7f4793e, 0x8043fbf6, 0xf7c24f59,
+ 0x80474248, 0xf79026b9,
+ 0x804a9c4d, 0xf75dff66, 0x804e0a04, 0xf72bd967, 0x80518b6b, 0xf6f9b4c6,
+ 0x80552084, 0xf6c79188,
+ 0x8058c94c, 0xf6956fb7, 0x805c85c4, 0xf6634f59, 0x806055eb, 0xf6313077,
+ 0x806439c0, 0xf5ff1318,
+ 0x80683143, 0xf5ccf743, 0x806c3c74, 0xf59add02, 0x80705b50, 0xf568c45b,
+ 0x80748dd9, 0xf536ad56,
+ 0x8078d40d, 0xf50497fb, 0x807d2dec, 0xf4d28451, 0x80819b74, 0xf4a07261,
+ 0x80861ca6, 0xf46e6231,
+ 0x808ab180, 0xf43c53cb, 0x808f5a02, 0xf40a4735, 0x8094162c, 0xf3d83c77,
+ 0x8098e5fb, 0xf3a63398,
+ 0x809dc971, 0xf3742ca2, 0x80a2c08b, 0xf342279b, 0x80a7cb49, 0xf310248a,
+ 0x80ace9ab, 0xf2de2379,
+ 0x80b21baf, 0xf2ac246e, 0x80b76156, 0xf27a2771, 0x80bcba9d, 0xf2482c8a,
+ 0x80c22784, 0xf21633c0,
+ 0x80c7a80a, 0xf1e43d1c, 0x80cd3c2f, 0xf1b248a5, 0x80d2e3f2, 0xf1805662,
+ 0x80d89f51, 0xf14e665c,
+ 0x80de6e4c, 0xf11c789a, 0x80e450e2, 0xf0ea8d24, 0x80ea4712, 0xf0b8a401,
+ 0x80f050db, 0xf086bd39,
+ 0x80f66e3c, 0xf054d8d5, 0x80fc9f35, 0xf022f6da, 0x8102e3c4, 0xeff11753,
+ 0x81093be8, 0xefbf3a45,
+ 0x810fa7a0, 0xef8d5fb8, 0x811626ec, 0xef5b87b5, 0x811cb9ca, 0xef29b243,
+ 0x8123603a, 0xeef7df6a,
+ 0x812a1a3a, 0xeec60f31, 0x8130e7c9, 0xee9441a0, 0x8137c8e6, 0xee6276bf,
+ 0x813ebd90, 0xee30ae96,
+ 0x8145c5c7, 0xedfee92b, 0x814ce188, 0xedcd2687, 0x815410d4, 0xed9b66b2,
+ 0x815b53a8, 0xed69a9b3,
+ 0x8162aa04, 0xed37ef91, 0x816a13e6, 0xed063856, 0x8171914e, 0xecd48407,
+ 0x8179223a, 0xeca2d2ad,
+ 0x8180c6a9, 0xec71244f, 0x81887e9a, 0xec3f78f6, 0x81904a0c, 0xec0dd0a8,
+ 0x819828fd, 0xebdc2b6e,
+ 0x81a01b6d, 0xebaa894f, 0x81a82159, 0xeb78ea52, 0x81b03ac2, 0xeb474e81,
+ 0x81b867a5, 0xeb15b5e1,
+ 0x81c0a801, 0xeae4207a, 0x81c8fbd6, 0xeab28e56, 0x81d16321, 0xea80ff7a,
+ 0x81d9dde1, 0xea4f73ee,
+ 0x81e26c16, 0xea1debbb, 0x81eb0dbe, 0xe9ec66e8, 0x81f3c2d7, 0xe9bae57d,
+ 0x81fc8b60, 0xe9896781,
+ 0x82056758, 0xe957ecfb, 0x820e56be, 0xe92675f4, 0x82175990, 0xe8f50273,
+ 0x82206fcc, 0xe8c39280,
+ 0x82299971, 0xe8922622, 0x8232d67f, 0xe860bd61, 0x823c26f3, 0xe82f5844,
+ 0x82458acc, 0xe7fdf6d4,
+ 0x824f0208, 0xe7cc9917, 0x82588ca7, 0xe79b3f16, 0x82622aa6, 0xe769e8d8,
+ 0x826bdc04, 0xe7389665,
+ 0x8275a0c0, 0xe70747c4, 0x827f78d8, 0xe6d5fcfc, 0x8289644b, 0xe6a4b616,
+ 0x82936317, 0xe6737319,
+ 0x829d753a, 0xe642340d, 0x82a79ab3, 0xe610f8f9, 0x82b1d381, 0xe5dfc1e5,
+ 0x82bc1fa2, 0xe5ae8ed8,
+ 0x82c67f14, 0xe57d5fda, 0x82d0f1d5, 0xe54c34f3, 0x82db77e5, 0xe51b0e2a,
+ 0x82e61141, 0xe4e9eb87,
+ 0x82f0bde8, 0xe4b8cd11, 0x82fb7dd8, 0xe487b2d0, 0x83065110, 0xe4569ccb,
+ 0x8311378d, 0xe4258b0a,
+ 0x831c314e, 0xe3f47d96, 0x83273e52, 0xe3c37474, 0x83325e97, 0xe3926fad,
+ 0x833d921b, 0xe3616f48,
+ 0x8348d8dc, 0xe330734d, 0x835432d8, 0xe2ff7bc3, 0x835fa00f, 0xe2ce88b3,
+ 0x836b207d, 0xe29d9a23,
+ 0x8376b422, 0xe26cb01b, 0x83825afb, 0xe23bcaa2, 0x838e1507, 0xe20ae9c1,
+ 0x8399e244, 0xe1da0d7e,
+ 0x83a5c2b0, 0xe1a935e2, 0x83b1b649, 0xe17862f3, 0x83bdbd0e, 0xe14794ba,
+ 0x83c9d6fc, 0xe116cb3d,
+ 0x83d60412, 0xe0e60685, 0x83e2444d, 0xe0b54698, 0x83ee97ad, 0xe0848b7f,
+ 0x83fafe2e, 0xe053d541,
+ 0x840777d0, 0xe02323e5, 0x84140490, 0xdff27773, 0x8420a46c, 0xdfc1cff3,
+ 0x842d5762, 0xdf912d6b,
+ 0x843a1d70, 0xdf608fe4, 0x8446f695, 0xdf2ff764, 0x8453e2cf, 0xdeff63f4,
+ 0x8460e21a, 0xdeced59b,
+ 0x846df477, 0xde9e4c60, 0x847b19e1, 0xde6dc84b, 0x84885258, 0xde3d4964,
+ 0x84959dd9, 0xde0ccfb1,
+ 0x84a2fc62, 0xdddc5b3b, 0x84b06df2, 0xddabec08, 0x84bdf286, 0xdd7b8220,
+ 0x84cb8a1b, 0xdd4b1d8c,
+ 0x84d934b1, 0xdd1abe51, 0x84e6f244, 0xdcea6478, 0x84f4c2d4, 0xdcba1008,
+ 0x8502a65c, 0xdc89c109,
+ 0x85109cdd, 0xdc597781, 0x851ea652, 0xdc293379, 0x852cc2bb, 0xdbf8f4f8,
+ 0x853af214, 0xdbc8bc06,
+ 0x8549345c, 0xdb9888a8, 0x85578991, 0xdb685ae9, 0x8565f1b0, 0xdb3832cd,
+ 0x85746cb8, 0xdb08105e,
+ 0x8582faa5, 0xdad7f3a2, 0x85919b76, 0xdaa7dca1, 0x85a04f28, 0xda77cb63,
+ 0x85af15b9, 0xda47bfee,
+ 0x85bdef28, 0xda17ba4a, 0x85ccdb70, 0xd9e7ba7f, 0x85dbda91, 0xd9b7c094,
+ 0x85eaec88, 0xd987cc90,
+ 0x85fa1153, 0xd957de7a, 0x860948ef, 0xd927f65b, 0x86189359, 0xd8f81439,
+ 0x8627f091, 0xd8c8381d,
+ 0x86376092, 0xd898620c, 0x8646e35c, 0xd868920f, 0x865678eb, 0xd838c82d,
+ 0x8666213c, 0xd809046e,
+ 0x8675dc4f, 0xd7d946d8, 0x8685aa20, 0xd7a98f73, 0x86958aac, 0xd779de47,
+ 0x86a57df2, 0xd74a335b,
+ 0x86b583ee, 0xd71a8eb5, 0x86c59c9f, 0xd6eaf05f, 0x86d5c802, 0xd6bb585e,
+ 0x86e60614, 0xd68bc6ba,
+ 0x86f656d3, 0xd65c3b7b, 0x8706ba3d, 0xd62cb6a8, 0x8717304e, 0xd5fd3848,
+ 0x8727b905, 0xd5cdc062,
+ 0x8738545e, 0xd59e4eff, 0x87490258, 0xd56ee424, 0x8759c2ef, 0xd53f7fda,
+ 0x876a9621, 0xd5102228,
+ 0x877b7bec, 0xd4e0cb15, 0x878c744d, 0xd4b17aa8, 0x879d7f41, 0xd48230e9,
+ 0x87ae9cc5, 0xd452eddf,
+ 0x87bfccd7, 0xd423b191, 0x87d10f75, 0xd3f47c06, 0x87e2649b, 0xd3c54d47,
+ 0x87f3cc48, 0xd396255a,
+ 0x88054677, 0xd3670446, 0x8816d327, 0xd337ea12, 0x88287256, 0xd308d6c7,
+ 0x883a23ff, 0xd2d9ca6a,
+ 0x884be821, 0xd2aac504, 0x885dbeb8, 0xd27bc69c, 0x886fa7c2, 0xd24ccf39,
+ 0x8881a33d, 0xd21ddee2,
+ 0x8893b125, 0xd1eef59e, 0x88a5d177, 0xd1c01375, 0x88b80432, 0xd191386e,
+ 0x88ca4951, 0xd1626490,
+ 0x88dca0d3, 0xd13397e2, 0x88ef0ab4, 0xd104d26b, 0x890186f2, 0xd0d61434,
+ 0x89141589, 0xd0a75d42,
+ 0x8926b677, 0xd078ad9e, 0x893969b9, 0xd04a054e, 0x894c2f4c, 0xd01b6459,
+ 0x895f072e, 0xcfeccac7,
+ 0x8971f15a, 0xcfbe389f, 0x8984edcf, 0xcf8fade9, 0x8997fc8a, 0xcf612aaa,
+ 0x89ab1d87, 0xcf32aeeb,
+ 0x89be50c3, 0xcf043ab3, 0x89d1963c, 0xced5ce08, 0x89e4edef, 0xcea768f2,
+ 0x89f857d8, 0xce790b79,
+ 0x8a0bd3f5, 0xce4ab5a2, 0x8a1f6243, 0xce1c6777, 0x8a3302be, 0xcdee20fc,
+ 0x8a46b564, 0xcdbfe23a,
+ 0x8a5a7a31, 0xcd91ab39, 0x8a6e5123, 0xcd637bfe, 0x8a823a36, 0xcd355491,
+ 0x8a963567, 0xcd0734f9,
+ 0x8aaa42b4, 0xccd91d3d, 0x8abe6219, 0xccab0d65, 0x8ad29394, 0xcc7d0578,
+ 0x8ae6d720, 0xcc4f057c,
+ 0x8afb2cbb, 0xcc210d79, 0x8b0f9462, 0xcbf31d75, 0x8b240e11, 0xcbc53579,
+ 0x8b3899c6, 0xcb97558a,
+ 0x8b4d377c, 0xcb697db0, 0x8b61e733, 0xcb3badf3, 0x8b76a8e4, 0xcb0de658,
+ 0x8b8b7c8f, 0xcae026e8,
+ 0x8ba0622f, 0xcab26fa9, 0x8bb559c1, 0xca84c0a3, 0x8bca6343, 0xca5719db,
+ 0x8bdf7eb0, 0xca297b5a,
+ 0x8bf4ac05, 0xc9fbe527, 0x8c09eb40, 0xc9ce5748, 0x8c1f3c5d, 0xc9a0d1c5,
+ 0x8c349f58, 0xc97354a4,
+ 0x8c4a142f, 0xc945dfec, 0x8c5f9ade, 0xc91873a5, 0x8c753362, 0xc8eb0fd6,
+ 0x8c8addb7, 0xc8bdb485,
+ 0x8ca099da, 0xc89061ba, 0x8cb667c8, 0xc863177b, 0x8ccc477d, 0xc835d5d0,
+ 0x8ce238f6, 0xc8089cbf,
+ 0x8cf83c30, 0xc7db6c50, 0x8d0e5127, 0xc7ae4489, 0x8d2477d8, 0xc7812572,
+ 0x8d3ab03f, 0xc7540f11,
+ 0x8d50fa59, 0xc727016d, 0x8d675623, 0xc6f9fc8d, 0x8d7dc399, 0xc6cd0079,
+ 0x8d9442b8, 0xc6a00d37,
+ 0x8daad37b, 0xc67322ce, 0x8dc175e0, 0xc6464144, 0x8dd829e4, 0xc61968a2,
+ 0x8deeef82, 0xc5ec98ee,
+ 0x8e05c6b7, 0xc5bfd22e, 0x8e1caf80, 0xc593146a, 0x8e33a9da, 0xc5665fa9,
+ 0x8e4ab5bf, 0xc539b3f1,
+ 0x8e61d32e, 0xc50d1149, 0x8e790222, 0xc4e077b8, 0x8e904298, 0xc4b3e746,
+ 0x8ea7948c, 0xc4875ff9,
+ 0x8ebef7fb, 0xc45ae1d7, 0x8ed66ce1, 0xc42e6ce8, 0x8eedf33b, 0xc4020133,
+ 0x8f058b04, 0xc3d59ebe,
+ 0x8f1d343a, 0xc3a94590, 0x8f34eed8, 0xc37cf5b0, 0x8f4cbadb, 0xc350af26,
+ 0x8f649840, 0xc32471f7,
+ 0x8f7c8701, 0xc2f83e2a, 0x8f94871d, 0xc2cc13c7, 0x8fac988f, 0xc29ff2d4,
+ 0x8fc4bb53, 0xc273db58,
+ 0x8fdcef66, 0xc247cd5a, 0x8ff534c4, 0xc21bc8e1, 0x900d8b69, 0xc1efcdf3,
+ 0x9025f352, 0xc1c3dc97,
+ 0x903e6c7b, 0xc197f4d4, 0x9056f6df, 0xc16c16b0, 0x906f927c, 0xc1404233,
+ 0x90883f4d, 0xc1147764,
+ 0x90a0fd4e, 0xc0e8b648, 0x90b9cc7d, 0xc0bcfee7, 0x90d2acd4, 0xc0915148,
+ 0x90eb9e50, 0xc065ad70,
+ 0x9104a0ee, 0xc03a1368, 0x911db4a9, 0xc00e8336, 0x9136d97d, 0xbfe2fcdf,
+ 0x91500f67, 0xbfb7806c,
+ 0x91695663, 0xbf8c0de3, 0x9182ae6d, 0xbf60a54a, 0x919c1781, 0xbf3546a8,
+ 0x91b5919a, 0xbf09f205,
+ 0x91cf1cb6, 0xbedea765, 0x91e8b8d0, 0xbeb366d1, 0x920265e4, 0xbe88304f,
+ 0x921c23ef, 0xbe5d03e6,
+ 0x9235f2ec, 0xbe31e19b, 0x924fd2d7, 0xbe06c977, 0x9269c3ac, 0xbddbbb7f,
+ 0x9283c568, 0xbdb0b7bb,
+ 0x929dd806, 0xbd85be30, 0x92b7fb82, 0xbd5acee5, 0x92d22fd9, 0xbd2fe9e2,
+ 0x92ec7505, 0xbd050f2c,
+ 0x9306cb04, 0xbcda3ecb, 0x932131d1, 0xbcaf78c4, 0x933ba968, 0xbc84bd1f,
+ 0x935631c5, 0xbc5a0be2,
+ 0x9370cae4, 0xbc2f6513, 0x938b74c1, 0xbc04c8ba, 0x93a62f57, 0xbbda36dd,
+ 0x93c0faa3, 0xbbafaf82,
+ 0x93dbd6a0, 0xbb8532b0, 0x93f6c34a, 0xbb5ac06d, 0x9411c09e, 0xbb3058c0,
+ 0x942cce96, 0xbb05fbb0,
+ 0x9447ed2f, 0xbadba943, 0x94631c65, 0xbab16180, 0x947e5c33, 0xba87246d,
+ 0x9499ac95, 0xba5cf210,
+ 0x94b50d87, 0xba32ca71, 0x94d07f05, 0xba08ad95, 0x94ec010b, 0xb9de9b83,
+ 0x95079394, 0xb9b49442,
+ 0x9523369c, 0xb98a97d8, 0x953eea1e, 0xb960a64c, 0x955aae17, 0xb936bfa4,
+ 0x95768283, 0xb90ce3e6,
+ 0x9592675c, 0xb8e31319, 0x95ae5c9f, 0xb8b94d44, 0x95ca6247, 0xb88f926d,
+ 0x95e67850, 0xb865e299,
+ 0x96029eb6, 0xb83c3dd1, 0x961ed574, 0xb812a41a, 0x963b1c86, 0xb7e9157a,
+ 0x965773e7, 0xb7bf91f8,
+ 0x9673db94, 0xb796199b, 0x96905388, 0xb76cac69, 0x96acdbbe, 0xb7434a67,
+ 0x96c97432, 0xb719f39e,
+ 0x96e61ce0, 0xb6f0a812, 0x9702d5c3, 0xb6c767ca, 0x971f9ed7, 0xb69e32cd,
+ 0x973c7817, 0xb6750921,
+ 0x9759617f, 0xb64beacd, 0x97765b0a, 0xb622d7d6, 0x979364b5, 0xb5f9d043,
+ 0x97b07e7a, 0xb5d0d41a,
+ 0x97cda855, 0xb5a7e362, 0x97eae242, 0xb57efe22, 0x98082c3b, 0xb556245e,
+ 0x9825863d, 0xb52d561e,
+ 0x9842f043, 0xb5049368, 0x98606a49, 0xb4dbdc42, 0x987df449, 0xb4b330b3,
+ 0x989b8e40, 0xb48a90c0,
+ 0x98b93828, 0xb461fc70, 0x98d6f1fe, 0xb43973ca, 0x98f4bbbc, 0xb410f6d3,
+ 0x9912955f, 0xb3e88592,
+ 0x99307ee0, 0xb3c0200c, 0x994e783d, 0xb397c649, 0x996c816f, 0xb36f784f,
+ 0x998a9a74, 0xb3473623,
+ 0x99a8c345, 0xb31effcc, 0x99c6fbde, 0xb2f6d550, 0x99e5443b, 0xb2ceb6b5,
+ 0x9a039c57, 0xb2a6a402,
+ 0x9a22042d, 0xb27e9d3c, 0x9a407bb9, 0xb256a26a, 0x9a5f02f5, 0xb22eb392,
+ 0x9a7d99de, 0xb206d0ba,
+ 0x9a9c406e, 0xb1def9e9, 0x9abaf6a1, 0xb1b72f23, 0x9ad9bc71, 0xb18f7071,
+ 0x9af891db, 0xb167bdd7,
+ 0x9b1776da, 0xb140175b, 0x9b366b68, 0xb1187d05, 0x9b556f81, 0xb0f0eeda,
+ 0x9b748320, 0xb0c96ce0,
+ 0x9b93a641, 0xb0a1f71d, 0x9bb2d8de, 0xb07a8d97, 0x9bd21af3, 0xb0533055,
+ 0x9bf16c7a, 0xb02bdf5c,
+ 0x9c10cd70, 0xb0049ab3, 0x9c303dcf, 0xafdd625f, 0x9c4fbd93, 0xafb63667,
+ 0x9c6f4cb6, 0xaf8f16d1,
+ 0x9c8eeb34, 0xaf6803a2, 0x9cae9907, 0xaf40fce1, 0x9cce562c, 0xaf1a0293,
+ 0x9cee229c, 0xaef314c0,
+ 0x9d0dfe54, 0xaecc336c, 0x9d2de94d, 0xaea55e9e, 0x9d4de385, 0xae7e965b,
+ 0x9d6decf4, 0xae57daab,
+ 0x9d8e0597, 0xae312b92, 0x9dae2d68, 0xae0a8916, 0x9dce6463, 0xade3f33e,
+ 0x9deeaa82, 0xadbd6a10,
+ 0x9e0effc1, 0xad96ed92, 0x9e2f641b, 0xad707dc8, 0x9e4fd78a, 0xad4a1aba,
+ 0x9e705a09, 0xad23c46e,
+ 0x9e90eb94, 0xacfd7ae8, 0x9eb18c26, 0xacd73e30, 0x9ed23bb9, 0xacb10e4b,
+ 0x9ef2fa49, 0xac8aeb3e,
+ 0x9f13c7d0, 0xac64d510, 0x9f34a449, 0xac3ecbc7, 0x9f558fb0, 0xac18cf69,
+ 0x9f7689ff, 0xabf2dffb,
+ 0x9f979331, 0xabccfd83, 0x9fb8ab41, 0xaba72807, 0x9fd9d22a, 0xab815f8d,
+ 0x9ffb07e7, 0xab5ba41a,
+ 0xa01c4c73, 0xab35f5b5, 0xa03d9fc8, 0xab105464, 0xa05f01e1, 0xaaeac02c,
+ 0xa08072ba, 0xaac53912,
+ 0xa0a1f24d, 0xaa9fbf1e, 0xa0c38095, 0xaa7a5253, 0xa0e51d8c, 0xaa54f2ba,
+ 0xa106c92f, 0xaa2fa056,
+ 0xa1288376, 0xaa0a5b2e, 0xa14a4c5e, 0xa9e52347, 0xa16c23e1, 0xa9bff8a8,
+ 0xa18e09fa, 0xa99adb56,
+ 0xa1affea3, 0xa975cb57, 0xa1d201d7, 0xa950c8b0, 0xa1f41392, 0xa92bd367,
+ 0xa21633cd, 0xa906eb82,
+ 0xa2386284, 0xa8e21106, 0xa25a9fb1, 0xa8bd43fa, 0xa27ceb4f, 0xa8988463,
+ 0xa29f4559, 0xa873d246,
+ 0xa2c1adc9, 0xa84f2daa, 0xa2e4249b, 0xa82a9693, 0xa306a9c8, 0xa8060d08,
+ 0xa3293d4b, 0xa7e1910f,
+ 0xa34bdf20, 0xa7bd22ac, 0xa36e8f41, 0xa798c1e5, 0xa3914da8, 0xa7746ec0,
+ 0xa3b41a50, 0xa7502943,
+ 0xa3d6f534, 0xa72bf174, 0xa3f9de4e, 0xa707c757, 0xa41cd599, 0xa6e3aaf2,
+ 0xa43fdb10, 0xa6bf9c4b,
+ 0xa462eeac, 0xa69b9b68, 0xa486106a, 0xa677a84e, 0xa4a94043, 0xa653c303,
+ 0xa4cc7e32, 0xa62feb8b,
+ 0xa4efca31, 0xa60c21ee, 0xa513243b, 0xa5e8662f, 0xa5368c4b, 0xa5c4b855,
+ 0xa55a025b, 0xa5a11866,
+ 0xa57d8666, 0xa57d8666, 0xa5a11866, 0xa55a025b, 0xa5c4b855, 0xa5368c4b,
+ 0xa5e8662f, 0xa513243b,
+ 0xa60c21ee, 0xa4efca31, 0xa62feb8b, 0xa4cc7e32, 0xa653c303, 0xa4a94043,
+ 0xa677a84e, 0xa486106a,
+ 0xa69b9b68, 0xa462eeac, 0xa6bf9c4b, 0xa43fdb10, 0xa6e3aaf2, 0xa41cd599,
+ 0xa707c757, 0xa3f9de4e,
+ 0xa72bf174, 0xa3d6f534, 0xa7502943, 0xa3b41a50, 0xa7746ec0, 0xa3914da8,
+ 0xa798c1e5, 0xa36e8f41,
+ 0xa7bd22ac, 0xa34bdf20, 0xa7e1910f, 0xa3293d4b, 0xa8060d08, 0xa306a9c8,
+ 0xa82a9693, 0xa2e4249b,
+ 0xa84f2daa, 0xa2c1adc9, 0xa873d246, 0xa29f4559, 0xa8988463, 0xa27ceb4f,
+ 0xa8bd43fa, 0xa25a9fb1,
+ 0xa8e21106, 0xa2386284, 0xa906eb82, 0xa21633cd, 0xa92bd367, 0xa1f41392,
+ 0xa950c8b0, 0xa1d201d7,
+ 0xa975cb57, 0xa1affea3, 0xa99adb56, 0xa18e09fa, 0xa9bff8a8, 0xa16c23e1,
+ 0xa9e52347, 0xa14a4c5e,
+ 0xaa0a5b2e, 0xa1288376, 0xaa2fa056, 0xa106c92f, 0xaa54f2ba, 0xa0e51d8c,
+ 0xaa7a5253, 0xa0c38095,
+ 0xaa9fbf1e, 0xa0a1f24d, 0xaac53912, 0xa08072ba, 0xaaeac02c, 0xa05f01e1,
+ 0xab105464, 0xa03d9fc8,
+ 0xab35f5b5, 0xa01c4c73, 0xab5ba41a, 0x9ffb07e7, 0xab815f8d, 0x9fd9d22a,
+ 0xaba72807, 0x9fb8ab41,
+ 0xabccfd83, 0x9f979331, 0xabf2dffb, 0x9f7689ff, 0xac18cf69, 0x9f558fb0,
+ 0xac3ecbc7, 0x9f34a449,
+ 0xac64d510, 0x9f13c7d0, 0xac8aeb3e, 0x9ef2fa49, 0xacb10e4b, 0x9ed23bb9,
+ 0xacd73e30, 0x9eb18c26,
+ 0xacfd7ae8, 0x9e90eb94, 0xad23c46e, 0x9e705a09, 0xad4a1aba, 0x9e4fd78a,
+ 0xad707dc8, 0x9e2f641b,
+ 0xad96ed92, 0x9e0effc1, 0xadbd6a10, 0x9deeaa82, 0xade3f33e, 0x9dce6463,
+ 0xae0a8916, 0x9dae2d68,
+ 0xae312b92, 0x9d8e0597, 0xae57daab, 0x9d6decf4, 0xae7e965b, 0x9d4de385,
+ 0xaea55e9e, 0x9d2de94d,
+ 0xaecc336c, 0x9d0dfe54, 0xaef314c0, 0x9cee229c, 0xaf1a0293, 0x9cce562c,
+ 0xaf40fce1, 0x9cae9907,
+ 0xaf6803a2, 0x9c8eeb34, 0xaf8f16d1, 0x9c6f4cb6, 0xafb63667, 0x9c4fbd93,
+ 0xafdd625f, 0x9c303dcf,
+ 0xb0049ab3, 0x9c10cd70, 0xb02bdf5c, 0x9bf16c7a, 0xb0533055, 0x9bd21af3,
+ 0xb07a8d97, 0x9bb2d8de,
+ 0xb0a1f71d, 0x9b93a641, 0xb0c96ce0, 0x9b748320, 0xb0f0eeda, 0x9b556f81,
+ 0xb1187d05, 0x9b366b68,
+ 0xb140175b, 0x9b1776da, 0xb167bdd7, 0x9af891db, 0xb18f7071, 0x9ad9bc71,
+ 0xb1b72f23, 0x9abaf6a1,
+ 0xb1def9e9, 0x9a9c406e, 0xb206d0ba, 0x9a7d99de, 0xb22eb392, 0x9a5f02f5,
+ 0xb256a26a, 0x9a407bb9,
+ 0xb27e9d3c, 0x9a22042d, 0xb2a6a402, 0x9a039c57, 0xb2ceb6b5, 0x99e5443b,
+ 0xb2f6d550, 0x99c6fbde,
+ 0xb31effcc, 0x99a8c345, 0xb3473623, 0x998a9a74, 0xb36f784f, 0x996c816f,
+ 0xb397c649, 0x994e783d,
+ 0xb3c0200c, 0x99307ee0, 0xb3e88592, 0x9912955f, 0xb410f6d3, 0x98f4bbbc,
+ 0xb43973ca, 0x98d6f1fe,
+ 0xb461fc70, 0x98b93828, 0xb48a90c0, 0x989b8e40, 0xb4b330b3, 0x987df449,
+ 0xb4dbdc42, 0x98606a49,
+ 0xb5049368, 0x9842f043, 0xb52d561e, 0x9825863d, 0xb556245e, 0x98082c3b,
+ 0xb57efe22, 0x97eae242,
+ 0xb5a7e362, 0x97cda855, 0xb5d0d41a, 0x97b07e7a, 0xb5f9d043, 0x979364b5,
+ 0xb622d7d6, 0x97765b0a,
+ 0xb64beacd, 0x9759617f, 0xb6750921, 0x973c7817, 0xb69e32cd, 0x971f9ed7,
+ 0xb6c767ca, 0x9702d5c3,
+ 0xb6f0a812, 0x96e61ce0, 0xb719f39e, 0x96c97432, 0xb7434a67, 0x96acdbbe,
+ 0xb76cac69, 0x96905388,
+ 0xb796199b, 0x9673db94, 0xb7bf91f8, 0x965773e7, 0xb7e9157a, 0x963b1c86,
+ 0xb812a41a, 0x961ed574,
+ 0xb83c3dd1, 0x96029eb6, 0xb865e299, 0x95e67850, 0xb88f926d, 0x95ca6247,
+ 0xb8b94d44, 0x95ae5c9f,
+ 0xb8e31319, 0x9592675c, 0xb90ce3e6, 0x95768283, 0xb936bfa4, 0x955aae17,
+ 0xb960a64c, 0x953eea1e,
+ 0xb98a97d8, 0x9523369c, 0xb9b49442, 0x95079394, 0xb9de9b83, 0x94ec010b,
+ 0xba08ad95, 0x94d07f05,
+ 0xba32ca71, 0x94b50d87, 0xba5cf210, 0x9499ac95, 0xba87246d, 0x947e5c33,
+ 0xbab16180, 0x94631c65,
+ 0xbadba943, 0x9447ed2f, 0xbb05fbb0, 0x942cce96, 0xbb3058c0, 0x9411c09e,
+ 0xbb5ac06d, 0x93f6c34a,
+ 0xbb8532b0, 0x93dbd6a0, 0xbbafaf82, 0x93c0faa3, 0xbbda36dd, 0x93a62f57,
+ 0xbc04c8ba, 0x938b74c1,
+ 0xbc2f6513, 0x9370cae4, 0xbc5a0be2, 0x935631c5, 0xbc84bd1f, 0x933ba968,
+ 0xbcaf78c4, 0x932131d1,
+ 0xbcda3ecb, 0x9306cb04, 0xbd050f2c, 0x92ec7505, 0xbd2fe9e2, 0x92d22fd9,
+ 0xbd5acee5, 0x92b7fb82,
+ 0xbd85be30, 0x929dd806, 0xbdb0b7bb, 0x9283c568, 0xbddbbb7f, 0x9269c3ac,
+ 0xbe06c977, 0x924fd2d7,
+ 0xbe31e19b, 0x9235f2ec, 0xbe5d03e6, 0x921c23ef, 0xbe88304f, 0x920265e4,
+ 0xbeb366d1, 0x91e8b8d0,
+ 0xbedea765, 0x91cf1cb6, 0xbf09f205, 0x91b5919a, 0xbf3546a8, 0x919c1781,
+ 0xbf60a54a, 0x9182ae6d,
+ 0xbf8c0de3, 0x91695663, 0xbfb7806c, 0x91500f67, 0xbfe2fcdf, 0x9136d97d,
+ 0xc00e8336, 0x911db4a9,
+ 0xc03a1368, 0x9104a0ee, 0xc065ad70, 0x90eb9e50, 0xc0915148, 0x90d2acd4,
+ 0xc0bcfee7, 0x90b9cc7d,
+ 0xc0e8b648, 0x90a0fd4e, 0xc1147764, 0x90883f4d, 0xc1404233, 0x906f927c,
+ 0xc16c16b0, 0x9056f6df,
+ 0xc197f4d4, 0x903e6c7b, 0xc1c3dc97, 0x9025f352, 0xc1efcdf3, 0x900d8b69,
+ 0xc21bc8e1, 0x8ff534c4,
+ 0xc247cd5a, 0x8fdcef66, 0xc273db58, 0x8fc4bb53, 0xc29ff2d4, 0x8fac988f,
+ 0xc2cc13c7, 0x8f94871d,
+ 0xc2f83e2a, 0x8f7c8701, 0xc32471f7, 0x8f649840, 0xc350af26, 0x8f4cbadb,
+ 0xc37cf5b0, 0x8f34eed8,
+ 0xc3a94590, 0x8f1d343a, 0xc3d59ebe, 0x8f058b04, 0xc4020133, 0x8eedf33b,
+ 0xc42e6ce8, 0x8ed66ce1,
+ 0xc45ae1d7, 0x8ebef7fb, 0xc4875ff9, 0x8ea7948c, 0xc4b3e746, 0x8e904298,
+ 0xc4e077b8, 0x8e790222,
+ 0xc50d1149, 0x8e61d32e, 0xc539b3f1, 0x8e4ab5bf, 0xc5665fa9, 0x8e33a9da,
+ 0xc593146a, 0x8e1caf80,
+ 0xc5bfd22e, 0x8e05c6b7, 0xc5ec98ee, 0x8deeef82, 0xc61968a2, 0x8dd829e4,
+ 0xc6464144, 0x8dc175e0,
+ 0xc67322ce, 0x8daad37b, 0xc6a00d37, 0x8d9442b8, 0xc6cd0079, 0x8d7dc399,
+ 0xc6f9fc8d, 0x8d675623,
+ 0xc727016d, 0x8d50fa59, 0xc7540f11, 0x8d3ab03f, 0xc7812572, 0x8d2477d8,
+ 0xc7ae4489, 0x8d0e5127,
+ 0xc7db6c50, 0x8cf83c30, 0xc8089cbf, 0x8ce238f6, 0xc835d5d0, 0x8ccc477d,
+ 0xc863177b, 0x8cb667c8,
+ 0xc89061ba, 0x8ca099da, 0xc8bdb485, 0x8c8addb7, 0xc8eb0fd6, 0x8c753362,
+ 0xc91873a5, 0x8c5f9ade,
+ 0xc945dfec, 0x8c4a142f, 0xc97354a4, 0x8c349f58, 0xc9a0d1c5, 0x8c1f3c5d,
+ 0xc9ce5748, 0x8c09eb40,
+ 0xc9fbe527, 0x8bf4ac05, 0xca297b5a, 0x8bdf7eb0, 0xca5719db, 0x8bca6343,
+ 0xca84c0a3, 0x8bb559c1,
+ 0xcab26fa9, 0x8ba0622f, 0xcae026e8, 0x8b8b7c8f, 0xcb0de658, 0x8b76a8e4,
+ 0xcb3badf3, 0x8b61e733,
+ 0xcb697db0, 0x8b4d377c, 0xcb97558a, 0x8b3899c6, 0xcbc53579, 0x8b240e11,
+ 0xcbf31d75, 0x8b0f9462,
+ 0xcc210d79, 0x8afb2cbb, 0xcc4f057c, 0x8ae6d720, 0xcc7d0578, 0x8ad29394,
+ 0xccab0d65, 0x8abe6219,
+ 0xccd91d3d, 0x8aaa42b4, 0xcd0734f9, 0x8a963567, 0xcd355491, 0x8a823a36,
+ 0xcd637bfe, 0x8a6e5123,
+ 0xcd91ab39, 0x8a5a7a31, 0xcdbfe23a, 0x8a46b564, 0xcdee20fc, 0x8a3302be,
+ 0xce1c6777, 0x8a1f6243,
+ 0xce4ab5a2, 0x8a0bd3f5, 0xce790b79, 0x89f857d8, 0xcea768f2, 0x89e4edef,
+ 0xced5ce08, 0x89d1963c,
+ 0xcf043ab3, 0x89be50c3, 0xcf32aeeb, 0x89ab1d87, 0xcf612aaa, 0x8997fc8a,
+ 0xcf8fade9, 0x8984edcf,
+ 0xcfbe389f, 0x8971f15a, 0xcfeccac7, 0x895f072e, 0xd01b6459, 0x894c2f4c,
+ 0xd04a054e, 0x893969b9,
+ 0xd078ad9e, 0x8926b677, 0xd0a75d42, 0x89141589, 0xd0d61434, 0x890186f2,
+ 0xd104d26b, 0x88ef0ab4,
+ 0xd13397e2, 0x88dca0d3, 0xd1626490, 0x88ca4951, 0xd191386e, 0x88b80432,
+ 0xd1c01375, 0x88a5d177,
+ 0xd1eef59e, 0x8893b125, 0xd21ddee2, 0x8881a33d, 0xd24ccf39, 0x886fa7c2,
+ 0xd27bc69c, 0x885dbeb8,
+ 0xd2aac504, 0x884be821, 0xd2d9ca6a, 0x883a23ff, 0xd308d6c7, 0x88287256,
+ 0xd337ea12, 0x8816d327,
+ 0xd3670446, 0x88054677, 0xd396255a, 0x87f3cc48, 0xd3c54d47, 0x87e2649b,
+ 0xd3f47c06, 0x87d10f75,
+ 0xd423b191, 0x87bfccd7, 0xd452eddf, 0x87ae9cc5, 0xd48230e9, 0x879d7f41,
+ 0xd4b17aa8, 0x878c744d,
+ 0xd4e0cb15, 0x877b7bec, 0xd5102228, 0x876a9621, 0xd53f7fda, 0x8759c2ef,
+ 0xd56ee424, 0x87490258,
+ 0xd59e4eff, 0x8738545e, 0xd5cdc062, 0x8727b905, 0xd5fd3848, 0x8717304e,
+ 0xd62cb6a8, 0x8706ba3d,
+ 0xd65c3b7b, 0x86f656d3, 0xd68bc6ba, 0x86e60614, 0xd6bb585e, 0x86d5c802,
+ 0xd6eaf05f, 0x86c59c9f,
+ 0xd71a8eb5, 0x86b583ee, 0xd74a335b, 0x86a57df2, 0xd779de47, 0x86958aac,
+ 0xd7a98f73, 0x8685aa20,
+ 0xd7d946d8, 0x8675dc4f, 0xd809046e, 0x8666213c, 0xd838c82d, 0x865678eb,
+ 0xd868920f, 0x8646e35c,
+ 0xd898620c, 0x86376092, 0xd8c8381d, 0x8627f091, 0xd8f81439, 0x86189359,
+ 0xd927f65b, 0x860948ef,
+ 0xd957de7a, 0x85fa1153, 0xd987cc90, 0x85eaec88, 0xd9b7c094, 0x85dbda91,
+ 0xd9e7ba7f, 0x85ccdb70,
+ 0xda17ba4a, 0x85bdef28, 0xda47bfee, 0x85af15b9, 0xda77cb63, 0x85a04f28,
+ 0xdaa7dca1, 0x85919b76,
+ 0xdad7f3a2, 0x8582faa5, 0xdb08105e, 0x85746cb8, 0xdb3832cd, 0x8565f1b0,
+ 0xdb685ae9, 0x85578991,
+ 0xdb9888a8, 0x8549345c, 0xdbc8bc06, 0x853af214, 0xdbf8f4f8, 0x852cc2bb,
+ 0xdc293379, 0x851ea652,
+ 0xdc597781, 0x85109cdd, 0xdc89c109, 0x8502a65c, 0xdcba1008, 0x84f4c2d4,
+ 0xdcea6478, 0x84e6f244,
+ 0xdd1abe51, 0x84d934b1, 0xdd4b1d8c, 0x84cb8a1b, 0xdd7b8220, 0x84bdf286,
+ 0xddabec08, 0x84b06df2,
+ 0xdddc5b3b, 0x84a2fc62, 0xde0ccfb1, 0x84959dd9, 0xde3d4964, 0x84885258,
+ 0xde6dc84b, 0x847b19e1,
+ 0xde9e4c60, 0x846df477, 0xdeced59b, 0x8460e21a, 0xdeff63f4, 0x8453e2cf,
+ 0xdf2ff764, 0x8446f695,
+ 0xdf608fe4, 0x843a1d70, 0xdf912d6b, 0x842d5762, 0xdfc1cff3, 0x8420a46c,
+ 0xdff27773, 0x84140490,
+ 0xe02323e5, 0x840777d0, 0xe053d541, 0x83fafe2e, 0xe0848b7f, 0x83ee97ad,
+ 0xe0b54698, 0x83e2444d,
+ 0xe0e60685, 0x83d60412, 0xe116cb3d, 0x83c9d6fc, 0xe14794ba, 0x83bdbd0e,
+ 0xe17862f3, 0x83b1b649,
+ 0xe1a935e2, 0x83a5c2b0, 0xe1da0d7e, 0x8399e244, 0xe20ae9c1, 0x838e1507,
+ 0xe23bcaa2, 0x83825afb,
+ 0xe26cb01b, 0x8376b422, 0xe29d9a23, 0x836b207d, 0xe2ce88b3, 0x835fa00f,
+ 0xe2ff7bc3, 0x835432d8,
+ 0xe330734d, 0x8348d8dc, 0xe3616f48, 0x833d921b, 0xe3926fad, 0x83325e97,
+ 0xe3c37474, 0x83273e52,
+ 0xe3f47d96, 0x831c314e, 0xe4258b0a, 0x8311378d, 0xe4569ccb, 0x83065110,
+ 0xe487b2d0, 0x82fb7dd8,
+ 0xe4b8cd11, 0x82f0bde8, 0xe4e9eb87, 0x82e61141, 0xe51b0e2a, 0x82db77e5,
+ 0xe54c34f3, 0x82d0f1d5,
+ 0xe57d5fda, 0x82c67f14, 0xe5ae8ed8, 0x82bc1fa2, 0xe5dfc1e5, 0x82b1d381,
+ 0xe610f8f9, 0x82a79ab3,
+ 0xe642340d, 0x829d753a, 0xe6737319, 0x82936317, 0xe6a4b616, 0x8289644b,
+ 0xe6d5fcfc, 0x827f78d8,
+ 0xe70747c4, 0x8275a0c0, 0xe7389665, 0x826bdc04, 0xe769e8d8, 0x82622aa6,
+ 0xe79b3f16, 0x82588ca7,
+ 0xe7cc9917, 0x824f0208, 0xe7fdf6d4, 0x82458acc, 0xe82f5844, 0x823c26f3,
+ 0xe860bd61, 0x8232d67f,
+ 0xe8922622, 0x82299971, 0xe8c39280, 0x82206fcc, 0xe8f50273, 0x82175990,
+ 0xe92675f4, 0x820e56be,
+ 0xe957ecfb, 0x82056758, 0xe9896781, 0x81fc8b60, 0xe9bae57d, 0x81f3c2d7,
+ 0xe9ec66e8, 0x81eb0dbe,
+ 0xea1debbb, 0x81e26c16, 0xea4f73ee, 0x81d9dde1, 0xea80ff7a, 0x81d16321,
+ 0xeab28e56, 0x81c8fbd6,
+ 0xeae4207a, 0x81c0a801, 0xeb15b5e1, 0x81b867a5, 0xeb474e81, 0x81b03ac2,
+ 0xeb78ea52, 0x81a82159,
+ 0xebaa894f, 0x81a01b6d, 0xebdc2b6e, 0x819828fd, 0xec0dd0a8, 0x81904a0c,
+ 0xec3f78f6, 0x81887e9a,
+ 0xec71244f, 0x8180c6a9, 0xeca2d2ad, 0x8179223a, 0xecd48407, 0x8171914e,
+ 0xed063856, 0x816a13e6,
+ 0xed37ef91, 0x8162aa04, 0xed69a9b3, 0x815b53a8, 0xed9b66b2, 0x815410d4,
+ 0xedcd2687, 0x814ce188,
+ 0xedfee92b, 0x8145c5c7, 0xee30ae96, 0x813ebd90, 0xee6276bf, 0x8137c8e6,
+ 0xee9441a0, 0x8130e7c9,
+ 0xeec60f31, 0x812a1a3a, 0xeef7df6a, 0x8123603a, 0xef29b243, 0x811cb9ca,
+ 0xef5b87b5, 0x811626ec,
+ 0xef8d5fb8, 0x810fa7a0, 0xefbf3a45, 0x81093be8, 0xeff11753, 0x8102e3c4,
+ 0xf022f6da, 0x80fc9f35,
+ 0xf054d8d5, 0x80f66e3c, 0xf086bd39, 0x80f050db, 0xf0b8a401, 0x80ea4712,
+ 0xf0ea8d24, 0x80e450e2,
+ 0xf11c789a, 0x80de6e4c, 0xf14e665c, 0x80d89f51, 0xf1805662, 0x80d2e3f2,
+ 0xf1b248a5, 0x80cd3c2f,
+ 0xf1e43d1c, 0x80c7a80a, 0xf21633c0, 0x80c22784, 0xf2482c8a, 0x80bcba9d,
+ 0xf27a2771, 0x80b76156,
+ 0xf2ac246e, 0x80b21baf, 0xf2de2379, 0x80ace9ab, 0xf310248a, 0x80a7cb49,
+ 0xf342279b, 0x80a2c08b,
+ 0xf3742ca2, 0x809dc971, 0xf3a63398, 0x8098e5fb, 0xf3d83c77, 0x8094162c,
+ 0xf40a4735, 0x808f5a02,
+ 0xf43c53cb, 0x808ab180, 0xf46e6231, 0x80861ca6, 0xf4a07261, 0x80819b74,
+ 0xf4d28451, 0x807d2dec,
+ 0xf50497fb, 0x8078d40d, 0xf536ad56, 0x80748dd9, 0xf568c45b, 0x80705b50,
+ 0xf59add02, 0x806c3c74,
+ 0xf5ccf743, 0x80683143, 0xf5ff1318, 0x806439c0, 0xf6313077, 0x806055eb,
+ 0xf6634f59, 0x805c85c4,
+ 0xf6956fb7, 0x8058c94c, 0xf6c79188, 0x80552084, 0xf6f9b4c6, 0x80518b6b,
+ 0xf72bd967, 0x804e0a04,
+ 0xf75dff66, 0x804a9c4d, 0xf79026b9, 0x80474248, 0xf7c24f59, 0x8043fbf6,
+ 0xf7f4793e, 0x8040c956,
+ 0xf826a462, 0x803daa6a, 0xf858d0bb, 0x803a9f31, 0xf88afe42, 0x8037a7ac,
+ 0xf8bd2cef, 0x8034c3dd,
+ 0xf8ef5cbb, 0x8031f3c2, 0xf9218d9e, 0x802f375d, 0xf953bf91, 0x802c8ead,
+ 0xf985f28a, 0x8029f9b4,
+ 0xf9b82684, 0x80277872, 0xf9ea5b75, 0x80250ae7, 0xfa1c9157, 0x8022b114,
+ 0xfa4ec821, 0x80206af8,
+ 0xfa80ffcb, 0x801e3895, 0xfab3384f, 0x801c19ea, 0xfae571a4, 0x801a0ef8,
+ 0xfb17abc2, 0x801817bf,
+ 0xfb49e6a3, 0x80163440, 0xfb7c223d, 0x8014647b, 0xfbae5e89, 0x8012a86f,
+ 0xfbe09b80, 0x8011001f,
+ 0xfc12d91a, 0x800f6b88, 0xfc45174e, 0x800deaad, 0xfc775616, 0x800c7d8c,
+ 0xfca9956a, 0x800b2427,
+ 0xfcdbd541, 0x8009de7e, 0xfd0e1594, 0x8008ac90, 0xfd40565c, 0x80078e5e,
+ 0xfd729790, 0x800683e8,
+ 0xfda4d929, 0x80058d2f, 0xfdd71b1e, 0x8004aa32, 0xfe095d69, 0x8003daf1,
+ 0xfe3ba002, 0x80031f6d,
+ 0xfe6de2e0, 0x800277a6, 0xfea025fd, 0x8001e39b, 0xfed2694f, 0x8001634e,
+ 0xff04acd0, 0x8000f6bd,
+ 0xff36f078, 0x80009dea, 0xff69343f, 0x800058d4, 0xff9b781d, 0x8000277a,
+ 0xffcdbc0b, 0x800009df,
+
+};
+
+
+/*
+* @brief Q15 Twiddle factors Table
+*/
+
+/**
+* \par
+* Example code for Q15 Twiddle factors Generation::
+* \par
+* <pre>for(i = 0; i< 3N/4; i++)
+* {
+* twiddleCoefQ15[2*i]= cos(i * 2*PI/(float)N);
+* twiddleCoefQ15[2*i+1]= sin(i * 2*PI/(float)N);
+* } </pre>
+* \par
+* where N = 4096 and PI = 3.14159265358979
+* \par
+* Cos and Sin values are interleaved fashion
+* \par
+* Convert Floating point to Q15(Fixed point 1.15):
+* round(twiddleCoefQ15(i) * pow(2, 15))
+*
+*/
+
+const q15_t ALIGN4 twiddleCoefQ15[6144] = {
+
+ 0x7fff, 0x0, 0x7fff, 0x32, 0x7fff, 0x65, 0x7fff, 0x97,
+ 0x7fff, 0xc9, 0x7fff, 0xfb, 0x7fff, 0x12e, 0x7ffe, 0x160,
+ 0x7ffe, 0x192, 0x7ffd, 0x1c4, 0x7ffc, 0x1f7, 0x7ffb, 0x229,
+ 0x7ffa, 0x25b, 0x7ff9, 0x28d, 0x7ff8, 0x2c0, 0x7ff7, 0x2f2,
+ 0x7ff6, 0x324, 0x7ff5, 0x356, 0x7ff4, 0x389, 0x7ff2, 0x3bb,
+ 0x7ff1, 0x3ed, 0x7fef, 0x41f, 0x7fed, 0x452, 0x7fec, 0x484,
+ 0x7fea, 0x4b6, 0x7fe8, 0x4e8, 0x7fe6, 0x51b, 0x7fe4, 0x54d,
+ 0x7fe2, 0x57f, 0x7fe0, 0x5b1, 0x7fdd, 0x5e3, 0x7fdb, 0x616,
+ 0x7fd9, 0x648, 0x7fd6, 0x67a, 0x7fd3, 0x6ac, 0x7fd1, 0x6de,
+ 0x7fce, 0x711, 0x7fcb, 0x743, 0x7fc8, 0x775, 0x7fc5, 0x7a7,
+ 0x7fc2, 0x7d9, 0x7fbf, 0x80c, 0x7fbc, 0x83e, 0x7fb9, 0x870,
+ 0x7fb5, 0x8a2, 0x7fb2, 0x8d4, 0x7fae, 0x906, 0x7fab, 0x938,
+ 0x7fa7, 0x96b, 0x7fa3, 0x99d, 0x7fa0, 0x9cf, 0x7f9c, 0xa01,
+ 0x7f98, 0xa33, 0x7f94, 0xa65, 0x7f90, 0xa97, 0x7f8b, 0xac9,
+ 0x7f87, 0xafb, 0x7f83, 0xb2d, 0x7f7e, 0xb60, 0x7f7a, 0xb92,
+ 0x7f75, 0xbc4, 0x7f71, 0xbf6, 0x7f6c, 0xc28, 0x7f67, 0xc5a,
+ 0x7f62, 0xc8c, 0x7f5d, 0xcbe, 0x7f58, 0xcf0, 0x7f53, 0xd22,
+ 0x7f4e, 0xd54, 0x7f49, 0xd86, 0x7f43, 0xdb8, 0x7f3e, 0xdea,
+ 0x7f38, 0xe1c, 0x7f33, 0xe4e, 0x7f2d, 0xe80, 0x7f27, 0xeb2,
+ 0x7f22, 0xee4, 0x7f1c, 0xf15, 0x7f16, 0xf47, 0x7f10, 0xf79,
+ 0x7f0a, 0xfab, 0x7f03, 0xfdd, 0x7efd, 0x100f, 0x7ef7, 0x1041,
+ 0x7ef0, 0x1073, 0x7eea, 0x10a4, 0x7ee3, 0x10d6, 0x7edd, 0x1108,
+ 0x7ed6, 0x113a, 0x7ecf, 0x116c, 0x7ec8, 0x119e, 0x7ec1, 0x11cf,
+ 0x7eba, 0x1201, 0x7eb3, 0x1233, 0x7eac, 0x1265, 0x7ea5, 0x1296,
+ 0x7e9d, 0x12c8, 0x7e96, 0x12fa, 0x7e8e, 0x132b, 0x7e87, 0x135d,
+ 0x7e7f, 0x138f, 0x7e78, 0x13c1, 0x7e70, 0x13f2, 0x7e68, 0x1424,
+ 0x7e60, 0x1455, 0x7e58, 0x1487, 0x7e50, 0x14b9, 0x7e48, 0x14ea,
+ 0x7e3f, 0x151c, 0x7e37, 0x154d, 0x7e2f, 0x157f, 0x7e26, 0x15b1,
+ 0x7e1e, 0x15e2, 0x7e15, 0x1614, 0x7e0c, 0x1645, 0x7e03, 0x1677,
+ 0x7dfb, 0x16a8, 0x7df2, 0x16da, 0x7de9, 0x170b, 0x7de0, 0x173c,
+ 0x7dd6, 0x176e, 0x7dcd, 0x179f, 0x7dc4, 0x17d1, 0x7dba, 0x1802,
+ 0x7db1, 0x1833, 0x7da7, 0x1865, 0x7d9e, 0x1896, 0x7d94, 0x18c7,
+ 0x7d8a, 0x18f9, 0x7d81, 0x192a, 0x7d77, 0x195b, 0x7d6d, 0x198d,
+ 0x7d63, 0x19be, 0x7d58, 0x19ef, 0x7d4e, 0x1a20, 0x7d44, 0x1a51,
+ 0x7d3a, 0x1a83, 0x7d2f, 0x1ab4, 0x7d25, 0x1ae5, 0x7d1a, 0x1b16,
+ 0x7d0f, 0x1b47, 0x7d05, 0x1b78, 0x7cfa, 0x1ba9, 0x7cef, 0x1bda,
+ 0x7ce4, 0x1c0c, 0x7cd9, 0x1c3d, 0x7cce, 0x1c6e, 0x7cc2, 0x1c9f,
+ 0x7cb7, 0x1cd0, 0x7cac, 0x1d01, 0x7ca0, 0x1d31, 0x7c95, 0x1d62,
+ 0x7c89, 0x1d93, 0x7c7e, 0x1dc4, 0x7c72, 0x1df5, 0x7c66, 0x1e26,
+ 0x7c5a, 0x1e57, 0x7c4e, 0x1e88, 0x7c42, 0x1eb8, 0x7c36, 0x1ee9,
+ 0x7c2a, 0x1f1a, 0x7c1e, 0x1f4b, 0x7c11, 0x1f7b, 0x7c05, 0x1fac,
+ 0x7bf9, 0x1fdd, 0x7bec, 0x200e, 0x7bdf, 0x203e, 0x7bd3, 0x206f,
+ 0x7bc6, 0x209f, 0x7bb9, 0x20d0, 0x7bac, 0x2101, 0x7b9f, 0x2131,
+ 0x7b92, 0x2162, 0x7b85, 0x2192, 0x7b78, 0x21c3, 0x7b6a, 0x21f3,
+ 0x7b5d, 0x2224, 0x7b50, 0x2254, 0x7b42, 0x2284, 0x7b34, 0x22b5,
+ 0x7b27, 0x22e5, 0x7b19, 0x2316, 0x7b0b, 0x2346, 0x7afd, 0x2376,
+ 0x7aef, 0x23a7, 0x7ae1, 0x23d7, 0x7ad3, 0x2407, 0x7ac5, 0x2437,
+ 0x7ab7, 0x2467, 0x7aa8, 0x2498, 0x7a9a, 0x24c8, 0x7a8c, 0x24f8,
+ 0x7a7d, 0x2528, 0x7a6e, 0x2558, 0x7a60, 0x2588, 0x7a51, 0x25b8,
+ 0x7a42, 0x25e8, 0x7a33, 0x2618, 0x7a24, 0x2648, 0x7a15, 0x2678,
+ 0x7a06, 0x26a8, 0x79f7, 0x26d8, 0x79e7, 0x2708, 0x79d8, 0x2738,
+ 0x79c9, 0x2768, 0x79b9, 0x2797, 0x79aa, 0x27c7, 0x799a, 0x27f7,
+ 0x798a, 0x2827, 0x797a, 0x2856, 0x796a, 0x2886, 0x795b, 0x28b6,
+ 0x794a, 0x28e5, 0x793a, 0x2915, 0x792a, 0x2945, 0x791a, 0x2974,
+ 0x790a, 0x29a4, 0x78f9, 0x29d3, 0x78e9, 0x2a03, 0x78d8, 0x2a32,
+ 0x78c8, 0x2a62, 0x78b7, 0x2a91, 0x78a6, 0x2ac1, 0x7895, 0x2af0,
+ 0x7885, 0x2b1f, 0x7874, 0x2b4f, 0x7863, 0x2b7e, 0x7851, 0x2bad,
+ 0x7840, 0x2bdc, 0x782f, 0x2c0c, 0x781e, 0x2c3b, 0x780c, 0x2c6a,
+ 0x77fb, 0x2c99, 0x77e9, 0x2cc8, 0x77d8, 0x2cf7, 0x77c6, 0x2d26,
+ 0x77b4, 0x2d55, 0x77a2, 0x2d84, 0x7790, 0x2db3, 0x777e, 0x2de2,
+ 0x776c, 0x2e11, 0x775a, 0x2e40, 0x7748, 0x2e6f, 0x7736, 0x2e9e,
+ 0x7723, 0x2ecc, 0x7711, 0x2efb, 0x76fe, 0x2f2a, 0x76ec, 0x2f59,
+ 0x76d9, 0x2f87, 0x76c7, 0x2fb6, 0x76b4, 0x2fe5, 0x76a1, 0x3013,
+ 0x768e, 0x3042, 0x767b, 0x3070, 0x7668, 0x309f, 0x7655, 0x30cd,
+ 0x7642, 0x30fc, 0x762e, 0x312a, 0x761b, 0x3159, 0x7608, 0x3187,
+ 0x75f4, 0x31b5, 0x75e1, 0x31e4, 0x75cd, 0x3212, 0x75b9, 0x3240,
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+ 0x12c8, 0x7e9d, 0x1296, 0x7ea5, 0x1265, 0x7eac, 0x1233, 0x7eb3,
+ 0x1201, 0x7eba, 0x11cf, 0x7ec1, 0x119e, 0x7ec8, 0x116c, 0x7ecf,
+ 0x113a, 0x7ed6, 0x1108, 0x7edd, 0x10d6, 0x7ee3, 0x10a4, 0x7eea,
+ 0x1073, 0x7ef0, 0x1041, 0x7ef7, 0x100f, 0x7efd, 0xfdd, 0x7f03,
+ 0xfab, 0x7f0a, 0xf79, 0x7f10, 0xf47, 0x7f16, 0xf15, 0x7f1c,
+ 0xee4, 0x7f22, 0xeb2, 0x7f27, 0xe80, 0x7f2d, 0xe4e, 0x7f33,
+ 0xe1c, 0x7f38, 0xdea, 0x7f3e, 0xdb8, 0x7f43, 0xd86, 0x7f49,
+ 0xd54, 0x7f4e, 0xd22, 0x7f53, 0xcf0, 0x7f58, 0xcbe, 0x7f5d,
+ 0xc8c, 0x7f62, 0xc5a, 0x7f67, 0xc28, 0x7f6c, 0xbf6, 0x7f71,
+ 0xbc4, 0x7f75, 0xb92, 0x7f7a, 0xb60, 0x7f7e, 0xb2d, 0x7f83,
+ 0xafb, 0x7f87, 0xac9, 0x7f8b, 0xa97, 0x7f90, 0xa65, 0x7f94,
+ 0xa33, 0x7f98, 0xa01, 0x7f9c, 0x9cf, 0x7fa0, 0x99d, 0x7fa3,
+ 0x96b, 0x7fa7, 0x938, 0x7fab, 0x906, 0x7fae, 0x8d4, 0x7fb2,
+ 0x8a2, 0x7fb5, 0x870, 0x7fb9, 0x83e, 0x7fbc, 0x80c, 0x7fbf,
+ 0x7d9, 0x7fc2, 0x7a7, 0x7fc5, 0x775, 0x7fc8, 0x743, 0x7fcb,
+ 0x711, 0x7fce, 0x6de, 0x7fd1, 0x6ac, 0x7fd3, 0x67a, 0x7fd6,
+ 0x648, 0x7fd9, 0x616, 0x7fdb, 0x5e3, 0x7fdd, 0x5b1, 0x7fe0,
+ 0x57f, 0x7fe2, 0x54d, 0x7fe4, 0x51b, 0x7fe6, 0x4e8, 0x7fe8,
+ 0x4b6, 0x7fea, 0x484, 0x7fec, 0x452, 0x7fed, 0x41f, 0x7fef,
+ 0x3ed, 0x7ff1, 0x3bb, 0x7ff2, 0x389, 0x7ff4, 0x356, 0x7ff5,
+ 0x324, 0x7ff6, 0x2f2, 0x7ff7, 0x2c0, 0x7ff8, 0x28d, 0x7ff9,
+ 0x25b, 0x7ffa, 0x229, 0x7ffb, 0x1f7, 0x7ffc, 0x1c4, 0x7ffd,
+ 0x192, 0x7ffe, 0x160, 0x7ffe, 0x12e, 0x7fff, 0xfb, 0x7fff,
+ 0xc9, 0x7fff, 0x97, 0x7fff, 0x65, 0x7fff, 0x32, 0x7fff,
+ 0x0, 0x7fff, 0xffce, 0x7fff, 0xff9b, 0x7fff, 0xff69, 0x7fff,
+ 0xff37, 0x7fff, 0xff05, 0x7fff, 0xfed2, 0x7fff, 0xfea0, 0x7ffe,
+ 0xfe6e, 0x7ffe, 0xfe3c, 0x7ffd, 0xfe09, 0x7ffc, 0xfdd7, 0x7ffb,
+ 0xfda5, 0x7ffa, 0xfd73, 0x7ff9, 0xfd40, 0x7ff8, 0xfd0e, 0x7ff7,
+ 0xfcdc, 0x7ff6, 0xfcaa, 0x7ff5, 0xfc77, 0x7ff4, 0xfc45, 0x7ff2,
+ 0xfc13, 0x7ff1, 0xfbe1, 0x7fef, 0xfbae, 0x7fed, 0xfb7c, 0x7fec,
+ 0xfb4a, 0x7fea, 0xfb18, 0x7fe8, 0xfae5, 0x7fe6, 0xfab3, 0x7fe4,
+ 0xfa81, 0x7fe2, 0xfa4f, 0x7fe0, 0xfa1d, 0x7fdd, 0xf9ea, 0x7fdb,
+ 0xf9b8, 0x7fd9, 0xf986, 0x7fd6, 0xf954, 0x7fd3, 0xf922, 0x7fd1,
+ 0xf8ef, 0x7fce, 0xf8bd, 0x7fcb, 0xf88b, 0x7fc8, 0xf859, 0x7fc5,
+ 0xf827, 0x7fc2, 0xf7f4, 0x7fbf, 0xf7c2, 0x7fbc, 0xf790, 0x7fb9,
+ 0xf75e, 0x7fb5, 0xf72c, 0x7fb2, 0xf6fa, 0x7fae, 0xf6c8, 0x7fab,
+ 0xf695, 0x7fa7, 0xf663, 0x7fa3, 0xf631, 0x7fa0, 0xf5ff, 0x7f9c,
+ 0xf5cd, 0x7f98, 0xf59b, 0x7f94, 0xf569, 0x7f90, 0xf537, 0x7f8b,
+ 0xf505, 0x7f87, 0xf4d3, 0x7f83, 0xf4a0, 0x7f7e, 0xf46e, 0x7f7a,
+ 0xf43c, 0x7f75, 0xf40a, 0x7f71, 0xf3d8, 0x7f6c, 0xf3a6, 0x7f67,
+ 0xf374, 0x7f62, 0xf342, 0x7f5d, 0xf310, 0x7f58, 0xf2de, 0x7f53,
+ 0xf2ac, 0x7f4e, 0xf27a, 0x7f49, 0xf248, 0x7f43, 0xf216, 0x7f3e,
+ 0xf1e4, 0x7f38, 0xf1b2, 0x7f33, 0xf180, 0x7f2d, 0xf14e, 0x7f27,
+ 0xf11c, 0x7f22, 0xf0eb, 0x7f1c, 0xf0b9, 0x7f16, 0xf087, 0x7f10,
+ 0xf055, 0x7f0a, 0xf023, 0x7f03, 0xeff1, 0x7efd, 0xefbf, 0x7ef7,
+ 0xef8d, 0x7ef0, 0xef5c, 0x7eea, 0xef2a, 0x7ee3, 0xeef8, 0x7edd,
+ 0xeec6, 0x7ed6, 0xee94, 0x7ecf, 0xee62, 0x7ec8, 0xee31, 0x7ec1,
+ 0xedff, 0x7eba, 0xedcd, 0x7eb3, 0xed9b, 0x7eac, 0xed6a, 0x7ea5,
+ 0xed38, 0x7e9d, 0xed06, 0x7e96, 0xecd5, 0x7e8e, 0xeca3, 0x7e87,
+ 0xec71, 0x7e7f, 0xec3f, 0x7e78, 0xec0e, 0x7e70, 0xebdc, 0x7e68,
+ 0xebab, 0x7e60, 0xeb79, 0x7e58, 0xeb47, 0x7e50, 0xeb16, 0x7e48,
+ 0xeae4, 0x7e3f, 0xeab3, 0x7e37, 0xea81, 0x7e2f, 0xea4f, 0x7e26,
+ 0xea1e, 0x7e1e, 0xe9ec, 0x7e15, 0xe9bb, 0x7e0c, 0xe989, 0x7e03,
+ 0xe958, 0x7dfb, 0xe926, 0x7df2, 0xe8f5, 0x7de9, 0xe8c4, 0x7de0,
+ 0xe892, 0x7dd6, 0xe861, 0x7dcd, 0xe82f, 0x7dc4, 0xe7fe, 0x7dba,
+ 0xe7cd, 0x7db1, 0xe79b, 0x7da7, 0xe76a, 0x7d9e, 0xe739, 0x7d94,
+ 0xe707, 0x7d8a, 0xe6d6, 0x7d81, 0xe6a5, 0x7d77, 0xe673, 0x7d6d,
+ 0xe642, 0x7d63, 0xe611, 0x7d58, 0xe5e0, 0x7d4e, 0xe5af, 0x7d44,
+ 0xe57d, 0x7d3a, 0xe54c, 0x7d2f, 0xe51b, 0x7d25, 0xe4ea, 0x7d1a,
+ 0xe4b9, 0x7d0f, 0xe488, 0x7d05, 0xe457, 0x7cfa, 0xe426, 0x7cef,
+ 0xe3f4, 0x7ce4, 0xe3c3, 0x7cd9, 0xe392, 0x7cce, 0xe361, 0x7cc2,
+ 0xe330, 0x7cb7, 0xe2ff, 0x7cac, 0xe2cf, 0x7ca0, 0xe29e, 0x7c95,
+ 0xe26d, 0x7c89, 0xe23c, 0x7c7e, 0xe20b, 0x7c72, 0xe1da, 0x7c66,
+ 0xe1a9, 0x7c5a, 0xe178, 0x7c4e, 0xe148, 0x7c42, 0xe117, 0x7c36,
+ 0xe0e6, 0x7c2a, 0xe0b5, 0x7c1e, 0xe085, 0x7c11, 0xe054, 0x7c05,
+ 0xe023, 0x7bf9, 0xdff2, 0x7bec, 0xdfc2, 0x7bdf, 0xdf91, 0x7bd3,
+ 0xdf61, 0x7bc6, 0xdf30, 0x7bb9, 0xdeff, 0x7bac, 0xdecf, 0x7b9f,
+ 0xde9e, 0x7b92, 0xde6e, 0x7b85, 0xde3d, 0x7b78, 0xde0d, 0x7b6a,
+ 0xdddc, 0x7b5d, 0xddac, 0x7b50, 0xdd7c, 0x7b42, 0xdd4b, 0x7b34,
+ 0xdd1b, 0x7b27, 0xdcea, 0x7b19, 0xdcba, 0x7b0b, 0xdc8a, 0x7afd,
+ 0xdc59, 0x7aef, 0xdc29, 0x7ae1, 0xdbf9, 0x7ad3, 0xdbc9, 0x7ac5,
+ 0xdb99, 0x7ab7, 0xdb68, 0x7aa8, 0xdb38, 0x7a9a, 0xdb08, 0x7a8c,
+ 0xdad8, 0x7a7d, 0xdaa8, 0x7a6e, 0xda78, 0x7a60, 0xda48, 0x7a51,
+ 0xda18, 0x7a42, 0xd9e8, 0x7a33, 0xd9b8, 0x7a24, 0xd988, 0x7a15,
+ 0xd958, 0x7a06, 0xd928, 0x79f7, 0xd8f8, 0x79e7, 0xd8c8, 0x79d8,
+ 0xd898, 0x79c9, 0xd869, 0x79b9, 0xd839, 0x79aa, 0xd809, 0x799a,
+ 0xd7d9, 0x798a, 0xd7aa, 0x797a, 0xd77a, 0x796a, 0xd74a, 0x795b,
+ 0xd71b, 0x794a, 0xd6eb, 0x793a, 0xd6bb, 0x792a, 0xd68c, 0x791a,
+ 0xd65c, 0x790a, 0xd62d, 0x78f9, 0xd5fd, 0x78e9, 0xd5ce, 0x78d8,
+ 0xd59e, 0x78c8, 0xd56f, 0x78b7, 0xd53f, 0x78a6, 0xd510, 0x7895,
+ 0xd4e1, 0x7885, 0xd4b1, 0x7874, 0xd482, 0x7863, 0xd453, 0x7851,
+ 0xd424, 0x7840, 0xd3f4, 0x782f, 0xd3c5, 0x781e, 0xd396, 0x780c,
+ 0xd367, 0x77fb, 0xd338, 0x77e9, 0xd309, 0x77d8, 0xd2da, 0x77c6,
+ 0xd2ab, 0x77b4, 0xd27c, 0x77a2, 0xd24d, 0x7790, 0xd21e, 0x777e,
+ 0xd1ef, 0x776c, 0xd1c0, 0x775a, 0xd191, 0x7748, 0xd162, 0x7736,
+ 0xd134, 0x7723, 0xd105, 0x7711, 0xd0d6, 0x76fe, 0xd0a7, 0x76ec,
+ 0xd079, 0x76d9, 0xd04a, 0x76c7, 0xd01b, 0x76b4, 0xcfed, 0x76a1,
+ 0xcfbe, 0x768e, 0xcf90, 0x767b, 0xcf61, 0x7668, 0xcf33, 0x7655,
+ 0xcf04, 0x7642, 0xced6, 0x762e, 0xcea7, 0x761b, 0xce79, 0x7608,
+ 0xce4b, 0x75f4, 0xce1c, 0x75e1, 0xcdee, 0x75cd, 0xcdc0, 0x75b9,
+ 0xcd92, 0x75a6, 0xcd63, 0x7592, 0xcd35, 0x757e, 0xcd07, 0x756a,
+ 0xccd9, 0x7556, 0xccab, 0x7542, 0xcc7d, 0x752d, 0xcc4f, 0x7519,
+ 0xcc21, 0x7505, 0xcbf3, 0x74f0, 0xcbc5, 0x74dc, 0xcb97, 0x74c7,
+ 0xcb69, 0x74b3, 0xcb3c, 0x749e, 0xcb0e, 0x7489, 0xcae0, 0x7475,
+ 0xcab2, 0x7460, 0xca85, 0x744b, 0xca57, 0x7436, 0xca29, 0x7421,
+ 0xc9fc, 0x740b, 0xc9ce, 0x73f6, 0xc9a1, 0x73e1, 0xc973, 0x73cb,
+ 0xc946, 0x73b6, 0xc918, 0x73a0, 0xc8eb, 0x738b, 0xc8be, 0x7375,
+ 0xc890, 0x735f, 0xc863, 0x734a, 0xc836, 0x7334, 0xc809, 0x731e,
+ 0xc7db, 0x7308, 0xc7ae, 0x72f2, 0xc781, 0x72dc, 0xc754, 0x72c5,
+ 0xc727, 0x72af, 0xc6fa, 0x7299, 0xc6cd, 0x7282, 0xc6a0, 0x726c,
+ 0xc673, 0x7255, 0xc646, 0x723f, 0xc619, 0x7228, 0xc5ed, 0x7211,
+ 0xc5c0, 0x71fa, 0xc593, 0x71e3, 0xc566, 0x71cc, 0xc53a, 0x71b5,
+ 0xc50d, 0x719e, 0xc4e0, 0x7187, 0xc4b4, 0x7170, 0xc487, 0x7158,
+ 0xc45b, 0x7141, 0xc42e, 0x712a, 0xc402, 0x7112, 0xc3d6, 0x70fa,
+ 0xc3a9, 0x70e3, 0xc37d, 0x70cb, 0xc351, 0x70b3, 0xc324, 0x709b,
+ 0xc2f8, 0x7083, 0xc2cc, 0x706b, 0xc2a0, 0x7053, 0xc274, 0x703b,
+ 0xc248, 0x7023, 0xc21c, 0x700b, 0xc1f0, 0x6ff2, 0xc1c4, 0x6fda,
+ 0xc198, 0x6fc2, 0xc16c, 0x6fa9, 0xc140, 0x6f90, 0xc114, 0x6f78,
+ 0xc0e9, 0x6f5f, 0xc0bd, 0x6f46, 0xc091, 0x6f2d, 0xc066, 0x6f14,
+ 0xc03a, 0x6efb, 0xc00f, 0x6ee2, 0xbfe3, 0x6ec9, 0xbfb8, 0x6eb0,
+ 0xbf8c, 0x6e97, 0xbf61, 0x6e7d, 0xbf35, 0x6e64, 0xbf0a, 0x6e4a,
+ 0xbedf, 0x6e31, 0xbeb3, 0x6e17, 0xbe88, 0x6dfe, 0xbe5d, 0x6de4,
+ 0xbe32, 0x6dca, 0xbe07, 0x6db0, 0xbddc, 0x6d96, 0xbdb1, 0x6d7c,
+ 0xbd86, 0x6d62, 0xbd5b, 0x6d48, 0xbd30, 0x6d2e, 0xbd05, 0x6d14,
+ 0xbcda, 0x6cf9, 0xbcaf, 0x6cdf, 0xbc85, 0x6cc4, 0xbc5a, 0x6caa,
+ 0xbc2f, 0x6c8f, 0xbc05, 0x6c75, 0xbbda, 0x6c5a, 0xbbb0, 0x6c3f,
+ 0xbb85, 0x6c24, 0xbb5b, 0x6c09, 0xbb30, 0x6bee, 0xbb06, 0x6bd3,
+ 0xbadc, 0x6bb8, 0xbab1, 0x6b9d, 0xba87, 0x6b82, 0xba5d, 0x6b66,
+ 0xba33, 0x6b4b, 0xba09, 0x6b30, 0xb9df, 0x6b14, 0xb9b5, 0x6af8,
+ 0xb98b, 0x6add, 0xb961, 0x6ac1, 0xb937, 0x6aa5, 0xb90d, 0x6a89,
+ 0xb8e3, 0x6a6e, 0xb8b9, 0x6a52, 0xb890, 0x6a36, 0xb866, 0x6a1a,
+ 0xb83c, 0x69fd, 0xb813, 0x69e1, 0xb7e9, 0x69c5, 0xb7c0, 0x69a9,
+ 0xb796, 0x698c, 0xb76d, 0x6970, 0xb743, 0x6953, 0xb71a, 0x6937,
+ 0xb6f1, 0x691a, 0xb6c7, 0x68fd, 0xb69e, 0x68e0, 0xb675, 0x68c4,
+ 0xb64c, 0x68a7, 0xb623, 0x688a, 0xb5fa, 0x686d, 0xb5d1, 0x6850,
+ 0xb5a8, 0x6832, 0xb57f, 0x6815, 0xb556, 0x67f8, 0xb52d, 0x67da,
+ 0xb505, 0x67bd, 0xb4dc, 0x67a0, 0xb4b3, 0x6782, 0xb48b, 0x6764,
+ 0xb462, 0x6747, 0xb439, 0x6729, 0xb411, 0x670b, 0xb3e9, 0x66ed,
+ 0xb3c0, 0x66d0, 0xb398, 0x66b2, 0xb36f, 0x6693, 0xb347, 0x6675,
+ 0xb31f, 0x6657, 0xb2f7, 0x6639, 0xb2cf, 0x661b, 0xb2a7, 0x65fc,
+ 0xb27f, 0x65de, 0xb257, 0x65c0, 0xb22f, 0x65a1, 0xb207, 0x6582,
+ 0xb1df, 0x6564, 0xb1b7, 0x6545, 0xb18f, 0x6526, 0xb168, 0x6507,
+ 0xb140, 0x64e9, 0xb118, 0x64ca, 0xb0f1, 0x64ab, 0xb0c9, 0x648b,
+ 0xb0a2, 0x646c, 0xb07b, 0x644d, 0xb053, 0x642e, 0xb02c, 0x640f,
+ 0xb005, 0x63ef, 0xafdd, 0x63d0, 0xafb6, 0x63b0, 0xaf8f, 0x6391,
+ 0xaf68, 0x6371, 0xaf41, 0x6351, 0xaf1a, 0x6332, 0xaef3, 0x6312,
+ 0xaecc, 0x62f2, 0xaea5, 0x62d2, 0xae7f, 0x62b2, 0xae58, 0x6292,
+ 0xae31, 0x6272, 0xae0b, 0x6252, 0xade4, 0x6232, 0xadbd, 0x6211,
+ 0xad97, 0x61f1, 0xad70, 0x61d1, 0xad4a, 0x61b0, 0xad24, 0x6190,
+ 0xacfd, 0x616f, 0xacd7, 0x614e, 0xacb1, 0x612e, 0xac8b, 0x610d,
+ 0xac65, 0x60ec, 0xac3f, 0x60cb, 0xac19, 0x60aa, 0xabf3, 0x6089,
+ 0xabcd, 0x6068, 0xaba7, 0x6047, 0xab81, 0x6026, 0xab5c, 0x6005,
+ 0xab36, 0x5fe4, 0xab10, 0x5fc2, 0xaaeb, 0x5fa1, 0xaac5, 0x5f80,
+ 0xaaa0, 0x5f5e, 0xaa7a, 0x5f3c, 0xaa55, 0x5f1b, 0xaa30, 0x5ef9,
+ 0xaa0a, 0x5ed7, 0xa9e5, 0x5eb6, 0xa9c0, 0x5e94, 0xa99b, 0x5e72,
+ 0xa976, 0x5e50, 0xa951, 0x5e2e, 0xa92c, 0x5e0c, 0xa907, 0x5dea,
+ 0xa8e2, 0x5dc8, 0xa8bd, 0x5da5, 0xa899, 0x5d83, 0xa874, 0x5d61,
+ 0xa84f, 0x5d3e, 0xa82b, 0x5d1c, 0xa806, 0x5cf9, 0xa7e2, 0x5cd7,
+ 0xa7bd, 0x5cb4, 0xa799, 0x5c91, 0xa774, 0x5c6f, 0xa750, 0x5c4c,
+ 0xa72c, 0x5c29, 0xa708, 0x5c06, 0xa6e4, 0x5be3, 0xa6c0, 0x5bc0,
+ 0xa69c, 0x5b9d, 0xa678, 0x5b7a, 0xa654, 0x5b57, 0xa630, 0x5b34,
+ 0xa60c, 0x5b10, 0xa5e8, 0x5aed, 0xa5c5, 0x5ac9, 0xa5a1, 0x5aa6,
+ 0xa57e, 0x5a82, 0xa55a, 0x5a5f, 0xa537, 0x5a3b, 0xa513, 0x5a18,
+ 0xa4f0, 0x59f4, 0xa4cc, 0x59d0, 0xa4a9, 0x59ac, 0xa486, 0x5988,
+ 0xa463, 0x5964, 0xa440, 0x5940, 0xa41d, 0x591c, 0xa3fa, 0x58f8,
+ 0xa3d7, 0x58d4, 0xa3b4, 0x58b0, 0xa391, 0x588c, 0xa36f, 0x5867,
+ 0xa34c, 0x5843, 0xa329, 0x581e, 0xa307, 0x57fa, 0xa2e4, 0x57d5,
+ 0xa2c2, 0x57b1, 0xa29f, 0x578c, 0xa27d, 0x5767, 0xa25b, 0x5743,
+ 0xa238, 0x571e, 0xa216, 0x56f9, 0xa1f4, 0x56d4, 0xa1d2, 0x56af,
+ 0xa1b0, 0x568a, 0xa18e, 0x5665, 0xa16c, 0x5640, 0xa14a, 0x561b,
+ 0xa129, 0x55f6, 0xa107, 0x55d0, 0xa0e5, 0x55ab, 0xa0c4, 0x5586,
+ 0xa0a2, 0x5560, 0xa080, 0x553b, 0xa05f, 0x5515, 0xa03e, 0x54f0,
+ 0xa01c, 0x54ca, 0x9ffb, 0x54a4, 0x9fda, 0x547f, 0x9fb9, 0x5459,
+ 0x9f98, 0x5433, 0x9f77, 0x540d, 0x9f56, 0x53e7, 0x9f35, 0x53c1,
+ 0x9f14, 0x539b, 0x9ef3, 0x5375, 0x9ed2, 0x534f, 0x9eb2, 0x5329,
+ 0x9e91, 0x5303, 0x9e70, 0x52dc, 0x9e50, 0x52b6, 0x9e2f, 0x5290,
+ 0x9e0f, 0x5269, 0x9def, 0x5243, 0x9dce, 0x521c, 0x9dae, 0x51f5,
+ 0x9d8e, 0x51cf, 0x9d6e, 0x51a8, 0x9d4e, 0x5181, 0x9d2e, 0x515b,
+ 0x9d0e, 0x5134, 0x9cee, 0x510d, 0x9cce, 0x50e6, 0x9caf, 0x50bf,
+ 0x9c8f, 0x5098, 0x9c6f, 0x5071, 0x9c50, 0x504a, 0x9c30, 0x5023,
+ 0x9c11, 0x4ffb, 0x9bf1, 0x4fd4, 0x9bd2, 0x4fad, 0x9bb3, 0x4f85,
+ 0x9b94, 0x4f5e, 0x9b75, 0x4f37, 0x9b55, 0x4f0f, 0x9b36, 0x4ee8,
+ 0x9b17, 0x4ec0, 0x9af9, 0x4e98, 0x9ada, 0x4e71, 0x9abb, 0x4e49,
+ 0x9a9c, 0x4e21, 0x9a7e, 0x4df9, 0x9a5f, 0x4dd1, 0x9a40, 0x4da9,
+ 0x9a22, 0x4d81, 0x9a04, 0x4d59, 0x99e5, 0x4d31, 0x99c7, 0x4d09,
+ 0x99a9, 0x4ce1, 0x998b, 0x4cb9, 0x996d, 0x4c91, 0x994e, 0x4c68,
+ 0x9930, 0x4c40, 0x9913, 0x4c17, 0x98f5, 0x4bef, 0x98d7, 0x4bc7,
+ 0x98b9, 0x4b9e, 0x989c, 0x4b75, 0x987e, 0x4b4d, 0x9860, 0x4b24,
+ 0x9843, 0x4afb, 0x9826, 0x4ad3, 0x9808, 0x4aaa, 0x97eb, 0x4a81,
+ 0x97ce, 0x4a58, 0x97b0, 0x4a2f, 0x9793, 0x4a06, 0x9776, 0x49dd,
+ 0x9759, 0x49b4, 0x973c, 0x498b, 0x9720, 0x4962, 0x9703, 0x4939,
+ 0x96e6, 0x490f, 0x96c9, 0x48e6, 0x96ad, 0x48bd, 0x9690, 0x4893,
+ 0x9674, 0x486a, 0x9657, 0x4840, 0x963b, 0x4817, 0x961f, 0x47ed,
+ 0x9603, 0x47c4, 0x95e6, 0x479a, 0x95ca, 0x4770, 0x95ae, 0x4747,
+ 0x9592, 0x471d, 0x9577, 0x46f3, 0x955b, 0x46c9, 0x953f, 0x469f,
+ 0x9523, 0x4675, 0x9508, 0x464b, 0x94ec, 0x4621, 0x94d0, 0x45f7,
+ 0x94b5, 0x45cd, 0x949a, 0x45a3, 0x947e, 0x4579, 0x9463, 0x454f,
+ 0x9448, 0x4524, 0x942d, 0x44fa, 0x9412, 0x44d0, 0x93f7, 0x44a5,
+ 0x93dc, 0x447b, 0x93c1, 0x4450, 0x93a6, 0x4426, 0x938b, 0x43fb,
+ 0x9371, 0x43d1, 0x9356, 0x43a6, 0x933c, 0x437b, 0x9321, 0x4351,
+ 0x9307, 0x4326, 0x92ec, 0x42fb, 0x92d2, 0x42d0, 0x92b8, 0x42a5,
+ 0x929e, 0x427a, 0x9284, 0x424f, 0x926a, 0x4224, 0x9250, 0x41f9,
+ 0x9236, 0x41ce, 0x921c, 0x41a3, 0x9202, 0x4178, 0x91e9, 0x414d,
+ 0x91cf, 0x4121, 0x91b6, 0x40f6, 0x919c, 0x40cb, 0x9183, 0x409f,
+ 0x9169, 0x4074, 0x9150, 0x4048, 0x9137, 0x401d, 0x911e, 0x3ff1,
+ 0x9105, 0x3fc6, 0x90ec, 0x3f9a, 0x90d3, 0x3f6f, 0x90ba, 0x3f43,
+ 0x90a1, 0x3f17, 0x9088, 0x3eec, 0x9070, 0x3ec0, 0x9057, 0x3e94,
+ 0x903e, 0x3e68, 0x9026, 0x3e3c, 0x900e, 0x3e10, 0x8ff5, 0x3de4,
+ 0x8fdd, 0x3db8, 0x8fc5, 0x3d8c, 0x8fad, 0x3d60, 0x8f95, 0x3d34,
+ 0x8f7d, 0x3d08, 0x8f65, 0x3cdc, 0x8f4d, 0x3caf, 0x8f35, 0x3c83,
+ 0x8f1d, 0x3c57, 0x8f06, 0x3c2a, 0x8eee, 0x3bfe, 0x8ed6, 0x3bd2,
+ 0x8ebf, 0x3ba5, 0x8ea8, 0x3b79, 0x8e90, 0x3b4c, 0x8e79, 0x3b20,
+ 0x8e62, 0x3af3, 0x8e4b, 0x3ac6, 0x8e34, 0x3a9a, 0x8e1d, 0x3a6d,
+ 0x8e06, 0x3a40, 0x8def, 0x3a13, 0x8dd8, 0x39e7, 0x8dc1, 0x39ba,
+ 0x8dab, 0x398d, 0x8d94, 0x3960, 0x8d7e, 0x3933, 0x8d67, 0x3906,
+ 0x8d51, 0x38d9, 0x8d3b, 0x38ac, 0x8d24, 0x387f, 0x8d0e, 0x3852,
+ 0x8cf8, 0x3825, 0x8ce2, 0x37f7, 0x8ccc, 0x37ca, 0x8cb6, 0x379d,
+ 0x8ca1, 0x3770, 0x8c8b, 0x3742, 0x8c75, 0x3715, 0x8c60, 0x36e8,
+ 0x8c4a, 0x36ba, 0x8c35, 0x368d, 0x8c1f, 0x365f, 0x8c0a, 0x3632,
+ 0x8bf5, 0x3604, 0x8bdf, 0x35d7, 0x8bca, 0x35a9, 0x8bb5, 0x357b,
+ 0x8ba0, 0x354e, 0x8b8b, 0x3520, 0x8b77, 0x34f2, 0x8b62, 0x34c4,
+ 0x8b4d, 0x3497, 0x8b39, 0x3469, 0x8b24, 0x343b, 0x8b10, 0x340d,
+ 0x8afb, 0x33df, 0x8ae7, 0x33b1, 0x8ad3, 0x3383, 0x8abe, 0x3355,
+ 0x8aaa, 0x3327, 0x8a96, 0x32f9, 0x8a82, 0x32cb, 0x8a6e, 0x329d,
+ 0x8a5a, 0x326e, 0x8a47, 0x3240, 0x8a33, 0x3212, 0x8a1f, 0x31e4,
+ 0x8a0c, 0x31b5, 0x89f8, 0x3187, 0x89e5, 0x3159, 0x89d2, 0x312a,
+ 0x89be, 0x30fc, 0x89ab, 0x30cd, 0x8998, 0x309f, 0x8985, 0x3070,
+ 0x8972, 0x3042, 0x895f, 0x3013, 0x894c, 0x2fe5, 0x8939, 0x2fb6,
+ 0x8927, 0x2f87, 0x8914, 0x2f59, 0x8902, 0x2f2a, 0x88ef, 0x2efb,
+ 0x88dd, 0x2ecc, 0x88ca, 0x2e9e, 0x88b8, 0x2e6f, 0x88a6, 0x2e40,
+ 0x8894, 0x2e11, 0x8882, 0x2de2, 0x8870, 0x2db3, 0x885e, 0x2d84,
+ 0x884c, 0x2d55, 0x883a, 0x2d26, 0x8828, 0x2cf7, 0x8817, 0x2cc8,
+ 0x8805, 0x2c99, 0x87f4, 0x2c6a, 0x87e2, 0x2c3b, 0x87d1, 0x2c0c,
+ 0x87c0, 0x2bdc, 0x87af, 0x2bad, 0x879d, 0x2b7e, 0x878c, 0x2b4f,
+ 0x877b, 0x2b1f, 0x876b, 0x2af0, 0x875a, 0x2ac1, 0x8749, 0x2a91,
+ 0x8738, 0x2a62, 0x8728, 0x2a32, 0x8717, 0x2a03, 0x8707, 0x29d3,
+ 0x86f6, 0x29a4, 0x86e6, 0x2974, 0x86d6, 0x2945, 0x86c6, 0x2915,
+ 0x86b6, 0x28e5, 0x86a5, 0x28b6, 0x8696, 0x2886, 0x8686, 0x2856,
+ 0x8676, 0x2827, 0x8666, 0x27f7, 0x8656, 0x27c7, 0x8647, 0x2797,
+ 0x8637, 0x2768, 0x8628, 0x2738, 0x8619, 0x2708, 0x8609, 0x26d8,
+ 0x85fa, 0x26a8, 0x85eb, 0x2678, 0x85dc, 0x2648, 0x85cd, 0x2618,
+ 0x85be, 0x25e8, 0x85af, 0x25b8, 0x85a0, 0x2588, 0x8592, 0x2558,
+ 0x8583, 0x2528, 0x8574, 0x24f8, 0x8566, 0x24c8, 0x8558, 0x2498,
+ 0x8549, 0x2467, 0x853b, 0x2437, 0x852d, 0x2407, 0x851f, 0x23d7,
+ 0x8511, 0x23a7, 0x8503, 0x2376, 0x84f5, 0x2346, 0x84e7, 0x2316,
+ 0x84d9, 0x22e5, 0x84cc, 0x22b5, 0x84be, 0x2284, 0x84b0, 0x2254,
+ 0x84a3, 0x2224, 0x8496, 0x21f3, 0x8488, 0x21c3, 0x847b, 0x2192,
+ 0x846e, 0x2162, 0x8461, 0x2131, 0x8454, 0x2101, 0x8447, 0x20d0,
+ 0x843a, 0x209f, 0x842d, 0x206f, 0x8421, 0x203e, 0x8414, 0x200e,
+ 0x8407, 0x1fdd, 0x83fb, 0x1fac, 0x83ef, 0x1f7b, 0x83e2, 0x1f4b,
+ 0x83d6, 0x1f1a, 0x83ca, 0x1ee9, 0x83be, 0x1eb8, 0x83b2, 0x1e88,
+ 0x83a6, 0x1e57, 0x839a, 0x1e26, 0x838e, 0x1df5, 0x8382, 0x1dc4,
+ 0x8377, 0x1d93, 0x836b, 0x1d62, 0x8360, 0x1d31, 0x8354, 0x1d01,
+ 0x8349, 0x1cd0, 0x833e, 0x1c9f, 0x8332, 0x1c6e, 0x8327, 0x1c3d,
+ 0x831c, 0x1c0c, 0x8311, 0x1bda, 0x8306, 0x1ba9, 0x82fb, 0x1b78,
+ 0x82f1, 0x1b47, 0x82e6, 0x1b16, 0x82db, 0x1ae5, 0x82d1, 0x1ab4,
+ 0x82c6, 0x1a83, 0x82bc, 0x1a51, 0x82b2, 0x1a20, 0x82a8, 0x19ef,
+ 0x829d, 0x19be, 0x8293, 0x198d, 0x8289, 0x195b, 0x827f, 0x192a,
+ 0x8276, 0x18f9, 0x826c, 0x18c7, 0x8262, 0x1896, 0x8259, 0x1865,
+ 0x824f, 0x1833, 0x8246, 0x1802, 0x823c, 0x17d1, 0x8233, 0x179f,
+ 0x822a, 0x176e, 0x8220, 0x173c, 0x8217, 0x170b, 0x820e, 0x16da,
+ 0x8205, 0x16a8, 0x81fd, 0x1677, 0x81f4, 0x1645, 0x81eb, 0x1614,
+ 0x81e2, 0x15e2, 0x81da, 0x15b1, 0x81d1, 0x157f, 0x81c9, 0x154d,
+ 0x81c1, 0x151c, 0x81b8, 0x14ea, 0x81b0, 0x14b9, 0x81a8, 0x1487,
+ 0x81a0, 0x1455, 0x8198, 0x1424, 0x8190, 0x13f2, 0x8188, 0x13c1,
+ 0x8181, 0x138f, 0x8179, 0x135d, 0x8172, 0x132b, 0x816a, 0x12fa,
+ 0x8163, 0x12c8, 0x815b, 0x1296, 0x8154, 0x1265, 0x814d, 0x1233,
+ 0x8146, 0x1201, 0x813f, 0x11cf, 0x8138, 0x119e, 0x8131, 0x116c,
+ 0x812a, 0x113a, 0x8123, 0x1108, 0x811d, 0x10d6, 0x8116, 0x10a4,
+ 0x8110, 0x1073, 0x8109, 0x1041, 0x8103, 0x100f, 0x80fd, 0xfdd,
+ 0x80f6, 0xfab, 0x80f0, 0xf79, 0x80ea, 0xf47, 0x80e4, 0xf15,
+ 0x80de, 0xee4, 0x80d9, 0xeb2, 0x80d3, 0xe80, 0x80cd, 0xe4e,
+ 0x80c8, 0xe1c, 0x80c2, 0xdea, 0x80bd, 0xdb8, 0x80b7, 0xd86,
+ 0x80b2, 0xd54, 0x80ad, 0xd22, 0x80a8, 0xcf0, 0x80a3, 0xcbe,
+ 0x809e, 0xc8c, 0x8099, 0xc5a, 0x8094, 0xc28, 0x808f, 0xbf6,
+ 0x808b, 0xbc4, 0x8086, 0xb92, 0x8082, 0xb60, 0x807d, 0xb2d,
+ 0x8079, 0xafb, 0x8075, 0xac9, 0x8070, 0xa97, 0x806c, 0xa65,
+ 0x8068, 0xa33, 0x8064, 0xa01, 0x8060, 0x9cf, 0x805d, 0x99d,
+ 0x8059, 0x96b, 0x8055, 0x938, 0x8052, 0x906, 0x804e, 0x8d4,
+ 0x804b, 0x8a2, 0x8047, 0x870, 0x8044, 0x83e, 0x8041, 0x80c,
+ 0x803e, 0x7d9, 0x803b, 0x7a7, 0x8038, 0x775, 0x8035, 0x743,
+ 0x8032, 0x711, 0x802f, 0x6de, 0x802d, 0x6ac, 0x802a, 0x67a,
+ 0x8027, 0x648, 0x8025, 0x616, 0x8023, 0x5e3, 0x8020, 0x5b1,
+ 0x801e, 0x57f, 0x801c, 0x54d, 0x801a, 0x51b, 0x8018, 0x4e8,
+ 0x8016, 0x4b6, 0x8014, 0x484, 0x8013, 0x452, 0x8011, 0x41f,
+ 0x800f, 0x3ed, 0x800e, 0x3bb, 0x800c, 0x389, 0x800b, 0x356,
+ 0x800a, 0x324, 0x8009, 0x2f2, 0x8008, 0x2c0, 0x8007, 0x28d,
+ 0x8006, 0x25b, 0x8005, 0x229, 0x8004, 0x1f7, 0x8003, 0x1c4,
+ 0x8002, 0x192, 0x8002, 0x160, 0x8001, 0x12e, 0x8001, 0xfb,
+ 0x8001, 0xc9, 0x8000, 0x97, 0x8000, 0x65, 0x8000, 0x32,
+ 0x8000, 0x0, 0x8000, 0xffce, 0x8000, 0xff9b, 0x8000, 0xff69,
+ 0x8001, 0xff37, 0x8001, 0xff05, 0x8001, 0xfed2, 0x8002, 0xfea0,
+ 0x8002, 0xfe6e, 0x8003, 0xfe3c, 0x8004, 0xfe09, 0x8005, 0xfdd7,
+ 0x8006, 0xfda5, 0x8007, 0xfd73, 0x8008, 0xfd40, 0x8009, 0xfd0e,
+ 0x800a, 0xfcdc, 0x800b, 0xfcaa, 0x800c, 0xfc77, 0x800e, 0xfc45,
+ 0x800f, 0xfc13, 0x8011, 0xfbe1, 0x8013, 0xfbae, 0x8014, 0xfb7c,
+ 0x8016, 0xfb4a, 0x8018, 0xfb18, 0x801a, 0xfae5, 0x801c, 0xfab3,
+ 0x801e, 0xfa81, 0x8020, 0xfa4f, 0x8023, 0xfa1d, 0x8025, 0xf9ea,
+ 0x8027, 0xf9b8, 0x802a, 0xf986, 0x802d, 0xf954, 0x802f, 0xf922,
+ 0x8032, 0xf8ef, 0x8035, 0xf8bd, 0x8038, 0xf88b, 0x803b, 0xf859,
+ 0x803e, 0xf827, 0x8041, 0xf7f4, 0x8044, 0xf7c2, 0x8047, 0xf790,
+ 0x804b, 0xf75e, 0x804e, 0xf72c, 0x8052, 0xf6fa, 0x8055, 0xf6c8,
+ 0x8059, 0xf695, 0x805d, 0xf663, 0x8060, 0xf631, 0x8064, 0xf5ff,
+ 0x8068, 0xf5cd, 0x806c, 0xf59b, 0x8070, 0xf569, 0x8075, 0xf537,
+ 0x8079, 0xf505, 0x807d, 0xf4d3, 0x8082, 0xf4a0, 0x8086, 0xf46e,
+ 0x808b, 0xf43c, 0x808f, 0xf40a, 0x8094, 0xf3d8, 0x8099, 0xf3a6,
+ 0x809e, 0xf374, 0x80a3, 0xf342, 0x80a8, 0xf310, 0x80ad, 0xf2de,
+ 0x80b2, 0xf2ac, 0x80b7, 0xf27a, 0x80bd, 0xf248, 0x80c2, 0xf216,
+ 0x80c8, 0xf1e4, 0x80cd, 0xf1b2, 0x80d3, 0xf180, 0x80d9, 0xf14e,
+ 0x80de, 0xf11c, 0x80e4, 0xf0eb, 0x80ea, 0xf0b9, 0x80f0, 0xf087,
+ 0x80f6, 0xf055, 0x80fd, 0xf023, 0x8103, 0xeff1, 0x8109, 0xefbf,
+ 0x8110, 0xef8d, 0x8116, 0xef5c, 0x811d, 0xef2a, 0x8123, 0xeef8,
+ 0x812a, 0xeec6, 0x8131, 0xee94, 0x8138, 0xee62, 0x813f, 0xee31,
+ 0x8146, 0xedff, 0x814d, 0xedcd, 0x8154, 0xed9b, 0x815b, 0xed6a,
+ 0x8163, 0xed38, 0x816a, 0xed06, 0x8172, 0xecd5, 0x8179, 0xeca3,
+ 0x8181, 0xec71, 0x8188, 0xec3f, 0x8190, 0xec0e, 0x8198, 0xebdc,
+ 0x81a0, 0xebab, 0x81a8, 0xeb79, 0x81b0, 0xeb47, 0x81b8, 0xeb16,
+ 0x81c1, 0xeae4, 0x81c9, 0xeab3, 0x81d1, 0xea81, 0x81da, 0xea4f,
+ 0x81e2, 0xea1e, 0x81eb, 0xe9ec, 0x81f4, 0xe9bb, 0x81fd, 0xe989,
+ 0x8205, 0xe958, 0x820e, 0xe926, 0x8217, 0xe8f5, 0x8220, 0xe8c4,
+ 0x822a, 0xe892, 0x8233, 0xe861, 0x823c, 0xe82f, 0x8246, 0xe7fe,
+ 0x824f, 0xe7cd, 0x8259, 0xe79b, 0x8262, 0xe76a, 0x826c, 0xe739,
+ 0x8276, 0xe707, 0x827f, 0xe6d6, 0x8289, 0xe6a5, 0x8293, 0xe673,
+ 0x829d, 0xe642, 0x82a8, 0xe611, 0x82b2, 0xe5e0, 0x82bc, 0xe5af,
+ 0x82c6, 0xe57d, 0x82d1, 0xe54c, 0x82db, 0xe51b, 0x82e6, 0xe4ea,
+ 0x82f1, 0xe4b9, 0x82fb, 0xe488, 0x8306, 0xe457, 0x8311, 0xe426,
+ 0x831c, 0xe3f4, 0x8327, 0xe3c3, 0x8332, 0xe392, 0x833e, 0xe361,
+ 0x8349, 0xe330, 0x8354, 0xe2ff, 0x8360, 0xe2cf, 0x836b, 0xe29e,
+ 0x8377, 0xe26d, 0x8382, 0xe23c, 0x838e, 0xe20b, 0x839a, 0xe1da,
+ 0x83a6, 0xe1a9, 0x83b2, 0xe178, 0x83be, 0xe148, 0x83ca, 0xe117,
+ 0x83d6, 0xe0e6, 0x83e2, 0xe0b5, 0x83ef, 0xe085, 0x83fb, 0xe054,
+ 0x8407, 0xe023, 0x8414, 0xdff2, 0x8421, 0xdfc2, 0x842d, 0xdf91,
+ 0x843a, 0xdf61, 0x8447, 0xdf30, 0x8454, 0xdeff, 0x8461, 0xdecf,
+ 0x846e, 0xde9e, 0x847b, 0xde6e, 0x8488, 0xde3d, 0x8496, 0xde0d,
+ 0x84a3, 0xdddc, 0x84b0, 0xddac, 0x84be, 0xdd7c, 0x84cc, 0xdd4b,
+ 0x84d9, 0xdd1b, 0x84e7, 0xdcea, 0x84f5, 0xdcba, 0x8503, 0xdc8a,
+ 0x8511, 0xdc59, 0x851f, 0xdc29, 0x852d, 0xdbf9, 0x853b, 0xdbc9,
+ 0x8549, 0xdb99, 0x8558, 0xdb68, 0x8566, 0xdb38, 0x8574, 0xdb08,
+ 0x8583, 0xdad8, 0x8592, 0xdaa8, 0x85a0, 0xda78, 0x85af, 0xda48,
+ 0x85be, 0xda18, 0x85cd, 0xd9e8, 0x85dc, 0xd9b8, 0x85eb, 0xd988,
+ 0x85fa, 0xd958, 0x8609, 0xd928, 0x8619, 0xd8f8, 0x8628, 0xd8c8,
+ 0x8637, 0xd898, 0x8647, 0xd869, 0x8656, 0xd839, 0x8666, 0xd809,
+ 0x8676, 0xd7d9, 0x8686, 0xd7aa, 0x8696, 0xd77a, 0x86a5, 0xd74a,
+ 0x86b6, 0xd71b, 0x86c6, 0xd6eb, 0x86d6, 0xd6bb, 0x86e6, 0xd68c,
+ 0x86f6, 0xd65c, 0x8707, 0xd62d, 0x8717, 0xd5fd, 0x8728, 0xd5ce,
+ 0x8738, 0xd59e, 0x8749, 0xd56f, 0x875a, 0xd53f, 0x876b, 0xd510,
+ 0x877b, 0xd4e1, 0x878c, 0xd4b1, 0x879d, 0xd482, 0x87af, 0xd453,
+ 0x87c0, 0xd424, 0x87d1, 0xd3f4, 0x87e2, 0xd3c5, 0x87f4, 0xd396,
+ 0x8805, 0xd367, 0x8817, 0xd338, 0x8828, 0xd309, 0x883a, 0xd2da,
+ 0x884c, 0xd2ab, 0x885e, 0xd27c, 0x8870, 0xd24d, 0x8882, 0xd21e,
+ 0x8894, 0xd1ef, 0x88a6, 0xd1c0, 0x88b8, 0xd191, 0x88ca, 0xd162,
+ 0x88dd, 0xd134, 0x88ef, 0xd105, 0x8902, 0xd0d6, 0x8914, 0xd0a7,
+ 0x8927, 0xd079, 0x8939, 0xd04a, 0x894c, 0xd01b, 0x895f, 0xcfed,
+ 0x8972, 0xcfbe, 0x8985, 0xcf90, 0x8998, 0xcf61, 0x89ab, 0xcf33,
+ 0x89be, 0xcf04, 0x89d2, 0xced6, 0x89e5, 0xcea7, 0x89f8, 0xce79,
+ 0x8a0c, 0xce4b, 0x8a1f, 0xce1c, 0x8a33, 0xcdee, 0x8a47, 0xcdc0,
+ 0x8a5a, 0xcd92, 0x8a6e, 0xcd63, 0x8a82, 0xcd35, 0x8a96, 0xcd07,
+ 0x8aaa, 0xccd9, 0x8abe, 0xccab, 0x8ad3, 0xcc7d, 0x8ae7, 0xcc4f,
+ 0x8afb, 0xcc21, 0x8b10, 0xcbf3, 0x8b24, 0xcbc5, 0x8b39, 0xcb97,
+ 0x8b4d, 0xcb69, 0x8b62, 0xcb3c, 0x8b77, 0xcb0e, 0x8b8b, 0xcae0,
+ 0x8ba0, 0xcab2, 0x8bb5, 0xca85, 0x8bca, 0xca57, 0x8bdf, 0xca29,
+ 0x8bf5, 0xc9fc, 0x8c0a, 0xc9ce, 0x8c1f, 0xc9a1, 0x8c35, 0xc973,
+ 0x8c4a, 0xc946, 0x8c60, 0xc918, 0x8c75, 0xc8eb, 0x8c8b, 0xc8be,
+ 0x8ca1, 0xc890, 0x8cb6, 0xc863, 0x8ccc, 0xc836, 0x8ce2, 0xc809,
+ 0x8cf8, 0xc7db, 0x8d0e, 0xc7ae, 0x8d24, 0xc781, 0x8d3b, 0xc754,
+ 0x8d51, 0xc727, 0x8d67, 0xc6fa, 0x8d7e, 0xc6cd, 0x8d94, 0xc6a0,
+ 0x8dab, 0xc673, 0x8dc1, 0xc646, 0x8dd8, 0xc619, 0x8def, 0xc5ed,
+ 0x8e06, 0xc5c0, 0x8e1d, 0xc593, 0x8e34, 0xc566, 0x8e4b, 0xc53a,
+ 0x8e62, 0xc50d, 0x8e79, 0xc4e0, 0x8e90, 0xc4b4, 0x8ea8, 0xc487,
+ 0x8ebf, 0xc45b, 0x8ed6, 0xc42e, 0x8eee, 0xc402, 0x8f06, 0xc3d6,
+ 0x8f1d, 0xc3a9, 0x8f35, 0xc37d, 0x8f4d, 0xc351, 0x8f65, 0xc324,
+ 0x8f7d, 0xc2f8, 0x8f95, 0xc2cc, 0x8fad, 0xc2a0, 0x8fc5, 0xc274,
+ 0x8fdd, 0xc248, 0x8ff5, 0xc21c, 0x900e, 0xc1f0, 0x9026, 0xc1c4,
+ 0x903e, 0xc198, 0x9057, 0xc16c, 0x9070, 0xc140, 0x9088, 0xc114,
+ 0x90a1, 0xc0e9, 0x90ba, 0xc0bd, 0x90d3, 0xc091, 0x90ec, 0xc066,
+ 0x9105, 0xc03a, 0x911e, 0xc00f, 0x9137, 0xbfe3, 0x9150, 0xbfb8,
+ 0x9169, 0xbf8c, 0x9183, 0xbf61, 0x919c, 0xbf35, 0x91b6, 0xbf0a,
+ 0x91cf, 0xbedf, 0x91e9, 0xbeb3, 0x9202, 0xbe88, 0x921c, 0xbe5d,
+ 0x9236, 0xbe32, 0x9250, 0xbe07, 0x926a, 0xbddc, 0x9284, 0xbdb1,
+ 0x929e, 0xbd86, 0x92b8, 0xbd5b, 0x92d2, 0xbd30, 0x92ec, 0xbd05,
+ 0x9307, 0xbcda, 0x9321, 0xbcaf, 0x933c, 0xbc85, 0x9356, 0xbc5a,
+ 0x9371, 0xbc2f, 0x938b, 0xbc05, 0x93a6, 0xbbda, 0x93c1, 0xbbb0,
+ 0x93dc, 0xbb85, 0x93f7, 0xbb5b, 0x9412, 0xbb30, 0x942d, 0xbb06,
+ 0x9448, 0xbadc, 0x9463, 0xbab1, 0x947e, 0xba87, 0x949a, 0xba5d,
+ 0x94b5, 0xba33, 0x94d0, 0xba09, 0x94ec, 0xb9df, 0x9508, 0xb9b5,
+ 0x9523, 0xb98b, 0x953f, 0xb961, 0x955b, 0xb937, 0x9577, 0xb90d,
+ 0x9592, 0xb8e3, 0x95ae, 0xb8b9, 0x95ca, 0xb890, 0x95e6, 0xb866,
+ 0x9603, 0xb83c, 0x961f, 0xb813, 0x963b, 0xb7e9, 0x9657, 0xb7c0,
+ 0x9674, 0xb796, 0x9690, 0xb76d, 0x96ad, 0xb743, 0x96c9, 0xb71a,
+ 0x96e6, 0xb6f1, 0x9703, 0xb6c7, 0x9720, 0xb69e, 0x973c, 0xb675,
+ 0x9759, 0xb64c, 0x9776, 0xb623, 0x9793, 0xb5fa, 0x97b0, 0xb5d1,
+ 0x97ce, 0xb5a8, 0x97eb, 0xb57f, 0x9808, 0xb556, 0x9826, 0xb52d,
+ 0x9843, 0xb505, 0x9860, 0xb4dc, 0x987e, 0xb4b3, 0x989c, 0xb48b,
+ 0x98b9, 0xb462, 0x98d7, 0xb439, 0x98f5, 0xb411, 0x9913, 0xb3e9,
+ 0x9930, 0xb3c0, 0x994e, 0xb398, 0x996d, 0xb36f, 0x998b, 0xb347,
+ 0x99a9, 0xb31f, 0x99c7, 0xb2f7, 0x99e5, 0xb2cf, 0x9a04, 0xb2a7,
+ 0x9a22, 0xb27f, 0x9a40, 0xb257, 0x9a5f, 0xb22f, 0x9a7e, 0xb207,
+ 0x9a9c, 0xb1df, 0x9abb, 0xb1b7, 0x9ada, 0xb18f, 0x9af9, 0xb168,
+ 0x9b17, 0xb140, 0x9b36, 0xb118, 0x9b55, 0xb0f1, 0x9b75, 0xb0c9,
+ 0x9b94, 0xb0a2, 0x9bb3, 0xb07b, 0x9bd2, 0xb053, 0x9bf1, 0xb02c,
+ 0x9c11, 0xb005, 0x9c30, 0xafdd, 0x9c50, 0xafb6, 0x9c6f, 0xaf8f,
+ 0x9c8f, 0xaf68, 0x9caf, 0xaf41, 0x9cce, 0xaf1a, 0x9cee, 0xaef3,
+ 0x9d0e, 0xaecc, 0x9d2e, 0xaea5, 0x9d4e, 0xae7f, 0x9d6e, 0xae58,
+ 0x9d8e, 0xae31, 0x9dae, 0xae0b, 0x9dce, 0xade4, 0x9def, 0xadbd,
+ 0x9e0f, 0xad97, 0x9e2f, 0xad70, 0x9e50, 0xad4a, 0x9e70, 0xad24,
+ 0x9e91, 0xacfd, 0x9eb2, 0xacd7, 0x9ed2, 0xacb1, 0x9ef3, 0xac8b,
+ 0x9f14, 0xac65, 0x9f35, 0xac3f, 0x9f56, 0xac19, 0x9f77, 0xabf3,
+ 0x9f98, 0xabcd, 0x9fb9, 0xaba7, 0x9fda, 0xab81, 0x9ffb, 0xab5c,
+ 0xa01c, 0xab36, 0xa03e, 0xab10, 0xa05f, 0xaaeb, 0xa080, 0xaac5,
+ 0xa0a2, 0xaaa0, 0xa0c4, 0xaa7a, 0xa0e5, 0xaa55, 0xa107, 0xaa30,
+ 0xa129, 0xaa0a, 0xa14a, 0xa9e5, 0xa16c, 0xa9c0, 0xa18e, 0xa99b,
+ 0xa1b0, 0xa976, 0xa1d2, 0xa951, 0xa1f4, 0xa92c, 0xa216, 0xa907,
+ 0xa238, 0xa8e2, 0xa25b, 0xa8bd, 0xa27d, 0xa899, 0xa29f, 0xa874,
+ 0xa2c2, 0xa84f, 0xa2e4, 0xa82b, 0xa307, 0xa806, 0xa329, 0xa7e2,
+ 0xa34c, 0xa7bd, 0xa36f, 0xa799, 0xa391, 0xa774, 0xa3b4, 0xa750,
+ 0xa3d7, 0xa72c, 0xa3fa, 0xa708, 0xa41d, 0xa6e4, 0xa440, 0xa6c0,
+ 0xa463, 0xa69c, 0xa486, 0xa678, 0xa4a9, 0xa654, 0xa4cc, 0xa630,
+ 0xa4f0, 0xa60c, 0xa513, 0xa5e8, 0xa537, 0xa5c5, 0xa55a, 0xa5a1,
+ 0xa57e, 0xa57e, 0xa5a1, 0xa55a, 0xa5c5, 0xa537, 0xa5e8, 0xa513,
+ 0xa60c, 0xa4f0, 0xa630, 0xa4cc, 0xa654, 0xa4a9, 0xa678, 0xa486,
+ 0xa69c, 0xa463, 0xa6c0, 0xa440, 0xa6e4, 0xa41d, 0xa708, 0xa3fa,
+ 0xa72c, 0xa3d7, 0xa750, 0xa3b4, 0xa774, 0xa391, 0xa799, 0xa36f,
+ 0xa7bd, 0xa34c, 0xa7e2, 0xa329, 0xa806, 0xa307, 0xa82b, 0xa2e4,
+ 0xa84f, 0xa2c2, 0xa874, 0xa29f, 0xa899, 0xa27d, 0xa8bd, 0xa25b,
+ 0xa8e2, 0xa238, 0xa907, 0xa216, 0xa92c, 0xa1f4, 0xa951, 0xa1d2,
+ 0xa976, 0xa1b0, 0xa99b, 0xa18e, 0xa9c0, 0xa16c, 0xa9e5, 0xa14a,
+ 0xaa0a, 0xa129, 0xaa30, 0xa107, 0xaa55, 0xa0e5, 0xaa7a, 0xa0c4,
+ 0xaaa0, 0xa0a2, 0xaac5, 0xa080, 0xaaeb, 0xa05f, 0xab10, 0xa03e,
+ 0xab36, 0xa01c, 0xab5c, 0x9ffb, 0xab81, 0x9fda, 0xaba7, 0x9fb9,
+ 0xabcd, 0x9f98, 0xabf3, 0x9f77, 0xac19, 0x9f56, 0xac3f, 0x9f35,
+ 0xac65, 0x9f14, 0xac8b, 0x9ef3, 0xacb1, 0x9ed2, 0xacd7, 0x9eb2,
+ 0xacfd, 0x9e91, 0xad24, 0x9e70, 0xad4a, 0x9e50, 0xad70, 0x9e2f,
+ 0xad97, 0x9e0f, 0xadbd, 0x9def, 0xade4, 0x9dce, 0xae0b, 0x9dae,
+ 0xae31, 0x9d8e, 0xae58, 0x9d6e, 0xae7f, 0x9d4e, 0xaea5, 0x9d2e,
+ 0xaecc, 0x9d0e, 0xaef3, 0x9cee, 0xaf1a, 0x9cce, 0xaf41, 0x9caf,
+ 0xaf68, 0x9c8f, 0xaf8f, 0x9c6f, 0xafb6, 0x9c50, 0xafdd, 0x9c30,
+ 0xb005, 0x9c11, 0xb02c, 0x9bf1, 0xb053, 0x9bd2, 0xb07b, 0x9bb3,
+ 0xb0a2, 0x9b94, 0xb0c9, 0x9b75, 0xb0f1, 0x9b55, 0xb118, 0x9b36,
+ 0xb140, 0x9b17, 0xb168, 0x9af9, 0xb18f, 0x9ada, 0xb1b7, 0x9abb,
+ 0xb1df, 0x9a9c, 0xb207, 0x9a7e, 0xb22f, 0x9a5f, 0xb257, 0x9a40,
+ 0xb27f, 0x9a22, 0xb2a7, 0x9a04, 0xb2cf, 0x99e5, 0xb2f7, 0x99c7,
+ 0xb31f, 0x99a9, 0xb347, 0x998b, 0xb36f, 0x996d, 0xb398, 0x994e,
+ 0xb3c0, 0x9930, 0xb3e9, 0x9913, 0xb411, 0x98f5, 0xb439, 0x98d7,
+ 0xb462, 0x98b9, 0xb48b, 0x989c, 0xb4b3, 0x987e, 0xb4dc, 0x9860,
+ 0xb505, 0x9843, 0xb52d, 0x9826, 0xb556, 0x9808, 0xb57f, 0x97eb,
+ 0xb5a8, 0x97ce, 0xb5d1, 0x97b0, 0xb5fa, 0x9793, 0xb623, 0x9776,
+ 0xb64c, 0x9759, 0xb675, 0x973c, 0xb69e, 0x9720, 0xb6c7, 0x9703,
+ 0xb6f1, 0x96e6, 0xb71a, 0x96c9, 0xb743, 0x96ad, 0xb76d, 0x9690,
+ 0xb796, 0x9674, 0xb7c0, 0x9657, 0xb7e9, 0x963b, 0xb813, 0x961f,
+ 0xb83c, 0x9603, 0xb866, 0x95e6, 0xb890, 0x95ca, 0xb8b9, 0x95ae,
+ 0xb8e3, 0x9592, 0xb90d, 0x9577, 0xb937, 0x955b, 0xb961, 0x953f,
+ 0xb98b, 0x9523, 0xb9b5, 0x9508, 0xb9df, 0x94ec, 0xba09, 0x94d0,
+ 0xba33, 0x94b5, 0xba5d, 0x949a, 0xba87, 0x947e, 0xbab1, 0x9463,
+ 0xbadc, 0x9448, 0xbb06, 0x942d, 0xbb30, 0x9412, 0xbb5b, 0x93f7,
+ 0xbb85, 0x93dc, 0xbbb0, 0x93c1, 0xbbda, 0x93a6, 0xbc05, 0x938b,
+ 0xbc2f, 0x9371, 0xbc5a, 0x9356, 0xbc85, 0x933c, 0xbcaf, 0x9321,
+ 0xbcda, 0x9307, 0xbd05, 0x92ec, 0xbd30, 0x92d2, 0xbd5b, 0x92b8,
+ 0xbd86, 0x929e, 0xbdb1, 0x9284, 0xbddc, 0x926a, 0xbe07, 0x9250,
+ 0xbe32, 0x9236, 0xbe5d, 0x921c, 0xbe88, 0x9202, 0xbeb3, 0x91e9,
+ 0xbedf, 0x91cf, 0xbf0a, 0x91b6, 0xbf35, 0x919c, 0xbf61, 0x9183,
+ 0xbf8c, 0x9169, 0xbfb8, 0x9150, 0xbfe3, 0x9137, 0xc00f, 0x911e,
+ 0xc03a, 0x9105, 0xc066, 0x90ec, 0xc091, 0x90d3, 0xc0bd, 0x90ba,
+ 0xc0e9, 0x90a1, 0xc114, 0x9088, 0xc140, 0x9070, 0xc16c, 0x9057,
+ 0xc198, 0x903e, 0xc1c4, 0x9026, 0xc1f0, 0x900e, 0xc21c, 0x8ff5,
+ 0xc248, 0x8fdd, 0xc274, 0x8fc5, 0xc2a0, 0x8fad, 0xc2cc, 0x8f95,
+ 0xc2f8, 0x8f7d, 0xc324, 0x8f65, 0xc351, 0x8f4d, 0xc37d, 0x8f35,
+ 0xc3a9, 0x8f1d, 0xc3d6, 0x8f06, 0xc402, 0x8eee, 0xc42e, 0x8ed6,
+ 0xc45b, 0x8ebf, 0xc487, 0x8ea8, 0xc4b4, 0x8e90, 0xc4e0, 0x8e79,
+ 0xc50d, 0x8e62, 0xc53a, 0x8e4b, 0xc566, 0x8e34, 0xc593, 0x8e1d,
+ 0xc5c0, 0x8e06, 0xc5ed, 0x8def, 0xc619, 0x8dd8, 0xc646, 0x8dc1,
+ 0xc673, 0x8dab, 0xc6a0, 0x8d94, 0xc6cd, 0x8d7e, 0xc6fa, 0x8d67,
+ 0xc727, 0x8d51, 0xc754, 0x8d3b, 0xc781, 0x8d24, 0xc7ae, 0x8d0e,
+ 0xc7db, 0x8cf8, 0xc809, 0x8ce2, 0xc836, 0x8ccc, 0xc863, 0x8cb6,
+ 0xc890, 0x8ca1, 0xc8be, 0x8c8b, 0xc8eb, 0x8c75, 0xc918, 0x8c60,
+ 0xc946, 0x8c4a, 0xc973, 0x8c35, 0xc9a1, 0x8c1f, 0xc9ce, 0x8c0a,
+ 0xc9fc, 0x8bf5, 0xca29, 0x8bdf, 0xca57, 0x8bca, 0xca85, 0x8bb5,
+ 0xcab2, 0x8ba0, 0xcae0, 0x8b8b, 0xcb0e, 0x8b77, 0xcb3c, 0x8b62,
+ 0xcb69, 0x8b4d, 0xcb97, 0x8b39, 0xcbc5, 0x8b24, 0xcbf3, 0x8b10,
+ 0xcc21, 0x8afb, 0xcc4f, 0x8ae7, 0xcc7d, 0x8ad3, 0xccab, 0x8abe,
+ 0xccd9, 0x8aaa, 0xcd07, 0x8a96, 0xcd35, 0x8a82, 0xcd63, 0x8a6e,
+ 0xcd92, 0x8a5a, 0xcdc0, 0x8a47, 0xcdee, 0x8a33, 0xce1c, 0x8a1f,
+ 0xce4b, 0x8a0c, 0xce79, 0x89f8, 0xcea7, 0x89e5, 0xced6, 0x89d2,
+ 0xcf04, 0x89be, 0xcf33, 0x89ab, 0xcf61, 0x8998, 0xcf90, 0x8985,
+ 0xcfbe, 0x8972, 0xcfed, 0x895f, 0xd01b, 0x894c, 0xd04a, 0x8939,
+ 0xd079, 0x8927, 0xd0a7, 0x8914, 0xd0d6, 0x8902, 0xd105, 0x88ef,
+ 0xd134, 0x88dd, 0xd162, 0x88ca, 0xd191, 0x88b8, 0xd1c0, 0x88a6,
+ 0xd1ef, 0x8894, 0xd21e, 0x8882, 0xd24d, 0x8870, 0xd27c, 0x885e,
+ 0xd2ab, 0x884c, 0xd2da, 0x883a, 0xd309, 0x8828, 0xd338, 0x8817,
+ 0xd367, 0x8805, 0xd396, 0x87f4, 0xd3c5, 0x87e2, 0xd3f4, 0x87d1,
+ 0xd424, 0x87c0, 0xd453, 0x87af, 0xd482, 0x879d, 0xd4b1, 0x878c,
+ 0xd4e1, 0x877b, 0xd510, 0x876b, 0xd53f, 0x875a, 0xd56f, 0x8749,
+ 0xd59e, 0x8738, 0xd5ce, 0x8728, 0xd5fd, 0x8717, 0xd62d, 0x8707,
+ 0xd65c, 0x86f6, 0xd68c, 0x86e6, 0xd6bb, 0x86d6, 0xd6eb, 0x86c6,
+ 0xd71b, 0x86b6, 0xd74a, 0x86a5, 0xd77a, 0x8696, 0xd7aa, 0x8686,
+ 0xd7d9, 0x8676, 0xd809, 0x8666, 0xd839, 0x8656, 0xd869, 0x8647,
+ 0xd898, 0x8637, 0xd8c8, 0x8628, 0xd8f8, 0x8619, 0xd928, 0x8609,
+ 0xd958, 0x85fa, 0xd988, 0x85eb, 0xd9b8, 0x85dc, 0xd9e8, 0x85cd,
+ 0xda18, 0x85be, 0xda48, 0x85af, 0xda78, 0x85a0, 0xdaa8, 0x8592,
+ 0xdad8, 0x8583, 0xdb08, 0x8574, 0xdb38, 0x8566, 0xdb68, 0x8558,
+ 0xdb99, 0x8549, 0xdbc9, 0x853b, 0xdbf9, 0x852d, 0xdc29, 0x851f,
+ 0xdc59, 0x8511, 0xdc8a, 0x8503, 0xdcba, 0x84f5, 0xdcea, 0x84e7,
+ 0xdd1b, 0x84d9, 0xdd4b, 0x84cc, 0xdd7c, 0x84be, 0xddac, 0x84b0,
+ 0xdddc, 0x84a3, 0xde0d, 0x8496, 0xde3d, 0x8488, 0xde6e, 0x847b,
+ 0xde9e, 0x846e, 0xdecf, 0x8461, 0xdeff, 0x8454, 0xdf30, 0x8447,
+ 0xdf61, 0x843a, 0xdf91, 0x842d, 0xdfc2, 0x8421, 0xdff2, 0x8414,
+ 0xe023, 0x8407, 0xe054, 0x83fb, 0xe085, 0x83ef, 0xe0b5, 0x83e2,
+ 0xe0e6, 0x83d6, 0xe117, 0x83ca, 0xe148, 0x83be, 0xe178, 0x83b2,
+ 0xe1a9, 0x83a6, 0xe1da, 0x839a, 0xe20b, 0x838e, 0xe23c, 0x8382,
+ 0xe26d, 0x8377, 0xe29e, 0x836b, 0xe2cf, 0x8360, 0xe2ff, 0x8354,
+ 0xe330, 0x8349, 0xe361, 0x833e, 0xe392, 0x8332, 0xe3c3, 0x8327,
+ 0xe3f4, 0x831c, 0xe426, 0x8311, 0xe457, 0x8306, 0xe488, 0x82fb,
+ 0xe4b9, 0x82f1, 0xe4ea, 0x82e6, 0xe51b, 0x82db, 0xe54c, 0x82d1,
+ 0xe57d, 0x82c6, 0xe5af, 0x82bc, 0xe5e0, 0x82b2, 0xe611, 0x82a8,
+ 0xe642, 0x829d, 0xe673, 0x8293, 0xe6a5, 0x8289, 0xe6d6, 0x827f,
+ 0xe707, 0x8276, 0xe739, 0x826c, 0xe76a, 0x8262, 0xe79b, 0x8259,
+ 0xe7cd, 0x824f, 0xe7fe, 0x8246, 0xe82f, 0x823c, 0xe861, 0x8233,
+ 0xe892, 0x822a, 0xe8c4, 0x8220, 0xe8f5, 0x8217, 0xe926, 0x820e,
+ 0xe958, 0x8205, 0xe989, 0x81fd, 0xe9bb, 0x81f4, 0xe9ec, 0x81eb,
+ 0xea1e, 0x81e2, 0xea4f, 0x81da, 0xea81, 0x81d1, 0xeab3, 0x81c9,
+ 0xeae4, 0x81c1, 0xeb16, 0x81b8, 0xeb47, 0x81b0, 0xeb79, 0x81a8,
+ 0xebab, 0x81a0, 0xebdc, 0x8198, 0xec0e, 0x8190, 0xec3f, 0x8188,
+ 0xec71, 0x8181, 0xeca3, 0x8179, 0xecd5, 0x8172, 0xed06, 0x816a,
+ 0xed38, 0x8163, 0xed6a, 0x815b, 0xed9b, 0x8154, 0xedcd, 0x814d,
+ 0xedff, 0x8146, 0xee31, 0x813f, 0xee62, 0x8138, 0xee94, 0x8131,
+ 0xeec6, 0x812a, 0xeef8, 0x8123, 0xef2a, 0x811d, 0xef5c, 0x8116,
+ 0xef8d, 0x8110, 0xefbf, 0x8109, 0xeff1, 0x8103, 0xf023, 0x80fd,
+ 0xf055, 0x80f6, 0xf087, 0x80f0, 0xf0b9, 0x80ea, 0xf0eb, 0x80e4,
+ 0xf11c, 0x80de, 0xf14e, 0x80d9, 0xf180, 0x80d3, 0xf1b2, 0x80cd,
+ 0xf1e4, 0x80c8, 0xf216, 0x80c2, 0xf248, 0x80bd, 0xf27a, 0x80b7,
+ 0xf2ac, 0x80b2, 0xf2de, 0x80ad, 0xf310, 0x80a8, 0xf342, 0x80a3,
+ 0xf374, 0x809e, 0xf3a6, 0x8099, 0xf3d8, 0x8094, 0xf40a, 0x808f,
+ 0xf43c, 0x808b, 0xf46e, 0x8086, 0xf4a0, 0x8082, 0xf4d3, 0x807d,
+ 0xf505, 0x8079, 0xf537, 0x8075, 0xf569, 0x8070, 0xf59b, 0x806c,
+ 0xf5cd, 0x8068, 0xf5ff, 0x8064, 0xf631, 0x8060, 0xf663, 0x805d,
+ 0xf695, 0x8059, 0xf6c8, 0x8055, 0xf6fa, 0x8052, 0xf72c, 0x804e,
+ 0xf75e, 0x804b, 0xf790, 0x8047, 0xf7c2, 0x8044, 0xf7f4, 0x8041,
+ 0xf827, 0x803e, 0xf859, 0x803b, 0xf88b, 0x8038, 0xf8bd, 0x8035,
+ 0xf8ef, 0x8032, 0xf922, 0x802f, 0xf954, 0x802d, 0xf986, 0x802a,
+ 0xf9b8, 0x8027, 0xf9ea, 0x8025, 0xfa1d, 0x8023, 0xfa4f, 0x8020,
+ 0xfa81, 0x801e, 0xfab3, 0x801c, 0xfae5, 0x801a, 0xfb18, 0x8018,
+ 0xfb4a, 0x8016, 0xfb7c, 0x8014, 0xfbae, 0x8013, 0xfbe1, 0x8011,
+ 0xfc13, 0x800f, 0xfc45, 0x800e, 0xfc77, 0x800c, 0xfcaa, 0x800b,
+ 0xfcdc, 0x800a, 0xfd0e, 0x8009, 0xfd40, 0x8008, 0xfd73, 0x8007,
+ 0xfda5, 0x8006, 0xfdd7, 0x8005, 0xfe09, 0x8004, 0xfe3c, 0x8003,
+ 0xfe6e, 0x8002, 0xfea0, 0x8002, 0xfed2, 0x8001, 0xff05, 0x8001,
+ 0xff37, 0x8001, 0xff69, 0x8000, 0xff9b, 0x8000, 0xffce, 0x8000,
+};
+
+/**
+* @} end of CFFT_CIFFT group
+*/
+
+/*
+* @brief Q15 table for reciprocal
+*/
+const q15_t ALIGN4 armRecipTableQ15[64] = {
+ 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0,
+ 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82,
+ 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484,
+ 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0,
+ 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E,
+ 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255,
+ 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6,
+ 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978,
+ 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8,
+ 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255,
+ 0x41CC, 0x4146, 0x40C2, 0x4040
+};
+
+/*
+* @brief Q31 table for reciprocal
+*/
+const q31_t armRecipTableQ31[64] = {
+ 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928,
+ 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3,
+ 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519,
+ 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB,
+ 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318,
+ 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0,
+ 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D,
+ 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96,
+ 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2,
+ 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426,
+ 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102
+};
+
+const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH] =
+{
+ //8x2, size 20
+ 8,64, 24,72, 16,64, 40,80, 32,64, 56,88, 48,72, 88,104, 72,96, 104,112
+};
+
+const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH] =
+{
+ //8x4, size 48
+ 8,64, 16,128, 24,192, 32,64, 40,72, 48,136, 56,200, 64,128, 72,80, 88,208,
+ 80,144, 96,192, 104,208, 112,152, 120,216, 136,192, 144,160, 168,208,
+ 152,224, 176,208, 184,232, 216,240, 200,224, 232,240
+};
+
+const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH] =
+{
+ //radix 8, size 56
+ 8,64, 16,128, 24,192, 32,256, 40,320, 48,384, 56,448, 80,136, 88,200,
+ 96,264, 104,328, 112,392, 120,456, 152,208, 160,272, 168,336, 176,400,
+ 184,464, 224,280, 232,344, 240,408, 248,472, 296,352, 304,416, 312,480,
+ 368,424, 376,488, 440,496
+};
+
+const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH] =
+{
+ //8x2, size 208
+ 8,512, 16,64, 24,576, 32,128, 40,640, 48,192, 56,704, 64,256, 72,768,
+ 80,320, 88,832, 96,384, 104,896, 112,448, 120,960, 128,512, 136,520,
+ 144,768, 152,584, 160,520, 168,648, 176,200, 184,712, 192,264, 200,776,
+ 208,328, 216,840, 224,392, 232,904, 240,456, 248,968, 264,528, 272,320,
+ 280,592, 288,768, 296,656, 304,328, 312,720, 328,784, 344,848, 352,400,
+ 360,912, 368,464, 376,976, 384,576, 392,536, 400,832, 408,600, 416,584,
+ 424,664, 432,840, 440,728, 448,592, 456,792, 464,848, 472,856, 480,600,
+ 488,920, 496,856, 504,984, 520,544, 528,576, 536,608, 552,672, 560,608,
+ 568,736, 576,768, 584,800, 592,832, 600,864, 608,800, 616,928, 624,864,
+ 632,992, 648,672, 656,896, 664,928, 688,904, 696,744, 704,896, 712,808,
+ 720,912, 728,872, 736,928, 744,936, 752,920, 760,1000, 776,800, 784,832,
+ 792,864, 808,904, 816,864, 824,920, 840,864, 856,880, 872,944, 888,1008,
+ 904,928, 912,960, 920,992, 944,968, 952,1000, 968,992, 984,1008
+};
+
+const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH] =
+{
+ //8x4, size 440
+ 8,512, 16,1024, 24,1536, 32,64, 40,576, 48,1088, 56,1600, 64,128, 72,640,
+ 80,1152, 88,1664, 96,192, 104,704, 112,1216, 120,1728, 128,256, 136,768,
+ 144,1280, 152,1792, 160,320, 168,832, 176,1344, 184,1856, 192,384,
+ 200,896, 208,1408, 216,1920, 224,448, 232,960, 240,1472, 248,1984,
+ 256,512, 264,520, 272,1032, 280,1544, 288,640, 296,584, 304,1096, 312,1608,
+ 320,768, 328,648, 336,1160, 344,1672, 352,896, 360,712, 368,1224, 376,1736,
+ 384,520, 392,776, 400,1288, 408,1800, 416,648, 424,840, 432,1352, 440,1864,
+ 448,776, 456,904, 464,1416, 472,1928, 480,904, 488,968, 496,1480, 504,1992,
+ 520,528, 512,1024, 528,1040, 536,1552, 544,1152, 552,592, 560,1104,
+ 568,1616, 576,1280, 584,656, 592,1168, 600,1680, 608,1408, 616,720,
+ 624,1232, 632,1744, 640,1032, 648,784, 656,1296, 664,1808, 672,1160,
+ 680,848, 688,1360, 696,1872, 704,1288, 712,912, 720,1424, 728,1936,
+ 736,1416, 744,976, 752,1488, 760,2000, 768,1536, 776,1552, 784,1048,
+ 792,1560, 800,1664, 808,1680, 816,1112, 824,1624, 832,1792, 840,1808,
+ 848,1176, 856,1688, 864,1920, 872,1936, 880,1240, 888,1752, 896,1544,
+ 904,1560, 912,1304, 920,1816, 928,1672, 936,1688, 944,1368, 952,1880,
+ 960,1800, 968,1816, 976,1432, 984,1944, 992,1928, 1000,1944, 1008,1496,
+ 1016,2008, 1032,1152, 1040,1056, 1048,1568, 1064,1408, 1072,1120,
+ 1080,1632, 1088,1536, 1096,1160, 1104,1184, 1112,1696, 1120,1552,
+ 1128,1416, 1136,1248, 1144,1760, 1160,1664, 1168,1312, 1176,1824,
+ 1184,1544, 1192,1920, 1200,1376, 1208,1888, 1216,1568, 1224,1672,
+ 1232,1440, 1240,1952, 1248,1560, 1256,1928, 1264,1504, 1272,2016,
+ 1288,1312, 1296,1408, 1304,1576, 1320,1424, 1328,1416, 1336,1640,
+ 1344,1792, 1352,1824, 1360,1920, 1368,1704, 1376,1800, 1384,1432,
+ 1392,1928, 1400,1768, 1416,1680, 1432,1832, 1440,1576, 1448,1936,
+ 1456,1832, 1464,1896, 1472,1808, 1480,1688, 1488,1936, 1496,1960,
+ 1504,1816, 1512,1944, 1520,1944, 1528,2024, 1560,1584, 1592,1648,
+ 1600,1792, 1608,1920, 1616,1800, 1624,1712, 1632,1808, 1640,1936,
+ 1648,1816, 1656,1776, 1672,1696, 1688,1840, 1704,1952, 1712,1928,
+ 1720,1904, 1728,1824, 1736,1952, 1744,1832, 1752,1968, 1760,1840,
+ 1768,1960, 1776,1944, 1784,2032, 1864,1872, 1848,1944, 1872,1888,
+ 1880,1904, 1888,1984, 1896,2000, 1912,2032, 1904,2016, 1976,2032,
+ 1960,1968, 2008,2032, 1992,2016, 2024,2032
+};
+
+const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH] =
+{
+ //radix 8, size 448
+ 8,512, 16,1024, 24,1536, 32,2048, 40,2560, 48,3072, 56,3584, 72,576,
+ 80,1088, 88,1600, 96,2112, 104,2624, 112,3136, 120,3648, 136,640, 144,1152,
+ 152,1664, 160,2176, 168,2688, 176,3200, 184,3712, 200,704, 208,1216,
+ 216,1728, 224,2240, 232,2752, 240,3264, 248,3776, 264,768, 272,1280,
+ 280,1792, 288,2304, 296,2816, 304,3328, 312,3840, 328,832, 336,1344,
+ 344,1856, 352,2368, 360,2880, 368,3392, 376,3904, 392,896, 400,1408,
+ 408,1920, 416,2432, 424,2944, 432,3456, 440,3968, 456,960, 464,1472,
+ 472,1984, 480,2496, 488,3008, 496,3520, 504,4032, 528,1032, 536,1544,
+ 544,2056, 552,2568, 560,3080, 568,3592, 592,1096, 600,1608, 608,2120,
+ 616,2632, 624,3144, 632,3656, 656,1160, 664,1672, 672,2184, 680,2696,
+ 688,3208, 696,3720, 720,1224, 728,1736, 736,2248, 744,2760, 752,3272,
+ 760,3784, 784,1288, 792,1800, 800,2312, 808,2824, 816,3336, 824,3848,
+ 848,1352, 856,1864, 864,2376, 872,2888, 880,3400, 888,3912, 912,1416,
+ 920,1928, 928,2440, 936,2952, 944,3464, 952,3976, 976,1480, 984,1992,
+ 992,2504, 1000,3016, 1008,3528, 1016,4040, 1048,1552, 1056,2064, 1064,2576,
+ 1072,3088, 1080,3600, 1112,1616, 1120,2128, 1128,2640, 1136,3152,
+ 1144,3664, 1176,1680, 1184,2192, 1192,2704, 1200,3216, 1208,3728,
+ 1240,1744, 1248,2256, 1256,2768, 1264,3280, 1272,3792, 1304,1808,
+ 1312,2320, 1320,2832, 1328,3344, 1336,3856, 1368,1872, 1376,2384,
+ 1384,2896, 1392,3408, 1400,3920, 1432,1936, 1440,2448, 1448,2960,
+ 1456,3472, 1464,3984, 1496,2000, 1504,2512, 1512,3024, 1520,3536,
+ 1528,4048, 1568,2072, 1576,2584, 1584,3096, 1592,3608, 1632,2136,
+ 1640,2648, 1648,3160, 1656,3672, 1696,2200, 1704,2712, 1712,3224,
+ 1720,3736, 1760,2264, 1768,2776, 1776,3288, 1784,3800, 1824,2328,
+ 1832,2840, 1840,3352, 1848,3864, 1888,2392, 1896,2904, 1904,3416,
+ 1912,3928, 1952,2456, 1960,2968, 1968,3480, 1976,3992, 2016,2520,
+ 2024,3032, 2032,3544, 2040,4056, 2088,2592, 2096,3104, 2104,3616,
+ 2152,2656, 2160,3168, 2168,3680, 2216,2720, 2224,3232, 2232,3744,
+ 2280,2784, 2288,3296, 2296,3808, 2344,2848, 2352,3360, 2360,3872,
+ 2408,2912, 2416,3424, 2424,3936, 2472,2976, 2480,3488, 2488,4000,
+ 2536,3040, 2544,3552, 2552,4064, 2608,3112, 2616,3624, 2672,3176,
+ 2680,3688, 2736,3240, 2744,3752, 2800,3304, 2808,3816, 2864,3368,
+ 2872,3880, 2928,3432, 2936,3944, 2992,3496, 3000,4008, 3056,3560,
+ 3064,4072, 3128,3632, 3192,3696, 3256,3760, 3320,3824, 3384,3888,
+ 3448,3952, 3512,4016, 3576,4080
+};
+
+const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH] =
+{
+ //8x2, size 1800
+ 8,4096, 16,512, 24,4608, 32,1024, 40,5120, 48,1536, 56,5632, 64,2048,
+ 72,6144, 80,2560, 88,6656, 96,3072, 104,7168, 112,3584, 120,7680, 128,2048,
+ 136,4160, 144,576, 152,4672, 160,1088, 168,5184, 176,1600, 184,5696,
+ 192,2112, 200,6208, 208,2624, 216,6720, 224,3136, 232,7232, 240,3648,
+ 248,7744, 256,2048, 264,4224, 272,640, 280,4736, 288,1152, 296,5248,
+ 304,1664, 312,5760, 320,2176, 328,6272, 336,2688, 344,6784, 352,3200,
+ 360,7296, 368,3712, 376,7808, 384,2112, 392,4288, 400,704, 408,4800,
+ 416,1216, 424,5312, 432,1728, 440,5824, 448,2240, 456,6336, 464,2752,
+ 472,6848, 480,3264, 488,7360, 496,3776, 504,7872, 512,2048, 520,4352,
+ 528,768, 536,4864, 544,1280, 552,5376, 560,1792, 568,5888, 576,2304,
+ 584,6400, 592,2816, 600,6912, 608,3328, 616,7424, 624,3840, 632,7936,
+ 640,2176, 648,4416, 656,832, 664,4928, 672,1344, 680,5440, 688,1856,
+ 696,5952, 704,2368, 712,6464, 720,2880, 728,6976, 736,3392, 744,7488,
+ 752,3904, 760,8000, 768,2112, 776,4480, 784,896, 792,4992, 800,1408,
+ 808,5504, 816,1920, 824,6016, 832,2432, 840,6528, 848,2944, 856,7040,
+ 864,3456, 872,7552, 880,3968, 888,8064, 896,2240, 904,4544, 912,960,
+ 920,5056, 928,1472, 936,5568, 944,1984, 952,6080, 960,2496, 968,6592,
+ 976,3008, 984,7104, 992,3520, 1000,7616, 1008,4032, 1016,8128, 1024,4096,
+ 1032,4104, 1040,4352, 1048,4616, 1056,4104, 1064,5128, 1072,1544,
+ 1080,5640, 1088,2056, 1096,6152, 1104,2568, 1112,6664, 1120,3080,
+ 1128,7176, 1136,3592, 1144,7688, 1152,6144, 1160,4168, 1168,6400,
+ 1176,4680, 1184,6152, 1192,5192, 1200,1608, 1208,5704, 1216,2120,
+ 1224,6216, 1232,2632, 1240,6728, 1248,3144, 1256,7240, 1264,3656,
+ 1272,7752, 1280,4160, 1288,4232, 1296,4416, 1304,4744, 1312,4168,
+ 1320,5256, 1328,1672, 1336,5768, 1344,2184, 1352,6280, 1360,2696,
+ 1368,6792, 1376,3208, 1384,7304, 1392,3720, 1400,7816, 1408,6208,
+ 1416,4296, 1424,6464, 1432,4808, 1440,6216, 1448,5320, 1456,1736,
+ 1464,5832, 1472,2248, 1480,6344, 1488,2760, 1496,6856, 1504,3272,
+ 1512,7368, 1520,3784, 1528,7880, 1536,4224, 1544,4360, 1552,4480,
+ 1560,4872, 1568,4232, 1576,5384, 1584,1800, 1592,5896, 1600,2312,
+ 1608,6408, 1616,2824, 1624,6920, 1632,3336, 1640,7432, 1648,3848,
+ 1656,7944, 1664,6272, 1672,4424, 1680,6528, 1688,4936, 1696,6280,
+ 1704,5448, 1712,1864, 1720,5960, 1728,2376, 1736,6472, 1744,2888,
+ 1752,6984, 1760,3400, 1768,7496, 1776,3912, 1784,8008, 1792,4288,
+ 1800,4488, 1808,4544, 1816,5000, 1824,4296, 1832,5512, 1840,1928,
+ 1848,6024, 1856,2440, 1864,6536, 1872,2952, 1880,7048, 1888,3464,
+ 1896,7560, 1904,3976, 1912,8072, 1920,6336, 1928,4552, 1936,6592,
+ 1944,5064, 1952,6344, 1960,5576, 1968,1992, 1976,6088, 1984,2504,
+ 1992,6600, 2000,3016, 2008,7112, 2016,3528, 2024,7624, 2032,4040,
+ 2040,8136, 2056,4112, 2064,2112, 2072,4624, 2080,4352, 2088,5136,
+ 2096,4480, 2104,5648, 2120,6160, 2128,2576, 2136,6672, 2144,3088,
+ 2152,7184, 2160,3600, 2168,7696, 2176,2560, 2184,4176, 2192,2816,
+ 2200,4688, 2208,2568, 2216,5200, 2224,2824, 2232,5712, 2240,2576,
+ 2248,6224, 2256,2640, 2264,6736, 2272,3152, 2280,7248, 2288,3664,
+ 2296,7760, 2312,4240, 2320,2432, 2328,4752, 2336,6400, 2344,5264,
+ 2352,6528, 2360,5776, 2368,2816, 2376,6288, 2384,2704, 2392,6800,
+ 2400,3216, 2408,7312, 2416,3728, 2424,7824, 2432,2624, 2440,4304,
+ 2448,2880, 2456,4816, 2464,2632, 2472,5328, 2480,2888, 2488,5840,
+ 2496,2640, 2504,6352, 2512,2768, 2520,6864, 2528,3280, 2536,7376,
+ 2544,3792, 2552,7888, 2568,4368, 2584,4880, 2592,4416, 2600,5392,
+ 2608,4544, 2616,5904, 2632,6416, 2640,2832, 2648,6928, 2656,3344,
+ 2664,7440, 2672,3856, 2680,7952, 2696,4432, 2704,2944, 2712,4944,
+ 2720,4432, 2728,5456, 2736,2952, 2744,5968, 2752,2944, 2760,6480,
+ 2768,2896, 2776,6992, 2784,3408, 2792,7504, 2800,3920, 2808,8016,
+ 2824,4496, 2840,5008, 2848,6464, 2856,5520, 2864,6592, 2872,6032,
+ 2888,6544, 2896,2960, 2904,7056, 2912,3472, 2920,7568, 2928,3984,
+ 2936,8080, 2952,4560, 2960,3008, 2968,5072, 2976,6480, 2984,5584,
+ 2992,3016, 3000,6096, 3016,6608, 3032,7120, 3040,3536, 3048,7632,
+ 3056,4048, 3064,8144, 3072,4608, 3080,4120, 3088,4864, 3096,4632,
+ 3104,4616, 3112,5144, 3120,4872, 3128,5656, 3136,4624, 3144,6168,
+ 3152,4880, 3160,6680, 3168,4632, 3176,7192, 3184,3608, 3192,7704,
+ 3200,6656, 3208,4184, 3216,6912, 3224,4696, 3232,6664, 3240,5208,
+ 3248,6920, 3256,5720, 3264,6672, 3272,6232, 3280,6928, 3288,6744,
+ 3296,6680, 3304,7256, 3312,3672, 3320,7768, 3328,4672, 3336,4248,
+ 3344,4928, 3352,4760, 3360,4680, 3368,5272, 3376,4936, 3384,5784,
+ 3392,4688, 3400,6296, 3408,4944, 3416,6808, 3424,4696, 3432,7320,
+ 3440,3736, 3448,7832, 3456,6720, 3464,4312, 3472,6976, 3480,4824,
+ 3488,6728, 3496,5336, 3504,6984, 3512,5848, 3520,6736, 3528,6360,
+ 3536,6992, 3544,6872, 3552,6744, 3560,7384, 3568,3800, 3576,7896,
+ 3584,4736, 3592,4376, 3600,4992, 3608,4888, 3616,4744, 3624,5400,
+ 3632,5000, 3640,5912, 3648,4752, 3656,6424, 3664,5008, 3672,6936,
+ 3680,4760, 3688,7448, 3696,3864, 3704,7960, 3712,6784, 3720,4440,
+ 3728,7040, 3736,4952, 3744,6792, 3752,5464, 3760,7048, 3768,5976,
+ 3776,6800, 3784,6488, 3792,7056, 3800,7000, 3808,6808, 3816,7512,
+ 3824,3928, 3832,8024, 3840,4800, 3848,4504, 3856,5056, 3864,5016,
+ 3872,4808, 3880,5528, 3888,5064, 3896,6040, 3904,4816, 3912,6552,
+ 3920,5072, 3928,7064, 3936,4824, 3944,7576, 3952,3992, 3960,8088,
+ 3968,6848, 3976,4568, 3984,7104, 3992,5080, 4000,6856, 4008,5592,
+ 4016,7112, 4024,6104, 4032,6864, 4040,6616, 4048,7120, 4056,7128,
+ 4064,6872, 4072,7640, 4080,7128, 4088,8152, 4104,4128, 4112,4160,
+ 4120,4640, 4136,5152, 4144,4232, 4152,5664, 4160,4352, 4168,6176,
+ 4176,4416, 4184,6688, 4192,4616, 4200,7200, 4208,4744, 4216,7712,
+ 4224,4608, 4232,4616, 4240,4672, 4248,4704, 4256,4640, 4264,5216,
+ 4272,4704, 4280,5728, 4288,4864, 4296,6240, 4304,4928, 4312,6752,
+ 4320,4632, 4328,7264, 4336,4760, 4344,7776, 4360,4640, 4368,4416,
+ 4376,4768, 4384,6152, 4392,5280, 4400,6280, 4408,5792, 4424,6304,
+ 4440,6816, 4448,6664, 4456,7328, 4464,6792, 4472,7840, 4480,4624,
+ 4488,4632, 4496,4688, 4504,4832, 4512,6168, 4520,5344, 4528,6296,
+ 4536,5856, 4544,4880, 4552,6368, 4560,4944, 4568,6880, 4576,6680,
+ 4584,7392, 4592,6808, 4600,7904, 4608,6144, 4616,6152, 4624,6208,
+ 4632,4896, 4640,6176, 4648,5408, 4656,6240, 4664,5920, 4672,6400,
+ 4680,6432, 4688,6464, 4696,6944, 4704,6432, 4712,7456, 4720,4808,
+ 4728,7968, 4736,6656, 4744,6664, 4752,6720, 4760,4960, 4768,6688,
+ 4776,5472, 4784,6752, 4792,5984, 4800,6912, 4808,6496, 4816,6976,
+ 4824,7008, 4832,6944, 4840,7520, 4848,7008, 4856,8032, 4864,6160,
+ 4872,6168, 4880,6224, 4888,5024, 4896,6216, 4904,5536, 4912,6344,
+ 4920,6048, 4928,6416, 4936,6560, 4944,6480, 4952,7072, 4960,6728,
+ 4968,7584, 4976,6856, 4984,8096, 4992,6672, 5000,6680, 5008,6736,
+ 5016,5088, 5024,6232, 5032,5600, 5040,6360, 5048,6112, 5056,6928,
+ 5064,6624, 5072,6992, 5080,7136, 5088,6744, 5096,7648, 5104,6872,
+ 5112,8160, 5128,5152, 5136,5376, 5144,5408, 5168,5384, 5176,5672,
+ 5184,5376, 5192,6184, 5200,5392, 5208,6696, 5216,5408, 5224,7208,
+ 5232,5400, 5240,7720, 5248,7168, 5256,7200, 5264,7424, 5272,7456,
+ 5280,7176, 5288,7208, 5296,7432, 5304,5736, 5312,7184, 5320,6248,
+ 5328,7440, 5336,6760, 5344,7192, 5352,7272, 5360,7448, 5368,7784,
+ 5384,5408, 5392,5440, 5400,5472, 5408,6184, 5416,7208, 5424,5448,
+ 5432,5800, 5448,6312, 5464,6824, 5472,6696, 5480,7336, 5488,6824,
+ 5496,7848, 5504,7232, 5512,7264, 5520,7488, 5528,7520, 5536,7240,
+ 5544,7272, 5552,7496, 5560,5864, 5568,7248, 5576,6376, 5584,7504,
+ 5592,6888, 5600,7256, 5608,7400, 5616,7512, 5624,7912, 5632,7168,
+ 5640,7176, 5648,7232, 5656,7240, 5664,7200, 5672,7208, 5680,7264,
+ 5688,5928, 5696,7424, 5704,6440, 5712,7488, 5720,6952, 5728,7456,
+ 5736,7464, 5744,7520, 5752,7976, 5760,7296, 5768,7328, 5776,7552,
+ 5784,7584, 5792,7304, 5800,7336, 5808,7560, 5816,5992, 5824,7312,
+ 5832,6504, 5840,7568, 5848,7016, 5856,7320, 5864,7528, 5872,7576,
+ 5880,8040, 5888,7184, 5896,7192, 5904,7248, 5912,7256, 5920,6248,
+ 5928,7272, 5936,6376, 5944,6056, 5952,7440, 5960,6568, 5968,7504,
+ 5976,7080, 5984,6760, 5992,7592, 6000,6888, 6008,8104, 6016,7360,
+ 6024,7392, 6032,7616, 6040,7648, 6048,7368, 6056,7400, 6064,7624,
+ 6072,6120, 6080,7376, 6088,6632, 6096,7632, 6104,7144, 6112,7384,
+ 6120,7656, 6128,7640, 6136,8168, 6168,6240, 6192,6216, 6200,7264,
+ 6232,6704, 6248,7216, 6256,6680, 6264,7728, 6272,6656, 6280,6664,
+ 6288,6912, 6296,6496, 6304,6688, 6312,6696, 6320,6944, 6328,7520,
+ 6336,6672, 6344,6680, 6352,6928, 6360,6768, 6368,6704, 6376,7280,
+ 6384,6744, 6392,7792, 6408,6432, 6424,6752, 6440,7432, 6448,6536,
+ 6456,7560, 6472,6944, 6488,6832, 6496,6920, 6504,7344, 6512,7048,
+ 6520,7856, 6528,6720, 6536,6728, 6544,6976, 6552,7008, 6560,6752,
+ 6568,7448, 6576,7008, 6584,7576, 6592,6736, 6600,6744, 6608,6992,
+ 6616,6896, 6624,6936, 6632,7408, 6640,7064, 6648,7920, 6712,7280,
+ 6744,6960, 6760,7472, 6768,6936, 6776,7984, 6800,6848, 6808,6856,
+ 6832,6880, 6840,6888, 6848,7040, 6856,7048, 6864,7104, 6872,7024,
+ 6880,7072, 6888,7536, 6896,7136, 6904,8048, 6952,7496, 6968,7624,
+ 6984,7008, 7000,7088, 7016,7600, 7024,7112, 7032,8112, 7056,7104,
+ 7064,7112, 7080,7512, 7088,7136, 7096,7640, 7128,7152, 7144,7664,
+ 7160,8176, 7176,7200, 7192,7216, 7224,7272, 7240,7264, 7256,7280,
+ 7288,7736, 7296,7680, 7304,7712, 7312,7936, 7320,7968, 7328,7688,
+ 7336,7720, 7344,7944, 7352,7976, 7360,7696, 7368,7728, 7376,7952,
+ 7384,7984, 7392,7704, 7400,7736, 7408,7960, 7416,7800, 7432,7456,
+ 7448,7472, 7480,7592, 7496,7520, 7512,7536, 7528,7976, 7544,7864,
+ 7552,7744, 7560,7776, 7568,8000, 7576,8032, 7584,7752, 7592,7784,
+ 7600,8008, 7608,8040, 7616,7760, 7624,7792, 7632,8016, 7640,8048,
+ 7648,7768, 7656,7800, 7664,8024, 7672,7928, 7688,7712, 7704,7728,
+ 7752,7776, 7768,7792, 7800,7992, 7816,7840, 7824,8064, 7832,8096,
+ 7856,8072, 7864,8104, 7872,8064, 7880,8072, 7888,8080, 7896,8112,
+ 7904,8096, 7912,8104, 7920,8088, 7928,8056, 7944,7968, 7960,7984,
+ 8008,8032, 8024,8048, 8056,8120, 8072,8096, 8080,8128, 8088,8160,
+ 8112,8136, 8120,8168, 8136,8160, 8152,8176
+};
+
+const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH] =
+{
+ //8x2, size 3808
+ 8,4096, 16,8192, 24,12288, 32,512, 40,4608, 48,8704, 56,12800, 64,1024,
+ 72,5120, 80,9216, 88,13312, 96,1536, 104,5632, 112,9728, 120,13824,
+ 128,2048, 136,6144, 144,10240, 152,14336, 160,2560, 168,6656, 176,10752,
+ 184,14848, 192,3072, 200,7168, 208,11264, 216,15360, 224,3584, 232,7680,
+ 240,11776, 248,15872, 256,1024, 264,4160, 272,8256, 280,12352, 288,576,
+ 296,4672, 304,8768, 312,12864, 320,1088, 328,5184, 336,9280, 344,13376,
+ 352,1600, 360,5696, 368,9792, 376,13888, 384,2112, 392,6208, 400,10304,
+ 408,14400, 416,2624, 424,6720, 432,10816, 440,14912, 448,3136, 456,7232,
+ 464,11328, 472,15424, 480,3648, 488,7744, 496,11840, 504,15936, 512,2048,
+ 520,4224, 528,8320, 536,12416, 544,640, 552,4736, 560,8832, 568,12928,
+ 576,1152, 584,5248, 592,9344, 600,13440, 608,1664, 616,5760, 624,9856,
+ 632,13952, 640,2176, 648,6272, 656,10368, 664,14464, 672,2688, 680,6784,
+ 688,10880, 696,14976, 704,3200, 712,7296, 720,11392, 728,15488, 736,3712,
+ 744,7808, 752,11904, 760,16000, 768,3072, 776,4288, 784,8384, 792,12480,
+ 800,3200, 808,4800, 816,8896, 824,12992, 832,1216, 840,5312, 848,9408,
+ 856,13504, 864,1728, 872,5824, 880,9920, 888,14016, 896,2240, 904,6336,
+ 912,10432, 920,14528, 928,2752, 936,6848, 944,10944, 952,15040, 960,3264,
+ 968,7360, 976,11456, 984,15552, 992,3776, 1000,7872, 1008,11968, 1016,16064,
+ 1032,4352, 1040,8448, 1048,12544, 1056,3072, 1064,4864, 1072,8960,
+ 1080,13056, 1088,1280, 1096,5376, 1104,9472, 1112,13568, 1120,1792,
+ 1128,5888, 1136,9984, 1144,14080, 1152,2304, 1160,6400, 1168,10496,
+ 1176,14592, 1184,2816, 1192,6912, 1200,11008, 1208,15104, 1216,3328,
+ 1224,7424, 1232,11520, 1240,15616, 1248,3840, 1256,7936, 1264,12032,
+ 1272,16128, 1288,4416, 1296,8512, 1304,12608, 1312,3328, 1320,4928,
+ 1328,9024, 1336,13120, 1352,5440, 1360,9536, 1368,13632, 1376,1856,
+ 1384,5952, 1392,10048, 1400,14144, 1408,2368, 1416,6464, 1424,10560,
+ 1432,14656, 1440,2880, 1448,6976, 1456,11072, 1464,15168, 1472,3392,
+ 1480,7488, 1488,11584, 1496,15680, 1504,3904, 1512,8000, 1520,12096,
+ 1528,16192, 1536,2112, 1544,4480, 1552,8576, 1560,12672, 1568,2240,
+ 1576,4992, 1584,9088, 1592,13184, 1600,2368, 1608,5504, 1616,9600,
+ 1624,13696, 1632,1920, 1640,6016, 1648,10112, 1656,14208, 1664,2432,
+ 1672,6528, 1680,10624, 1688,14720, 1696,2944, 1704,7040, 1712,11136,
+ 1720,15232, 1728,3456, 1736,7552, 1744,11648, 1752,15744, 1760,3968,
+ 1768,8064, 1776,12160, 1784,16256, 1792,3136, 1800,4544, 1808,8640,
+ 1816,12736, 1824,3264, 1832,5056, 1840,9152, 1848,13248, 1856,3392,
+ 1864,5568, 1872,9664, 1880,13760, 1888,1984, 1896,6080, 1904,10176,
+ 1912,14272, 1920,2496, 1928,6592, 1936,10688, 1944,14784, 1952,3008,
+ 1960,7104, 1968,11200, 1976,15296, 1984,3520, 1992,7616, 2000,11712,
+ 2008,15808, 2016,4032, 2024,8128, 2032,12224, 2040,16320, 2048,4096,
+ 2056,4104, 2064,8200, 2072,12296, 2080,4224, 2088,4616, 2096,8712,
+ 2104,12808, 2112,4352, 2120,5128, 2128,9224, 2136,13320, 2144,4480,
+ 2152,5640, 2160,9736, 2168,13832, 2176,4104, 2184,6152, 2192,10248,
+ 2200,14344, 2208,2568, 2216,6664, 2224,10760, 2232,14856, 2240,3080,
+ 2248,7176, 2256,11272, 2264,15368, 2272,3592, 2280,7688, 2288,11784,
+ 2296,15880, 2304,5120, 2312,4168, 2320,8264, 2328,12360, 2336,5248,
+ 2344,4680, 2352,8776, 2360,12872, 2368,5376, 2376,5192, 2384,9288,
+ 2392,13384, 2400,5504, 2408,5704, 2416,9800, 2424,13896, 2432,5128,
+ 2440,6216, 2448,10312, 2456,14408, 2464,2632, 2472,6728, 2480,10824,
+ 2488,14920, 2496,3144, 2504,7240, 2512,11336, 2520,15432, 2528,3656,
+ 2536,7752, 2544,11848, 2552,15944, 2560,6144, 2568,4232, 2576,8328,
+ 2584,12424, 2592,6272, 2600,4744, 2608,8840, 2616,12936, 2624,6400,
+ 2632,5256, 2640,9352, 2648,13448, 2656,6528, 2664,5768, 2672,9864,
+ 2680,13960, 2688,6152, 2696,6280, 2704,10376, 2712,14472, 2720,6280,
+ 2728,6792, 2736,10888, 2744,14984, 2752,3208, 2760,7304, 2768,11400,
+ 2776,15496, 2784,3720, 2792,7816, 2800,11912, 2808,16008, 2816,7168,
+ 2824,4296, 2832,8392, 2840,12488, 2848,7296, 2856,4808, 2864,8904,
+ 2872,13000, 2880,7424, 2888,5320, 2896,9416, 2904,13512, 2912,7552,
+ 2920,5832, 2928,9928, 2936,14024, 2944,7176, 2952,6344, 2960,10440,
+ 2968,14536, 2976,7304, 2984,6856, 2992,10952, 3000,15048, 3008,3272,
+ 3016,7368, 3024,11464, 3032,15560, 3040,3784, 3048,7880, 3056,11976,
+ 3064,16072, 3072,4160, 3080,4360, 3088,8456, 3096,12552, 3104,4288,
+ 3112,4872, 3120,8968, 3128,13064, 3136,4416, 3144,5384, 3152,9480,
+ 3160,13576, 3168,4544, 3176,5896, 3184,9992, 3192,14088, 3200,4168,
+ 3208,6408, 3216,10504, 3224,14600, 3232,4296, 3240,6920, 3248,11016,
+ 3256,15112, 3264,3336, 3272,7432, 3280,11528, 3288,15624, 3296,3848,
+ 3304,7944, 3312,12040, 3320,16136, 3328,5184, 3336,4424, 3344,8520,
+ 3352,12616, 3360,5312, 3368,4936, 3376,9032, 3384,13128, 3392,5440,
+ 3400,5448, 3408,9544, 3416,13640, 3424,5568, 3432,5960, 3440,10056,
+ 3448,14152, 3456,5192, 3464,6472, 3472,10568, 3480,14664, 3488,5320,
+ 3496,6984, 3504,11080, 3512,15176, 3520,5448, 3528,7496, 3536,11592,
+ 3544,15688, 3552,3912, 3560,8008, 3568,12104, 3576,16200, 3584,6208,
+ 3592,4488, 3600,8584, 3608,12680, 3616,6336, 3624,5000, 3632,9096,
+ 3640,13192, 3648,6464, 3656,5512, 3664,9608, 3672,13704, 3680,6592,
+ 3688,6024, 3696,10120, 3704,14216, 3712,6216, 3720,6536, 3728,10632,
+ 3736,14728, 3744,6344, 3752,7048, 3760,11144, 3768,15240, 3776,6472,
+ 3784,7560, 3792,11656, 3800,15752, 3808,3976, 3816,8072, 3824,12168,
+ 3832,16264, 3840,7232, 3848,4552, 3856,8648, 3864,12744, 3872,7360,
+ 3880,5064, 3888,9160, 3896,13256, 3904,7488, 3912,5576, 3920,9672,
+ 3928,13768, 3936,7616, 3944,6088, 3952,10184, 3960,14280, 3968,7240,
+ 3976,6600, 3984,10696, 3992,14792, 4000,7368, 4008,7112, 4016,11208,
+ 4024,15304, 4032,7496, 4040,7624, 4048,11720, 4056,15816, 4064,7624,
+ 4072,8136, 4080,12232, 4088,16328, 4096,8192, 4104,4112, 4112,8208,
+ 4120,12304, 4128,8320, 4136,4624, 4144,8720, 4152,12816, 4160,8448,
+ 4168,5136, 4176,9232, 4184,13328, 4192,8576, 4200,5648, 4208,9744,
+ 4216,13840, 4224,8200, 4232,6160, 4240,10256, 4248,14352, 4256,8328,
+ 4264,6672, 4272,10768, 4280,14864, 4288,8456, 4296,7184, 4304,11280,
+ 4312,15376, 4320,8584, 4328,7696, 4336,11792, 4344,15888, 4352,9216,
+ 4360,9232, 4368,8272, 4376,12368, 4384,9344, 4392,4688, 4400,8784,
+ 4408,12880, 4416,9472, 4424,5200, 4432,9296, 4440,13392, 4448,9600,
+ 4456,5712, 4464,9808, 4472,13904, 4480,9224, 4488,6224, 4496,10320,
+ 4504,14416, 4512,9352, 4520,6736, 4528,10832, 4536,14928, 4544,9480,
+ 4552,7248, 4560,11344, 4568,15440, 4576,9608, 4584,7760, 4592,11856,
+ 4600,15952, 4608,10240, 4616,10256, 4624,8336, 4632,12432, 4640,10368,
+ 4648,4752, 4656,8848, 4664,12944, 4672,10496, 4680,5264, 4688,9360,
+ 4696,13456, 4704,10624, 4712,5776, 4720,9872, 4728,13968, 4736,10248,
+ 4744,6288, 4752,10384, 4760,14480, 4768,10376, 4776,6800, 4784,10896,
+ 4792,14992, 4800,10504, 4808,7312, 4816,11408, 4824,15504, 4832,10632,
+ 4840,7824, 4848,11920, 4856,16016, 4864,11264, 4872,11280, 4880,8400,
+ 4888,12496, 4896,11392, 4904,11408, 4912,8912, 4920,13008, 4928,11520,
+ 4936,5328, 4944,9424, 4952,13520, 4960,11648, 4968,5840, 4976,9936,
+ 4984,14032, 4992,11272, 5000,6352, 5008,10448, 5016,14544, 5024,11400,
+ 5032,6864, 5040,10960, 5048,15056, 5056,11528, 5064,7376, 5072,11472,
+ 5080,15568, 5088,11656, 5096,7888, 5104,11984, 5112,16080, 5120,8256,
+ 5128,8272, 5136,8464, 5144,12560, 5152,8384, 5160,8400, 5168,8976,
+ 5176,13072, 5184,8512, 5192,5392, 5200,9488, 5208,13584, 5216,8640,
+ 5224,5904, 5232,10000, 5240,14096, 5248,8264, 5256,6416, 5264,10512,
+ 5272,14608, 5280,8392, 5288,6928, 5296,11024, 5304,15120, 5312,8520,
+ 5320,7440, 5328,11536, 5336,15632, 5344,8648, 5352,7952, 5360,12048,
+ 5368,16144, 5376,9280, 5384,9296, 5392,8528, 5400,12624, 5408,9408,
+ 5416,9424, 5424,9040, 5432,13136, 5440,9536, 5448,5456, 5456,9552,
+ 5464,13648, 5472,9664, 5480,5968, 5488,10064, 5496,14160, 5504,9288,
+ 5512,6480, 5520,10576, 5528,14672, 5536,9416, 5544,6992, 5552,11088,
+ 5560,15184, 5568,9544, 5576,7504, 5584,11600, 5592,15696, 5600,9672,
+ 5608,8016, 5616,12112, 5624,16208, 5632,10304, 5640,10320, 5648,8592,
+ 5656,12688, 5664,10432, 5672,10448, 5680,9104, 5688,13200, 5696,10560,
+ 5704,10576, 5712,9616, 5720,13712, 5728,10688, 5736,6032, 5744,10128,
+ 5752,14224, 5760,10312, 5768,6544, 5776,10640, 5784,14736, 5792,10440,
+ 5800,7056, 5808,11152, 5816,15248, 5824,10568, 5832,7568, 5840,11664,
+ 5848,15760, 5856,10696, 5864,8080, 5872,12176, 5880,16272, 5888,11328,
+ 5896,11344, 5904,8656, 5912,12752, 5920,11456, 5928,11472, 5936,9168,
+ 5944,13264, 5952,11584, 5960,11600, 5968,9680, 5976,13776, 5984,11712,
+ 5992,6096, 6000,10192, 6008,14288, 6016,11336, 6024,6608, 6032,10704,
+ 6040,14800, 6048,11464, 6056,7120, 6064,11216, 6072,15312, 6080,11592,
+ 6088,7632, 6096,11728, 6104,15824, 6112,11720, 6120,8144, 6128,12240,
+ 6136,16336, 6144,12288, 6152,12304, 6160,8216, 6168,12312, 6176,12416,
+ 6184,12432, 6192,8728, 6200,12824, 6208,12544, 6216,12560, 6224,9240,
+ 6232,13336, 6240,12672, 6248,12688, 6256,9752, 6264,13848, 6272,12296,
+ 6280,12312, 6288,10264, 6296,14360, 6304,12424, 6312,6680, 6320,10776,
+ 6328,14872, 6336,12552, 6344,7192, 6352,11288, 6360,15384, 6368,12680,
+ 6376,7704, 6384,11800, 6392,15896, 6400,13312, 6408,13328, 6416,8280,
+ 6424,12376, 6432,13440, 6440,13456, 6448,8792, 6456,12888, 6464,13568,
+ 6472,13584, 6480,9304, 6488,13400, 6496,13696, 6504,13712, 6512,9816,
+ 6520,13912, 6528,13320, 6536,13336, 6544,10328, 6552,14424, 6560,13448,
+ 6568,6744, 6576,10840, 6584,14936, 6592,13576, 6600,7256, 6608,11352,
+ 6616,15448, 6624,13704, 6632,7768, 6640,11864, 6648,15960, 6656,14336,
+ 6664,14352, 6672,8344, 6680,12440, 6688,14464, 6696,14480, 6704,8856,
+ 6712,12952, 6720,14592, 6728,14608, 6736,9368, 6744,13464, 6752,14720,
+ 6760,14736, 6768,9880, 6776,13976, 6784,14344, 6792,14360, 6800,10392,
+ 6808,14488, 6816,14472, 6824,14488, 6832,10904, 6840,15000, 6848,14600,
+ 6856,7320, 6864,11416, 6872,15512, 6880,14728, 6888,7832, 6896,11928,
+ 6904,16024, 6912,15360, 6920,15376, 6928,8408, 6936,12504, 6944,15488,
+ 6952,15504, 6960,8920, 6968,13016, 6976,15616, 6984,15632, 6992,9432,
+ 7000,13528, 7008,15744, 7016,15760, 7024,9944, 7032,14040, 7040,15368,
+ 7048,15384, 7056,10456, 7064,14552, 7072,15496, 7080,15512, 7088,10968,
+ 7096,15064, 7104,15624, 7112,7384, 7120,11480, 7128,15576, 7136,15752,
+ 7144,7896, 7152,11992, 7160,16088, 7168,12352, 7176,12368, 7184,8472,
+ 7192,12568, 7200,12480, 7208,12496, 7216,8984, 7224,13080, 7232,12608,
+ 7240,12624, 7248,9496, 7256,13592, 7264,12736, 7272,12752, 7280,10008,
+ 7288,14104, 7296,12360, 7304,12376, 7312,10520, 7320,14616, 7328,12488,
+ 7336,12504, 7344,11032, 7352,15128, 7360,12616, 7368,7448, 7376,11544,
+ 7384,15640, 7392,12744, 7400,7960, 7408,12056, 7416,16152, 7424,13376,
+ 7432,13392, 7440,8536, 7448,12632, 7456,13504, 7464,13520, 7472,9048,
+ 7480,13144, 7488,13632, 7496,13648, 7504,9560, 7512,13656, 7520,13760,
+ 7528,13776, 7536,10072, 7544,14168, 7552,13384, 7560,13400, 7568,10584,
+ 7576,14680, 7584,13512, 7592,13528, 7600,11096, 7608,15192, 7616,13640,
+ 7624,13656, 7632,11608, 7640,15704, 7648,13768, 7656,8024, 7664,12120,
+ 7672,16216, 7680,14400, 7688,14416, 7696,8600, 7704,12696, 7712,14528,
+ 7720,14544, 7728,9112, 7736,13208, 7744,14656, 7752,14672, 7760,9624,
+ 7768,13720, 7776,14784, 7784,14800, 7792,10136, 7800,14232, 7808,14408,
+ 7816,14424, 7824,10648, 7832,14744, 7840,14536, 7848,14552, 7856,11160,
+ 7864,15256, 7872,14664, 7880,14680, 7888,11672, 7896,15768, 7904,14792,
+ 7912,8088, 7920,12184, 7928,16280, 7936,15424, 7944,15440, 7952,8664,
+ 7960,12760, 7968,15552, 7976,15568, 7984,9176, 7992,13272, 8000,15680,
+ 8008,15696, 8016,9688, 8024,13784, 8032,15808, 8040,15824, 8048,10200,
+ 8056,14296, 8064,15432, 8072,15448, 8080,10712, 8088,14808, 8096,15560,
+ 8104,15576, 8112,11224, 8120,15320, 8128,15688, 8136,15704, 8144,11736,
+ 8152,15832, 8160,15816, 8168,15832, 8176,12248, 8184,16344, 8200,8320,
+ 8208,8224, 8216,12320, 8232,10368, 8240,8736, 8248,12832, 8256,8448,
+ 8264,8384, 8272,9248, 8280,13344, 8288,9232, 8296,10432, 8304,9760,
+ 8312,13856, 8328,12416, 8336,10272, 8344,14368, 8352,12296, 8360,14464,
+ 8368,10784, 8376,14880, 8384,8456, 8392,12480, 8400,11296, 8408,15392,
+ 8416,12552, 8424,14528, 8432,11808, 8440,15904, 8448,9216, 8456,8576,
+ 8464,9232, 8472,12384, 8480,9248, 8488,10624, 8496,8800, 8504,12896,
+ 8512,9472, 8520,8640, 8528,9312, 8536,13408, 8544,9296, 8552,10688,
+ 8560,9824, 8568,13920, 8576,9224, 8584,12672, 8592,10336, 8600,14432,
+ 8608,13320, 8616,14720, 8624,10848, 8632,14944, 8640,9480, 8648,12736,
+ 8656,11360, 8664,15456, 8672,13576, 8680,14784, 8688,11872, 8696,15968,
+ 8704,12288, 8712,12416, 8720,12296, 8728,12448, 8736,12304, 8744,10376,
+ 8752,8864, 8760,12960, 8768,12352, 8776,12480, 8784,9376, 8792,13472,
+ 8800,12368, 8808,10440, 8816,9888, 8824,13984, 8832,12320, 8840,12424,
+ 8848,10400, 8856,14496, 8864,12312, 8872,14472, 8880,10912, 8888,15008,
+ 8896,12384, 8904,12488, 8912,11424, 8920,15520, 8928,12568, 8936,14536,
+ 8944,11936, 8952,16032, 8960,12544, 8968,12672, 8976,12552, 8984,12512,
+ 8992,12560, 9000,10632, 9008,12568, 9016,13024, 9024,12608, 9032,12736,
+ 9040,9440, 9048,13536, 9056,12624, 9064,10696, 9072,9952, 9080,14048,
+ 9088,9240, 9096,12680, 9104,10464, 9112,14560, 9120,13336, 9128,14728,
+ 9136,10976, 9144,15072, 9152,9496, 9160,12744, 9168,11488, 9176,15584,
+ 9184,13592, 9192,14792, 9200,12000, 9208,16096, 9224,9344, 9232,9248,
+ 9240,12576, 9256,11392, 9264,12560, 9272,13088, 9280,9472, 9288,9408,
+ 9296,9504, 9304,13600, 9312,9488, 9320,11456, 9328,10016, 9336,14112,
+ 9352,13440, 9360,10528, 9368,14624, 9376,12360, 9384,15488, 9392,11040,
+ 9400,15136, 9408,9480, 9416,13504, 9424,11552, 9432,15648, 9440,12616,
+ 9448,15552, 9456,12064, 9464,16160, 9480,9600, 9488,9504, 9496,12640,
+ 9512,11648, 9520,12624, 9528,13152, 9544,9664, 9552,9568, 9560,13664,
+ 9576,11712, 9584,10080, 9592,14176, 9608,13696, 9616,10592, 9624,14688,
+ 9632,13384, 9640,15744, 9648,11104, 9656,15200, 9672,13760, 9680,11616,
+ 9688,15712, 9696,13640, 9704,15808, 9712,12128, 9720,16224, 9728,13312,
+ 9736,13440, 9744,13320, 9752,12704, 9760,13328, 9768,11400, 9776,13336,
+ 9784,13216, 9792,13376, 9800,13504, 9808,13384, 9816,13728, 9824,13392,
+ 9832,11464, 9840,10144, 9848,14240, 9856,13344, 9864,13448, 9872,10656,
+ 9880,14752, 9888,12376, 9896,15496, 9904,11168, 9912,15264, 9920,13408,
+ 9928,13512, 9936,11680, 9944,15776, 9952,12632, 9960,15560, 9968,12192,
+ 9976,16288, 9984,13568, 9992,13696, 10000,13576, 10008,12768, 10016,13584,
+ 10024,11656, 10032,13592, 10040,13280, 10048,13632, 10056,13760,
+ 10064,13640, 10072,13792, 10080,13648, 10088,11720, 10096,10208,
+ 10104,14304, 10112,13600, 10120,13704, 10128,10720, 10136,14816,
+ 10144,13400, 10152,15752, 10160,11232, 10168,15328, 10176,13664,
+ 10184,13768, 10192,11744, 10200,15840, 10208,13656, 10216,15816,
+ 10224,12256, 10232,16352, 10248,10272, 10256,10368, 10264,12328,
+ 10280,10384, 10288,10376, 10296,12840, 10304,11264, 10312,11296,
+ 10320,11392, 10328,13352, 10336,11272, 10344,10448, 10352,11400,
+ 10360,13864, 10376,12432, 10392,14376, 10400,12328, 10408,14480,
+ 10416,10792, 10424,14888, 10432,11280, 10440,12496, 10448,11304,
+ 10456,15400, 10464,11288, 10472,14544, 10480,11816, 10488,15912,
+ 10496,11264, 10504,11272, 10512,11280, 10520,12392, 10528,11296,
+ 10536,10640, 10544,12496, 10552,12904, 10560,11328, 10568,11360,
+ 10576,11456, 10584,13416, 10592,11336, 10600,10704, 10608,11464,
+ 10616,13928, 10624,11392, 10632,12688, 10640,11304, 10648,14440,
+ 10656,13352, 10664,14736, 10672,10856, 10680,14952, 10688,11344,
+ 10696,12752, 10704,11368, 10712,15464, 10720,11352, 10728,14800,
+ 10736,11880, 10744,15976, 10752,14336, 10760,14368, 10768,14464,
+ 10776,12456, 10784,14344, 10792,14376, 10800,14472, 10808,12968,
+ 10816,15360, 10824,15392, 10832,15488, 10840,13480, 10848,15368,
+ 10856,15400, 10864,15496, 10872,13992, 10880,14352, 10888,12440,
+ 10896,14480, 10904,14504, 10912,14360, 10920,14488, 10928,14488,
+ 10936,15016, 10944,15376, 10952,12504, 10960,11432, 10968,15528,
+ 10976,15384, 10984,14552, 10992,11944, 11000,16040, 11008,14400,
+ 11016,14432, 11024,14528, 11032,12520, 11040,14408, 11048,14440,
+ 11056,14536, 11064,13032, 11072,15424, 11080,15456, 11088,15552,
+ 11096,13544, 11104,15432, 11112,15464, 11120,15560, 11128,14056,
+ 11136,14416, 11144,12696, 11152,14544, 11160,14568, 11168,14424,
+ 11176,14744, 11184,14552, 11192,15080, 11200,15440, 11208,12760,
+ 11216,11496, 11224,15592, 11232,15448, 11240,14808, 11248,12008,
+ 11256,16104, 11272,11296, 11280,11392, 11288,12584, 11304,11408,
+ 11312,12688, 11320,13096, 11328,11520, 11336,11552, 11344,11648,
+ 11352,13608, 11360,11528, 11368,11472, 11376,11656, 11384,14120,
+ 11400,13456, 11416,14632, 11424,12392, 11432,15504, 11440,14440,
+ 11448,15144, 11456,11536, 11464,13520, 11472,11560, 11480,15656,
+ 11488,11544, 11496,15568, 11504,12072, 11512,16168, 11528,11552,
+ 11536,11648, 11544,12648, 11560,11664, 11568,12752, 11576,13160,
+ 11592,11616, 11600,11712, 11608,13672, 11624,11728, 11632,11720,
+ 11640,14184, 11656,13712, 11672,14696, 11680,13416, 11688,15760,
+ 11696,15464, 11704,15208, 11720,13776, 11736,15720, 11744,13672,
+ 11752,15824, 11760,12136, 11768,16232, 11776,14592, 11784,14624,
+ 11792,14720, 11800,12712, 11808,14600, 11816,14632, 11824,14728,
+ 11832,13224, 11840,15616, 11848,15648, 11856,15744, 11864,13736,
+ 11872,15624, 11880,15656, 11888,15752, 11896,14248, 11904,14608,
+ 11912,13464, 11920,14736, 11928,14760, 11936,14616, 11944,15512,
+ 11952,14744, 11960,15272, 11968,15632, 11976,13528, 11984,15760,
+ 11992,15784, 12000,15640, 12008,15576, 12016,12200, 12024,16296,
+ 12032,14656, 12040,14688, 12048,14784, 12056,12776, 12064,14664,
+ 12072,14696, 12080,14792, 12088,13288, 12096,15680, 12104,15712,
+ 12112,15808, 12120,13800, 12128,15688, 12136,15720, 12144,15816,
+ 12152,14312, 12160,14672, 12168,13720, 12176,14800, 12184,14824,
+ 12192,14680, 12200,15768, 12208,14808, 12216,15336, 12224,15696,
+ 12232,13784, 12240,15824, 12248,15848, 12256,15704, 12264,15832,
+ 12272,15832, 12280,16360, 12312,12336, 12344,12848, 12352,12544,
+ 12360,12552, 12368,12560, 12376,13360, 12384,12576, 12392,12584,
+ 12400,13336, 12408,13872, 12424,12448, 12440,14384, 12456,14496,
+ 12464,14472, 12472,14896, 12480,12672, 12488,12512, 12496,12688,
+ 12504,15408, 12512,12680, 12520,14560, 12528,14728, 12536,15920,
+ 12544,13312, 12552,13320, 12560,13328, 12568,13336, 12576,13344,
+ 12584,13352, 12592,13360, 12600,12912, 12608,13568, 12616,13576,
+ 12624,13584, 12632,13424, 12640,13600, 12648,13608, 12656,13400,
+ 12664,13936, 12672,13440, 12680,12704, 12688,13456, 12696,14448,
+ 12704,13448, 12712,14752, 12720,15496, 12728,14960, 12736,13696,
+ 12744,12768, 12752,13712, 12760,15472, 12768,13704, 12776,14816,
+ 12784,15752, 12792,15984, 12800,14336, 12808,14464, 12816,14344,
+ 12824,14472, 12832,14352, 12840,14480, 12848,14360, 12856,12976,
+ 12864,14400, 12872,14528, 12880,14408, 12888,13488, 12896,14416,
+ 12904,14544, 12912,14424, 12920,14000, 12928,14368, 12936,14496,
+ 12944,14376, 12952,14512, 12960,14384, 12968,14504, 12976,14488,
+ 12984,15024, 12992,14432, 13000,14560, 13008,14440, 13016,15536,
+ 13024,14448, 13032,14568, 13040,14744, 13048,16048, 13056,14592,
+ 13064,14720, 13072,14600, 13080,14728, 13088,14608, 13096,14736,
+ 13104,14616, 13112,14744, 13120,14656, 13128,14784, 13136,14664,
+ 13144,13552, 13152,14672, 13160,14800, 13168,14680, 13176,14064,
+ 13184,14624, 13192,14752, 13200,14632, 13208,14576, 13216,13464,
+ 13224,14760, 13232,15512, 13240,15088, 13248,14688, 13256,14816,
+ 13264,14696, 13272,15600, 13280,13720, 13288,14824, 13296,15768,
+ 13304,16112, 13336,13360, 13368,14616, 13376,13568, 13384,13576,
+ 13392,13584, 13400,13616, 13408,13600, 13416,13608, 13424,13592,
+ 13432,14128, 13448,13472, 13464,14640, 13480,15520, 13488,14536,
+ 13496,15152, 13504,13696, 13512,13536, 13520,13712, 13528,15664,
+ 13536,13704, 13544,15584, 13552,14792, 13560,16176, 13592,13616,
+ 13624,14680, 13656,13680, 13688,14192, 13704,13728, 13720,14704,
+ 13736,15776, 13744,15560, 13752,15216, 13768,13792, 13784,15728,
+ 13800,15840, 13808,15816, 13816,16240, 13824,15360, 13832,15488,
+ 13840,15368, 13848,15496, 13856,15376, 13864,15504, 13872,15384,
+ 13880,15512, 13888,15424, 13896,15552, 13904,15432, 13912,15560,
+ 13920,15440, 13928,15568, 13936,15448, 13944,14256, 13952,15392,
+ 13960,15520, 13968,15400, 13976,14768, 13984,15408, 13992,15528,
+ 14000,14552, 14008,15280, 14016,15456, 14024,15584, 14032,15464,
+ 14040,15792, 14048,15472, 14056,15592, 14064,14808, 14072,16304,
+ 14080,15616, 14088,15744, 14096,15624, 14104,15752, 14112,15632,
+ 14120,15760, 14128,15640, 14136,15768, 14144,15680, 14152,15808,
+ 14160,15688, 14168,15816, 14176,15696, 14184,15824, 14192,15704,
+ 14200,14320, 14208,15648, 14216,15776, 14224,15656, 14232,14832,
+ 14240,15664, 14248,15784, 14256,15576, 14264,15344, 14272,15712,
+ 14280,15840, 14288,15720, 14296,15856, 14304,15728, 14312,15848,
+ 14320,15832, 14328,16368, 14392,14488, 14400,14592, 14408,14600,
+ 14416,14608, 14424,14616, 14432,14624, 14440,14632, 14448,14640,
+ 14456,15512, 14504,14512, 14520,14904, 14528,14720, 14536,14728,
+ 14544,14736, 14552,15416, 14560,14752, 14568,14576, 14584,15928,
+ 14576,14760, 14592,15360, 14600,15368, 14608,15376, 14616,15384,
+ 14624,15392, 14632,15400, 14640,15408, 14648,15416, 14656,15616,
+ 14664,15624, 14672,15632, 14680,15640, 14688,15648, 14696,15656,
+ 14704,15664, 14712,15576, 14720,15488, 14728,15496, 14736,15504,
+ 14744,15512, 14752,15520, 14760,14768, 14776,14968, 14768,15528,
+ 14784,15744, 14792,15752, 14800,15760, 14808,15480, 14816,15776,
+ 14824,14832, 14840,15992, 14832,15784, 14856,14864, 14864,14880,
+ 14872,14896, 14880,14976, 14888,14992, 14896,15008, 14904,15024,
+ 14912,15104, 14920,15120, 14928,15136, 14936,15152, 14944,15232,
+ 14952,15248, 14960,15264, 14968,15280, 14984,15008, 15000,15024,
+ 15016,15024, 15040,15112, 15048,15128, 15056,15144, 15064,15544,
+ 15072,15240, 15080,15256, 15088,15272, 15096,16056, 15104,15872,
+ 15112,15888, 15120,15904, 15128,15920, 15136,16000, 15144,16016,
+ 15152,16032, 15160,16048, 15168,16128, 15176,16144, 15184,16160,
+ 15192,16176, 15200,16256, 15208,16272, 15216,16288, 15224,16304,
+ 15232,15880, 15240,15896, 15248,15912, 15256,15928, 15264,16008,
+ 15272,16024, 15280,16040, 15288,16056, 15296,16136, 15304,16152,
+ 15312,16168, 15320,15608, 15328,16264, 15336,16280, 15344,16296,
+ 15352,16120, 15416,15512, 15424,15616, 15432,15624, 15440,15632,
+ 15448,15640, 15456,15648, 15464,15656, 15472,15664, 15480,15768,
+ 15528,15536, 15544,16048, 15552,15744, 15560,15752, 15568,15760,
+ 15576,15672, 15584,15776, 15592,15600, 15600,15784, 15608,16184,
+ 15672,15768, 15736,15832, 15784,15792, 15800,16304, 15848,15856,
+ 15880,16000, 15864,16248, 15888,16000, 15896,16008, 15904,16000,
+ 15912,16016, 15920,16008, 15928,16024, 15936,16128, 15944,16160,
+ 15952,16256, 15960,16288, 15968,16136, 15976,16168, 15984,16264,
+ 15992,16296, 16008,16032, 16024,16040, 16064,16144, 16040,16048,
+ 16072,16176, 16080,16272, 16088,16304, 16096,16152, 16104,16184,
+ 16112,16280, 16136,16256, 16120,16312, 16144,16256, 16152,16264,
+ 16160,16256, 16168,16272, 16176,16264, 16184,16280, 16200,16208,
+ 16208,16224, 16216,16240, 16224,16320, 16232,16336, 16240,16352,
+ 16248,16368, 16264,16288, 16280,16296, 16296,16304, 16344,16368,
+ 16328,16352, 16360,16368
+};
+
+const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH] =
+{
+ //radix 8, size 4032
+ 8,4096, 16,8192, 24,12288, 32,16384, 40,20480, 48,24576, 56,28672, 64,512,
+ 72,4608, 80,8704, 88,12800, 96,16896, 104,20992, 112,25088, 120,29184,
+ 128,1024, 136,5120, 144,9216, 152,13312, 160,17408, 168,21504, 176,25600,
+ 184,29696, 192,1536, 200,5632, 208,9728, 216,13824, 224,17920, 232,22016,
+ 240,26112, 248,30208, 256,2048, 264,6144, 272,10240, 280,14336, 288,18432,
+ 296,22528, 304,26624, 312,30720, 320,2560, 328,6656, 336,10752, 344,14848,
+ 352,18944, 360,23040, 368,27136, 376,31232, 384,3072, 392,7168, 400,11264,
+ 408,15360, 416,19456, 424,23552, 432,27648, 440,31744, 448,3584, 456,7680,
+ 464,11776, 472,15872, 480,19968, 488,24064, 496,28160, 504,32256, 520,4160,
+ 528,8256, 536,12352, 544,16448, 552,20544, 560,24640, 568,28736, 584,4672,
+ 592,8768, 600,12864, 608,16960, 616,21056, 624,25152, 632,29248, 640,1088,
+ 648,5184, 656,9280, 664,13376, 672,17472, 680,21568, 688,25664, 696,29760,
+ 704,1600, 712,5696, 720,9792, 728,13888, 736,17984, 744,22080, 752,26176,
+ 760,30272, 768,2112, 776,6208, 784,10304, 792,14400, 800,18496, 808,22592,
+ 816,26688, 824,30784, 832,2624, 840,6720, 848,10816, 856,14912, 864,19008,
+ 872,23104, 880,27200, 888,31296, 896,3136, 904,7232, 912,11328, 920,15424,
+ 928,19520, 936,23616, 944,27712, 952,31808, 960,3648, 968,7744, 976,11840,
+ 984,15936, 992,20032, 1000,24128, 1008,28224, 1016,32320, 1032,4224,
+ 1040,8320, 1048,12416, 1056,16512, 1064,20608, 1072,24704, 1080,28800,
+ 1096,4736, 1104,8832, 1112,12928, 1120,17024, 1128,21120, 1136,25216,
+ 1144,29312, 1160,5248, 1168,9344, 1176,13440, 1184,17536, 1192,21632,
+ 1200,25728, 1208,29824, 1216,1664, 1224,5760, 1232,9856, 1240,13952,
+ 1248,18048, 1256,22144, 1264,26240, 1272,30336, 1280,2176, 1288,6272,
+ 1296,10368, 1304,14464, 1312,18560, 1320,22656, 1328,26752, 1336,30848,
+ 1344,2688, 1352,6784, 1360,10880, 1368,14976, 1376,19072, 1384,23168,
+ 1392,27264, 1400,31360, 1408,3200, 1416,7296, 1424,11392, 1432,15488,
+ 1440,19584, 1448,23680, 1456,27776, 1464,31872, 1472,3712, 1480,7808,
+ 1488,11904, 1496,16000, 1504,20096, 1512,24192, 1520,28288, 1528,32384,
+ 1544,4288, 1552,8384, 1560,12480, 1568,16576, 1576,20672, 1584,24768,
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+ 15088,26456, 15096,30552, 15136,18776, 15144,22872, 15152,26968,
+ 15160,31064, 15200,19288, 15208,23384, 15216,27480, 15224,31576,
+ 15256,15704, 15264,19800, 15272,23896, 15280,27992, 15288,32088,
+ 15320,16216, 15328,20312, 15336,24408, 15344,28504, 15352,32600,
+ 15392,16792, 15400,20888, 15408,24984, 15416,29080, 15456,17304,
+ 15464,21400, 15472,25496, 15480,29592, 15520,17816, 15528,21912,
+ 15536,26008, 15544,30104, 15584,18328, 15592,22424, 15600,26520,
+ 15608,30616, 15648,18840, 15656,22936, 15664,27032, 15672,31128,
+ 15712,19352, 15720,23448, 15728,27544, 15736,31640, 15776,19864,
+ 15784,23960, 15792,28056, 15800,32152, 15832,16280, 15840,20376,
+ 15848,24472, 15856,28568, 15864,32664, 15904,16856, 15912,20952,
+ 15920,25048, 15928,29144, 15968,17368, 15976,21464, 15984,25560,
+ 15992,29656, 16032,17880, 16040,21976, 16048,26072, 16056,30168,
+ 16096,18392, 16104,22488, 16112,26584, 16120,30680, 16160,18904,
+ 16168,23000, 16176,27096, 16184,31192, 16224,19416, 16232,23512,
+ 16240,27608, 16248,31704, 16288,19928, 16296,24024, 16304,28120,
+ 16312,32216, 16352,20440, 16360,24536, 16368,28632, 16376,32728,
+ 16424,20512, 16432,24608, 16440,28704, 16480,16928, 16488,21024,
+ 16496,25120, 16504,29216, 16544,17440, 16552,21536, 16560,25632,
+ 16568,29728, 16608,17952, 16616,22048, 16624,26144, 16632,30240,
+ 16672,18464, 16680,22560, 16688,26656, 16696,30752, 16736,18976,
+ 16744,23072, 16752,27168, 16760,31264, 16800,19488, 16808,23584,
+ 16816,27680, 16824,31776, 16864,20000, 16872,24096, 16880,28192,
+ 16888,32288, 16936,20576, 16944,24672, 16952,28768, 17000,21088,
+ 17008,25184, 17016,29280, 17056,17504, 17064,21600, 17072,25696,
+ 17080,29792, 17120,18016, 17128,22112, 17136,26208, 17144,30304,
+ 17184,18528, 17192,22624, 17200,26720, 17208,30816, 17248,19040,
+ 17256,23136, 17264,27232, 17272,31328, 17312,19552, 17320,23648,
+ 17328,27744, 17336,31840, 17376,20064, 17384,24160, 17392,28256,
+ 17400,32352, 17448,20640, 17456,24736, 17464,28832, 17512,21152,
+ 17520,25248, 17528,29344, 17576,21664, 17584,25760, 17592,29856,
+ 17632,18080, 17640,22176, 17648,26272, 17656,30368, 17696,18592,
+ 17704,22688, 17712,26784, 17720,30880, 17760,19104, 17768,23200,
+ 17776,27296, 17784,31392, 17824,19616, 17832,23712, 17840,27808,
+ 17848,31904, 17888,20128, 17896,24224, 17904,28320, 17912,32416,
+ 17960,20704, 17968,24800, 17976,28896, 18024,21216, 18032,25312,
+ 18040,29408, 18088,21728, 18096,25824, 18104,29920, 18152,22240,
+ 18160,26336, 18168,30432, 18208,18656, 18216,22752, 18224,26848,
+ 18232,30944, 18272,19168, 18280,23264, 18288,27360, 18296,31456,
+ 18336,19680, 18344,23776, 18352,27872, 18360,31968, 18400,20192,
+ 18408,24288, 18416,28384, 18424,32480, 18472,20768, 18480,24864,
+ 18488,28960, 18536,21280, 18544,25376, 18552,29472, 18600,21792,
+ 18608,25888, 18616,29984, 18664,22304, 18672,26400, 18680,30496,
+ 18728,22816, 18736,26912, 18744,31008, 18784,19232, 18792,23328,
+ 18800,27424, 18808,31520, 18848,19744, 18856,23840, 18864,27936,
+ 18872,32032, 18912,20256, 18920,24352, 18928,28448, 18936,32544,
+ 18984,20832, 18992,24928, 19000,29024, 19048,21344, 19056,25440,
+ 19064,29536, 19112,21856, 19120,25952, 19128,30048, 19176,22368,
+ 19184,26464, 19192,30560, 19240,22880, 19248,26976, 19256,31072,
+ 19304,23392, 19312,27488, 19320,31584, 19360,19808, 19368,23904,
+ 19376,28000, 19384,32096, 19424,20320, 19432,24416, 19440,28512,
+ 19448,32608, 19496,20896, 19504,24992, 19512,29088, 19560,21408,
+ 19568,25504, 19576,29600, 19624,21920, 19632,26016, 19640,30112,
+ 19688,22432, 19696,26528, 19704,30624, 19752,22944, 19760,27040,
+ 19768,31136, 19816,23456, 19824,27552, 19832,31648, 19880,23968,
+ 19888,28064, 19896,32160, 19936,20384, 19944,24480, 19952,28576,
+ 19960,32672, 20008,20960, 20016,25056, 20024,29152, 20072,21472,
+ 20080,25568, 20088,29664, 20136,21984, 20144,26080, 20152,30176,
+ 20200,22496, 20208,26592, 20216,30688, 20264,23008, 20272,27104,
+ 20280,31200, 20328,23520, 20336,27616, 20344,31712, 20392,24032,
+ 20400,28128, 20408,32224, 20456,24544, 20464,28640, 20472,32736,
+ 20528,24616, 20536,28712, 20584,21032, 20592,25128, 20600,29224,
+ 20648,21544, 20656,25640, 20664,29736, 20712,22056, 20720,26152,
+ 20728,30248, 20776,22568, 20784,26664, 20792,30760, 20840,23080,
+ 20848,27176, 20856,31272, 20904,23592, 20912,27688, 20920,31784,
+ 20968,24104, 20976,28200, 20984,32296, 21040,24680, 21048,28776,
+ 21104,25192, 21112,29288, 21160,21608, 21168,25704, 21176,29800,
+ 21224,22120, 21232,26216, 21240,30312, 21288,22632, 21296,26728,
+ 21304,30824, 21352,23144, 21360,27240, 21368,31336, 21416,23656,
+ 21424,27752, 21432,31848, 21480,24168, 21488,28264, 21496,32360,
+ 21552,24744, 21560,28840, 21616,25256, 21624,29352, 21680,25768,
+ 21688,29864, 21736,22184, 21744,26280, 21752,30376, 21800,22696,
+ 21808,26792, 21816,30888, 21864,23208, 21872,27304, 21880,31400,
+ 21928,23720, 21936,27816, 21944,31912, 21992,24232, 22000,28328,
+ 22008,32424, 22064,24808, 22072,28904, 22128,25320, 22136,29416,
+ 22192,25832, 22200,29928, 22256,26344, 22264,30440, 22312,22760,
+ 22320,26856, 22328,30952, 22376,23272, 22384,27368, 22392,31464,
+ 22440,23784, 22448,27880, 22456,31976, 22504,24296, 22512,28392,
+ 22520,32488, 22576,24872, 22584,28968, 22640,25384, 22648,29480,
+ 22704,25896, 22712,29992, 22768,26408, 22776,30504, 22832,26920,
+ 22840,31016, 22888,23336, 22896,27432, 22904,31528, 22952,23848,
+ 22960,27944, 22968,32040, 23016,24360, 23024,28456, 23032,32552,
+ 23088,24936, 23096,29032, 23152,25448, 23160,29544, 23216,25960,
+ 23224,30056, 23280,26472, 23288,30568, 23344,26984, 23352,31080,
+ 23408,27496, 23416,31592, 23464,23912, 23472,28008, 23480,32104,
+ 23528,24424, 23536,28520, 23544,32616, 23600,25000, 23608,29096,
+ 23664,25512, 23672,29608, 23728,26024, 23736,30120, 23792,26536,
+ 23800,30632, 23856,27048, 23864,31144, 23920,27560, 23928,31656,
+ 23984,28072, 23992,32168, 24040,24488, 24048,28584, 24056,32680,
+ 24112,25064, 24120,29160, 24176,25576, 24184,29672, 24240,26088,
+ 24248,30184, 24304,26600, 24312,30696, 24368,27112, 24376,31208,
+ 24432,27624, 24440,31720, 24496,28136, 24504,32232, 24560,28648,
+ 24568,32744, 24632,28720, 24688,25136, 24696,29232, 24752,25648,
+ 24760,29744, 24816,26160, 24824,30256, 24880,26672, 24888,30768,
+ 24944,27184, 24952,31280, 25008,27696, 25016,31792, 25072,28208,
+ 25080,32304, 25144,28784, 25208,29296, 25264,25712, 25272,29808,
+ 25328,26224, 25336,30320, 25392,26736, 25400,30832, 25456,27248,
+ 25464,31344, 25520,27760, 25528,31856, 25584,28272, 25592,32368,
+ 25656,28848, 25720,29360, 25784,29872, 25840,26288, 25848,30384,
+ 25904,26800, 25912,30896, 25968,27312, 25976,31408, 26032,27824,
+ 26040,31920, 26096,28336, 26104,32432, 26168,28912, 26232,29424,
+ 26296,29936, 26360,30448, 26416,26864, 26424,30960, 26480,27376,
+ 26488,31472, 26544,27888, 26552,31984, 26608,28400, 26616,32496,
+ 26680,28976, 26744,29488, 26808,30000, 26872,30512, 26936,31024,
+ 26992,27440, 27000,31536, 27056,27952, 27064,32048, 27120,28464,
+ 27128,32560, 27192,29040, 27256,29552, 27320,30064, 27384,30576,
+ 27448,31088, 27512,31600, 27568,28016, 27576,32112, 27632,28528,
+ 27640,32624, 27704,29104, 27768,29616, 27832,30128, 27896,30640,
+ 27960,31152, 28024,31664, 28088,32176, 28144,28592, 28152,32688,
+ 28216,29168, 28280,29680, 28344,30192, 28408,30704, 28472,31216,
+ 28536,31728, 28600,32240, 28664,32752, 28792,29240, 28856,29752,
+ 28920,30264, 28984,30776, 29048,31288, 29112,31800, 29176,32312,
+ 29368,29816, 29432,30328, 29496,30840, 29560,31352, 29624,31864,
+ 29688,32376, 29944,30392, 30008,30904, 30072,31416, 30136,31928,
+ 30200,32440, 30520,30968, 30584,31480, 30648,31992, 30712,32504,
+ 31096,31544, 31160,32056, 31224,32568, 31672,32120, 31736,32632,
+ 32248,32696
+};
+
+
+/**
+* \par
+* Example code for Floating-point RFFT Twiddle factors Generation:
+* \par
+* <pre>TW = exp(2*pi*i*[0:L/2-1]/L - pi/2*i).' </pre>
+* \par
+* Real and Imag values are in interleaved fashion
+*/
+const float32_t twiddleCoef_rfft_32[32] = {
+0.0f , 1.0f ,
+0.195090322f , 0.98078528f ,
+0.382683432f , 0.923879533f ,
+0.555570233f , 0.831469612f ,
+0.707106781f , 0.707106781f ,
+0.831469612f , 0.555570233f ,
+0.923879533f , 0.382683432f ,
+0.98078528f , 0.195090322f ,
+1.0f , 0.0f ,
+0.98078528f , -0.195090322f ,
+0.923879533f , -0.382683432f ,
+0.831469612f , -0.555570233f ,
+0.707106781f , -0.707106781f ,
+0.555570233f , -0.831469612f ,
+0.382683432f , -0.923879533f ,
+0.195090322f , -0.98078528f
+};
+
+const float32_t twiddleCoef_rfft_64[64] = {
+0.0f, 1.0f,
+0.098017140329561f, 0.995184726672197f,
+0.195090322016128f, 0.98078528040323f,
+0.290284677254462f, 0.956940335732209f,
+0.38268343236509f, 0.923879532511287f,
+0.471396736825998f, 0.881921264348355f,
+0.555570233019602f, 0.831469612302545f,
+0.634393284163645f, 0.773010453362737f,
+0.707106781186547f, 0.707106781186548f,
+0.773010453362737f, 0.634393284163645f,
+0.831469612302545f, 0.555570233019602f,
+0.881921264348355f, 0.471396736825998f,
+0.923879532511287f, 0.38268343236509f,
+0.956940335732209f, 0.290284677254462f,
+0.98078528040323f, 0.195090322016128f,
+0.995184726672197f, 0.098017140329561f,
+1.0f, 0.0f,
+0.995184726672197f, -0.098017140329561f,
+0.98078528040323f, -0.195090322016128f,
+0.956940335732209f, -0.290284677254462f,
+0.923879532511287f, -0.38268343236509f,
+0.881921264348355f, -0.471396736825998f,
+0.831469612302545f, -0.555570233019602f,
+0.773010453362737f, -0.634393284163645f,
+0.707106781186548f, -0.707106781186547f,
+0.634393284163645f, -0.773010453362737f,
+0.555570233019602f, -0.831469612302545f,
+0.471396736825998f, -0.881921264348355f,
+0.38268343236509f, -0.923879532511287f,
+0.290284677254462f, -0.956940335732209f,
+0.195090322016129f, -0.98078528040323f,
+0.098017140329561f, -0.995184726672197f
+};
+
+const float32_t twiddleCoef_rfft_128[128] = {
+ 0.000000000f, 1.000000000f,
+ 0.049067674f, 0.998795456f,
+ 0.098017140f, 0.995184727f,
+ 0.146730474f, 0.989176510f,
+ 0.195090322f, 0.980785280f,
+ 0.242980180f, 0.970031253f,
+ 0.290284677f, 0.956940336f,
+ 0.336889853f, 0.941544065f,
+ 0.382683432f, 0.923879533f,
+ 0.427555093f, 0.903989293f,
+ 0.471396737f, 0.881921264f,
+ 0.514102744f, 0.857728610f,
+ 0.555570233f, 0.831469612f,
+ 0.595699304f, 0.803207531f,
+ 0.634393284f, 0.773010453f,
+ 0.671558955f, 0.740951125f,
+ 0.707106781f, 0.707106781f,
+ 0.740951125f, 0.671558955f,
+ 0.773010453f, 0.634393284f,
+ 0.803207531f, 0.595699304f,
+ 0.831469612f, 0.555570233f,
+ 0.857728610f, 0.514102744f,
+ 0.881921264f, 0.471396737f,
+ 0.903989293f, 0.427555093f,
+ 0.923879533f, 0.382683432f,
+ 0.941544065f, 0.336889853f,
+ 0.956940336f, 0.290284677f,
+ 0.970031253f, 0.242980180f,
+ 0.980785280f, 0.195090322f,
+ 0.989176510f, 0.146730474f,
+ 0.995184727f, 0.098017140f,
+ 0.998795456f, 0.049067674f,
+ 1.000000000f, 0.000000000f,
+ 0.998795456f, -0.049067674f,
+ 0.995184727f, -0.098017140f,
+ 0.989176510f, -0.146730474f,
+ 0.980785280f, -0.195090322f,
+ 0.970031253f, -0.242980180f,
+ 0.956940336f, -0.290284677f,
+ 0.941544065f, -0.336889853f,
+ 0.923879533f, -0.382683432f,
+ 0.903989293f, -0.427555093f,
+ 0.881921264f, -0.471396737f,
+ 0.857728610f, -0.514102744f,
+ 0.831469612f, -0.555570233f,
+ 0.803207531f, -0.595699304f,
+ 0.773010453f, -0.634393284f,
+ 0.740951125f, -0.671558955f,
+ 0.707106781f, -0.707106781f,
+ 0.671558955f, -0.740951125f,
+ 0.634393284f, -0.773010453f,
+ 0.595699304f, -0.803207531f,
+ 0.555570233f, -0.831469612f,
+ 0.514102744f, -0.857728610f,
+ 0.471396737f, -0.881921264f,
+ 0.427555093f, -0.903989293f,
+ 0.382683432f, -0.923879533f,
+ 0.336889853f, -0.941544065f,
+ 0.290284677f, -0.956940336f,
+ 0.242980180f, -0.970031253f,
+ 0.195090322f, -0.980785280f,
+ 0.146730474f, -0.989176510f,
+ 0.098017140f, -0.995184727f,
+ 0.049067674f, -0.998795456f
+};
+
+const float32_t twiddleCoef_rfft_256[256] = {
+ 0.000000000f, 1.000000000f,
+ 0.024541229f, 0.999698819f,
+ 0.049067674f, 0.998795456f,
+ 0.073564564f, 0.997290457f,
+ 0.098017140f, 0.995184727f,
+ 0.122410675f, 0.992479535f,
+ 0.146730474f, 0.989176510f,
+ 0.170961889f, 0.985277642f,
+ 0.195090322f, 0.980785280f,
+ 0.219101240f, 0.975702130f,
+ 0.242980180f, 0.970031253f,
+ 0.266712757f, 0.963776066f,
+ 0.290284677f, 0.956940336f,
+ 0.313681740f, 0.949528181f,
+ 0.336889853f, 0.941544065f,
+ 0.359895037f, 0.932992799f,
+ 0.382683432f, 0.923879533f,
+ 0.405241314f, 0.914209756f,
+ 0.427555093f, 0.903989293f,
+ 0.449611330f, 0.893224301f,
+ 0.471396737f, 0.881921264f,
+ 0.492898192f, 0.870086991f,
+ 0.514102744f, 0.857728610f,
+ 0.534997620f, 0.844853565f,
+ 0.555570233f, 0.831469612f,
+ 0.575808191f, 0.817584813f,
+ 0.595699304f, 0.803207531f,
+ 0.615231591f, 0.788346428f,
+ 0.634393284f, 0.773010453f,
+ 0.653172843f, 0.757208847f,
+ 0.671558955f, 0.740951125f,
+ 0.689540545f, 0.724247083f,
+ 0.707106781f, 0.707106781f,
+ 0.724247083f, 0.689540545f,
+ 0.740951125f, 0.671558955f,
+ 0.757208847f, 0.653172843f,
+ 0.773010453f, 0.634393284f,
+ 0.788346428f, 0.615231591f,
+ 0.803207531f, 0.595699304f,
+ 0.817584813f, 0.575808191f,
+ 0.831469612f, 0.555570233f,
+ 0.844853565f, 0.534997620f,
+ 0.857728610f, 0.514102744f,
+ 0.870086991f, 0.492898192f,
+ 0.881921264f, 0.471396737f,
+ 0.893224301f, 0.449611330f,
+ 0.903989293f, 0.427555093f,
+ 0.914209756f, 0.405241314f,
+ 0.923879533f, 0.382683432f,
+ 0.932992799f, 0.359895037f,
+ 0.941544065f, 0.336889853f,
+ 0.949528181f, 0.313681740f,
+ 0.956940336f, 0.290284677f,
+ 0.963776066f, 0.266712757f,
+ 0.970031253f, 0.242980180f,
+ 0.975702130f, 0.219101240f,
+ 0.980785280f, 0.195090322f,
+ 0.985277642f, 0.170961889f,
+ 0.989176510f, 0.146730474f,
+ 0.992479535f, 0.122410675f,
+ 0.995184727f, 0.098017140f,
+ 0.997290457f, 0.073564564f,
+ 0.998795456f, 0.049067674f,
+ 0.999698819f, 0.024541229f,
+ 1.000000000f, 0.000000000f,
+ 0.999698819f, -0.024541229f,
+ 0.998795456f, -0.049067674f,
+ 0.997290457f, -0.073564564f,
+ 0.995184727f, -0.098017140f,
+ 0.992479535f, -0.122410675f,
+ 0.989176510f, -0.146730474f,
+ 0.985277642f, -0.170961889f,
+ 0.980785280f, -0.195090322f,
+ 0.975702130f, -0.219101240f,
+ 0.970031253f, -0.242980180f,
+ 0.963776066f, -0.266712757f,
+ 0.956940336f, -0.290284677f,
+ 0.949528181f, -0.313681740f,
+ 0.941544065f, -0.336889853f,
+ 0.932992799f, -0.359895037f,
+ 0.923879533f, -0.382683432f,
+ 0.914209756f, -0.405241314f,
+ 0.903989293f, -0.427555093f,
+ 0.893224301f, -0.449611330f,
+ 0.881921264f, -0.471396737f,
+ 0.870086991f, -0.492898192f,
+ 0.857728610f, -0.514102744f,
+ 0.844853565f, -0.534997620f,
+ 0.831469612f, -0.555570233f,
+ 0.817584813f, -0.575808191f,
+ 0.803207531f, -0.595699304f,
+ 0.788346428f, -0.615231591f,
+ 0.773010453f, -0.634393284f,
+ 0.757208847f, -0.653172843f,
+ 0.740951125f, -0.671558955f,
+ 0.724247083f, -0.689540545f,
+ 0.707106781f, -0.707106781f,
+ 0.689540545f, -0.724247083f,
+ 0.671558955f, -0.740951125f,
+ 0.653172843f, -0.757208847f,
+ 0.634393284f, -0.773010453f,
+ 0.615231591f, -0.788346428f,
+ 0.595699304f, -0.803207531f,
+ 0.575808191f, -0.817584813f,
+ 0.555570233f, -0.831469612f,
+ 0.534997620f, -0.844853565f,
+ 0.514102744f, -0.857728610f,
+ 0.492898192f, -0.870086991f,
+ 0.471396737f, -0.881921264f,
+ 0.449611330f, -0.893224301f,
+ 0.427555093f, -0.903989293f,
+ 0.405241314f, -0.914209756f,
+ 0.382683432f, -0.923879533f,
+ 0.359895037f, -0.932992799f,
+ 0.336889853f, -0.941544065f,
+ 0.313681740f, -0.949528181f,
+ 0.290284677f, -0.956940336f,
+ 0.266712757f, -0.963776066f,
+ 0.242980180f, -0.970031253f,
+ 0.219101240f, -0.975702130f,
+ 0.195090322f, -0.980785280f,
+ 0.170961889f, -0.985277642f,
+ 0.146730474f, -0.989176510f,
+ 0.122410675f, -0.992479535f,
+ 0.098017140f, -0.995184727f,
+ 0.073564564f, -0.997290457f,
+ 0.049067674f, -0.998795456f,
+ 0.024541229f, -0.999698819f
+};
+
+const float32_t twiddleCoef_rfft_512[512] = {
+ 0.000000000f, 1.000000000f,
+ 0.012271538f, 0.999924702f,
+ 0.024541229f, 0.999698819f,
+ 0.036807223f, 0.999322385f,
+ 0.049067674f, 0.998795456f,
+ 0.061320736f, 0.998118113f,
+ 0.073564564f, 0.997290457f,
+ 0.085797312f, 0.996312612f,
+ 0.098017140f, 0.995184727f,
+ 0.110222207f, 0.993906970f,
+ 0.122410675f, 0.992479535f,
+ 0.134580709f, 0.990902635f,
+ 0.146730474f, 0.989176510f,
+ 0.158858143f, 0.987301418f,
+ 0.170961889f, 0.985277642f,
+ 0.183039888f, 0.983105487f,
+ 0.195090322f, 0.980785280f,
+ 0.207111376f, 0.978317371f,
+ 0.219101240f, 0.975702130f,
+ 0.231058108f, 0.972939952f,
+ 0.242980180f, 0.970031253f,
+ 0.254865660f, 0.966976471f,
+ 0.266712757f, 0.963776066f,
+ 0.278519689f, 0.960430519f,
+ 0.290284677f, 0.956940336f,
+ 0.302005949f, 0.953306040f,
+ 0.313681740f, 0.949528181f,
+ 0.325310292f, 0.945607325f,
+ 0.336889853f, 0.941544065f,
+ 0.348418680f, 0.937339012f,
+ 0.359895037f, 0.932992799f,
+ 0.371317194f, 0.928506080f,
+ 0.382683432f, 0.923879533f,
+ 0.393992040f, 0.919113852f,
+ 0.405241314f, 0.914209756f,
+ 0.416429560f, 0.909167983f,
+ 0.427555093f, 0.903989293f,
+ 0.438616239f, 0.898674466f,
+ 0.449611330f, 0.893224301f,
+ 0.460538711f, 0.887639620f,
+ 0.471396737f, 0.881921264f,
+ 0.482183772f, 0.876070094f,
+ 0.492898192f, 0.870086991f,
+ 0.503538384f, 0.863972856f,
+ 0.514102744f, 0.857728610f,
+ 0.524589683f, 0.851355193f,
+ 0.534997620f, 0.844853565f,
+ 0.545324988f, 0.838224706f,
+ 0.555570233f, 0.831469612f,
+ 0.565731811f, 0.824589303f,
+ 0.575808191f, 0.817584813f,
+ 0.585797857f, 0.810457198f,
+ 0.595699304f, 0.803207531f,
+ 0.605511041f, 0.795836905f,
+ 0.615231591f, 0.788346428f,
+ 0.624859488f, 0.780737229f,
+ 0.634393284f, 0.773010453f,
+ 0.643831543f, 0.765167266f,
+ 0.653172843f, 0.757208847f,
+ 0.662415778f, 0.749136395f,
+ 0.671558955f, 0.740951125f,
+ 0.680600998f, 0.732654272f,
+ 0.689540545f, 0.724247083f,
+ 0.698376249f, 0.715730825f,
+ 0.707106781f, 0.707106781f,
+ 0.715730825f, 0.698376249f,
+ 0.724247083f, 0.689540545f,
+ 0.732654272f, 0.680600998f,
+ 0.740951125f, 0.671558955f,
+ 0.749136395f, 0.662415778f,
+ 0.757208847f, 0.653172843f,
+ 0.765167266f, 0.643831543f,
+ 0.773010453f, 0.634393284f,
+ 0.780737229f, 0.624859488f,
+ 0.788346428f, 0.615231591f,
+ 0.795836905f, 0.605511041f,
+ 0.803207531f, 0.595699304f,
+ 0.810457198f, 0.585797857f,
+ 0.817584813f, 0.575808191f,
+ 0.824589303f, 0.565731811f,
+ 0.831469612f, 0.555570233f,
+ 0.838224706f, 0.545324988f,
+ 0.844853565f, 0.534997620f,
+ 0.851355193f, 0.524589683f,
+ 0.857728610f, 0.514102744f,
+ 0.863972856f, 0.503538384f,
+ 0.870086991f, 0.492898192f,
+ 0.876070094f, 0.482183772f,
+ 0.881921264f, 0.471396737f,
+ 0.887639620f, 0.460538711f,
+ 0.893224301f, 0.449611330f,
+ 0.898674466f, 0.438616239f,
+ 0.903989293f, 0.427555093f,
+ 0.909167983f, 0.416429560f,
+ 0.914209756f, 0.405241314f,
+ 0.919113852f, 0.393992040f,
+ 0.923879533f, 0.382683432f,
+ 0.928506080f, 0.371317194f,
+ 0.932992799f, 0.359895037f,
+ 0.937339012f, 0.348418680f,
+ 0.941544065f, 0.336889853f,
+ 0.945607325f, 0.325310292f,
+ 0.949528181f, 0.313681740f,
+ 0.953306040f, 0.302005949f,
+ 0.956940336f, 0.290284677f,
+ 0.960430519f, 0.278519689f,
+ 0.963776066f, 0.266712757f,
+ 0.966976471f, 0.254865660f,
+ 0.970031253f, 0.242980180f,
+ 0.972939952f, 0.231058108f,
+ 0.975702130f, 0.219101240f,
+ 0.978317371f, 0.207111376f,
+ 0.980785280f, 0.195090322f,
+ 0.983105487f, 0.183039888f,
+ 0.985277642f, 0.170961889f,
+ 0.987301418f, 0.158858143f,
+ 0.989176510f, 0.146730474f,
+ 0.990902635f, 0.134580709f,
+ 0.992479535f, 0.122410675f,
+ 0.993906970f, 0.110222207f,
+ 0.995184727f, 0.098017140f,
+ 0.996312612f, 0.085797312f,
+ 0.997290457f, 0.073564564f,
+ 0.998118113f, 0.061320736f,
+ 0.998795456f, 0.049067674f,
+ 0.999322385f, 0.036807223f,
+ 0.999698819f, 0.024541229f,
+ 0.999924702f, 0.012271538f,
+ 1.000000000f, 0.000000000f,
+ 0.999924702f, -0.012271538f,
+ 0.999698819f, -0.024541229f,
+ 0.999322385f, -0.036807223f,
+ 0.998795456f, -0.049067674f,
+ 0.998118113f, -0.061320736f,
+ 0.997290457f, -0.073564564f,
+ 0.996312612f, -0.085797312f,
+ 0.995184727f, -0.098017140f,
+ 0.993906970f, -0.110222207f,
+ 0.992479535f, -0.122410675f,
+ 0.990902635f, -0.134580709f,
+ 0.989176510f, -0.146730474f,
+ 0.987301418f, -0.158858143f,
+ 0.985277642f, -0.170961889f,
+ 0.983105487f, -0.183039888f,
+ 0.980785280f, -0.195090322f,
+ 0.978317371f, -0.207111376f,
+ 0.975702130f, -0.219101240f,
+ 0.972939952f, -0.231058108f,
+ 0.970031253f, -0.242980180f,
+ 0.966976471f, -0.254865660f,
+ 0.963776066f, -0.266712757f,
+ 0.960430519f, -0.278519689f,
+ 0.956940336f, -0.290284677f,
+ 0.953306040f, -0.302005949f,
+ 0.949528181f, -0.313681740f,
+ 0.945607325f, -0.325310292f,
+ 0.941544065f, -0.336889853f,
+ 0.937339012f, -0.348418680f,
+ 0.932992799f, -0.359895037f,
+ 0.928506080f, -0.371317194f,
+ 0.923879533f, -0.382683432f,
+ 0.919113852f, -0.393992040f,
+ 0.914209756f, -0.405241314f,
+ 0.909167983f, -0.416429560f,
+ 0.903989293f, -0.427555093f,
+ 0.898674466f, -0.438616239f,
+ 0.893224301f, -0.449611330f,
+ 0.887639620f, -0.460538711f,
+ 0.881921264f, -0.471396737f,
+ 0.876070094f, -0.482183772f,
+ 0.870086991f, -0.492898192f,
+ 0.863972856f, -0.503538384f,
+ 0.857728610f, -0.514102744f,
+ 0.851355193f, -0.524589683f,
+ 0.844853565f, -0.534997620f,
+ 0.838224706f, -0.545324988f,
+ 0.831469612f, -0.555570233f,
+ 0.824589303f, -0.565731811f,
+ 0.817584813f, -0.575808191f,
+ 0.810457198f, -0.585797857f,
+ 0.803207531f, -0.595699304f,
+ 0.795836905f, -0.605511041f,
+ 0.788346428f, -0.615231591f,
+ 0.780737229f, -0.624859488f,
+ 0.773010453f, -0.634393284f,
+ 0.765167266f, -0.643831543f,
+ 0.757208847f, -0.653172843f,
+ 0.749136395f, -0.662415778f,
+ 0.740951125f, -0.671558955f,
+ 0.732654272f, -0.680600998f,
+ 0.724247083f, -0.689540545f,
+ 0.715730825f, -0.698376249f,
+ 0.707106781f, -0.707106781f,
+ 0.698376249f, -0.715730825f,
+ 0.689540545f, -0.724247083f,
+ 0.680600998f, -0.732654272f,
+ 0.671558955f, -0.740951125f,
+ 0.662415778f, -0.749136395f,
+ 0.653172843f, -0.757208847f,
+ 0.643831543f, -0.765167266f,
+ 0.634393284f, -0.773010453f,
+ 0.624859488f, -0.780737229f,
+ 0.615231591f, -0.788346428f,
+ 0.605511041f, -0.795836905f,
+ 0.595699304f, -0.803207531f,
+ 0.585797857f, -0.810457198f,
+ 0.575808191f, -0.817584813f,
+ 0.565731811f, -0.824589303f,
+ 0.555570233f, -0.831469612f,
+ 0.545324988f, -0.838224706f,
+ 0.534997620f, -0.844853565f,
+ 0.524589683f, -0.851355193f,
+ 0.514102744f, -0.857728610f,
+ 0.503538384f, -0.863972856f,
+ 0.492898192f, -0.870086991f,
+ 0.482183772f, -0.876070094f,
+ 0.471396737f, -0.881921264f,
+ 0.460538711f, -0.887639620f,
+ 0.449611330f, -0.893224301f,
+ 0.438616239f, -0.898674466f,
+ 0.427555093f, -0.903989293f,
+ 0.416429560f, -0.909167983f,
+ 0.405241314f, -0.914209756f,
+ 0.393992040f, -0.919113852f,
+ 0.382683432f, -0.923879533f,
+ 0.371317194f, -0.928506080f,
+ 0.359895037f, -0.932992799f,
+ 0.348418680f, -0.937339012f,
+ 0.336889853f, -0.941544065f,
+ 0.325310292f, -0.945607325f,
+ 0.313681740f, -0.949528181f,
+ 0.302005949f, -0.953306040f,
+ 0.290284677f, -0.956940336f,
+ 0.278519689f, -0.960430519f,
+ 0.266712757f, -0.963776066f,
+ 0.254865660f, -0.966976471f,
+ 0.242980180f, -0.970031253f,
+ 0.231058108f, -0.972939952f,
+ 0.219101240f, -0.975702130f,
+ 0.207111376f, -0.978317371f,
+ 0.195090322f, -0.980785280f,
+ 0.183039888f, -0.983105487f,
+ 0.170961889f, -0.985277642f,
+ 0.158858143f, -0.987301418f,
+ 0.146730474f, -0.989176510f,
+ 0.134580709f, -0.990902635f,
+ 0.122410675f, -0.992479535f,
+ 0.110222207f, -0.993906970f,
+ 0.098017140f, -0.995184727f,
+ 0.085797312f, -0.996312612f,
+ 0.073564564f, -0.997290457f,
+ 0.061320736f, -0.998118113f,
+ 0.049067674f, -0.998795456f,
+ 0.036807223f, -0.999322385f,
+ 0.024541229f, -0.999698819f,
+ 0.012271538f, -0.999924702f
+};
+
+const float32_t twiddleCoef_rfft_1024[1024] = {
+ 0.000000000f, 1.000000000f,
+ 0.006135885f, 0.999981175f,
+ 0.012271538f, 0.999924702f,
+ 0.018406730f, 0.999830582f,
+ 0.024541229f, 0.999698819f,
+ 0.030674803f, 0.999529418f,
+ 0.036807223f, 0.999322385f,
+ 0.042938257f, 0.999077728f,
+ 0.049067674f, 0.998795456f,
+ 0.055195244f, 0.998475581f,
+ 0.061320736f, 0.998118113f,
+ 0.067443920f, 0.997723067f,
+ 0.073564564f, 0.997290457f,
+ 0.079682438f, 0.996820299f,
+ 0.085797312f, 0.996312612f,
+ 0.091908956f, 0.995767414f,
+ 0.098017140f, 0.995184727f,
+ 0.104121634f, 0.994564571f,
+ 0.110222207f, 0.993906970f,
+ 0.116318631f, 0.993211949f,
+ 0.122410675f, 0.992479535f,
+ 0.128498111f, 0.991709754f,
+ 0.134580709f, 0.990902635f,
+ 0.140658239f, 0.990058210f,
+ 0.146730474f, 0.989176510f,
+ 0.152797185f, 0.988257568f,
+ 0.158858143f, 0.987301418f,
+ 0.164913120f, 0.986308097f,
+ 0.170961889f, 0.985277642f,
+ 0.177004220f, 0.984210092f,
+ 0.183039888f, 0.983105487f,
+ 0.189068664f, 0.981963869f,
+ 0.195090322f, 0.980785280f,
+ 0.201104635f, 0.979569766f,
+ 0.207111376f, 0.978317371f,
+ 0.213110320f, 0.977028143f,
+ 0.219101240f, 0.975702130f,
+ 0.225083911f, 0.974339383f,
+ 0.231058108f, 0.972939952f,
+ 0.237023606f, 0.971503891f,
+ 0.242980180f, 0.970031253f,
+ 0.248927606f, 0.968522094f,
+ 0.254865660f, 0.966976471f,
+ 0.260794118f, 0.965394442f,
+ 0.266712757f, 0.963776066f,
+ 0.272621355f, 0.962121404f,
+ 0.278519689f, 0.960430519f,
+ 0.284407537f, 0.958703475f,
+ 0.290284677f, 0.956940336f,
+ 0.296150888f, 0.955141168f,
+ 0.302005949f, 0.953306040f,
+ 0.307849640f, 0.951435021f,
+ 0.313681740f, 0.949528181f,
+ 0.319502031f, 0.947585591f,
+ 0.325310292f, 0.945607325f,
+ 0.331106306f, 0.943593458f,
+ 0.336889853f, 0.941544065f,
+ 0.342660717f, 0.939459224f,
+ 0.348418680f, 0.937339012f,
+ 0.354163525f, 0.935183510f,
+ 0.359895037f, 0.932992799f,
+ 0.365612998f, 0.930766961f,
+ 0.371317194f, 0.928506080f,
+ 0.377007410f, 0.926210242f,
+ 0.382683432f, 0.923879533f,
+ 0.388345047f, 0.921514039f,
+ 0.393992040f, 0.919113852f,
+ 0.399624200f, 0.916679060f,
+ 0.405241314f, 0.914209756f,
+ 0.410843171f, 0.911706032f,
+ 0.416429560f, 0.909167983f,
+ 0.422000271f, 0.906595705f,
+ 0.427555093f, 0.903989293f,
+ 0.433093819f, 0.901348847f,
+ 0.438616239f, 0.898674466f,
+ 0.444122145f, 0.895966250f,
+ 0.449611330f, 0.893224301f,
+ 0.455083587f, 0.890448723f,
+ 0.460538711f, 0.887639620f,
+ 0.465976496f, 0.884797098f,
+ 0.471396737f, 0.881921264f,
+ 0.476799230f, 0.879012226f,
+ 0.482183772f, 0.876070094f,
+ 0.487550160f, 0.873094978f,
+ 0.492898192f, 0.870086991f,
+ 0.498227667f, 0.867046246f,
+ 0.503538384f, 0.863972856f,
+ 0.508830143f, 0.860866939f,
+ 0.514102744f, 0.857728610f,
+ 0.519355990f, 0.854557988f,
+ 0.524589683f, 0.851355193f,
+ 0.529803625f, 0.848120345f,
+ 0.534997620f, 0.844853565f,
+ 0.540171473f, 0.841554977f,
+ 0.545324988f, 0.838224706f,
+ 0.550457973f, 0.834862875f,
+ 0.555570233f, 0.831469612f,
+ 0.560661576f, 0.828045045f,
+ 0.565731811f, 0.824589303f,
+ 0.570780746f, 0.821102515f,
+ 0.575808191f, 0.817584813f,
+ 0.580813958f, 0.814036330f,
+ 0.585797857f, 0.810457198f,
+ 0.590759702f, 0.806847554f,
+ 0.595699304f, 0.803207531f,
+ 0.600616479f, 0.799537269f,
+ 0.605511041f, 0.795836905f,
+ 0.610382806f, 0.792106577f,
+ 0.615231591f, 0.788346428f,
+ 0.620057212f, 0.784556597f,
+ 0.624859488f, 0.780737229f,
+ 0.629638239f, 0.776888466f,
+ 0.634393284f, 0.773010453f,
+ 0.639124445f, 0.769103338f,
+ 0.643831543f, 0.765167266f,
+ 0.648514401f, 0.761202385f,
+ 0.653172843f, 0.757208847f,
+ 0.657806693f, 0.753186799f,
+ 0.662415778f, 0.749136395f,
+ 0.666999922f, 0.745057785f,
+ 0.671558955f, 0.740951125f,
+ 0.676092704f, 0.736816569f,
+ 0.680600998f, 0.732654272f,
+ 0.685083668f, 0.728464390f,
+ 0.689540545f, 0.724247083f,
+ 0.693971461f, 0.720002508f,
+ 0.698376249f, 0.715730825f,
+ 0.702754744f, 0.711432196f,
+ 0.707106781f, 0.707106781f,
+ 0.711432196f, 0.702754744f,
+ 0.715730825f, 0.698376249f,
+ 0.720002508f, 0.693971461f,
+ 0.724247083f, 0.689540545f,
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+ 0.901348847f, 0.433093819f,
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+ 0.960430519f, 0.278519689f,
+ 0.962121404f, 0.272621355f,
+ 0.963776066f, 0.266712757f,
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+ 0.977028143f, 0.213110320f,
+ 0.978317371f, 0.207111376f,
+ 0.979569766f, 0.201104635f,
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+ 0.993211949f, 0.116318631f,
+ 0.993906970f, 0.110222207f,
+ 0.994564571f, 0.104121634f,
+ 0.995184727f, 0.098017140f,
+ 0.995767414f, 0.091908956f,
+ 0.996312612f, 0.085797312f,
+ 0.996820299f, 0.079682438f,
+ 0.997290457f, 0.073564564f,
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+ 0.998475581f, 0.055195244f,
+ 0.998795456f, 0.049067674f,
+ 0.999077728f, 0.042938257f,
+ 0.999322385f, 0.036807223f,
+ 0.999529418f, 0.030674803f,
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+ 0.634393284f, -0.773010453f,
+ 0.629638239f, -0.776888466f,
+ 0.624859488f, -0.780737229f,
+ 0.620057212f, -0.784556597f,
+ 0.615231591f, -0.788346428f,
+ 0.610382806f, -0.792106577f,
+ 0.605511041f, -0.795836905f,
+ 0.600616479f, -0.799537269f,
+ 0.595699304f, -0.803207531f,
+ 0.590759702f, -0.806847554f,
+ 0.585797857f, -0.810457198f,
+ 0.580813958f, -0.814036330f,
+ 0.575808191f, -0.817584813f,
+ 0.570780746f, -0.821102515f,
+ 0.565731811f, -0.824589303f,
+ 0.560661576f, -0.828045045f,
+ 0.555570233f, -0.831469612f,
+ 0.550457973f, -0.834862875f,
+ 0.545324988f, -0.838224706f,
+ 0.540171473f, -0.841554977f,
+ 0.534997620f, -0.844853565f,
+ 0.529803625f, -0.848120345f,
+ 0.524589683f, -0.851355193f,
+ 0.519355990f, -0.854557988f,
+ 0.514102744f, -0.857728610f,
+ 0.508830143f, -0.860866939f,
+ 0.503538384f, -0.863972856f,
+ 0.498227667f, -0.867046246f,
+ 0.492898192f, -0.870086991f,
+ 0.487550160f, -0.873094978f,
+ 0.482183772f, -0.876070094f,
+ 0.476799230f, -0.879012226f,
+ 0.471396737f, -0.881921264f,
+ 0.465976496f, -0.884797098f,
+ 0.460538711f, -0.887639620f,
+ 0.455083587f, -0.890448723f,
+ 0.449611330f, -0.893224301f,
+ 0.444122145f, -0.895966250f,
+ 0.438616239f, -0.898674466f,
+ 0.433093819f, -0.901348847f,
+ 0.427555093f, -0.903989293f,
+ 0.422000271f, -0.906595705f,
+ 0.416429560f, -0.909167983f,
+ 0.410843171f, -0.911706032f,
+ 0.405241314f, -0.914209756f,
+ 0.399624200f, -0.916679060f,
+ 0.393992040f, -0.919113852f,
+ 0.388345047f, -0.921514039f,
+ 0.382683432f, -0.923879533f,
+ 0.377007410f, -0.926210242f,
+ 0.371317194f, -0.928506080f,
+ 0.365612998f, -0.930766961f,
+ 0.359895037f, -0.932992799f,
+ 0.354163525f, -0.935183510f,
+ 0.348418680f, -0.937339012f,
+ 0.342660717f, -0.939459224f,
+ 0.336889853f, -0.941544065f,
+ 0.331106306f, -0.943593458f,
+ 0.325310292f, -0.945607325f,
+ 0.319502031f, -0.947585591f,
+ 0.313681740f, -0.949528181f,
+ 0.307849640f, -0.951435021f,
+ 0.302005949f, -0.953306040f,
+ 0.296150888f, -0.955141168f,
+ 0.290284677f, -0.956940336f,
+ 0.284407537f, -0.958703475f,
+ 0.278519689f, -0.960430519f,
+ 0.272621355f, -0.962121404f,
+ 0.266712757f, -0.963776066f,
+ 0.260794118f, -0.965394442f,
+ 0.254865660f, -0.966976471f,
+ 0.248927606f, -0.968522094f,
+ 0.242980180f, -0.970031253f,
+ 0.237023606f, -0.971503891f,
+ 0.231058108f, -0.972939952f,
+ 0.225083911f, -0.974339383f,
+ 0.219101240f, -0.975702130f,
+ 0.213110320f, -0.977028143f,
+ 0.207111376f, -0.978317371f,
+ 0.201104635f, -0.979569766f,
+ 0.195090322f, -0.980785280f,
+ 0.189068664f, -0.981963869f,
+ 0.183039888f, -0.983105487f,
+ 0.177004220f, -0.984210092f,
+ 0.170961889f, -0.985277642f,
+ 0.164913120f, -0.986308097f,
+ 0.158858143f, -0.987301418f,
+ 0.152797185f, -0.988257568f,
+ 0.146730474f, -0.989176510f,
+ 0.140658239f, -0.990058210f,
+ 0.134580709f, -0.990902635f,
+ 0.128498111f, -0.991709754f,
+ 0.122410675f, -0.992479535f,
+ 0.116318631f, -0.993211949f,
+ 0.110222207f, -0.993906970f,
+ 0.104121634f, -0.994564571f,
+ 0.098017140f, -0.995184727f,
+ 0.091908956f, -0.995767414f,
+ 0.085797312f, -0.996312612f,
+ 0.079682438f, -0.996820299f,
+ 0.073564564f, -0.997290457f,
+ 0.067443920f, -0.997723067f,
+ 0.061320736f, -0.998118113f,
+ 0.055195244f, -0.998475581f,
+ 0.049067674f, -0.998795456f,
+ 0.042938257f, -0.999077728f,
+ 0.036807223f, -0.999322385f,
+ 0.030674803f, -0.999529418f,
+ 0.024541229f, -0.999698819f,
+ 0.018406730f, -0.999830582f,
+ 0.012271538f, -0.999924702f,
+ 0.006135885f, -0.999981175f
+};
+
+const float32_t twiddleCoef_rfft_2048[2048] = {
+ 0.000000000f, 1.000000000f,
+ 0.003067957f, 0.999995294f,
+ 0.006135885f, 0.999981175f,
+ 0.009203755f, 0.999957645f,
+ 0.012271538f, 0.999924702f,
+ 0.015339206f, 0.999882347f,
+ 0.018406730f, 0.999830582f,
+ 0.021474080f, 0.999769405f,
+ 0.024541229f, 0.999698819f,
+ 0.027608146f, 0.999618822f,
+ 0.030674803f, 0.999529418f,
+ 0.033741172f, 0.999430605f,
+ 0.036807223f, 0.999322385f,
+ 0.039872928f, 0.999204759f,
+ 0.042938257f, 0.999077728f,
+ 0.046003182f, 0.998941293f,
+ 0.049067674f, 0.998795456f,
+ 0.052131705f, 0.998640218f,
+ 0.055195244f, 0.998475581f,
+ 0.058258265f, 0.998301545f,
+ 0.061320736f, 0.998118113f,
+ 0.064382631f, 0.997925286f,
+ 0.067443920f, 0.997723067f,
+ 0.070504573f, 0.997511456f,
+ 0.073564564f, 0.997290457f,
+ 0.076623861f, 0.997060070f,
+ 0.079682438f, 0.996820299f,
+ 0.082740265f, 0.996571146f,
+ 0.085797312f, 0.996312612f,
+ 0.088853553f, 0.996044701f,
+ 0.091908956f, 0.995767414f,
+ 0.094963495f, 0.995480755f,
+ 0.098017140f, 0.995184727f,
+ 0.101069863f, 0.994879331f,
+ 0.104121634f, 0.994564571f,
+ 0.107172425f, 0.994240449f,
+ 0.110222207f, 0.993906970f,
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+ 0.408044163f, -0.912962190f,
+ 0.405241314f, -0.914209756f,
+ 0.402434651f, -0.915448716f,
+ 0.399624200f, -0.916679060f,
+ 0.396809987f, -0.917900776f,
+ 0.393992040f, -0.919113852f,
+ 0.391170384f, -0.920318277f,
+ 0.388345047f, -0.921514039f,
+ 0.385516054f, -0.922701128f,
+ 0.382683432f, -0.923879533f,
+ 0.379847209f, -0.925049241f,
+ 0.377007410f, -0.926210242f,
+ 0.374164063f, -0.927362526f,
+ 0.371317194f, -0.928506080f,
+ 0.368466830f, -0.929640896f,
+ 0.365612998f, -0.930766961f,
+ 0.362755724f, -0.931884266f,
+ 0.359895037f, -0.932992799f,
+ 0.357030961f, -0.934092550f,
+ 0.354163525f, -0.935183510f,
+ 0.351292756f, -0.936265667f,
+ 0.348418680f, -0.937339012f,
+ 0.345541325f, -0.938403534f,
+ 0.342660717f, -0.939459224f,
+ 0.339776884f, -0.940506071f,
+ 0.336889853f, -0.941544065f,
+ 0.333999651f, -0.942573198f,
+ 0.331106306f, -0.943593458f,
+ 0.328209844f, -0.944604837f,
+ 0.325310292f, -0.945607325f,
+ 0.322407679f, -0.946600913f,
+ 0.319502031f, -0.947585591f,
+ 0.316593376f, -0.948561350f,
+ 0.313681740f, -0.949528181f,
+ 0.310767153f, -0.950486074f,
+ 0.307849640f, -0.951435021f,
+ 0.304929230f, -0.952375013f,
+ 0.302005949f, -0.953306040f,
+ 0.299079826f, -0.954228095f,
+ 0.296150888f, -0.955141168f,
+ 0.293219163f, -0.956045251f,
+ 0.290284677f, -0.956940336f,
+ 0.287347460f, -0.957826413f,
+ 0.284407537f, -0.958703475f,
+ 0.281464938f, -0.959571513f,
+ 0.278519689f, -0.960430519f,
+ 0.275571819f, -0.961280486f,
+ 0.272621355f, -0.962121404f,
+ 0.269668326f, -0.962953267f,
+ 0.266712757f, -0.963776066f,
+ 0.263754679f, -0.964589793f,
+ 0.260794118f, -0.965394442f,
+ 0.257831102f, -0.966190003f,
+ 0.254865660f, -0.966976471f,
+ 0.251897818f, -0.967753837f,
+ 0.248927606f, -0.968522094f,
+ 0.245955050f, -0.969281235f,
+ 0.242980180f, -0.970031253f,
+ 0.240003022f, -0.970772141f,
+ 0.237023606f, -0.971503891f,
+ 0.234041959f, -0.972226497f,
+ 0.231058108f, -0.972939952f,
+ 0.228072083f, -0.973644250f,
+ 0.225083911f, -0.974339383f,
+ 0.222093621f, -0.975025345f,
+ 0.219101240f, -0.975702130f,
+ 0.216106797f, -0.976369731f,
+ 0.213110320f, -0.977028143f,
+ 0.210111837f, -0.977677358f,
+ 0.207111376f, -0.978317371f,
+ 0.204108966f, -0.978948175f,
+ 0.201104635f, -0.979569766f,
+ 0.198098411f, -0.980182136f,
+ 0.195090322f, -0.980785280f,
+ 0.192080397f, -0.981379193f,
+ 0.189068664f, -0.981963869f,
+ 0.186055152f, -0.982539302f,
+ 0.183039888f, -0.983105487f,
+ 0.180022901f, -0.983662419f,
+ 0.177004220f, -0.984210092f,
+ 0.173983873f, -0.984748502f,
+ 0.170961889f, -0.985277642f,
+ 0.167938295f, -0.985797509f,
+ 0.164913120f, -0.986308097f,
+ 0.161886394f, -0.986809402f,
+ 0.158858143f, -0.987301418f,
+ 0.155828398f, -0.987784142f,
+ 0.152797185f, -0.988257568f,
+ 0.149764535f, -0.988721692f,
+ 0.146730474f, -0.989176510f,
+ 0.143695033f, -0.989622017f,
+ 0.140658239f, -0.990058210f,
+ 0.137620122f, -0.990485084f,
+ 0.134580709f, -0.990902635f,
+ 0.131540029f, -0.991310860f,
+ 0.128498111f, -0.991709754f,
+ 0.125454983f, -0.992099313f,
+ 0.122410675f, -0.992479535f,
+ 0.119365215f, -0.992850414f,
+ 0.116318631f, -0.993211949f,
+ 0.113270952f, -0.993564136f,
+ 0.110222207f, -0.993906970f,
+ 0.107172425f, -0.994240449f,
+ 0.104121634f, -0.994564571f,
+ 0.101069863f, -0.994879331f,
+ 0.098017140f, -0.995184727f,
+ 0.094963495f, -0.995480755f,
+ 0.091908956f, -0.995767414f,
+ 0.088853553f, -0.996044701f,
+ 0.085797312f, -0.996312612f,
+ 0.082740265f, -0.996571146f,
+ 0.079682438f, -0.996820299f,
+ 0.076623861f, -0.997060070f,
+ 0.073564564f, -0.997290457f,
+ 0.070504573f, -0.997511456f,
+ 0.067443920f, -0.997723067f,
+ 0.064382631f, -0.997925286f,
+ 0.061320736f, -0.998118113f,
+ 0.058258265f, -0.998301545f,
+ 0.055195244f, -0.998475581f,
+ 0.052131705f, -0.998640218f,
+ 0.049067674f, -0.998795456f,
+ 0.046003182f, -0.998941293f,
+ 0.042938257f, -0.999077728f,
+ 0.039872928f, -0.999204759f,
+ 0.036807223f, -0.999322385f,
+ 0.033741172f, -0.999430605f,
+ 0.030674803f, -0.999529418f,
+ 0.027608146f, -0.999618822f,
+ 0.024541229f, -0.999698819f,
+ 0.021474080f, -0.999769405f,
+ 0.018406730f, -0.999830582f,
+ 0.015339206f, -0.999882347f,
+ 0.012271538f, -0.999924702f,
+ 0.009203755f, -0.999957645f,
+ 0.006135885f, -0.999981175f,
+ 0.003067957f, -0.999995294f
+};
+
+const float32_t twiddleCoef_rfft_4096[4096] = {
+ 0.000000000f, 1.000000000f,
+ 0.001533980f, 0.999998823f,
+ 0.003067957f, 0.999995294f,
+ 0.004601926f, 0.999989411f,
+ 0.006135885f, 0.999981175f,
+ 0.007669829f, 0.999970586f,
+ 0.009203755f, 0.999957645f,
+ 0.010737659f, 0.999942350f,
+ 0.012271538f, 0.999924702f,
+ 0.013805389f, 0.999904701f,
+ 0.015339206f, 0.999882347f,
+ 0.016872988f, 0.999857641f,
+ 0.018406730f, 0.999830582f,
+ 0.019940429f, 0.999801170f,
+ 0.021474080f, 0.999769405f,
+ 0.023007681f, 0.999735288f,
+ 0.024541229f, 0.999698819f,
+ 0.026074718f, 0.999659997f,
+ 0.027608146f, 0.999618822f,
+ 0.029141509f, 0.999575296f,
+ 0.030674803f, 0.999529418f,
+ 0.032208025f, 0.999481187f,
+ 0.033741172f, 0.999430605f,
+ 0.035274239f, 0.999377670f,
+ 0.036807223f, 0.999322385f,
+ 0.038340120f, 0.999264747f,
+ 0.039872928f, 0.999204759f,
+ 0.041405641f, 0.999142419f,
+ 0.042938257f, 0.999077728f,
+ 0.044470772f, 0.999010686f,
+ 0.046003182f, 0.998941293f,
+ 0.047535484f, 0.998869550f,
+ 0.049067674f, 0.998795456f,
+ 0.050599749f, 0.998719012f,
+ 0.052131705f, 0.998640218f,
+ 0.053663538f, 0.998559074f,
+ 0.055195244f, 0.998475581f,
+ 0.056726821f, 0.998389737f,
+ 0.058258265f, 0.998301545f,
+ 0.059789571f, 0.998211003f,
+ 0.061320736f, 0.998118113f,
+ 0.062851758f, 0.998022874f,
+ 0.064382631f, 0.997925286f,
+ 0.065913353f, 0.997825350f,
+ 0.067443920f, 0.997723067f,
+ 0.068974328f, 0.997618435f,
+ 0.070504573f, 0.997511456f,
+ 0.072034653f, 0.997402130f,
+ 0.073564564f, 0.997290457f,
+ 0.075094301f, 0.997176437f,
+ 0.076623861f, 0.997060070f,
+ 0.078153242f, 0.996941358f,
+ 0.079682438f, 0.996820299f,
+ 0.081211447f, 0.996696895f,
+ 0.082740265f, 0.996571146f,
+ 0.084268888f, 0.996443051f,
+ 0.085797312f, 0.996312612f,
+ 0.087325535f, 0.996179829f,
+ 0.088853553f, 0.996044701f,
+ 0.090381361f, 0.995907229f,
+ 0.091908956f, 0.995767414f,
+ 0.093436336f, 0.995625256f,
+ 0.094963495f, 0.995480755f,
+ 0.096490431f, 0.995333912f,
+ 0.098017140f, 0.995184727f,
+ 0.099543619f, 0.995033199f,
+ 0.101069863f, 0.994879331f,
+ 0.102595869f, 0.994723121f,
+ 0.104121634f, 0.994564571f,
+ 0.105647154f, 0.994403680f,
+ 0.107172425f, 0.994240449f,
+ 0.108697444f, 0.994074879f,
+ 0.110222207f, 0.993906970f,
+ 0.111746711f, 0.993736722f,
+ 0.113270952f, 0.993564136f,
+ 0.114794927f, 0.993389211f,
+ 0.116318631f, 0.993211949f,
+ 0.117842062f, 0.993032350f,
+ 0.119365215f, 0.992850414f,
+ 0.120888087f, 0.992666142f,
+ 0.122410675f, 0.992479535f,
+ 0.123932975f, 0.992290591f,
+ 0.125454983f, 0.992099313f,
+ 0.126976696f, 0.991905700f,
+ 0.128498111f, 0.991709754f,
+ 0.130019223f, 0.991511473f,
+ 0.131540029f, 0.991310860f,
+ 0.133060525f, 0.991107914f,
+ 0.134580709f, 0.990902635f,
+ 0.136100575f, 0.990695025f,
+ 0.137620122f, 0.990485084f,
+ 0.139139344f, 0.990272812f,
+ 0.140658239f, 0.990058210f,
+ 0.142176804f, 0.989841278f,
+ 0.143695033f, 0.989622017f,
+ 0.145212925f, 0.989400428f,
+ 0.146730474f, 0.989176510f,
+ 0.148247679f, 0.988950265f,
+ 0.149764535f, 0.988721692f,
+ 0.151281038f, 0.988490793f,
+ 0.152797185f, 0.988257568f,
+ 0.154312973f, 0.988022017f,
+ 0.155828398f, 0.987784142f,
+ 0.157343456f, 0.987543942f,
+ 0.158858143f, 0.987301418f,
+ 0.160372457f, 0.987056571f,
+ 0.161886394f, 0.986809402f,
+ 0.163399949f, 0.986559910f,
+ 0.164913120f, 0.986308097f,
+ 0.166425904f, 0.986053963f,
+ 0.167938295f, 0.985797509f,
+ 0.169450291f, 0.985538735f,
+ 0.170961889f, 0.985277642f,
+ 0.172473084f, 0.985014231f,
+ 0.173983873f, 0.984748502f,
+ 0.175494253f, 0.984480455f,
+ 0.177004220f, 0.984210092f,
+ 0.178513771f, 0.983937413f,
+ 0.180022901f, 0.983662419f,
+ 0.181531608f, 0.983385110f,
+ 0.183039888f, 0.983105487f,
+ 0.184547737f, 0.982823551f,
+ 0.186055152f, 0.982539302f,
+ 0.187562129f, 0.982252741f,
+ 0.189068664f, 0.981963869f,
+ 0.190574755f, 0.981672686f,
+ 0.192080397f, 0.981379193f,
+ 0.193585587f, 0.981083391f,
+ 0.195090322f, 0.980785280f,
+ 0.196594598f, 0.980484862f,
+ 0.198098411f, 0.980182136f,
+ 0.199601758f, 0.979877104f,
+ 0.201104635f, 0.979569766f,
+ 0.202607039f, 0.979260123f,
+ 0.204108966f, 0.978948175f,
+ 0.205610413f, 0.978633924f,
+ 0.207111376f, 0.978317371f,
+ 0.208611852f, 0.977998515f,
+ 0.210111837f, 0.977677358f,
+ 0.211611327f, 0.977353900f,
+ 0.213110320f, 0.977028143f,
+ 0.214608811f, 0.976700086f,
+ 0.216106797f, 0.976369731f,
+ 0.217604275f, 0.976037079f,
+ 0.219101240f, 0.975702130f,
+ 0.220597690f, 0.975364885f,
+ 0.222093621f, 0.975025345f,
+ 0.223589029f, 0.974683511f,
+ 0.225083911f, 0.974339383f,
+ 0.226578264f, 0.973992962f,
+ 0.228072083f, 0.973644250f,
+ 0.229565366f, 0.973293246f,
+ 0.231058108f, 0.972939952f,
+ 0.232550307f, 0.972584369f,
+ 0.234041959f, 0.972226497f,
+ 0.235533059f, 0.971866337f,
+ 0.237023606f, 0.971503891f,
+ 0.238513595f, 0.971139158f,
+ 0.240003022f, 0.970772141f,
+ 0.241491885f, 0.970402839f,
+ 0.242980180f, 0.970031253f,
+ 0.244467903f, 0.969657385f,
+ 0.245955050f, 0.969281235f,
+ 0.247441619f, 0.968902805f,
+ 0.248927606f, 0.968522094f,
+ 0.250413007f, 0.968139105f,
+ 0.251897818f, 0.967753837f,
+ 0.253382037f, 0.967366292f,
+ 0.254865660f, 0.966976471f,
+ 0.256348682f, 0.966584374f,
+ 0.257831102f, 0.966190003f,
+ 0.259312915f, 0.965793359f,
+ 0.260794118f, 0.965394442f,
+ 0.262274707f, 0.964993253f,
+ 0.263754679f, 0.964589793f,
+ 0.265234030f, 0.964184064f,
+ 0.266712757f, 0.963776066f,
+ 0.268190857f, 0.963365800f,
+ 0.269668326f, 0.962953267f,
+ 0.271145160f, 0.962538468f,
+ 0.272621355f, 0.962121404f,
+ 0.274096910f, 0.961702077f,
+ 0.275571819f, 0.961280486f,
+ 0.277046080f, 0.960856633f,
+ 0.278519689f, 0.960430519f,
+ 0.279992643f, 0.960002146f,
+ 0.281464938f, 0.959571513f,
+ 0.282936570f, 0.959138622f,
+ 0.284407537f, 0.958703475f,
+ 0.285877835f, 0.958266071f,
+ 0.287347460f, 0.957826413f,
+ 0.288816408f, 0.957384501f,
+ 0.290284677f, 0.956940336f,
+ 0.291752263f, 0.956493919f,
+ 0.293219163f, 0.956045251f,
+ 0.294685372f, 0.955594334f,
+ 0.296150888f, 0.955141168f,
+ 0.297615707f, 0.954685755f,
+ 0.299079826f, 0.954228095f,
+ 0.300543241f, 0.953768190f,
+ 0.302005949f, 0.953306040f,
+ 0.303467947f, 0.952841648f,
+ 0.304929230f, 0.952375013f,
+ 0.306389795f, 0.951906137f,
+ 0.307849640f, 0.951435021f,
+ 0.309308760f, 0.950961666f,
+ 0.310767153f, 0.950486074f,
+ 0.312224814f, 0.950008245f,
+ 0.313681740f, 0.949528181f,
+ 0.315137929f, 0.949045882f,
+ 0.316593376f, 0.948561350f,
+ 0.318048077f, 0.948074586f,
+ 0.319502031f, 0.947585591f,
+ 0.320955232f, 0.947094366f,
+ 0.322407679f, 0.946600913f,
+ 0.323859367f, 0.946105232f,
+ 0.325310292f, 0.945607325f,
+ 0.326760452f, 0.945107193f,
+ 0.328209844f, 0.944604837f,
+ 0.329658463f, 0.944100258f,
+ 0.331106306f, 0.943593458f,
+ 0.332553370f, 0.943084437f,
+ 0.333999651f, 0.942573198f,
+ 0.335445147f, 0.942059740f,
+ 0.336889853f, 0.941544065f,
+ 0.338333767f, 0.941026175f,
+ 0.339776884f, 0.940506071f,
+ 0.341219202f, 0.939983753f,
+ 0.342660717f, 0.939459224f,
+ 0.344101426f, 0.938932484f,
+ 0.345541325f, 0.938403534f,
+ 0.346980411f, 0.937872376f,
+ 0.348418680f, 0.937339012f,
+ 0.349856130f, 0.936803442f,
+ 0.351292756f, 0.936265667f,
+ 0.352728556f, 0.935725689f,
+ 0.354163525f, 0.935183510f,
+ 0.355597662f, 0.934639130f,
+ 0.357030961f, 0.934092550f,
+ 0.358463421f, 0.933543773f,
+ 0.359895037f, 0.932992799f,
+ 0.361325806f, 0.932439629f,
+ 0.362755724f, 0.931884266f,
+ 0.364184790f, 0.931326709f,
+ 0.365612998f, 0.930766961f,
+ 0.367040346f, 0.930205023f,
+ 0.368466830f, 0.929640896f,
+ 0.369892447f, 0.929074581f,
+ 0.371317194f, 0.928506080f,
+ 0.372741067f, 0.927935395f,
+ 0.374164063f, 0.927362526f,
+ 0.375586178f, 0.926787474f,
+ 0.377007410f, 0.926210242f,
+ 0.378427755f, 0.925630831f,
+ 0.379847209f, 0.925049241f,
+ 0.381265769f, 0.924465474f,
+ 0.382683432f, 0.923879533f,
+ 0.384100195f, 0.923291417f,
+ 0.385516054f, 0.922701128f,
+ 0.386931006f, 0.922108669f,
+ 0.388345047f, 0.921514039f,
+ 0.389758174f, 0.920917242f,
+ 0.391170384f, 0.920318277f,
+ 0.392581674f, 0.919717146f,
+ 0.393992040f, 0.919113852f,
+ 0.395401479f, 0.918508394f,
+ 0.396809987f, 0.917900776f,
+ 0.398217562f, 0.917290997f,
+ 0.399624200f, 0.916679060f,
+ 0.401029897f, 0.916064966f,
+ 0.402434651f, 0.915448716f,
+ 0.403838458f, 0.914830312f,
+ 0.405241314f, 0.914209756f,
+ 0.406643217f, 0.913587048f,
+ 0.408044163f, 0.912962190f,
+ 0.409444149f, 0.912335185f,
+ 0.410843171f, 0.911706032f,
+ 0.412241227f, 0.911074734f,
+ 0.413638312f, 0.910441292f,
+ 0.415034424f, 0.909805708f,
+ 0.416429560f, 0.909167983f,
+ 0.417823716f, 0.908528119f,
+ 0.419216888f, 0.907886116f,
+ 0.420609074f, 0.907241978f,
+ 0.422000271f, 0.906595705f,
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+ 0.117842062f, -0.993032350f,
+ 0.116318631f, -0.993211949f,
+ 0.114794927f, -0.993389211f,
+ 0.113270952f, -0.993564136f,
+ 0.111746711f, -0.993736722f,
+ 0.110222207f, -0.993906970f,
+ 0.108697444f, -0.994074879f,
+ 0.107172425f, -0.994240449f,
+ 0.105647154f, -0.994403680f,
+ 0.104121634f, -0.994564571f,
+ 0.102595869f, -0.994723121f,
+ 0.101069863f, -0.994879331f,
+ 0.099543619f, -0.995033199f,
+ 0.098017140f, -0.995184727f,
+ 0.096490431f, -0.995333912f,
+ 0.094963495f, -0.995480755f,
+ 0.093436336f, -0.995625256f,
+ 0.091908956f, -0.995767414f,
+ 0.090381361f, -0.995907229f,
+ 0.088853553f, -0.996044701f,
+ 0.087325535f, -0.996179829f,
+ 0.085797312f, -0.996312612f,
+ 0.084268888f, -0.996443051f,
+ 0.082740265f, -0.996571146f,
+ 0.081211447f, -0.996696895f,
+ 0.079682438f, -0.996820299f,
+ 0.078153242f, -0.996941358f,
+ 0.076623861f, -0.997060070f,
+ 0.075094301f, -0.997176437f,
+ 0.073564564f, -0.997290457f,
+ 0.072034653f, -0.997402130f,
+ 0.070504573f, -0.997511456f,
+ 0.068974328f, -0.997618435f,
+ 0.067443920f, -0.997723067f,
+ 0.065913353f, -0.997825350f,
+ 0.064382631f, -0.997925286f,
+ 0.062851758f, -0.998022874f,
+ 0.061320736f, -0.998118113f,
+ 0.059789571f, -0.998211003f,
+ 0.058258265f, -0.998301545f,
+ 0.056726821f, -0.998389737f,
+ 0.055195244f, -0.998475581f,
+ 0.053663538f, -0.998559074f,
+ 0.052131705f, -0.998640218f,
+ 0.050599749f, -0.998719012f,
+ 0.049067674f, -0.998795456f,
+ 0.047535484f, -0.998869550f,
+ 0.046003182f, -0.998941293f,
+ 0.044470772f, -0.999010686f,
+ 0.042938257f, -0.999077728f,
+ 0.041405641f, -0.999142419f,
+ 0.039872928f, -0.999204759f,
+ 0.038340120f, -0.999264747f,
+ 0.036807223f, -0.999322385f,
+ 0.035274239f, -0.999377670f,
+ 0.033741172f, -0.999430605f,
+ 0.032208025f, -0.999481187f,
+ 0.030674803f, -0.999529418f,
+ 0.029141509f, -0.999575296f,
+ 0.027608146f, -0.999618822f,
+ 0.026074718f, -0.999659997f,
+ 0.024541229f, -0.999698819f,
+ 0.023007681f, -0.999735288f,
+ 0.021474080f, -0.999769405f,
+ 0.019940429f, -0.999801170f,
+ 0.018406730f, -0.999830582f,
+ 0.016872988f, -0.999857641f,
+ 0.015339206f, -0.999882347f,
+ 0.013805389f, -0.999904701f,
+ 0.012271538f, -0.999924702f,
+ 0.010737659f, -0.999942350f,
+ 0.009203755f, -0.999957645f,
+ 0.007669829f, -0.999970586f,
+ 0.006135885f, -0.999981175f,
+ 0.004601926f, -0.999989411f,
+ 0.003067957f, -0.999995294f,
+ 0.001533980f, -0.999998823f
+};
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_f32.c
new file mode 100644
index 000000000..83d7fe7f9
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_f32.c
@@ -0,0 +1,182 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_conj_f32.c
+*
+* Description: Floating-point complex conjugate.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_conj Complex Conjugate
+ *
+ * Conjugates the elements of a complex data vector.
+ *
+ * The <code>pSrc</code> points to the source data and
+ * <code>pDst</code> points to the where the result should be written.
+ * <code>numSamples</code> specifies the number of complex samples
+ * and the data in each array is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * Each array has a total of <code>2*numSamples</code> values.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pDst[(2*n)+0)] = pSrc[(2*n)+0]; // real part
+ * pDst[(2*n)+1)] = -pSrc[(2*n)+1]; // imag part
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief Floating-point complex conjugate.
+ * @param *pSrc points to the input vector
+ * @param *pDst points to the output vector
+ * @param numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inR1, inR2, inR3, inR4;
+ float32_t inI1, inI2, inI3, inI4;
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ /* read real input samples */
+ inR1 = pSrc[0];
+ /* store real samples to destination */
+ pDst[0] = inR1;
+ inR2 = pSrc[2];
+ pDst[2] = inR2;
+ inR3 = pSrc[4];
+ pDst[4] = inR3;
+ inR4 = pSrc[6];
+ pDst[6] = inR4;
+
+ /* read imaginary input samples */
+ inI1 = pSrc[1];
+ inI2 = pSrc[3];
+
+ /* conjugate input */
+ inI1 = -inI1;
+
+ /* read imaginary input samples */
+ inI3 = pSrc[5];
+
+ /* conjugate input */
+ inI2 = -inI2;
+
+ /* read imaginary input samples */
+ inI4 = pSrc[7];
+
+ /* conjugate input */
+ inI3 = -inI3;
+
+ /* store imaginary samples to destination */
+ pDst[1] = inI1;
+ pDst[3] = inI2;
+
+ /* conjugate input */
+ inI4 = -inI4;
+
+ /* store imaginary samples to destination */
+ pDst[5] = inI3;
+
+ /* increment source pointer by 8 to process next sampels */
+ pSrc += 8u;
+
+ /* store imaginary sample to destination */
+ pDst[7] = inI4;
+
+ /* increment destination pointer by 8 to store next samples */
+ pDst += 8u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* realOut + j (imagOut) = realIn + j (-1) imagIn */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ *pDst++ = *pSrc++;
+ *pDst++ = -*pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_q15.c
new file mode 100644
index 000000000..5f13ca3cb
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_q15.c
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_conj_q15.c
+*
+* Description: Q15 complex conjugate.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief Q15 complex conjugate.
+ * @param *pSrc points to the input vector
+ * @param *pDst points to the output vector
+ * @param numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.
+ */
+
+void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+ q31_t in1, in2, in3, in4;
+ q31_t zero = 0;
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ in1 = *__SIMD32(pSrc)++;
+ in2 = *__SIMD32(pSrc)++;
+ in3 = *__SIMD32(pSrc)++;
+ in4 = *__SIMD32(pSrc)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ in1 = __QASX(zero, in1);
+ in2 = __QASX(zero, in2);
+ in3 = __QASX(zero, in3);
+ in4 = __QASX(zero, in4);
+
+#else
+
+ in1 = __QSAX(zero, in1);
+ in2 = __QSAX(zero, in2);
+ in3 = __QSAX(zero, in3);
+ in4 = __QSAX(zero, in4);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ in1 = ((uint32_t) in1 >> 16) | ((uint32_t) in1 << 16);
+ in2 = ((uint32_t) in2 >> 16) | ((uint32_t) in2 << 16);
+ in3 = ((uint32_t) in3 >> 16) | ((uint32_t) in3 << 16);
+ in4 = ((uint32_t) in4 >> 16) | ((uint32_t) in4 << 16);
+
+ *__SIMD32(pDst)++ = in1;
+ *__SIMD32(pDst)++ = in2;
+ *__SIMD32(pDst)++ = in3;
+ *__SIMD32(pDst)++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ *pDst++ = *pSrc++;
+ *pDst++ = __SSAT(-*pSrc++, 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ q15_t in;
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ *pDst++ = *pSrc++;
+ in = *pSrc++;
+ *pDst++ = (in == (q15_t) 0x8000) ? 0x7fff : -in;
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_q31.c
new file mode 100644
index 000000000..496107352
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_q31.c
@@ -0,0 +1,180 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_conj_q31.c
+*
+* Description: Q31 complex conjugate.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_conj
+ * @{
+ */
+
+/**
+ * @brief Q31 complex conjugate.
+ * @param *pSrc points to the input vector
+ * @param *pDst points to the output vector
+ * @param numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.
+ */
+
+void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ uint32_t blkCnt; /* loop counter */
+ q31_t in; /* Input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t inR1, inR2, inR3, inR4; /* Temporary real variables */
+ q31_t inI1, inI2, inI3, inI4; /* Temporary imaginary variables */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+ /* read real input sample */
+ inR1 = pSrc[0];
+ /* store real input sample */
+ pDst[0] = inR1;
+
+ /* read imaginary input sample */
+ inI1 = pSrc[1];
+
+ /* read real input sample */
+ inR2 = pSrc[2];
+ /* store real input sample */
+ pDst[2] = inR2;
+
+ /* read imaginary input sample */
+ inI2 = pSrc[3];
+
+ /* negate imaginary input sample */
+ inI1 = __QSUB(0, inI1);
+
+ /* read real input sample */
+ inR3 = pSrc[4];
+ /* store real input sample */
+ pDst[4] = inR3;
+
+ /* read imaginary input sample */
+ inI3 = pSrc[5];
+
+ /* negate imaginary input sample */
+ inI2 = __QSUB(0, inI2);
+
+ /* read real input sample */
+ inR4 = pSrc[6];
+ /* store real input sample */
+ pDst[6] = inR4;
+
+ /* negate imaginary input sample */
+ inI3 = __QSUB(0, inI3);
+
+ /* store imaginary input sample */
+ inI4 = pSrc[7];
+
+ /* store imaginary input samples */
+ pDst[1] = inI1;
+
+ /* negate imaginary input sample */
+ inI4 = __QSUB(0, inI4);
+
+ /* store imaginary input samples */
+ pDst[3] = inI2;
+
+ /* increment source pointer by 8 to proecess next samples */
+ pSrc += 8u;
+
+ /* store imaginary input samples */
+ pDst[5] = inI3;
+ pDst[7] = inI4;
+
+ /* increment destination pointer by 8 to process next samples */
+ pDst += 8u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+ /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+ /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+ *pDst++ = *pSrc++;
+ in = *pSrc++;
+ *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_conj group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
new file mode 100644
index 000000000..da7c5517c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
@@ -0,0 +1,168 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_dot_prod_f32.c
+*
+* Description: Floating-point complex dot product
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_dot_prod Complex Dot Product
+ *
+ * Computes the dot product of two complex vectors.
+ * The vectors are multiplied element-by-element and then summed.
+ *
+ * The <code>pSrcA</code> points to the first complex input vector and
+ * <code>pSrcB</code> points to the second complex input vector.
+ * <code>numSamples</code> specifies the number of complex samples
+ * and the data in each array is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * Each array has a total of <code>2*numSamples</code> values.
+ *
+ * The underlying algorithm is used:
+ * <pre>
+ * realResult=0;
+ * imagResult=0;
+ * for(n=0; n<numSamples; n++) {
+ * realResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+0] - pSrcA[(2*n)+1]*pSrcB[(2*n)+1];
+ * imagResult += pSrcA[(2*n)+0]*pSrcB[(2*n)+1] + pSrcA[(2*n)+1]*pSrcB[(2*n)+0];
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief Floating-point complex dot product
+ * @param *pSrcA points to the first input vector
+ * @param *pSrcB points to the second input vector
+ * @param numSamples number of complex samples in each vector
+ * @param *realResult real part of the result returned here
+ * @param *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult)
+{
+ float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ real_sum += (*pSrcA++) * (*pSrcB++);
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ imag_sum += (*pSrcA++) * (*pSrcB++);
+
+ real_sum += (*pSrcA++) * (*pSrcB++);
+ imag_sum += (*pSrcA++) * (*pSrcB++);
+
+ real_sum += (*pSrcA++) * (*pSrcB++);
+ imag_sum += (*pSrcA++) * (*pSrcB++);
+
+ real_sum += (*pSrcA++) * (*pSrcB++);
+ imag_sum += (*pSrcA++) * (*pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ real_sum += (*pSrcA++) * (*pSrcB++);
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ imag_sum += (*pSrcA++) * (*pSrcB++);
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ real_sum += (*pSrcA++) * (*pSrcB++);
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ imag_sum += (*pSrcA++) * (*pSrcB++);
+
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the real and imaginary results in the destination buffers */
+ *realResult = real_sum;
+ *imagResult = imag_sum;
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
new file mode 100644
index 000000000..1d168d7c9
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_dot_prod_q15.c
+*
+* Description: Processing function for the Q15 Complex Dot product
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief Q15 complex dot product
+ * @param *pSrcA points to the first input vector
+ * @param *pSrcB points to the second input vector
+ * @param numSamples number of complex samples in each vector
+ * @param *realResult real part of the result returned here
+ * @param *imagResult imaginary part of the result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.
+ * These are accumulated in a 64-bit accumulator with 34.30 precision.
+ * As a final step, the accumulators are converted to 8.24 format.
+ * The return results <code>realResult</code> and <code>imagResult</code> are in 8.24 format.
+ */
+
+void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult)
+{
+ q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+ real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+ imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+ real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+ imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+ real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+ imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the real and imaginary results in 8.24 format */
+ /* Convert real data in 34.30 to 8.24 by 6 right shifts */
+ *realResult = (q31_t) (real_sum) >> 6;
+ /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
+ *imagResult = (q31_t) (imag_sum) >> 6;
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
new file mode 100644
index 000000000..f7e2363bc
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_dot_prod_q31.c
+*
+* Description: Q31 complex dot product
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_dot_prod
+ * @{
+ */
+
+/**
+ * @brief Q31 complex dot product
+ * @param *pSrcA points to the first input vector
+ * @param *pSrcB points to the second input vector
+ * @param numSamples number of complex samples in each vector
+ * @param *realResult real part of the result returned here
+ * @param *imagResult imaginary part of the result returned here
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.
+ * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.
+ * Additions are nonsaturating and no overflow will occur as long as <code>numSamples</code> is less than 32768.
+ * The return results <code>realResult</code> and <code>imagResult</code> are in 16.48 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult)
+{
+ q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ /* Convert real data in 2.62 to 16.48 by 14 right shifts */
+ real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ /* Convert imag data in 2.62 to 16.48 by 14 right shifts */
+ imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+ real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+ imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+ real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+ imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+ real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+ imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+ real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+ /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+ imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* outReal = realA[0]* realB[0] + realA[2]* realB[2] + realA[4]* realB[4] + .....+ realA[numSamples-2]* realB[numSamples-2] */
+ real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+ /* outImag = imagA[1]* imagB[1] + imagA[3]* imagB[3] + imagA[5]* imagB[5] + .....+ imagA[numSamples-1]* imagB[numSamples-1] */
+ imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the real and imaginary results in 16.48 format */
+ *realResult = real_sum;
+ *imagResult = imag_sum;
+}
+
+/**
+ * @} end of cmplx_dot_prod group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_f32.c
new file mode 100644
index 000000000..2dc16b1a7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_f32.c
+*
+* Description: Floating-point complex magnitude.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_mag Complex Magnitude
+ *
+ * Computes the magnitude of the elements of a complex data vector.
+ *
+ * The <code>pSrc</code> points to the source data and
+ * <code>pDst</code> points to the where the result should be written.
+ * <code>numSamples</code> specifies the number of complex samples
+ * in the input array and the data is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The input array has a total of <code>2*numSamples</code> values;
+ * the output array has a total of <code>numSamples</code> values.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pDst[n] = sqrt(pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2);
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+/**
+ * @brief Floating-point complex magnitude.
+ * @param[in] *pSrc points to complex input buffer
+ * @param[out] *pDst points to real output buffer
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ */
+
+
+void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ float32_t realIn, imagIn; /* Temporary variables to hold input values */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ /* store the result in the destination buffer. */
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ /* store the result in the destination buffer. */
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* out = sqrt((real * real) + (imag * imag)) */
+ realIn = *pSrc++;
+ imagIn = *pSrc++;
+ /* store the result in the destination buffer. */
+ arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q15.c
new file mode 100644
index 000000000..89decf2b5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q15.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_q15.c
+*
+* Description: Q15 complex magnitude.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+
+
+/**
+ * @brief Q15 complex magnitude
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.
+ */
+
+void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t acc0, acc1; /* Accumulators */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+ q31_t in1, in2, in3, in4;
+ q31_t acc2, acc3;
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ in2 = *__SIMD32(pSrc)++;
+ in3 = *__SIMD32(pSrc)++;
+ in4 = *__SIMD32(pSrc)++;
+
+ acc0 = __SMUAD(in1, in1);
+ acc1 = __SMUAD(in2, in2);
+ acc2 = __SMUAD(in3, in3);
+ acc3 = __SMUAD(in4, in4);
+
+ /* store the result in 2.14 format in the destination buffer. */
+ arm_sqrt_q15((q15_t) ((acc0) >> 17), pDst++);
+ arm_sqrt_q15((q15_t) ((acc1) >> 17), pDst++);
+ arm_sqrt_q15((q15_t) ((acc2) >> 17), pDst++);
+ arm_sqrt_q15((q15_t) ((acc3) >> 17), pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ acc0 = __SMUAD(in1, in1);
+
+ /* store the result in 2.14 format in the destination buffer. */
+ arm_sqrt_q15((q15_t) (acc0 >> 17), pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t real, imag; /* Temporary variables to hold input values */
+
+ while(numSamples > 0u)
+ {
+ /* out = sqrt(real * real + imag * imag) */
+ real = *pSrc++;
+ imag = *pSrc++;
+
+ acc0 = (real * real);
+ acc1 = (imag * imag);
+
+ /* store the result in 2.14 format in the destination buffer. */
+ arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q31.c
new file mode 100644
index 000000000..c92fcb46f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q31.c
@@ -0,0 +1,185 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_q31.c
+*
+* Description: Q31 complex magnitude
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag
+ * @{
+ */
+
+/**
+ * @brief Q31 complex magnitude
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t real, imag; /* Temporary variables to hold input values */
+ q31_t acc0, acc1; /* Accumulators */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t real1, real2, imag1, imag2; /* Temporary variables to hold input values */
+ q31_t out1, out2, out3, out4; /* Accumulators */
+ q63_t mul1, mul2, mul3, mul4; /* Temporary variables */
+
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* read complex input from source buffer */
+ real1 = pSrc[0];
+ imag1 = pSrc[1];
+ real2 = pSrc[2];
+ imag2 = pSrc[3];
+
+ /* calculate power of input values */
+ mul1 = (q63_t) real1 *real1;
+ mul2 = (q63_t) imag1 *imag1;
+ mul3 = (q63_t) real2 *real2;
+ mul4 = (q63_t) imag2 *imag2;
+
+ /* get the result to 3.29 format */
+ out1 = (q31_t) (mul1 >> 33);
+ out2 = (q31_t) (mul2 >> 33);
+ out3 = (q31_t) (mul3 >> 33);
+ out4 = (q31_t) (mul4 >> 33);
+
+ /* add real and imaginary accumulators */
+ out1 = out1 + out2;
+ out3 = out3 + out4;
+
+ /* read complex input from source buffer */
+ real1 = pSrc[4];
+ imag1 = pSrc[5];
+ real2 = pSrc[6];
+ imag2 = pSrc[7];
+
+ /* calculate square root */
+ arm_sqrt_q31(out1, &pDst[0]);
+
+ /* calculate power of input values */
+ mul1 = (q63_t) real1 *real1;
+
+ /* calculate square root */
+ arm_sqrt_q31(out3, &pDst[1]);
+
+ /* calculate power of input values */
+ mul2 = (q63_t) imag1 *imag1;
+ mul3 = (q63_t) real2 *real2;
+ mul4 = (q63_t) imag2 *imag2;
+
+ /* get the result to 3.29 format */
+ out1 = (q31_t) (mul1 >> 33);
+ out2 = (q31_t) (mul2 >> 33);
+ out3 = (q31_t) (mul3 >> 33);
+ out4 = (q31_t) (mul4 >> 33);
+
+ /* add real and imaginary accumulators */
+ out1 = out1 + out2;
+ out3 = out3 + out4;
+
+ /* calculate square root */
+ arm_sqrt_q31(out1, &pDst[2]);
+
+ /* increment destination by 8 to process next samples */
+ pSrc += 8u;
+
+ /* calculate square root */
+ arm_sqrt_q31(out3, &pDst[3]);
+
+ /* increment destination by 4 to process next samples */
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 2.30 format in the destination buffer. */
+ arm_sqrt_q31(acc0 + acc1, pDst++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_mag group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
new file mode 100644
index 000000000..abc36976d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
@@ -0,0 +1,215 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_squared_f32.c
+*
+* Description: Floating-point complex magnitude squared.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup cmplx_mag_squared Complex Magnitude Squared
+ *
+ * Computes the magnitude squared of the elements of a complex data vector.
+ *
+ * The <code>pSrc</code> points to the source data and
+ * <code>pDst</code> points to the where the result should be written.
+ * <code>numSamples</code> specifies the number of complex samples
+ * in the input array and the data is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The input array has a total of <code>2*numSamples</code> values;
+ * the output array has a total of <code>numSamples</code> values.
+ *
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pDst[n] = pSrc[(2*n)+0]^2 + pSrc[(2*n)+1]^2;
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ float32_t real, imag; /* Temporary variables to store real and imaginary values */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+ float32_t real1, real2, real3, real4; /* Temporary variables to hold real values */
+ float32_t imag1, imag2, imag3, imag4; /* Temporary variables to hold imaginary values */
+ float32_t mul1, mul2, mul3, mul4; /* Temporary variables */
+ float32_t mul5, mul6, mul7, mul8; /* Temporary variables */
+ float32_t out1, out2, out3, out4; /* Temporary variables to hold output values */
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ /* read real input sample from source buffer */
+ real1 = pSrc[0];
+ /* read imaginary input sample from source buffer */
+ imag1 = pSrc[1];
+
+ /* calculate power of real value */
+ mul1 = real1 * real1;
+
+ /* read real input sample from source buffer */
+ real2 = pSrc[2];
+
+ /* calculate power of imaginary value */
+ mul2 = imag1 * imag1;
+
+ /* read imaginary input sample from source buffer */
+ imag2 = pSrc[3];
+
+ /* calculate power of real value */
+ mul3 = real2 * real2;
+
+ /* read real input sample from source buffer */
+ real3 = pSrc[4];
+
+ /* calculate power of imaginary value */
+ mul4 = imag2 * imag2;
+
+ /* read imaginary input sample from source buffer */
+ imag3 = pSrc[5];
+
+ /* calculate power of real value */
+ mul5 = real3 * real3;
+ /* calculate power of imaginary value */
+ mul6 = imag3 * imag3;
+
+ /* read real input sample from source buffer */
+ real4 = pSrc[6];
+
+ /* accumulate real and imaginary powers */
+ out1 = mul1 + mul2;
+
+ /* read imaginary input sample from source buffer */
+ imag4 = pSrc[7];
+
+ /* accumulate real and imaginary powers */
+ out2 = mul3 + mul4;
+
+ /* calculate power of real value */
+ mul7 = real4 * real4;
+ /* calculate power of imaginary value */
+ mul8 = imag4 * imag4;
+
+ /* store output to destination */
+ pDst[0] = out1;
+
+ /* accumulate real and imaginary powers */
+ out3 = mul5 + mul6;
+
+ /* store output to destination */
+ pDst[1] = out2;
+
+ /* accumulate real and imaginary powers */
+ out4 = mul7 + mul8;
+
+ /* store output to destination */
+ pDst[2] = out3;
+
+ /* increment destination pointer by 8 to process next samples */
+ pSrc += 8u;
+
+ /* store output to destination */
+ pDst[3] = out4;
+
+ /* increment destination pointer by 4 to process next samples */
+ pDst += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+
+ /* out = (real * real) + (imag * imag) */
+ /* store the result in the destination buffer. */
+ *pDst++ = (real * real) + (imag * imag);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
new file mode 100644
index 000000000..2dfce2ca1
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_squared_q15.c
+*
+* Description: Q15 complex magnitude squared.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+/**
+ * @brief Q15 complex magnitude squared
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.
+ */
+
+void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t acc0, acc1; /* Accumulators */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+ q31_t in1, in2, in3, in4;
+ q31_t acc2, acc3;
+
+ /*loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ in2 = *__SIMD32(pSrc)++;
+ in3 = *__SIMD32(pSrc)++;
+ in4 = *__SIMD32(pSrc)++;
+
+ acc0 = __SMUAD(in1, in1);
+ acc1 = __SMUAD(in2, in2);
+ acc2 = __SMUAD(in3, in3);
+ acc3 = __SMUAD(in4, in4);
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ = (q15_t) (acc0 >> 17);
+ *pDst++ = (q15_t) (acc1 >> 17);
+ *pDst++ = (q15_t) (acc2 >> 17);
+ *pDst++ = (q15_t) (acc3 >> 17);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ in1 = *__SIMD32(pSrc)++;
+ acc0 = __SMUAD(in1, in1);
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ = (q15_t) (acc0 >> 17);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t real, imag; /* Temporary variables to store real and imaginary values */
+
+ while(numSamples > 0u)
+ {
+ /* out = ((real * real) + (imag * imag)) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (real * real);
+ acc1 = (imag * imag);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
new file mode 100644
index 000000000..3d1408069
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
@@ -0,0 +1,161 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mag_squared_q31.c
+*
+* Description: Q31 complex magnitude squared.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup cmplx_mag_squared
+ * @{
+ */
+
+
+/**
+ * @brief Q31 complex magnitude squared
+ * @param *pSrc points to the complex input vector
+ * @param *pDst points to the real output vector
+ * @param numSamples number of complex samples in the input vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t real, imag; /* Temporary variables to store real and imaginary values */
+ q31_t acc0, acc1; /* Accumulators */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counter */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* out = ((real * real) + (imag * imag)) */
+ real = *pSrc++;
+ imag = *pSrc++;
+ acc0 = (q31_t) (((q63_t) real * real) >> 33);
+ acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+ /* store the result in 3.29 format in the destination buffer. */
+ *pDst++ = acc0 + acc1;
+
+ /* Decrement the loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of cmplx_mag_squared group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
new file mode 100644
index 000000000..1fe0f36b7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_cmplx_f32.c
+*
+* Description: Floating-point complex-by-complex multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication
+ *
+ * Multiplies a complex vector by another complex vector and generates a complex result.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The parameter <code>numSamples</code> represents the number of complex
+ * samples processed. The complex arrays have a total of <code>2*numSamples</code>
+ * real values.
+ *
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pDst[(2*n)+0] = pSrcA[(2*n)+0] * pSrcB[(2*n)+0] - pSrcA[(2*n)+1] * pSrcB[(2*n)+1];
+ * pDst[(2*n)+1] = pSrcA[(2*n)+0] * pSrcB[(2*n)+1] + pSrcA[(2*n)+1] * pSrcB[(2*n)+0];
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples)
+{
+ float32_t a1, b1, c1, d1; /* Temporary variables to store real and imaginary values */
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t a2, b2, c2, d2; /* Temporary variables to store real and imaginary values */
+ float32_t acc1, acc2, acc3, acc4;
+
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a1 = *pSrcA; /* A[2 * i] */
+ c1 = *pSrcB; /* B[2 * i] */
+
+ b1 = *(pSrcA + 1); /* A[2 * i + 1] */
+ acc1 = a1 * c1; /* acc1 = A[2 * i] * B[2 * i] */
+
+ a2 = *(pSrcA + 2); /* A[2 * i + 2] */
+ acc2 = (b1 * c1); /* acc2 = A[2 * i + 1] * B[2 * i] */
+
+ d1 = *(pSrcB + 1); /* B[2 * i + 1] */
+ c2 = *(pSrcB + 2); /* B[2 * i + 2] */
+ acc1 -= b1 * d1; /* acc1 = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
+
+ d2 = *(pSrcB + 3); /* B[2 * i + 3] */
+ acc3 = a2 * c2; /* acc3 = A[2 * i + 2] * B[2 * i + 2] */
+
+ b2 = *(pSrcA + 3); /* A[2 * i + 3] */
+ acc2 += (a1 * d1); /* acc2 = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
+
+ a1 = *(pSrcA + 4); /* A[2 * i + 4] */
+ acc4 = (a2 * d2); /* acc4 = A[2 * i + 2] * B[2 * i + 3] */
+
+ c1 = *(pSrcB + 4); /* B[2 * i + 4] */
+ acc3 -= (b2 * d2); /* acc3 = A[2 * i + 2] * B[2 * i + 2] - A[2 * i + 3] * B[2 * i + 3] */
+ *pDst = acc1; /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1] */
+
+ b1 = *(pSrcA + 5); /* A[2 * i + 5] */
+ acc4 += b2 * c2; /* acc4 = A[2 * i + 2] * B[2 * i + 3] + A[2 * i + 3] * B[2 * i + 2] */
+
+ *(pDst + 1) = acc2; /* C[2 * i + 1] = A[2 * i + 1] * B[2 * i] + A[2 * i] * B[2 * i + 1] */
+ acc1 = (a1 * c1);
+
+ d1 = *(pSrcB + 5);
+ acc2 = (b1 * c1);
+
+ *(pDst + 2) = acc3;
+ *(pDst + 3) = acc4;
+
+ a2 = *(pSrcA + 6);
+ acc1 -= (b1 * d1);
+
+ c2 = *(pSrcB + 6);
+ acc2 += (a1 * d1);
+
+ b2 = *(pSrcA + 7);
+ acc3 = (a2 * c2);
+
+ d2 = *(pSrcB + 7);
+ acc4 = (b2 * c2);
+
+ *(pDst + 4) = acc1;
+ pSrcA += 8u;
+
+ acc3 -= (b2 * d2);
+ acc4 += (a2 * d2);
+
+ *(pDst + 5) = acc2;
+ pSrcB += 8u;
+
+ *(pDst + 6) = acc3;
+ *(pDst + 7) = acc4;
+
+ pDst += 8u;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a1 = *pSrcA++;
+ b1 = *pSrcA++;
+ c1 = *pSrcB++;
+ d1 = *pSrcB++;
+
+ /* store the result in the destination buffer. */
+ *pDst++ = (a1 * c1) - (b1 * d1);
+ *pDst++ = (a1 * d1) + (b1 * c1);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
new file mode 100644
index 000000000..a775d9831
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
@@ -0,0 +1,193 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_cmplx_q15.c
+*
+* Description: Q15 complex-by-complex multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+/**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.
+ */
+
+void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples)
+{
+ q15_t a, b, c, d; /* Temporary variables to store real and imaginary values */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counters */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+ /* store the result in 3.13 format in the destination buffer. */
+ *pDst++ =
+ (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+ /* Decrement the blockSize loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
new file mode 100644
index 000000000..7b91b35ea
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
@@ -0,0 +1,326 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_cmplx_q31.c
+*
+* Description: Q31 complex-by-complex multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByCmplxMult
+ * @{
+ */
+
+
+/**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.
+ * Input down scaling is not required.
+ */
+
+void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples)
+{
+ q31_t a, b, c, d; /* Temporary variables to store real and imaginary values */
+ uint32_t blkCnt; /* loop counters */
+ q31_t mul1, mul2, mul3, mul4;
+ q31_t out1, out2;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 1u;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ ** a second loop below computes the remaining 1 sample. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x2u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1]. */
+ /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i]. */
+ a = *pSrcA++;
+ b = *pSrcA++;
+ c = *pSrcB++;
+ d = *pSrcB++;
+
+ mul1 = (q31_t) (((q63_t) a * c) >> 32);
+ mul2 = (q31_t) (((q63_t) b * d) >> 32);
+ mul3 = (q31_t) (((q63_t) a * d) >> 32);
+ mul4 = (q31_t) (((q63_t) b * c) >> 32);
+
+ mul1 = (mul1 >> 1);
+ mul2 = (mul2 >> 1);
+ mul3 = (mul3 >> 1);
+ mul4 = (mul4 >> 1);
+
+ out1 = mul1 - mul2;
+ out2 = mul3 + mul4;
+
+ /* store the real result in 3.29 format in the destination buffer. */
+ *pDst++ = out1;
+ /* store the imag result in 3.29 format in the destination buffer. */
+ *pDst++ = out2;
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of CmplxByCmplxMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
new file mode 100644
index 000000000..10d3f512c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
@@ -0,0 +1,225 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_real_f32.c
+*
+* Description: Floating-point complex by real multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @defgroup CmplxByRealMult Complex-by-Real Multiplication
+ *
+ * Multiplies a complex vector by a real vector and generates a complex result.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * The parameter <code>numSamples</code> represents the number of complex
+ * samples processed. The complex arrays have a total of <code>2*numSamples</code>
+ * real values while the real array has a total of <code>numSamples</code>
+ * real values.
+ *
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * for(n=0; n<numSamples; n++) {
+ * pCmplxDst[(2*n)+0] = pSrcCmplx[(2*n)+0] * pSrcReal[n];
+ * pCmplxDst[(2*n)+1] = pSrcCmplx[(2*n)+1] * pSrcReal[n];
+ * }
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q15, and Q31 data types.
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ float32_t in; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t inA1, inA2, inA3, inA4; /* Temporary variables to hold input data */
+ float32_t inA5, inA6, inA7, inA8; /* Temporary variables to hold input data */
+ float32_t inB1, inB2, inB3, inB4; /* Temporary variables to hold input data */
+ float32_t out1, out2, out3, out4; /* Temporary variables to hold output data */
+ float32_t out5, out6, out7, out8; /* Temporary variables to hold output data */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read input from complex input buffer */
+ inA1 = pSrcCmplx[0];
+ inA2 = pSrcCmplx[1];
+ /* read input from real input buffer */
+ inB1 = pSrcReal[0];
+
+ /* read input from complex input buffer */
+ inA3 = pSrcCmplx[2];
+
+ /* multiply complex buffer real input with real buffer input */
+ out1 = inA1 * inB1;
+
+ /* read input from complex input buffer */
+ inA4 = pSrcCmplx[3];
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out2 = inA2 * inB1;
+
+ /* read input from real input buffer */
+ inB2 = pSrcReal[1];
+ /* read input from complex input buffer */
+ inA5 = pSrcCmplx[4];
+
+ /* multiply complex buffer real input with real buffer input */
+ out3 = inA3 * inB2;
+
+ /* read input from complex input buffer */
+ inA6 = pSrcCmplx[5];
+ /* read input from real input buffer */
+ inB3 = pSrcReal[2];
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out4 = inA4 * inB2;
+
+ /* read input from complex input buffer */
+ inA7 = pSrcCmplx[6];
+
+ /* multiply complex buffer real input with real buffer input */
+ out5 = inA5 * inB3;
+
+ /* read input from complex input buffer */
+ inA8 = pSrcCmplx[7];
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out6 = inA6 * inB3;
+
+ /* read input from real input buffer */
+ inB4 = pSrcReal[3];
+
+ /* store result to destination bufer */
+ pCmplxDst[0] = out1;
+
+ /* multiply complex buffer real input with real buffer input */
+ out7 = inA7 * inB4;
+
+ /* store result to destination bufer */
+ pCmplxDst[1] = out2;
+
+ /* multiply complex buffer imaginary input with real buffer input */
+ out8 = inA8 * inB4;
+
+ /* store result to destination bufer */
+ pCmplxDst[2] = out3;
+ pCmplxDst[3] = out4;
+ pCmplxDst[4] = out5;
+
+ /* incremnet complex input buffer by 8 to process next samples */
+ pSrcCmplx += 8u;
+
+ /* store result to destination bufer */
+ pCmplxDst[5] = out6;
+
+ /* increment real input buffer by 4 to process next samples */
+ pSrcReal += 4u;
+
+ /* store result to destination bufer */
+ pCmplxDst[6] = out7;
+ pCmplxDst[7] = out8;
+
+ /* increment destination buffer by 8 to process next sampels */
+ pCmplxDst += 8u;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ in = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ = (*pSrcCmplx++) * (in);
+ *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
new file mode 100644
index 000000000..0bba42363
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_real_q15.c
+*
+* Description: Q15 complex by real multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ q15_t in; /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counters */
+ q31_t inA1, inA2; /* Temporary variables to hold input data */
+ q31_t inB1; /* Temporary variables to hold input data */
+ q15_t out1, out2, out3, out4; /* Temporary variables to hold output data */
+ q31_t mul1, mul2, mul3, mul4; /* Temporary variables to hold intermediate data */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read complex number both real and imaginary from complex input buffer */
+ inA1 = *__SIMD32(pSrcCmplx)++;
+ /* read two real values at a time from real input buffer */
+ inB1 = *__SIMD32(pSrcReal)++;
+ /* read complex number both real and imaginary from complex input buffer */
+ inA2 = *__SIMD32(pSrcCmplx)++;
+
+ /* multiply complex number with real numbers */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+ mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+
+#else
+
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+ mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+ mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ /* saturate the result */
+ out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
+ out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
+ out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
+ out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
+
+ /* pack real and imaginary outputs and store them to destination */
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
+
+ inA1 = *__SIMD32(pSrcCmplx)++;
+ inB1 = *__SIMD32(pSrcReal)++;
+ inA2 = *__SIMD32(pSrcCmplx)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ mul1 = (q31_t) ((q15_t) (inA1) * (q15_t) (inB1));
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1));
+ mul3 = (q31_t) ((q15_t) (inA2) * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) (inB1 >> 16));
+
+#else
+
+ mul2 = (q31_t) ((q15_t) (inA1 >> 16) * (q15_t) (inB1 >> 16));
+ mul1 = (q31_t) ((q15_t) inA1 * (q15_t) (inB1 >> 16));
+ mul4 = (q31_t) ((q15_t) (inA2 >> 16) * (q15_t) inB1);
+ mul3 = (q31_t) ((q15_t) inA2 * (q15_t) inB1);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = (q15_t) __SSAT(mul1 >> 15u, 16);
+ out2 = (q15_t) __SSAT(mul2 >> 15u, 16);
+ out3 = (q15_t) __SSAT(mul3 >> 15u, 16);
+ out4 = (q15_t) __SSAT(mul4 >> 15u, 16);
+
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out1, out2, 16);
+ *__SIMD32(pCmplxDst)++ = __PKHBT(out3, out4, 16);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ in = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* realOut = realA * realB. */
+ /* imagOut = imagA * realB. */
+ in = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+ *pCmplxDst++ =
+ (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+ /* Decrement the numSamples loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
new file mode 100644
index 000000000..44641ea2b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
@@ -0,0 +1,223 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cmplx_mult_real_q31.c
+*
+* Description: Q31 complex by real multiplication
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupCmplxMath
+ */
+
+/**
+ * @addtogroup CmplxByRealMult
+ * @{
+ */
+
+
+/**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples)
+{
+ q31_t inA1; /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ uint32_t blkCnt; /* loop counters */
+ q31_t inA2, inA3, inA4; /* Temporary variables to hold input data */
+ q31_t inB1, inB2; /* Temporary variabels to hold input data */
+ q31_t out1, out2, out3, out4; /* Temporary variables to hold output data */
+
+ /* loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read real input from complex input buffer */
+ inA1 = *pSrcCmplx++;
+ inA2 = *pSrcCmplx++;
+ /* read input from real input bufer */
+ inB1 = *pSrcReal++;
+ inB2 = *pSrcReal++;
+ /* read imaginary input from complex input buffer */
+ inA3 = *pSrcCmplx++;
+ inA4 = *pSrcCmplx++;
+
+ /* multiply complex input with real input */
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB1) >> 32;
+ out3 = ((q63_t) inA3 * inB2) >> 32;
+ out4 = ((q63_t) inA4 * inB2) >> 32;
+
+ /* sature the result */
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+ out3 = __SSAT(out3, 31);
+ out4 = __SSAT(out4, 31);
+
+ /* get result in 1.31 format */
+ out1 = out1 << 1;
+ out2 = out2 << 1;
+ out3 = out3 << 1;
+ out4 = out4 << 1;
+
+ /* store the result to destination buffer */
+ *pCmplxDst++ = out1;
+ *pCmplxDst++ = out2;
+ *pCmplxDst++ = out3;
+ *pCmplxDst++ = out4;
+
+ /* read real input from complex input buffer */
+ inA1 = *pSrcCmplx++;
+ inA2 = *pSrcCmplx++;
+ /* read input from real input bufer */
+ inB1 = *pSrcReal++;
+ inB2 = *pSrcReal++;
+ /* read imaginary input from complex input buffer */
+ inA3 = *pSrcCmplx++;
+ inA4 = *pSrcCmplx++;
+
+ /* multiply complex input with real input */
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB1) >> 32;
+ out3 = ((q63_t) inA3 * inB2) >> 32;
+ out4 = ((q63_t) inA4 * inB2) >> 32;
+
+ /* sature the result */
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+ out3 = __SSAT(out3, 31);
+ out4 = __SSAT(out4, 31);
+
+ /* get result in 1.31 format */
+ out1 = out1 << 1;
+ out2 = out2 << 1;
+ out3 = out3 << 1;
+ out4 = out4 << 1;
+
+ /* store the result to destination buffer */
+ *pCmplxDst++ = out1;
+ *pCmplxDst++ = out2;
+ *pCmplxDst++ = out3;
+ *pCmplxDst++ = out4;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C[2 * i] = A[2 * i] * B[i]. */
+ /* C[2 * i + 1] = A[2 * i + 1] * B[i]. */
+ /* read real input from complex input buffer */
+ inA1 = *pSrcCmplx++;
+ inA2 = *pSrcCmplx++;
+ /* read input from real input bufer */
+ inB1 = *pSrcReal++;
+
+ /* multiply complex input with real input */
+ out1 = ((q63_t) inA1 * inB1) >> 32;
+ out2 = ((q63_t) inA2 * inB1) >> 32;
+
+ /* sature the result */
+ out1 = __SSAT(out1, 31);
+ out2 = __SSAT(out2, 31);
+
+ /* get result in 1.31 format */
+ out1 = out1 << 1;
+ out2 = out2 << 1;
+
+ /* store the result to destination buffer */
+ *pCmplxDst++ = out1;
+ *pCmplxDst++ = out2;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(numSamples > 0u)
+ {
+ /* realOut = realA * realB. */
+ /* imagReal = imagA * realB. */
+ inA1 = *pSrcReal++;
+ /* store the result in the destination buffer. */
+ *pCmplxDst++ =
+ (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
+ *pCmplxDst++ =
+ (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * inA1) >> 31);
+
+ /* Decrement the numSamples loop counter */
+ numSamples--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of CmplxByRealMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_f32.c
new file mode 100644
index 000000000..cc1fc99a0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_f32.c
@@ -0,0 +1,87 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_init_f32.c
+*
+* Description: Floating-point PID Control initialization function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state & 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The <code>resetStateFlag</code> specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: <code>A0</code>, <code>A1</code> <code>A2</code>
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag)
+{
+
+ /* Derived coefficient A0 */
+ S->A0 = S->Kp + S->Ki + S->Kd;
+
+ /* Derived coefficient A1 */
+ S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);
+
+ /* Derived coefficient A2 */
+ S->A2 = S->Kd;
+
+ /* Check whether state needs reset or not */
+ if(resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(float32_t));
+ }
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_q15.c
new file mode 100644
index 000000000..8f293f6e3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_q15.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_init_q15.c
+*
+* Description: Q15 PID Control initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @details
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The <code>resetStateFlag</code> specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: <code>A0</code>, <code>A1</code> <code>A2</code>
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Derived coefficient A0 */
+ S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);
+
+ /* Derived coefficients and pack into A1 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);
+
+#else
+
+ S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Check whether state needs reset or not */
+ if(resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q15_t));
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t temp; /*to store the sum */
+
+ /* Derived coefficient A0 */
+ temp = S->Kp + S->Ki + S->Kd;
+ S->A0 = (q15_t) __SSAT(temp, 16);
+
+ /* Derived coefficients and pack into A1 */
+ temp = -(S->Kd + S->Kd + S->Kp);
+ S->A1 = (q15_t) __SSAT(temp, 16);
+ S->A2 = S->Kd;
+
+
+
+ /* Check whether state needs reset or not */
+ if(resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q15_t));
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_q31.c
new file mode 100644
index 000000000..b492cf79f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_q31.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_init_q31.c
+*
+* Description: Q31 PID Control initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ * \par Description:
+ * \par
+ * The <code>resetStateFlag</code> specifies whether to set state to zero or not. \n
+ * The function computes the structure fields: <code>A0</code>, <code>A1</code> <code>A2</code>
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)
+ * also sets the state variables to all zeros.
+ */
+
+void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Derived coefficient A0 */
+ S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
+
+ /* Derived coefficient A1 */
+ S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t temp;
+
+ /* Derived coefficient A0 */
+ temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
+ S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
+
+ /* Derived coefficient A1 */
+ temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
+ S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Derived coefficient A2 */
+ S->A2 = S->Kd;
+
+ /* Check whether state needs reset or not */
+ if(resetStateFlag)
+ {
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q31_t));
+ }
+
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_f32.c
new file mode 100644
index 000000000..c6753b1b5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_f32.c
@@ -0,0 +1,65 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_reset_f32.c
+*
+* Description: Floating-point PID Control reset function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief Reset function for the floating-point PID Control.
+* @param[in] *S Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S)
+{
+
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(float32_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_q15.c
new file mode 100644
index 000000000..410339e59
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_q15.c
@@ -0,0 +1,64 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_reset_q15.c
+*
+* Description: Q15 PID Control reset function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief Reset function for the Q15 PID Control.
+* @param[in] *S Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S)
+{
+ /* Reset state to zero, The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q15_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_q31.c
new file mode 100644
index 000000000..fd8208008
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_q31.c
@@ -0,0 +1,65 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_pid_reset_q31.c
+*
+* Description: Q31 PID Control reset function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+/**
+* @brief Reset function for the Q31 PID Control.
+* @param[in] *S Instance pointer of PID control data structure.
+* @return none.
+* \par Description:
+* The function resets the state buffer to zeros.
+*/
+void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S)
+{
+
+ /* Clear the state buffer. The size will be always 3 samples */
+ memset(S->state, 0, 3u * sizeof(q31_t));
+}
+
+/**
+ * @} end of PID group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_sin_cos_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_sin_cos_f32.c
new file mode 100644
index 000000000..4658f9a2a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_sin_cos_f32.c
@@ -0,0 +1,436 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_cos_f32.c
+*
+* Description: Sine and Cosine calculation for floating-point values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupController
+ */
+
+/**
+ * @defgroup SinCos Sine Cosine
+ *
+ * Computes the trigonometric sine and cosine values using a combination of table lookup
+ * and linear interpolation.
+ * There are separate functions for Q31 and floating-point data types.
+ * The input to the floating-point version is in degrees while the
+ * fixed-point Q31 have a scaled input with the range
+ * [-1 0.9999] mapping to [-180 179] degrees.
+ *
+ * The implementation is based on table lookup using 360 values together with linear interpolation.
+ * The steps used are:
+ * -# Calculation of the nearest integer table index.
+ * -# Compute the fractional portion (fract) of the input.
+ * -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.
+ * -# Sine value is computed as <code> *psinVal = y0 + (fract * (y1 - y0))</code>.
+ * -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.
+ * -# Cosine value is computed as <code> *pcosVal = y0 + (fract * (y1 - y0))</code>.
+ */
+
+ /**
+ * @addtogroup SinCos
+ * @{
+ */
+
+
+/**
+* \par
+* Cosine Table is generated from following loop
+* <pre>for(i = 0; i < 360; i++)
+* {
+* cosTable[i]= cos((i-180) * PI/180.0);
+* } </pre>
+*/
+
+static const float32_t cosTable[360] = {
+ -0.999847695156391270f, -0.999390827019095760f, -0.998629534754573830f,
+ -0.997564050259824200f, -0.996194698091745550f, -0.994521895368273290f,
+ -0.992546151641321980f, -0.990268068741570250f,
+ -0.987688340595137660f, -0.984807753012208020f, -0.981627183447663980f,
+ -0.978147600733805690f, -0.974370064785235250f, -0.970295726275996470f,
+ -0.965925826289068200f, -0.961261695938318670f,
+ -0.956304755963035440f, -0.951056516295153530f, -0.945518575599316740f,
+ -0.939692620785908320f, -0.933580426497201740f, -0.927183854566787310f,
+ -0.920504853452440150f, -0.913545457642600760f,
+ -0.906307787036649940f, -0.898794046299167040f, -0.891006524188367790f,
+ -0.882947592858926770f, -0.874619707139395740f, -0.866025403784438710f,
+ -0.857167300702112220f, -0.848048096156425960f,
+ -0.838670567945424160f, -0.829037572555041620f, -0.819152044288991580f,
+ -0.809016994374947340f, -0.798635510047292940f, -0.788010753606721900f,
+ -0.777145961456970680f, -0.766044443118977900f,
+ -0.754709580222772010f, -0.743144825477394130f, -0.731353701619170460f,
+ -0.719339800338651300f, -0.707106781186547460f, -0.694658370458997030f,
+ -0.681998360062498370f, -0.669130606358858240f,
+ -0.656059028990507500f, -0.642787609686539360f, -0.629320391049837280f,
+ -0.615661475325658290f, -0.601815023152048380f, -0.587785252292473030f,
+ -0.573576436351045830f, -0.559192903470746680f,
+ -0.544639035015027080f, -0.529919264233204790f, -0.515038074910054270f,
+ -0.499999999999999780f, -0.484809620246337000f, -0.469471562785890530f,
+ -0.453990499739546750f, -0.438371146789077510f,
+ -0.422618261740699330f, -0.406736643075800100f, -0.390731128489273600f,
+ -0.374606593415912070f, -0.358367949545300270f, -0.342020143325668710f,
+ -0.325568154457156420f, -0.309016994374947340f,
+ -0.292371704722736660f, -0.275637355816999050f, -0.258819045102520850f,
+ -0.241921895599667790f, -0.224951054343864810f, -0.207911690817759120f,
+ -0.190808995376544800f, -0.173648177666930300f,
+ -0.156434465040231040f, -0.139173100960065350f, -0.121869343405147370f,
+ -0.104528463267653330f, -0.087155742747658235f, -0.069756473744125330f,
+ -0.052335956242943620f, -0.034899496702500733f,
+ -0.017452406437283477f, 0.000000000000000061f, 0.017452406437283376f,
+ 0.034899496702501080f, 0.052335956242943966f, 0.069756473744125455f,
+ 0.087155742747658138f, 0.104528463267653460f,
+ 0.121869343405147490f, 0.139173100960065690f, 0.156434465040230920f,
+ 0.173648177666930410f, 0.190808995376544920f, 0.207911690817759450f,
+ 0.224951054343864920f, 0.241921895599667900f,
+ 0.258819045102520740f, 0.275637355816999160f, 0.292371704722736770f,
+ 0.309016994374947450f, 0.325568154457156760f, 0.342020143325668820f,
+ 0.358367949545300380f, 0.374606593415911960f,
+ 0.390731128489273940f, 0.406736643075800210f, 0.422618261740699440f,
+ 0.438371146789077460f, 0.453990499739546860f, 0.469471562785890860f,
+ 0.484809620246337110f, 0.500000000000000110f,
+ 0.515038074910054380f, 0.529919264233204900f, 0.544639035015027200f,
+ 0.559192903470746790f, 0.573576436351046050f, 0.587785252292473140f,
+ 0.601815023152048270f, 0.615661475325658290f,
+ 0.629320391049837500f, 0.642787609686539360f, 0.656059028990507280f,
+ 0.669130606358858240f, 0.681998360062498480f, 0.694658370458997370f,
+ 0.707106781186547570f, 0.719339800338651190f,
+ 0.731353701619170570f, 0.743144825477394240f, 0.754709580222772010f,
+ 0.766044443118978010f, 0.777145961456970900f, 0.788010753606722010f,
+ 0.798635510047292830f, 0.809016994374947450f,
+ 0.819152044288991800f, 0.829037572555041620f, 0.838670567945424050f,
+ 0.848048096156425960f, 0.857167300702112330f, 0.866025403784438710f,
+ 0.874619707139395740f, 0.882947592858926990f,
+ 0.891006524188367900f, 0.898794046299167040f, 0.906307787036649940f,
+ 0.913545457642600870f, 0.920504853452440370f, 0.927183854566787420f,
+ 0.933580426497201740f, 0.939692620785908430f,
+ 0.945518575599316850f, 0.951056516295153530f, 0.956304755963035440f,
+ 0.961261695938318890f, 0.965925826289068310f, 0.970295726275996470f,
+ 0.974370064785235250f, 0.978147600733805690f,
+ 0.981627183447663980f, 0.984807753012208020f, 0.987688340595137770f,
+ 0.990268068741570360f, 0.992546151641321980f, 0.994521895368273290f,
+ 0.996194698091745550f, 0.997564050259824200f,
+ 0.998629534754573830f, 0.999390827019095760f, 0.999847695156391270f,
+ 1.000000000000000000f, 0.999847695156391270f, 0.999390827019095760f,
+ 0.998629534754573830f, 0.997564050259824200f,
+ 0.996194698091745550f, 0.994521895368273290f, 0.992546151641321980f,
+ 0.990268068741570360f, 0.987688340595137770f, 0.984807753012208020f,
+ 0.981627183447663980f, 0.978147600733805690f,
+ 0.974370064785235250f, 0.970295726275996470f, 0.965925826289068310f,
+ 0.961261695938318890f, 0.956304755963035440f, 0.951056516295153530f,
+ 0.945518575599316850f, 0.939692620785908430f,
+ 0.933580426497201740f, 0.927183854566787420f, 0.920504853452440370f,
+ 0.913545457642600870f, 0.906307787036649940f, 0.898794046299167040f,
+ 0.891006524188367900f, 0.882947592858926990f,
+ 0.874619707139395740f, 0.866025403784438710f, 0.857167300702112330f,
+ 0.848048096156425960f, 0.838670567945424050f, 0.829037572555041620f,
+ 0.819152044288991800f, 0.809016994374947450f,
+ 0.798635510047292830f, 0.788010753606722010f, 0.777145961456970900f,
+ 0.766044443118978010f, 0.754709580222772010f, 0.743144825477394240f,
+ 0.731353701619170570f, 0.719339800338651190f,
+ 0.707106781186547570f, 0.694658370458997370f, 0.681998360062498480f,
+ 0.669130606358858240f, 0.656059028990507280f, 0.642787609686539360f,
+ 0.629320391049837500f, 0.615661475325658290f,
+ 0.601815023152048270f, 0.587785252292473140f, 0.573576436351046050f,
+ 0.559192903470746790f, 0.544639035015027200f, 0.529919264233204900f,
+ 0.515038074910054380f, 0.500000000000000110f,
+ 0.484809620246337110f, 0.469471562785890860f, 0.453990499739546860f,
+ 0.438371146789077460f, 0.422618261740699440f, 0.406736643075800210f,
+ 0.390731128489273940f, 0.374606593415911960f,
+ 0.358367949545300380f, 0.342020143325668820f, 0.325568154457156760f,
+ 0.309016994374947450f, 0.292371704722736770f, 0.275637355816999160f,
+ 0.258819045102520740f, 0.241921895599667900f,
+ 0.224951054343864920f, 0.207911690817759450f, 0.190808995376544920f,
+ 0.173648177666930410f, 0.156434465040230920f, 0.139173100960065690f,
+ 0.121869343405147490f, 0.104528463267653460f,
+ 0.087155742747658138f, 0.069756473744125455f, 0.052335956242943966f,
+ 0.034899496702501080f, 0.017452406437283376f, 0.000000000000000061f,
+ -0.017452406437283477f, -0.034899496702500733f,
+ -0.052335956242943620f, -0.069756473744125330f, -0.087155742747658235f,
+ -0.104528463267653330f, -0.121869343405147370f, -0.139173100960065350f,
+ -0.156434465040231040f, -0.173648177666930300f,
+ -0.190808995376544800f, -0.207911690817759120f, -0.224951054343864810f,
+ -0.241921895599667790f, -0.258819045102520850f, -0.275637355816999050f,
+ -0.292371704722736660f, -0.309016994374947340f,
+ -0.325568154457156420f, -0.342020143325668710f, -0.358367949545300270f,
+ -0.374606593415912070f, -0.390731128489273600f, -0.406736643075800100f,
+ -0.422618261740699330f, -0.438371146789077510f,
+ -0.453990499739546750f, -0.469471562785890530f, -0.484809620246337000f,
+ -0.499999999999999780f, -0.515038074910054270f, -0.529919264233204790f,
+ -0.544639035015027080f, -0.559192903470746680f,
+ -0.573576436351045830f, -0.587785252292473030f, -0.601815023152048380f,
+ -0.615661475325658290f, -0.629320391049837280f, -0.642787609686539360f,
+ -0.656059028990507500f, -0.669130606358858240f,
+ -0.681998360062498370f, -0.694658370458997030f, -0.707106781186547460f,
+ -0.719339800338651300f, -0.731353701619170460f, -0.743144825477394130f,
+ -0.754709580222772010f, -0.766044443118977900f,
+ -0.777145961456970680f, -0.788010753606721900f, -0.798635510047292940f,
+ -0.809016994374947340f, -0.819152044288991580f, -0.829037572555041620f,
+ -0.838670567945424160f, -0.848048096156425960f,
+ -0.857167300702112220f, -0.866025403784438710f, -0.874619707139395740f,
+ -0.882947592858926770f, -0.891006524188367790f, -0.898794046299167040f,
+ -0.906307787036649940f, -0.913545457642600760f,
+ -0.920504853452440150f, -0.927183854566787310f, -0.933580426497201740f,
+ -0.939692620785908320f, -0.945518575599316740f, -0.951056516295153530f,
+ -0.956304755963035440f, -0.961261695938318670f,
+ -0.965925826289068200f, -0.970295726275996470f, -0.974370064785235250f,
+ -0.978147600733805690f, -0.981627183447663980f, -0.984807753012208020f,
+ -0.987688340595137660f, -0.990268068741570250f,
+ -0.992546151641321980f, -0.994521895368273290f, -0.996194698091745550f,
+ -0.997564050259824200f, -0.998629534754573830f, -0.999390827019095760f,
+ -0.999847695156391270f, -1.000000000000000000f
+};
+
+/**
+* \par
+* Sine Table is generated from following loop
+* <pre>for(i = 0; i < 360; i++)
+* {
+* sinTable[i]= sin((i-180) * PI/180.0);
+* } </pre>
+*/
+
+
+static const float32_t sinTable[360] = {
+ -0.017452406437283439f, -0.034899496702500699f, -0.052335956242943807f,
+ -0.069756473744125524f, -0.087155742747658638f, -0.104528463267653730f,
+ -0.121869343405147550f, -0.139173100960065740f,
+ -0.156434465040230980f, -0.173648177666930280f, -0.190808995376544970f,
+ -0.207911690817759310f, -0.224951054343864780f, -0.241921895599667730f,
+ -0.258819045102521020f, -0.275637355816999660f,
+ -0.292371704722737050f, -0.309016994374947510f, -0.325568154457156980f,
+ -0.342020143325668880f, -0.358367949545300210f, -0.374606593415912240f,
+ -0.390731128489274160f, -0.406736643075800430f,
+ -0.422618261740699500f, -0.438371146789077290f, -0.453990499739546860f,
+ -0.469471562785891080f, -0.484809620246337170f, -0.499999999999999940f,
+ -0.515038074910054380f, -0.529919264233204900f,
+ -0.544639035015026860f, -0.559192903470746900f, -0.573576436351046380f,
+ -0.587785252292473250f, -0.601815023152048160f, -0.615661475325658400f,
+ -0.629320391049837720f, -0.642787609686539470f,
+ -0.656059028990507280f, -0.669130606358858350f, -0.681998360062498590f,
+ -0.694658370458997140f, -0.707106781186547570f, -0.719339800338651410f,
+ -0.731353701619170570f, -0.743144825477394240f,
+ -0.754709580222771790f, -0.766044443118978010f, -0.777145961456971010f,
+ -0.788010753606722010f, -0.798635510047292720f, -0.809016994374947450f,
+ -0.819152044288992020f, -0.829037572555041740f,
+ -0.838670567945424050f, -0.848048096156426070f, -0.857167300702112330f,
+ -0.866025403784438710f, -0.874619707139395850f, -0.882947592858927100f,
+ -0.891006524188367900f, -0.898794046299166930f,
+ -0.906307787036650050f, -0.913545457642600980f, -0.920504853452440370f,
+ -0.927183854566787420f, -0.933580426497201740f, -0.939692620785908430f,
+ -0.945518575599316850f, -0.951056516295153640f,
+ -0.956304755963035550f, -0.961261695938318890f, -0.965925826289068310f,
+ -0.970295726275996470f, -0.974370064785235250f, -0.978147600733805690f,
+ -0.981627183447663980f, -0.984807753012208020f,
+ -0.987688340595137660f, -0.990268068741570360f, -0.992546151641322090f,
+ -0.994521895368273400f, -0.996194698091745550f, -0.997564050259824200f,
+ -0.998629534754573830f, -0.999390827019095760f,
+ -0.999847695156391270f, -1.000000000000000000f, -0.999847695156391270f,
+ -0.999390827019095760f, -0.998629534754573830f, -0.997564050259824200f,
+ -0.996194698091745550f, -0.994521895368273290f,
+ -0.992546151641321980f, -0.990268068741570250f, -0.987688340595137770f,
+ -0.984807753012208020f, -0.981627183447663980f, -0.978147600733805580f,
+ -0.974370064785235250f, -0.970295726275996470f,
+ -0.965925826289068310f, -0.961261695938318890f, -0.956304755963035440f,
+ -0.951056516295153530f, -0.945518575599316740f, -0.939692620785908320f,
+ -0.933580426497201740f, -0.927183854566787420f,
+ -0.920504853452440260f, -0.913545457642600870f, -0.906307787036649940f,
+ -0.898794046299167040f, -0.891006524188367790f, -0.882947592858926880f,
+ -0.874619707139395740f, -0.866025403784438600f,
+ -0.857167300702112220f, -0.848048096156426070f, -0.838670567945423940f,
+ -0.829037572555041740f, -0.819152044288991800f, -0.809016994374947450f,
+ -0.798635510047292830f, -0.788010753606722010f,
+ -0.777145961456970790f, -0.766044443118978010f, -0.754709580222772010f,
+ -0.743144825477394240f, -0.731353701619170460f, -0.719339800338651080f,
+ -0.707106781186547460f, -0.694658370458997250f,
+ -0.681998360062498480f, -0.669130606358858240f, -0.656059028990507160f,
+ -0.642787609686539250f, -0.629320391049837390f, -0.615661475325658180f,
+ -0.601815023152048270f, -0.587785252292473140f,
+ -0.573576436351046050f, -0.559192903470746900f, -0.544639035015027080f,
+ -0.529919264233204900f, -0.515038074910054160f, -0.499999999999999940f,
+ -0.484809620246337060f, -0.469471562785890810f,
+ -0.453990499739546750f, -0.438371146789077400f, -0.422618261740699440f,
+ -0.406736643075800150f, -0.390731128489273720f, -0.374606593415912010f,
+ -0.358367949545300270f, -0.342020143325668710f,
+ -0.325568154457156640f, -0.309016994374947400f, -0.292371704722736770f,
+ -0.275637355816999160f, -0.258819045102520740f, -0.241921895599667730f,
+ -0.224951054343865000f, -0.207911690817759310f,
+ -0.190808995376544800f, -0.173648177666930330f, -0.156434465040230870f,
+ -0.139173100960065440f, -0.121869343405147480f, -0.104528463267653460f,
+ -0.087155742747658166f, -0.069756473744125302f,
+ -0.052335956242943828f, -0.034899496702500969f, -0.017452406437283512f,
+ 0.000000000000000000f, 0.017452406437283512f, 0.034899496702500969f,
+ 0.052335956242943828f, 0.069756473744125302f,
+ 0.087155742747658166f, 0.104528463267653460f, 0.121869343405147480f,
+ 0.139173100960065440f, 0.156434465040230870f, 0.173648177666930330f,
+ 0.190808995376544800f, 0.207911690817759310f,
+ 0.224951054343865000f, 0.241921895599667730f, 0.258819045102520740f,
+ 0.275637355816999160f, 0.292371704722736770f, 0.309016994374947400f,
+ 0.325568154457156640f, 0.342020143325668710f,
+ 0.358367949545300270f, 0.374606593415912010f, 0.390731128489273720f,
+ 0.406736643075800150f, 0.422618261740699440f, 0.438371146789077400f,
+ 0.453990499739546750f, 0.469471562785890810f,
+ 0.484809620246337060f, 0.499999999999999940f, 0.515038074910054160f,
+ 0.529919264233204900f, 0.544639035015027080f, 0.559192903470746900f,
+ 0.573576436351046050f, 0.587785252292473140f,
+ 0.601815023152048270f, 0.615661475325658180f, 0.629320391049837390f,
+ 0.642787609686539250f, 0.656059028990507160f, 0.669130606358858240f,
+ 0.681998360062498480f, 0.694658370458997250f,
+ 0.707106781186547460f, 0.719339800338651080f, 0.731353701619170460f,
+ 0.743144825477394240f, 0.754709580222772010f, 0.766044443118978010f,
+ 0.777145961456970790f, 0.788010753606722010f,
+ 0.798635510047292830f, 0.809016994374947450f, 0.819152044288991800f,
+ 0.829037572555041740f, 0.838670567945423940f, 0.848048096156426070f,
+ 0.857167300702112220f, 0.866025403784438600f,
+ 0.874619707139395740f, 0.882947592858926880f, 0.891006524188367790f,
+ 0.898794046299167040f, 0.906307787036649940f, 0.913545457642600870f,
+ 0.920504853452440260f, 0.927183854566787420f,
+ 0.933580426497201740f, 0.939692620785908320f, 0.945518575599316740f,
+ 0.951056516295153530f, 0.956304755963035440f, 0.961261695938318890f,
+ 0.965925826289068310f, 0.970295726275996470f,
+ 0.974370064785235250f, 0.978147600733805580f, 0.981627183447663980f,
+ 0.984807753012208020f, 0.987688340595137770f, 0.990268068741570250f,
+ 0.992546151641321980f, 0.994521895368273290f,
+ 0.996194698091745550f, 0.997564050259824200f, 0.998629534754573830f,
+ 0.999390827019095760f, 0.999847695156391270f, 1.000000000000000000f,
+ 0.999847695156391270f, 0.999390827019095760f,
+ 0.998629534754573830f, 0.997564050259824200f, 0.996194698091745550f,
+ 0.994521895368273400f, 0.992546151641322090f, 0.990268068741570360f,
+ 0.987688340595137660f, 0.984807753012208020f,
+ 0.981627183447663980f, 0.978147600733805690f, 0.974370064785235250f,
+ 0.970295726275996470f, 0.965925826289068310f, 0.961261695938318890f,
+ 0.956304755963035550f, 0.951056516295153640f,
+ 0.945518575599316850f, 0.939692620785908430f, 0.933580426497201740f,
+ 0.927183854566787420f, 0.920504853452440370f, 0.913545457642600980f,
+ 0.906307787036650050f, 0.898794046299166930f,
+ 0.891006524188367900f, 0.882947592858927100f, 0.874619707139395850f,
+ 0.866025403784438710f, 0.857167300702112330f, 0.848048096156426070f,
+ 0.838670567945424050f, 0.829037572555041740f,
+ 0.819152044288992020f, 0.809016994374947450f, 0.798635510047292720f,
+ 0.788010753606722010f, 0.777145961456971010f, 0.766044443118978010f,
+ 0.754709580222771790f, 0.743144825477394240f,
+ 0.731353701619170570f, 0.719339800338651410f, 0.707106781186547570f,
+ 0.694658370458997140f, 0.681998360062498590f, 0.669130606358858350f,
+ 0.656059028990507280f, 0.642787609686539470f,
+ 0.629320391049837720f, 0.615661475325658400f, 0.601815023152048160f,
+ 0.587785252292473250f, 0.573576436351046380f, 0.559192903470746900f,
+ 0.544639035015026860f, 0.529919264233204900f,
+ 0.515038074910054380f, 0.499999999999999940f, 0.484809620246337170f,
+ 0.469471562785891080f, 0.453990499739546860f, 0.438371146789077290f,
+ 0.422618261740699500f, 0.406736643075800430f,
+ 0.390731128489274160f, 0.374606593415912240f, 0.358367949545300210f,
+ 0.342020143325668880f, 0.325568154457156980f, 0.309016994374947510f,
+ 0.292371704722737050f, 0.275637355816999660f,
+ 0.258819045102521020f, 0.241921895599667730f, 0.224951054343864780f,
+ 0.207911690817759310f, 0.190808995376544970f, 0.173648177666930280f,
+ 0.156434465040230980f, 0.139173100960065740f,
+ 0.121869343405147550f, 0.104528463267653730f, 0.087155742747658638f,
+ 0.069756473744125524f, 0.052335956242943807f, 0.034899496702500699f,
+ 0.017452406437283439f, 0.000000000000000122f
+};
+
+
+/**
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+
+void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCosVal)
+{
+ int32_t i; /* Index for reading nearwst output values */
+ float32_t x1 = -179.0f; /* Initial input value */
+ float32_t y0, y1; /* nearest output values */
+ float32_t y2, y3;
+ float32_t fract; /* fractional part of input */
+
+ /* Calculation of fractional part */
+ if(theta > 0.0f)
+ {
+ fract = theta - (float32_t) ((int32_t) theta);
+ }
+ else
+ {
+ fract = (theta - (float32_t) ((int32_t) theta)) + 1.0f;
+ }
+
+ /* index calculation for reading nearest output values */
+ i = (uint32_t) (theta - x1);
+
+ /* Checking min and max index of table */
+ if(i < 0)
+ {
+ i = 0;
+ }
+ else if(i >= 359)
+ {
+ i = 358;
+ }
+
+ /* reading nearest sine output values */
+ y0 = sinTable[i];
+ y1 = sinTable[i + 1u];
+
+ /* reading nearest cosine output values */
+ y2 = cosTable[i];
+ y3 = cosTable[i + 1u];
+
+ y1 = y1 - y0;
+ y3 = y3 - y2;
+
+ y1 = fract * y1;
+ y3 = fract * y3;
+
+ /* Calculation of sine value */
+ *pSinVal = y0 + y1;
+
+ /* Calculation of cosine value */
+ *pCosVal = y2 + y3;
+
+}
+
+/**
+ * @} end of SinCos group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_sin_cos_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_sin_cos_q31.c
new file mode 100644
index 000000000..370b7b6ef
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/ControllerFunctions/arm_sin_cos_q31.c
@@ -0,0 +1,328 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_cos_q31.c
+*
+* Description: Cosine & Sine calculation for Q31 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupController
+ */
+
+ /**
+ * @addtogroup SinCos
+ * @{
+ */
+
+/**
+* \par
+* Sine Table is generated from following loop
+* <pre>for(i = 0; i < 360; i++)
+* {
+* sinTable[i]= sin((i-180) * PI/180.0);
+* } </pre>
+* Convert above coefficients to fixed point 1.31 format.
+*/
+
+static const int32_t sinTableQ31[360] = {
+
+ 0x0, 0xfdc41e9b, 0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2,
+ 0xf06695da,
+ 0xee2f9369, 0xebf9f498, 0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9,
+ 0xe108b40d, 0xdedf047d,
+ 0xdcb7ea46, 0xda939061, 0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0,
+ 0xd00ce422, 0xcdfc85bb,
+ 0xcbf00dbe, 0xc9e7a512, 0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224,
+ 0xc0000000, 0xbe133b7c,
+ 0xbc2b9b05, 0xba4944a2, 0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af,
+ 0xb1320139, 0xaf726def,
+ 0xadb922b7, 0xac0641fb, 0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666,
+ 0xa3ecac65, 0xa263007d,
+ 0xa0e0a15f, 0x9f65ad2d, 0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5,
+ 0x98722192, 0x9726069c,
+ 0x95e218c9, 0x94a6715d, 0x937328f5, 0x92485786, 0x9126145f, 0x900c7621,
+ 0x8efb92c2, 0x8df37f8b,
+ 0x8cf45113, 0x8bfe1b3f, 0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4,
+ 0x87b826f7, 0x86f93f50,
+ 0x8643c7b3, 0x8597ce46, 0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b,
+ 0x82cc0f36, 0x825a0a5b,
+ 0x81f1d1ce, 0x81936daf, 0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130,
+ 0x804fd23a, 0x802ce84c,
+ 0x8013f61d, 0x8004fda0, 0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c,
+ 0x804fd23a, 0x807cb130,
+ 0x80b381ac, 0x80f43f69, 0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b,
+ 0x82cc0f36, 0x8347d77b,
+ 0x83cd5982, 0x845c8ae3, 0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50,
+ 0x87b826f7, 0x88806fc4,
+ 0x89520a1a, 0x8a2ce59f, 0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b,
+ 0x8efb92c2, 0x900c7621,
+ 0x9126145f, 0x92485786, 0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c,
+ 0x98722192, 0x99c64fc5,
+ 0x9b2276b0, 0x9c867b2c, 0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d,
+ 0xa3ecac65, 0xa57d8666,
+ 0xa7156f3c, 0xa8b4471a, 0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def,
+ 0xb1320139, 0xb2f7b9af,
+ 0xb4c373ee, 0xb6950c1e, 0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c,
+ 0xc0000000, 0xc1f1c224,
+ 0xc3e85b18, 0xc5e3a3a9, 0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb,
+ 0xd00ce422, 0xd220ffc0,
+ 0xd438af17, 0xd653c860, 0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d,
+ 0xe108b40d, 0xe334cdc9,
+ 0xe5632654, 0xe7939223, 0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da,
+ 0xf29ecfb2, 0xf4d814a4,
+ 0xf7123849, 0xf94d0e2e, 0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632,
+ 0x6b2f1d2,
+ 0x8edc7b7, 0xb27eb5c, 0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68,
+ 0x163a1a7e, 0x186c6ddd,
+ 0x1a9cd9ac, 0x1ccb3237, 0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f,
+ 0x278dde6e, 0x29ac37a0,
+ 0x2bc750e9, 0x2ddf0040, 0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee,
+ 0x381c8bb5, 0x3a1c5c57,
+ 0x3c17a4e8, 0x3e0e3ddc, 0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e,
+ 0x4793a210, 0x496af3e2,
+ 0x4b3c8c12, 0x4d084651, 0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05,
+ 0x55a6125c, 0x574bb8e6,
+ 0x58ea90c4, 0x5a82799a, 0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3,
+ 0x620dbe8b, 0x637984d4,
+ 0x64dd8950, 0x6639b03b, 0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3,
+ 0x6c8cd70b, 0x6db7a87a,
+ 0x6ed9eba1, 0x6ff389df, 0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1,
+ 0x74ef0ebc, 0x75d31a61,
+ 0x76adf5e6, 0x777f903c, 0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba,
+ 0x7b0a9f8d, 0x7ba3751d,
+ 0x7c32a67e, 0x7cb82885, 0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251,
+ 0x7ec11aa5, 0x7f0bc097,
+ 0x7f4c7e54, 0x7f834ed0, 0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260,
+ 0x7fffffff, 0x7ffb0260,
+ 0x7fec09e3, 0x7fd317b4, 0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097,
+ 0x7ec11aa5, 0x7e6c9251,
+ 0x7e0e2e32, 0x7da5f5a5, 0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d,
+ 0x7b0a9f8d, 0x7a6831ba,
+ 0x79bc384d, 0x7906c0b0, 0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61,
+ 0x74ef0ebc, 0x7401e4c1,
+ 0x730baeed, 0x720c8075, 0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a,
+ 0x6c8cd70b, 0x6b598ea3,
+ 0x6a1de737, 0x68d9f964, 0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4,
+ 0x620dbe8b, 0x609a52d3,
+ 0x5f1f5ea1, 0x5d9cff83, 0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6,
+ 0x55a6125c, 0x53f9be05,
+ 0x5246dd49, 0x508d9211, 0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2,
+ 0x4793a210, 0x45b6bb5e,
+ 0x43d464fb, 0x41ecc484, 0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57,
+ 0x381c8bb5, 0x36185aee,
+ 0x340ff242, 0x32037a45, 0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0,
+ 0x278dde6e, 0x256c6f9f,
+ 0x234815ba, 0x2120fb83, 0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd,
+ 0x163a1a7e, 0x14060b68,
+ 0x11d06c97, 0xf996a26, 0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2,
+ 0x4779632, 0x23be165,
+
+
+};
+
+/**
+* \par
+* Cosine Table is generated from following loop
+* <pre>for(i = 0; i < 360; i++)
+* {
+* cosTable[i]= cos((i-180) * PI/180.0);
+* } </pre>
+* \par
+* Convert above coefficients to fixed point 1.31 format.
+*/
+static const int32_t cosTableQ31[360] = {
+ 0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c, 0x804fd23a, 0x807cb130,
+ 0x80b381ac, 0x80f43f69,
+ 0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b, 0x82cc0f36, 0x8347d77b,
+ 0x83cd5982, 0x845c8ae3,
+ 0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50, 0x87b826f7, 0x88806fc4,
+ 0x89520a1a, 0x8a2ce59f,
+ 0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b, 0x8efb92c2, 0x900c7621,
+ 0x9126145f, 0x92485786,
+ 0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c, 0x98722192, 0x99c64fc5,
+ 0x9b2276b0, 0x9c867b2c,
+ 0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d, 0xa3ecac65, 0xa57d8666,
+ 0xa7156f3c, 0xa8b4471a,
+ 0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def, 0xb1320139, 0xb2f7b9af,
+ 0xb4c373ee, 0xb6950c1e,
+ 0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c, 0xc0000000, 0xc1f1c224,
+ 0xc3e85b18, 0xc5e3a3a9,
+ 0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb, 0xd00ce422, 0xd220ffc0,
+ 0xd438af17, 0xd653c860,
+ 0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d, 0xe108b40d, 0xe334cdc9,
+ 0xe5632654, 0xe7939223,
+ 0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da, 0xf29ecfb2, 0xf4d814a4,
+ 0xf7123849, 0xf94d0e2e,
+ 0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632, 0x6b2f1d2, 0x8edc7b7,
+ 0xb27eb5c,
+ 0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68, 0x163a1a7e, 0x186c6ddd,
+ 0x1a9cd9ac, 0x1ccb3237,
+ 0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f, 0x278dde6e, 0x29ac37a0,
+ 0x2bc750e9, 0x2ddf0040,
+ 0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee, 0x381c8bb5, 0x3a1c5c57,
+ 0x3c17a4e8, 0x3e0e3ddc,
+ 0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e, 0x4793a210, 0x496af3e2,
+ 0x4b3c8c12, 0x4d084651,
+ 0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05, 0x55a6125c, 0x574bb8e6,
+ 0x58ea90c4, 0x5a82799a,
+ 0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3, 0x620dbe8b, 0x637984d4,
+ 0x64dd8950, 0x6639b03b,
+ 0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3, 0x6c8cd70b, 0x6db7a87a,
+ 0x6ed9eba1, 0x6ff389df,
+ 0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1, 0x74ef0ebc, 0x75d31a61,
+ 0x76adf5e6, 0x777f903c,
+ 0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba, 0x7b0a9f8d, 0x7ba3751d,
+ 0x7c32a67e, 0x7cb82885,
+ 0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251, 0x7ec11aa5, 0x7f0bc097,
+ 0x7f4c7e54, 0x7f834ed0,
+ 0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260, 0x7fffffff, 0x7ffb0260,
+ 0x7fec09e3, 0x7fd317b4,
+ 0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097, 0x7ec11aa5, 0x7e6c9251,
+ 0x7e0e2e32, 0x7da5f5a5,
+ 0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d, 0x7b0a9f8d, 0x7a6831ba,
+ 0x79bc384d, 0x7906c0b0,
+ 0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61, 0x74ef0ebc, 0x7401e4c1,
+ 0x730baeed, 0x720c8075,
+ 0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a, 0x6c8cd70b, 0x6b598ea3,
+ 0x6a1de737, 0x68d9f964,
+ 0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4, 0x620dbe8b, 0x609a52d3,
+ 0x5f1f5ea1, 0x5d9cff83,
+ 0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6, 0x55a6125c, 0x53f9be05,
+ 0x5246dd49, 0x508d9211,
+ 0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2, 0x4793a210, 0x45b6bb5e,
+ 0x43d464fb, 0x41ecc484,
+ 0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57, 0x381c8bb5, 0x36185aee,
+ 0x340ff242, 0x32037a45,
+ 0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0, 0x278dde6e, 0x256c6f9f,
+ 0x234815ba, 0x2120fb83,
+ 0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd, 0x163a1a7e, 0x14060b68,
+ 0x11d06c97, 0xf996a26,
+ 0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2, 0x4779632, 0x23be165, 0x0,
+ 0xfdc41e9b,
+ 0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2, 0xf06695da,
+ 0xee2f9369, 0xebf9f498,
+ 0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9, 0xe108b40d, 0xdedf047d,
+ 0xdcb7ea46, 0xda939061,
+ 0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0, 0xd00ce422, 0xcdfc85bb,
+ 0xcbf00dbe, 0xc9e7a512,
+ 0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224, 0xc0000000, 0xbe133b7c,
+ 0xbc2b9b05, 0xba4944a2,
+ 0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af, 0xb1320139, 0xaf726def,
+ 0xadb922b7, 0xac0641fb,
+ 0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666, 0xa3ecac65, 0xa263007d,
+ 0xa0e0a15f, 0x9f65ad2d,
+ 0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5, 0x98722192, 0x9726069c,
+ 0x95e218c9, 0x94a6715d,
+ 0x937328f5, 0x92485786, 0x9126145f, 0x900c7621, 0x8efb92c2, 0x8df37f8b,
+ 0x8cf45113, 0x8bfe1b3f,
+ 0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4, 0x87b826f7, 0x86f93f50,
+ 0x8643c7b3, 0x8597ce46,
+ 0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b, 0x82cc0f36, 0x825a0a5b,
+ 0x81f1d1ce, 0x81936daf,
+ 0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130, 0x804fd23a, 0x802ce84c,
+ 0x8013f61d, 0x8004fda0,
+
+};
+
+
+/**
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ *
+ * The Q31 input value is in the range [-1 0.999999] and is mapped to a degree value in the range [-180 179].
+ *
+ */
+
+
+void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal)
+{
+ q31_t x0; /* Nearest input value */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t xSpacing = INPUT_SPACING; /* Spaing between inputs */
+ uint32_t i; /* Index */
+ q31_t oneByXSpacing; /* 1/ xSpacing value */
+ q31_t out; /* temporary variable */
+ uint32_t sign_bits; /* No.of sign bits */
+ uint32_t firstX = 0x80000000; /* First X value */
+
+ /* Calculation of index */
+ i = ((uint32_t) theta - firstX) / (uint32_t) xSpacing;
+
+ /* Checking min and max index of table */
+ if(i >= 359)
+ {
+ i = 358;
+ }
+
+ /* Calculation of first nearest input value */
+ x0 = (q31_t) firstX + ((q31_t) i * xSpacing);
+
+ /* Reading nearest sine output values from table */
+ y0 = sinTableQ31[i];
+ y1 = sinTableQ31[i + 1u];
+
+ /* Calculation of 1/(x1-x0) */
+ /* (x1-x0) is xSpacing which is fixed value */
+ sign_bits = 8u;
+ oneByXSpacing = 0x5A000000;
+
+ /* Calculation of (theta - x0)/(x1-x0) */
+ out =
+ (((q31_t) (((q63_t) (theta - x0) * oneByXSpacing) >> 32)) << sign_bits);
+
+ /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
+ *pSinVal = __QADD(y0, ((q31_t) (((q63_t) (y1 - y0) * out) >> 30)));
+
+ /* Reading nearest cosine output values from table */
+ y0 = cosTableQ31[i];
+ y1 = cosTableQ31[i + 1u];
+
+ /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
+ *pCosVal = __QADD(y0, ((q31_t) (((q63_t) (y1 - y0) * out) >> 30)));
+
+}
+
+/**
+ * @} end of SinCos group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_f32.c
new file mode 100644
index 000000000..20a9f3657
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_f32.c
@@ -0,0 +1,290 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cos_f32.c
+*
+* Description: Fast cosine calculation for floating-point values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @defgroup cos Cosine
+ *
+ * Computes the trigonometric cosine function using a combination of table lookup
+ * and cubic interpolation. There are separate functions for
+ * Q15, Q31, and floating-point data types.
+ * The input to the floating-point version is in radians while the
+ * fixed-point Q15 and Q31 have a scaled input with the range
+ * [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
+ * value of 2*pi wraps around to 0.
+ *
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.
+ * The steps used are:
+ * -# Calculation of the nearest integer table index
+ * -# Fetch the four table values a, b, c, and d
+ * -# Compute the fractional portion (fract) of the table index.
+ * -# Calculation of wa, wb, wc, wd
+ * -# The final result equals <code>a*wa + b*wb + c*wc + d*wd</code>
+ *
+ * where
+ * <pre>
+ * a=Table[index-1];
+ * b=Table[index+0];
+ * c=Table[index+1];
+ * d=Table[index+2];
+ * </pre>
+ * and
+ * <pre>
+ * wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;
+ * wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;
+ * wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;
+ * wd=(1/6)*fract.^3 - (1/6)*fract;
+ * </pre>
+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+
+/**
+* \par
+* <b>Example code for Generation of Cos Table:</b>
+* <pre>
+* tableSize = 256;
+* for(n = -1; n < (tableSize + 2); n++)
+* {
+* cosTable[n+1]= cos(2*pi*n/tableSize);
+* } </pre>
+* where pi value is 3.14159265358979
+*/
+
+static const float32_t cosTable[260] = {
+ 0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+ 0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,
+ 0.992479562759399410f, 0.989176511764526370f,
+ 0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,
+ 0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,
+ 0.949528157711029050f, 0.941544055938720700f,
+ 0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,
+ 0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,
+ 0.870086967945098880f, 0.857728600502014160f,
+ 0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,
+ 0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,
+ 0.757208824157714840f, 0.740951120853424070f,
+ 0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,
+ 0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,
+ 0.615231573581695560f, 0.595699310302734380f,
+ 0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,
+ 0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,
+ 0.449611335992813110f, 0.427555084228515630f,
+ 0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,
+ 0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,
+ 0.266712754964828490f, 0.242980182170867920f,
+ 0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,
+ 0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,
+ 0.073564566671848297f, 0.049067676067352295f,
+ 0.024541229009628296f, 0.000000000000000061f, -0.024541229009628296f,
+ -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,
+ -0.122410677373409270f, -0.146730467677116390f,
+ -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,
+ -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,
+ -0.313681751489639280f, -0.336889863014221190f,
+ -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,
+ -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,
+ -0.492898195981979370f, -0.514102756977081300f,
+ -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,
+ -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,
+ -0.653172850608825680f, -0.671558976173400880f,
+ -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,
+ -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,
+ -0.788346409797668460f, -0.803207516670227050f,
+ -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,
+ -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,
+ -0.893224298954010010f, -0.903989315032958980f,
+ -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,
+ -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,
+ -0.963776051998138430f, -0.970031261444091800f,
+ -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,
+ -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,
+ -0.997290432453155520f, -0.998795449733734130f,
+ -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,
+ -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,
+ -0.992479562759399410f, -0.989176511764526370f,
+ -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,
+ -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,
+ -0.949528157711029050f, -0.941544055938720700f,
+ -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,
+ -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,
+ -0.870086967945098880f, -0.857728600502014160f,
+ -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,
+ -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,
+ -0.757208824157714840f, -0.740951120853424070f,
+ -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,
+ -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,
+ -0.615231573581695560f, -0.595699310302734380f,
+ -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,
+ -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,
+ -0.449611335992813110f, -0.427555084228515630f,
+ -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,
+ -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,
+ -0.266712754964828490f, -0.242980182170867920f,
+ -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,
+ -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,
+ -0.073564566671848297f, -0.049067676067352295f,
+ -0.024541229009628296f, -0.000000000000000184f, 0.024541229009628296f,
+ 0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,
+ 0.122410677373409270f, 0.146730467677116390f,
+ 0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,
+ 0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,
+ 0.313681751489639280f, 0.336889863014221190f,
+ 0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,
+ 0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,
+ 0.492898195981979370f, 0.514102756977081300f,
+ 0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,
+ 0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,
+ 0.653172850608825680f, 0.671558976173400880f,
+ 0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,
+ 0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,
+ 0.788346409797668460f, 0.803207516670227050f,
+ 0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,
+ 0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,
+ 0.893224298954010010f, 0.903989315032958980f,
+ 0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,
+ 0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,
+ 0.963776051998138430f, 0.970031261444091800f,
+ 0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,
+ 0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,
+ 0.997290432453155520f, 0.998795449733734130f,
+ 0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+ 0.998795449733734130f
+};
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+
+float32_t arm_cos_f32(
+ float32_t x)
+{
+ float32_t cosVal, fract, in;
+ int32_t index;
+ uint32_t tableSize = (uint32_t) TABLE_SIZE;
+ float32_t wa, wb, wc, wd;
+ float32_t a, b, c, d;
+ float32_t *tablePtr;
+ int32_t n;
+ float32_t fractsq, fractby2, fractby6, fractby3, fractsqby2;
+ float32_t oneminusfractby2;
+ float32_t frby2xfrsq, frby6xfrsq;
+
+ /* input x is in radians */
+ /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+ in = x * 0.159154943092f;
+
+ /* Calculation of floor value of input */
+ n = (int32_t) in;
+
+ /* Make negative values towards -infinity */
+ if(x < 0.0f)
+ {
+ n = n - 1;
+ }
+
+ /* Map input value to [0 1] */
+ in = in - (float32_t) n;
+
+ /* Calculation of index of the table */
+ index = (uint32_t) (tableSize * in);
+
+ /* fractional value calculation */
+ fract = ((float32_t) tableSize * in) - (float32_t) index;
+
+ /* Checking min and max index of table */
+ if(index < 0)
+ {
+ index = 0;
+ }
+ else if(index > 256)
+ {
+ index = 256;
+ }
+
+ /* Initialise table pointer */
+ tablePtr = (float32_t *) & cosTable[index];
+
+ /* Read four nearest values of input value from the cos table */
+ a = tablePtr[0];
+ b = tablePtr[1];
+ c = tablePtr[2];
+ d = tablePtr[3];
+
+ /* Cubic interpolation process */
+ fractsq = fract * fract;
+ fractby2 = fract * 0.5f;
+ fractby6 = fract * 0.166666667f;
+ fractby3 = fract * 0.3333333333333f;
+ fractsqby2 = fractsq * 0.5f;
+ frby2xfrsq = (fractby2) * fractsq;
+ frby6xfrsq = (fractby6) * fractsq;
+ oneminusfractby2 = 1.0f - fractby2;
+ wb = fractsqby2 - fractby3;
+ wc = (fractsqby2 + fract);
+ wa = wb - frby6xfrsq;
+ wb = frby2xfrsq - fractsq;
+ cosVal = wa * a;
+ wc = wc - frby2xfrsq;
+ wd = (frby6xfrsq) - fractby6;
+ wb = wb + oneminusfractby2;
+
+ /* Calculate cos value */
+ cosVal = (cosVal + (b * wb)) + ((c * wc) + (d * wd));
+
+ /* Return the output value */
+ return (cosVal);
+
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_q15.c
new file mode 100644
index 000000000..ffc0929f7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_q15.c
@@ -0,0 +1,214 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cos_q15.c
+*
+* Description: Fast cosine calculation for Q15 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+/**
+* \par
+ * Table values are in Q15 (1.15 fixed-point format) and generation is done in
+ * three steps. First, generate cos values in floating point:
+ * <pre>
+ * tableSize = 256;
+ * for(n = -1; n < (tableSize + 1); n++)
+ * {
+ * cosTable[n+1]= cos(2*pi*n/tableSize);
+ * } </pre>
+ * where pi value is 3.14159265358979
+ * \par
+ * Second, convert floating-point to Q15 (fixed-point):
+ * (cosTable[i] * pow(2, 15))
+ * \par
+ * Finally, round to the nearest integer value:
+ * cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);
+*/
+
+static const q15_t cosTableQ15[259] = {
+ 0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,
+ 0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,
+ 0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,
+ 0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,
+ 0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,
+ 0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,
+ 0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,
+ 0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,
+ 0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,
+ 0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,
+ 0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,
+ 0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,
+ 0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,
+ 0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,
+ 0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,
+ 0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,
+ 0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,
+ 0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,
+ 0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,
+ 0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,
+ 0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,
+ 0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,
+ 0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,
+ 0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,
+ 0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
+ 0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,
+ 0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,
+ 0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,
+ 0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,
+ 0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,
+ 0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,
+ 0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,
+ 0x7ff6, 0x7fff, 0x7ff6
+};
+
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ *
+ * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian
+ * value in the range [0 2*pi).
+ */
+
+q15_t arm_cos_q15(
+ q15_t x)
+{
+ q31_t cosVal; /* Temporary variable for output */
+ q15_t *tablePtr; /* Pointer to table */
+ q15_t in, in2; /* Temporary variables for input */
+ q31_t wa, wb, wc, wd; /* Cubic interpolation coefficients */
+ q15_t a, b, c, d; /* Four nearest output values */
+ q15_t fract, fractCube, fractSquare; /* Variables for fractional value */
+ q15_t oneBy6 = 0x1555; /* Fixed point value of 1/6 */
+ q15_t tableSpacing = TABLE_SPACING_Q15; /* Table spacing */
+ int32_t index; /* Index variable */
+
+ in = x;
+
+ /* Calculate the nearest index */
+ index = (int32_t) in / tableSpacing;
+
+ /* Calculate the nearest value of input */
+ in2 = (q15_t) index *tableSpacing;
+
+ /* Calculation of fractional value */
+ fract = (in - in2) << 8;
+
+ /* fractSquare = fract * fract */
+ fractSquare = (q15_t) ((fract * fract) >> 15);
+
+ /* fractCube = fract * fract * fract */
+ fractCube = (q15_t) ((fractSquare * fract) >> 15);
+
+ /* Checking min and max index of table */
+ if(index < 0)
+ {
+ index = 0;
+ }
+ else if(index > 256)
+ {
+ index = 256;
+ }
+
+ /* Initialise table pointer */
+ tablePtr = (q15_t *) & cosTableQ15[index];
+
+ /* Cubic interpolation process */
+ /* Calculation of wa */
+ /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */
+ wa = (q31_t) oneBy6 *fractCube;
+ wa += (q31_t) 0x2AAA *fract;
+ wa = -(wa >> 15);
+ wa += (fractSquare >> 1u);
+
+ /* Read first nearest value of output from the cos table */
+ a = *tablePtr++;
+
+ /* cosVal = a * wa */
+ cosVal = a * wa;
+
+ /* Calculation of wb */
+ wb = (((fractCube >> 1u) - fractSquare) - (fract >> 1u)) + 0x7FFF;
+
+ /* Read second nearest value of output from the cos table */
+ b = *tablePtr++;
+
+ /* cosVal += b*wb */
+ cosVal += b * wb;
+
+ /* Calculation of wc */
+ wc = -(q31_t) fractCube + fractSquare;
+ wc = (wc >> 1u) + fract;
+
+ /* Read third nearest value of output from the cos table */
+ c = *tablePtr++;
+
+ /* cosVal += c*wc */
+ cosVal += c * wc;
+
+ /* Calculation of wd */
+ /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+ fractCube = fractCube - fract;
+ wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));
+
+ /* Read fourth nearest value of output from the cos table */
+ d = *tablePtr++;
+
+ /* cosVal += d*wd; */
+ cosVal += d * wd;
+
+ /* Convert output value in 1.15(q15) format and saturate */
+ cosVal = __SSAT((cosVal >> 15), 16);
+
+ /* Return the output value in 1.15(q15) format */
+ return ((q15_t) cosVal);
+
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_q31.c
new file mode 100644
index 000000000..9ae4b5f80
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_q31.c
@@ -0,0 +1,249 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cos_q31.c
+*
+* Description: Fast cosine calculation for Q31 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup cos
+ * @{
+ */
+
+/**
+ * \par
+ * Table values are in Q31 (1.31 fixed-point format) and generation is done in
+ * three steps. First, generate cos values in floating point:
+ * <pre>
+ * tableSize = 256;
+ * for(n = -1; n < (tableSize + 1); n++)
+ * {
+ * cosTable[n+1]= cos(2*pi*n/tableSize);
+ * } </pre>
+ * where pi value is 3.14159265358979
+ * \par
+ * Second, convert floating-point to Q31 (Fixed point):
+ * (cosTable[i] * pow(2, 31))
+ * \par
+ * Finally, round to the nearest integer value:
+ * cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);
+ */
+
+
+static const q31_t cosTableQ31[259] = {
+ 0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,
+ 0x7f0991c4, 0x7e9d55fc,
+ 0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,
+ 0x798a23b1, 0x78848414,
+ 0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,
+ 0x6f5f02b2, 0x6dca0d14,
+ 0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,
+ 0x60ec3830, 0x5ed77c8a,
+ 0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,
+ 0x4ebfe8a5, 0x4c3fdff4,
+ 0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,
+ 0x398cdd32, 0x36ba2014,
+ 0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,
+ 0x2223a4c5, 0x1f19f97b,
+ 0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,
+ 0x96a9049, 0x647d97c,
+ 0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,
+ 0xed37ef91,
+ 0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,
+ 0xd7d946d8, 0xd4e0cb15,
+ 0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,
+ 0xc0e8b648, 0xbe31e19b,
+ 0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,
+ 0xac64d510, 0xaa0a5b2e,
+ 0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,
+ 0x9b1776da, 0x99307ee0,
+ 0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,
+ 0x8daad37b, 0x8c4a142f,
+ 0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,
+ 0x84a2fc62, 0x83d60412,
+ 0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,
+ 0x8058c94c, 0x80277872,
+ 0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,
+ 0x80f66e3c, 0x8162aa04,
+ 0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,
+ 0x8675dc4f, 0x877b7bec,
+ 0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,
+ 0x90a0fd4e, 0x9235f2ec,
+ 0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,
+ 0x9f13c7d0, 0xa1288376,
+ 0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,
+ 0xb140175b, 0xb3c0200c,
+ 0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,
+ 0xc67322ce, 0xc945dfec,
+ 0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,
+ 0xdddc5b3b, 0xe0e60685,
+ 0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,
+ 0xf6956fb7, 0xf9b82684,
+ 0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,
+ 0x12c8106f,
+ 0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,
+ 0x2826b928, 0x2b1f34eb,
+ 0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,
+ 0x3f1749b8, 0x41ce1e65,
+ 0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,
+ 0x539b2af0, 0x55f5a4d2,
+ 0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,
+ 0x64e88926, 0x66cf8120,
+ 0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,
+ 0x72552c85, 0x73b5ebd1,
+ 0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,
+ 0x7b5d039e, 0x7c29fbee,
+ 0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,
+ 0x7fa736b4, 0x7fd8878e,
+ 0x7ff62182, 0x7fffffff, 0x7ff62182
+};
+
+/**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ *
+ * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian
+ * value in the range [0 2*pi).
+ */
+
+q31_t arm_cos_q31(
+ q31_t x)
+{
+ q31_t cosVal, in, in2; /* Temporary variables for input, output */
+ q31_t wa, wb, wc, wd; /* Cubic interpolation coefficients */
+ q31_t a, b, c, d; /* Four nearest output values */
+ q31_t *tablePtr; /* Pointer to table */
+ q31_t fract, fractCube, fractSquare; /* Temporary values for fractional values */
+ q31_t oneBy6 = 0x15555555; /* Fixed point value of 1/6 */
+ q31_t tableSpacing = TABLE_SPACING_Q31; /* Table spacing */
+ q31_t temp; /* Temporary variable for intermediate process */
+ int32_t index; /* Index variable */
+
+ in = x;
+
+ /* Calculate the nearest index */
+ index = in / tableSpacing;
+
+ /* Calculate the nearest value of input */
+ in2 = ((q31_t) index) * tableSpacing;
+
+ /* Calculation of fractional value */
+ fract = (in - in2) << 8;
+
+ /* fractSquare = fract * fract */
+ fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));
+ fractSquare = fractSquare << 1;
+
+ /* fractCube = fract * fract * fract */
+ fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));
+ fractCube = fractCube << 1;
+
+ /* Checking min and max index of table */
+ if(index < 0)
+ {
+ index = 0;
+ }
+ else if(index > 256)
+ {
+ index = 256;
+ }
+
+ /* Initialise table pointer */
+ tablePtr = (q31_t *) & cosTableQ31[index];
+
+ /* Cubic interpolation process */
+ /* Calculation of wa */
+ /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */
+ wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+ temp = 0x2AAAAAAA;
+ wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);
+ wa = -(wa << 1u);
+ wa += (fractSquare >> 1u);
+
+ /* Read first nearest value of output from the cos table */
+ a = *tablePtr++;
+
+ /* cosVal = a*wa */
+ cosVal = ((q31_t) (((q63_t) a * wa) >> 32));
+
+ /* q31(1.31) Fixed point value of 1 */
+ temp = 0x7FFFFFFF;
+
+ /* Calculation of wb */
+ wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;
+ /* Read second nearest value of output from the cos table */
+ b = *tablePtr++;
+
+ /* cosVal += b*wb */
+ cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) b * (wb))) >> 32);
+
+ /* Calculation of wc */
+ wc = -fractCube + fractSquare;
+ wc = (wc >> 1u) + fract;
+ /* Read third nearest values of output value from the cos table */
+ c = *tablePtr++;
+
+ /* cosVal += c*wc */
+ cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) c * (wc))) >> 32);
+
+ /* Calculation of wd */
+ /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+ fractCube = fractCube - fract;
+ wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+ wd = (wd << 1u);
+
+ /* Read fourth nearest value of output from the cos table */
+ d = *tablePtr++;
+
+ /* cosVal += d*wd; */
+ cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) d * (wd))) >> 32);
+
+
+ /* convert cosVal in 2.30 format to 1.31 format */
+ return (__QADD(cosVal, cosVal));
+
+}
+
+/**
+ * @} end of cos group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_f32.c
new file mode 100644
index 000000000..038229f06
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_f32.c
@@ -0,0 +1,291 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_f32.c
+*
+* Description: Fast sine calculation for floating-point values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @defgroup sin Sine
+ *
+ * Computes the trigonometric sine function using a combination of table lookup
+ * and cubic interpolation. There are separate functions for
+ * Q15, Q31, and floating-point data types.
+ * The input to the floating-point version is in radians while the
+ * fixed-point Q15 and Q31 have a scaled input with the range
+ * [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
+ * value of 2*pi wraps around to 0.
+ *
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.
+ * The steps used are:
+ * -# Calculation of the nearest integer table index
+ * -# Fetch the four table values a, b, c, and d
+ * -# Compute the fractional portion (fract) of the table index.
+ * -# Calculation of wa, wb, wc, wd
+ * -# The final result equals <code>a*wa + b*wb + c*wc + d*wd</code>
+ *
+ * where
+ * <pre>
+ * a=Table[index-1];
+ * b=Table[index+0];
+ * c=Table[index+1];
+ * d=Table[index+2];
+ * </pre>
+ * and
+ * <pre>
+ * wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;
+ * wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;
+ * wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;
+ * wd=(1/6)*fract.^3 - (1/6)*fract;
+ * </pre>
+ */
+
+/**
+ * @addtogroup sin
+ * @{
+ */
+
+
+/**
+ * \par
+ * Example code for the generation of the floating-point sine table:
+ * <pre>
+ * tableSize = 256;
+ * for(n = -1; n < (tableSize + 1); n++)
+ * {
+ * sinTable[n+1]=sin(2*pi*n/tableSize);
+ * }</pre>
+ * \par
+ * where pi value is 3.14159265358979
+ */
+
+static const float32_t sinTable[259] = {
+ -0.024541229009628296f, 0.000000000000000000f, 0.024541229009628296f,
+ 0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,
+ 0.122410677373409270f, 0.146730467677116390f,
+ 0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,
+ 0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,
+ 0.313681751489639280f, 0.336889863014221190f,
+ 0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,
+ 0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,
+ 0.492898195981979370f, 0.514102756977081300f,
+ 0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,
+ 0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,
+ 0.653172850608825680f, 0.671558976173400880f,
+ 0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,
+ 0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,
+ 0.788346409797668460f, 0.803207516670227050f,
+ 0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,
+ 0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,
+ 0.893224298954010010f, 0.903989315032958980f,
+ 0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,
+ 0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,
+ 0.963776051998138430f, 0.970031261444091800f,
+ 0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,
+ 0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,
+ 0.997290432453155520f, 0.998795449733734130f,
+ 0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+ 0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,
+ 0.992479562759399410f, 0.989176511764526370f,
+ 0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,
+ 0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,
+ 0.949528157711029050f, 0.941544055938720700f,
+ 0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,
+ 0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,
+ 0.870086967945098880f, 0.857728600502014160f,
+ 0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,
+ 0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,
+ 0.757208824157714840f, 0.740951120853424070f,
+ 0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,
+ 0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,
+ 0.615231573581695560f, 0.595699310302734380f,
+ 0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,
+ 0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,
+ 0.449611335992813110f, 0.427555084228515630f,
+ 0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,
+ 0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,
+ 0.266712754964828490f, 0.242980182170867920f,
+ 0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,
+ 0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,
+ 0.073564566671848297f, 0.049067676067352295f,
+ 0.024541229009628296f, 0.000000000000000122f, -0.024541229009628296f,
+ -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,
+ -0.122410677373409270f, -0.146730467677116390f,
+ -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,
+ -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,
+ -0.313681751489639280f, -0.336889863014221190f,
+ -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,
+ -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,
+ -0.492898195981979370f, -0.514102756977081300f,
+ -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,
+ -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,
+ -0.653172850608825680f, -0.671558976173400880f,
+ -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,
+ -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,
+ -0.788346409797668460f, -0.803207516670227050f,
+ -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,
+ -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,
+ -0.893224298954010010f, -0.903989315032958980f,
+ -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,
+ -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,
+ -0.963776051998138430f, -0.970031261444091800f,
+ -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,
+ -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,
+ -0.997290432453155520f, -0.998795449733734130f,
+ -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,
+ -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,
+ -0.992479562759399410f, -0.989176511764526370f,
+ -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,
+ -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,
+ -0.949528157711029050f, -0.941544055938720700f,
+ -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,
+ -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,
+ -0.870086967945098880f, -0.857728600502014160f,
+ -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,
+ -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,
+ -0.757208824157714840f, -0.740951120853424070f,
+ -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,
+ -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,
+ -0.615231573581695560f, -0.595699310302734380f,
+ -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,
+ -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,
+ -0.449611335992813110f, -0.427555084228515630f,
+ -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,
+ -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,
+ -0.266712754964828490f, -0.242980182170867920f,
+ -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,
+ -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,
+ -0.073564566671848297f, -0.049067676067352295f,
+ -0.024541229009628296f, -0.000000000000000245f, 0.024541229009628296f
+};
+
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+
+float32_t arm_sin_f32(
+ float32_t x)
+{
+ float32_t sinVal, fract, in; /* Temporary variables for input, output */
+ int32_t index; /* Index variable */
+ uint32_t tableSize = (uint32_t) TABLE_SIZE; /* Initialise tablesize */
+ float32_t wa, wb, wc, wd; /* Cubic interpolation coefficients */
+ float32_t a, b, c, d; /* Four nearest output values */
+ float32_t *tablePtr; /* Pointer to table */
+ int32_t n;
+ float32_t fractsq, fractby2, fractby6, fractby3, fractsqby2;
+ float32_t oneminusfractby2;
+ float32_t frby2xfrsq, frby6xfrsq;
+
+ /* input x is in radians */
+ /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+ in = x * 0.159154943092f;
+
+ /* Calculation of floor value of input */
+ n = (int32_t) in;
+
+ /* Make negative values towards -infinity */
+ if(x < 0.0f)
+ {
+ n = n - 1;
+ }
+
+ /* Map input value to [0 1] */
+ in = in - (float32_t) n;
+
+ /* Calculation of index of the table */
+ index = (uint32_t) (tableSize * in);
+
+ /* fractional value calculation */
+ fract = ((float32_t) tableSize * in) - (float32_t) index;
+
+ /* Checking min and max index of table */
+ if(index < 0)
+ {
+ index = 0;
+ }
+ else if(index > 256)
+ {
+ index = 256;
+ }
+
+ /* Initialise table pointer */
+ tablePtr = (float32_t *) & sinTable[index];
+
+ /* Read four nearest values of input value from the sin table */
+ a = tablePtr[0];
+ b = tablePtr[1];
+ c = tablePtr[2];
+ d = tablePtr[3];
+
+ /* Cubic interpolation process */
+ fractsq = fract * fract;
+ fractby2 = fract * 0.5f;
+ fractby6 = fract * 0.166666667f;
+ fractby3 = fract * 0.3333333333333f;
+ fractsqby2 = fractsq * 0.5f;
+ frby2xfrsq = (fractby2) * fractsq;
+ frby6xfrsq = (fractby6) * fractsq;
+ oneminusfractby2 = 1.0f - fractby2;
+ wb = fractsqby2 - fractby3;
+ wc = (fractsqby2 + fract);
+ wa = wb - frby6xfrsq;
+ wb = frby2xfrsq - fractsq;
+ sinVal = wa * a;
+ wc = wc - frby2xfrsq;
+ wd = (frby6xfrsq) - fractby6;
+ wb = wb + oneminusfractby2;
+
+ /* Calculate sin value */
+ sinVal = (sinVal + (b * wb)) + ((c * wc) + (d * wd));
+
+ /* Return the output value */
+ return (sinVal);
+
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_q15.c
new file mode 100644
index 000000000..6bbacc634
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_q15.c
@@ -0,0 +1,216 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_q15.c
+*
+* Description: Fast sine calculation for Q15 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup sin
+ * @{
+ */
+
+
+/**
+* \par
+ * Table values are in Q15 (1.15 fixed-point format) and generation is done in
+ * three steps. First, generate sin values in floating point:
+ * <pre>
+ * tableSize = 256;
+ * for(n = -1; n < (tableSize + 1); n++)
+ * {
+ * sinTable[n+1]= sin(2*pi*n/tableSize);
+ * } </pre>
+ * where pi value is 3.14159265358979
+ * \par
+ * Second, convert floating-point to Q15 (fixed-point):
+ * (sinTable[i] * pow(2, 15))
+ * \par
+ * Finally, round to the nearest integer value:
+ * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
+*/
+
+static const q15_t sinTableQ15[259] = {
+ 0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
+ 0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,
+ 0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,
+ 0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,
+ 0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,
+ 0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,
+ 0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,
+ 0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,
+ 0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,
+ 0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,
+ 0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,
+ 0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,
+ 0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,
+ 0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,
+ 0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,
+ 0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,
+ 0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,
+ 0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,
+ 0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,
+ 0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,
+ 0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,
+ 0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,
+ 0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,
+ 0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,
+ 0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,
+ 0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,
+ 0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,
+ 0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,
+ 0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,
+ 0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,
+ 0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,
+ 0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,
+ 0xfcdc, 0x0, 0x324
+};
+
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ *
+ * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi).
+ */
+
+q15_t arm_sin_q15(
+ q15_t x)
+{
+ q31_t sinVal; /* Temporary variables output */
+ q15_t *tablePtr; /* Pointer to table */
+ q15_t fract, in, in2; /* Temporary variables for input, output */
+ q31_t wa, wb, wc, wd; /* Cubic interpolation coefficients */
+ q15_t a, b, c, d; /* Four nearest output values */
+ q15_t fractCube, fractSquare; /* Temporary values for fractional value */
+ q15_t oneBy6 = 0x1555; /* Fixed point value of 1/6 */
+ q15_t tableSpacing = TABLE_SPACING_Q15; /* Table spacing */
+ int32_t index; /* Index variable */
+
+ in = x;
+
+ /* Calculate the nearest index */
+ index = (int32_t) in / tableSpacing;
+
+ /* Calculate the nearest value of input */
+ in2 = (q15_t) ((index) * tableSpacing);
+
+ /* Calculation of fractional value */
+ fract = (in - in2) << 8;
+
+ /* fractSquare = fract * fract */
+ fractSquare = (q15_t) ((fract * fract) >> 15);
+
+ /* fractCube = fract * fract * fract */
+ fractCube = (q15_t) ((fractSquare * fract) >> 15);
+
+ /* Checking min and max index of table */
+ if(index < 0)
+ {
+ index = 0;
+ }
+ else if(index > 256)
+ {
+ index = 256;
+ }
+
+ /* Initialise table pointer */
+ tablePtr = (q15_t *) & sinTableQ15[index];
+
+ /* Cubic interpolation process */
+ /* Calculation of wa */
+ /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */
+ wa = (q31_t) oneBy6 *fractCube;
+ wa += (q31_t) 0x2AAA *fract;
+ wa = -(wa >> 15);
+ wa += ((q31_t) fractSquare >> 1u);
+
+ /* Read first nearest value of output from the sin table */
+ a = *tablePtr++;
+
+ /* sinVal = a * wa */
+ sinVal = a * wa;
+
+ /* Calculation of wb */
+ wb = (((q31_t) fractCube >> 1u) - (q31_t) fractSquare) -
+ (((q31_t) fract >> 1u) - 0x7FFF);
+
+ /* Read second nearest value of output from the sin table */
+ b = *tablePtr++;
+
+ /* sinVal += b*wb */
+ sinVal += b * wb;
+
+
+ /* Calculation of wc */
+ wc = -(q31_t) fractCube + fractSquare;
+ wc = (wc >> 1u) + fract;
+
+ /* Read third nearest value of output from the sin table */
+ c = *tablePtr++;
+
+ /* sinVal += c*wc */
+ sinVal += c * wc;
+
+ /* Calculation of wd */
+ /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+ fractCube = fractCube - fract;
+ wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));
+
+ /* Read fourth nearest value of output from the sin table */
+ d = *tablePtr++;
+
+ /* sinVal += d*wd; */
+ sinVal += d * wd;
+
+ /* Convert output value in 1.15(q15) format and saturate */
+ sinVal = __SSAT((sinVal >> 15), 16);
+
+ /* Return the output value in 1.15(q15) format */
+ return ((q15_t) sinVal);
+
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_q31.c
new file mode 100644
index 000000000..034a3b42c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_q31.c
@@ -0,0 +1,248 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sin_q31.c
+*
+* Description: Fast sine calculation for Q31 values.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+ /**
+ * @addtogroup sin
+ * @{
+ */
+
+/**
+ * \par
+ * Table values are in Q31 (1.31 fixed-point format) and generation is done in
+ * three steps. First, generate sin values in floating point:
+ * <pre>
+ * tableSize = 256;
+ * for(n = -1; n < (tableSize + 1); n++)
+ * {
+ * sinTable[n+1]= sin(2*pi*n/tableSize);
+ * } </pre>
+ * where pi value is 3.14159265358979
+ * \par
+ * Second, convert floating-point to Q31 (Fixed point):
+ * (sinTable[i] * pow(2, 31))
+ * \par
+ * Finally, round to the nearest integer value:
+ * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
+ */
+
+static const q31_t sinTableQ31[259] = {
+ 0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,
+ 0x12c8106f,
+ 0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,
+ 0x2826b928, 0x2b1f34eb,
+ 0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,
+ 0x3f1749b8, 0x41ce1e65,
+ 0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,
+ 0x539b2af0, 0x55f5a4d2,
+ 0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,
+ 0x64e88926, 0x66cf8120,
+ 0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,
+ 0x72552c85, 0x73b5ebd1,
+ 0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,
+ 0x7b5d039e, 0x7c29fbee,
+ 0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,
+ 0x7fa736b4, 0x7fd8878e,
+ 0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,
+ 0x7f0991c4, 0x7e9d55fc,
+ 0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,
+ 0x798a23b1, 0x78848414,
+ 0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,
+ 0x6f5f02b2, 0x6dca0d14,
+ 0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,
+ 0x60ec3830, 0x5ed77c8a,
+ 0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,
+ 0x4ebfe8a5, 0x4c3fdff4,
+ 0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,
+ 0x398cdd32, 0x36ba2014,
+ 0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,
+ 0x2223a4c5, 0x1f19f97b,
+ 0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,
+ 0x96a9049, 0x647d97c,
+ 0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,
+ 0xed37ef91,
+ 0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,
+ 0xd7d946d8, 0xd4e0cb15,
+ 0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,
+ 0xc0e8b648, 0xbe31e19b,
+ 0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,
+ 0xac64d510, 0xaa0a5b2e,
+ 0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,
+ 0x9b1776da, 0x99307ee0,
+ 0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,
+ 0x8daad37b, 0x8c4a142f,
+ 0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,
+ 0x84a2fc62, 0x83d60412,
+ 0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,
+ 0x8058c94c, 0x80277872,
+ 0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,
+ 0x80f66e3c, 0x8162aa04,
+ 0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,
+ 0x8675dc4f, 0x877b7bec,
+ 0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,
+ 0x90a0fd4e, 0x9235f2ec,
+ 0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,
+ 0x9f13c7d0, 0xa1288376,
+ 0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,
+ 0xb140175b, 0xb3c0200c,
+ 0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,
+ 0xc67322ce, 0xc945dfec,
+ 0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,
+ 0xdddc5b3b, 0xe0e60685,
+ 0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,
+ 0xf6956fb7, 0xf9b82684,
+ 0xfcdbd541, 0x0, 0x3242abf
+};
+
+
+/**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ *
+ * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). */
+
+q31_t arm_sin_q31(
+ q31_t x)
+{
+ q31_t sinVal, in, in2; /* Temporary variables for input, output */
+ int32_t index; /* Index variables */
+ q31_t wa, wb, wc, wd; /* Cubic interpolation coefficients */
+ q31_t a, b, c, d; /* Four nearest output values */
+ q31_t *tablePtr; /* Pointer to table */
+ q31_t fract, fractCube, fractSquare; /* Temporary values for fractional values */
+ q31_t oneBy6 = 0x15555555; /* Fixed point value of 1/6 */
+ q31_t tableSpacing = TABLE_SPACING_Q31; /* Table spacing */
+ q31_t temp; /* Temporary variable for intermediate process */
+
+ in = x;
+
+ /* Calculate the nearest index */
+ index = (uint32_t) in / (uint32_t) tableSpacing;
+
+ /* Calculate the nearest value of input */
+ in2 = (q31_t) index *tableSpacing;
+
+ /* Calculation of fractional value */
+ fract = (in - in2) << 8;
+
+ /* fractSquare = fract * fract */
+ fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));
+ fractSquare = fractSquare << 1;
+
+ /* fractCube = fract * fract * fract */
+ fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));
+ fractCube = fractCube << 1;
+
+ /* Checking min and max index of table */
+ if(index < 0)
+ {
+ index = 0;
+ }
+ else if(index > 256)
+ {
+ index = 256;
+ }
+
+ /* Initialise table pointer */
+ tablePtr = (q31_t *) & sinTableQ31[index];
+
+ /* Cubic interpolation process */
+ /* Calculation of wa */
+ /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */
+ wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+ temp = 0x2AAAAAAA;
+ wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);
+ wa = -(wa << 1u);
+ wa += (fractSquare >> 1u);
+
+ /* Read first nearest value of output from the sin table */
+ a = *tablePtr++;
+
+ /* sinVal = a*wa */
+ sinVal = ((q31_t) (((q63_t) a * wa) >> 32));
+
+ /* q31(1.31) Fixed point value of 1 */
+ temp = 0x7FFFFFFF;
+
+ /* Calculation of wb */
+ wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;
+
+ /* Read second nearest value of output from the sin table */
+ b = *tablePtr++;
+
+ /* sinVal += b*wb */
+ sinVal = (q31_t) ((((q63_t) sinVal << 32) + (q63_t) b * (wb)) >> 32);
+
+ /* Calculation of wc */
+ wc = -fractCube + fractSquare;
+ wc = (wc >> 1u) + fract;
+
+ /* Read third nearest value of output from the sin table */
+ c = *tablePtr++;
+
+ /* sinVal += c*wc */
+ sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) c * wc)) >> 32);
+
+ /* Calculation of wd */
+ /* wd = (oneBy6) * fractCube - (oneBy6) * fract; */
+ fractCube = fractCube - fract;
+ wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+ wd = (wd << 1u);
+
+ /* Read fourth nearest value of output from the sin table */
+ d = *tablePtr++;
+
+ /* sinVal += d*wd; */
+ sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) d * wd)) >> 32);
+
+ /* convert sinVal in 2.30 format to 1.31 format */
+ return (__QADD(sinVal, sinVal));
+
+}
+
+/**
+ * @} end of sin group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sqrt_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sqrt_q15.c
new file mode 100644
index 000000000..07b5a90c1
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sqrt_q15.c
@@ -0,0 +1,155 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sqrt_q15.c
+*
+* Description: Q15 square root function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if the input value is positive
+ * and ARM_MATH_ARGUMENT_ERROR if the input is negative. For
+ * negative inputs, the function returns *pOut = 0.
+ */
+
+arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut)
+{
+ q15_t number, temp1, var1, signBits1, half;
+ q31_t bits_val1;
+ float32_t temp_float1;
+ union
+ {
+ q31_t fracval;
+ float32_t floatval;
+ } tempconv;
+
+ number = in;
+
+ /* If the input is a positive number then compute the signBits. */
+ if(number > 0)
+ {
+ signBits1 = __CLZ(number) - 17;
+
+ /* Shift by the number of signBits1 */
+ if((signBits1 % 2) == 0)
+ {
+ number = number << signBits1;
+ }
+ else
+ {
+ number = number << (signBits1 - 1);
+ }
+
+ /* Calculate half value of the number */
+ half = number >> 1;
+ /* Store the number for later use */
+ temp1 = number;
+
+ /*Convert to float */
+ temp_float1 = number * 3.051757812500000e-005f;
+ /*Store as integer */
+ tempconv.floatval = temp_float1;
+ bits_val1 = tempconv.fracval;
+ /* Subtract the shifted value from the magic number to give intial guess */
+ bits_val1 = 0x5f3759df - (bits_val1 >> 1); // gives initial guess
+ /* Store as float */
+ tempconv.fracval = bits_val1;
+ temp_float1 = tempconv.floatval;
+ /* Convert to integer format */
+ var1 = (q31_t) (temp_float1 * 16384);
+
+ /* 1st iteration */
+ var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+ ((q15_t)
+ ((((q15_t)
+ (((q31_t) var1 * var1) >> 15)) *
+ (q31_t) half) >> 15))) >> 15)) << 2;
+ /* 2nd iteration */
+ var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+ ((q15_t)
+ ((((q15_t)
+ (((q31_t) var1 * var1) >> 15)) *
+ (q31_t) half) >> 15))) >> 15)) << 2;
+ /* 3rd iteration */
+ var1 = ((q15_t) ((q31_t) var1 * (0x3000 -
+ ((q15_t)
+ ((((q15_t)
+ (((q31_t) var1 * var1) >> 15)) *
+ (q31_t) half) >> 15))) >> 15)) << 2;
+
+ /* Multiply the inverse square root with the original value */
+ var1 = ((q15_t) (((q31_t) temp1 * var1) >> 15)) << 1;
+
+ /* Shift the output down accordingly */
+ if((signBits1 % 2) == 0)
+ {
+ var1 = var1 >> (signBits1 / 2);
+ }
+ else
+ {
+ var1 = var1 >> ((signBits1 - 1) / 2);
+ }
+ *pOut = var1;
+
+ return (ARM_MATH_SUCCESS);
+ }
+ /* If the number is a negative number then store zero as its square root value */
+ else
+ {
+ *pOut = 0;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+}
+
+/**
+ * @} end of SQRT group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sqrt_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sqrt_q31.c
new file mode 100644
index 000000000..7217834a8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sqrt_q31.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_sqrt_q31.c
+*
+* Description: Q31 square root function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupFastMath
+ */
+
+/**
+ * @addtogroup SQRT
+ * @{
+ */
+
+/**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if the input value is positive
+ * and ARM_MATH_ARGUMENT_ERROR if the input is negative. For
+ * negative inputs, the function returns *pOut = 0.
+ */
+
+arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut)
+{
+ q31_t number, temp1, bits_val1, var1, signBits1, half;
+ float32_t temp_float1;
+ union
+ {
+ q31_t fracval;
+ float32_t floatval;
+ } tempconv;
+
+ number = in;
+
+ /* If the input is a positive number then compute the signBits. */
+ if(number > 0)
+ {
+ signBits1 = __CLZ(number) - 1;
+
+ /* Shift by the number of signBits1 */
+ if((signBits1 % 2) == 0)
+ {
+ number = number << signBits1;
+ }
+ else
+ {
+ number = number << (signBits1 - 1);
+ }
+
+ /* Calculate half value of the number */
+ half = number >> 1;
+ /* Store the number for later use */
+ temp1 = number;
+
+ /*Convert to float */
+ temp_float1 = number * 4.6566128731e-010f;
+ /*Store as integer */
+ tempconv.floatval = temp_float1;
+ bits_val1 = tempconv.fracval;
+ /* Subtract the shifted value from the magic number to give intial guess */
+ bits_val1 = 0x5f3759df - (bits_val1 >> 1); // gives initial guess
+ /* Store as float */
+ tempconv.fracval = bits_val1;
+ temp_float1 = tempconv.floatval;
+ /* Convert to integer format */
+ var1 = (q31_t) (temp_float1 * 1073741824);
+
+ /* 1st iteration */
+ var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+ ((q31_t)
+ ((((q31_t)
+ (((q63_t) var1 * var1) >> 31)) *
+ (q63_t) half) >> 31))) >> 31)) << 2;
+ /* 2nd iteration */
+ var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+ ((q31_t)
+ ((((q31_t)
+ (((q63_t) var1 * var1) >> 31)) *
+ (q63_t) half) >> 31))) >> 31)) << 2;
+ /* 3rd iteration */
+ var1 = ((q31_t) ((q63_t) var1 * (0x30000000 -
+ ((q31_t)
+ ((((q31_t)
+ (((q63_t) var1 * var1) >> 31)) *
+ (q63_t) half) >> 31))) >> 31)) << 2;
+
+ /* Multiply the inverse square root with the original value */
+ var1 = ((q31_t) (((q63_t) temp1 * var1) >> 31)) << 1;
+
+ /* Shift the output down accordingly */
+ if((signBits1 % 2) == 0)
+ {
+ var1 = var1 >> (signBits1 / 2);
+ }
+ else
+ {
+ var1 = var1 >> ((signBits1 - 1) / 2);
+ }
+ *pOut = var1;
+
+ return (ARM_MATH_SUCCESS);
+ }
+ /* If the number is a negative number then store zero as its square root value */
+ else
+ {
+ *pOut = 0;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+}
+
+/**
+ * @} end of SQRT group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
new file mode 100644
index 000000000..dccba7b52
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_32x64_init_q31.c
+*
+* Description: High precision Q31 Biquad cascade filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1_32x64
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format.
+ * @return none
+ *
+ * <b>Coefficient and State Ordering:</b>
+ *
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * </pre>
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
+ *
+ * \par
+ * The <code>pState</code> points to state variables array and size of each state variable is 1.63 format.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the state array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1_32x64 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
new file mode 100644
index 000000000..f6a4f83ec
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
@@ -0,0 +1,561 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_32x64_q31.c
+*
+* Description: High precision Q31 Biquad cascade filter processing function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter
+ *
+ * This function implements a high precision Biquad cascade filter which operates on
+ * Q31 data values. The filter coefficients are in 1.31 format and the state variables
+ * are in 1.63 format. The double precision state variables reduce quantization noise
+ * in the filter and provide a cleaner output.
+ * These filters are particularly useful when implementing filters in which the
+ * singularities are close to the unit circle. This is common for low pass or high
+ * pass filters with very low cutoff frequencies.
+ *
+ * The function operates on blocks of input and output data
+ * and each call to the function processes <code>blockSize</code> samples through
+ * the filter. <code>pSrc</code> and <code>pDst</code> points to input and output arrays
+ * containing <code>blockSize</code> Q31 values.
+ *
+ * \par Algorithm
+ * Each Biquad stage implements a second order filter using the difference equation:
+ * <pre>
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * </pre>
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
+ * \image html Biquad.gif "Single Biquad filter stage"
+ * Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
+ * Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
+ * Pay careful attention to the sign of the feedback coefficients.
+ * Some design tools use the difference equation
+ * <pre>
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+ * </pre>
+ * In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
+ *
+ * \par
+ * Higher order filters are realized as a cascade of second order sections.
+ * <code>numStages</code> refers to the number of second order stages used.
+ * For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
+ * A 9th order filter would be realized with <code>numStages=5</code> second order stages with the coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
+ *
+ * \par
+ * The <code>pState</code> points to state variables array .
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code> and each state variable in 1.63 format to improve precision.
+ * The state variables are arranged in the array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ *
+ * \par
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values of data in 1.63 format.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ *
+ * \par Init Function
+ * There is also an associated initialization function which performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * For example, to statically initialize the filter instance structure use
+ * <pre>
+ * arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};
+ * </pre>
+ * where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer;
+ * <code>pCoeffs</code> is the address of the coefficient buffer; <code>postShift</code> shift to be applied which is described in detail below.
+ * \par Fixed-Point Behavior
+ * Care must be taken while using Biquad Cascade 32x64 filter function.
+ * Following issues must be considered:
+ * - Scaling of coefficients
+ * - Filter gain
+ * - Overflow and saturation
+ *
+ * \par
+ * Filter coefficients are represented as fractional values and
+ * restricted to lie in the range <code>[-1 +1)</code>.
+ * The processing function has an additional scaling parameter <code>postShift</code>
+ * which allows the filter coefficients to exceed the range <code>[+1 -1)</code>.
+ * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
+ * This essentially scales the filter coefficients by <code>2^postShift</code>.
+ * For example, to realize the coefficients
+ * <pre>
+ * {1.5, -0.8, 1.2, 1.6, -0.9}
+ * </pre>
+ * set the Coefficient array to:
+ * <pre>
+ * {0.75, -0.4, 0.6, 0.8, -0.45}
+ * </pre>
+ * and set <code>postShift=1</code>
+ *
+ * \par
+ * The second thing to keep in mind is the gain through the filter.
+ * The frequency response of a Biquad filter is a function of its coefficients.
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
+ *
+ * \par
+ * The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.
+ * This is described in the function specific documentation below.
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1_32x64
+ * @{
+ */
+
+/**
+ * @details
+
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by <code>postShift</code> bits and the result truncated to
+ * 1.31 format by discarding the low 32 bits.
+ *
+ * \par
+ * Two related functions are provided in the CMSIS DSP library.
+ * <code>arm_biquad_cascade_df1_q31()</code> implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.
+ * <code>arm_biquad_cascade_df1_fast_q31()</code> implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.
+ */
+
+void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q63_t *pState = S->pState; /* state pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q63_t acc; /* accumulator */
+ q31_t Xn1, Xn2; /* Input Filter state variables */
+ q63_t Yn1, Yn2; /* Output Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t Xn; /* temporary input */
+ int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+ q31_t acc_l, acc_h; /* temporary output */
+ uint32_t uShift = ((uint32_t) S->postShift + 1u);
+ uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = (q31_t) (pState[0]);
+ Xn2 = (q31_t) (pState[1]);
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variable acc hold output value that is being computed and
+ * stored in the destination buffer
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* The result is converted to 1.63 , Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut = acc_h;
+
+ /* Read the second input into Xn2, to reuse the value */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc += b1 * x[n-1] */
+ acc = (q63_t) Xn *b1;
+
+ /* acc = b0 * x[n] */
+ acc += (q63_t) Xn2 *b0;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn1 *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn2, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn1, a2);
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Read the third input into Xn1, to reuse the value */
+ Xn1 = *pIn++;
+
+ /* The result is converted to 1.31 */
+ /* Store the output in the destination buffer. */
+ *(pOut + 1u) = acc_h;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn1 *b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn2 *b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* The result is converted to 1.63, Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *(pOut + 2u) = acc_h;
+
+ /* Read the fourth input into Xn, to reuse the value */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn2, a1);
+
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn1, a2);
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *(pOut + 3u) = acc_h;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* update output pointer */
+ pOut += 4u;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = (blockSize & 0x3u);
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut++ = acc_h;
+ //Yn1 = acc << shift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+// *pOut++ = (q31_t) (acc >> (32 - shift));
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage output is given as input to the second stage. */
+ pIn = pDst;
+
+ /* Reset to destination buffer working pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ /* Store the updated state variables back into the pState array */
+ *pState++ = (q63_t) Xn1;
+ *pState++ = (q63_t) Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variable acc hold output value that is being computed and
+ * stored in the destination buffer
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q63_t) Xn *b0;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) Xn1 *b1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) Xn2 *b2;
+ /* acc += a1 * y[n-1] */
+ acc += mult32x64(Yn1, a1);
+ /* acc += a2 * y[n-2] */
+ acc += mult32x64(Yn2, a2);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+
+ /* The result is converted to 1.63, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc_h = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ *pOut++ = acc_h;
+
+ //Yn1 = acc << shift;
+
+ /* Store the output in the destination buffer in 1.31 format. */
+ //*pOut++ = (q31_t) (acc >> (32 - shift));
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage output is given as input to the second stage. */
+ pIn = pDst;
+
+ /* Reset to destination buffer working pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = (q63_t) Xn1;
+ *pState++ = (q63_t) Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
+
+ /**
+ * @} end of BiquadCascadeDF1_32x64 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_f32.c
new file mode 100644
index 000000000..f3002bb3e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_f32.c
@@ -0,0 +1,425 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_f32.c
+*
+* Description: Processing function for the
+* floating-point Biquad cascade DirectFormI(DF1) filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure
+ *
+ * This set of functions implements arbitrary order recursive (IIR) filters.
+ * The filters are implemented as a cascade of second order Biquad sections.
+ * The functions support Q15, Q31 and floating-point data types.
+ * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.
+ *
+ * The functions operate on blocks of input and output data and each call to the function
+ * processes <code>blockSize</code> samples through the filter.
+ * <code>pSrc</code> points to the array of input data and
+ * <code>pDst</code> points to the array of output data.
+ * Both arrays contain <code>blockSize</code> values.
+ *
+ * \par Algorithm
+ * Each Biquad stage implements a second order filter using the difference equation:
+ * <pre>
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * </pre>
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.
+ * \image html Biquad.gif "Single Biquad filter stage"
+ * Coefficients <code>b0, b1 and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
+ * Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
+ * Pay careful attention to the sign of the feedback coefficients.
+ * Some design tools use the difference equation
+ * <pre>
+ * y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]
+ * </pre>
+ * In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
+ *
+ * \par
+ * Higher order filters are realized as a cascade of second order sections.
+ * <code>numStages</code> refers to the number of second order stages used.
+ * For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"
+ * A 9th order filter would be realized with <code>numStages=5</code> second order stages with the coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
+ *
+ * \par
+ * The <code>pState</code> points to state variables array.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the <code>pState</code> array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ *
+ * \par
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Init Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ * <pre>
+ * arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};
+ * arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};
+ * arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};
+ * </pre>
+ * where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer;
+ * <code>pCoeffs</code> is the address of the coefficient buffer; <code>postShift</code> shift to be applied.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.
+ * Following issues must be considered:
+ * - Scaling of coefficients
+ * - Filter gain
+ * - Overflow and saturation
+ *
+ * \par
+ * <b>Scaling of coefficients: </b>
+ * Filter coefficients are represented as fractional values and
+ * coefficients are restricted to lie in the range <code>[-1 +1)</code>.
+ * The fixed-point functions have an additional scaling parameter <code>postShift</code>
+ * which allow the filter coefficients to exceed the range <code>[+1 -1)</code>.
+ * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"
+ * This essentially scales the filter coefficients by <code>2^postShift</code>.
+ * For example, to realize the coefficients
+ * <pre>
+ * {1.5, -0.8, 1.2, 1.6, -0.9}
+ * </pre>
+ * set the pCoeffs array to:
+ * <pre>
+ * {0.75, -0.4, 0.6, 0.8, -0.45}
+ * </pre>
+ * and set <code>postShift=1</code>
+ *
+ * \par
+ * <b>Filter gain: </b>
+ * The frequency response of a Biquad filter is a function of its coefficients.
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.
+ *
+ * \par
+ * <b>Overflow and saturation: </b>
+ * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ */
+
+void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* source pointer */
+ float32_t *pOut = pDst; /* destination pointer */
+ float32_t *pState = S->pState; /* pState pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float32_t acc; /* Simulates the accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn1, Xn2, Yn1, Yn2; /* Filter pState variables */
+ float32_t Xn; /* temporary input */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the pState values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u)
+ {
+ /* Read the first input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the second input */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the third input */
+ Xn1 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+
+ /* Read the forth input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* decrement the loop counter */
+ sample--;
+
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = blockSize & 0x3u;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* decrement the loop counter */
+ sample--;
+
+ }
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent numStages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the pState values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent numStages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+ /**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
new file mode 100644
index 000000000..65b0e41a8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
@@ -0,0 +1,286 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_fast_q15.c
+*
+* Description: Fast processing function for the
+* Q15 Biquad cascade filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).
+ * The 2.30 accumulator is then shifted by <code>postShift</code> bits and the result truncated to 1.15 format by discarding the low 16 bits.
+ *
+ * \par
+ * Refer to the function <code>arm_biquad_cascade_df1_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure.
+ * Use the function <code>arm_biquad_cascade_df1_init_q15()</code> to initialize the filter structure.
+ *
+ */
+
+void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q31_t in; /* Temporary variable to hold input value */
+ q31_t out; /* Temporary variable to hold output value */
+ q31_t b0; /* Temporary variable to hold bo value */
+ q31_t b1, a1; /* Filter coefficients */
+ q31_t state_in, state_out; /* Filter state variables */
+ q31_t acc; /* Accumulator */
+ int32_t shift = (int32_t) (15 - S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = S->numStages; /* Stage loop counter */
+
+
+
+ do
+ {
+
+ /* Read the b0 and 0 coefficients using SIMD */
+ b0 = *__SIMD32(pCoeffs)++;
+
+ /* Read the b1 and b2 coefficients using SIMD */
+ b1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the a1 and a2 coefficients using SIMD */
+ a1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the input state values from the state buffer: x[n-1], x[n-2] */
+ state_in = *__SIMD32(pState)++;
+
+ /* Read the output state values from the state buffer: y[n-1], y[n-2] */
+ state_out = *__SIMD32(pState)--;
+
+ /* Apply loop unrolling and compute 2 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+ sample = blockSize >> 1u;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ ** a second loop below computes the remaining 1 sample. */
+ while(sample > 0u)
+ {
+
+ /* Read the input */
+ in = *__SIMD32(pIn)++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUAD(b0, in);
+ /* acc = b1 * x[n-1] + acc += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+ state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUADX(b0, in);
+ /* acc0 = b1 * x[n-1] , acc0 += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+
+ /* Store the output in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in >> 16, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Decrement the loop counter */
+ sample--;
+
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ if((blockSize & 0x1u) != 0u)
+ {
+ /* Read the input */
+ in = *pIn++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out = __SMUAD(b0, in);
+
+#else
+
+ out = __SMUADX(b0, in);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc = b1 * x[n-1], acc += b2 * x[n-2] + out */
+ acc = __SMLAD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + acc += a2 * y[n-2] */
+ acc = __SMLAD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+ out = __SSAT((acc >> shift), 16);
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) out;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent (numStages - 1) occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the state array */
+ *__SIMD32(pState)++ = state_in;
+ *__SIMD32(pState)++ = state_out;
+
+
+ /* Decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+}
+
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
new file mode 100644
index 000000000..196047c39
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
@@ -0,0 +1,305 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_fast_q31.c
+*
+* Description: Processing function for the
+* Q31 Fast Biquad cascade DirectFormI(DF1) filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are added to a 2.30 accumulator.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function
+ * arm_biquad_cascade_df1_init_q31() to initialize filter structure.
+ *
+ * \par
+ * Refer to the function <code>arm_biquad_cascade_df1_q31()</code> for a slower implementation of this function which uses 64-bit accumulation to provide higher precision. Both the slow and the fast versions use the same instance structure.
+ * Use the function <code>arm_biquad_cascade_df1_init_q31()</code> to initialize the filter structure.
+ */
+
+void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t acc = 0; /* accumulator */
+ q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q31_t *pState = S->pState; /* pState pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q31_t Xn; /* temporary input */
+ int32_t shift = (int32_t) S->postShift + 1; /* Shift to be applied to the output */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variables acc ... acc3 hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);
+ mult_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);
+ multAcc_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31 , Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Read the second input */
+ Xn2 = *(pIn + 1u);
+
+ /* Store the output in the destination buffer. */
+ *pOut = Yn2;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);
+ mult_32x32_keep32_R(acc, b0, Xn2);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);
+ multAcc_32x32_keep32_R(acc, b1, Xn);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn1);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn2);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn1);
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Read the third input */
+ Xn1 = *(pIn + 2u);
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 1u) = Yn1;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);
+ mult_32x32_keep32_R(acc, b0, Xn1);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, b1, Xn2);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31, Yn2 variable is reused */
+ Yn2 = acc << shift;
+
+ /* Read the forth input */
+ Xn = *(pIn + 3u);
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 2u) = Yn2;
+ pIn += 4u;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+ mult_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn2);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn1);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ Xn2 = Xn1;
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ Yn1 = acc << shift;
+
+ /* Xn1 = Xn */
+ Xn1 = Xn;
+
+ /* Store the output in the destination buffer. */
+ *(pOut + 3u) = Yn1;
+ pOut += 4u;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = (blockSize & 0x3u);
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ //acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+ mult_32x32_keep32_R(acc, b0, Xn);
+ /* acc += b1 * x[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, b1, Xn1);
+ /* acc += b[2] * x[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, b2, Xn2);
+ /* acc += a1 * y[n-1] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+ multAcc_32x32_keep32_R(acc, a1, Yn1);
+ /* acc += a2 * y[n-2] */
+ //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+ multAcc_32x32_keep32_R(acc, a2, Yn2);
+
+ /* The result is converted to 1.31 */
+ acc = acc << shift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
new file mode 100644
index 000000000..5533f5095
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
@@ -0,0 +1,109 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_init_f32.c
+*
+* Description: floating-point Biquad cascade DirectFormI(DF1) filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients array.
+ * @param[in] *pState points to the state array.
+ * @return none
+ *
+ *
+ * <b>Coefficient and State Ordering:</b>
+ *
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * </pre>
+ *
+ * \par
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
+ *
+ * \par
+ * The <code>pState</code> is a pointer to state array.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the <code>pState</code> array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ *
+ */
+
+void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
new file mode 100644
index 000000000..b74734d35
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
@@ -0,0 +1,111 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_init_q15.c
+*
+* Description: Q15 Biquad cascade DirectFormI(DF1) filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the accumulator result. Varies according to the coefficients format
+ * @return none
+ *
+ * <b>Coefficient and State Ordering:</b>
+ *
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}
+ * </pre>
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>6*numStages</code> values.
+ * The zero coefficient between <code>b1</code> and <code>b2</code> facilities use of 16-bit SIMD instructions on the Cortex-M4.
+ *
+ * \par
+ * The state variables are stored in the array <code>pState</code>.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the <code>pState</code> array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
new file mode 100644
index 000000000..89b2477fc
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
@@ -0,0 +1,111 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_init_q31.c
+*
+* Description: Q31 Biquad cascade DirectFormI(DF1) filter initialization function.
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied after the accumulator. Varies according to the coefficients format
+ * @return none
+ *
+ * <b>Coefficient and State Ordering:</b>
+ *
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * </pre>
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
+ *
+ * \par
+ * The <code>pState</code> points to state variables array.
+ * Each Biquad stage has 4 state variables <code>x[n-1], x[n-2], y[n-1],</code> and <code>y[n-2]</code>.
+ * The state variables are arranged in the <code>pState</code> array as:
+ * <pre>
+ * {x[n-1], x[n-2], y[n-1], y[n-2]}
+ * </pre>
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.
+ * The state array has a total length of <code>4*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign postShift to be applied to the output */
+ S->postShift = postShift;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 4 * numStages */
+ memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_q15.c
new file mode 100644
index 000000000..f891a412a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_q15.c
@@ -0,0 +1,411 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_q15.c
+*
+* Description: Processing function for the
+* Q15 Biquad cascade DirectFormI(DF1) filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * The accumulator is then shifted by <code>postShift</code> bits to truncate the result to 1.15 format by discarding the low 16 bits.
+ * Finally, the result is saturated to 1.15 format.
+ *
+ * \par
+ * Refer to the function <code>arm_biquad_cascade_df1_fast_q15()</code> for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q31_t in; /* Temporary variable to hold input value */
+ q31_t out; /* Temporary variable to hold output value */
+ q31_t b0; /* Temporary variable to hold bo value */
+ q31_t b1, a1; /* Filter coefficients */
+ q31_t state_in, state_out; /* Filter state variables */
+ q31_t acc_l, acc_h;
+ q63_t acc; /* Accumulator */
+ int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */
+ int32_t uShift = (32 - lShift);
+
+ do
+ {
+ /* Read the b0 and 0 coefficients using SIMD */
+ b0 = *__SIMD32(pCoeffs)++;
+
+ /* Read the b1 and b2 coefficients using SIMD */
+ b1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the a1 and a2 coefficients using SIMD */
+ a1 = *__SIMD32(pCoeffs)++;
+
+ /* Read the input state values from the state buffer: x[n-1], x[n-2] */
+ state_in = *__SIMD32(pState)++;
+
+ /* Read the output state values from the state buffer: y[n-1], y[n-2] */
+ state_out = *__SIMD32(pState)--;
+
+ /* Apply loop unrolling and compute 2 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+ sample = blockSize >> 1u;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ ** a second loop below computes the remaining 1 sample. */
+ while(sample > 0u)
+ {
+
+ /* Read the input */
+ in = *__SIMD32(pIn)++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUAD(b0, in);
+
+ /* acc += b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+ state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* out = b0 * x[n] + 0 * 0 */
+ out = __SMUADX(b0, in);
+ /* acc += b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Store the output in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in >> 16, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Decrement the loop counter */
+ sample--;
+
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ if((blockSize & 0x1u) != 0u)
+ {
+ /* Read the input */
+ in = *pIn++;
+
+ /* out = b0 * x[n] + 0 * 0 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out = __SMUAD(b0, in);
+
+#else
+
+ out = __SMUADX(b0, in);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc = b1 * x[n-1] + b2 * x[n-2] + out */
+ acc = __SMLALD(b1, state_in, out);
+ /* acc += a1 * y[n-1] + a2 * y[n-2] */
+ acc = __SMLALD(a1, state_out, acc);
+
+ /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ out = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ out = __SSAT(out, 16);
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) out;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+ /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ state_in = __PKHBT(in, state_in, 16);
+ state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+ state_in = __PKHBT(state_in >> 16, in, 16);
+ state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ }
+
+ /* The first stage goes from the input wire to the output wire. */
+ /* Subsequent numStages occur in-place in the output wire */
+ pIn = pDst;
+
+ /* Reset the output pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the state array */
+ *__SIMD32(pState)++ = state_in;
+ *__SIMD32(pState)++ = state_out;
+
+
+ /* Decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t *pIn = pSrc; /* Source pointer */
+ q15_t *pOut = pDst; /* Destination pointer */
+ q15_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q15_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q15_t Xn; /* temporary input */
+ q63_t acc; /* Accumulator */
+ int32_t shift = (15 - (int32_t) S->postShift); /* Post shift */
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ uint32_t sample, stage = (uint32_t) S->numStages; /* Stage loop counter */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ pCoeffs++; // skip the 0 coefficient
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q31_t) b0 *Xn;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q31_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q31_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q31_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q31_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 */
+ acc = __SSAT((acc >> shift), 16);
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q15_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_q31.c
new file mode 100644
index 000000000..174398b9d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_q31.c
@@ -0,0 +1,402 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df1_q31.c
+*
+* Description: Processing function for the
+* Q31 Biquad cascade filter
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF1
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by <code>postShift</code> bits and the result truncated to
+ * 1.31 format by discarding the low 32 bits.
+ *
+ * \par
+ * Refer to the function <code>arm_biquad_cascade_df1_fast_q31()</code> for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q63_t acc; /* accumulator */
+ uint32_t uShift = ((uint32_t) S->postShift + 1u);
+ uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
+ q31_t *pIn = pSrc; /* input pointer initialization */
+ q31_t *pOut = pDst; /* output pointer initialization */
+ q31_t *pState = S->pState; /* pState pointer initialization */
+ q31_t *pCoeffs = S->pCoeffs; /* coeff pointer initialization */
+ q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
+ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ q31_t Xn; /* temporary input */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t acc_l, acc_h; /* temporary output variables */
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ /* The variable acc hold output values that are being computed:
+ *
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 , Yn2 variable is reused */
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Read the second input */
+ Xn2 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn2;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn1;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn2;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn1;
+
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* Read the third input */
+ Xn1 = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn1;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn2;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31, Yn2 variable is reused */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn2 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn2;
+
+ /* Read the forth input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn2;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn1;
+
+ /* The result is converted to 1.31, Yn1 variable is reused */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ Yn1 = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = Yn1;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ sample = (blockSize & 0x3u);
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 */
+ acc = acc >> lShift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q31_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /* Reading the state values */
+ Xn1 = pState[0];
+ Xn2 = pState[1];
+ Yn1 = pState[2];
+ Yn2 = pState[3];
+
+ /* The variables acc holds the output value that is computed:
+ * acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]
+ */
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn = *pIn++;
+
+ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+ /* acc = b0 * x[n] */
+ acc = (q63_t) b0 *Xn;
+
+ /* acc += b1 * x[n-1] */
+ acc += (q63_t) b1 *Xn1;
+ /* acc += b[2] * x[n-2] */
+ acc += (q63_t) b2 *Xn2;
+ /* acc += a1 * y[n-1] */
+ acc += (q63_t) a1 *Yn1;
+ /* acc += a2 * y[n-2] */
+ acc += (q63_t) a2 *Yn2;
+
+ /* The result is converted to 1.31 */
+ acc = acc >> lShift;
+
+ /* Every time after the output is computed state should be updated. */
+ /* The states should be updated as: */
+ /* Xn2 = Xn1 */
+ /* Xn1 = Xn */
+ /* Yn2 = Yn1 */
+ /* Yn1 = acc */
+ Xn2 = Xn1;
+ Xn1 = Xn;
+ Yn2 = Yn1;
+ Yn1 = (q31_t) acc;
+
+ /* Store the output in the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* The first stage goes from the input buffer to the output buffer. */
+ /* Subsequent stages occur in-place in the output buffer */
+ pIn = pDst;
+
+ /* Reset to destination pointer */
+ pOut = pDst;
+
+ /* Store the updated state variables back into the pState array */
+ *pState++ = Xn1;
+ *pState++ = Xn2;
+ *pState++ = Yn1;
+ *pState++ = Yn2;
+
+ } while(--stage);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+}
+
+/**
+ * @} end of BiquadCascadeDF1 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
new file mode 100644
index 000000000..1462d51e7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
@@ -0,0 +1,359 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df2T_f32.c
+*
+* Description: Processing function for the floating-point transposed
+* direct form II Biquad cascade filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
+*
+* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
+* The filters are implemented as a cascade of second order Biquad sections.
+* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
+* Only floating-point data is supported.
+*
+* This function operate on blocks of input and output data and each call to the function
+* processes <code>blockSize</code> samples through the filter.
+* <code>pSrc</code> points to the array of input data and
+* <code>pDst</code> points to the array of output data.
+* Both arrays contain <code>blockSize</code> values.
+*
+* \par Algorithm
+* Each Biquad stage implements a second order filter using the difference equation:
+* <pre>
+* y[n] = b0 * x[n] + d1
+* d1 = b1 * x[n] + a1 * y[n] + d2
+* d2 = b2 * x[n] + a2 * y[n]
+* </pre>
+* where d1 and d2 represent the two state values.
+*
+* \par
+* A Biquad filter using a transposed Direct Form II structure is shown below.
+* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
+* Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
+* Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
+* Pay careful attention to the sign of the feedback coefficients.
+* Some design tools flip the sign of the feedback coefficients:
+* <pre>
+* y[n] = b0 * x[n] + d1;
+* d1 = b1 * x[n] - a1 * y[n] + d2;
+* d2 = b2 * x[n] - a2 * y[n];
+* </pre>
+* In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
+*
+* \par
+* Higher order filters are realized as a cascade of second order sections.
+* <code>numStages</code> refers to the number of second order stages used.
+* For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
+* A 9th order filter would be realized with <code>numStages=5</code> second order stages with the
+* coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
+*
+* \par
+* <code>pState</code> points to the state variable array.
+* Each Biquad stage has 2 state variables <code>d1</code> and <code>d2</code>.
+* The state variables are arranged in the <code>pState</code> array as:
+* <pre>
+* {d11, d12, d21, d22, ...}
+* </pre>
+* where <code>d1x</code> refers to the state variables for the first Biquad and
+* <code>d2x</code> refers to the state variables for the second Biquad.
+* The state array has a total length of <code>2*numStages</code> values.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+*
+* \par
+* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
+* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
+* That is why the Direct Form I structure supports Q15 and Q31 data types.
+* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables <code>d1</code> and <code>d2</code>.
+* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
+* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
+*
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+*
+* \par Init Functions
+* There is also an associated initialization function.
+* The initialization function performs following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* For example, to statically initialize the instance structure use
+* <pre>
+* arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
+* </pre>
+* where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer.
+* <code>pCoeffs</code> is the address of the coefficient buffer;
+*
+*/
+
+/**
+* @addtogroup BiquadCascadeDF2T
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+* @param[in] *S points to an instance of the filter data structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[out] *pDst points to the block of output data
+* @param[in] blockSize number of samples to process.
+* @return none.
+*/
+
+
+LOW_OPTIMIZATION_ENTER
+void arm_biquad_cascade_df2T_f32(
+const arm_biquad_cascade_df2T_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+
+ float32_t *pIn = pSrc; /* source pointer */
+ float32_t *pOut = pDst; /* destination pointer */
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
+ float32_t acc1; /* accumulator */
+ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
+ float32_t Xn1; /* temporary input */
+ float32_t d1, d2; /* state variables */
+ uint32_t sample, stage = S->numStages; /* loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY_FAMILY
+
+ float32_t Xn2, Xn3, Xn4; /* Input State variables */
+ float32_t acc2, acc3, acc4; /* accumulator */
+
+
+ float32_t p0, p1, p2, p3, p4, A1;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+ /* Apply loop unrolling and compute 4 output values simultaneously. */
+ sample = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(sample > 0u) {
+
+ /* y[n] = b0 * x[n] + d1 */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ /* d2 = b2 * x[n] + a2 * y[n] */
+
+ /* Read the four inputs */
+ Xn1 = pIn[0];
+ Xn2 = pIn[1];
+ Xn3 = pIn[2];
+ Xn4 = pIn[3];
+ pIn += 4;
+
+ p0 = b0 * Xn1;
+ p1 = b1 * Xn1;
+ acc1 = p0 + d1;
+ p0 = b0 * Xn2;
+ p3 = a1 * acc1;
+ p2 = b2 * Xn1;
+ A1 = p1 + p3;
+ p4 = a2 * acc1;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ p1 = b1 * Xn2;
+ acc2 = p0 + d1;
+ p0 = b0 * Xn3;
+ p3 = a1 * acc2;
+ p2 = b2 * Xn2;
+ A1 = p1 + p3;
+ p4 = a2 * acc2;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ p1 = b1 * Xn3;
+ acc3 = p0 + d1;
+ p0 = b0 * Xn4;
+ p3 = a1 * acc3;
+ p2 = b2 * Xn3;
+ A1 = p1 + p3;
+ p4 = a2 * acc3;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ acc4 = p0 + d1;
+ p1 = b1 * Xn4;
+ p3 = a1 * acc4;
+ p2 = b2 * Xn4;
+ A1 = p1 + p3;
+ p4 = a2 * acc4;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ pOut[0] = acc1;
+ pOut[1] = acc2;
+ pOut[2] = acc3;
+ pOut[3] = acc4;
+ pOut += 4;
+
+ sample--;
+ }
+
+ sample = blockSize & 0x3u;
+ while(sample > 0u) {
+ Xn1 = *pIn++;
+
+ p0 = b0 * Xn1;
+ p1 = b1 * Xn1;
+ acc1 = p0 + d1;
+ p3 = a1 * acc1;
+ p2 = b2 * Xn1;
+ A1 = p1 + p3;
+ p4 = a2 * acc1;
+ d1 = A1 + d2;
+ d2 = p2 + p4;
+
+ *pOut++ = acc1;
+
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1;
+ *pState++ = d2;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ do
+ {
+ /* Reading the coefficients */
+ b0 = *pCoeffs++;
+ b1 = *pCoeffs++;
+ b2 = *pCoeffs++;
+ a1 = *pCoeffs++;
+ a2 = *pCoeffs++;
+
+ /*Reading the state values */
+ d1 = pState[0];
+ d2 = pState[1];
+
+
+ sample = blockSize;
+
+ while(sample > 0u)
+ {
+ /* Read the input */
+ Xn1 = *pIn++;
+
+ /* y[n] = b0 * x[n] + d1 */
+ acc1 = (b0 * Xn1) + d1;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc1;
+
+ /* Every time after the output is computed state should be updated. */
+ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+ d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
+
+ /* d2 = b2 * x[n] + a2 * y[n] */
+ d2 = (b2 * Xn1) + (a2 * acc1);
+
+ /* decrement the loop counter */
+ sample--;
+ }
+
+ /* Store the updated state variables back into the state array */
+ *pState++ = d1;
+ *pState++ = d2;
+
+ /* The current stage input is given as the output to the next stage */
+ pIn = pDst;
+
+ /*Reset the output working pointer */
+ pOut = pDst;
+
+ /* decrement the loop counter */
+ stage--;
+
+ } while(stage > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+LOW_OPTIMIZATION_EXIT
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
new file mode 100644
index 000000000..a84d095d7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
@@ -0,0 +1,102 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_biquad_cascade_df2T_init_f32.c
+*
+* Description: Initialization function for the floating-point transposed
+* direct form II Biquad cascade filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup BiquadCascadeDF2T
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ *
+ * <b>Coefficient and State Ordering:</b>
+ * \par
+ * The coefficients are stored in the array <code>pCoeffs</code> in the following order:
+ * <pre>
+ * {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}
+ * </pre>
+ *
+ * \par
+ * where <code>b1x</code> and <code>a1x</code> are the coefficients for the first stage,
+ * <code>b2x</code> and <code>a2x</code> are the coefficients for the second stage,
+ * and so on. The <code>pCoeffs</code> array contains a total of <code>5*numStages</code> values.
+ *
+ * \par
+ * The <code>pState</code> is a pointer to state array.
+ * Each Biquad stage has 2 state variables <code>d1,</code> and <code>d2</code>.
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.
+ * The state array has a total length of <code>2*numStages</code> values.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ */
+
+void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter stages */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always 2 * numStages */
+ memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+}
+
+/**
+ * @} end of BiquadCascadeDF2T group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_f32.c
new file mode 100644
index 000000000..dd9c95ae7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_f32.c
@@ -0,0 +1,647 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_f32.c
+*
+* Description: Convolution of floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup Conv Convolution
+ *
+ * Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector.
+ * Convolution is similar to correlation and is frequently used in filtering and data analysis.
+ * The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types.
+ * The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.
+ *
+ * \par Algorithm
+ * Let <code>a[n]</code> and <code>b[n]</code> be sequences of length <code>srcALen</code> and <code>srcBLen</code> samples respectively.
+ * Then the convolution
+ *
+ * <pre>
+ * c[n] = a[n] * b[n]
+ * </pre>
+ *
+ * \par
+ * is defined as
+ * \image html ConvolutionEquation.gif
+ * \par
+ * Note that <code>c[n]</code> is of length <code>srcALen + srcBLen - 1</code> and is defined over the interval <code>n=0, 1, 2, ..., srcALen + srcBLen - 2</code>.
+ * <code>pSrcA</code> points to the first input vector of length <code>srcALen</code> and
+ * <code>pSrcB</code> points to the second input vector of length <code>srcBLen</code>.
+ * The output result is written to <code>pDst</code> and the calling function must allocate <code>srcALen+srcBLen-1</code> words for the result.
+ *
+ * \par
+ * Conceptually, when two signals <code>a[n]</code> and <code>b[n]</code> are convolved,
+ * the signal <code>b[n]</code> slides over <code>a[n]</code>.
+ * For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together.
+ *
+ * \par
+ * Note that convolution is a commutative operation:
+ *
+ * <pre>
+ * a[n] * b[n] = b[n] * a[n].
+ * </pre>
+ *
+ * \par
+ * This means that switching the A and B arguments to the convolution functions has no effect.
+ *
+ * <b>Fixed-Point Behavior</b>
+ *
+ * \par
+ * Convolution requires summing up a large number of intermediate products.
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.
+ * Refer to the function specific documentation below for further details of the particular algorithm used.
+ *
+ *
+ * <b>Fast Versions</b>
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of conv and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * <b>Opt Versions</b>
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t *pIn1; /* inputA pointer */
+ float32_t *pIn2; /* inputB pointer */
+ float32_t *pOut = pDst; /* output pointer */
+ float32_t *px; /* Intermediate inputA pointer */
+ float32_t *py; /* Intermediate inputB pointer */
+ float32_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ float32_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ float32_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counters */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* x[1] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* x[2] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* x[3] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += x0 * c0;
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += x1 * c0;
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += x2 * c0;
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 += x3 * c0;
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px + 1u);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += x1 * c0;
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += x2 * c0;
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += x3 * c0;
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 += x0 * c0;
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px + 2u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += x2 * c0;
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += x3 * c0;
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += x0 * c0;
+ /* acc3 += x[5] * y[srcBLen - 2] */
+ acc3 += x1 * c0;
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px + 3u);
+ px += 4u;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 += x3 * c0;
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 += x0 * c0;
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 += x1 * c0;
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 += x2 * c0;
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += x0 * c0;
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += x1 * c0;
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += x2 * c0;
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += x3 * c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc0;
+ *pOut++ = acc1;
+ *pOut++ = acc2;
+ *pOut++ = acc3;
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB; /* inputB pointer */
+ float32_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0u; i < ((srcALen + srcBLen) - 1u); i++)
+ {
+ /* Initialize sum with zero to carry out MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += pIn1[j] * pIn2[i - j];
+ }
+ }
+ /* Store the output in the destination buffer */
+ pDst[i] = sum;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_opt_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_opt_q15.c
new file mode 100644
index 000000000..339854e4a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_opt_q15.c
@@ -0,0 +1,543 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_fast_opt_q15.c
+*
+* Description: Fast Q15 Convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results
+ * but provides only a single guard bit. There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_conv_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ */
+
+void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ uint32_t tapCnt; /* loop count */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifdef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1u) zeros in scratch1 buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ /* First part of the processing with loop unrolling process 4 data points at a time.
+ ** a second loop below process for the remaining 1 to 3 samples. */
+
+ /* Actual convolution process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x2, y2, acc0);
+ acc2 = __SMLAD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ a = *pScr1;
+ b = *(pScr1 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ a = *(pScr1 + 2);
+ b = *(pScr1 + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ acc0 += (*pScr1++ * *pIn2++);
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_q15.c
new file mode 100644
index 000000000..56bce36ca
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_q15.c
@@ -0,0 +1,1410 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_fast_q15.c
+*
+* Description: Fast Q15 Convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results
+ * but provides only a single guard bit. There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_conv_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ */
+
+void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + (count - 1u);
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2u;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ /* Read y[srcBLen - 7] */
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16);
+ *__SIMD32(pOut)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16);
+ *__SIMD32(pOut)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = blockSize3 >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
+ q15_t a, b;
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + (count - 1u);
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ a = *px++;
+ b = *px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *px;
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *px;
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x2 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(b, a, 16);
+
+#else
+
+ x2 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5], x[6] */
+ a = *(px + 2);
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ a = *px;
+ b = *(px+1);
+ px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ /* Read y[srcBLen - 7] */
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ a = *(px+2);
+ b = *(px+3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q15_t)(acc0 >> 15);
+ *pOut++ = (q15_t)(acc1 >> 15);
+ *pOut++ = (q15_t)(acc2 >> 15);
+ *pOut++ = (q15_t)(acc3 >> 15);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = blockSize3 >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while(k > 0u)
+ {
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_q31.c
new file mode 100644
index 000000000..b30d32589
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_q31.c
@@ -0,0 +1,577 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_fast_q31.c
+*
+* Description: Q31 Convolution (fast version).
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ *
+ * \par
+ * See <code>arm_conv_q31()</code> for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
+ */
+
+void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[1] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[2] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[3] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc1 += x[3] * y[srcBLen - 3] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc2 += x[4] * y[srcBLen - 3] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc3 += x[5] * y[srcBLen - 3] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 << 1);
+ *pOut++ = (q31_t) (acc1 << 1);
+ *pOut++ = (q31_t) (acc2 << 1);
+ *pOut++ = (q31_t) (acc3 << 1);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_opt_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_opt_q15.c
new file mode 100644
index 000000000..ff0b949b8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_opt_q15.c
@@ -0,0 +1,545 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_opt_q15.c
+*
+* Description: Convolution of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ *
+ * \par
+ * Refer to <code>arm_conv_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ *
+ */
+
+void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q63_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ uint32_t tapCnt; /* loop count */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ /* First part of the processing with loop unrolling process 4 data points at a time.
+ ** a second loop below process for the remaining 1 to 3 samples. */
+
+ /* Actual convolution process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x1, y1, acc0);
+ acc2 = __SMLALD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x2, y2, acc0);
+ acc2 = __SMLALD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ a = *pScr1;
+ b = *(pScr1 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLALD(x2, y2, acc0);
+
+ acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ a = *(pScr1 + 2);
+ b = *(pScr1 + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ acc0 += (*pScr1++ * *pIn2++);
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+}
+
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_opt_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_opt_q7.c
new file mode 100644
index 000000000..e3dc97ea7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_opt_q7.c
@@ -0,0 +1,435 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_opt_q7.c
+*
+* Description: Convolution of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as <code>max(srcALen, srcBLen)<131072</code>.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
+ *
+ */
+
+void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
+ q15_t x4; /* Temporary input variable */
+ q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* loop counter */
+ q7_t *px; /* Temporary input1 pointer */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3, y1; /* Temporary input variables */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t out0, out1, out2, out3; /* temporary variables */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2;
+
+ /* points to smaller length sequence */
+ px = pIn2 + srcBLen - 1;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = (q7_t *) py;
+
+ pScr2 = py;
+
+ /* Actual convolution process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+ acc0 = __SMLAD(x2, y1, acc0);
+
+ acc2 = __SMLAD(x1, y1, acc2);
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ pScr2 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+ *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+ acc0 += (*pScr1++ * *pScr2++);
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+}
+
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_f32.c
new file mode 100644
index 000000000..0ced29916
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_f32.c
@@ -0,0 +1,662 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_f32.c
+*
+* Description: Partial convolution of floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup PartialConv Partial Convolution
+ *
+ * Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.
+ * Each function has two additional arguments.
+ * <code>firstIndex</code> specifies the starting index of the subset of output samples.
+ * <code>numPoints</code> is the number of output samples to compute.
+ * The function computes the output in the range
+ * <code>[firstIndex, ..., firstIndex+numPoints-1]</code>.
+ * The output array <code>pDst</code> contains <code>numPoints</code> values.
+ *
+ * The allowable range of output indices is [0 srcALen+srcBLen-2].
+ * If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.
+ * Otherwise the functions return ARM_MATH_SUCCESS.
+ * \note Refer arm_conv_f32() for details on fixed point behavior.
+ *
+ *
+ * <b>Fast Versions</b>
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15 of partial convolution. Cycles for Fast versions are less compared to Q31 and Q15 of partial conv and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * <b>Opt Versions</b>
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of partial convolution
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB; /* inputB pointer */
+ float32_t *pOut = pDst; /* output pointer */
+ float32_t *px; /* Intermediate inputA pointer */
+ float32_t *py; /* Intermediate inputB pointer */
+ float32_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ float32_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ float32_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count = 0u, blkCnt, check;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = (int32_t) check - (int32_t) srcALen;
+ blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+ blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = ((int32_t) check - blockSize3) -
+ (blockSize1 + (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + firstIndex;
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* x[1] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* x[2] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* x[3] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc1;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += x0 * c0;
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += x1 * c0;
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += x2 * c0;
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 += x3 * c0;
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += x1 * c0;
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += x2 * c0;
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += x3 * c0;
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 += x0 * c0;
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += x2 * c0;
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += x3 * c0;
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += x0 * c0;
+ /* acc3 += x[5] * y[srcBLen - 2] */
+ acc3 += x1 * c0;
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 += x3 * c0;
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 += x0 * c0;
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 += x1 * c0;
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 += x2 * c0;
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += x0 * c0;
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += x1 * c0;
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += x2 * c0;
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += x3 * c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = acc0;
+ *pOut++ = acc1;
+ *pOut++ = acc2;
+ *pOut++ = acc3;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum += *px++ * *py--;
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += *px++ * *py--;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB; /* inputB pointer */
+ float32_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations for inputs */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += pIn1[j] * pIn2[i - j];
+ }
+ }
+ /* Store the output in the destination buffer */
+ pDst[i] = sum;
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_opt_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
new file mode 100644
index 000000000..3df1d3f21
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
@@ -0,0 +1,768 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_fast_opt_q15.c
+*
+* Description: Fast Q15 Partial convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See <code>arm_conv_partial_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status;
+
+ uint32_t tapCnt; /* loop count */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+
+ /* Copy smaller length input sequence in reverse order into second scratch buffer */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Assuming scratch1 buffer is aligned by 32-bit */
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* First part of the processing with loop unrolling process 4 data points at a time.
+ ** a second loop below process for the remaining 1 to 3 samples. */
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read two samples from smaller buffer */
+ y1 = *__SIMD32(pIn2)++;
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+ /* Return to application */
+ return (status);
+}
+
+#else
+
+arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status; /* Status variable */
+ uint32_t tapCnt; /* loop count */
+ q15_t x10, x11, x20, x21; /* Temporary variables to hold srcA buffer */
+ q15_t y10, y11; /* Temporary variables to hold srcB buffer */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *pScr1++;
+ x21 = *pScr1++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2;
+ y11 = *(pIn2 + 1u);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+ acc2 += (q31_t) x20 *y10;
+ acc2 += (q31_t) x21 *y11;
+
+ /* multiply and accumlate */
+ acc1 += (q31_t) x11 *y10;
+ acc1 += (q31_t) x20 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1;
+ x11 = *(pScr1 + 1u);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x21 *y10;
+ acc3 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch2 buffer */
+ y10 = *(pIn2 + 2u);
+ y11 = *(pIn2 + 3u);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x20 *y10;
+ acc0 += (q31_t) x21 *y11;
+ acc2 += (q31_t) x10 *y10;
+ acc2 += (q31_t) x11 *y11;
+ acc1 += (q31_t) x21 *y10;
+ acc1 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *(pScr1 + 2);
+ x21 = *(pScr1 + 3);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x11 *y10;
+ acc3 += (q31_t) x20 *y11;
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = __SSAT((acc0 >> 15), 16);
+ *pOut++ = __SSAT((acc1 >> 15), 16);
+ *pOut++ = __SSAT((acc2 >> 15), 16);
+ *pOut++ = __SSAT((acc3 >> 15), 16);
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2++;
+ y11 = *pIn2++;
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_q15.c
new file mode 100644
index 000000000..42a96ce3e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_q15.c
@@ -0,0 +1,1478 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_fast_q15.c
+*
+* Description: Fast Q15 Partial convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See <code>arm_conv_partial_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+
+arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >=srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t) check - (int32_t) srcALen);
+ blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2 - 1u;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2u;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ = __PKHBT(acc0 >> 15, acc1 >> 15, 16);
+ *__SIMD32(pOut)++ = __PKHBT(acc2 >> 15, acc3 >> 15, 16);
+
+#else
+
+ *__SIMD32(pOut)++ = __PKHBT(acc1 >> 15, acc0 >> 15, 16);
+ *__SIMD32(pOut)++ = __PKHBT(acc3 >> 15, acc2 >> 15, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = count >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLAD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+ q15_t a, b;
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >=srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t) check - (int32_t) srcALen);
+ blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2 - 1u;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ a = *px++;
+ b = *px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *px;
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *px;
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLADX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x2 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(b, a, 16);
+
+#else
+
+ x2 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLADX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLADX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ a = *py;
+ b = *(py+1);
+ py -= 2;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLADX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLADX(x3, c0, acc1);
+
+ /* Read x[4], x[5], x[6] */
+ a = *(px + 2);
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLADX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ a = *px;
+ b = *(px+1);
+ px++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ a = *py;
+ b = *(py+1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x0, c0, acc0);
+ acc1 = __SMLADX(x1, c0, acc1);
+ acc2 = __SMLADX(x3, c0, acc2);
+ acc3 = __SMLADX(x2, c0, acc3);
+
+ /* Read y[srcBLen - 7] */
+ c0 = *(py-1);
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ a = *(px+2);
+ b = *(px+3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q15_t)(acc0 >> 15);
+ *pOut++ = (q15_t)(acc1 >> 15);
+ *pOut++ = (q15_t)(acc2 >> 15);
+ *pOut++ = (q15_t)(acc3 >> 15);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = count >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ py++;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ sum += ((q31_t) * px++ * *py--);
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (sum >> 15);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_q31.c
new file mode 100644
index 000000000..3b31583f6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_q31.c
@@ -0,0 +1,604 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_fast_q31.c
+*
+* Description: Fast Q31 Partial convolution.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par
+ * See <code>arm_conv_partial_q31()</code> for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.
+ */
+
+arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x0, x1, x2, x3, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t) check - (int32_t) srcALen);
+ blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[1] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[2] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* x[3] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+ /* acc3 += x[3] * y[srcBLen - 1] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py--);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc3 += x[4] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc3 += x[5] * y[srcBLen - 2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read y[srcBLen - 4] sample */
+ c0 = *(py--);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[srcBLen - 4] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc1 += x[4] * y[srcBLen - 4] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc2 += x[5] * y[srcBLen - 4] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc3 += x[6] * y[srcBLen - 4] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 << 1);
+ *pOut++ = (q31_t) (acc1 << 1);
+ *pOut++ = (q31_t) (acc2 << 1);
+ *pOut++ = (q31_t) (acc3 << 1);
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py--))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = sum << 1;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_opt_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_opt_q15.c
new file mode 100644
index 000000000..412c0eefa
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_opt_q15.c
@@ -0,0 +1,765 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_opt_q15.c
+*
+* Description: Partial convolution of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, state buffers should be aligned by 32-bit
+ *
+ * Refer to <code>arm_conv_partial_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ *
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3; /* Temporary variables to hold state and coefficient values */
+ q31_t y1, y2; /* State variables */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status; /* Status variable */
+ uint32_t tapCnt; /* loop count */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr1, srcALen);
+
+ /* Update pointers */
+ pScr1 += srcALen;
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x1, y1, acc0);
+ acc2 = __SMLALD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = _SIMD32_OFFSET(pScr1);
+
+ /* multiply and accumlate */
+ acc0 = __SMLALD(x2, y2, acc0);
+ acc2 = __SMLALD(x1, y2, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr1 + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read two samples from smaller buffer */
+ y1 = *__SIMD32(pIn2)++;
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+#else
+
+arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch1 */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch1 */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ uint32_t j, k, blkCnt; /* loop counter */
+ arm_status status; /* Status variable */
+ uint32_t tapCnt; /* loop count */
+ q15_t x10, x11, x20, x21; /* Temporary variables to hold srcA buffer */
+ q15_t y10, y11; /* Temporary variables to hold srcB buffer */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2 + srcBLen - 1;
+
+ /* points to smaller length sequence */
+ px = pIn2;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr2-- = *px++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy bigger length sequence(srcALen) samples in scratch1 buffer */
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = py;
+
+ pScratch1 += firstIndex;
+
+ pOut = pDst + firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *pScr1++;
+ x21 = *pScr1++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2;
+ y11 = *(pIn2 + 1u);
+
+ /* multiply and accumlate */
+ acc0 += (q63_t) x10 *y10;
+ acc0 += (q63_t) x11 *y11;
+ acc2 += (q63_t) x20 *y10;
+ acc2 += (q63_t) x21 *y11;
+
+ /* multiply and accumlate */
+ acc1 += (q63_t) x11 *y10;
+ acc1 += (q63_t) x20 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1;
+ x11 = *(pScr1 + 1u);
+
+ /* multiply and accumlate */
+ acc3 += (q63_t) x21 *y10;
+ acc3 += (q63_t) x10 *y11;
+
+ /* Read next two samples from scratch2 buffer */
+ y10 = *(pIn2 + 2u);
+ y11 = *(pIn2 + 3u);
+
+ /* multiply and accumlate */
+ acc0 += (q63_t) x20 *y10;
+ acc0 += (q63_t) x21 *y11;
+ acc2 += (q63_t) x10 *y10;
+ acc2 += (q63_t) x11 *y11;
+ acc1 += (q63_t) x21 *y10;
+ acc1 += (q63_t) x10 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *(pScr1 + 2);
+ x21 = *(pScr1 + 3);
+
+ /* multiply and accumlate */
+ acc3 += (q63_t) x11 *y10;
+ acc3 += (q63_t) x20 *y11;
+
+ /* update scratch pointers */
+ pIn2 += 4u;
+ pScr1 += 4u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2);
+ acc1 += (*pScr1++ * *pIn2);
+ acc2 += (*pScr1++ * *pIn2);
+ acc3 += (*pScr1++ * *pIn2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = __SSAT((acc0 >> 15), 16);
+ *pOut++ = __SSAT((acc1 >> 15), 16);
+ *pOut++ = __SSAT((acc2 >> 15), 16);
+ *pOut++ = __SSAT((acc3 >> 15), 16);
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = numPoints & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read two samples from smaller buffer */
+ y10 = *pIn2++;
+ y11 = *pIn2++;
+
+ /* multiply and accumlate */
+ acc0 += (q63_t) x10 *y10;
+ acc0 += (q63_t) x11 *y11;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_opt_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_opt_q7.c
new file mode 100644
index 000000000..8c277c1e6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_opt_q7.c
@@ -0,0 +1,807 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_opt_q7.c
+*
+* Description: Partial convolution of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ *
+ *
+ */
+
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
+ q15_t x4; /* Temporary input variable */
+ q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* loop counter */
+ q7_t *px; /* Temporary input1 pointer */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t x1, x2, x3, y1; /* Temporary input variables */
+ arm_status status;
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t out0, out1, out2, out3; /* temporary variables */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2;
+
+ /* points to smaller length sequence */
+ px = pIn2 + srcBLen - 1;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = (q7_t *) py;
+
+ pScr2 = py;
+
+ pOut = pDst + firstIndex;
+
+ pScratch1 += firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+ acc0 = __SMLAD(x2, y1, acc0);
+
+ acc2 = __SMLAD(x1, y1, acc2);
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ pScr2 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+ *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+ blkCnt = (numPoints) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read two samples from smaller buffer */
+ y1 = *__SIMD32(pScr2)++;
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+
+ }
+
+ return (status);
+
+}
+
+#else
+
+arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+
+ q15_t *pScr2, *pScr1; /* Intermediate pointers for scratch pointers */
+ q15_t x4; /* Temporary input variable */
+ q7_t *pIn1, *pIn2; /* inputA and inputB pointer */
+ uint32_t j, k, blkCnt, tapCnt; /* loop counter */
+ q7_t *px; /* Temporary input1 pointer */
+ q15_t *py; /* Temporary input2 pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulator */
+ arm_status status;
+ q7_t *pOut = pDst; /* output pointer */
+ q15_t x10, x11, x20, x21; /* Temporary input variables */
+ q15_t y10, y11; /* Temporary input variables */
+ q7_t out0, out1, out2, out3; /* temporary variables */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* pointer to take end of scratch2 buffer */
+ pScr2 = pScratch2;
+
+ /* points to smaller length sequence */
+ px = pIn2 + srcBLen - 1;
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * px--;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Initialze temporary scratch pointer */
+ pScr1 = pScratch1;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Temporary pointer for scratch2 */
+ py = pScratch2;
+
+ /* Initialization of pIn2 pointer */
+ pIn2 = (q7_t *) py;
+
+ pScr2 = py;
+
+ pOut = pDst + firstIndex;
+
+ pScratch1 += firstIndex;
+
+ /* Actual convolution process starts here */
+ blkCnt = (numPoints) >> 2;
+
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *pScr1++;
+ x21 = *pScr1++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y10 = *pScr2;
+ y11 = *(pScr2 + 1u);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+ acc2 += (q31_t) x20 *y10;
+ acc2 += (q31_t) x21 *y11;
+
+
+ acc1 += (q31_t) x11 *y10;
+ acc1 += (q31_t) x20 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1;
+ x11 = *(pScr1 + 1u);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x21 *y10;
+ acc3 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch2 buffer */
+ y10 = *(pScr2 + 2u);
+ y11 = *(pScr2 + 3u);
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x20 *y10;
+ acc0 += (q31_t) x21 *y11;
+ acc2 += (q31_t) x10 *y10;
+ acc2 += (q31_t) x11 *y11;
+ acc1 += (q31_t) x21 *y10;
+ acc1 += (q31_t) x10 *y11;
+
+ /* Read next two samples from scratch1 buffer */
+ x20 = *(pScr1 + 2);
+ x21 = *(pScr1 + 3);
+
+ /* multiply and accumlate */
+ acc3 += (q31_t) x11 *y10;
+ acc3 += (q31_t) x20 *y11;
+
+ /* update scratch pointers */
+
+ pScr1 += 4u;
+ pScr2 += 4u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ out0 = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ out1 = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ out2 = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ out3 = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+
+ *__SIMD32(pOut)++ = __PACKq7(out0, out1, out2, out3);
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+ blkCnt = (numPoints) & 0x3;
+
+ /* Calculate convolution for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read next two samples from scratch1 buffer */
+ x10 = *pScr1++;
+ x11 = *pScr1++;
+
+ /* Read two samples from smaller buffer */
+ y10 = *pScr2++;
+ y11 = *pScr2++;
+
+ /* multiply and accumlate */
+ acc0 += (q31_t) x10 *y10;
+ acc0 += (q31_t) x11 *y11;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ return (status);
+
+}
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q15.c
new file mode 100644
index 000000000..920f8a16f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q15.c
@@ -0,0 +1,779 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_q15.c
+*
+* Description: Partial convolution of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * Refer to <code>arm_conv_partial_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ * \par
+ * Refer the function <code>arm_conv_partial_opt_q15()</code> for a faster implementation of this function using scratch buffers.
+ *
+ */
+
+
+arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary input variables */
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t) check - (int32_t) srcALen);
+ blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2 - 1u;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2u;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLALDX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLALDX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLALDX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLALDX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLALDX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLALDX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALDX(x1, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+
+ c0 = *(py-1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x1, c0, acc0);
+ acc1 = __SMLALD(x2, c0, acc1);
+ acc2 = __SMLALDX(x2, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = count >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t *pIn1 = pSrcA; /* inputA pointer */
+ q15_t *pIn2 = pSrcB; /* inputB pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q31_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q31.c
new file mode 100644
index 000000000..fb97eabfc
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q31.c
@@ -0,0 +1,600 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_q31.c
+*
+* Description: Partial convolution of Q31 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * See <code>arm_conv_partial_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q63_t sum, acc0, acc1, acc2; /* Accumulator */
+ q31_t x0, x1, x2, c0;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
+ arm_status status; /* status of Partial convolution */
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t) check - (int32_t) srcALen);
+ blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[1] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[2] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[3] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blkCnt */
+
+ blkCnt = blockSize2 / 3;
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+
+ /* Apply loop unrolling and compute 3 MACs simultaneously. */
+ k = srcBLen / 3;
+
+ /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py);
+
+ /* Read x[2] sample */
+ x2 = *(px);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += (q63_t) x0 *c0;
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += (q63_t) x1 *c0;
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += (q63_t) x2 *c0;
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py - 1u);
+
+ /* Read x[3] sample */
+ x0 = *(px + 1u);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += (q63_t) x1 *c0;
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += (q63_t) x2 *c0;
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += (q63_t) x0 *c0;
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py - 2u);
+
+ /* Read x[4] sample */
+ x1 = *(px + 2u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += (q63_t) x2 *c0;
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += (q63_t) x0 *c0;
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += (q63_t) x1 *c0;
+
+
+ px += 3u;
+
+ py -= 3u;
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen - (3 * (srcBLen / 3));
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += (q63_t) x0 *c0;
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += (q63_t) x1 *c0;
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += (q63_t) x2 *c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 >> 31);
+ *pOut++ = (q31_t) (acc1 >> 31);
+ *pOut++ = (q31_t) (acc2 >> 31);
+
+ /* Increment the pointer pIn1 index, count by 3 */
+ count += 3u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t *pIn1 = pSrcA; /* inputA pointer */
+ q31_t *pIn2 = pSrcB; /* inputB pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q31_t) (sum >> 31u);
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q7.c
new file mode 100644
index 000000000..6eea774ad
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_q7.c
@@ -0,0 +1,734 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_partial_q7.c
+*
+* Description: Partial convolution of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup PartialConv
+ * @{
+ */
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ *
+ * \par
+ * Refer the function <code>arm_conv_partial_opt_q7()</code> for a faster implementation of this function.
+ *
+ */
+
+arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t *pIn1; /* inputA pointer */
+ q7_t *pIn2; /* inputB pointer */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t *px; /* Intermediate inputA pointer */
+ q7_t *py; /* Intermediate inputB pointer */
+ q7_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t input1, input2;
+ q15_t in1, in2;
+ q7_t x0, x1, x2, x3, c0, c1;
+ uint32_t j, k, count, check, blkCnt;
+ int32_t blockSize1, blockSize2, blockSize3; /* loop counter */
+ arm_status status;
+
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_MATH_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* Conditions to check which loopCounter holds
+ * the first and last indices of the output samples to be calculated. */
+ check = firstIndex + numPoints;
+ blockSize3 = ((int32_t) check - (int32_t) srcALen);
+ blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+ blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+ blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+ (int32_t) numPoints) : 0;
+ blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+ (int32_t) firstIndex);
+ blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* Set the output pointer to point to the firstIndex
+ * of the output sample to be calculated. */
+ pOut = pDst + firstIndex;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed.
+ Since the partial convolution starts from from firstIndex
+ Number of Macs to be performed is firstIndex + 1 */
+ count = 1u + firstIndex;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + firstIndex;
+ py = pSrc2;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] , x[1] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 1] , y[srcBLen - 2] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[0] * y[srcBLen - 1] */
+ /* x[1] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[2] , x[3] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 3] , y[srcBLen - 4] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[2] * y[srcBLen - 3] */
+ /* x[3] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = ++pSrc2;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 2] sample */
+ c1 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* x[0] and x[1] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 1] and y[srcBLen - 2] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[1] and x[2] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 4] sample */
+ c1 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[4] and x[5] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* x[5] and x[6] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += ((q31_t) x0 * c0);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += ((q31_t) x1 * c0);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += ((q31_t) x2 * c0);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += ((q31_t) x3 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));
+ *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = (uint32_t) blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum += ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q7_t *pIn1 = pSrcA; /* inputA pointer */
+ q7_t *pIn2 = pSrcB; /* inputB pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counters */
+ arm_status status; /* status of Partial convolution */
+
+ /* Check for range of output samples to be calculated */
+ if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+ {
+ /* Set status as ARM_ARGUMENT_ERROR */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Loop to calculate convolution for output length number of values */
+ for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q15_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+ }
+ /* set status as ARM_SUCCESS as there are no argument errors */
+ status = ARM_MATH_SUCCESS;
+ }
+ return (status);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of PartialConv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q15.c
new file mode 100644
index 000000000..d4daec59e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q15.c
@@ -0,0 +1,734 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_q15.c
+*
+* Description: Convolution of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ * \par
+ * Refer to <code>arm_conv_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ * \par
+ * Refer the function <code>arm_conv_opt_q15()</code> for a faster implementation of this function using scratch buffers.
+ *
+ */
+
+void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q63_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations less than 4 */
+ /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ while((count < 4u) && (blockSize1 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over number of MAC operations between
+ * inputA samples and inputB samples */
+ k = count;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* The second part of the stage starts here */
+ /* The internal loop, over count, is unrolled by 4 */
+ /* To, read the last two inputB samples using SIMD:
+ * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+ py = py - 1;
+
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + (count - 1u);
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is the index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+
+ /* --------------------
+ * Stage2 process
+ * -------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ py = py - 1u;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px+1);
+ px+= 2u;
+
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the last two inputB samples using SIMD:
+ * y[srcBLen - 1] and y[srcBLen - 2] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLALDX(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px+1);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLALDX(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLALDX(x3, c0, acc3);
+
+ /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+ c0 = *__SIMD32(py)--;
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLALDX(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLALDX(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px+2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px+3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLALDX(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[srcBLen - 5] */
+ c0 = *(py+1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALDX(x1, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[srcBLen - 5], y[srcBLen - 6] */
+ c0 = _SIMD32_OFFSET(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px+1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x0, c0, acc0);
+ acc1 = __SMLALDX(x1, c0, acc1);
+ acc2 = __SMLALDX(x3, c0, acc2);
+ acc3 = __SMLALDX(x2, c0, acc3);
+
+ c0 = *(py-1);
+
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px+2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x1, c0, acc0);
+ acc1 = __SMLALD(x2, c0, acc1);
+ acc2 = __SMLALDX(x2, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pOut)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) ((q31_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ blockSize3 = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ pIn2 = pSrc2 - 1u;
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ /* For loop unrolling by 4, this stage is divided into two. */
+ /* First part of this stage computes the MAC operations greater than 4 */
+ /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+ /* The first part of the stage starts here */
+ j = blockSize3 >> 2u;
+
+ while((j > 0u) && (blockSize3 > 0u))
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied
+ * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+ /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied
+ * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+ sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* For the next MAC operations, the pointer py is used without SIMD
+ * So, py is incremented by 1 */
+ py = py + 1u;
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+
+ j--;
+ }
+
+ /* The second part of the stage starts here */
+ /* SIMD is not used for the next MAC operations,
+ * so pointer py is updated to read only one sample at a time */
+ py = py + 1u;
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen-1] * y[srcBLen-1] */
+ sum = __SMLALD(*px++, *py--, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ q15_t *pIn1 = pSrcA; /* input pointer */
+ q15_t *pIn2 = pSrcB; /* coefficient pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < (srcALen + srcBLen - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += (q31_t) pIn1[j] * (pIn2[i - j]);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+ }
+
+#endif /* #if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)*/
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q31.c
new file mode 100644
index 000000000..c5ce68e97
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q31.c
@@ -0,0 +1,565 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_q31.c
+*
+* Description: Convolution of Q31 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_conv_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q63_t sum; /* Accumulator */
+ q63_t acc0, acc1, acc2; /* Accumulator */
+ q31_t x0, x1, x2, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (q31_t *) pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = (q31_t *) pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[1] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[2] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py--);
+ /* x[3] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll by 3 */
+ blkCnt = blockSize2 / 3;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+
+ /* Apply loop unrolling and compute 3 MACs simultaneously. */
+ k = srcBLen / 3;
+
+ /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py);
+
+ /* Read x[3] sample */
+ x2 = *(px);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[0] * y[srcBLen - 1] */
+ acc0 += ((q63_t) x0 * c0);
+ /* acc1 += x[1] * y[srcBLen - 1] */
+ acc1 += ((q63_t) x1 * c0);
+ /* acc2 += x[2] * y[srcBLen - 1] */
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Read y[srcBLen - 2] sample */
+ c0 = *(py - 1u);
+
+ /* Read x[4] sample */
+ x0 = *(px + 1u);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[srcBLen - 2] */
+ acc0 += ((q63_t) x1 * c0);
+ /* acc1 += x[2] * y[srcBLen - 2] */
+ acc1 += ((q63_t) x2 * c0);
+ /* acc2 += x[3] * y[srcBLen - 2] */
+ acc2 += ((q63_t) x0 * c0);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py - 2u);
+
+ /* Read x[5] sample */
+ x1 = *(px + 2u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[srcBLen - 3] */
+ acc0 += ((q63_t) x2 * c0);
+ /* acc1 += x[3] * y[srcBLen - 2] */
+ acc1 += ((q63_t) x0 * c0);
+ /* acc2 += x[4] * y[srcBLen - 2] */
+ acc2 += ((q63_t) x1 * c0);
+
+ /* update scratch pointers */
+ px += 3u;
+ py -= 3u;
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen - (3 * (srcBLen / 3));
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += ((q63_t) x0 * c0);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += ((q63_t) x1 * c0);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut++ = (q31_t) (acc0 >> 31);
+ *pOut++ = (q31_t) (acc1 >> 31);
+ *pOut++ = (q31_t) (acc2 >> 31);
+
+ /* Increment the pointer pIn1 index, count by 3 */
+ count += 3u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py--);
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py--);
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py--);
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q31_t) (sum >> 31);
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t *pIn1 = pSrcA; /* input pointer */
+ q31_t *pIn2 = pSrcB; /* coefficient pointer */
+ q63_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < (srcALen + srcBLen - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q31_t) (sum >> 31u);
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q7.c
new file mode 100644
index 000000000..ab7b12f30
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_q7.c
@@ -0,0 +1,690 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_conv_q7.c
+*
+* Description: Convolution of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Conv
+ * @{
+ */
+
+/**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as <code>max(srcALen, srcBLen)<131072</code>.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.
+ *
+ * \par
+ * Refer the function <code>arm_conv_opt_q7()</code> for a faster implementation of this function.
+ *
+ */
+
+void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t *pIn1; /* inputA pointer */
+ q7_t *pIn2; /* inputB pointer */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t *px; /* Intermediate inputA pointer */
+ q7_t *py; /* Intermediate inputB pointer */
+ q7_t *pSrc1, *pSrc2; /* Intermediate pointers */
+ q7_t x0, x1, x2, x3, c0, c1; /* Temporary variables to hold state and coefficient values */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulator */
+ q31_t input1, input2; /* Temporary input variables */
+ q15_t in1, in2; /* Temporary input variables */
+ uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3; /* loop counter */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+ }
+
+ /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+ /* The function is internally
+ * divided into three stages according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first stage of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second stage of the algorithm, srcBLen number of multiplications are done.
+ * In the third stage of the algorithm, the multiplications decrease by one
+ * for every iteration. */
+
+ /* The algorithm is implemented in three stages.
+ The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = (srcALen - srcBLen) + 1u;
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[0]
+ * sum = x[0] * y[1] + x[1] * y[0]
+ * ....
+ * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] , x[1] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* y[srcBLen - 1] , y[srcBLen - 2] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* x[0] * y[srcBLen - 1] */
+ /* x[1] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[2] , x[3] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* y[srcBLen - 3] , y[srcBLen - 4] */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* x[2] * y[srcBLen - 3] */
+ /* x[3] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pIn2 + count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]
+ * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[srcBLen - 1] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 2] sample */
+ c1 = *(py--);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* x[0] and x[1] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* y[srcBLen - 1] and y[srcBLen - 2] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[1] and x[2] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ /* Read y[srcBLen - 3] sample */
+ c0 = *(py--);
+ /* Read y[srcBLen - 4] sample */
+ c1 = *(py--);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[4] and x[5] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* x[5] and x[6] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[srcBLen - 5] sample */
+ c0 = *(py--);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[srcBLen - 5] */
+ acc0 += ((q15_t) x0 * c0);
+ /* acc1 += x[5] * y[srcBLen - 5] */
+ acc1 += ((q15_t) x1 * c0);
+ /* acc2 += x[6] * y[srcBLen - 5] */
+ acc2 += ((q15_t) x2 * c0);
+ /* acc3 += x[7] * y[srcBLen - 5] */
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* srcBLen number of MACS should be performed */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]
+ * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]
+ * ....
+ * sum += x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]
+ * sum += x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The blockSize3 variable holds the number of MAC operations performed */
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ pSrc2 = pIn2 + (srcBLen - 1u);
+ py = pSrc2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = blockSize3 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+ /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+ in1 = (q15_t) * py--;
+ in2 = (q15_t) * py--;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+ /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = blockSize3 % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py--);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pSrc2;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q7_t *pIn1 = pSrcA; /* input pointer */
+ q7_t *pIn2 = pSrcB; /* coefficient pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i, j; /* loop counter */
+
+ /* Loop to calculate output of convolution for output length number of times */
+ for (i = 0; i < (srcALen + srcBLen - 1); i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if(((i - j) < srcBLen) && (j < srcALen))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += (q15_t) pIn1[j] * (pIn2[i - j]);
+ }
+ }
+
+ /* Store the output in the destination buffer */
+ pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Conv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_f32.c
new file mode 100644
index 000000000..317120906
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_f32.c
@@ -0,0 +1,739 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_f32.c
+*
+* Description: Correlation of floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup Corr Correlation
+ *
+ * Correlation is a mathematical operation that is similar to convolution.
+ * As with convolution, correlation uses two signals to produce a third signal.
+ * The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution.
+ * Correlation is commonly used to measure the similarity between two signals.
+ * It has applications in pattern recognition, cryptanalysis, and searching.
+ * The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types.
+ * Fast versions of the Q15 and Q31 functions are also provided.
+ *
+ * \par Algorithm
+ * Let <code>a[n]</code> and <code>b[n]</code> be sequences of length <code>srcALen</code> and <code>srcBLen</code> samples respectively.
+ * The convolution of the two signals is denoted by
+ * <pre>
+ * c[n] = a[n] * b[n]
+ * </pre>
+ * In correlation, one of the signals is flipped in time
+ * <pre>
+ * c[n] = a[n] * b[-n]
+ * </pre>
+ *
+ * \par
+ * and this is mathematically defined as
+ * \image html CorrelateEquation.gif
+ * \par
+ * The <code>pSrcA</code> points to the first input vector of length <code>srcALen</code> and <code>pSrcB</code> points to the second input vector of length <code>srcBLen</code>.
+ * The result <code>c[n]</code> is of length <code>2 * max(srcALen, srcBLen) - 1</code> and is defined over the interval <code>n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2)</code>.
+ * The output result is written to <code>pDst</code> and the calling function must allocate <code>2 * max(srcALen, srcBLen) - 1</code> words for the result.
+ *
+ * <b>Note</b>
+ * \par
+ * The <code>pDst</code> should be initialized to all zeros before being used.
+ *
+ * <b>Fixed-Point Behavior</b>
+ * \par
+ * Correlation requires summing up a large number of intermediate products.
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.
+ * Refer to the function specific documentation below for further details of the particular algorithm used.
+ *
+ *
+ * <b>Fast Versions</b>
+ *
+ * \par
+ * Fast versions are supported for Q31 and Q15. Cycles for Fast versions are less compared to Q31 and Q15 of correlate and the design requires
+ * the input signals should be scaled down to avoid intermediate overflows.
+ *
+ *
+ * <b>Opt Versions</b>
+ *
+ * \par
+ * Opt versions are supported for Q15 and Q7. Design uses internal scratch buffer for getting good optimisation.
+ * These versions are optimised in cycles and consumes more memory(Scratch memory) compared to Q15 and Q7 versions of correlate
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+/**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t *pIn1; /* inputA pointer */
+ float32_t *pIn2; /* inputB pointer */
+ float32_t *pOut = pDst; /* output pointer */
+ float32_t *px; /* Intermediate inputA pointer */
+ float32_t *py; /* Intermediate inputB pointer */
+ float32_t *pSrc1; /* Intermediate pointers */
+ float32_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ float32_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counters */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcA;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcB;
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding has to be done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ //while(j > 0u)
+ //{
+ // /* Zero is stored in the destination buffer */
+ // *pOut++ = 0.0f;
+
+ // /* Decrement the loop counter */
+ // j--;
+ //}
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization of inputB pointer */
+ pIn2 = pSrcA;
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] */
+ sum += *px++ * *py++;
+ /* x[1] * y[srcBLen - 3] */
+ sum += *px++ * *py++;
+ /* x[2] * y[srcBLen - 2] */
+ sum += *px++ * *py++;
+ /* x[3] * y[srcBLen - 1] */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ /* x[0] * y[srcBLen - 1] */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *(py++);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[0] */
+ acc0 += x0 * c0;
+ /* acc1 += x[1] * y[0] */
+ acc1 += x1 * c0;
+ /* acc2 += x[2] * y[0] */
+ acc2 += x2 * c0;
+ /* acc3 += x[3] * y[0] */
+ acc3 += x3 * c0;
+
+ /* Read y[1] sample */
+ c0 = *(py++);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[1] * y[1] */
+ acc0 += x1 * c0;
+ /* acc1 += x[2] * y[1] */
+ acc1 += x2 * c0;
+ /* acc2 += x[3] * y[1] */
+ acc2 += x3 * c0;
+ /* acc3 += x[4] * y[1] */
+ acc3 += x0 * c0;
+
+ /* Read y[2] sample */
+ c0 = *(py++);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[2] */
+ acc0 += x2 * c0;
+ /* acc1 += x[3] * y[2] */
+ acc1 += x3 * c0;
+ /* acc2 += x[4] * y[2] */
+ acc2 += x0 * c0;
+ /* acc3 += x[5] * y[2] */
+ acc3 += x1 * c0;
+
+ /* Read y[3] sample */
+ c0 = *(py++);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[3] */
+ acc0 += x3 * c0;
+ /* acc1 += x[4] * y[3] */
+ acc1 += x0 * c0;
+ /* acc2 += x[5] * y[3] */
+ acc2 += x1 * c0;
+ /* acc3 += x[6] * y[3] */
+ acc3 += x2 * c0;
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[4] sample */
+ c0 = *(py++);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 += x0 * c0;
+ /* acc1 += x[5] * y[4] */
+ acc1 += x1 * c0;
+ /* acc2 += x[6] * y[4] */
+ acc2 += x2 * c0;
+ /* acc3 += x[7] * y[4] */
+ acc3 += x3 * c0;
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = acc0;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = acc1;
+ pOut += inc;
+
+ *pOut = acc2;
+ pOut += inc;
+
+ *pOut = acc3;
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py++;
+ sum += *px++ * *py++;
+ sum += *px++ * *py++;
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0.0f;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum += *px++ * *py++;
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum += *px++ * *py++;
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum += *px++ * *py++;
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += *px++ * *py++;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pIn1 = pSrcA; /* inputA pointer */
+ float32_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
+ float32_t sum; /* Accumulator */
+ uint32_t i = 0u, j; /* loop counters */
+ uint32_t inv = 0u; /* Reverse order flag */
+ uint32_t tot = 0u; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and a varaible, inv is set to 1 */
+ /* If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we include zeroes
+ * in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer */
+ /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer */
+ /* Once the zero padding is done the remaining of the output is calcualted
+ * using convolution but with the shorter signal time shifted. */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2u);
+
+ if(srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if(srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1u);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0u; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0.0f;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += pIn1[j] * pIn2[-((int32_t) i - j)];
+ }
+ }
+ /* Store the output in the destination buffer */
+ if(inv == 1)
+ *pDst-- = sum;
+ else
+ *pDst++ = sum;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_opt_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_opt_q15.c
new file mode 100644
index 000000000..bd600765a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_opt_q15.c
@@ -0,0 +1,512 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_fast_opt_q15.c
+*
+* Description: Fast Q15 Correlation.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ *
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch buffers should be aligned by 32-bit
+ *
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_correlate_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch)
+{
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *py; /* Intermediate inputB pointer */
+ q31_t x1, x2, x3; /* temporary variables for holding input and coefficient values */
+ uint32_t j, blkCnt, outBlockSize; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+ uint32_t tapCnt;
+ q31_t y1, y2;
+ q15_t *pScr; /* Intermediate pointers */
+ q15_t *pOut = pDst; /* output pointer */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ pScr = pScratch;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr += (srcBLen - 1u);
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr, srcALen);
+
+ /* Update pointers */
+ pScr += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ j = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ j = srcALen % 0x4u;
+
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+ j = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr++ = 0;
+ *pScr++ = 0;
+ *pScr++ = 0;
+ *pScr++ = 0;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ j = (srcBLen - 1u) % 0x4u;
+
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr++ = 0;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Temporary pointer for scratch2 */
+ py = pIn2;
+
+
+ /* Actual correlation process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read four samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr)++;
+
+ /* Read next four samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x1 = _SIMD32_OFFSET(pScr);
+
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x1, y1, acc0);
+
+ acc2 = __SMLAD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ a = *pScr;
+ b = *(pScr + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLAD(x2, y2, acc0);
+
+ acc2 = __SMLAD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ acc1 = __SMLADX(x3, y2, acc1);
+
+ a = *(pScr + 2);
+ b = *(pScr + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ pIn2 += 4u;
+
+ pScr += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr++ * *pIn2);
+ acc1 += (*pScr++ * *pIn2);
+ acc2 += (*pScr++ * *pIn2);
+ acc3 += (*pScr++ * *pIn2++);
+
+ pScr -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut = (__SSAT(acc0 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc1 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc2 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc3 >> 15u, 16));
+ pOut += inc;
+
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate correlation for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ acc0 += (*pScr++ * *pIn2++);
+ acc0 += (*pScr++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+
+ *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 1u;
+
+ }
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_q15.c
new file mode 100644
index 000000000..184492f87
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_q15.c
@@ -0,0 +1,1319 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_fast_q15.c
+*
+* Description: Fast Q15 Correlation.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_correlate_q15()</code> for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.
+ */
+
+void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+ /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum = __SMLAD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px + 1);
+ px += 2u;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the first two inputB samples using SIMD:
+ * y[0] and y[1] */
+ c0 = *__SIMD32(py)++;
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px + 1);
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLAD(x3, c0, acc3);
+
+ /* Read y[2] and y[3] */
+ c0 = *__SIMD32(py)++;
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLAD(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLAD(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px + 2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px + 3);
+ px += 4u;
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLAD(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLAD(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[4] */
+ c0 = *py;
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[4], y[5] */
+ c0 = *__SIMD32(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px + 1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[4], y[5] */
+ c0 = *__SIMD32(py)++;
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px + 1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+
+ c0 = (*py);
+ /* Read y[6] */
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px + 2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (acc0 >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q15_t) (acc1 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc2 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc3 >> 15);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+ /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+ q15_t a, b;
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 2u;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the first two inputB samples using SIMD:
+ * y[0] and y[1] */
+ a = *py;
+ b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Read x[2], x[3], x[4] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x2 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(b, a, 16);
+
+#else
+
+ x2 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x3 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLAD(x3, c0, acc3);
+
+ /* Read y[2] and y[3] */
+ a = *(py + 2);
+ b = *(py + 3);
+
+ py += 4u;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLAD(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLAD(x3, c0, acc1);
+
+ /* Read x[4], x[5], x[6] */
+ a = *(px + 2);
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x0 = __PKHBT(a, b, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(b, a, 16);
+
+#else
+
+ x0 = __PKHBT(b, a, 16);
+ a = *(px + 4);
+ x1 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 4u;
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLAD(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLAD(x1, c0, acc3);
+
+ } while(--k);
+
+ /* For the next MAC operations, SIMD is not used
+ * So, the 16 bit pointer if inputB, py is updated */
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[4] */
+ c0 = *py;
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7] */
+ a = *px;
+ b = *(px + 1);
+
+ px++;;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLADX(x1, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[4], y[5] */
+ a = *py;
+ b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[4], y[5] */
+ a = *py;
+ b = *(py + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ c0 = __PKHBT(a, b, 16);
+
+#else
+
+ c0 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ py += 2u;
+
+ /* Read x[7], x[8], x[9] */
+ a = *px;
+ b = *(px + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(b, a, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+ a = *(px + 2);
+ x2 = __PKHBT(a, b, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+ acc2 = __SMLAD(x3, c0, acc2);
+ acc3 = __SMLAD(x2, c0, acc3);
+
+ c0 = (*py);
+ /* Read y[6] */
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+
+ /* Read x[10] */
+ b = *(px + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ x3 = __PKHBT(a, b, 16);
+
+#else
+
+ x3 = __PKHBT(b, a, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLADX(x1, c0, acc0);
+ acc1 = __SMLAD(x2, c0, acc1);
+ acc2 = __SMLADX(x2, c0, acc2);
+ acc3 = __SMLADX(x3, c0, acc3);
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (acc0 >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q15_t) (acc1 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc2 >> 15);
+ pOut += inc;
+
+ *pOut = (q15_t) (acc3 >> 15);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q31_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (sum >> 15);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_q31.c
new file mode 100644
index 000000000..b86f55080
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_fast_q31.c
@@ -0,0 +1,612 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_fast_q31.c
+*
+* Description: Fast Q31 Correlation.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ *
+ * \par
+ * See <code>arm_correlate_q31()</code> for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.
+ */
+
+void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* x[1] * y[srcBLen - 3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* x[2] * y[srcBLen - 2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* x[3] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *(py++);
+
+ /* Read x[3] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[0] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[1] * y[0] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[2] * y[0] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[3] * y[0] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Read y[1] sample */
+ c0 = *(py++);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[1] * y[1] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc1 += x[2] * y[1] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc2 += x[3] * y[1] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc3 += x[4] * y[1] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read y[2] sample */
+ c0 = *(py++);
+
+ /* Read x[5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[2] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc1 += x[3] * y[2] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc2 += x[4] * y[2] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc3 += x[5] * y[2] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read y[3] sample */
+ c0 = *(py++);
+
+ /* Read x[6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[3] * y[3] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+ /* acc1 += x[4] * y[3] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc2 += x[5] * y[3] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc3 += x[6] * y[3] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[4] sample */
+ c0 = *(py++);
+
+ /* Read x[7] sample */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ /* acc1 += x[5] * y[4] */
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+ /* acc2 += x[6] * y[4] */
+ acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+ /* acc3 += x[7] * y[4] */
+ acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (acc0 << 1);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q31_t) (acc1 << 1);
+ pOut += inc;
+
+ *pOut = (q31_t) (acc2 << 1);
+ pOut += inc;
+
+ *pOut = (q31_t) (acc3 << 1);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 4 */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1u;
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * px++ * (*py++))) >> 32);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = sum << 1;
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_opt_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_opt_q15.c
new file mode 100644
index 000000000..bb236d818
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_opt_q15.c
@@ -0,0 +1,513 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_opt_q15.c
+*
+* Description: Correlation of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch buffers should be aligned by 32-bit
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ * \par
+ * Refer to <code>arm_correlate_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ *
+ */
+
+
+void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch)
+{
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *py; /* Intermediate inputB pointer */
+ q31_t x1, x2, x3; /* temporary variables for holding input1 and input2 values */
+ uint32_t j, blkCnt, outBlockSize; /* loop counter */
+ int32_t inc = 1; /* output pointer increment */
+ uint32_t tapCnt;
+ q31_t y1, y2;
+ q15_t *pScr; /* Intermediate pointers */
+ q15_t *pOut = pDst; /* output pointer */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+
+ q15_t a, b;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ pScr = pScratch;
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr += (srcBLen - 1u);
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Copy (srcALen) samples in scratch buffer */
+ arm_copy_q15(pIn1, pScr, srcALen);
+
+ /* Update pointers */
+ //pIn1 += srcALen;
+ pScr += srcALen;
+
+#else
+
+ /* Apply loop unrolling and do 4 Copies simultaneously. */
+ j = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+ *pScr++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ j = srcALen % 0x4u;
+
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr++ = *pIn1++;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+ j = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr++ = 0;
+ *pScr++ = 0;
+ *pScr++ = 0;
+ *pScr++ = 0;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ j = (srcBLen - 1u) % 0x4u;
+
+ while(j > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr++ = 0;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Temporary pointer for scratch2 */
+ py = pIn2;
+
+
+ /* Actual correlation process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read four samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr)++;
+
+ /* Read next four samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pIn2);
+ y2 = _SIMD32_OFFSET(pIn2 + 2u);
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ x1 = _SIMD32_OFFSET(pScr);
+
+ acc0 = __SMLALD(x2, y2, acc0);
+
+ acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ x2 = _SIMD32_OFFSET(pScr + 2u);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+#else
+
+ /* Read four samples from smaller buffer */
+ a = *pIn2;
+ b = *(pIn2 + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ y1 = __PKHBT(a, b, 16);
+#else
+ y1 = __PKHBT(b, a, 16);
+#endif
+
+ a = *(pIn2 + 2);
+ b = *(pIn2 + 3);
+#ifndef ARM_MATH_BIG_ENDIAN
+ y2 = __PKHBT(a, b, 16);
+#else
+ y2 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLALD(x1, y1, acc0);
+
+ acc2 = __SMLALD(x2, y1, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc1 = __SMLALDX(x3, y1, acc1);
+
+ a = *pScr;
+ b = *(pScr + 1);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(a, b, 16);
+#else
+ x1 = __PKHBT(b, a, 16);
+#endif
+
+ acc0 = __SMLALD(x2, y2, acc0);
+
+ acc2 = __SMLALD(x1, y2, acc2);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y1, acc3);
+
+ acc1 = __SMLALDX(x3, y2, acc1);
+
+ a = *(pScr + 2);
+ b = *(pScr + 3);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x2 = __PKHBT(a, b, 16);
+#else
+ x2 = __PKHBT(b, a, 16);
+#endif
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLALDX(x3, y2, acc3);
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ pIn2 += 4u;
+
+ pScr += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr++ * *pIn2);
+ acc1 += (*pScr++ * *pIn2);
+ acc2 += (*pScr++ * *pIn2);
+ acc3 += (*pScr++ * *pIn2++);
+
+ pScr -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+
+ /* Store the results in the accumulators in the destination buffer. */
+ *pOut = (__SSAT(acc0 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc1 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc2 >> 15u, 16));
+ pOut += inc;
+ *pOut = (__SSAT(acc3 >> 15u, 16));
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate correlation for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr = pScratch;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ acc0 += (*pScr++ * *pIn2++);
+ acc0 += (*pScr++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr++ * *pIn2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pIn2 = py;
+
+ pScratch += 1u;
+
+ }
+
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_opt_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_opt_q7.c
new file mode 100644
index 000000000..adaea59d7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_opt_q7.c
@@ -0,0 +1,464 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_opt_q7.c
+*
+* Description: Correlation of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ *
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, scratch1 and scratch2 buffers should be aligned by 32-bit
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as <code>max(srcALen, srcBLen)<131072</code>.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.
+ *
+ *
+ */
+
+
+
+void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2)
+{
+ q7_t *pOut = pDst; /* output pointer */
+ q15_t *pScr1 = pScratch1; /* Temporary pointer for scratch */
+ q15_t *pScr2 = pScratch2; /* Temporary pointer for scratch */
+ q7_t *pIn1; /* inputA pointer */
+ q7_t *pIn2; /* inputB pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ uint32_t j, k = 0u, blkCnt; /* loop counter */
+ int32_t inc = 1; /* output pointer increment */
+ uint32_t outBlockSize; /* loop counter */
+ q15_t x4; /* Temporary input variable */
+ uint32_t tapCnt; /* loop counter */
+ q31_t x1, x2, x3, y1; /* Temporary input variables */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+
+ /* Copy (srcBLen) samples in scratch buffer */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn2++;
+ *pScr2++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Fill (srcBLen - 1u) zeros in scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update temporary scratch pointer */
+ pScr1 += (srcBLen - 1u);
+
+ /* Copy (srcALen) samples in scratch buffer */
+ k = srcALen >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = srcALen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ x4 = (q15_t) * pIn1++;
+ *pScr1++ = x4;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Fill (srcBLen - 1u) zeros at end of scratch buffer */
+ arm_fill_q15(0, pScr1, (srcBLen - 1u));
+
+ /* Update pointer */
+ pScr1 += (srcBLen - 1u);
+
+#else
+
+/* Apply loop unrolling and do 4 Copies simultaneously. */
+ k = (srcBLen - 1u) >> 2u;
+
+ /* First part of the processing with loop unrolling copies 4 data points at a time.
+ ** a second loop below copies for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner */
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, copy remaining samples here.
+ ** No loop unrolling is used. */
+ k = (srcBLen - 1u) % 0x4u;
+
+ while(k > 0u)
+ {
+ /* copy second buffer in reversal manner for remaining samples */
+ *pScr1++ = 0;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Temporary pointer for second sequence */
+ py = pScratch2;
+
+ /* Initialization of pScr2 pointer */
+ pScr2 = pScratch2;
+
+ /* Actual correlation process starts here */
+ blkCnt = (srcALen + srcBLen - 1u) >> 2;
+
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Read two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* Read next two samples from scratch1 buffer */
+ x2 = *__SIMD32(pScr1)++;
+
+ tapCnt = (srcBLen) >> 2u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2);
+
+ /* multiply and accumlate */
+ acc0 = __SMLAD(x1, y1, acc0);
+ acc2 = __SMLAD(x2, y1, acc2);
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ /* multiply and accumlate */
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ /* Read next two samples from scratch1 buffer */
+ x1 = *__SIMD32(pScr1)++;
+
+ /* pack input data */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x1, x2, 0);
+#else
+ x3 = __PKHBT(x2, x1, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ /* Read four samples from smaller buffer */
+ y1 = _SIMD32_OFFSET(pScr2 + 2u);
+
+ acc0 = __SMLAD(x2, y1, acc0);
+
+ acc2 = __SMLAD(x1, y1, acc2);
+
+ acc1 = __SMLADX(x3, y1, acc1);
+
+ x2 = *__SIMD32(pScr1)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+ x3 = __PKHBT(x2, x1, 0);
+#else
+ x3 = __PKHBT(x1, x2, 0);
+#endif
+
+ acc3 = __SMLADX(x3, y1, acc3);
+
+ pScr2 += 4u;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+
+ /* Update scratch pointer for remaining samples of smaller length sequence */
+ pScr1 -= 4u;
+
+
+ /* apply same above for remaining samples of smaller length sequence */
+ tapCnt = (srcBLen) & 3u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2);
+ acc1 += (*pScr1++ * *pScr2);
+ acc2 += (*pScr1++ * *pScr2);
+ acc3 += (*pScr1++ * *pScr2++);
+
+ pScr1 -= 3u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
+ pOut += inc;
+ *pOut = (q7_t) (__SSAT(acc1 >> 7u, 8));
+ pOut += inc;
+ *pOut = (q7_t) (__SSAT(acc2 >> 7u, 8));
+ pOut += inc;
+ *pOut = (q7_t) (__SSAT(acc3 >> 7u, 8));
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 4u;
+
+ }
+
+
+ blkCnt = (srcALen + srcBLen - 1u) & 0x3;
+
+ /* Calculate correlation for remaining samples of Bigger length sequence */
+ while(blkCnt > 0)
+ {
+ /* Initialze temporary scratch pointer as scratch1 */
+ pScr1 = pScratch1;
+
+ /* Clear Accumlators */
+ acc0 = 0;
+
+ tapCnt = (srcBLen) >> 1u;
+
+ while(tapCnt > 0u)
+ {
+ acc0 += (*pScr1++ * *pScr2++);
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (srcBLen) & 1u;
+
+ /* apply same above for remaining samples of smaller length sequence */
+ while(tapCnt > 0u)
+ {
+
+ /* accumlate the results */
+ acc0 += (*pScr1++ * *pScr2++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ blkCnt--;
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(acc0 >> 7u, 8));
+
+ pOut += inc;
+
+ /* Initialization of inputB pointer */
+ pScr2 = py;
+
+ pScratch1 += 1u;
+
+ }
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q15.c
new file mode 100644
index 000000000..7f861b35c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q15.c
@@ -0,0 +1,719 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_q15.c
+*
+* Description: Correlation of Q15 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * This approach provides 33 guard bits and there is no risk of overflow.
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.
+ *
+ * \par
+ * Refer to <code>arm_correlate_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ * \par
+ * Refer the function <code>arm_correlate_opt_q15()</code> for a faster implementation of this function using scratch buffers.
+ *
+ */
+
+void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst)
+{
+
+#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE)
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pIn1; /* inputA pointer */
+ q15_t *pIn2; /* inputB pointer */
+ q15_t *pOut = pDst; /* output pointer */
+ q63_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *px; /* Intermediate inputA pointer */
+ q15_t *py; /* Intermediate inputB pointer */
+ q15_t *pSrc1; /* Intermediate pointers */
+ q31_t x0, x1, x2, x3, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first loop starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+ sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+ /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+ sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum = __SMLALD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *__SIMD32(px);
+ /* read x[1], x[2] samples */
+ x1 = _SIMD32_OFFSET(px + 1);
+ px += 2u;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read the first two inputB samples using SIMD:
+ * y[0] and y[1] */
+ c0 = *__SIMD32(py)++;
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Read x[2], x[3] */
+ x2 = *__SIMD32(px);
+
+ /* Read x[3], x[4] */
+ x3 = _SIMD32_OFFSET(px + 1);
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLALD(x2, c0, acc2);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLALD(x3, c0, acc3);
+
+ /* Read y[2] and y[3] */
+ c0 = *__SIMD32(py)++;
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLALD(x2, c0, acc0);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLALD(x3, c0, acc1);
+
+ /* Read x[4], x[5] */
+ x0 = _SIMD32_OFFSET(px + 2);
+
+ /* Read x[5], x[6] */
+ x1 = _SIMD32_OFFSET(px + 3);
+
+ px += 4u;
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLALD(x0, c0, acc2);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLALD(x1, c0, acc3);
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ if(k == 1u)
+ {
+ /* Read y[4] */
+ c0 = *py;
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+
+#else
+
+ c0 = c0 & 0x0000FFFF;
+
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+ /* Read x[7] */
+ x3 = *__SIMD32(px);
+ px++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALDX(x1, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ if(k == 2u)
+ {
+ /* Read y[4], y[5] */
+ c0 = *__SIMD32(py);
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px + 1);
+ px += 2u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALD(x3, c0, acc2);
+ acc3 = __SMLALD(x2, c0, acc3);
+ }
+
+ if(k == 3u)
+ {
+ /* Read y[4], y[5] */
+ c0 = *__SIMD32(py)++;
+
+ /* Read x[7], x[8] */
+ x3 = *__SIMD32(px);
+
+ /* Read x[9] */
+ x2 = _SIMD32_OFFSET(px + 1);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALD(x3, c0, acc2);
+ acc3 = __SMLALD(x2, c0, acc3);
+
+ c0 = (*py);
+
+ /* Read y[6] */
+#ifdef ARM_MATH_BIG_ENDIAN
+
+ c0 = c0 << 16u;
+#else
+
+ c0 = c0 & 0x0000FFFF;
+#endif /* #ifdef ARM_MATH_BIG_ENDIAN */
+ /* Read x[10] */
+ x3 = _SIMD32_OFFSET(px + 2);
+ px += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALDX(x1, c0, acc0);
+ acc1 = __SMLALD(x2, c0, acc1);
+ acc2 = __SMLALDX(x2, c0, acc2);
+ acc3 = __SMLALDX(x3, c0, acc3);
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT(acc0 >> 15, 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q15_t) (__SSAT(acc1 >> 15, 16));
+ pOut += inc;
+
+ *pOut = (q15_t) (__SSAT(acc2 >> 15, 16));
+ pOut += inc;
+
+ *pOut = (q15_t) (__SSAT(acc3 >> 15, 16));
+ pOut += inc;
+
+ /* Increment the count by 4 as 4 output values are computed */
+ count += 4u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q63_t) * px++ * *py++);
+ sum += ((q63_t) * px++ * *py++);
+ sum += ((q63_t) * px++ * *py++);
+ sum += ((q63_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q63_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment count by 1, as one output value is computed */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q63_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+ /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum = __SMLALD(*px++, *py++, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ q15_t *pIn1 = pSrcA; /* inputA pointer */
+ q15_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
+ q63_t sum; /* Accumulators */
+ uint32_t i = 0u, j; /* loop counters */
+ uint32_t inv = 0u; /* Reverse order flag */
+ uint32_t tot = 0u; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and a varaible, inv is set to 1 */
+ /* If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we include zeroes
+ * in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer */
+ /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer */
+ /* Once the zero padding is done the remaining of the output is calcualted
+ * using convolution but with the shorter signal time shifted. */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2u);
+
+ if(srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if(srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1u);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0u; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if(inv == 1)
+ *pDst-- = (q15_t) __SSAT((sum >> 15u), 16u);
+ else
+ *pDst++ = (q15_t) __SSAT((sum >> 15u), 16u);
+ }
+
+#endif /*#if (defined(ARM_MATH_CM4) || defined(ARM_MATH_CM3)) && !defined(UNALIGNED_SUPPORT_DISABLE) */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q31.c
new file mode 100644
index 000000000..53ba335f3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q31.c
@@ -0,0 +1,665 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_q31.c
+*
+* Description: Correlation of Q31 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * Thus, if the accumulator overflows it wraps around and distorts the result.
+ * The input signals should be scaled down to avoid intermediate overflows.
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_correlate_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t *pIn1; /* inputA pointer */
+ q31_t *pIn2; /* inputB pointer */
+ q31_t *pOut = pDst; /* output pointer */
+ q31_t *px; /* Intermediate inputA pointer */
+ q31_t *py; /* Intermediate inputB pointer */
+ q31_t *pSrc1; /* Intermediate pointers */
+ q63_t sum, acc0, acc1, acc2; /* Accumulators */
+ q31_t x0, x1, x2, c0; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1; /* Destination address modifier */
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] * y[srcBLen - 4] */
+ sum += (q63_t) * px++ * (*py++);
+ /* x[1] * y[srcBLen - 3] */
+ sum += (q63_t) * px++ * (*py++);
+ /* x[2] * y[srcBLen - 2] */
+ sum += (q63_t) * px++ * (*py++);
+ /* x[3] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (sum >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll by 3 */
+ blkCnt = blockSize2 / 3;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* read x[0], x[1] samples */
+ x0 = *(px++);
+ x1 = *(px++);
+
+ /* Apply loop unrolling and compute 3 MACs simultaneously. */
+ k = srcBLen / 3;
+
+ /* First part of the processing with loop unrolling. Compute 3 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 2 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *(py);
+
+ /* Read x[2] sample */
+ x2 = *(px);
+
+ /* Perform the multiply-accumulate */
+ /* acc0 += x[0] * y[0] */
+ acc0 += ((q63_t) x0 * c0);
+ /* acc1 += x[1] * y[0] */
+ acc1 += ((q63_t) x1 * c0);
+ /* acc2 += x[2] * y[0] */
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Read y[1] sample */
+ c0 = *(py + 1u);
+
+ /* Read x[3] sample */
+ x0 = *(px + 1u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[1] * y[1] */
+ acc0 += ((q63_t) x1 * c0);
+ /* acc1 += x[2] * y[1] */
+ acc1 += ((q63_t) x2 * c0);
+ /* acc2 += x[3] * y[1] */
+ acc2 += ((q63_t) x0 * c0);
+
+ /* Read y[2] sample */
+ c0 = *(py + 2u);
+
+ /* Read x[4] sample */
+ x1 = *(px + 2u);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[2] * y[2] */
+ acc0 += ((q63_t) x2 * c0);
+ /* acc1 += x[3] * y[2] */
+ acc1 += ((q63_t) x0 * c0);
+ /* acc2 += x[4] * y[2] */
+ acc2 += ((q63_t) x1 * c0);
+
+ /* update scratch pointers */
+ px += 3u;
+ py += 3u;
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 3, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen - (3 * (srcBLen / 3));
+
+ while(k > 0u)
+ {
+ /* Read y[4] sample */
+ c0 = *(py++);
+
+ /* Read x[7] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 += ((q63_t) x0 * c0);
+ /* acc1 += x[5] * y[4] */
+ acc1 += ((q63_t) x1 * c0);
+ /* acc2 += x[6] * y[4] */
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (acc0 >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q31_t) (acc1 >> 31);
+ pOut += inc;
+
+ *pOut = (q31_t) (acc2 >> 31);
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 3 */
+ count += 3u;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 3, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 - 3 * (blockSize2 / 3);
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * px++ * (*py++);
+ sum += (q63_t) * px++ * (*py++);
+ sum += (q63_t) * px++ * (*py++);
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (sum >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (sum >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum += (q63_t) * px++ * (*py++);
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ sum += (q63_t) * px++ * (*py++);
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum += (q63_t) * px++ * (*py++);
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * px++ * (*py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q31_t) (sum >> 31);
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t *pIn1 = pSrcA; /* inputA pointer */
+ q31_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
+ q63_t sum; /* Accumulators */
+ uint32_t i = 0u, j; /* loop counters */
+ uint32_t inv = 0u; /* Reverse order flag */
+ uint32_t tot = 0u; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and a varaible, inv is set to 1 */
+ /* If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we include zeroes
+ * in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer */
+ /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer */
+ /* Once the zero padding is done the remaining of the output is calcualted
+ * using correlation but with the shorter signal time shifted. */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2u);
+
+ if(srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if(srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1u);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate correlation for output length number of times */
+ for (i = 0u; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to correlation equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if(inv == 1)
+ *pDst-- = (q31_t) (sum >> 31u);
+ else
+ *pDst++ = (q31_t) (sum >> 31u);
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q7.c
new file mode 100644
index 000000000..f0f7d12ea
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_correlate_q7.c
@@ -0,0 +1,790 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_correlate_q7.c
+*
+* Description: Correlation of Q7 sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup Corr
+ * @{
+ */
+
+/**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * This approach provides 17 guard bits and there is no risk of overflow as long as <code>max(srcALen, srcBLen)<131072</code>.
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.
+ *
+ * \par
+ * Refer the function <code>arm_correlate_opt_q7()</code> for a faster implementation of this function.
+ *
+ */
+
+void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t *pIn1; /* inputA pointer */
+ q7_t *pIn2; /* inputB pointer */
+ q7_t *pOut = pDst; /* output pointer */
+ q7_t *px; /* Intermediate inputA pointer */
+ q7_t *py; /* Intermediate inputB pointer */
+ q7_t *pSrc1; /* Intermediate pointers */
+ q31_t sum, acc0, acc1, acc2, acc3; /* Accumulators */
+ q31_t input1, input2; /* temporary variables */
+ q15_t in1, in2; /* temporary variables */
+ q7_t x0, x1, x2, x3, c0, c1; /* temporary variables for holding input and coefficient values */
+ uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3; /* loop counter */
+ int32_t inc = 1;
+
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and the destination pointer modifier, inc is set to -1 */
+ /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+ /* But to improve the performance,
+ * we include zeroes in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+ /* If srcALen < srcBLen,
+ * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+ if(srcALen >= srcBLen)
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcA);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcB);
+
+ /* Number of output samples is calculated */
+ outBlockSize = (2u * srcALen) - 1u;
+
+ /* When srcALen > srcBLen, zero padding is done to srcB
+ * to make their lengths equal.
+ * Instead, (outBlockSize - (srcALen + srcBLen - 1))
+ * number of output samples are made zero */
+ j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+ /* Updating the pointer position to non zero value */
+ pOut += j;
+
+ }
+ else
+ {
+ /* Initialization of inputA pointer */
+ pIn1 = (pSrcB);
+
+ /* Initialization of inputB pointer */
+ pIn2 = (pSrcA);
+
+ /* srcBLen is always considered as shorter or equal to srcALen */
+ j = srcBLen;
+ srcBLen = srcALen;
+ srcALen = j;
+
+ /* CORR(x, y) = Reverse order(CORR(y, x)) */
+ /* Hence set the destination pointer to point to the last output sample */
+ pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+ /* Destination address modifier is set to -1 */
+ inc = -1;
+
+ }
+
+ /* The function is internally
+ * divided into three parts according to the number of multiplications that has to be
+ * taken place between inputA samples and inputB samples. In the first part of the
+ * algorithm, the multiplications increase by one for every iteration.
+ * In the second part of the algorithm, srcBLen number of multiplications are done.
+ * In the third part of the algorithm, the multiplications decrease by one
+ * for every iteration.*/
+ /* The algorithm is implemented in three stages.
+ * The loop counters of each stage is initiated here. */
+ blockSize1 = srcBLen - 1u;
+ blockSize2 = srcALen - (srcBLen - 1u);
+ blockSize3 = blockSize1;
+
+ /* --------------------------
+ * Initializations of stage1
+ * -------------------------*/
+
+ /* sum = x[0] * y[srcBlen - 1]
+ * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]
+ * ....
+ * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]
+ */
+
+ /* In this stage the MAC operations are increased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = 1u;
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ pSrc1 = pIn2 + (srcBLen - 1u);
+ py = pSrc1;
+
+ /* ------------------------
+ * Stage1 process
+ * ----------------------*/
+
+ /* The first stage starts here */
+ while(blockSize1 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[0] , x[1] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 4] , y[srcBLen - 3] */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[0] * y[srcBLen - 4] */
+ /* x[1] * y[srcBLen - 3] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[2] , x[3] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[srcBLen - 2] , y[srcBLen - 1] */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* x[2] * y[srcBLen - 2] */
+ /* x[3] * y[srcBLen - 1] */
+ sum = __SMLAD(input1, input2, sum);
+
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ /* x[0] * y[srcBLen - 1] */
+ sum += (q31_t) ((q15_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ py = pSrc1 - count;
+ px = pIn1;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Decrement the loop counter */
+ blockSize1--;
+ }
+
+ /* --------------------------
+ * Initializations of stage2
+ * ------------------------*/
+
+ /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]
+ * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]
+ * ....
+ * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ */
+
+ /* Working pointer of inputA */
+ px = pIn1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* count is index by which the pointer pIn1 to be incremented */
+ count = 0u;
+
+ /* -------------------
+ * Stage2 process
+ * ------------------*/
+
+ /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.
+ * So, to loop unroll over blockSize2,
+ * srcBLen should be greater than or equal to 4 */
+ if(srcBLen >= 4u)
+ {
+ /* Loop unroll over blockSize2, by 4 */
+ blkCnt = blockSize2 >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* read x[0], x[1], x[2] samples */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ do
+ {
+ /* Read y[0] sample */
+ c0 = *py++;
+ /* Read y[1] sample */
+ c1 = *py++;
+
+ /* Read x[3] sample */
+ x3 = *px++;
+
+ /* x[0] and x[1] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[0] and y[1] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[0] * y[0] + x[1] * y[1] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[1] and x[2] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[1] * y[0] + x[2] * y[1] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[2] * y[0] + x[3] * y[1] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[4] sample */
+ x0 = *(px++);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[3] * y[0] + x[4] * y[1] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ /* Read y[2] sample */
+ c0 = *py++;
+ /* Read y[3] sample */
+ c1 = *py++;
+
+ /* Read x[5] sample */
+ x1 = *px++;
+
+ /* x[2] and x[3] are packed */
+ in1 = (q15_t) x2;
+ in2 = (q15_t) x3;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[2] and y[3] are packed */
+ in1 = (q15_t) c0;
+ in2 = (q15_t) c1;
+
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc0 += x[2] * y[2] + x[3] * y[3] */
+ acc0 = __SMLAD(input1, input2, acc0);
+
+ /* x[3] and x[4] are packed */
+ in1 = (q15_t) x3;
+ in2 = (q15_t) x0;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc1 += x[3] * y[2] + x[4] * y[3] */
+ acc1 = __SMLAD(input1, input2, acc1);
+
+ /* x[4] and x[5] are packed */
+ in1 = (q15_t) x0;
+ in2 = (q15_t) x1;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc2 += x[4] * y[2] + x[5] * y[3] */
+ acc2 = __SMLAD(input1, input2, acc2);
+
+ /* Read x[6] sample */
+ x2 = *px++;
+
+ /* x[5] and x[6] are packed */
+ in1 = (q15_t) x1;
+ in2 = (q15_t) x2;
+
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* acc3 += x[5] * y[2] + x[6] * y[3] */
+ acc3 = __SMLAD(input1, input2, acc3);
+
+ } while(--k);
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Read y[4] sample */
+ c0 = *py++;
+
+ /* Read x[7] sample */
+ x3 = *px++;
+
+ /* Perform the multiply-accumulates */
+ /* acc0 += x[4] * y[4] */
+ acc0 += ((q15_t) x0 * c0);
+ /* acc1 += x[5] * y[4] */
+ acc1 += ((q15_t) x1 * c0);
+ /* acc2 += x[6] * y[4] */
+ acc2 += ((q15_t) x2 * c0);
+ /* acc3 += x[7] * y[4] */
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Reuse the present samples for the next MAC */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(acc0 >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ *pOut = (q7_t) (__SSAT(acc1 >> 7, 8));
+ pOut += inc;
+
+ *pOut = (q7_t) (__SSAT(acc2 >> 7, 8));
+ pOut += inc;
+
+ *pOut = (q7_t) (__SSAT(acc3 >> 7, 8));
+ pOut += inc;
+
+ count += 4u;
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize2 % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = srcBLen >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Reading two inputs of SrcA buffer and packing */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Reading two inputs of SrcB buffer and packing */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* Perform the multiply-accumulates */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = srcBLen % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the pointer pIn1 index, count by 1 */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+ else
+ {
+ /* If the srcBLen is not a multiple of 4,
+ * the blockSize2 loop cannot be unrolled by 4 */
+ blkCnt = blockSize2;
+
+ while(blkCnt > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Loop over srcBLen */
+ k = srcBLen;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += ((q15_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Increment the MAC count */
+ count++;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = pIn1 + count;
+ py = pIn2;
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+ }
+
+ /* --------------------------
+ * Initializations of stage3
+ * -------------------------*/
+
+ /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]
+ * ....
+ * sum += x[srcALen-2] * y[0] + x[srcALen-1] * y[1]
+ * sum += x[srcALen-1] * y[0]
+ */
+
+ /* In this stage the MAC operations are decreased by 1 for every iteration.
+ The count variable holds the number of MAC operations performed */
+ count = srcBLen - 1u;
+
+ /* Working pointer of inputA */
+ pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+ px = pSrc1;
+
+ /* Working pointer of inputB */
+ py = pIn2;
+
+ /* -------------------
+ * Stage3 process
+ * ------------------*/
+
+ while(blockSize3 > 0u)
+ {
+ /* Accumulator is made zero for every iteration */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ k = count >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 MACs at a time.
+ ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+ while(k > 0u)
+ {
+ /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[0] , y[1] */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 1] * y[0] */
+ /* sum += x[srcALen - srcBLen + 2] * y[1] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */
+ in1 = (q15_t) * px++;
+ in2 = (q15_t) * px++;
+ input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* y[2] , y[3] */
+ in1 = (q15_t) * py++;
+ in2 = (q15_t) * py++;
+ input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+ /* sum += x[srcALen - srcBLen + 3] * y[2] */
+ /* sum += x[srcALen - srcBLen + 4] * y[3] */
+ sum = __SMLAD(input1, input2, sum);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* If the count is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ k = count % 0x4u;
+
+ while(k > 0u)
+ {
+ /* Perform the multiply-accumulates */
+ sum += ((q15_t) * px++ * *py++);
+
+ /* Decrement the loop counter */
+ k--;
+ }
+
+ /* Store the result in the accumulator in the destination buffer. */
+ *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+ /* Destination pointer is updated according to the address modifier, inc */
+ pOut += inc;
+
+ /* Update the inputA and inputB pointers for next MAC calculation */
+ px = ++pSrc1;
+ py = pIn2;
+
+ /* Decrement the MAC count */
+ count--;
+
+ /* Decrement the loop counter */
+ blockSize3--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ q7_t *pIn1 = pSrcA; /* inputA pointer */
+ q7_t *pIn2 = pSrcB + (srcBLen - 1u); /* inputB pointer */
+ q31_t sum; /* Accumulator */
+ uint32_t i = 0u, j; /* loop counters */
+ uint32_t inv = 0u; /* Reverse order flag */
+ uint32_t tot = 0u; /* Length */
+
+ /* The algorithm implementation is based on the lengths of the inputs. */
+ /* srcB is always made to slide across srcA. */
+ /* So srcBLen is always considered as shorter or equal to srcALen */
+ /* But CORR(x, y) is reverse of CORR(y, x) */
+ /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+ /* and a varaible, inv is set to 1 */
+ /* If lengths are not equal then zero pad has to be done to make the two
+ * inputs of same length. But to improve the performance, we include zeroes
+ * in the output instead of zero padding either of the the inputs*/
+ /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * starting of the output buffer */
+ /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the
+ * ending of the output buffer */
+ /* Once the zero padding is done the remaining of the output is calcualted
+ * using convolution but with the shorter signal time shifted. */
+
+ /* Calculate the length of the remaining sequence */
+ tot = ((srcALen + srcBLen) - 2u);
+
+ if(srcALen > srcBLen)
+ {
+ /* Calculating the number of zeros to be padded to the output */
+ j = srcALen - srcBLen;
+
+ /* Initialise the pointer after zero padding */
+ pDst += j;
+ }
+
+ else if(srcALen < srcBLen)
+ {
+ /* Initialization to inputB pointer */
+ pIn1 = pSrcB;
+
+ /* Initialization to the end of inputA pointer */
+ pIn2 = pSrcA + (srcALen - 1u);
+
+ /* Initialisation of the pointer after zero padding */
+ pDst = pDst + tot;
+
+ /* Swapping the lengths */
+ j = srcALen;
+ srcALen = srcBLen;
+ srcBLen = j;
+
+ /* Setting the reverse flag */
+ inv = 1;
+
+ }
+
+ /* Loop to calculate convolution for output length number of times */
+ for (i = 0u; i <= tot; i++)
+ {
+ /* Initialize sum with zero to carry on MAC operations */
+ sum = 0;
+
+ /* Loop to perform MAC operations according to convolution equation */
+ for (j = 0u; j <= i; j++)
+ {
+ /* Check the array limitations */
+ if((((i - j) < srcBLen) && (j < srcALen)))
+ {
+ /* z[i] += x[i-j] * y[j] */
+ sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+ }
+ }
+ /* Store the output in the destination buffer */
+ if(inv == 1)
+ *pDst-- = (q7_t) __SSAT((sum >> 7u), 8u);
+ else
+ *pDst++ = (q7_t) __SSAT((sum >> 7u), 8u);
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of Corr group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_f32.c
new file mode 100644
index 000000000..2c3d82a66
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_f32.c
@@ -0,0 +1,524 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_f32.c
+*
+* Description: FIR decimation for floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator
+ *
+ * These functions combine an FIR filter together with a decimator.
+ * They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion.
+ * Conceptually, the functions are equivalent to the block diagram below:
+ * \image html FIRDecimator.gif "Components included in the FIR Decimator functions"
+ * When decimating by a factor of <code>M</code>, the signal should be prefiltered by a lowpass filter with a normalized
+ * cutoff frequency of <code>1/M</code> in order to prevent aliasing distortion.
+ * The user of the function is responsible for providing the filter coefficients.
+ *
+ * The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner.
+ * Instead of calculating all of the FIR filter outputs and discarding <code>M-1</code> out of every <code>M</code>, only the
+ * samples output by the decimator are computed.
+ * The functions operate on blocks of input and output data.
+ * <code>pSrc</code> points to an array of <code>blockSize</code> input values and
+ * <code>pDst</code> points to an array of <code>blockSize/M</code> output values.
+ * In order to have an integer number of output samples <code>blockSize</code>
+ * must always be a multiple of the decimation factor <code>M</code>.
+ *
+ * The library provides separate functions for Q15, Q31 and floating-point data types.
+ *
+ * \par Algorithm:
+ * The FIR portion of the algorithm uses the standard form filter:
+ * <pre>
+ * y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+ * </pre>
+ * where, <code>b[n]</code> are the filter coefficients.
+ * \par
+ * The <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.
+ * Coefficients are stored in time reversed order.
+ * \par
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to a state array of size <code>numTaps + blockSize - 1</code>.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ * <pre>
+ * {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+ * </pre>
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * - Checks to make sure that the size of the input is a multiple of the decimation factor.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, M (decimation factor), pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ * <pre>
+ *arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};
+ *arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};
+ *arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};
+ * </pre>
+ * where <code>M</code> is the decimation factor; <code>numTaps</code> is the number of filter coefficients in the filter;
+ * <code>pCoeffs</code> is the address of the coefficient buffer;
+ * <code>pState</code> is the address of the state buffer.
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the FIR decimate filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t sum0; /* Accumulator */
+ float32_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t blkCntN4;
+ float32_t *px0, *px1, *px2, *px3;
+ float32_t acc0, acc1, acc2, acc3;
+ float32_t x1, x2, x3;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 4;
+ blkCntN4 = outBlockSize - (4 * blkCnt);
+
+ while(blkCnt > 0u)
+ {
+ /* Copy 4 * decimation factor number of new input samples into the state buffer */
+ i = 4 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* Initialize state pointer for all the samples */
+ px0 = pState;
+ px1 = pState + S->M;
+ px2 = pState + 2 * S->M;
+ px3 = pState + 3 * S->M;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample for acc0 */
+ x0 = *(px0++);
+ /* Read x[n-numTaps-1] sample for acc1 */
+ x1 = *(px1++);
+ /* Read x[n-numTaps-1] sample for acc2 */
+ x2 = *(px2++);
+ /* Read x[n-numTaps-1] sample for acc3 */
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample for acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch state variables for acc0, acc1, acc2, acc3 */
+ x0 = *(px0++);
+ x1 = *(px1++);
+ x2 = *(px2++);
+ x3 = *(px3++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + 4 * S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = acc0;
+ *pDst++ = acc1;
+ *pDst++ = acc2;
+ *pDst++ = acc3;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ while(blkCntN4 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum0;
+
+ /* Decrement the loop counter */
+ blkCntN4--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum0;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy numTaps number of values */
+ i = (numTaps - 1u);
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_fast_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_fast_q15.c
new file mode 100644
index 000000000..261be56ec
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_fast_q15.c
@@ -0,0 +1,598 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_fast_q15.c
+*
+* Description: Fast Q15 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, state buffers should be aligned by 32-bit
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2).
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.
+ *
+ * \par
+ * Refer to the function <code>arm_fir_decimate_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.
+ * Both the slow and the fast versions use the same instance structure.
+ * Use the function <code>arm_fir_decimate_init_q15()</code> to initialize the filter structure.
+ */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q31_t x0, x1, c0, c1; /* Temporary variables to hold state and coefficient values */
+ q31_t sum0; /* Accumulators */
+ q31_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ px1 = pState + S->M;
+
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+ x0 = *__SIMD32(px0)++;
+
+ x1 = *__SIMD32(px1)++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = *__SIMD32(px0)++;
+
+ x1 = *__SIMD32(px1)++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc1 = __SMLAD(x1, c0, acc1);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+
+ while(blkCntN3 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+ x0 = *__SIMD32(px)++;
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+ c1 = *__SIMD32(pb)++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLAD(x0, c0, sum0);
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = *__SIMD32(px)++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLAD(x0, c1, sum0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLAD(x0, c0, sum0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+#else
+
+
+void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */
+ q31_t sum0; /* Accumulators */
+ q31_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ px1 = pState + S->M;
+
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ while(blkCntN3 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] and sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] and sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_fast_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_fast_q31.c
new file mode 100644
index 000000000..623f080a5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_fast_q31.c
@@ -0,0 +1,351 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_fast_q31.c
+*
+* Description: Fast Q31 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are added to a 2.30 accumulator.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).
+ *
+ * \par
+ * Refer to the function <code>arm_fir_decimate_q31()</code> for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.
+ * Both the slow and the fast versions use the same instance structure.
+ * Use the function <code>arm_fir_decimate_init_q31()</code> to initialize the filter structure.
+ */
+
+void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q31_t *px; /* Temporary pointers for state buffer */
+ q31_t *pb; /* Temporary pointers for coefficient buffer */
+ q31_t sum0; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+ uint32_t blkCntN2;
+ q31_t x1;
+ q31_t acc0, acc1;
+ q31_t *px0, *px1;
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+
+ blkCnt = outBlockSize / 2;
+ blkCntN2 = outBlockSize - (2 * blkCnt);
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+ px1 = pState + S->M;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb);
+
+ /* Read x[n-numTaps-1] for sample 0 sample 1 */
+ x0 = *(px0);
+ x1 = *(px1);
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb + 1u);
+
+ /* Read x[n-numTaps-2] for sample 0 sample 1 */
+ x0 = *(px0 + 1u);
+ x1 = *(px1 + 1u);
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb + 2u);
+
+ /* Read x[n-numTaps-3] for sample 0 sample 1 */
+ x0 = *(px0 + 2u);
+ x1 = *(px1 + 2u);
+ pb += 4u;
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb - 1u);
+
+ /* Read x[n-numTaps-4] for sample 0 sample 1 */
+ x0 = *(px0 + 3u);
+ x1 = *(px1 + 3u);
+
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* update state pointers */
+ px0 += 4u;
+ px1 += 4u;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x0 = *(px0++);
+ x1 = *(px1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+ acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 << 1);
+ *pDst++ = (q31_t) (acc1 << 1);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ while(blkCntN2 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 = (q31_t) ((((q63_t) sum0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 << 1);
+
+ /* Decrement the loop counter */
+ blkCntN2--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_f32.c
new file mode 100644
index 000000000..1bc8ce0d5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_f32.c
@@ -0,0 +1,117 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_init_f32.c
+*
+* Description: Floating-point FIR Decimator initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> words where <code>blockSize</code> is the number of input samples passed to <code>arm_fir_decimate_f32()</code>.
+ * <code>M</code> is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The size of the input block must be a multiple of the decimation factor */
+ if((blockSize % M) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Decimation Factor */
+ S->M = M;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_q15.c
new file mode 100644
index 000000000..3127360c6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_q15.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_init_q15.c
+*
+* Description: Initialization function for the Q15 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> words where <code>blockSize</code> is the number of input samples
+ * to the call <code>arm_fir_decimate_q15()</code>.
+ * <code>M</code> is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+
+ arm_status status;
+
+ /* The size of the input block must be a multiple of the decimation factor */
+ if((blockSize % M) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size of buffer is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Decimation factor */
+ S->M = M;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_q31.c
new file mode 100644
index 000000000..20eebc7c9
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_init_q31.c
@@ -0,0 +1,117 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_init_q31.c
+*
+* Description: Initialization function for Q31 FIR Decimation filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> words where <code>blockSize</code> is the number of input samples passed to <code>arm_fir_decimate_q31()</code>.
+ * <code>M</code> is the decimation factor.
+ */
+
+arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The size of the input block must be a multiple of the decimation factor */
+ if((blockSize % M) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Decimation factor */
+ S->M = M;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_q15.c
new file mode 100644
index 000000000..cb86bac06
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_q15.c
@@ -0,0 +1,696 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_q15.c
+*
+* Description: Q15 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the location where the output result is written.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ *
+ * \par
+ * Refer to the function <code>arm_fir_decimate_fast_q15()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q31_t x0, x1, c0, c1; /* Temporary variables to hold state and coefficient values */
+ q63_t sum0; /* Accumulators */
+ q63_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ px1 = pState + S->M;
+
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+ x0 = *__SIMD32(px0)++;
+
+ x1 = *__SIMD32(px1)++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = *__SIMD32(px0)++;
+
+ x1 = *__SIMD32(px1)++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+
+ while(blkCntN3 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] and b[numTaps-2] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+ x0 = *__SIMD32(px)++;
+
+ /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+ c1 = *__SIMD32(pb)++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLALD(x0, c0, sum0);
+
+ /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+ x0 = *__SIMD32(px)++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLALD(x0, c1, sum0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 = __SMLALD(x0, c0, sum0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+#else
+
+
+void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q15_t x0, x1, c0; /* Temporary variables to hold state and coefficient values */
+ q63_t sum0; /* Accumulators */
+ q63_t acc0, acc1;
+ q15_t *px0, *px1;
+ uint32_t blkCntN3;
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize / 2;
+ blkCntN3 = outBlockSize - (2 * blkCnt);
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = 2 * S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ px0 = pState;
+
+ px1 = pState + S->M;
+
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] for sample 0 and for sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] for sample 0 and sample 1 */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px0++;
+ x1 = *px1++;
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M * 2;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *pDst++ = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ while(blkCntN3 > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the Read b[numTaps-1] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-1] and sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-2] and sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *pb++;
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* Store filter output, smlad returns the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCntN3--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#else
+
+
+void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer coefficient buffer */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q63_t sum0; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+
+/* Run the below code for Cortex-M0 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /*Set sum to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q31_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /*Store filter output , smlad will return the values in 2.14 format */
+ /* so downsacle by 15 to get output in 1.15 */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = numTaps - 1u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+}
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_q31.c
new file mode 100644
index 000000000..8c75e7f63
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_decimate_q31.c
@@ -0,0 +1,311 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_decimate_q31.c
+*
+* Description: Q31 FIR Decimator.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_decimate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ *
+ * \par
+ * Refer to the function <code>arm_fir_decimate_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ q31_t *px; /* Temporary pointers for state buffer */
+ q31_t *pb; /* Temporary pointers for coefficient buffer */
+ q63_t sum0; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of taps */
+ uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M; /* Loop counters */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-1] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-2] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 >> 31);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = (numTaps - 1u) % 0x04u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Total number of output samples to be computed */
+ blkCnt = outBlockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy decimation factor number of new input samples into the state buffer */
+ i = S->M;
+
+ do
+ {
+ *pStateCurnt++ = *pSrc++;
+
+ } while(--i);
+
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = pCoeffs;
+
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *pb++;
+
+ /* Fetch 1 state variable */
+ x0 = *px++;
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by the decimation factor
+ * to process the next group of decimation factor number samples */
+ pState = pState + S->M;
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 >> 31);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = numTaps - 1u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_decimate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_f32.c
new file mode 100644
index 000000000..f921acb31
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_f32.c
@@ -0,0 +1,651 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_f32.c
+*
+* Description: Floating-point FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupFilters
+*/
+
+/**
+* @defgroup FIR Finite Impulse Response (FIR) Filters
+*
+* This set of functions implements Finite Impulse Response (FIR) filters
+* for Q7, Q15, Q31, and floating-point data types. Fast versions of Q15 and Q31 are also provided.
+* The functions operate on blocks of input and output data and each call to the function processes
+* <code>blockSize</code> samples through the filter. <code>pSrc</code> and
+* <code>pDst</code> points to input and output arrays containing <code>blockSize</code> values.
+*
+* \par Algorithm:
+* The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations.
+* Each filter coefficient <code>b[n]</code> is multiplied by a state variable which equals a previous input sample <code>x[n]</code>.
+* <pre>
+* y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+* </pre>
+* \par
+* \image html FIR.gif "Finite Impulse Response filter"
+* \par
+* <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.
+* Coefficients are stored in time reversed order.
+* \par
+* <pre>
+* {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+* </pre>
+* \par
+* <code>pState</code> points to a state array of size <code>numTaps + blockSize - 1</code>.
+* Samples in the state buffer are stored in the following order.
+* \par
+* <pre>
+* {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+* </pre>
+* \par
+* Note that the length of the state buffer exceeds the length of the coefficient array by <code>blockSize-1</code>.
+* The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters,
+* to be avoided and yields a significant speed improvement.
+* The state variables are updated after each block of data is processed; the coefficients are untouched.
+* \par Instance Structure
+* The coefficients and state variables for a filter are stored together in an instance data structure.
+* A separate instance structure must be defined for each filter.
+* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+* There are separate instance structure declarations for each of the 4 supported data types.
+*
+* \par Initialization Functions
+* There is also an associated initialization function for each data type.
+* The initialization function performs the following operations:
+* - Sets the values of the internal structure fields.
+* - Zeros out the values in the state buffer.
+* To do this manually without calling the init function, assign the follow subfields of the instance structure:
+* numTaps, pCoeffs, pState. Also set all of the values in pState to zero.
+*
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+* To place an instance structure into a const data section, the instance structure must be manually initialized.
+* Set the values in the state buffer to zeros before static initialization.
+* The code below statically initializes each of the 4 different data type filter instance structures
+* <pre>
+*arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};
+*arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};
+*arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};
+*arm_fir_instance_q7 S = {numTaps, pState, pCoeffs};
+* </pre>
+*
+* where <code>numTaps</code> is the number of filter coefficients in the filter; <code>pState</code> is the address of the state buffer;
+* <code>pCoeffs</code> is the address of the coefficient buffer.
+*
+* \par Fixed-Point Behavior
+* Care must be taken when using the fixed-point versions of the FIR filter functions.
+* In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+* Refer to the function specific documentation below for usage guidelines.
+*/
+
+/**
+* @addtogroup FIR
+* @{
+*/
+
+/**
+*
+* @param[in] *S points to an instance of the floating-point FIR filter structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[out] *pDst points to the block of output data.
+* @param[in] blockSize number of samples to process per call.
+* @return none.
+*
+*/
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_f32(
+const arm_fir_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7; /* Accumulators */
+ float32_t x0, x1, x2, x3, x4, x5, x6, x7, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+ float32_t p0,p1,p2,p3,p4,p5,p6,p7; /* Temporary product values */
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 8 output values simultaneously.
+ * The variables acc0 ... acc7 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize >> 3;
+
+ /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
+ ** a second loop below computes the remaining 1 to 7 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+ acc4 = 0.0f;
+ acc5 = 0.0f;
+ acc6 = 0.0f;
+ acc7 = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* This is separated from the others to avoid
+ * a call to __aeabi_memmove which would be slower
+ */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Read the first seven samples from the state buffer: x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+ x0 = *px++;
+ x1 = *px++;
+ x2 = *px++;
+ x3 = *px++;
+ x4 = *px++;
+ x5 = *px++;
+ x6 = *px++;
+
+ /* Loop unrolling. Process 8 taps at a time. */
+ tapCnt = numTaps >> 3u;
+
+ /* Loop over the number of taps. Unroll by a factor of 8.
+ ** Repeat until we've computed numTaps-8 coefficients. */
+ while(tapCnt > 0u)
+ {
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x7 = *(px++);
+
+ /* acc0 += b[numTaps-1] * x[n-numTaps] */
+ p0 = x0 * c0;
+
+ /* acc1 += b[numTaps-1] * x[n-numTaps-1] */
+ p1 = x1 * c0;
+
+ /* acc2 += b[numTaps-1] * x[n-numTaps-2] */
+ p2 = x2 * c0;
+
+ /* acc3 += b[numTaps-1] * x[n-numTaps-3] */
+ p3 = x3 * c0;
+
+ /* acc4 += b[numTaps-1] * x[n-numTaps-4] */
+ p4 = x4 * c0;
+
+ /* acc1 += b[numTaps-1] * x[n-numTaps-5] */
+ p5 = x5 * c0;
+
+ /* acc2 += b[numTaps-1] * x[n-numTaps-6] */
+ p6 = x6 * c0;
+
+ /* acc3 += b[numTaps-1] * x[n-numTaps-7] */
+ p7 = x7 * c0;
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+
+ /* Perform the multiply-accumulate */
+ p0 = x1 * c0;
+ p1 = x2 * c0;
+ p2 = x3 * c0;
+ p3 = x4 * c0;
+ p4 = x5 * c0;
+ p5 = x6 * c0;
+ p6 = x7 * c0;
+ p7 = x0 * c0;
+
+ /* Read the b[numTaps-3] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-5] sample */
+ x1 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x2 * c0;
+ p1 = x3 * c0;
+ p2 = x4 * c0;
+ p3 = x5 * c0;
+ p4 = x6 * c0;
+ p5 = x7 * c0;
+ p6 = x0 * c0;
+ p7 = x1 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x2 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x3 * c0;
+ p1 = x4 * c0;
+ p2 = x5 * c0;
+ p3 = x6 * c0;
+ p4 = x7 * c0;
+ p5 = x0 * c0;
+ p6 = x1 * c0;
+ p7 = x2 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x3 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x4 * c0;
+ p1 = x5 * c0;
+ p2 = x6 * c0;
+ p3 = x7 * c0;
+ p4 = x0 * c0;
+ p5 = x1 * c0;
+ p6 = x2 * c0;
+ p7 = x3 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x4 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x5 * c0;
+ p1 = x6 * c0;
+ p2 = x7 * c0;
+ p3 = x0 * c0;
+ p4 = x1 * c0;
+ p5 = x2 * c0;
+ p6 = x3 * c0;
+ p7 = x4 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x5 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x6 * c0;
+ p1 = x7 * c0;
+ p2 = x0 * c0;
+ p3 = x1 * c0;
+ p4 = x2 * c0;
+ p5 = x3 * c0;
+ p6 = x4 * c0;
+ p7 = x5 * c0;
+
+ /* Read the b[numTaps-4] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x6 = *(px++);
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Perform the multiply-accumulates */
+ p0 = x7 * c0;
+ p1 = x0 * c0;
+ p2 = x1 * c0;
+ p3 = x2 * c0;
+ p4 = x3 * c0;
+ p5 = x4 * c0;
+ p6 = x5 * c0;
+ p7 = x6 * c0;
+
+ tapCnt--;
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+ }
+
+ /* If the filter length is not a multiple of 8, compute the remaining filter taps */
+ tapCnt = numTaps % 0x8u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x7 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ p0 = x0 * c0;
+ p1 = x1 * c0;
+ p2 = x2 * c0;
+ p3 = x3 * c0;
+ p4 = x4 * c0;
+ p5 = x5 * c0;
+ p6 = x6 * c0;
+ p7 = x7 * c0;
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+ x3 = x4;
+ x4 = x5;
+ x5 = x6;
+ x6 = x7;
+
+ acc0 += p0;
+ acc1 += p1;
+ acc2 += p2;
+ acc3 += p3;
+ acc4 += p4;
+ acc5 += p5;
+ acc6 += p6;
+ acc7 += p7;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance the state pointer by 8 to process the next group of 8 samples */
+ pState = pState + 8;
+
+ /* The results in the 8 accumulators, store in the destination buffer. */
+ *pDst++ = acc0;
+ *pDst++ = acc1;
+ *pDst++ = acc2;
+ *pDst++ = acc3;
+ *pDst++ = acc4;
+ *pDst++ = acc5;
+ *pDst++ = acc6;
+ *pDst++ = acc7;
+
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x8u;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = (pCoeffs);
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ acc0 += *px++ * *pb++;
+ i--;
+
+ } while(i > 0u);
+
+ /* The result is store in the destination buffer. */
+ *pDst++ = acc0;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+#else
+
+void arm_fir_f32(
+const arm_fir_instance_f32 * S,
+float32_t * pSrc,
+float32_t * pDst,
+uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t acc;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initialize blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0.0f;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = pCoeffs;
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+ acc += *px++ * *pb++;
+ i--;
+
+ } while(i > 0u);
+
+ /* The result is store in the destination buffer. */
+ *pDst++ = acc;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy numTaps number of values */
+ tapCnt = numTaps - 1u;
+
+ /* Copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+/**
+* @} end of FIR group
+*/
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_fast_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_fast_q15.c
new file mode 100644
index 000000000..e701ed2c9
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_fast_q15.c
@@ -0,0 +1,345 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_fast_q15.c
+*
+* Description: Q15 Fast FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * This fast version uses a 32-bit accumulator with 2.30 format.
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.
+ *
+ * \par
+ * Refer to the function <code>arm_fir_q15()</code> for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion. Both the slow and the fast versions use the same instance structure.
+ * Use the function <code>arm_fir_init_q15()</code> to initialize the filter structure.
+ */
+
+void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q15_t *px; /* Temporary q31 pointer for SIMD state buffer accesses */
+ q31_t x0, x1, x2, c0; /* Temporary variables to hold SIMD state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer.
+ ** Use 32-bit SIMD to move the 16-bit data. Only requires two copies. */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
+ px = pState;
+
+ /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
+ pb = pCoeffs;
+
+ /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */
+ x0 = *__SIMD32(px)++;
+
+ /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
+ x2 = *__SIMD32(px)++;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0)
+ {
+ /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ acc0 = __SMLAD(x0, c0, acc0);
+
+ /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* pack x[n-N-1] and x[n-N-2] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* Read state x[n-N-4], x[n-N-5] */
+ x0 = _SIMD32_OFFSET(px);
+
+ /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* pack x[n-N-3] and x[n-N-4] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x0, x2, 0);
+#else
+ x1 = __PKHBT(x2, x0, 0);
+#endif
+
+ /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ /* Read coefficients b[N-2], b[N-3] */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+ acc0 = __SMLAD(x2, c0, acc0);
+
+ /* Read state x[n-N-6], x[n-N-7] with offset */
+ x2 = _SIMD32_OFFSET(px + 2u);
+
+ /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+ acc2 = __SMLAD(x0, c0, acc2);
+
+ /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* pack x[n-N-5] and x[n-N-6] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+ acc3 = __SMLADX(x1, c0, acc3);
+
+ /* Update state pointer for next state reading */
+ px += 4u;
+
+ /* Decrement tap count */
+ tapCnt--;
+
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps.
+ ** This is always be 2 taps since the filter length is even. */
+ if((numTaps & 0x3u) != 0u)
+ {
+
+ /* Read last two coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLAD(x0, c0, acc0);
+ acc2 = __SMLAD(x2, c0, acc2);
+
+ /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* Read last state variables */
+ x0 = *__SIMD32(px);
+
+ /* Perform the multiply-accumulates */
+ acc1 = __SMLADX(x1, c0, acc1);
+
+ /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x0, x2, 0);
+#else
+ x1 = __PKHBT(x2, x0, 0);
+#endif
+
+ /* Perform the multiply-accumulates */
+ acc3 = __SMLADX(x1, c0, acc3);
+ }
+
+ /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+ while(blkCnt > 0u)
+ {
+ /* Copy two samples into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Use SIMD to hold states and coefficients */
+ px = pState;
+ pb = pCoeffs;
+
+ tapCnt = numTaps >> 1u;
+
+ do
+ {
+
+ acc0 += (q31_t) * px++ * *pb++;
+ acc0 += (q31_t) * px++ * *pb++;
+
+ tapCnt--;
+ }
+ while(tapCnt > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy remaining data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_fast_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_fast_q31.c
new file mode 100644
index 000000000..1ba7e38c8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_fast_q31.c
@@ -0,0 +1,299 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_fast_q31.c
+*
+* Description: Processing function for the Q31 Fast FIR filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q31 structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.
+ * These intermediate results are added to a 2.30 accumulator.
+ * Finally, the accumulator is saturated and converted to a 1.31 result.
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
+ *
+ * \par
+ * Refer to the function <code>arm_fir_q31()</code> for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision. Both the slow and the fast versions use the same instance structure.
+ * Use the function <code>arm_fir_init_q31()</code> to initialize the filter structure.
+ */
+
+IAR_ONLY_LOW_OPTIMIZATION_ENTER
+void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t x0, x1, x2, x3; /* Temporary variables to hold state */
+ q31_t c0; /* Temporary variable to hold coefficient value */
+ q31_t *px; /* Temporary pointer for state */
+ q31_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Read the first three samples from the state buffer:
+ * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+ i = tapCnt;
+
+ while(i > 0u)
+ {
+ /* Read the b[numTaps] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x3 = *(px++);
+
+ /* acc0 += b[numTaps] * x[n-numTaps] */
+ multAcc_32x32_keep32_R(acc0, x0, c0);
+
+ /* acc1 += b[numTaps] * x[n-numTaps-1] */
+ multAcc_32x32_keep32_R(acc1, x1, c0);
+
+ /* acc2 += b[numTaps] * x[n-numTaps-2] */
+ multAcc_32x32_keep32_R(acc2, x2, c0);
+
+ /* acc3 += b[numTaps] * x[n-numTaps-3] */
+ multAcc_32x32_keep32_R(acc3, x3, c0);
+
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x1, c0);
+ multAcc_32x32_keep32_R(acc1, x2, c0);
+ multAcc_32x32_keep32_R(acc2, x3, c0);
+ multAcc_32x32_keep32_R(acc3, x0, c0);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x2, c0);
+ multAcc_32x32_keep32_R(acc1, x3, c0);
+ multAcc_32x32_keep32_R(acc2, x0, c0);
+ multAcc_32x32_keep32_R(acc3, x1, c0);
+
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x3, c0);
+ multAcc_32x32_keep32_R(acc1, x0, c0);
+ multAcc_32x32_keep32_R(acc2, x1, c0);
+ multAcc_32x32_keep32_R(acc3, x2, c0);
+ i--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+ i = numTaps - (tapCnt * 4u);
+ while(i > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ multAcc_32x32_keep32_R(acc0, x0, c0);
+ multAcc_32x32_keep32_R(acc1, x1, c0);
+ multAcc_32x32_keep32_R(acc2, x2, c0);
+ multAcc_32x32_keep32_R(acc3, x3, c0);
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4;
+
+ /* The results in the 4 accumulators are in 2.30 format. Convert to 1.31
+ ** Then store the 4 outputs in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 << 1);
+ *pDst++ = (q31_t) (acc1 << 1);
+ *pDst++ = (q31_t) (acc2 << 1);
+ *pDst++ = (q31_t) (acc3 << 1);
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = (pCoeffs);
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ multAcc_32x32_keep32_R(acc0, (*px++), (*(pb++)));
+ i--;
+ } while(i > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.31
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 << 1);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+}
+IAR_ONLY_LOW_OPTIMIZATION_EXIT
+/**
+ * @} end of FIR group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_f32.c
new file mode 100644
index 000000000..429c958eb
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_f32.c
@@ -0,0 +1,96 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_init_f32.c
+*
+* Description: Floating-point FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed per call.
+ * @return none.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_f32()</code>.
+ */
+
+void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and the size of state buffer is (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q15.c
new file mode 100644
index 000000000..279757fca
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q15.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_init_q15.c
+*
+* Description: Q15 FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize is number of samples processed per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not greater than or equal to 4 and even.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * Note that <code>numTaps</code> must be even and greater than or equal to 4.
+ * To implement an odd length filter simply increase <code>numTaps</code> by 1 and set the last coefficient to zero.
+ * For example, to implement a filter with <code>numTaps=3</code> and coefficients
+ * <pre>
+ * {0.3, -0.8, 0.3}
+ * </pre>
+ * set <code>numTaps=4</code> and use the coefficients:
+ * <pre>
+ * {0.3, -0.8, 0.3, 0}.
+ * </pre>
+ * Similarly, to implement a two point filter
+ * <pre>
+ * {0.3, -0.3}
+ * </pre>
+ * set <code>numTaps=4</code> and use the coefficients:
+ * <pre>
+ * {0.3, -0.3, 0, 0}.
+ * </pre>
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>numTaps+blockSize</code>, when running on Cortex-M4 and Cortex-M3 and is of length <code>numTaps+blockSize-1</code>, when running on Cortex-M0 where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_q15()</code>.
+ */
+
+arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* The Number of filter coefficients in the filter must be even and at least 4 */
+ if(numTaps & 0x1u)
+ {
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+ else
+ {
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps ) */
+ memset(pState, 0, (numTaps + (blockSize)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+
+ return (status);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q31.c
new file mode 100644
index 000000000..2dfc87692
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q31.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_init_q31.c
+*
+* Description: Q31 FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @details
+ *
+ * @param[in,out] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed per call.
+ * @return none.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_q31()</code>.
+ */
+
+void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and state array size is (blockSize + numTaps - 1) */
+ memset(pState, 0, (blockSize + ((uint32_t) numTaps - 1u)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q7.c
new file mode 100644
index 000000000..107bfb37f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_init_q7.c
@@ -0,0 +1,94 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_init_q7.c
+*
+* Description: Q7 FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+/**
+ * @param[in,out] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed per call.
+ * @return none
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_q7()</code>.
+ */
+
+void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize)
+{
+
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear the state buffer. The size is always (blockSize + numTaps - 1) */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q7_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_f32.c
new file mode 100644
index 000000000..9f0cd46f3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_f32.c
@@ -0,0 +1,581 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_f32.c
+*
+* Description: FIR interpolation for floating-point sequences.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator
+ *
+ * These functions combine an upsampler (zero stuffer) and an FIR filter.
+ * They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images.
+ * Conceptually, the functions are equivalent to the block diagram below:
+ * \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions"
+ * After upsampling by a factor of <code>L</code>, the signal should be filtered by a lowpass filter with a normalized
+ * cutoff frequency of <code>1/L</code> in order to eliminate high frequency copies of the spectrum.
+ * The user of the function is responsible for providing the filter coefficients.
+ *
+ * The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner.
+ * The upsampler inserts <code>L-1</code> zeros between each sample.
+ * Instead of multiplying by these zero values, the FIR filter is designed to skip them.
+ * This leads to an efficient implementation without any wasted effort.
+ * The functions operate on blocks of input and output data.
+ * <code>pSrc</code> points to an array of <code>blockSize</code> input values and
+ * <code>pDst</code> points to an array of <code>blockSize*L</code> output values.
+ *
+ * The library provides separate functions for Q15, Q31, and floating-point data types.
+ *
+ * \par Algorithm:
+ * The functions use a polyphase filter structure:
+ * <pre>
+ * y[n] = b[0] * x[n] + b[L] * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]
+ * y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]
+ * ...
+ * y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]
+ * </pre>
+ * This approach is more efficient than straightforward upsample-then-filter algorithms.
+ * With this method the computation is reduced by a factor of <code>1/L</code> when compared to using a standard FIR filter.
+ * \par
+ * <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.
+ * <code>numTaps</code> must be a multiple of the interpolation factor <code>L</code> and this is checked by the
+ * initialization functions.
+ * Internally, the function divides the FIR filter's impulse response into shorter filters of length
+ * <code>phaseLength=numTaps/L</code>.
+ * Coefficients are stored in time reversed order.
+ * \par
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to a state array of size <code>blockSize + phaseLength - 1</code>.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ * <pre>
+ * {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}
+ * </pre>
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * - Checks to make sure that the length of the filter is a multiple of the interpolation factor.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * L (interpolation factor), pCoeffs, phaseLength (numTaps / L), pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ * <pre>
+ * arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};
+ * arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};
+ * arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};
+ * </pre>
+ * where <code>L</code> is the interpolation factor; <code>phaseLength=numTaps/L</code> is the
+ * length of each of the shorter FIR filters used internally,
+ * <code>pCoeffs</code> is the address of the coefficient buffer;
+ * <code>pState</code> is the address of the state buffer.
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the FIR interpolate filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+ float32_t sum0; /* Accumulators */
+ float32_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt, j; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+ float32_t acc0, acc1, acc2, acc3;
+ float32_t x1, x2, x3;
+ uint32_t blkCntN4;
+ float32_t c1, c2, c3;
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (phaseLen - 1u);
+
+ /* Initialise blkCnt */
+ blkCnt = blockSize / 4;
+ blkCntN4 = blockSize - (4 * blkCnt);
+
+ /* Samples loop unrolled by 4 */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = (S->L);
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ acc0 = 0.0f;
+ acc1 = 0.0f;
+ acc2 = 0.0f;
+ acc3 = 0.0f;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2u;
+
+ x0 = *(ptr1++);
+ x1 = *(ptr1++);
+ x2 = *(ptr1++);
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x3 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Read the coefficient */
+ c1 = *(ptr2 + S->L);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x1 * c1;
+ acc1 += x2 * c1;
+ acc2 += x3 * c1;
+ acc3 += x0 * c1;
+
+ /* Read the coefficient */
+ c2 = *(ptr2 + S->L * 2);
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x2 * c2;
+ acc1 += x3 * c2;
+ acc2 += x0 * c2;
+ acc3 += x1 * c2;
+
+ /* Read the coefficient */
+ c3 = *(ptr2 + S->L * 3);
+
+ /* Read the input sample */
+ x2 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x3 * c3;
+ acc1 += x0 * c3;
+ acc2 += x1 * c3;
+ acc3 += x2 * c3;
+
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += 4 * S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x3 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += x0 * c0;
+ acc1 += x1 * c0;
+ acc2 += x2 * c0;
+ acc3 += x3 * c0;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* update states for next sample processing */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst = acc0;
+ *(pDst + S->L) = acc1;
+ *(pDst + 2 * S->L) = acc2;
+ *(pDst + 3 * S->L) = acc3;
+
+ pDst++;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 4;
+
+ pDst += S->L * 3;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ while(blkCntN4 > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0.0f;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2u;
+ while(tapCnt > 0u)
+ {
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += x0 * c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum0 += *(ptr1++) * (*ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum0;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCntN4--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (phaseLen - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (phaseLen - 1u) % 0x04u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+
+
+ float32_t sum; /* Accumulator */
+ uint32_t i, blkCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (phaseLen - 1u);
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum = 0.0f;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (i - 1u);
+
+ /* Loop over the polyPhase length */
+ tapCnt = phaseLen;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += *ptr1++ * *ptr2;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = sum;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = phaseLen - 1u;
+
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_f32.c
new file mode 100644
index 000000000..ffcb7e8cf
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_f32.c
@@ -0,0 +1,121 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_init_f32.c
+*
+* Description: Floating-point FIR interpolator initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+ * </pre>
+ * The length of the filter <code>numTaps</code> must be a multiple of the interpolation factor <code>L</code>.
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>(numTaps/L)+blockSize-1</code> words
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_interpolate_f32()</code>.
+ */
+
+arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The filter length must be a multiple of the interpolation factor */
+ if((numTaps % L) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign Interpolation factor */
+ S->L = L;
+
+ /* Assign polyPhaseLength */
+ S->phaseLength = numTaps / L;
+
+ /* Clear state buffer and size of state array is always phaseLength + blockSize - 1 */
+ memset(pState, 0,
+ (blockSize +
+ ((uint32_t) S->phaseLength - 1u)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_q15.c
new file mode 100644
index 000000000..1beeac21c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_q15.c
@@ -0,0 +1,120 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_init_q15.c
+*
+* Description: Q15 FIR interpolator initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+ * </pre>
+ * The length of the filter <code>numTaps</code> must be a multiple of the interpolation factor <code>L</code>.
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>(numTaps/L)+blockSize-1</code> words
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_interpolate_q15()</code>.
+ */
+
+arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The filter length must be a multiple of the interpolation factor */
+ if((numTaps % L) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign Interpolation factor */
+ S->L = L;
+
+ /* Assign polyPhaseLength */
+ S->phaseLength = numTaps / L;
+
+ /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+ memset(pState, 0,
+ (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_q31.c
new file mode 100644
index 000000000..cb2ab0441
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_init_q31.c
@@ -0,0 +1,121 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_init_q31.c
+*
+* Description: Q31 FIR interpolator initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+
+/**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}
+ * </pre>
+ * The length of the filter <code>numTaps</code> must be a multiple of the interpolation factor <code>L</code>.
+ * \par
+ * <code>pState</code> points to the array of state variables.
+ * <code>pState</code> is of length <code>(numTaps/L)+blockSize-1</code> words
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_fir_interpolate_q31()</code>.
+ */
+
+arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ arm_status status;
+
+ /* The filter length must be a multiple of the interpolation factor */
+ if((numTaps % L) != 0u)
+ {
+ /* Set status as ARM_MATH_LENGTH_ERROR */
+ status = ARM_MATH_LENGTH_ERROR;
+ }
+ else
+ {
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign Interpolation factor */
+ S->L = L;
+
+ /* Assign polyPhaseLength */
+ S->phaseLength = numTaps / L;
+
+ /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+ memset(pState, 0,
+ (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ status = ARM_MATH_SUCCESS;
+ }
+
+ return (status);
+
+}
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_q15.c
new file mode 100644
index 000000000..836169237
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_q15.c
@@ -0,0 +1,508 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_q15.c
+*
+* Description: Q15 FIR interpolation.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+ q63_t sum0; /* Accumulators */
+ q15_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt, j, tapCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
+ uint32_t blkCntN2;
+ q63_t acc0, acc1;
+ q15_t x1;
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+ /* Initialise blkCnt */
+ blkCnt = blockSize / 2;
+ blkCntN2 = blockSize - (2 * blkCnt);
+
+ /* Samples loop unrolled by 2 */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = (S->L);
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2u;
+
+ x0 = *(ptr1++);
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x1 *c0;
+ acc1 += (q63_t) x0 *c0;
+
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L * 2);
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L * 3);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x1 *c0;
+ acc1 += (q63_t) x0 *c0;
+
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += 4 * S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* update states for next sample processing */
+ x0 = x1;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst = (q15_t) (__SSAT((acc0 >> 15), 16));
+ *(pDst + S->L) = (q15_t) (__SSAT((acc1 >> 15), 16));
+
+ pDst++;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 2;
+
+ pDst += S->L;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blkCntN2;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2;
+ while(tapCnt > 0u)
+ {
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen & 0x3u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = ((uint32_t) phaseLen - 1u) >> 2u;
+
+ /* copy data */
+ while(i > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ i = ((uint32_t) phaseLen - 1u) % 0x04u;
+
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+}
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+ q63_t sum; /* Accumulator */
+ q15_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt, tapCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength; /* Length of each polyphase filter component */
+
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (phaseLen - 1u);
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (i - 1u);
+
+ /* Loop over the polyPhase length */
+ tapCnt = (uint32_t) phaseLen;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the coefficient */
+ c0 = *ptr2;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *ptr1++;
+
+ /* Perform the multiply-accumulate */
+ sum += ((q31_t) x0 * c0);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Store the result after converting to 1.15 format in the destination buffer */
+ *pDst++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the start of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ i = (uint32_t) phaseLen - 1u;
+
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_q31.c
new file mode 100644
index 000000000..33ecec21d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_interpolate_q31.c
@@ -0,0 +1,504 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_interpolate_q31.c
+*
+* Description: Q31 FIR interpolation.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Interpolate
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by <code>1/(numTaps/L)</code>.
+ * since <code>numTaps/L</code> additions occur per output sample.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+ q63_t sum0; /* Accumulators */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt, j; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+
+ uint32_t blkCntN2;
+ q63_t acc0, acc1;
+ q31_t x1;
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+ /* Initialise blkCnt */
+ blkCnt = blockSize / 2;
+ blkCntN2 = blockSize - (2 * blkCnt);
+
+ /* Samples loop unrolled by 2 */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = (S->L);
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ acc0 = 0;
+ acc1 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2u;
+
+ x0 = *(ptr1++);
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x1 *c0;
+ acc1 += (q63_t) x0 *c0;
+
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L * 2);
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2 + S->L * 3);
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x1 *c0;
+ acc1 += (q63_t) x0 *c0;
+
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += 4 * S->L;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Read the input sample */
+ x1 = *(ptr1++);
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Perform the multiply-accumulate */
+ acc0 += (q63_t) x0 *c0;
+ acc1 += (q63_t) x1 *c0;
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* update states for next sample processing */
+ x0 = x1;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst = (q31_t) (acc0 >> 31);
+ *(pDst + S->L) = (q31_t) (acc1 >> 31);
+
+
+ pDst++;
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 2;
+
+ pDst += S->L;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 2, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blkCntN2;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Address modifier index of coefficient buffer */
+ j = 1u;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum0 = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (S->L - j);
+
+ /* Loop over the polyPhase length. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+ tapCnt = phaseLen >> 2;
+ while(tapCnt > 0u)
+ {
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Upsampling is done by stuffing L-1 zeros between each sample.
+ * So instead of multiplying zeros with coefficients,
+ * Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = phaseLen & 0x3u;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *(ptr1++);
+
+ /* Perform the multiply-accumulate */
+ sum0 += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum0 >> 31);
+
+ /* Increment the address modifier index of coefficient buffer */
+ j++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (phaseLen - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ tapCnt = (phaseLen - 1u) % 0x04u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+
+#else
+
+void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t *ptr1, *ptr2; /* Temporary pointers for state and coefficient buffers */
+
+ /* Run the below code for Cortex-M0 */
+
+ q63_t sum; /* Accumulator */
+ q31_t x0, c0; /* Temporary variables to hold state and coefficient values */
+ uint32_t i, blkCnt; /* Loop counters */
+ uint16_t phaseLen = S->phaseLength, tapCnt; /* Length of each polyphase filter component */
+
+
+ /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+ /* Total number of intput samples */
+ blkCnt = blockSize;
+
+ /* Loop over the blockSize. */
+ while(blkCnt > 0u)
+ {
+ /* Copy new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Loop over the Interpolation factor. */
+ i = S->L;
+
+ while(i > 0u)
+ {
+ /* Set accumulator to zero */
+ sum = 0;
+
+ /* Initialize state pointer */
+ ptr1 = pState;
+
+ /* Initialize coefficient pointer */
+ ptr2 = pCoeffs + (i - 1u);
+
+ tapCnt = phaseLen;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the coefficient */
+ c0 = *(ptr2);
+
+ /* Increment the coefficient pointer by interpolation factor times. */
+ ptr2 += S->L;
+
+ /* Read the input sample */
+ x0 = *ptr1++;
+
+ /* Perform the multiply-accumulate */
+ sum += (q63_t) x0 *c0;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is in the accumulator, store in the destination buffer. */
+ *pDst++ = (q31_t) (sum >> 31);
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 1
+ * to process the next group of interpolation factor number samples */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = phaseLen - 1u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /**
+ * @} end of FIR_Interpolate group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_f32.c
new file mode 100644
index 000000000..0e9990b15
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_f32.c
@@ -0,0 +1,506 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_f32.c
+*
+* Description: Processing function for the floating-point FIR Lattice filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters
+ *
+ * This set of functions implements Finite Impulse Response (FIR) lattice filters
+ * for Q15, Q31 and floating-point data types. Lattice filters are used in a
+ * variety of adaptive filter applications. The filter structure is feedforward and
+ * the net impulse response is finite length.
+ * The functions operate on blocks
+ * of input and output data and each call to the function processes
+ * <code>blockSize</code> samples through the filter. <code>pSrc</code> and
+ * <code>pDst</code> point to input and output arrays containing <code>blockSize</code> values.
+ *
+ * \par Algorithm:
+ * \image html FIRLattice.gif "Finite Impulse Response Lattice filter"
+ * The following difference equation is implemented:
+ * <pre>
+ * f0[n] = g0[n] = x[n]
+ * fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M
+ * gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M
+ * y[n] = fM[n]
+ * </pre>
+ * \par
+ * <code>pCoeffs</code> points to tha array of reflection coefficients of size <code>numStages</code>.
+ * Reflection Coefficients are stored in the following order.
+ * \par
+ * <pre>
+ * {k1, k2, ..., kM}
+ * </pre>
+ * where M is number of stages
+ * \par
+ * <code>pState</code> points to a state array of size <code>numStages</code>.
+ * The state variables (g values) hold previous inputs and are stored in the following order.
+ * <pre>
+ * {g0[n], g1[n], g2[n] ...gM-1[n]}
+ * </pre>
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pCoeffs, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:
+ * <pre>
+ *arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};
+ *arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};
+ *arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};
+ * </pre>
+ * \par
+ * where <code>numStages</code> is the number of stages in the filter; <code>pState</code> is the address of the state buffer;
+ * <code>pCoeffs</code> is the address of the coefficient buffer.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the FIR Lattice filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *px; /* temporary state pointer */
+ float32_t *pk; /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t fcurr1, fnext1, gcurr1, gnext1; /* temporary variables for first sample in loop unrolling */
+ float32_t fcurr2, fnext2, gnext2; /* temporary variables for second sample in loop unrolling */
+ float32_t fcurr3, fnext3, gnext3; /* temporary variables for third sample in loop unrolling */
+ float32_t fcurr4, fnext4, gnext4; /* temporary variables for fourth sample in loop unrolling */
+ uint32_t numStages = S->numStages; /* Number of stages in the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ gcurr1 = 0.0f;
+ pState = &S->pState[0];
+
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+ /* Read two samples from input buffer */
+ /* f0(n) = x(n) */
+ fcurr1 = *pSrc++;
+ fcurr2 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Read g0(n-1) from state */
+ gcurr1 = *px;
+
+ /* Process first sample for first tap */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (fcurr1 * (*pk)) + gcurr1;
+
+ /* Process second sample for first tap */
+ /* for sample 2 processing */
+ fnext2 = fcurr2 + ((*pk) * fcurr1);
+ gnext2 = (fcurr2 * (*pk)) + fcurr1;
+
+ /* Read next two samples from input buffer */
+ /* f0(n+2) = x(n+2) */
+ fcurr3 = *pSrc++;
+ fcurr4 = *pSrc++;
+
+ /* Copy only last input samples into the state buffer
+ which will be used for next four samples processing */
+ *px++ = fcurr4;
+
+ /* Process third sample for first tap */
+ fnext3 = fcurr3 + ((*pk) * fcurr2);
+ gnext3 = (fcurr3 * (*pk)) + fcurr2;
+
+ /* Process fourth sample for first tap */
+ fnext4 = fcurr4 + ((*pk) * fcurr3);
+ gnext4 = (fcurr4 * (*pk++)) + fcurr3;
+
+ /* Update of f values for next coefficient set processing */
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+ fcurr3 = fnext3;
+ fcurr4 = fnext4;
+
+ /* Loop unrolling. Process 4 taps at a time . */
+ stageCnt = (numStages - 1u) >> 2u;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numStages-3 coefficients. */
+
+ /* Process 2nd, 3rd, 4th and 5th taps ... here */
+ while(stageCnt > 0u)
+ {
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurr1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext4;
+
+ /* Process first sample for 2nd, 6th .. tap */
+ /* Sample processing for K2, K6.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* Process second sample for 2nd, 6th .. tap */
+ /* for sample 2 processing */
+ fnext2 = fcurr2 + ((*pk) * gnext1);
+ /* Process third sample for 2nd, 6th .. tap */
+ fnext3 = fcurr3 + ((*pk) * gnext2);
+ /* Process fourth sample for 2nd, 6th .. tap */
+ fnext4 = fcurr4 + ((*pk) * gnext3);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ /* Calculation of state values for next stage */
+ gnext4 = (fcurr4 * (*pk)) + gnext3;
+ gnext3 = (fcurr3 * (*pk)) + gnext2;
+ gnext2 = (fcurr2 * (*pk)) + gnext1;
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurr1 = *px;
+
+ /* save g2(n) in state buffer */
+ *px++ = gnext4;
+
+ /* Sample processing for K3, K7.... */
+ /* Process first sample for 3rd, 7th .. tap */
+ /* f3(n) = f2(n) + K3 * g2(n-1) */
+ fcurr1 = fnext1 + ((*pk) * gcurr1);
+ /* Process second sample for 3rd, 7th .. tap */
+ fcurr2 = fnext2 + ((*pk) * gnext1);
+ /* Process third sample for 3rd, 7th .. tap */
+ fcurr3 = fnext3 + ((*pk) * gnext2);
+ /* Process fourth sample for 3rd, 7th .. tap */
+ fcurr4 = fnext4 + ((*pk) * gnext3);
+
+ /* Calculation of state values for next stage */
+ /* g3(n) = f2(n) * K3 + g2(n-1) */
+ gnext4 = (fnext4 * (*pk)) + gnext3;
+ gnext3 = (fnext3 * (*pk)) + gnext2;
+ gnext2 = (fnext2 * (*pk)) + gnext1;
+ gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurr1 = *px;
+
+ /* save g3(n) in state buffer */
+ *px++ = gnext4;
+
+ /* Sample processing for K4, K8.... */
+ /* Process first sample for 4th, 8th .. tap */
+ /* f4(n) = f3(n) + K4 * g3(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* Process second sample for 4th, 8th .. tap */
+ /* for sample 2 processing */
+ fnext2 = fcurr2 + ((*pk) * gnext1);
+ /* Process third sample for 4th, 8th .. tap */
+ fnext3 = fcurr3 + ((*pk) * gnext2);
+ /* Process fourth sample for 4th, 8th .. tap */
+ fnext4 = fcurr4 + ((*pk) * gnext3);
+
+ /* g4(n) = f3(n) * K4 + g3(n-1) */
+ /* Calculation of state values for next stage */
+ gnext4 = (fcurr4 * (*pk)) + gnext3;
+ gnext3 = (fcurr3 * (*pk)) + gnext2;
+ gnext2 = (fcurr2 * (*pk)) + gnext1;
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurr1 = *px;
+
+ /* save g4(n) in state buffer */
+ *px++ = gnext4;
+
+ /* Sample processing for K5, K9.... */
+ /* Process first sample for 5th, 9th .. tap */
+ /* f5(n) = f4(n) + K5 * g4(n-1) */
+ fcurr1 = fnext1 + ((*pk) * gcurr1);
+ /* Process second sample for 5th, 9th .. tap */
+ fcurr2 = fnext2 + ((*pk) * gnext1);
+ /* Process third sample for 5th, 9th .. tap */
+ fcurr3 = fnext3 + ((*pk) * gnext2);
+ /* Process fourth sample for 5th, 9th .. tap */
+ fcurr4 = fnext4 + ((*pk) * gnext3);
+
+ /* Calculation of state values for next stage */
+ /* g5(n) = f4(n) * K5 + g4(n-1) */
+ gnext4 = (fnext4 * (*pk)) + gnext3;
+ gnext3 = (fnext3 * (*pk)) + gnext2;
+ gnext2 = (fnext2 * (*pk)) + gnext1;
+ gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+ stageCnt--;
+ }
+
+ /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+ stageCnt = (numStages - 1u) % 0x4u;
+
+ while(stageCnt > 0u)
+ {
+ gcurr1 = *px;
+
+ /* save g value in state buffer */
+ *px++ = gnext4;
+
+ /* Process four samples for last three taps here */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ fnext2 = fcurr2 + ((*pk) * gnext1);
+ fnext3 = fcurr3 + ((*pk) * gnext2);
+ fnext4 = fcurr4 + ((*pk) * gnext3);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext4 = (fcurr4 * (*pk)) + gnext3;
+ gnext3 = (fcurr3 * (*pk)) + gnext2;
+ gnext2 = (fcurr2 * (*pk)) + gnext1;
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+ /* Update of f values for next coefficient set processing */
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+ fcurr3 = fnext3;
+ fcurr4 = fnext4;
+
+ stageCnt--;
+
+ }
+
+ /* The results in the 4 accumulators, store in the destination buffer. */
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr1;
+ *pDst++ = fcurr2;
+ *pDst++ = fcurr3;
+ *pDst++ = fcurr4;
+
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr1 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g2(n) from state buffer */
+ gcurr1 = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+ /* save g1(n) in state buffer */
+ *px++ = fcurr1;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g2(n) from state buffer */
+ gcurr1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext1;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = fcurr1 + ((*pk) * gcurr1);
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr1;
+
+ blkCnt--;
+
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t fcurr, fnext, gcurr, gnext; /* temporary variables */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = pCoeffs;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n-1) from state buffer */
+ gcurr = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext = fcurr + ((*pk) * gcurr);
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext = (fcurr * (*pk++)) + gcurr;
+
+ /* save f0(n) in state buffer */
+ *px++ = fcurr;
+
+ /* f1(n) is saved in fcurr
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g2(n) from state buffer */
+ gcurr = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext = fcurr + ((*pk) * gcurr);
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext = (fcurr * (*pk++)) + gcurr;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr;
+
+ blkCnt--;
+
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_f32.c
new file mode 100644
index 000000000..0580f4032
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_f32.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_init_f32.c
+*
+* Description: Floating-point FIR Lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always numStages */
+ memset(pState, 0, (numStages) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_q15.c
new file mode 100644
index 000000000..cb6a8eadc
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_q15.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_init_q15.c
+*
+* Description: Q15 FIR Lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always numStages */
+ memset(pState, 0, (numStages) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_q31.c
new file mode 100644
index 000000000..51acb790a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_init_q31.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_init_q31.c
+*
+* Description: Q31 FIR lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always numStages */
+ memset(pState, 0, (numStages) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_q15.c
new file mode 100644
index 000000000..06dfff9cb
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_q15.c
@@ -0,0 +1,536 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_q15.c
+*
+* Description: Q15 FIR lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+
+/**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *px; /* temporary state pointer */
+ q15_t *pk; /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t fcurnt1, fnext1, gcurnt1 = 0, gnext1; /* temporary variables for first sample in loop unrolling */
+ q31_t fcurnt2, fnext2, gnext2; /* temporary variables for second sample in loop unrolling */
+ q31_t fcurnt3, fnext3, gnext3; /* temporary variables for third sample in loop unrolling */
+ q31_t fcurnt4, fnext4, gnext4; /* temporary variables for fourth sample in loop unrolling */
+ uint32_t numStages = S->numStages; /* Number of stages in the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+ /* Read two samples from input buffer */
+ /* f0(n) = x(n) */
+ fcurnt1 = *pSrc++;
+ fcurnt2 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Read g0(n-1) from state */
+ gcurnt1 = *px;
+
+ /* Process first sample for first tap */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ /* Process second sample for first tap */
+ /* for sample 2 processing */
+ fnext2 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + fcurnt2;
+ fnext2 = __SSAT(fnext2, 16);
+
+ gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt1;
+ gnext2 = __SSAT(gnext2, 16);
+
+
+ /* Read next two samples from input buffer */
+ /* f0(n+2) = x(n+2) */
+ fcurnt3 = *pSrc++;
+ fcurnt4 = *pSrc++;
+
+ /* Copy only last input samples into the state buffer
+ which is used for next four samples processing */
+ *px++ = (q15_t) fcurnt4;
+
+ /* Process third sample for first tap */
+ fnext3 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt3;
+ fnext3 = __SSAT(fnext3, 16);
+ gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ /* Process fourth sample for first tap */
+ fnext4 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt4;
+ fnext4 = __SSAT(fnext4, 16);
+ gnext4 = (q31_t) ((fcurnt4 * (*pk++)) >> 15u) + fcurnt3;
+ gnext4 = __SSAT(gnext4, 16);
+
+ /* Update of f values for next coefficient set processing */
+ fcurnt1 = fnext1;
+ fcurnt2 = fnext2;
+ fcurnt3 = fnext3;
+ fcurnt4 = fnext4;
+
+
+ /* Loop unrolling. Process 4 taps at a time . */
+ stageCnt = (numStages - 1u) >> 2;
+
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numStages-3 coefficients. */
+
+ /* Process 2nd, 3rd, 4th and 5th taps ... here */
+ while(stageCnt > 0u)
+ {
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurnt1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Process first sample for 2nd, 6th .. tap */
+ /* Sample processing for K2, K6.... */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+
+ /* Process second sample for 2nd, 6th .. tap */
+ /* for sample 2 processing */
+ fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+ fnext2 = __SSAT(fnext2, 16);
+ /* Process third sample for 2nd, 6th .. tap */
+ fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+ fnext3 = __SSAT(fnext3, 16);
+ /* Process fourth sample for 2nd, 6th .. tap */
+ /* fnext4 = fcurnt4 + (*pk) * gnext3; */
+ fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+ fnext4 = __SSAT(fnext4, 16);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ /* Calculation of state values for next stage */
+ gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+ gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+
+ gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurnt1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Sample processing for K3, K7.... */
+ /* Process first sample for 3rd, 7th .. tap */
+ /* f3(n) = f2(n) + K3 * g2(n-1) */
+ fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+ fcurnt1 = __SSAT(fcurnt1, 16);
+
+ /* Process second sample for 3rd, 7th .. tap */
+ fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+ fcurnt2 = __SSAT(fcurnt2, 16);
+
+ /* Process third sample for 3rd, 7th .. tap */
+ fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+ fcurnt3 = __SSAT(fcurnt3, 16);
+
+ /* Process fourth sample for 3rd, 7th .. tap */
+ fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+ fcurnt4 = __SSAT(fcurnt4, 16);
+
+ /* Calculation of state values for next stage */
+ /* g3(n) = f2(n) * K3 + g2(n-1) */
+ gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+
+ gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+
+ gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ /* Read g1(n-1), g3(n-1) .... from state */
+ gcurnt1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Sample processing for K4, K8.... */
+ /* Process first sample for 4th, 8th .. tap */
+ /* f4(n) = f3(n) + K4 * g3(n-1) */
+ fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+ /* Process second sample for 4th, 8th .. tap */
+ /* for sample 2 processing */
+ fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+ fnext2 = __SSAT(fnext2, 16);
+
+ /* Process third sample for 4th, 8th .. tap */
+ fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+ fnext3 = __SSAT(fnext3, 16);
+
+ /* Process fourth sample for 4th, 8th .. tap */
+ fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+ fnext4 = __SSAT(fnext4, 16);
+
+ /* g4(n) = f3(n) * K4 + g3(n-1) */
+ /* Calculation of state values for next stage */
+ gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+
+ gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+
+ gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+ gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+
+ /* Read g2(n-1), g4(n-1) .... from state */
+ gcurnt1 = *px;
+
+ /* save g4(n) in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Sample processing for K5, K9.... */
+ /* Process first sample for 5th, 9th .. tap */
+ /* f5(n) = f4(n) + K5 * g4(n-1) */
+ fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+ fcurnt1 = __SSAT(fcurnt1, 16);
+
+ /* Process second sample for 5th, 9th .. tap */
+ fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+ fcurnt2 = __SSAT(fcurnt2, 16);
+
+ /* Process third sample for 5th, 9th .. tap */
+ fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+ fcurnt3 = __SSAT(fcurnt3, 16);
+
+ /* Process fourth sample for 5th, 9th .. tap */
+ fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+ fcurnt4 = __SSAT(fcurnt4, 16);
+
+ /* Calculation of state values for next stage */
+ /* g5(n) = f4(n) * K5 + g4(n-1) */
+ gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+ gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+ gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+ gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ stageCnt--;
+ }
+
+ /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+ stageCnt = (numStages - 1u) % 0x4u;
+
+ while(stageCnt > 0u)
+ {
+ gcurnt1 = *px;
+
+ /* save g value in state buffer */
+ *px++ = (q15_t) gnext4;
+
+ /* Process four samples for last three taps here */
+ fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+ fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+ fnext2 = __SSAT(fnext2, 16);
+
+ fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+ fnext3 = __SSAT(fnext3, 16);
+
+ fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+ fnext4 = __SSAT(fnext4, 16);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+ gnext4 = __SSAT(gnext4, 16);
+ gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+ gnext3 = __SSAT(gnext3, 16);
+ gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+ gnext2 = __SSAT(gnext2, 16);
+ gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ /* Update of f values for next coefficient set processing */
+ fcurnt1 = fnext1;
+ fcurnt2 = fnext2;
+ fcurnt3 = fnext3;
+ fcurnt4 = fnext4;
+
+ stageCnt--;
+
+ }
+
+ /* The results in the 4 accumulators, store in the destination buffer. */
+ /* y(n) = fN(n) */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = __PKHBT(fcurnt1, fcurnt2, 16);
+ *__SIMD32(pDst)++ = __PKHBT(fcurnt3, fcurnt4, 16);
+
+#else
+
+ *__SIMD32(pDst)++ = __PKHBT(fcurnt2, fcurnt1, 16);
+ *__SIMD32(pDst)++ = __PKHBT(fcurnt4, fcurnt3, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurnt1 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g2(n) from state buffer */
+ gcurnt1 = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) fcurnt1;
+
+ /* f1(n) is saved in fcurnt1
+ for next stage processing */
+ fcurnt1 = fnext1;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g2(n) from state buffer */
+ gcurnt1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = (q15_t) gnext1;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+ fnext1 = __SSAT(fnext1, 16);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+ gnext1 = __SSAT(gnext1, 16);
+
+
+ /* f1(n) is saved in fcurnt1
+ for next stage processing */
+ fcurnt1 = fnext1;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = __SSAT(fcurnt1, 16);
+
+
+ blkCnt--;
+
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t fcurnt, fnext, gcurnt, gnext; /* temporary variables */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurnt = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n-1) from state buffer */
+ gcurnt = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+ fnext = __SSAT(fnext, 16);
+
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+ gnext = __SSAT(gnext, 16);
+
+ /* save f0(n) in state buffer */
+ *px++ = (q15_t) fcurnt;
+
+ /* f1(n) is saved in fcurnt
+ for next stage processing */
+ fcurnt = fnext;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g1(n-1) from state buffer */
+ gcurnt = *px;
+
+ /* save g0(n-1) in state buffer */
+ *px++ = (q15_t) gnext;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+ fnext = __SSAT(fnext, 16);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+ gnext = __SSAT(gnext, 16);
+
+
+ /* f1(n) is saved in fcurnt
+ for next stage processing */
+ fcurnt = fnext;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = __SSAT(fcurnt, 16);
+
+
+ blkCnt--;
+
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_q31.c
new file mode 100644
index 000000000..c0ddf9693
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_lattice_q31.c
@@ -0,0 +1,353 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_lattice_q31.c
+*
+* Description: Q31 FIR lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Lattice
+ * @{
+ */
+
+
+/**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *px; /* temporary state pointer */
+ q31_t *pk; /* temporary coefficient pointer */
+ q31_t fcurr1, fnext1, gcurr1 = 0, gnext1; /* temporary variables for first sample in loop unrolling */
+ q31_t fcurr2, fnext2, gnext2; /* temporary variables for second sample in loop unrolling */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+ q31_t k;
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize >> 1u;
+
+ /* First part of the processing with loop unrolling. Compute 2 outputs at a time.
+ a second loop below computes the remaining 1 sample. */
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr1 = *pSrc++;
+
+ /* f0(n) = x(n) */
+ fcurr2 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n - 1) from state buffer */
+ gcurr1 = *px;
+
+ /* Read the reflection coefficient */
+ k = *pk++;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+ fnext1 = fcurr1 + (fnext1 << 1u);
+ gnext1 = gcurr1 + (gnext1 << 1u);
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext2 = (q31_t) (((q63_t) fcurr1 * k) >> 32);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
+ fnext2 = fcurr2 + (fnext2 << 1u);
+ gnext2 = fcurr1 + (gnext2 << 1u);
+
+ /* save g1(n) in state buffer */
+ *px++ = fcurr2;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+
+ /* Read the reflection coefficient */
+ k = *pk++;
+
+ /* read g2(n) from state buffer */
+ gcurr1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext2;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+ fnext2 = (q31_t) (((q63_t) gnext1 * k) >> 32);
+
+ fnext1 = fcurr1 + (fnext1 << 1u);
+ fnext2 = fcurr2 + (fnext2 << 1u);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext2 = (q31_t) (((q63_t) fcurr2 * (k)) >> 32);
+ gnext2 = gnext1 + (gnext2 << 1u);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+ gnext1 = gcurr1 + (gnext1 << 1u);
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+ fcurr2 = fnext2;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr1;
+ *pDst++ = fcurr2;
+
+ blkCnt--;
+
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x2u;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr1 = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n - 1) from state buffer */
+ gcurr1 = *px;
+
+ /* Read the reflection coefficient */
+ k = *pk++;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+ fnext1 = fcurr1 + (fnext1 << 1u);
+
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+ gnext1 = gcurr1 + (gnext1 << 1u);
+
+ /* save g1(n) in state buffer */
+ *px++ = fcurr1;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* Read the reflection coefficient */
+ k = *pk++;
+
+ /* read g2(n) from state buffer */
+ gcurr1 = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext1;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext1 = (q31_t) (((q63_t) gcurr1 * k) >> 32);
+ fnext1 = fcurr1 + (fnext1 << 1u);
+
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext1 = (q31_t) (((q63_t) fcurr1 * (k)) >> 32);
+ gnext1 = gcurr1 + (gnext1 << 1u);
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr1 = fnext1;
+
+ stageCnt--;
+
+ }
+
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr1;
+
+ blkCnt--;
+
+ }
+
+
+}
+
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *px; /* temporary state pointer */
+ q31_t *pk; /* temporary coefficient pointer */
+ q31_t fcurr, fnext, gcurr, gnext; /* temporary variables */
+ uint32_t numStages = S->numStages; /* Length of the filter */
+ uint32_t blkCnt, stageCnt; /* temporary variables for counts */
+
+ pState = &S->pState[0];
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* f0(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize coeff pointer */
+ pk = (pCoeffs);
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* read g0(n-1) from state buffer */
+ gcurr = *px;
+
+ /* for sample 1 processing */
+ /* f1(n) = f0(n) + K1 * g0(n-1) */
+ fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+ /* g1(n) = f0(n) * K1 + g0(n-1) */
+ gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+ /* save g1(n) in state buffer */
+ *px++ = fcurr;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt = (numStages - 1u);
+
+ /* stage loop */
+ while(stageCnt > 0u)
+ {
+ /* read g2(n) from state buffer */
+ gcurr = *px;
+
+ /* save g1(n) in state buffer */
+ *px++ = gnext;
+
+ /* Sample processing for K2, K3.... */
+ /* f2(n) = f1(n) + K2 * g1(n-1) */
+ fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+ /* g2(n) = f1(n) * K2 + g1(n-1) */
+ gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+
+ /* f1(n) is saved in fcurr1
+ for next stage processing */
+ fcurr = fnext;
+
+ stageCnt--;
+
+ }
+
+ /* y(n) = fN(n) */
+ *pDst++ = fcurr;
+
+ blkCnt--;
+
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+/**
+ * @} end of FIR_Lattice group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q15.c
new file mode 100644
index 000000000..840507fb7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q15.c
@@ -0,0 +1,691 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_q15.c
+*
+* Description: Q15 FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ *
+ * \par Restrictions
+ * If the silicon does not support unaligned memory access enable the macro UNALIGNED_SUPPORT_DISABLE
+ * In this case input, output, state buffers should be aligned by 32-bit
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ *
+ * \par
+ * Refer to the function <code>arm_fir_fast_q15()</code> for a faster but less precise implementation of this function.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+/* Run the below code for Cortex-M4 and Cortex-M3 */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+
+void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px1; /* Temporary q15 pointer for state buffer */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t x0, x1, x2, x3, c0; /* Temporary variables to hold SIMD state and coefficient values */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer.
+ ** Use 32-bit SIMD to move the 16-bit data. Only requires two copies. */
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer of type q15 */
+ px1 = pState;
+
+ /* Initialize coeff pointer of type q31 */
+ pb = pCoeffs;
+
+ /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */
+ x0 = _SIMD32_OFFSET(px1);
+
+ /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
+ x1 = _SIMD32_OFFSET(px1 + 1u);
+
+ px1 += 2u;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-4 coefficients. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+ acc1 = __SMLALD(x1, c0, acc1);
+
+ /* Read state x[n-N-2], x[n-N-3] */
+ x2 = _SIMD32_OFFSET(px1);
+
+ /* Read state x[n-N-3], x[n-N-4] */
+ x3 = _SIMD32_OFFSET(px1 + 1u);
+
+ /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+ acc2 = __SMLALD(x2, c0, acc2);
+
+ /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+ acc3 = __SMLALD(x3, c0, acc3);
+
+ /* Read coefficients b[N-2], b[N-3] */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+ acc0 = __SMLALD(x2, c0, acc0);
+
+ /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+ acc1 = __SMLALD(x3, c0, acc1);
+
+ /* Read state x[n-N-4], x[n-N-5] */
+ x0 = _SIMD32_OFFSET(px1 + 2u);
+
+ /* Read state x[n-N-5], x[n-N-6] */
+ x1 = _SIMD32_OFFSET(px1 + 3u);
+
+ /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+ acc2 = __SMLALD(x0, c0, acc2);
+
+ /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+ acc3 = __SMLALD(x1, c0, acc3);
+
+ px1 += 4u;
+
+ tapCnt--;
+
+ }
+
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps.
+ ** This is always be 2 taps since the filter length is even. */
+ if((numTaps & 0x3u) != 0u)
+ {
+ /* Read 2 coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Fetch 4 state variables */
+ x2 = _SIMD32_OFFSET(px1);
+
+ x3 = _SIMD32_OFFSET(px1 + 1u);
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ px1 += 2u;
+
+ acc1 = __SMLALD(x1, c0, acc1);
+ acc2 = __SMLALD(x2, c0, acc2);
+ acc3 = __SMLALD(x3, c0, acc3);
+ }
+
+ /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+ while(blkCnt > 0u)
+ {
+ /* Copy two samples into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer of type q15 */
+ px1 = pState;
+
+ /* Initialize coeff pointer of type q31 */
+ pb = pCoeffs;
+
+ tapCnt = numTaps >> 1;
+
+ do
+ {
+
+ c0 = *__SIMD32(pb)++;
+ x0 = *__SIMD32(px1)++;
+
+ acc0 = __SMLALD(x0, c0, acc0);
+ tapCnt--;
+ }
+ while(tapCnt > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Copy state values to start of state buffer */
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy remaining data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+#else /* UNALIGNED_SUPPORT_DISABLE */
+
+void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q63_t acc0, acc1, acc2, acc3; /* Accumulators */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q15_t *px; /* Temporary q31 pointer for SIMD state buffer accesses */
+ q31_t x0, x1, x2, c0; /* Temporary variables to hold SIMD state and coefficient values */
+ uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer.
+ ** Use 32-bit SIMD to move the 16-bit data. Only requires two copies. */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Typecast q15_t pointer to q31_t pointer for state reading in q31_t */
+ px = pState;
+
+ /* Typecast q15_t pointer to q31_t pointer for coefficient reading in q31_t */
+ pb = pCoeffs;
+
+ /* Read the first two samples from the state buffer: x[n-N], x[n-N-1] */
+ x0 = *__SIMD32(px)++;
+
+ /* Read the third and forth samples from the state buffer: x[n-N-2], x[n-N-3] */
+ x2 = *__SIMD32(px)++;
+
+ /* Loop over the number of taps. Unroll by a factor of 4.
+ ** Repeat until we've computed numTaps-(numTaps%4) coefficients. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0)
+ {
+ /* Read the first two coefficients using SIMD: b[N] and b[N-1] coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ acc0 = __SMLALD(x0, c0, acc0);
+
+ /* acc2 += b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+ acc2 = __SMLALD(x2, c0, acc2);
+
+ /* pack x[n-N-1] and x[n-N-2] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* Read state x[n-N-4], x[n-N-5] */
+ x0 = _SIMD32_OFFSET(px);
+
+ /* acc1 += b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* pack x[n-N-3] and x[n-N-4] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x0, x2, 0);
+#else
+ x1 = __PKHBT(x2, x0, 0);
+#endif
+
+ /* acc3 += b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ /* Read coefficients b[N-2], b[N-3] */
+ c0 = *__SIMD32(pb)++;
+
+ /* acc0 += b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+ acc0 = __SMLALD(x2, c0, acc0);
+
+ /* Read state x[n-N-6], x[n-N-7] with offset */
+ x2 = _SIMD32_OFFSET(px + 2u);
+
+ /* acc2 += b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+ acc2 = __SMLALD(x0, c0, acc2);
+
+ /* acc1 += b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* pack x[n-N-5] and x[n-N-6] */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* acc3 += b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+ acc3 = __SMLALDX(x1, c0, acc3);
+
+ /* Update state pointer for next state reading */
+ px += 4u;
+
+ /* Decrement tap count */
+ tapCnt--;
+
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps.
+ ** This is always be 2 taps since the filter length is even. */
+ if((numTaps & 0x3u) != 0u)
+ {
+
+ /* Read last two coefficients */
+ c0 = *__SIMD32(pb)++;
+
+ /* Perform the multiply-accumulates */
+ acc0 = __SMLALD(x0, c0, acc0);
+ acc2 = __SMLALD(x2, c0, acc2);
+
+ /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x2, x0, 0);
+#else
+ x1 = __PKHBT(x0, x2, 0);
+#endif
+
+ /* Read last state variables */
+ x0 = *__SIMD32(px);
+
+ /* Perform the multiply-accumulates */
+ acc1 = __SMLALDX(x1, c0, acc1);
+
+ /* pack state variables */
+#ifndef ARM_MATH_BIG_ENDIAN
+ x1 = __PKHBT(x0, x2, 0);
+#else
+ x1 = __PKHBT(x2, x0, 0);
+#endif
+
+ /* Perform the multiply-accumulates */
+ acc3 = __SMLALDX(x1, c0, acc3);
+ }
+
+ /* The results in the 4 accumulators are in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+
+ *__SIMD32(pDst)++ =
+ __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+ while(blkCnt > 0u)
+ {
+ /* Copy two samples into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Use SIMD to hold states and coefficients */
+ px = pState;
+ pb = pCoeffs;
+
+ tapCnt = numTaps >> 1u;
+
+ do
+ {
+ acc0 += (q31_t) * px++ * *pb++;
+ acc0 += (q31_t) * px++ * *pb++;
+ tapCnt--;
+ }
+ while(tapCnt > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.15 with saturation.
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy remaining data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#else /* ARM_MATH_CM0_FAMILY */
+
+
+/* Run the below code for Cortex-M0 */
+
+void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+
+
+
+ q15_t *px; /* Temporary pointer for state buffer */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ q63_t acc; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Number of nTaps in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initialize blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = pCoeffs;
+
+ tapCnt = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+ acc += (q31_t) * px++ * *pb++;
+ tapCnt--;
+ } while(tapCnt > 0u);
+
+ /* The result is in 2.30 format. Convert to 1.15
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q15_t) __SSAT((acc >> 15u), 16);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy numTaps number of values */
+ tapCnt = (numTaps - 1u);
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q31.c
new file mode 100644
index 000000000..dc43626b1
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q31.c
@@ -0,0 +1,365 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_q31.c
+*
+* Description: Q31 FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * Refer to the function <code>arm_fir_fast_q31()</code> for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.
+ */
+
+void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t x0, x1, x2; /* Temporary variables to hold state */
+ q31_t c0; /* Temporary variable to hold coefficient value */
+ q31_t *px; /* Temporary pointer for state */
+ q31_t *pb; /* Temporary pointer for coefficient buffer */
+ q63_t acc0, acc1, acc2; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt, tapCntN3; /* Loop counters */
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize / 3;
+ blockSize = blockSize - (3 * blkCnt);
+
+ tapCnt = numTaps / 3;
+ tapCntN3 = numTaps - (3 * tapCnt);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy three new input samples into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Read the first two samples from the state buffer:
+ * x[n-numTaps], x[n-numTaps-1] */
+ x0 = *(px++);
+ x1 = *(px++);
+
+ /* Loop unrolling. Process 3 taps at a time. */
+ i = tapCnt;
+
+ while(i > 0u)
+ {
+ /* Read the b[numTaps] coefficient */
+ c0 = *pb;
+
+ /* Read x[n-numTaps-2] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q63_t) x0 * c0);
+ acc1 += ((q63_t) x1 * c0);
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Read the coefficient and state */
+ c0 = *(pb + 1u);
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q63_t) x1 * c0);
+ acc1 += ((q63_t) x2 * c0);
+ acc2 += ((q63_t) x0 * c0);
+
+ /* Read the coefficient and state */
+ c0 = *(pb + 2u);
+ x1 = *(px++);
+
+ /* update coefficient pointer */
+ pb += 3u;
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q63_t) x2 * c0);
+ acc1 += ((q63_t) x0 * c0);
+ acc2 += ((q63_t) x1 * c0);
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* If the filter length is not a multiple of 3, compute the remaining filter taps */
+
+ i = tapCntN3;
+
+ while(i > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q63_t) x0 * c0);
+ acc1 += ((q63_t) x1 * c0);
+ acc2 += ((q63_t) x2 * c0);
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 3 to process the next group of 3 samples */
+ pState = pState + 3;
+
+ /* The results in the 3 accumulators are in 2.30 format. Convert to 1.31
+ ** Then store the 3 outputs in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 >> 31u);
+ *pDst++ = (q31_t) (acc1 >> 31u);
+ *pDst++ = (q31_t) (acc2 >> 31u);
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 3, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+
+ while(blockSize > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = (pCoeffs);
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ acc0 += (q63_t) * (px++) * (*(pb++));
+ i--;
+ } while(i > 0u);
+
+ /* The result is in 2.62 format. Convert to 1.31
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q31_t) (acc0 >> 31u);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blockSize--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ q31_t *px; /* Temporary pointer for state */
+ q31_t *pb; /* Temporary pointer for coefficient buffer */
+ q63_t acc; /* Accumulator */
+ uint32_t numTaps = S->numTaps; /* Length of the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+ /* S->pState buffer contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initialize blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = pCoeffs;
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+ acc += (q63_t) * px++ * *pb++;
+ i--;
+ } while(i > 0u);
+
+ /* The result is in 2.62 format. Convert to 1.31
+ ** Then store the output in the destination buffer. */
+ *pDst++ = (q31_t) (acc >> 31u);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the starting of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy numTaps number of values */
+ tapCnt = numTaps - 1u;
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q7.c
new file mode 100644
index 000000000..e7cd81e2c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_q7.c
@@ -0,0 +1,390 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_q7.c
+*
+* Description: Q7 FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR
+ * @{
+ */
+
+/**
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * The accumulator is converted to 18.7 format by discarding the low 7 bits.
+ * Finally, the result is truncated to 1.7 format.
+ */
+
+void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t *pState = S->pState; /* State pointer */
+ q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q7_t *pStateCurnt; /* Points to the current sample of the state */
+ q7_t x0, x1, x2, x3; /* Temporary variables to hold state */
+ q7_t c0; /* Temporary variable to hold coefficient value */
+ q7_t *px; /* Temporary pointer for state */
+ q7_t *pb; /* Temporary pointer for coefficient buffer */
+ q31_t acc0, acc1, acc2, acc3; /* Accumulators */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t i, tapCnt, blkCnt; /* Loop counters */
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Apply loop unrolling and compute 4 output values simultaneously.
+ * The variables acc0 ... acc3 hold output values that are being computed:
+ *
+ * acc0 = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]
+ * acc1 = b[numTaps-1] * x[n-numTaps] + b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]
+ * acc2 = b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] + b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]
+ * acc3 = b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps] +...+ b[0] * x[3]
+ */
+ blkCnt = blockSize >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Copy four new input samples into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set all accumulators to zero */
+ acc0 = 0;
+ acc1 = 0;
+ acc2 = 0;
+ acc3 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Read the first three samples from the state buffer:
+ * x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+ x0 = *(px++);
+ x1 = *(px++);
+ x2 = *(px++);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+ i = tapCnt;
+
+ while(i > 0u)
+ {
+ /* Read the b[numTaps] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-3] sample */
+ x3 = *(px++);
+
+ /* acc0 += b[numTaps] * x[n-numTaps] */
+ acc0 += ((q15_t) x0 * c0);
+
+ /* acc1 += b[numTaps] * x[n-numTaps-1] */
+ acc1 += ((q15_t) x1 * c0);
+
+ /* acc2 += b[numTaps] * x[n-numTaps-2] */
+ acc2 += ((q15_t) x2 * c0);
+
+ /* acc3 += b[numTaps] * x[n-numTaps-3] */
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Read the b[numTaps-1] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-4] sample */
+ x0 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x1 * c0);
+ acc1 += ((q15_t) x2 * c0);
+ acc2 += ((q15_t) x3 * c0);
+ acc3 += ((q15_t) x0 * c0);
+
+ /* Read the b[numTaps-2] coefficient */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-5] sample */
+ x1 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x2 * c0);
+ acc1 += ((q15_t) x3 * c0);
+ acc2 += ((q15_t) x0 * c0);
+ acc3 += ((q15_t) x1 * c0);
+ /* Read the b[numTaps-3] coefficients */
+ c0 = *(pb++);
+
+ /* Read x[n-numTaps-6] sample */
+ x2 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x3 * c0);
+ acc1 += ((q15_t) x0 * c0);
+ acc2 += ((q15_t) x1 * c0);
+ acc3 += ((q15_t) x2 * c0);
+ i--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+ i = numTaps - (tapCnt * 4u);
+ while(i > 0u)
+ {
+ /* Read coefficients */
+ c0 = *(pb++);
+
+ /* Fetch 1 state variable */
+ x3 = *(px++);
+
+ /* Perform the multiply-accumulates */
+ acc0 += ((q15_t) x0 * c0);
+ acc1 += ((q15_t) x1 * c0);
+ acc2 += ((q15_t) x2 * c0);
+ acc3 += ((q15_t) x3 * c0);
+
+ /* Reuse the present sample states for next sample */
+ x0 = x1;
+ x1 = x2;
+ x2 = x3;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 4;
+
+ /* The results in the 4 accumulators are in 2.62 format. Convert to 1.31
+ ** Then store the 4 outputs in the destination buffer. */
+ acc0 = __SSAT((acc0 >> 7u), 8);
+ *pDst++ = acc0;
+ acc1 = __SSAT((acc1 >> 7u), 8);
+ *pDst++ = acc1;
+ acc2 = __SSAT((acc2 >> 7u), 8);
+ *pDst++ = acc2;
+ acc3 = __SSAT((acc3 >> 7u), 8);
+ *pDst++ = acc3;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set the accumulator to zero */
+ acc0 = 0;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize Coefficient pointer */
+ pb = (pCoeffs);
+
+ i = numTaps;
+
+ /* Perform the multiply-accumulates */
+ do
+ {
+ acc0 += (q15_t) * (px++) * (*(pb++));
+ i--;
+ } while(i > 0u);
+
+ /* The result is in 2.14 format. Convert to 1.7
+ ** Then store the output in the destination buffer. */
+ *pDst++ = __SSAT((acc0 >> 7u), 8);
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the samples loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ uint32_t numTaps = S->numTaps; /* Number of taps in the filter */
+ uint32_t i, blkCnt; /* Loop counters */
+ q7_t *pState = S->pState; /* State pointer */
+ q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q7_t *px, *pb; /* Temporary pointers to state and coeff */
+ q31_t acc = 0; /* Accumlator */
+ q7_t *pStateCurnt; /* Points to the current sample of the state */
+
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = S->pState + (numTaps - 1u);
+
+ /* Initialize blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ /* Perform filtering upto BlockSize - BlockSize%4 */
+ while(blkCnt > 0u)
+ {
+ /* Copy one sample at a time into state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Set accumulator to zero */
+ acc = 0;
+
+ /* Initialize state pointer of type q7 */
+ px = pState;
+
+ /* Initialize coeff pointer of type q7 */
+ pb = pCoeffs;
+
+
+ i = numTaps;
+
+ while(i > 0u)
+ {
+ /* acc = b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+ acc += (q15_t) * px++ * *pb++;
+ i--;
+ }
+
+ /* Store the 1.7 format filter output in destination buffer */
+ *pDst++ = (q7_t) __SSAT((acc >> 7), 8);
+
+ /* Advance the state pointer by 1 to process the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete.
+ ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.
+ ** This prepares the state buffer for the next function call. */
+
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = S->pState;
+
+
+ /* Copy numTaps number of values */
+ i = (numTaps - 1u);
+
+ /* Copy q7_t data */
+ while(i > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ i--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_f32.c
new file mode 100644
index 000000000..3a3db2c10
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_f32.c
@@ -0,0 +1,372 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_f32.c
+*
+* Description: Floating-point sparse FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters
+ *
+ * This group of functions implements sparse FIR filters.
+ * Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero.
+ * Sparse filters are used for simulating reflections in communications and audio applications.
+ *
+ * There are separate functions for Q7, Q15, Q31, and floating-point data types.
+ * The functions operate on blocks of input and output data and each call to the function processes
+ * <code>blockSize</code> samples through the filter. <code>pSrc</code> and
+ * <code>pDst</code> points to input and output arrays respectively containing <code>blockSize</code> values.
+ *
+ * \par Algorithm:
+ * The sparse filter instant structure contains an array of tap indices <code>pTapDelay</code> which specifies the locations of the non-zero coefficients.
+ * This is in addition to the coefficient array <code>b</code>.
+ * The implementation essentially skips the multiplications by zero and leads to an efficient realization.
+ * <pre>
+ * y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]
+ * </pre>
+ * \par
+ * \image html FIRSparse.gif "Sparse FIR filter. b[n] represents the filter coefficients"
+ * \par
+ * <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>;
+ * <code>pTapDelay</code> points to an array of nonzero indices and is also of size <code>numTaps</code>;
+ * <code>pState</code> points to a state array of size <code>maxDelay + blockSize</code>, where
+ * <code>maxDelay</code> is the largest offset value that is ever used in the <code>pTapDelay</code> array.
+ * Some of the processing functions also require temporary working buffers.
+ *
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 4 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, pTapDelay, maxDelay, stateIndex, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * The code below statically initializes each of the 4 different data type filter instance structures
+ * <pre>
+ *arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ *arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ *arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ *arm_fir_sparse_instance_q7 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};
+ * </pre>
+ * \par
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the sparse FIR filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize)
+{
+
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *px; /* Scratch buffer pointer */
+ float32_t *py = pState; /* Temporary pointers for state buffer */
+ float32_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ float32_t *pOut; /* Destination pointer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ float32_t coeff = *pCoeffs++; /* Read the first coefficient value */
+
+
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+ (int32_t *) pSrc, 1, blockSize);
+
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer */
+ px = pb;
+
+ /* Working pointer for destination buffer */
+ pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 Multiplications at a time. */
+ blkCnt = blockSize >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in destination buffer */
+ *pOut++ = *px++ * coeff;
+ *pOut++ = *px++ * coeff;
+ *pOut++ = *px++ * coeff;
+ *pOut++ = *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in destination buffer */
+ *pOut++ = *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer */
+ px = pb;
+
+ /* Working pointer for destination buffer */
+ pOut = pDst;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex -
+ (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in destination buffer */
+ *pOut++ = *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer */
+ px = pb;
+
+ /* Working pointer for destination buffer */
+ pOut = pDst;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pOut++ += *px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex =
+ ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_f32.c
new file mode 100644
index 000000000..fe48f35ad
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_f32.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_init_f32.c
+*
+* Description: Floating-point sparse FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> holds the filter coefficients and has length <code>numTaps</code>.
+ * <code>pState</code> holds the filter's state variables and must be of length
+ * <code>maxDelay + blockSize</code>, where <code>maxDelay</code>
+ * is the maximum number of delay line values.
+ * <code>blockSize</code> is the
+ * number of samples processed by the <code>arm_fir_sparse_f32()</code> function.
+ */
+
+void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0u;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q15.c
new file mode 100644
index 000000000..ef50dbffe
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q15.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_init_q15.c
+*
+* Description: Q15 sparse FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> holds the filter coefficients and has length <code>numTaps</code>.
+ * <code>pState</code> holds the filter's state variables and must be of length
+ * <code>maxDelay + blockSize</code>, where <code>maxDelay</code>
+ * is the maximum number of delay line values.
+ * <code>blockSize</code> is the
+ * number of words processed by <code>arm_fir_sparse_q15()</code> function.
+ */
+
+void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0u;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q31.c
new file mode 100644
index 000000000..3ba24559b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q31.c
@@ -0,0 +1,106 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_init_q31.c
+*
+* Description: Q31 sparse FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> holds the filter coefficients and has length <code>numTaps</code>.
+ * <code>pState</code> holds the filter's state variables and must be of length
+ * <code>maxDelay + blockSize</code>, where <code>maxDelay</code>
+ * is the maximum number of delay line values.
+ * <code>blockSize</code> is the number of words processed by <code>arm_fir_sparse_q31()</code> function.
+ */
+
+void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0u;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q7.c
new file mode 100644
index 000000000..205721378
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_init_q7.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_init_q7.c
+*
+* Description: Q7 sparse FIR filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> holds the filter coefficients and has length <code>numTaps</code>.
+ * <code>pState</code> holds the filter's state variables and must be of length
+ * <code>maxDelay + blockSize</code>, where <code>maxDelay</code>
+ * is the maximum number of delay line values.
+ * <code>blockSize</code> is the
+ * number of samples processed by the <code>arm_fir_sparse_q7()</code> function.
+ */
+
+void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Assign TapDelay pointer */
+ S->pTapDelay = pTapDelay;
+
+ /* Assign MaxDelay */
+ S->maxDelay = maxDelay;
+
+ /* reset the stateIndex to 0 */
+ S->stateIndex = 0u;
+
+ /* Clear state buffer and size is always maxDelay + blockSize */
+ memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q15.c
new file mode 100644
index 000000000..bd363bb56
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q15.c
@@ -0,0 +1,411 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_q15.c
+*
+* Description: Q15 sparse FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator.
+ * Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator.
+ * If the accumulator result overflows it will wrap around rather than saturate.
+ * After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format.
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.
+ */
+
+
+void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize)
+{
+
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pIn = pSrc; /* Working pointer for input */
+ q15_t *pOut = pDst; /* Working pointer for output */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *px; /* Temporary pointers for scratch buffer */
+ q15_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q15_t *py = pState; /* Temporary pointers for state buffer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Filter order */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q15_t coeff = *pCoeffs++; /* Read the first coefficient value */
+ q31_t *pScr2 = pScratchOut; /* Working pointer for pScratchOut */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in1, in2; /* Temporary variables */
+
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 multiplications at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+ /* Loop over the blockSize. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ in1 = *pScr2++;
+ in2 = *pScr2++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+ 16);
+
+#else
+ *__SIMD32(pOut)++ =
+ __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+ 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ in1 = *pScr2++;
+
+ in2 = *pScr2++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pOut)++ =
+ __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+ 16);
+
+#else
+
+ *__SIMD32(pOut)++ =
+ __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+ 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+
+ blkCnt--;
+
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ remaining samples are processed in the below loop */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q15(py, delaySize, &readIndex, 1,
+ pb, pb, blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ *pScratchOut++ += (q31_t) * px++ * coeff;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+ /* Loop over the blockSize. */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q31.c
new file mode 100644
index 000000000..88b7181e2
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q31.c
@@ -0,0 +1,375 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_q31.c
+*
+* Description: Q31 sparse FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The 1.31 x 1.31 multiplications are truncated to 2.30 format.
+ * This leads to loss of precision on the intermediate multiplications and provides only a single guard bit.
+ * If the accumulator result overflows, it wraps around rather than saturate.
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.
+ */
+
+void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize)
+{
+
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *px; /* Scratch buffer pointer */
+ q31_t *py = pState; /* Temporary pointers for state buffer */
+ q31_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q31_t *pOut; /* Destination pointer */
+ q63_t out; /* Temporary output variable */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Filter order */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q31_t coeff = *pCoeffs++; /* Read the first coefficient value */
+ q31_t in;
+
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+ (int32_t *) pSrc, 1, blockSize);
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 Multiplications at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in the destination buffer */
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in the destination buffer */
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* Working output pointer is updated */
+ pOut = pDst;
+
+ /* Output is converted into 1.31 format. */
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * process 4 output samples at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ in = *pOut << 1;
+ *pOut++ = in;
+ in = *pOut << 1;
+ *pOut++ = in;
+ in = *pOut << 1;
+ *pOut++ = in;
+ in = *pOut << 1;
+ *pOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * process the remaining output samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ in = *pOut << 1;
+ *pOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiplications and store in the destination buffer */
+ *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+ (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+ blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pOut = pDst;
+
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ out = *pOut;
+ out += ((q63_t) * px++ * coeff) >> 32;
+ *pOut++ = (q31_t) (out);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* Working output pointer is updated */
+ pOut = pDst;
+
+ /* Output is converted into 1.31 format. */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ in = *pOut << 1;
+ *pOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q7.c
new file mode 100644
index 000000000..33067b6c8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_fir_sparse_q7.c
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fir_sparse_q7.c
+*
+* Description: Q7 sparse FIR filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup FIR_Sparse
+ * @{
+ */
+
+
+/**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * The accumulator is then converted to 18.7 format by discarding the low 7 bits.
+ * Finally, the result is truncated to 1.7 format.
+ */
+
+void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize)
+{
+
+ q7_t *pState = S->pState; /* State pointer */
+ q7_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q7_t *px; /* Scratch buffer pointer */
+ q7_t *py = pState; /* Temporary pointers for state buffer */
+ q7_t *pb = pScratchIn; /* Temporary pointers for scratch buffer */
+ q7_t *pOut = pDst; /* Destination pointer */
+ int32_t *pTapDelay = S->pTapDelay; /* Pointer to the array containing offset of the non-zero tap values. */
+ uint32_t delaySize = S->maxDelay + blockSize; /* state length */
+ uint16_t numTaps = S->numTaps; /* Filter order */
+ int32_t readIndex; /* Read index of the state buffer */
+ uint32_t tapCnt, blkCnt; /* loop counters */
+ q7_t coeff = *pCoeffs++; /* Read the coefficient value */
+ q31_t *pScr2 = pScratchOut; /* Working pointer for scratch buffer of output values */
+ q31_t in;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t in1, in2, in3, in4;
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+ blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 multiplications at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize. Unroll by a factor of 4.
+ * Compute 4 MACS at a time. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ * compute the remaining samples */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex -
+ (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+ /* Loop over the blockSize. */
+ blkCnt = blockSize >> 2;
+
+ while(blkCnt > 0u)
+ {
+ in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+ in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+ in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+ in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+ *__SIMD32(pOut)++ = __PACKq7(in1, in2, in3, in4);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4,
+ remaining samples are processed in the below loop */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* BlockSize of Input samples are copied into the state buffer */
+ /* StateIndex points to the starting position to write in the state buffer */
+ arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+ blockSize);
+
+ /* Loop over the number of taps. */
+ tapCnt = numTaps;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform multiplication and store in the scratch buffer */
+ *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Loop over the number of taps. */
+ tapCnt = (uint32_t) numTaps - 1u;
+
+ while(tapCnt > 0u)
+ {
+ /* Working pointer for state buffer is updated */
+ py = pState;
+
+ /* blockSize samples are read from the state buffer */
+ arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+ (int32_t) blockSize, 1, blockSize);
+
+ /* Working pointer for the scratch buffer of state values */
+ px = pb;
+
+ /* Working pointer for scratch buffer of output values */
+ pScratchOut = pScr2;
+
+ /* Loop over the blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Perform Multiply-Accumulate */
+ in = *pScratchOut + ((q31_t) * px++ * coeff);
+ *pScratchOut++ = in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Load the coefficient value and
+ * increment the coefficient buffer for the next set of state values */
+ coeff = *pCoeffs++;
+
+ /* Read Index, from where the state buffer should be read, is calculated. */
+ readIndex =
+ ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+ /* Wraparound of readIndex */
+ if(readIndex < 0)
+ {
+ readIndex += (int32_t) delaySize;
+ }
+
+ /* Decrement the tap loop counter */
+ tapCnt--;
+ }
+
+ /* All the output values are in pScratchOut buffer.
+ Convert them into 1.15 format, saturate and store in the destination buffer. */
+ /* Loop over the blockSize. */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+ /* Decrement the blockSize loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of FIR_Sparse group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_f32.c
new file mode 100644
index 000000000..8c6c8ef7a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_f32.c
@@ -0,0 +1,447 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_f32.c
+*
+* Description: Floating-point IIR Lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters
+ *
+ * This set of functions implements lattice filters
+ * for Q15, Q31 and floating-point data types. Lattice filters are used in a
+ * variety of adaptive filter applications. The filter structure has feedforward and
+ * feedback components and the net impulse response is infinite length.
+ * The functions operate on blocks
+ * of input and output data and each call to the function processes
+ * <code>blockSize</code> samples through the filter. <code>pSrc</code> and
+ * <code>pDst</code> point to input and output arrays containing <code>blockSize</code> values.
+
+ * \par Algorithm:
+ * \image html IIRLattice.gif "Infinite Impulse Response Lattice filter"
+ * <pre>
+ * fN(n) = x(n)
+ * fm-1(n) = fm(n) - km * gm-1(n-1) for m = N, N-1, ...1
+ * gm(n) = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1
+ * y(n) = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)
+ * </pre>
+ * \par
+ * <code>pkCoeffs</code> points to array of reflection coefficients of size <code>numStages</code>.
+ * Reflection coefficients are stored in time-reversed order.
+ * \par
+ * <pre>
+ * {kN, kN-1, ....k1}
+ * </pre>
+ * <code>pvCoeffs</code> points to the array of ladder coefficients of size <code>(numStages+1)</code>.
+ * Ladder coefficients are stored in time-reversed order.
+ * \par
+ * <pre>
+ * {vN, vN-1, ...v0}
+ * </pre>
+ * <code>pState</code> points to a state array of size <code>numStages + blockSize</code>.
+ * The state variables shown in the figure above (the g values) are stored in the <code>pState</code> array.
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter.
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numStages, pkCoeffs, pvCoeffs, pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:
+ * <pre>
+ *arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};
+ *arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};
+ *arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};
+ * </pre>
+ * \par
+ * where <code>numStages</code> is the number of stages in the filter; <code>pState</code> points to the state buffer array;
+ * <code>pkCoeffs</code> points to array of the reflection coefficients; <code>pvCoeffs</code> points to the array of ladder coefficients.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the IIR lattice filter functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t fnext1, gcurr1, gnext; /* Temporary variables for lattice stages */
+ float32_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* temporary variables for counts */
+ float32_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ float32_t *pState; /* State pointer */
+ float32_t *pStateCurnt; /* State current pointer */
+ float32_t k1, k2;
+ float32_t v1, v2, v3, v4;
+ float32_t gcurr2;
+ float32_t fnext2;
+
+ /* initialise loop count */
+ blkCnt = blockSize;
+
+ /* initialise state pointer */
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fnext2 = *pSrc++;
+
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+
+ /* Set accumulator to zero */
+ acc = 0.0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = (numStages) >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Read gN-1(n-1) from state buffer */
+ gcurr1 = *px1;
+
+ /* read reflection coefficient kN */
+ k1 = *pk;
+
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext1 = fnext2 - (k1 * gcurr1);
+
+ /* read ladder coefficient vN */
+ v1 = *pv;
+
+ /* read next reflection coefficient kN-1 */
+ k2 = *(pk + 1u);
+
+ /* Read gN-2(n-1) from state buffer */
+ gcurr2 = *(px1 + 1u);
+
+ /* read next ladder coefficient vN-1 */
+ v2 = *(pv + 1u);
+
+ /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+ fnext2 = fnext1 - (k2 * gcurr2);
+
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = gcurr1 + (k1 * fnext1);
+
+ /* read reflection coefficient kN-2 */
+ k1 = *(pk + 2u);
+
+ /* write gN(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* Read gN-3(n-1) from state buffer */
+ gcurr1 = *(px1 + 2u);
+
+ /* y(n) += gN(n) * vN */
+ acc += (gnext * v1);
+
+ /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+ fnext1 = fnext2 - (k1 * gcurr1);
+
+ /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+ gnext = gcurr2 + (k2 * fnext2);
+
+ /* Read gN-4(n-1) from state buffer */
+ gcurr2 = *(px1 + 3u);
+
+ /* y(n) += gN-1(n) * vN-1 */
+ acc += (gnext * v2);
+
+ /* read reflection coefficient kN-3 */
+ k2 = *(pk + 3u);
+
+ /* write gN-1(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+ fnext2 = fnext1 - (k2 * gcurr2);
+
+ /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+ gnext = gcurr1 + (k1 * fnext1);
+
+ /* read ladder coefficient vN-2 */
+ v3 = *(pv + 2u);
+
+ /* y(n) += gN-2(n) * vN-2 */
+ acc += (gnext * v3);
+
+ /* write gN-2(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* update pointer */
+ pk += 4u;
+
+ /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+ gnext = (fnext2 * k2) + gcurr2;
+
+ /* read next ladder coefficient vN-3 */
+ v4 = *(pv + 3u);
+
+ /* y(n) += gN-4(n) * vN-4 */
+ acc += (gnext * v4);
+
+ /* write gN-3(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* update pointers */
+ px1 += 4u;
+ pv += 4u;
+
+ tapCnt--;
+
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = (numStages) % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ gcurr1 = *px1++;
+ /* Process sample for last taps */
+ fnext1 = fnext2 - ((*pk) * gcurr1);
+ gnext = (fnext1 * (*pk++)) + gcurr1;
+ /* Output samples for last taps */
+ acc += (gnext * (*pv++));
+ *px2++ = gnext;
+ fnext2 = fnext1;
+
+ tapCnt--;
+
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (fnext2 * (*pv));
+
+ *px2++ = fnext2;
+
+ /* write out into pDst */
+ *pDst++ = acc;
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 1u;
+
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numStages) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+}
+
+#else
+
+void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t fcurr, fnext = 0, gcurr, gnext; /* Temporary variables for lattice stages */
+ float32_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* temporary variables for counts */
+ float32_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ float32_t *pState; /* State pointer */
+ float32_t *pStateCurnt; /* State current pointer */
+
+
+ /* Run the below code for Cortex-M0 */
+
+ blkCnt = blockSize;
+
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0.0f;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+
+ /* Process sample for numStages */
+ tapCnt = numStages;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample for last taps */
+ fnext = fcurr - ((*pk) * gcurr);
+ gnext = (fnext * (*pk++)) + gcurr;
+
+ /* Output samples for last taps */
+ acc += (gnext * (*pv++));
+ *px2++ = gnext;
+ fcurr = fnext;
+
+ /* Decrementing loop counter */
+ tapCnt--;
+
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (fnext * (*pv));
+
+ *px2++ = fnext;
+
+ /* write out into pDst */
+ *pDst++ = acc;
+
+ /* Advance the state pointer by 1 to process the next group of samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages;
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+}
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_f32.c
new file mode 100644
index 000000000..6538364f9
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_f32.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_init_f32.c
+*
+* Description: Floating-point IIR lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign reflection coefficient pointer */
+ S->pkCoeffs = pkCoeffs;
+
+ /* Assign ladder coefficient pointer */
+ S->pvCoeffs = pvCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numStages */
+ memset(pState, 0, (numStages + blockSize) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+
+}
+
+ /**
+ * @} end of IIR_Lattice group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_q15.c
new file mode 100644
index 000000000..55a31289f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_q15.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_init_q15.c
+*
+* Description: Q15 IIR lattice filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign reflection coefficient pointer */
+ S->pkCoeffs = pkCoeffs;
+
+ /* Assign ladder coefficient pointer */
+ S->pvCoeffs = pvCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numStages */
+ memset(pState, 0, (numStages + blockSize) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+
+}
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_q31.c
new file mode 100644
index 000000000..84dcabf46
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_init_q31.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_init_q31.c
+*
+* Description: Initialization function for the Q31 IIR lattice filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numStages = numStages;
+
+ /* Assign reflection coefficient pointer */
+ S->pkCoeffs = pkCoeffs;
+
+ /* Assign ladder coefficient pointer */
+ S->pvCoeffs = pvCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numStages */
+ memset(pState, 0, (numStages + blockSize) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+
+}
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_q15.c
new file mode 100644
index 000000000..9b0ff9869
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_q15.c
@@ -0,0 +1,464 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_q15.c
+*
+* Description: Q15 IIR lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t fcurr, fnext, gcurr = 0, gnext; /* Temporary variables for lattice stages */
+ q15_t gnext1, gnext2; /* Temporary variables for lattice stages */
+ uint32_t stgCnt; /* Temporary variables for counts */
+ q63_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
+ q15_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ q15_t *pState; /* State pointer */
+ q15_t *pStateCurnt; /* State current pointer */
+ q15_t out; /* Temporary variable for output */
+ q31_t v; /* Temporary variable for ladder coefficient */
+#ifdef UNALIGNED_SUPPORT_DISABLE
+ q15_t v1, v2;
+#endif
+
+
+ blkCnt = blockSize;
+
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+
+ /* Process sample for first tap */
+ gcurr = *px1++;
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext = __SSAT(gnext, 16);
+ /* write gN(n) into state for next sample processing */
+ *px2++ = (q15_t) gnext;
+ /* y(n) += gN(n) * vN */
+ acc += (q31_t) ((gnext * (*pv++)));
+
+
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = (numStages - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Process sample for 2nd, 6th ...taps */
+ /* Read gN-2(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 2nd, 6th .. taps */
+ /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext1 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-1(n) into state */
+ *px2++ = (q15_t) gnext1;
+
+
+ /* Process sample for 3nd, 7th ...taps */
+ /* Read gN-3(n-1) from state */
+ gcurr = *px1++;
+ /* Process sample for 3rd, 7th .. taps */
+ /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+ fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+ fcurr = __SSAT(fcurr, 16);
+ /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+ gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+ gnext2 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-2(n) into state */
+ *px2++ = (q15_t) gnext2;
+
+ /* Read vN-1 and vN-2 at a time */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ v = *__SIMD32(pv)++;
+
+#else
+
+ v1 = *pv++;
+ v2 = *pv++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ v = __PKHBT(v1, v2, 16);
+
+#else
+
+ v = __PKHBT(v2, v1, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+ /* Pack gN-1(n) and gN-2(n) */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+ gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* y(n) += gN-1(n) * vN-1 */
+ /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+ /* y(n) += gN-2(n) * vN-2 */
+ /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+ acc = __SMLALD(gnext, v, acc);
+
+
+ /* Process sample for 4th, 8th ...taps */
+ /* Read gN-4(n-1) from state */
+ gcurr = *px1++;
+ /* Process sample for 4th, 8th .. taps */
+ /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext1 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-3(n) for the next sample process */
+ *px2++ = (q15_t) gnext1;
+
+
+ /* Process sample for 5th, 9th ...taps */
+ /* Read gN-5(n-1) from state */
+ gcurr = *px1++;
+ /* Process sample for 5th, 9th .. taps */
+ /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */
+ fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+ fcurr = __SSAT(fcurr, 16);
+ /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+ gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+ gnext2 = (q15_t) __SSAT(gnext, 16);
+ /* write gN-4(n) for the next sample process */
+ *px2++ = (q15_t) gnext2;
+
+ /* Read vN-3 and vN-4 at a time */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ v = *__SIMD32(pv)++;
+
+#else
+
+ v1 = *pv++;
+ v2 = *pv++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ v = __PKHBT(v1, v2, 16);
+
+#else
+
+ v = __PKHBT(v2, v1, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+
+ /* Pack gN-3(n) and gN-4(n) */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+ gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* y(n) += gN-4(n) * vN-4 */
+ /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+ /* y(n) += gN-3(n) * vN-3 */
+ /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+ acc = __SMLALD(gnext, v, acc);
+
+ tapCnt--;
+
+ }
+
+ fnext = fcurr;
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = (numStages - 1u) % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample for last taps */
+ fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+ gnext = __SSAT(gnext, 16);
+ /* Output samples for last taps */
+ acc += (q31_t) (((q31_t) gnext * (*pv++)));
+ *px2++ = (q15_t) gnext;
+ fcurr = fnext;
+
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q31_t) (((q31_t) fnext * (*pv++)));
+
+ out = (q15_t) __SSAT(acc >> 15, 16);
+ *px2++ = (q15_t) fnext;
+
+ /* write out into pDst */
+ *pDst++ = out;
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ stgCnt = (numStages >> 2u);
+
+ /* copy data */
+ while(stgCnt > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ stgCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ stgCnt = (numStages) % 0x4u;
+
+ /* copy data */
+ while(stgCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ stgCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */
+ uint32_t stgCnt; /* Temporary variables for counts */
+ q63_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
+ q15_t *px1, *px2, *pk, *pv; /* temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ q15_t *pState; /* State pointer */
+ q15_t *pStateCurnt; /* State current pointer */
+ q15_t out; /* Temporary variable for output */
+
+
+ blkCnt = blockSize;
+
+ pState = &S->pState[0];
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ tapCnt = numStages;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample */
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext = fcurr - ((gcurr * (*pk)) >> 15);
+ fnext = __SSAT(fnext, 16);
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = ((fnext * (*pk++)) >> 15) + gcurr;
+ gnext = __SSAT(gnext, 16);
+ /* Output samples */
+ /* y(n) += gN(n) * vN */
+ acc += (q31_t) ((gnext * (*pv++)));
+ /* write gN(n) into state for next sample processing */
+ *px2++ = (q15_t) gnext;
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q31_t) ((fnext * (*pv++)));
+
+ out = (q15_t) __SSAT(acc >> 15, 16);
+ *px2++ = (q15_t) fnext;
+
+ /* write out into pDst */
+ *pDst++ = out;
+
+ /* Advance the state pointer by 1 to process the next group of samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ stgCnt = numStages;
+
+ /* copy data */
+ while(stgCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ stgCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_q31.c
new file mode 100644
index 000000000..978c4a70d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_iir_lattice_q31.c
@@ -0,0 +1,350 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_iir_lattice_q31.c
+*
+* Description: Q31 IIR lattice filter processing function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup IIR_Lattice
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format.
+ */
+
+void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t fcurr, fnext = 0, gcurr = 0, gnext; /* Temporary variables for lattice stages */
+ q63_t acc; /* Accumlator */
+ uint32_t blkCnt, tapCnt; /* Temporary variables for counts */
+ q31_t *px1, *px2, *pk, *pv; /* Temporary pointers for state and coef */
+ uint32_t numStages = S->numStages; /* number of stages */
+ q31_t *pState; /* State pointer */
+ q31_t *pStateCurnt; /* State current pointer */
+
+ blkCnt = blockSize;
+
+ pState = &S->pState[0];
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+
+ /* Process sample for first tap */
+ gcurr = *px1++;
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+ /* write gN-1(n-1) into state for next sample processing */
+ *px2++ = gnext;
+ /* y(n) += gN(n) * vN */
+ acc += ((q63_t) gnext * *pv++);
+
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = (numStages - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Process sample for 2nd, 6th .. taps */
+ /* Read gN-2(n-1) from state buffer */
+ gcurr = *px1++;
+ /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+ /* y(n) += gN-1(n) * vN-1 */
+ /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-1(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ /* Process sample for 3nd, 7th ...taps */
+ /* Read gN-3(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 3rd, 7th .. taps */
+ /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+ fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+ /* y(n) += gN-2(n) * vN-2 */
+ /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-2(n) into state for next sample processing */
+ *px2++ = gnext;
+
+
+ /* Process sample for 4th, 8th ...taps */
+ /* Read gN-4(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 4th, 8th .. taps */
+ /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+ /* y(n) += gN-3(n) * vN-3 */
+ /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-3(n) into state for next sample processing */
+ *px2++ = gnext;
+
+
+ /* Process sample for 5th, 9th ...taps */
+ /* Read gN-5(n-1) from state buffer */
+ gcurr = *px1++;
+ /* Process sample for 5th, 9th .. taps */
+ /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
+ fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+ /* y(n) += gN-4(n) * vN-4 */
+ /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-4(n) into state for next sample processing */
+ *px2++ = gnext;
+
+ tapCnt--;
+
+ }
+
+ fnext = fcurr;
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = (numStages - 1u) % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample for last taps */
+ fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+ gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+ /* Output samples for last taps */
+ acc += ((q63_t) gnext * *pv++);
+ *px2++ = gnext;
+ fcurr = fnext;
+
+ tapCnt--;
+
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q63_t) fnext *(
+ *pv++);
+
+ *px2++ = fnext;
+
+ /* write out into pDst */
+ *pDst++ = (q31_t) (acc >> 31u);
+
+ /* Advance the state pointer by 4 to process the next group of 4 samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numStages) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ };
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ /* Sample processing */
+ while(blkCnt > 0u)
+ {
+ /* Read Sample from input buffer */
+ /* fN(n) = x(n) */
+ fcurr = *pSrc++;
+
+ /* Initialize state read pointer */
+ px1 = pState;
+ /* Initialize state write pointer */
+ px2 = pState;
+ /* Set accumulator to zero */
+ acc = 0;
+ /* Initialize Ladder coeff pointer */
+ pv = &S->pvCoeffs[0];
+ /* Initialize Reflection coeff pointer */
+ pk = &S->pkCoeffs[0];
+
+ tapCnt = numStages;
+
+ while(tapCnt > 0u)
+ {
+ gcurr = *px1++;
+ /* Process sample */
+ /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+ fnext =
+ clip_q63_to_q31(((q63_t) fcurr -
+ ((q31_t) (((q63_t) gcurr * (*pk)) >> 31))));
+ /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+ gnext =
+ clip_q63_to_q31(((q63_t) gcurr +
+ ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));
+ /* Output samples */
+ /* y(n) += gN(n) * vN */
+ acc += ((q63_t) gnext * *pv++);
+ /* write gN-1(n-1) into state for next sample processing */
+ *px2++ = gnext;
+ /* Update f values for next coefficient processing */
+ fcurr = fnext;
+
+ tapCnt--;
+ }
+
+ /* y(n) += g0(n) * v0 */
+ acc += (q63_t) fnext *(
+ *pv++);
+
+ *px2++ = fnext;
+
+ /* write out into pDst */
+ *pDst++ = (q31_t) (acc >> 31u);
+
+ /* Advance the state pointer by 1 to process the next group of samples */
+ pState = pState + 1u;
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy last S->numStages samples to start of the buffer
+ for the preperation of next frame process */
+
+ /* Points to the start of the state buffer */
+ pStateCurnt = &S->pState[0];
+ pState = &S->pState[blockSize];
+
+ tapCnt = numStages;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+
+
+/**
+ * @} end of IIR_Lattice group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_f32.c
new file mode 100644
index 000000000..cca785fae
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_f32.c
@@ -0,0 +1,442 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_f32.c
+*
+* Description: Processing function for the floating-point LMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup LMS Least Mean Square (LMS) Filters
+ *
+ * LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions.
+ * LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal.
+ * Adaptive filters are often used in communication systems, equalizers, and noise removal.
+ * The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types.
+ * The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.
+ *
+ * An LMS filter consists of two components as shown below.
+ * The first component is a standard transversal or FIR filter.
+ * The second component is a coefficient update mechanism.
+ * The LMS filter has two input signals.
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.
+ * This "error signal" tends towards zero as the filter adapts.
+ * The LMS processing functions accept the input and reference input signals and generate the filter output and error signal.
+ * \image html LMS.gif "Internal structure of the Least Mean Square filter"
+ *
+ * The functions operate on blocks of data and each call to the function processes
+ * <code>blockSize</code> samples through the filter.
+ * <code>pSrc</code> points to input signal, <code>pRef</code> points to reference signal,
+ * <code>pOut</code> points to output signal and <code>pErr</code> points to error signal.
+ * All arrays contain <code>blockSize</code> values.
+ *
+ * The functions operate on a block-by-block basis.
+ * Internally, the filter coefficients <code>b[n]</code> are updated on a sample-by-sample basis.
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.
+ *
+ * \par Algorithm:
+ * The output signal <code>y[n]</code> is computed by a standard FIR filter:
+ * <pre>
+ * y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+ * </pre>
+ *
+ * \par
+ * The error signal equals the difference between the reference signal <code>d[n]</code> and the filter output:
+ * <pre>
+ * e[n] = d[n] - y[n].
+ * </pre>
+ *
+ * \par
+ * After each sample of the error signal is computed, the filter coefficients <code>b[k]</code> are updated on a sample-by-sample basis:
+ * <pre>
+ * b[k] = b[k] + e[n] * mu * x[n-k], for k=0, 1, ..., numTaps-1
+ * </pre>
+ * where <code>mu</code> is the step size and controls the rate of coefficient convergence.
+ *\par
+ * In the APIs, <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.
+ * Coefficients are stored in time reversed order.
+ * \par
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to a state array of size <code>numTaps + blockSize - 1</code>.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ * <pre>
+ * {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+ * </pre>
+ * \par
+ * Note that the length of the state buffer exceeds the length of the coefficient array by <code>blockSize-1</code> samples.
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,
+ * to be avoided and yields a significant speed improvement.
+ * The state variables are updated after each block of data is processed.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter and
+ * coefficient and state arrays cannot be shared among instances.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, mu, postShift (not for f32), pState. Also set all of the values in pState to zero.
+ *
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Set the values in the state buffer to zeros before static initialization.
+ * The code below statically initializes each of the 3 different data type filter instance structures
+ * <pre>
+ * arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};
+ * arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};
+ * arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};
+ * </pre>
+ * where <code>numTaps</code> is the number of filter coefficients in the filter; <code>pState</code> is the address of the state buffer;
+ * <code>pCoeffs</code> is the address of the coefficient buffer; <code>mu</code> is the step size parameter; and <code>postShift</code> is the shift applied to coefficients.
+ *
+ * \par Fixed-Point Behavior:
+ * Care must be taken when using the Q15 and Q31 versions of the LMS filter.
+ * The following issues must be considered:
+ * - Scaling of coefficients
+ * - Overflow and saturation
+ *
+ * \par Scaling of Coefficients:
+ * Filter coefficients are represented as fractional values and
+ * coefficients are restricted to lie in the range <code>[-1 +1)</code>.
+ * The fixed-point functions have an additional scaling parameter <code>postShift</code>.
+ * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.
+ * This essentially scales the filter coefficients by <code>2^postShift</code> and
+ * allows the filter coefficients to exceed the range <code>[+1 -1)</code>.
+ * The value of <code>postShift</code> is set by the user based on the expected gain through the system being modeled.
+ *
+ * \par Overflow and Saturation:
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are
+ * described separately as part of the function specific documentation below.
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+/**
+ * @details
+ * This function operates on floating-point data types.
+ *
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ float32_t sum, e, d; /* accumulator, error, reference data sample */
+ float32_t w = 0.0f; /* weight factor */
+
+ e = 0.0f;
+ d = 0.0f;
+
+ /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result in the accumulator, store in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = (float32_t) (*pRef++);
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Calculation of Weighting factor for the updating filter coefficients */
+ w = e * mu;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop unrolling for (numTaps - 1u) samples copy */
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result is stored in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = (float32_t) (*pRef++);
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Weighting factor for the LMS version */
+ w = e * mu;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb = *pb + (w * (*px++));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ * start of the state buffer. This prepares the state buffer for the
+ * next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy (numTaps - 1u) samples */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_f32.c
new file mode 100644
index 000000000..05f3416c8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_f32.c
@@ -0,0 +1,95 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_init_f32.c
+*
+* Description: Floating-point LMS filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+/**
+ * \par Description:
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * <code>pState</code> points to an array of length <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_lms_f32()</code>.
+ */
+
+void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps */
+ memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_q15.c
new file mode 100644
index 000000000..a49d821b8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_q15.c
@@ -0,0 +1,105 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_init_q15.c
+*
+* Description: Q15 LMS filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+/**
+* @brief Initialization function for the Q15 LMS filter.
+* @param[in] *S points to an instance of the Q15 LMS filter structure.
+* @param[in] numTaps number of filter coefficients.
+* @param[in] *pCoeffs points to the coefficient buffer.
+* @param[in] *pState points to the state buffer.
+* @param[in] mu step size that controls filter coefficient updates.
+* @param[in] blockSize number of samples to process.
+* @param[in] postShift bit shift applied to coefficients.
+* @return none.
+*
+* \par Description:
+* <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+* <pre>
+* {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+* </pre>
+* The initial filter coefficients serve as a starting point for the adaptive filter.
+* <code>pState</code> points to the array of state variables and size of array is
+* <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of
+* input samples processed by each call to <code>arm_lms_q15()</code>.
+*/
+
+void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Assign postShift value to be applied */
+ S->postShift = postShift;
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_q31.c
new file mode 100644
index 000000000..2519b0d53
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_init_q31.c
@@ -0,0 +1,105 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_init_q31.c
+*
+* Description: Q31 LMS filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ *
+ * \par Description:
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * <code>pState</code> points to an array of length <code>numTaps+blockSize-1</code> samples,
+ * where <code>blockSize</code> is the number of input samples processed by each call to
+ * <code>arm_lms_q31()</code>.
+ */
+
+void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, ((uint32_t) numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Assign postShift value to be applied */
+ S->postShift = postShift;
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_f32.c
new file mode 100644
index 000000000..5357ee87e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_f32.c
@@ -0,0 +1,466 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_f32.c
+*
+* Description: Processing function for the floating-point Normalised LMS.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @defgroup LMS_NORM Normalized LMS Filters
+ *
+ * This set of functions implements a commonly used adaptive filter.
+ * It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization
+ * factor which increases the adaptation rate of the filter.
+ * The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.
+ *
+ * A normalized least mean square (NLMS) filter consists of two components as shown below.
+ * The first component is a standard transversal or FIR filter.
+ * The second component is a coefficient update mechanism.
+ * The NLMS filter has two input signals.
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.
+ * This "error signal" tends towards zero as the filter adapts.
+ * The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal.
+ * \image html LMS.gif "Internal structure of the NLMS adaptive filter"
+ *
+ * The functions operate on blocks of data and each call to the function processes
+ * <code>blockSize</code> samples through the filter.
+ * <code>pSrc</code> points to input signal, <code>pRef</code> points to reference signal,
+ * <code>pOut</code> points to output signal and <code>pErr</code> points to error signal.
+ * All arrays contain <code>blockSize</code> values.
+ *
+ * The functions operate on a block-by-block basis.
+ * Internally, the filter coefficients <code>b[n]</code> are updated on a sample-by-sample basis.
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.
+ *
+ * \par Algorithm:
+ * The output signal <code>y[n]</code> is computed by a standard FIR filter:
+ * <pre>
+ * y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]
+ * </pre>
+ *
+ * \par
+ * The error signal equals the difference between the reference signal <code>d[n]</code> and the filter output:
+ * <pre>
+ * e[n] = d[n] - y[n].
+ * </pre>
+ *
+ * \par
+ * After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated:
+ * <pre>
+ * E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.
+ * </pre>
+ * The filter coefficients <code>b[k]</code> are then updated on a sample-by-sample basis:
+ * <pre>
+ * b[k] = b[k] + e[n] * (mu/E) * x[n-k], for k=0, 1, ..., numTaps-1
+ * </pre>
+ * where <code>mu</code> is the step size and controls the rate of coefficient convergence.
+ *\par
+ * In the APIs, <code>pCoeffs</code> points to a coefficient array of size <code>numTaps</code>.
+ * Coefficients are stored in time reversed order.
+ * \par
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * \par
+ * <code>pState</code> points to a state array of size <code>numTaps + blockSize - 1</code>.
+ * Samples in the state buffer are stored in the order:
+ * \par
+ * <pre>
+ * {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}
+ * </pre>
+ * \par
+ * Note that the length of the state buffer exceeds the length of the coefficient array by <code>blockSize-1</code> samples.
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,
+ * to be avoided and yields a significant speed improvement.
+ * The state variables are updated after each block of data is processed.
+ * \par Instance Structure
+ * The coefficients and state variables for a filter are stored together in an instance data structure.
+ * A separate instance structure must be defined for each filter and
+ * coefficient and state arrays cannot be shared among instances.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Zeros out the values in the state buffer.
+ * To do this manually without calling the init function, assign the follow subfields of the instance structure:
+ * numTaps, pCoeffs, mu, energy, x0, pState. Also set all of the values in pState to zero.
+ * For Q7, Q15, and Q31 the following fields must also be initialized;
+ * recipTable, postShift
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ * \par Fixed-Point Behavior:
+ * Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter.
+ * The following issues must be considered:
+ * - Scaling of coefficients
+ * - Overflow and saturation
+ *
+ * \par Scaling of Coefficients:
+ * Filter coefficients are represented as fractional values and
+ * coefficients are restricted to lie in the range <code>[-1 +1)</code>.
+ * The fixed-point functions have an additional scaling parameter <code>postShift</code>.
+ * At the output of the filter's accumulator is a shift register which shifts the result by <code>postShift</code> bits.
+ * This essentially scales the filter coefficients by <code>2^postShift</code> and
+ * allows the filter coefficients to exceed the range <code>[+1 -1)</code>.
+ * The value of <code>postShift</code> is set by the user based on the expected gain through the system being modeled.
+ *
+ * \par Overflow and Saturation:
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are
+ * described separately as part of the function specific documentation below.
+ */
+
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize)
+{
+ float32_t *pState = S->pState; /* State pointer */
+ float32_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ float32_t *pStateCurnt; /* Points to the current sample of the state */
+ float32_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ float32_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ float32_t energy; /* Energy of the input */
+ float32_t sum, e, d; /* accumulator, error, reference data sample */
+ float32_t w, x0, in; /* weight factor, temporary variable to hold input sample and state */
+
+ /* Initializations of error, difference, Coefficient update */
+ e = 0.0f;
+ d = 0.0f;
+ w = 0.0f;
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= x0 * x0;
+ energy += in * in;
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result in the accumulator, store in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = (float32_t) (*pRef++);
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Calculation of Weighting factor for updating filter coefficients */
+ /* epsilon value 0.000000119209289f */
+ w = (e * mu) / (energy + 0.000000119209289f);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+ *pb += w * (*px++);
+ pb++;
+
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb += w * (*px++);
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ S->energy = energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop unrolling for (numTaps - 1u)/4 samples copy */
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= x0 * x0;
+ energy += in * in;
+
+ /* Set the accumulator to zero */
+ sum = 0.0f;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ sum += (*px++) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* The result in the accumulator is stored in the destination buffer. */
+ *pOut++ = sum;
+
+ /* Compute and store error */
+ d = (float32_t) (*pRef++);
+ e = d - sum;
+ *pErr++ = e;
+
+ /* Calculation of Weighting factor for updating filter coefficients */
+ /* epsilon value 0.000000119209289f */
+ w = (e * mu) / (energy + 0.000000119209289f);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCcoeffs pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb += w * (*px++);
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ S->energy = energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy (numTaps - 1u) samples */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_f32.c
new file mode 100644
index 000000000..070377823
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_f32.c
@@ -0,0 +1,105 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_init_f32.c
+*
+* Description: Floating-point NLMS filter initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * \par Description:
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * <code>pState</code> points to an array of length <code>numTaps+blockSize-1</code> samples,
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_lms_norm_f32()</code>.
+ */
+
+void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Initialise Energy to zero */
+ S->energy = 0.0f;
+
+ /* Initialise x0 to zero */
+ S->x0 = 0.0f;
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_q15.c
new file mode 100644
index 000000000..8ed6db428
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_q15.c
@@ -0,0 +1,112 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_init_q15.c
+*
+* Description: Q15 NLMS initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * <code>pState</code> points to the array of state variables and size of array is
+ * <code>numTaps+blockSize-1</code> samples, where <code>blockSize</code> is the number of input samples processed
+ * by each call to <code>arm_lms_norm_q15()</code>.
+ */
+
+void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+ /* Assign post Shift value applied to coefficients */
+ S->postShift = postShift;
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Initialize reciprocal pointer table */
+ S->recipTable = (q15_t *) armRecipTableQ15;
+
+ /* Initialise Energy to zero */
+ S->energy = 0;
+
+ /* Initialise x0 to zero */
+ S->x0 = 0;
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_q31.c
new file mode 100644
index 000000000..c422f77f2
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_init_q31.c
@@ -0,0 +1,111 @@
+/*-----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_init_q31.c
+*
+* Description: Q31 NLMS initialization function.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ *
+ * <b>Description:</b>
+ * \par
+ * <code>pCoeffs</code> points to the array of filter coefficients stored in time reversed order:
+ * <pre>
+ * {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}
+ * </pre>
+ * The initial filter coefficients serve as a starting point for the adaptive filter.
+ * <code>pState</code> points to an array of length <code>numTaps+blockSize-1</code> samples,
+ * where <code>blockSize</code> is the number of input samples processed by each call to <code>arm_lms_norm_q31()</code>.
+ */
+
+void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift)
+{
+ /* Assign filter taps */
+ S->numTaps = numTaps;
+
+ /* Assign coefficient pointer */
+ S->pCoeffs = pCoeffs;
+
+ /* Clear state buffer and size is always blockSize + numTaps - 1 */
+ memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+ /* Assign post Shift value applied to coefficients */
+ S->postShift = postShift;
+
+ /* Assign state pointer */
+ S->pState = pState;
+
+ /* Assign Step size value */
+ S->mu = mu;
+
+ /* Initialize reciprocal pointer table */
+ S->recipTable = (q31_t *) armRecipTableQ31;
+
+ /* Initialise Energy to zero */
+ S->energy = 0;
+
+ /* Initialise x0 to zero */
+ S->x0 = 0;
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_q15.c
new file mode 100644
index 000000000..795b03bee
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_q15.c
@@ -0,0 +1,440 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_q15.c
+*
+* Description: Q15 NLMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+/**
+* @brief Processing function for Q15 normalized LMS filter.
+* @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[in] *pRef points to the block of reference data.
+* @param[out] *pOut points to the block of output data.
+* @param[out] *pErr points to the block of error data.
+* @param[in] blockSize number of samples to process.
+* @return none.
+*
+* <b>Scaling and Overflow Behavior:</b>
+* \par
+* The function is implemented using a 64-bit internal accumulator.
+* Both coefficients and state variables are represented in 1.15 format and
+* multiplications yield a 2.30 result. The 2.30 intermediate results are
+* accumulated in a 64-bit accumulator in 34.30 format.
+* There is no risk of internal overflow with this approach and the full
+* precision of intermediate multiplications is preserved. After all additions
+* have been performed, the accumulator is truncated to 34.15 format by
+* discarding low 15 bits. Lastly, the accumulator is saturated to yield a
+* result in 1.15 format.
+*
+* \par
+* In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
+*
+ */
+
+void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ q15_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q31_t energy; /* Energy of the input */
+ q63_t acc; /* Accumulator */
+ q15_t e = 0, d = 0; /* error, reference data sample */
+ q15_t w = 0, in; /* weight factor and state */
+ q15_t x0; /* temporary variable to hold input sample */
+ //uint32_t shift = (uint32_t) S->postShift + 1u; /* Shift to be applied to the output */
+ q15_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */
+ q15_t postShift; /* Post shift to be applied to weight after reciprocal calculation */
+ q31_t coef; /* Teporary variable for coefficient */
+ q31_t acc_l, acc_h;
+ int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
+ int32_t uShift = (32 - lShift);
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= (((q31_t) x0 * (x0)) >> 15);
+ energy += (((q31_t) in * (in)) >> 15);
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+ /* Perform the multiply-accumulate */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+ acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+#else
+
+ acc += (((q31_t) * px++ * (*pb++)));
+ acc += (((q31_t) * px++ * (*pb++)));
+ acc += (((q31_t) * px++ * (*pb++)));
+ acc += (((q31_t) * px++ * (*pb++)));
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (((q31_t) * px++ * (*pb++)));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = __SSAT(acc, 16u);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q15_t) acc;
+ *pErr++ = e;
+
+ /* Calculation of 1/energy */
+ postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+ &oneByEnergy, S->recipTable);
+
+ /* Calculation of e * mu value */
+ errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+ /* Calculation of (e * mu) * (1/energy) value */
+ acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+ /* Weighting factor for the normalized version */
+ w = (q15_t) __SSAT((q31_t) acc, 16);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q15_t) energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+#else
+
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+#endif
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy -= (((q31_t) x0 * (x0)) >> 15);
+ energy += (((q31_t) in * (in)) >> 15);
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (((q31_t) * px++ * (*pb++)));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = __SSAT(acc, 16u);
+
+ /* Converting the result to 1.15 format */
+ //acc = __SSAT((acc >> (16u - shift)), 16u);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q15_t) acc;
+ *pErr++ = e;
+
+ /* Calculation of 1/energy */
+ postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+ &oneByEnergy, S->recipTable);
+
+ /* Calculation of e * mu value */
+ errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+ /* Calculation of (e * mu) * (1/energy) value */
+ acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+ /* Weighting factor for the normalized version */
+ w = (q15_t) __SSAT((q31_t) acc, 16);
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = *pb + (((q31_t) w * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q15_t) energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* copy (numTaps - 1u) data */
+ tapCnt = (numTaps - 1u);
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_q31.c
new file mode 100644
index 000000000..223816a04
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_norm_q31.c
@@ -0,0 +1,431 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_norm_q31.c
+*
+* Description: Processing function for the Q31 NLMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS_NORM
+ * @{
+ */
+
+/**
+* @brief Processing function for Q31 normalized LMS filter.
+* @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+* @param[in] *pSrc points to the block of input data.
+* @param[in] *pRef points to the block of reference data.
+* @param[out] *pOut points to the block of output data.
+* @param[out] *pErr points to the block of error data.
+* @param[in] blockSize number of samples to process.
+* @return none.
+*
+* <b>Scaling and Overflow Behavior:</b>
+* \par
+* The function is implemented using an internal 64-bit accumulator.
+* The accumulator has a 2.62 format and maintains full precision of the intermediate
+* multiplication results but provides only a single guard bit.
+* Thus, if the accumulator result overflows it wraps around rather than clip.
+* In order to avoid overflows completely the input signal must be scaled down by
+* log2(numTaps) bits. The reference signal should not be scaled down.
+* After all multiply-accumulates are performed, the 2.62 accumulator is shifted
+* and saturated to 1.31 format to yield the final result.
+* The output signal and error signal are in 1.31 format.
+*
+* \par
+* In this filter, filter coefficients are updated for each sample and the
+* updation of filter cofficients are saturted.
+*
+*/
+
+void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t *px, *pb; /* Temporary pointers for state and coefficient buffers */
+ q31_t mu = S->mu; /* Adaptive factor */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t energy; /* Energy of the input */
+ q63_t acc; /* Accumulator */
+ q31_t e = 0, d = 0; /* error, reference data sample */
+ q31_t w = 0, in; /* weight factor and state */
+ q31_t x0; /* temporary variable to hold input sample */
+// uint32_t shift = 32u - ((uint32_t) S->postShift + 1u); /* Shift to be applied to the output */
+ q31_t errorXmu, oneByEnergy; /* Temporary variables to store error and mu product and reciprocal of energy */
+ q31_t postShift; /* Post shift to be applied to weight after reciprocal calculation */
+ q31_t coef; /* Temporary variable for coef */
+ q31_t acc_l, acc_h; /* temporary input */
+ uint32_t uShift = ((uint32_t) S->postShift + 1u);
+ uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
+
+ energy = S->energy;
+ x0 = S->x0;
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy = (q31_t) ((((q63_t) energy << 32) -
+ (((q63_t) x0 * x0) << 1)) >> 32);
+ energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+ acc += ((q63_t) (*px++)) * (*pb++);
+ acc += ((q63_t) (*px++)) * (*pb++);
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q31_t) acc;
+ *pErr++ = e;
+
+ /* Calculates the reciprocal of energy */
+ postShift = arm_recip_q31(energy + DELTA_Q31,
+ &oneByEnergy, &S->recipTable[0]);
+
+ /* Calculation of product of (e * mu) */
+ errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+ /* Weighting factor for the normalized version */
+ w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+
+ /* coef is in 2.30 format */
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ /* get coef in 1.31 format by left shifting */
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ /* update coefficient buffer to next coefficient */
+ pb++;
+
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q31_t) energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop unrolling for (numTaps - 1u) samples copy */
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Read the sample from input buffer */
+ in = *pSrc++;
+
+ /* Update the energy calculation */
+ energy =
+ (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32);
+ energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Converting the result to 1.31 format */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+
+ //acc = (q31_t) (acc >> shift);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* Compute and store error */
+ d = *pRef++;
+ e = d - (q31_t) acc;
+ *pErr++ = e;
+
+ /* Calculates the reciprocal of energy */
+ postShift =
+ arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]);
+
+ /* Calculation of product of (e * mu) */
+ errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+ /* Weighting factor for the normalized version */
+ w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize coeff pointer */
+ pb = (pCoeffs);
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ /* coef is in 2.30 format */
+ coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+ /* get coef in 1.31 format by left shifting */
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ /* update coefficient buffer to next coefficient */
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Read the sample from state buffer */
+ x0 = *pState;
+
+ /* Advance state pointer by 1 for the next sample */
+ pState = pState + 1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Save energy and x0 values for the next frame */
+ S->energy = (q31_t) energy;
+ S->x0 = x0;
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ start of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop for (numTaps - 1u) samples copy */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS_NORM group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_q15.c
new file mode 100644
index 000000000..a52a04bf6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_q15.c
@@ -0,0 +1,379 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_q15.c
+*
+* Description: Processing function for the Q15 LMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * \par Scaling and Overflow Behavior:
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ *
+ * \par
+ * In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
+ *
+ */
+
+void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize)
+{
+ q15_t *pState = S->pState; /* State pointer */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ q15_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q15_t *pStateCurnt; /* Points to the current sample of the state */
+ q15_t mu = S->mu; /* Adaptive factor */
+ q15_t *px; /* Temporary pointer for state */
+ q15_t *pb; /* Temporary pointer for coefficient buffer */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t acc; /* Accumulator */
+ q15_t e = 0; /* error of data sample */
+ q15_t alpha; /* Intermediate constant for taps update */
+ q31_t acc_l, acc_h;
+ int32_t lShift = (15 - (int32_t) S->postShift); /* Post shift */
+ int32_t uShift = (32 - lShift);
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t coef; /* Teporary variable for coefficient */
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initializing blkCnt with blockSize */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2u;
+
+ while(tapCnt > 0u)
+ {
+ /* acc += b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+ /* Perform the multiply-accumulate */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+ acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+#else
+
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = __SSAT(acc, 16);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q15_t) acc;
+
+ *pErr++ = (q15_t) e;
+
+ /* Compute alpha i.e. intermediate constant for taps update */
+ alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+ /* Initialize state pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2u;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+ *pb++ = (q15_t) __SSAT((coef), 16);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Calculation of count for copying integer writes */
+ tapCnt = (numTaps - 1u) >> 2;
+
+ while(tapCnt > 0u)
+ {
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+ *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+#else
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+#endif
+
+ tapCnt--;
+
+ }
+
+ /* Calculation of count for remaining q15_t data */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += (q63_t) ((q31_t) (*px++) * (*pb++));
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ /* Apply shift for lower part of acc and upper part of acc */
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Converting the result to 1.15 format and saturate the output */
+ acc = __SSAT(acc, 16);
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q15_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q15_t) acc;
+
+ *pErr++ = (q15_t) e;
+
+ /* Compute alpha i.e. intermediate constant for taps update */
+ alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+ /* Initialize pState pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ *pb++ += (q15_t) (((q31_t) alpha * (*px++)) >> 15);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ start of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy (numTaps - 1u) samples */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_q31.c
new file mode 100644
index 000000000..0356133df
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/FilteringFunctions/arm_lms_q31.c
@@ -0,0 +1,369 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_lms_q31.c
+*
+* Description: Processing function for the Q31 LMS filter.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**
+ * @ingroup groupFilters
+ */
+
+/**
+ * @addtogroup LMS
+ * @{
+ */
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ *
+ * \par Scaling and Overflow Behavior:
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate
+ * multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clips.
+ * In order to avoid overflows completely the input signal must be scaled down by
+ * log2(numTaps) bits.
+ * The reference signal should not be scaled down.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is shifted
+ * and saturated to 1.31 format to yield the final result.
+ * The output signal and error signal are in 1.31 format.
+ *
+ * \par
+ * In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.
+ */
+
+void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize)
+{
+ q31_t *pState = S->pState; /* State pointer */
+ uint32_t numTaps = S->numTaps; /* Number of filter coefficients in the filter */
+ q31_t *pCoeffs = S->pCoeffs; /* Coefficient pointer */
+ q31_t *pStateCurnt; /* Points to the current sample of the state */
+ q31_t mu = S->mu; /* Adaptive factor */
+ q31_t *px; /* Temporary pointer for state */
+ q31_t *pb; /* Temporary pointer for coefficient buffer */
+ uint32_t tapCnt, blkCnt; /* Loop counters */
+ q63_t acc; /* Accumulator */
+ q31_t e = 0; /* error of data sample */
+ q31_t alpha; /* Intermediate constant for taps update */
+ q31_t coef; /* Temporary variable for coef */
+ q31_t acc_l, acc_h; /* temporary input */
+ uint32_t uShift = ((uint32_t) S->postShift + 1u);
+ uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
+
+ /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+ /* pStateCurnt points to the location where the new input data should be written */
+ pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+ /* Initializing blkCnt with blockSize */
+ blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize state pointer */
+ px = pState;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ /* acc += b[N] * x[n-N] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-1] * x[n-N-1] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-2] * x[n-N-2] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* acc += b[N-3] * x[n-N-3] */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ /* Store the result from accumulator into the destination buffer. */
+ *pOut++ = (q31_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q31_t) acc;
+
+ *pErr++ = (q31_t) e;
+
+ /* Compute alpha i.e. intermediate constant for taps update */
+ alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+ /* Initialize state pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize coefficient pointer */
+ pb = pCoeffs;
+
+ /* Loop unrolling. Process 4 taps at a time. */
+ tapCnt = numTaps >> 2;
+
+ /* Update filter coefficients */
+ while(tapCnt > 0u)
+ {
+ /* coef is in 2.30 format */
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ /* get coef in 1.31 format by left shifting */
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ /* update coefficient buffer to next coefficient */
+ pb++;
+
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+ tapCnt = numTaps % 0x4u;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ satrt of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Loop unrolling for (numTaps - 1u) samples copy */
+ tapCnt = (numTaps - 1u) >> 2u;
+
+ /* copy data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Calculate remaining number of copies */
+ tapCnt = (numTaps - 1u) % 0x4u;
+
+ /* Copy the remaining q31_t data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ while(blkCnt > 0u)
+ {
+ /* Copy the new input sample into the state buffer */
+ *pStateCurnt++ = *pSrc++;
+
+ /* Initialize pState pointer */
+ px = pState;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Set the accumulator to zero */
+ acc = 0;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ acc += ((q63_t) (*px++)) * (*pb++);
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Converting the result to 1.31 format */
+ /* Store the result from accumulator into the destination buffer. */
+ /* Calc lower part of acc */
+ acc_l = acc & 0xffffffff;
+
+ /* Calc upper part of acc */
+ acc_h = (acc >> 32) & 0xffffffff;
+
+ acc = (uint32_t) acc_l >> lShift | acc_h << uShift;
+
+ *pOut++ = (q31_t) acc;
+
+ /* Compute and store error */
+ e = *pRef++ - (q31_t) acc;
+
+ *pErr++ = (q31_t) e;
+
+ /* Weighting factor for the LMS version */
+ alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+ /* Initialize pState pointer */
+ /* Advance state pointer by 1 for the next sample */
+ px = pState++;
+
+ /* Initialize pCoeffs pointer */
+ pb = pCoeffs;
+
+ /* Loop over numTaps number of values */
+ tapCnt = numTaps;
+
+ while(tapCnt > 0u)
+ {
+ /* Perform the multiply-accumulate */
+ coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+ *pb += (coef << 1u);
+ pb++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Processing is complete. Now copy the last numTaps - 1 samples to the
+ start of the state buffer. This prepares the state buffer for the
+ next function call. */
+
+ /* Points to the start of the pState buffer */
+ pStateCurnt = S->pState;
+
+ /* Copy (numTaps - 1u) samples */
+ tapCnt = (numTaps - 1u);
+
+ /* Copy the data */
+ while(tapCnt > 0u)
+ {
+ *pStateCurnt++ = *pState++;
+
+ /* Decrement the loop counter */
+ tapCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of LMS group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_f32.c
new file mode 100644
index 000000000..5bb93007b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_f32.c
@@ -0,0 +1,208 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_add_f32.c
+*
+* Description: Floating-point matrix addition
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixAdd Matrix Addition
+ *
+ * Adds two matrices.
+ * \image html MatrixAddition.gif "Addition of two 3 x 3 matrices"
+ *
+ * The functions check to make sure that
+ * <code>pSrcA</code>, <code>pSrcB</code>, and <code>pDst</code> have the same
+ * number of rows and columns.
+ */
+
+/**
+ * @addtogroup MatrixAdd
+ * @{
+ */
+
+
+/**
+ * @brief Floating-point matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ float32_t inA1, inA2, inB1, inB2, out1, out2; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif
+ {
+
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Loop unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add and then store the results in the destination buffer. */
+ /* Read values from source A */
+ inA1 = pIn1[0];
+
+ /* Read values from source B */
+ inB1 = pIn2[0];
+
+ /* Read values from source A */
+ inA2 = pIn1[1];
+
+ /* out = sourceA + sourceB */
+ out1 = inA1 + inB1;
+
+ /* Read values from source B */
+ inB2 = pIn2[1];
+
+ /* Read values from source A */
+ inA1 = pIn1[2];
+
+ /* out = sourceA + sourceB */
+ out2 = inA2 + inB2;
+
+ /* Read values from source B */
+ inB1 = pIn2[2];
+
+ /* Store result in destination */
+ pOut[0] = out1;
+ pOut[1] = out2;
+
+ /* Read values from source A */
+ inA2 = pIn1[3];
+
+ /* Read values from source B */
+ inB2 = pIn2[3];
+
+ /* out = sourceA + sourceB */
+ out1 = inA1 + inB1;
+
+ /* out = sourceA + sourceB */
+ out2 = inA2 + inB2;
+
+ /* Store result in destination */
+ pOut[2] = out1;
+
+ /* Store result in destination */
+ pOut[3] = out2;
+
+
+ /* update pointers to process next sampels */
+ pIn1 += 4u;
+ pIn2 += 4u;
+ pOut += 4u;
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add and then store the results in the destination buffer. */
+ *pOut++ = (*pIn1++) + (*pIn2++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixAdd group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_q15.c
new file mode 100644
index 000000000..668937648
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_q15.c
@@ -0,0 +1,163 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_add_q15.c
+*
+* Description: Q15 matrix addition
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixAdd
+ * @{
+ */
+
+/**
+ * @brief Q15 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst)
+{
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint16_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint16_t) (pSrcA->numRows * pSrcA->numCols);
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop unrolling */
+ blkCnt = (uint32_t) numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, Saturate and then store the results in the destination buffer. */
+ *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+ *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = (uint32_t) numSamples % 0x4u;
+
+ /* q15 pointers of input and output are initialized */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, Saturate and then store the results in the destination buffer. */
+ *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = (uint32_t) numSamples;
+
+
+ /* q15 pointers of input and output are initialized */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, Saturate and then store the results in the destination buffer. */
+ *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ + *pInB++), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixAdd group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_q31.c
new file mode 100644
index 000000000..08f06f08e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_add_q31.c
@@ -0,0 +1,207 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_add_q31.c
+*
+* Description: Q31 matrix addition
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixAdd
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t inA1, inB1; /* temporary variables */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t inA2, inB2; /* temporary variables */
+ q31_t out1, out2; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, saturate and then store the results in the destination buffer. */
+ /* Read values from source A */
+ inA1 = pIn1[0];
+
+ /* Read values from source B */
+ inB1 = pIn2[0];
+
+ /* Read values from source A */
+ inA2 = pIn1[1];
+
+ /* Add and saturate */
+ out1 = __QADD(inA1, inB1);
+
+ /* Read values from source B */
+ inB2 = pIn2[1];
+
+ /* Read values from source A */
+ inA1 = pIn1[2];
+
+ /* Add and saturate */
+ out2 = __QADD(inA2, inB2);
+
+ /* Read values from source B */
+ inB1 = pIn2[2];
+
+ /* Store result in destination */
+ pOut[0] = out1;
+ pOut[1] = out2;
+
+ /* Read values from source A */
+ inA2 = pIn1[3];
+
+ /* Read values from source B */
+ inB2 = pIn2[3];
+
+ /* Add and saturate */
+ out1 = __QADD(inA1, inB1);
+ out2 = __QADD(inA2, inB2);
+
+ /* Store result in destination */
+ pOut[2] = out1;
+ pOut[3] = out2;
+
+ /* update pointers to process next sampels */
+ pIn1 += 4u;
+ pIn2 += 4u;
+ pOut += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) + B(m,n) */
+ /* Add, saturate and then store the results in the destination buffer. */
+ inA1 = *pIn1++;
+ inB1 = *pIn2++;
+
+ inA1 = __QADD(inA1, inB1);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ *pOut++ = inA1;
+
+ }
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixAdd group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_f32.c
new file mode 100644
index 000000000..6932adcba
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_f32.c
@@ -0,0 +1,88 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_init_f32.c
+*
+* Description: Floating-point matrix initialization.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixInit Matrix Initialization
+ *
+ * Initializes the underlying matrix data structure.
+ * The functions set the <code>numRows</code>,
+ * <code>numCols</code>, and <code>pData</code> fields
+ * of the matrix data structure.
+ */
+
+/**
+ * @addtogroup MatrixInit
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData)
+{
+ /* Assign Number of Rows */
+ S->numRows = nRows;
+
+ /* Assign Number of Columns */
+ S->numCols = nColumns;
+
+ /* Assign Data pointer */
+ S->pData = pData;
+}
+
+/**
+ * @} end of MatrixInit group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_q15.c
new file mode 100644
index 000000000..2c499b1ce
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_q15.c
@@ -0,0 +1,80 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_init_q15.c
+*
+* Description: Q15 matrix initialization.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixInit
+ * @{
+ */
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData)
+{
+ /* Assign Number of Rows */
+ S->numRows = nRows;
+
+ /* Assign Number of Columns */
+ S->numCols = nColumns;
+
+ /* Assign Data pointer */
+ S->pData = pData;
+}
+
+/**
+ * @} end of MatrixInit group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_q31.c
new file mode 100644
index 000000000..5dabc779c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_init_q31.c
@@ -0,0 +1,84 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_init_q31.c
+*
+* Description: Q31 matrix initialization.
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixInit Matrix Initialization
+ *
+ */
+
+/**
+ * @addtogroup MatrixInit
+ * @{
+ */
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData)
+{
+ /* Assign Number of Rows */
+ S->numRows = nRows;
+
+ /* Assign Number of Columns */
+ S->numCols = nColumns;
+
+ /* Assign Data pointer */
+ S->pData = pData;
+}
+
+/**
+ * @} end of MatrixInit group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_inverse_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_inverse_f32.c
new file mode 100644
index 000000000..52d83aa7d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_inverse_f32.c
@@ -0,0 +1,700 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 1. March 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_inverse_f32.c
+*
+* Description: Floating-point matrix inverse.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixInv Matrix Inverse
+ *
+ * Computes the inverse of a matrix.
+ *
+ * The inverse is defined only if the input matrix is square and non-singular (the determinant
+ * is non-zero). The function checks that the input and output matrices are square and of the
+ * same size.
+ *
+ * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix
+ * inversion of floating-point matrices.
+ *
+ * \par Algorithm
+ * The Gauss-Jordan method is used to find the inverse.
+ * The algorithm performs a sequence of elementary row-operations till it
+ * reduces the input matrix to an identity matrix. Applying the same sequence
+ * of elementary row-operations to an identity matrix yields the inverse matrix.
+ * If the input matrix is singular, then the algorithm terminates and returns error status
+ * <code>ARM_MATH_SINGULAR</code>.
+ * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"
+ */
+
+/**
+ * @addtogroup MatrixInv
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *pSrc points to input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns
+ * <code>ARM_MATH_SIZE_MISMATCH</code> if the input matrix is not square or if the size
+ * of the output matrix does not match the size of the input matrix.
+ * If the input matrix is found to be singular (non-invertible), then the function returns
+ * <code>ARM_MATH_SINGULAR</code>. Otherwise, the function returns <code>ARM_MATH_SUCCESS</code>.
+ */
+
+arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn = pSrc->pData; /* input data matrix pointer */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+ float32_t *pInT1, *pInT2; /* Temporary input data matrix pointer */
+ float32_t *pInT3, *pInT4; /* Temporary output data matrix pointer */
+ float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst; /* Temporary input and output data matrix pointer */
+ uint32_t numRows = pSrc->numRows; /* Number of rows in the matrix */
+ uint32_t numCols = pSrc->numCols; /* Number of Cols in the matrix */
+
+#ifndef ARM_MATH_CM0_FAMILY
+ float32_t maxC; /* maximum value in the column */
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t Xchg, in = 0.0f, in1; /* Temporary input values */
+ uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l; /* loop counters */
+ arm_status status; /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+ || (pSrc->numRows != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+
+ /*--------------------------------------------------------------------------------------------------------------
+ * Matrix Inverse can be solved using elementary row operations.
+ *
+ * Gauss-Jordan Method:
+ *
+ * 1. First combine the identity matrix and the input matrix separated by a bar to form an
+ * augmented matrix as follows:
+ * _ _ _ _
+ * | a11 a12 | 1 0 | | X11 X12 |
+ * | | | = | |
+ * |_ a21 a22 | 0 1 _| |_ X21 X21 _|
+ *
+ * 2. In our implementation, pDst Matrix is used as identity matrix.
+ *
+ * 3. Begin with the first row. Let i = 1.
+ *
+ * 4. Check to see if the pivot for column i is the greatest of the column.
+ * The pivot is the element of the main diagonal that is on the current row.
+ * For instance, if working with row i, then the pivot element is aii.
+ * If the pivot is not the most significant of the coluimns, exchange that row with a row
+ * below it that does contain the most significant value in column i. If the most
+ * significant value of the column is zero, then an inverse to that matrix does not exist.
+ * The most significant value of the column is the absolut maximum.
+ *
+ * 5. Divide every element of row i by the pivot.
+ *
+ * 6. For every row below and row i, replace that row with the sum of that row and
+ * a multiple of row i so that each new element in column i below row i is zero.
+ *
+ * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
+ * for every element below and above the main diagonal.
+ *
+ * 8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).
+ * Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).
+ *----------------------------------------------------------------------------------------------------------------*/
+
+ /* Working pointer for destination matrix */
+ pInT2 = pOut;
+
+ /* Loop over the number of rows */
+ rowCnt = numRows;
+
+ /* Making the destination matrix as identity matrix */
+ while(rowCnt > 0u)
+ {
+ /* Writing all zeroes in lower triangle of the destination matrix */
+ j = numRows - rowCnt;
+ while(j > 0u)
+ {
+ *pInT2++ = 0.0f;
+ j--;
+ }
+
+ /* Writing all ones in the diagonal of the destination matrix */
+ *pInT2++ = 1.0f;
+
+ /* Writing all zeroes in upper triangle of the destination matrix */
+ j = rowCnt - 1u;
+ while(j > 0u)
+ {
+ *pInT2++ = 0.0f;
+ j--;
+ }
+
+ /* Decrement the loop counter */
+ rowCnt--;
+ }
+
+ /* Loop over the number of columns of the input matrix.
+ All the elements in each column are processed by the row operations */
+ loopCnt = numCols;
+
+ /* Index modifier to navigate through the columns */
+ l = 0u;
+
+ while(loopCnt > 0u)
+ {
+ /* Check if the pivot element is zero..
+ * If it is zero then interchange the row with non zero row below.
+ * If there is no non zero element to replace in the rows below,
+ * then the matrix is Singular. */
+
+ /* Working pointer for the input matrix that points
+ * to the pivot element of the particular row */
+ pInT1 = pIn + (l * numCols);
+
+ /* Working pointer for the destination matrix that points
+ * to the pivot element of the particular row */
+ pInT3 = pOut + (l * numCols);
+
+ /* Temporary variable to hold the pivot value */
+ in = *pInT1;
+
+ /* Destination pointer modifier */
+ k = 1u;
+
+ /* Grab the most significant value from column l */
+ maxC = 0;
+ for (i = 0; i < numRows; i++)
+ {
+ maxC = *pInT1 > 0 ? (*pInT1 > maxC ? *pInT1 : maxC) : (-*pInT1 > maxC ? -*pInT1 : maxC);
+ pInT1 += numCols;
+ }
+
+ /* Update the status if the matrix is singular */
+ if(maxC == 0.0f)
+ {
+ status = ARM_MATH_SINGULAR;
+ break;
+ }
+
+ /* Restore pInT1 */
+ pInT1 -= numRows * numCols;
+
+ /* Check if the pivot element is the most significant of the column */
+ if( (in > 0.0f ? in : -in) != maxC)
+ {
+ /* Loop over the number rows present below */
+ i = numRows - (l + 1u);
+
+ while(i > 0u)
+ {
+ /* Update the input and destination pointers */
+ pInT2 = pInT1 + (numCols * l);
+ pInT4 = pInT3 + (numCols * k);
+
+ /* Look for the most significant element to
+ * replace in the rows below */
+ if((*pInT2 > 0.0f ? *pInT2: -*pInT2) == maxC)
+ {
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ j = numCols - l;
+
+ while(j > 0u)
+ {
+ /* Exchange the row elements of the input matrix */
+ Xchg = *pInT2;
+ *pInT2++ = *pInT1;
+ *pInT1++ = Xchg;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over number of columns of the destination matrix */
+ j = numCols;
+
+ while(j > 0u)
+ {
+ /* Exchange the row elements of the destination matrix */
+ Xchg = *pInT4;
+ *pInT4++ = *pInT3;
+ *pInT3++ = Xchg;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Flag to indicate whether exchange is done or not */
+ flag = 1u;
+
+ /* Break after exchange is done */
+ break;
+ }
+
+ /* Update the destination pointer modifier */
+ k++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+ }
+
+ /* Update the status if the matrix is singular */
+ if((flag != 1u) && (in == 0.0f))
+ {
+ status = ARM_MATH_SINGULAR;
+
+ break;
+ }
+
+ /* Points to the pivot row of input and destination matrices */
+ pPivotRowIn = pIn + (l * numCols);
+ pPivotRowDst = pOut + (l * numCols);
+
+ /* Temporary pointers to the pivot row pointers */
+ pInT1 = pPivotRowIn;
+ pInT2 = pPivotRowDst;
+
+ /* Pivot element of the row */
+ in = *pPivotRowIn;
+
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ j = (numCols - l);
+
+ while(j > 0u)
+ {
+ /* Divide each element of the row of the input matrix
+ * by the pivot element */
+ in1 = *pInT1;
+ *pInT1++ = in1 / in;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over number of columns of the destination matrix */
+ j = numCols;
+
+ while(j > 0u)
+ {
+ /* Divide each element of the row of the destination matrix
+ * by the pivot element */
+ in1 = *pInT2;
+ *pInT2++ = in1 / in;
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Replace the rows with the sum of that row and a multiple of row i
+ * so that each new element in column i above row i is zero.*/
+
+ /* Temporary pointers for input and destination matrices */
+ pInT1 = pIn;
+ pInT2 = pOut;
+
+ /* index used to check for pivot element */
+ i = 0u;
+
+ /* Loop over number of rows */
+ /* to be replaced by the sum of that row and a multiple of row i */
+ k = numRows;
+
+ while(k > 0u)
+ {
+ /* Check for the pivot element */
+ if(i == l)
+ {
+ /* If the processing element is the pivot element,
+ only the columns to the right are to be processed */
+ pInT1 += numCols - l;
+
+ pInT2 += numCols;
+ }
+ else
+ {
+ /* Element of the reference row */
+ in = *pInT1;
+
+ /* Working pointers for input and destination pivot rows */
+ pPRT_in = pPivotRowIn;
+ pPRT_pDst = pPivotRowDst;
+
+ /* Loop over the number of columns to the right of the pivot element,
+ to replace the elements in the input matrix */
+ j = (numCols - l);
+
+ while(j > 0u)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ in1 = *pInT1;
+ *pInT1++ = in1 - (in * *pPRT_in++);
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ /* Loop over the number of columns to
+ replace the elements in the destination matrix */
+ j = numCols;
+
+ while(j > 0u)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ in1 = *pInT2;
+ *pInT2++ = in1 - (in * *pPRT_pDst++);
+
+ /* Decrement the loop counter */
+ j--;
+ }
+
+ }
+
+ /* Increment the temporary input pointer */
+ pInT1 = pInT1 + l;
+
+ /* Decrement the loop counter */
+ k--;
+
+ /* Increment the pivot index */
+ i++;
+ }
+
+ /* Increment the input pointer */
+ pIn++;
+
+ /* Decrement the loop counter */
+ loopCnt--;
+
+ /* Increment the index modifier */
+ l++;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t Xchg, in = 0.0f; /* Temporary input values */
+ uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l; /* loop counters */
+ arm_status status; /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+ || (pSrc->numRows != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+ {
+
+ /*--------------------------------------------------------------------------------------------------------------
+ * Matrix Inverse can be solved using elementary row operations.
+ *
+ * Gauss-Jordan Method:
+ *
+ * 1. First combine the identity matrix and the input matrix separated by a bar to form an
+ * augmented matrix as follows:
+ * _ _ _ _ _ _ _ _
+ * | | a11 a12 | | | 1 0 | | | X11 X12 |
+ * | | | | | | | = | |
+ * |_ |_ a21 a22 _| | |_0 1 _| _| |_ X21 X21 _|
+ *
+ * 2. In our implementation, pDst Matrix is used as identity matrix.
+ *
+ * 3. Begin with the first row. Let i = 1.
+ *
+ * 4. Check to see if the pivot for row i is zero.
+ * The pivot is the element of the main diagonal that is on the current row.
+ * For instance, if working with row i, then the pivot element is aii.
+ * If the pivot is zero, exchange that row with a row below it that does not
+ * contain a zero in column i. If this is not possible, then an inverse
+ * to that matrix does not exist.
+ *
+ * 5. Divide every element of row i by the pivot.
+ *
+ * 6. For every row below and row i, replace that row with the sum of that row and
+ * a multiple of row i so that each new element in column i below row i is zero.
+ *
+ * 7. Move to the next row and column and repeat steps 2 through 5 until you have zeros
+ * for every element below and above the main diagonal.
+ *
+ * 8. Now an identical matrix is formed to the left of the bar(input matrix, src).
+ * Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).
+ *----------------------------------------------------------------------------------------------------------------*/
+
+ /* Working pointer for destination matrix */
+ pInT2 = pOut;
+
+ /* Loop over the number of rows */
+ rowCnt = numRows;
+
+ /* Making the destination matrix as identity matrix */
+ while(rowCnt > 0u)
+ {
+ /* Writing all zeroes in lower triangle of the destination matrix */
+ j = numRows - rowCnt;
+ while(j > 0u)
+ {
+ *pInT2++ = 0.0f;
+ j--;
+ }
+
+ /* Writing all ones in the diagonal of the destination matrix */
+ *pInT2++ = 1.0f;
+
+ /* Writing all zeroes in upper triangle of the destination matrix */
+ j = rowCnt - 1u;
+ while(j > 0u)
+ {
+ *pInT2++ = 0.0f;
+ j--;
+ }
+
+ /* Decrement the loop counter */
+ rowCnt--;
+ }
+
+ /* Loop over the number of columns of the input matrix.
+ All the elements in each column are processed by the row operations */
+ loopCnt = numCols;
+
+ /* Index modifier to navigate through the columns */
+ l = 0u;
+ //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)
+ while(loopCnt > 0u)
+ {
+ /* Check if the pivot element is zero..
+ * If it is zero then interchange the row with non zero row below.
+ * If there is no non zero element to replace in the rows below,
+ * then the matrix is Singular. */
+
+ /* Working pointer for the input matrix that points
+ * to the pivot element of the particular row */
+ pInT1 = pIn + (l * numCols);
+
+ /* Working pointer for the destination matrix that points
+ * to the pivot element of the particular row */
+ pInT3 = pOut + (l * numCols);
+
+ /* Temporary variable to hold the pivot value */
+ in = *pInT1;
+
+ /* Destination pointer modifier */
+ k = 1u;
+
+ /* Check if the pivot element is zero */
+ if(*pInT1 == 0.0f)
+ {
+ /* Loop over the number rows present below */
+ for (i = (l + 1u); i < numRows; i++)
+ {
+ /* Update the input and destination pointers */
+ pInT2 = pInT1 + (numCols * l);
+ pInT4 = pInT3 + (numCols * k);
+
+ /* Check if there is a non zero pivot element to
+ * replace in the rows below */
+ if(*pInT2 != 0.0f)
+ {
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ for (j = 0u; j < (numCols - l); j++)
+ {
+ /* Exchange the row elements of the input matrix */
+ Xchg = *pInT2;
+ *pInT2++ = *pInT1;
+ *pInT1++ = Xchg;
+ }
+
+ for (j = 0u; j < numCols; j++)
+ {
+ Xchg = *pInT4;
+ *pInT4++ = *pInT3;
+ *pInT3++ = Xchg;
+ }
+
+ /* Flag to indicate whether exchange is done or not */
+ flag = 1u;
+
+ /* Break after exchange is done */
+ break;
+ }
+
+ /* Update the destination pointer modifier */
+ k++;
+ }
+ }
+
+ /* Update the status if the matrix is singular */
+ if((flag != 1u) && (in == 0.0f))
+ {
+ status = ARM_MATH_SINGULAR;
+
+ break;
+ }
+
+ /* Points to the pivot row of input and destination matrices */
+ pPivotRowIn = pIn + (l * numCols);
+ pPivotRowDst = pOut + (l * numCols);
+
+ /* Temporary pointers to the pivot row pointers */
+ pInT1 = pPivotRowIn;
+ pInT2 = pPivotRowDst;
+
+ /* Pivot element of the row */
+ in = *(pIn + (l * numCols));
+
+ /* Loop over number of columns
+ * to the right of the pilot element */
+ for (j = 0u; j < (numCols - l); j++)
+ {
+ /* Divide each element of the row of the input matrix
+ * by the pivot element */
+ *pInT1 = *pInT1 / in;
+ pInT1++;
+ }
+ for (j = 0u; j < numCols; j++)
+ {
+ /* Divide each element of the row of the destination matrix
+ * by the pivot element */
+ *pInT2 = *pInT2 / in;
+ pInT2++;
+ }
+
+ /* Replace the rows with the sum of that row and a multiple of row i
+ * so that each new element in column i above row i is zero.*/
+
+ /* Temporary pointers for input and destination matrices */
+ pInT1 = pIn;
+ pInT2 = pOut;
+
+ for (i = 0u; i < numRows; i++)
+ {
+ /* Check for the pivot element */
+ if(i == l)
+ {
+ /* If the processing element is the pivot element,
+ only the columns to the right are to be processed */
+ pInT1 += numCols - l;
+ pInT2 += numCols;
+ }
+ else
+ {
+ /* Element of the reference row */
+ in = *pInT1;
+
+ /* Working pointers for input and destination pivot rows */
+ pPRT_in = pPivotRowIn;
+ pPRT_pDst = pPivotRowDst;
+
+ /* Loop over the number of columns to the right of the pivot element,
+ to replace the elements in the input matrix */
+ for (j = 0u; j < (numCols - l); j++)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ *pInT1 = *pInT1 - (in * *pPRT_in++);
+ pInT1++;
+ }
+ /* Loop over the number of columns to
+ replace the elements in the destination matrix */
+ for (j = 0u; j < numCols; j++)
+ {
+ /* Replace the element by the sum of that row
+ and a multiple of the reference row */
+ *pInT2 = *pInT2 - (in * *pPRT_pDst++);
+ pInT2++;
+ }
+
+ }
+ /* Increment the temporary input pointer */
+ pInT1 = pInT1 + l;
+ }
+ /* Increment the input pointer */
+ pIn++;
+
+ /* Decrement the loop counter */
+ loopCnt--;
+ /* Increment the index modifier */
+ l++;
+ }
+
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+
+ if((flag != 1u) && (in == 0.0f))
+ {
+ status = ARM_MATH_SINGULAR;
+ }
+ }
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixInv group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_f32.c
new file mode 100644
index 000000000..bae73f146
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_f32.c
@@ -0,0 +1,286 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_f32.c
+*
+* Description: Floating-point matrix multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixMult Matrix Multiplication
+ *
+ * Multiplies two matrices.
+ *
+ * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices"
+
+ * Matrix multiplication is only defined if the number of columns of the
+ * first matrix equals the number of rows of the second matrix.
+ * Multiplying an <code>M x N</code> matrix with an <code>N x P</code> matrix results
+ * in an <code>M x P</code> matrix.
+ * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of
+ * <code>pSrcA</code> and <code>pSrcB</code> are equal; and (2) that the size of the output
+ * matrix equals the outer dimensions of <code>pSrcA</code> and <code>pSrcB</code>.
+ */
+
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix multiplication.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ float32_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+ float32_t *px; /* Temporary output data matrix pointer */
+ float32_t sum; /* Accumulator */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t in1, in2, in3, in4;
+ uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0u;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0.0f;
+
+ /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+ pIn1 = pInA;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2u;
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ in3 = *pIn2;
+ pIn2 += numColsB;
+ in1 = pIn1[0];
+ in2 = pIn1[1];
+ sum += in1 * in3;
+ in4 = *pIn2;
+ pIn2 += numColsB;
+ sum += in2 * in4;
+
+ in3 = *pIn2;
+ pIn2 += numColsB;
+ in1 = pIn1[2];
+ in2 = pIn1[3];
+ sum += in1 * in3;
+ in4 = *pIn2;
+ pIn2 += numColsB;
+ sum += in2 * in4;
+ pIn1 += 4u;
+
+ /* Decrement the loop count */
+ colCnt--;
+ }
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA % 0x4u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ sum += *pIn1++ * (*pIn2);
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Store the result in the destination buffer */
+ *px++ = sum;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ j++;
+ pIn2 = pSrcB->pData + j;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t *pInB = pSrcB->pData; /* input data matrix pointer B */
+ uint16_t col, i = 0u, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pInA with each column in pInB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0.0f;
+
+ /* Initialize the pointer pIn1 to point to the starting address of the row being processed */
+ pIn1 = pInA;
+
+ /* Matrix A columns number of MAC operations are to be performed */
+ colCnt = numColsA;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ sum += *pIn1++ * (*pIn2);
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Store the result in the destination buffer */
+ *px++ = sum;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ pIn2 = pInB + (numColsB - col);
+
+ } while(col > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Update the pointer pInA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_fast_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_fast_q15.c
new file mode 100644
index 000000000..cf587ef16
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_fast_q15.c
@@ -0,0 +1,369 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_fast_q15.c
+*
+* Description: Q15 matrix multiplication (fast variant)
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The difference between the function arm_mat_mult_q15() and this fast variant is that
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.
+ * The result of each 1.15 x 1.15 multiplication is truncated to
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30
+ * format. Finally, the accumulator is saturated and converted to a 1.15 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides
+ * less precision since it discards the low 16 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * Scale down one of the input matrices by log2(numColsA) bits to
+ * avoid overflows, as a total of numColsA additions are computed internally for each
+ * output element.
+ *
+ * \par
+ * See <code>arm_mat_mult_q15()</code> for a slower implementation of this function
+ * which uses 64-bit accumulation to provide higher precision.
+ */
+
+arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState)
+{
+ q31_t sum; /* accumulator */
+ q15_t *pSrcBT = pState; /* input data matrix pointer for transpose */
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
+ q15_t *px; /* Temporary output data matrix pointer */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */
+ uint16_t col, i = 0u, row = numRowsB, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q31_t in; /* Temporary variable to hold the input value */
+ q31_t inA1, inA2, inB1, inB2;
+
+#else
+
+ q15_t in; /* Temporary variable to hold the input value */
+ q15_t inA1, inA2, inB1, inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif
+ {
+ /* Matrix transpose */
+ do
+ {
+ /* Apply loop unrolling and exchange the columns with row elements */
+ col = numColsB >> 2;
+
+ /* The pointer px is set to starting address of the column being processed */
+ px = pSrcBT + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(col > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) in;
+
+#else
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *px = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) in;
+
+#else
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *px = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+#else
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ col = numColsB % 0x4u;
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pInB++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* Reset the variables for the usage in the following multiplication process */
+ row = numRowsA;
+ i = 0u;
+ px = pDst->pData;
+
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the transposed pSrcB data */
+ pInB = pSrcBT;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 2 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+ /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+ pInA = pSrcA->pData + i;
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ inA1 = *__SIMD32(pInA)++;
+ inB1 = *__SIMD32(pInB)++;
+ inA2 = *__SIMD32(pInA)++;
+ inB2 = *__SIMD32(pInB)++;
+
+ sum = __SMLAD(inA1, inB1, sum);
+ sum = __SMLAD(inA2, inB2, sum);
+
+#else
+
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ inA2 = *pInA++;
+ sum += inA1 * inB1;
+ inB2 = *pInB++;
+
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ sum += inA2 * inB2;
+ inA2 = *pInA++;
+ inB2 = *pInB++;
+
+ sum += inA1 * inB1;
+ sum += inA2 * inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* process odd column samples */
+ colCnt = numColsA % 0x4u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ sum += (q31_t) (*pInA++) * (*pInB++);
+
+ colCnt--;
+ }
+
+ /* Saturate and store the result in the destination buffer */
+ *px = (q15_t) (sum >> 15);
+ px++;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+ i = i + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_fast_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_fast_q31.c
new file mode 100644
index 000000000..1c5f41434
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_fast_q31.c
@@ -0,0 +1,226 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_fast_q31.c
+*
+* Description: Q31 matrix multiplication (fast variant).
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The difference between the function arm_mat_mult_q31() and this fast variant is that
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.
+ * The result of each 1.31 x 1.31 multiplication is truncated to
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30
+ * format. Finally, the accumulator is saturated and converted to a 1.31 result.
+ *
+ * \par
+ * The fast version has the same overflow behavior as the standard version but provides
+ * less precision since it discards the low 32 bits of each multiplication result.
+ * In order to avoid overflows completely the input signals must be scaled down.
+ * Scale down one of the input matrices by log2(numColsA) bits to
+ * avoid overflows, as a total of numColsA additions are computed internally for each
+ * output element.
+ *
+ * \par
+ * See <code>arm_mat_mult_q31()</code> for a slower implementation of this function
+ * which uses 64-bit accumulation to provide higher precision.
+ */
+
+arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+// q31_t *pSrcB = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t *px; /* Temporary output data matrix pointer */
+ q31_t sum; /* Accumulator */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+ q31_t inA1, inA2, inA3, inA4, inB1, inB2, inB3, inB4;
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0u;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Initiate the pointer pIn1 to point to the starting address of pInA */
+ pIn1 = pInA;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ inB1 = *pIn2;
+ pIn2 += numColsB;
+
+ inA1 = pIn1[0];
+ inA2 = pIn1[1];
+
+ inB2 = *pIn2;
+ pIn2 += numColsB;
+
+ inB3 = *pIn2;
+ pIn2 += numColsB;
+
+ sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA1 * inB1)) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA2 * inB2)) >> 32);
+
+ inA3 = pIn1[2];
+ inA4 = pIn1[3];
+
+ inB4 = *pIn2;
+ pIn2 += numColsB;
+
+ sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA3 * inB3)) >> 32);
+ sum = (q31_t) ((((q63_t) sum << 32) + ((q63_t) inA4 * inB4)) >> 32);
+
+ pIn1 += 4u;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA % 0x4u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ sum = (q31_t) ((((q63_t) sum << 32) +
+ ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
+ *px++ = sum << 1;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ j++;
+ pIn2 = pSrcB->pData + j;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+ /* Update the pointer pInA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_q15.c
new file mode 100644
index 000000000..1e112ab77
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_q15.c
@@ -0,0 +1,469 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_q15.c
+*
+* Description: Q15 matrix multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+
+/**
+ * @brief Q15 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator. The inputs to the
+ * multiplications are in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate
+ * results are accumulated in a 64-bit accumulator in 34.30 format. This approach
+ * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then
+ * truncated to 34.15 format by discarding the low 15 bits and then saturated to
+ * 1.15 format.
+ *
+ * \par
+ * Refer to <code>arm_mat_mult_fast_q15()</code> for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.
+ *
+ */
+
+arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState CMSIS_UNUSED)
+{
+ q63_t sum; /* accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q15_t *pSrcBT = pState; /* input data matrix pointer for transpose */
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
+ q15_t *px; /* Temporary output data matrix pointer */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ uint16_t numRowsB = pSrcB->numRows; /* number of rows of input matrix A */
+ uint16_t col, i = 0u, row = numRowsB, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q31_t in; /* Temporary variable to hold the input value */
+ q31_t pSourceA1, pSourceB1, pSourceA2, pSourceB2;
+
+#else
+
+ q15_t in; /* Temporary variable to hold the input value */
+ q15_t inA1, inB1, inA2, inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+ {
+ /* Matrix transpose */
+ do
+ {
+ /* Apply loop unrolling and exchange the columns with row elements */
+ col = numColsB >> 2;
+
+ /* The pointer px is set to starting address of the column being processed */
+ px = pSrcBT + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(col > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) in;
+
+#else
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *px = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pInB)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) in;
+
+#else
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *px = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+#else
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Read one element from the row */
+ in = *pInB++;
+
+ /* Store one element in the destination */
+ *px = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ col = numColsB % 0x4u;
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pInB++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += numRowsB;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* Reset the variables for the usage in the following multiplication process */
+ row = numRowsA;
+ i = 0u;
+ px = pDst->pData;
+
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the transposed pSrcB data */
+ pInB = pSrcBT;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Apply loop unrolling and compute 2 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+ /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+ pInA = pSrcA->pData + i;
+
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ pSourceA1 = *__SIMD32(pInA)++;
+ pSourceB1 = *__SIMD32(pInB)++;
+
+ pSourceA2 = *__SIMD32(pInA)++;
+ pSourceB2 = *__SIMD32(pInB)++;
+
+ /* Multiply and Accumlates */
+ sum = __SMLALD(pSourceA1, pSourceB1, sum);
+ sum = __SMLALD(pSourceA2, pSourceB2, sum);
+
+#else
+ /* read real and imag values from pSrcA and pSrcB buffer */
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ inA2 = *pInA++;
+ /* Multiply and Accumlates */
+ sum += inA1 * inB1;
+ inB2 = *pInB++;
+
+ inA1 = *pInA++;
+ inB1 = *pInB++;
+ /* Multiply and Accumlates */
+ sum += inA2 * inB2;
+ inA2 = *pInA++;
+ inB2 = *pInB++;
+
+ /* Multiply and Accumlates */
+ sum += inA1 * inB1;
+ sum += inA2 * inB2;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* process remaining column samples */
+ colCnt = numColsA & 3u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ sum += *pInA++ * *pInB++;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Saturate and store the result in the destination buffer */
+ *px = (q15_t) (__SSAT((sum >> 15), 16));
+ px++;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+ i = i + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q15_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A of Q15 type */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B of Q15 type */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ q15_t *px; /* Temporary output data matrix pointer */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t col, i = 0u, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Initiate the pointer pIn1 to point to the starting address of pSrcA */
+ pIn1 = pInA;
+
+ /* Matrix A columns number of MAC operations are to be performed */
+ colCnt = numColsA;
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ sum += (q31_t) * pIn1++ * *pIn2;
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */
+ /* Saturate and store the result in the destination buffer */
+ *px++ = (q15_t) __SSAT((sum >> 15), 16);
+
+ /* Decrement the column loop counter */
+ col--;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ pIn2 = pInB + (numColsB - col);
+
+ } while(col > 0u);
+
+ /* Update the pointer pSrcA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_q31.c
new file mode 100644
index 000000000..218b7f53f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_mult_q31.c
@@ -0,0 +1,294 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_mult_q31.c
+*
+* Description: Q31 matrix multiplication.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixMult
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate
+ * multiplication results but provides only a single guard bit. There is no saturation
+ * on intermediate additions. Thus, if the accumulator overflows it wraps around and
+ * distorts the result. The input signals should be scaled down to avoid intermediate
+ * overflows. The input is thus scaled down by log2(numColsA) bits
+ * to avoid overflows, as a total of numColsA additions are performed internally.
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.
+ *
+ * \par
+ * See <code>arm_mat_mult_fast_q31()</code> for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.
+ *
+ */
+
+arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t *px; /* Temporary output data matrix pointer */
+ q63_t sum; /* Accumulator */
+ uint16_t numRowsA = pSrcA->numRows; /* number of rows of input matrix A */
+ uint16_t numColsB = pSrcB->numCols; /* number of columns of input matrix B */
+ uint16_t numColsA = pSrcA->numCols; /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ uint16_t col, i = 0u, j, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+ q31_t a0, a1, a2, a3, b0, b1, b2, b3;
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ j = 0u;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Initiate the pointer pIn1 to point to the starting address of pInA */
+ pIn1 = pInA;
+
+ /* Apply loop unrolling and compute 4 MACs simultaneously. */
+ colCnt = numColsA >> 2;
+
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ b0 = *pIn2;
+ pIn2 += numColsB;
+
+ a0 = *pIn1++;
+ a1 = *pIn1++;
+
+ b1 = *pIn2;
+ pIn2 += numColsB;
+ b2 = *pIn2;
+ pIn2 += numColsB;
+
+ sum += (q63_t) a0 *b0;
+ sum += (q63_t) a1 *b1;
+
+ a2 = *pIn1++;
+ a3 = *pIn1++;
+
+ b3 = *pIn2;
+ pIn2 += numColsB;
+
+ sum += (q63_t) a2 *b2;
+ sum += (q63_t) a3 *b3;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ colCnt = numColsA % 0x4u;
+
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * pIn1++ * *pIn2;
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+ *px++ = (q31_t) (sum >> 31);
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ j++;
+ pIn2 = (pSrcB->pData) + j;
+
+ /* Decrement the column loop counter */
+ col--;
+
+ } while(col > 0u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q31_t *pInB = pSrcB->pData; /* input data matrix pointer B */
+ uint16_t col, i = 0u, row = numRowsA, colCnt; /* loop counters */
+ arm_status status; /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numCols != pSrcB->numRows) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+ /* row loop */
+ do
+ {
+ /* Output pointer is set to starting address of the row being processed */
+ px = pOut + i;
+
+ /* For every row wise process, the column loop counter is to be initiated */
+ col = numColsB;
+
+ /* For every row wise process, the pIn2 pointer is set
+ ** to the starting address of the pSrcB data */
+ pIn2 = pSrcB->pData;
+
+ /* column loop */
+ do
+ {
+ /* Set the variable sum, that acts as accumulator, to zero */
+ sum = 0;
+
+ /* Initiate the pointer pIn1 to point to the starting address of pInA */
+ pIn1 = pInA;
+
+ /* Matrix A columns number of MAC operations are to be performed */
+ colCnt = numColsA;
+
+ /* matrix multiplication */
+ while(colCnt > 0u)
+ {
+ /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+ /* Perform the multiply-accumulates */
+ sum += (q63_t) * pIn1++ * *pIn2;
+ pIn2 += numColsB;
+
+ /* Decrement the loop counter */
+ colCnt--;
+ }
+
+ /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+ *px++ = (q31_t) (sum >> 31);
+
+ /* Decrement the column loop counter */
+ col--;
+
+ /* Update the pointer pIn2 to point to the starting address of the next column */
+ pIn2 = pInB + (numColsB - col);
+
+ } while(col > 0u);
+
+#endif
+
+ /* Update the pointer pInA to point to the starting address of the next row */
+ i = i + numColsB;
+ pInA = pInA + numColsA;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixMult group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_f32.c
new file mode 100644
index 000000000..a242c91c9
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_f32.c
@@ -0,0 +1,181 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_scale_f32.c
+*
+* Description: Multiplies a floating-point matrix by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixScale Matrix Scale
+ *
+ * Multiplies a matrix by a scalar. This is accomplished by multiplying each element in the
+ * matrix by the scalar. For example:
+ * \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix"
+ *
+ * The function checks to make sure that the input and output matrices are of the same size.
+ *
+ * In the fixed-point Q15 and Q31 functions, <code>scale</code> is represented by
+ * a fractional multiplication <code>scaleFract</code> and an arithmetic shift <code>shift</code>.
+ * The shift allows the gain of the scaling operation to exceed 1.0.
+ * The overall scale factor applied to the fixed-point data is
+ * <pre>
+ * scale = scaleFract * 2^shift.
+ * </pre>
+ */
+
+/**
+ * @addtogroup MatrixScale
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix scaling.
+ * @param[in] *pSrc points to input matrix structure
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ */
+
+arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn = pSrc->pData; /* input data matrix pointer */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix scaling */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ float32_t in1, in2, in3, in4; /* temporary variables */
+ float32_t out1, out2, out3, out4; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * scale */
+ /* Scaling and results are stored in the destination buffer. */
+ in1 = pIn[0];
+ in2 = pIn[1];
+ in3 = pIn[2];
+ in4 = pIn[3];
+
+ out1 = in1 * scale;
+ out2 = in2 * scale;
+ out3 = in3 * scale;
+ out4 = in4 * scale;
+
+
+ pOut[0] = out1;
+ pOut[1] = out2;
+ pOut[2] = out3;
+ pOut[3] = out4;
+
+ /* update pointers to process next sampels */
+ pIn += 4u;
+ pOut += 4u;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * scale */
+ /* The results are stored in the destination buffer. */
+ *pOut++ = (*pIn++) * scale;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixScale group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_q15.c
new file mode 100644
index 000000000..bb28cfc11
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_q15.c
@@ -0,0 +1,183 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_scale_q15.c
+*
+* Description: Multiplies a Q15 matrix by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixScale
+ * @{
+ */
+
+/**
+ * @brief Q15 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.15 format.
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.
+ */
+
+arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst)
+{
+ q15_t *pIn = pSrc->pData; /* input data matrix pointer */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint32_t numSamples; /* total number of elements in the matrix */
+ int32_t totShift = 15 - shift; /* total shift to apply after scaling */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix scaling */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q15_t in1, in2, in3, in4;
+ q31_t out1, out2, out3, out4;
+ q31_t inA1, inA2;
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch */
+ if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif // #ifdef ARM_MATH_MATRIX_CHECK
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * k */
+ /* Scale, saturate and then store the results in the destination buffer. */
+ /* Reading 2 inputs from memory */
+ inA1 = _SIMD32_OFFSET(pIn);
+ inA2 = _SIMD32_OFFSET(pIn + 2);
+
+ /* C = A * scale */
+ /* Scale the inputs and then store the 2 results in the destination buffer
+ * in single cycle by packing the outputs */
+ out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
+ out2 = (q31_t) ((q15_t) inA1 * scaleFract);
+ out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
+ out4 = (q31_t) ((q15_t) inA2 * scaleFract);
+
+ out1 = out1 >> totShift;
+ inA1 = _SIMD32_OFFSET(pIn + 4);
+ out2 = out2 >> totShift;
+ inA2 = _SIMD32_OFFSET(pIn + 6);
+ out3 = out3 >> totShift;
+ out4 = out4 >> totShift;
+
+ in1 = (q15_t) (__SSAT(out1, 16));
+ in2 = (q15_t) (__SSAT(out2, 16));
+ in3 = (q15_t) (__SSAT(out3, 16));
+ in4 = (q15_t) (__SSAT(out4, 16));
+
+ _SIMD32_OFFSET(pOut) = __PKHBT(in2, in1, 16);
+ _SIMD32_OFFSET(pOut + 2) = __PKHBT(in4, in3, 16);
+
+ /* update pointers to process next sampels */
+ pIn += 4u;
+ pOut += 4u;
+
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * k */
+ /* Scale, saturate and then store the results in the destination buffer. */
+ *pOut++ =
+ (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixScale group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_q31.c
new file mode 100644
index 000000000..6b2b1046b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_scale_q31.c
@@ -0,0 +1,202 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_scale_q31.c
+*
+* Description: Multiplies a Q31 matrix by a scalar.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE. ------------------------------------------------ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixScale
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.31 format.
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.
+ */
+
+arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn = pSrc->pData; /* input data matrix pointer */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint32_t numSamples; /* total number of elements in the matrix */
+ int32_t totShift = shift + 1; /* shift to apply after scaling */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix scaling */
+ q31_t in1, in2, out1; /* temporary variabels */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t in3, in4, out2, out3, out4; /* temporary variables */
+
+#endif // #ifndef ARM_MAT_CM0
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch */
+ if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif // #ifdef ARM_MATH_MATRIX_CHECK
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * k */
+ /* Read values from input */
+ in1 = *pIn;
+ in2 = *(pIn + 1);
+ in3 = *(pIn + 2);
+ in4 = *(pIn + 3);
+
+ /* multiply input with scaler value */
+ in1 = ((q63_t) in1 * scaleFract) >> 32;
+ in2 = ((q63_t) in2 * scaleFract) >> 32;
+ in3 = ((q63_t) in3 * scaleFract) >> 32;
+ in4 = ((q63_t) in4 * scaleFract) >> 32;
+
+ /* apply shifting */
+ out1 = in1 << totShift;
+ out2 = in2 << totShift;
+
+ /* saturate the results. */
+ if(in1 != (out1 >> totShift))
+ out1 = 0x7FFFFFFF ^ (in1 >> 31);
+
+ if(in2 != (out2 >> totShift))
+ out2 = 0x7FFFFFFF ^ (in2 >> 31);
+
+ out3 = in3 << totShift;
+ out4 = in4 << totShift;
+
+ *pOut = out1;
+ *(pOut + 1) = out2;
+
+ if(in3 != (out3 >> totShift))
+ out3 = 0x7FFFFFFF ^ (in3 >> 31);
+
+ if(in4 != (out4 >> totShift))
+ out4 = 0x7FFFFFFF ^ (in4 >> 31);
+
+
+ *(pOut + 2) = out3;
+ *(pOut + 3) = out4;
+
+ /* update pointers to process next sampels */
+ pIn += 4u;
+ pOut += 4u;
+
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) * k */
+ /* Scale, saturate and then store the results in the destination buffer. */
+ in1 = *pIn++;
+
+ in2 = ((q63_t) in1 * scaleFract) >> 32;
+
+ out1 = in2 << totShift;
+
+ if(in2 != (out1 >> totShift))
+ out1 = 0x7FFFFFFF ^ (in2 >> 31);
+
+ *pOut++ = out1;
+
+ /* Decrement the numSamples loop counter */
+ blkCnt--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixScale group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_f32.c
new file mode 100644
index 000000000..0b83133ca
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_f32.c
@@ -0,0 +1,209 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_sub_f32.c
+*
+* Description: Floating-point matrix subtraction.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @defgroup MatrixSub Matrix Subtraction
+ *
+ * Subtract two matrices.
+ * \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices"
+ *
+ * The functions check to make sure that
+ * <code>pSrcA</code>, <code>pSrcB</code>, and <code>pDst</code> have the same
+ * number of rows and columns.
+ */
+
+/**
+ * @addtogroup MatrixSub
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ float32_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ float32_t inA1, inA2, inB1, inB2, out1, out2; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix subtraction */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract and then store the results in the destination buffer. */
+ /* Read values from source A */
+ inA1 = pIn1[0];
+
+ /* Read values from source B */
+ inB1 = pIn2[0];
+
+ /* Read values from source A */
+ inA2 = pIn1[1];
+
+ /* out = sourceA - sourceB */
+ out1 = inA1 - inB1;
+
+ /* Read values from source B */
+ inB2 = pIn2[1];
+
+ /* Read values from source A */
+ inA1 = pIn1[2];
+
+ /* out = sourceA - sourceB */
+ out2 = inA2 - inB2;
+
+ /* Read values from source B */
+ inB1 = pIn2[2];
+
+ /* Store result in destination */
+ pOut[0] = out1;
+ pOut[1] = out2;
+
+ /* Read values from source A */
+ inA2 = pIn1[3];
+
+ /* Read values from source B */
+ inB2 = pIn2[3];
+
+ /* out = sourceA - sourceB */
+ out1 = inA1 - inB1;
+
+
+ /* out = sourceA - sourceB */
+ out2 = inA2 - inB2;
+
+ /* Store result in destination */
+ pOut[2] = out1;
+
+ /* Store result in destination */
+ pOut[3] = out2;
+
+
+ /* update pointers to process next sampels */
+ pIn1 += 4u;
+ pIn2 += 4u;
+ pOut += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract and then store the results in the destination buffer. */
+ *pOut++ = (*pIn1++) - (*pIn2++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixSub group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_q15.c
new file mode 100644
index 000000000..ff7c30432
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_q15.c
@@ -0,0 +1,160 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_sub_q15.c
+*
+* Description: Q15 Matrix subtraction
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixSub
+ * @{
+ */
+
+/**
+ * @brief Q15 matrix subtraction.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ */
+
+arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst)
+{
+ q15_t *pInA = pSrcA->pData; /* input data matrix pointer A */
+ q15_t *pInB = pSrcB->pData; /* input data matrix pointer B */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix subtraction */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Apply loop unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract, Saturate and then store the results in the destination buffer. */
+ *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+ *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract and then store the results in the destination buffer. */
+ *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract and then store the results in the destination buffer. */
+ *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixSub group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_q31.c
new file mode 100644
index 000000000..c2edef1eb
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_sub_q31.c
@@ -0,0 +1,208 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_sub_q31.c
+*
+* Description: Q31 matrix subtraction
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixSub
+ * @{
+ */
+
+/**
+ * @brief Q31 matrix subtraction.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.
+ */
+
+
+arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn1 = pSrcA->pData; /* input data matrix pointer A */
+ q31_t *pIn2 = pSrcB->pData; /* input data matrix pointer B */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t inA1, inB1; /* temporary variables */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t inA2, inB2; /* temporary variables */
+ q31_t out1, out2; /* temporary variables */
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ uint32_t numSamples; /* total number of elements in the matrix */
+ uint32_t blkCnt; /* loop counters */
+ arm_status status; /* status of matrix subtraction */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+ /* Check for matrix mismatch condition */
+ if((pSrcA->numRows != pSrcB->numRows) ||
+ (pSrcA->numCols != pSrcB->numCols) ||
+ (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif
+ {
+ /* Total number of samples in the input matrix */
+ numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Loop Unrolling */
+ blkCnt = numSamples >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract, saturate and then store the results in the destination buffer. */
+ /* Read values from source A */
+ inA1 = pIn1[0];
+
+ /* Read values from source B */
+ inB1 = pIn2[0];
+
+ /* Read values from source A */
+ inA2 = pIn1[1];
+
+ /* Subtract and saturate */
+ out1 = __QSUB(inA1, inB1);
+
+ /* Read values from source B */
+ inB2 = pIn2[1];
+
+ /* Read values from source A */
+ inA1 = pIn1[2];
+
+ /* Subtract and saturate */
+ out2 = __QSUB(inA2, inB2);
+
+ /* Read values from source B */
+ inB1 = pIn2[2];
+
+ /* Store result in destination */
+ pOut[0] = out1;
+ pOut[1] = out2;
+
+ /* Read values from source A */
+ inA2 = pIn1[3];
+
+ /* Read values from source B */
+ inB2 = pIn2[3];
+
+ /* Subtract and saturate */
+ out1 = __QSUB(inA1, inB1);
+
+ /* Subtract and saturate */
+ out2 = __QSUB(inA2, inB2);
+
+ /* Store result in destination */
+ pOut[2] = out1;
+ pOut[3] = out2;
+
+ /* update pointers to process next samples */
+ pIn1 += 4u;
+ pIn2 += 4u;
+ pOut += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the numSamples is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = numSamples % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initialize blkCnt with number of samples */
+ blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C(m,n) = A(m,n) - B(m,n) */
+ /* Subtract, saturate and then store the results in the destination buffer. */
+ inA1 = *pIn1++;
+ inB1 = *pIn2++;
+
+ inA1 = __QSUB(inA1, inB1);
+
+ *pOut++ = inA1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixSub group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_f32.c
new file mode 100644
index 000000000..4cd968ae1
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_f32.c
@@ -0,0 +1,218 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_trans_f32.c
+*
+* Description: Floating-point matrix transpose.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/**
+ * @defgroup MatrixTrans Matrix Transpose
+ *
+ * Tranposes a matrix.
+ * Transposing an <code>M x N</code> matrix flips it around the center diagonal and results in an <code>N x M</code> matrix.
+ * \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix"
+ */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixTrans
+ * @{
+ */
+
+/**
+ * @brief Floating-point matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+
+arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst)
+{
+ float32_t *pIn = pSrc->pData; /* input data matrix pointer */
+ float32_t *pOut = pDst->pData; /* output data matrix pointer */
+ float32_t *px; /* Temporary output data matrix pointer */
+ uint16_t nRows = pSrc->numRows; /* number of rows */
+ uint16_t nColumns = pSrc->numCols; /* number of columns */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ uint16_t blkCnt, i = 0u, row = nRows; /* loop counters */
+ arm_status status; /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* Loop Unrolling */
+ blkCnt = nColumns >> 2;
+
+ /* The pointer px is set to starting address of the column being processed */
+ px = pOut + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u) /* column loop */
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ blkCnt--;
+ }
+
+ /* Perform matrix transpose for last 3 samples here. */
+ blkCnt = nColumns % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ uint16_t col, i = 0u, row = nRows; /* loop counters */
+ arm_status status; /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* The pointer px is set to starting address of the column being processed */
+ px = pOut + i;
+
+ /* Initialize column loop counter */
+ col = nColumns;
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u); /* row loop end */
+
+ /* Set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixTrans group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_q15.c
new file mode 100644
index 000000000..ee4eea605
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_q15.c
@@ -0,0 +1,284 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_trans_q15.c
+*
+* Description: Q15 matrix transpose.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixTrans
+ * @{
+ */
+
+/*
+ * @brief Q15 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst)
+{
+ q15_t *pSrcA = pSrc->pData; /* input data matrix pointer */
+ q15_t *pOut = pDst->pData; /* output data matrix pointer */
+ uint16_t nRows = pSrc->numRows; /* number of nRows */
+ uint16_t nColumns = pSrc->numCols; /* number of nColumns */
+ uint16_t col, row = nRows, i = 0u; /* row and column loop counters */
+ arm_status status; /* status of matrix transpose */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ q31_t in; /* variable to hold temporary output */
+
+#else
+
+ q15_t in;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+
+ /* Apply loop unrolling and exchange the columns with row elements */
+ col = nColumns >> 2u;
+
+ /* The pointer pOut is set to starting address of the column being processed */
+ pOut = pDst->pData + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(col > 0u)
+ {
+#ifndef UNALIGNED_SUPPORT_DISABLE
+
+ /* Read two elements from the row */
+ in = *__SIMD32(pSrcA)++;
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pOut = (q15_t) in;
+
+#else
+
+ *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *pOut = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Read two elements from the row */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ in = *__SIMD32(pSrcA)++;
+
+#else
+
+ in = *__SIMD32(pSrcA)++;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pOut = (q15_t) in;
+
+#else
+
+ *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+ *pOut = (q15_t) in;
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+#else
+ /* Read one element from the row */
+ in = *pSrcA++;
+
+ /* Store one element in the destination */
+ *pOut = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Read one element from the row */
+ in = *pSrcA++;
+
+ /* Store one element in the destination */
+ *pOut = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Read one element from the row */
+ in = *pSrcA++;
+
+ /* Store one element in the destination */
+ *pOut = in;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Read one element from the row */
+ in = *pSrcA++;
+
+ /* Store one element in the destination */
+ *pOut = in;
+
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ /* Perform matrix transpose for last 3 samples here. */
+ col = nColumns % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* The pointer pOut is set to starting address of the column being processed */
+ pOut = pDst->pData + i;
+
+ /* Initialize column loop counter */
+ col = nColumns;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *pOut = *pSrcA++;
+
+ /* Update the pointer pOut to point to the next row of the transposed matrix */
+ pOut += nRows;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ } while(row > 0u);
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixTrans group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_q31.c
new file mode 100644
index 000000000..636eb45eb
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/MatrixFunctions/arm_mat_trans_q31.c
@@ -0,0 +1,210 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mat_trans_q31.c
+*
+* Description: Q31 matrix transpose.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupMatrix
+ */
+
+/**
+ * @addtogroup MatrixTrans
+ * @{
+ */
+
+/*
+ * @brief Q31 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst)
+{
+ q31_t *pIn = pSrc->pData; /* input data matrix pointer */
+ q31_t *pOut = pDst->pData; /* output data matrix pointer */
+ q31_t *px; /* Temporary output data matrix pointer */
+ uint16_t nRows = pSrc->numRows; /* number of nRows */
+ uint16_t nColumns = pSrc->numCols; /* number of nColumns */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ uint16_t blkCnt, i = 0u, row = nRows; /* loop counters */
+ arm_status status; /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* Apply loop unrolling and exchange the columns with row elements */
+ blkCnt = nColumns >> 2u;
+
+ /* The pointer px is set to starting address of the column being processed */
+ px = pOut + i;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ blkCnt--;
+ }
+
+ /* Perform matrix transpose for last 3 samples here. */
+ blkCnt = nColumns % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ uint16_t col, i = 0u, row = nRows; /* loop counters */
+ arm_status status; /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+ /* Check for matrix mismatch condition */
+ if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+ {
+ /* Set status as ARM_MATH_SIZE_MISMATCH */
+ status = ARM_MATH_SIZE_MISMATCH;
+ }
+ else
+#endif /* #ifdef ARM_MATH_MATRIX_CHECK */
+
+ {
+ /* Matrix transpose by exchanging the rows with columns */
+ /* row loop */
+ do
+ {
+ /* The pointer px is set to starting address of the column being processed */
+ px = pOut + i;
+
+ /* Initialize column loop counter */
+ col = nColumns;
+
+ while(col > 0u)
+ {
+ /* Read and store the input element in the destination */
+ *px = *pIn++;
+
+ /* Update the pointer px to point to the next row of the transposed matrix */
+ px += nRows;
+
+ /* Decrement the column loop counter */
+ col--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ i++;
+
+ /* Decrement the row loop counter */
+ row--;
+
+ }
+ while(row > 0u); /* row loop end */
+
+ /* set status as ARM_MATH_SUCCESS */
+ status = ARM_MATH_SUCCESS;
+ }
+
+ /* Return to application */
+ return (status);
+}
+
+/**
+ * @} end of MatrixTrans group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_f32.c
new file mode 100644
index 000000000..eb19ebbc1
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_f32.c
@@ -0,0 +1,186 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_max_f32.c
+*
+* Description: Maximum value of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup Max Maximum
+ *
+ * Computes the maximum value of an array of data.
+ * The function returns both the maximum value and its position within the array.
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 1u;
+ }
+
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 2u;
+ }
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ float32_t maxVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Store the maximum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q15.c
new file mode 100644
index 000000000..e4a90ef44
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q15.c
@@ -0,0 +1,176 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_max_q15.c
+*
+* Description: Maximum value of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q15_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 1u;
+ }
+
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 2u;
+ }
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t maxVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ blkCnt = (blockSize - 1u);
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt;
+ }
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Store the maximum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q31.c
new file mode 100644
index 000000000..d1bb6cad5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q31.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_max_q31.c
+*
+* Description: Maximum value of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 1u;
+ }
+
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 2u;
+ }
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q31_t maxVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Store the maximum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q7.c
new file mode 100644
index 000000000..c9bcc645d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_max_q7.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_max_q7.c
+*
+* Description: Maximum value of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Max
+ * @{
+ */
+
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t maxVal1, maxVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 1u;
+ }
+
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 2u;
+ }
+
+ maxVal2 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the maximum value */
+ if(out < maxVal2)
+ {
+ /* Update the maximum value and its index */
+ out = maxVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q7_t maxVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* Initialize maxVal to the next consecutive values one by one */
+ maxVal1 = *pSrc++;
+
+ /* compare for the maximum value */
+ if(out < maxVal1)
+ {
+ /* Update the maximum value and it's index */
+ out = maxVal1;
+ outIndex = blockSize - blkCnt;
+ }
+ /* Decrement the loop counter */
+ blkCnt--;
+
+ }
+
+ /* Store the maximum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+
+}
+
+/**
+ * @} end of Max group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_f32.c
new file mode 100644
index 000000000..cb36be661
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_f32.c
@@ -0,0 +1,139 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mean_f32.c
+*
+* Description: Mean value of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup mean Mean
+ *
+ * Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;
+ * </pre>
+ *
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+
+/**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult mean value returned here
+ * @return none.
+ */
+
+
+void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ sum += in1;
+ sum += in2;
+ sum += in3;
+ sum += in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store the result to the destination */
+ *pResult = sum / (float32_t) blockSize;
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q15.c
new file mode 100644
index 000000000..e599287bd
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q15.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mean_q15.c
+*
+* Description: Mean value of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+/**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult mean value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * The input is represented in 1.15 format and is accumulated in a 32-bit
+ * accumulator in 17.15 format.
+ * There is no risk of internal overflow with this approach, and the
+ * full precision of intermediate result is preserved.
+ * Finally, the accumulator is saturated and truncated to yield a result of 1.15 format.
+ *
+ */
+
+
+void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ q31_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store the result to the destination */
+ *pResult = (q15_t) (sum / blockSize);
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q31.c
new file mode 100644
index 000000000..5d41bde26
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q31.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mean_q31.c
+*
+* Description: Mean value of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+/**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult mean value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *\par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.31 format and is accumulated in a 64-bit
+ * accumulator in 33.31 format.
+ * There is no risk of internal overflow with this approach, and the
+ * full precision of intermediate result is preserved.
+ * Finally, the accumulator is truncated to yield a result of 1.31 format.
+ *
+ */
+
+
+void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q63_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ sum += in1;
+ sum += in2;
+ sum += in3;
+ sum += in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store the result to the destination */
+ *pResult = (q31_t) (sum / (int32_t) blockSize);
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q7.c
new file mode 100644
index 000000000..b71145fe5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_mean_q7.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_mean_q7.c
+*
+* Description: Mean value of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup mean
+ * @{
+ */
+
+/**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult mean value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * The input is represented in 1.7 format and is accumulated in a 32-bit
+ * accumulator in 25.7 format.
+ * There is no risk of internal overflow with this approach, and the
+ * full precision of intermediate result is preserved.
+ * Finally, the accumulator is truncated to yield a result of 1.7 format.
+ *
+ */
+
+
+void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult)
+{
+ q31_t sum = 0; /* Temporary result storage */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ in = *__SIMD32(pSrc)++;
+
+ sum += ((in << 24) >> 24);
+ sum += ((in << 16) >> 24);
+ sum += ((in << 8) >> 24);
+ sum += (in >> 24);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ sum += *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize */
+ /* Store the result to the destination */
+ *pResult = (q7_t) (sum / (int32_t) blockSize);
+}
+
+/**
+ * @} end of mean group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_f32.c
new file mode 100644
index 000000000..61af82686
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_f32.c
@@ -0,0 +1,183 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_min_f32.c
+*
+* Description: Minimum value of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup Min Minimum
+ *
+ * Computes the minimum value of an array of data.
+ * The function returns both the minimum value and its position within the array.
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult minimum value returned here
+ * @param[out] *pIndex index of minimum value returned here
+ * @return none.
+ *
+ */
+
+void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 1u;
+ }
+
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 2u;
+ }
+
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u ) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ float32_t minVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ blkCnt--;
+
+ }
+
+ /* Store the minimum value and it's index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q15.c
new file mode 100644
index 000000000..a31ca72bf
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q15.c
@@ -0,0 +1,177 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_min_q15.c
+*
+* Description: Minimum value of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult minimum value returned here
+ * @param[out] *pIndex index of minimum value returned here
+ * @return none.
+ *
+ */
+
+void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q15_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 1u;
+ }
+
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 2u;
+ }
+
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u ) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t minVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ blkCnt = (blockSize - 1u);
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ blkCnt--;
+
+ }
+
+
+
+ /* Store the minimum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q31.c
new file mode 100644
index 000000000..fe0a5131c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q31.c
@@ -0,0 +1,176 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_min_q31.c
+*
+* Description: Minimum value of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult minimum value returned here
+ * @param[out] *pIndex index of minimum value returned here
+ * @return none.
+ *
+ */
+
+void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 1u;
+ }
+
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 2u;
+ }
+
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u ) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q31_t minVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ blkCnt = (blockSize - 1u);
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ blkCnt--;
+
+ }
+
+ /* Store the minimum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q7.c
new file mode 100644
index 000000000..335aee702
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_min_q7.c
@@ -0,0 +1,178 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_min_q7.c
+*
+* Description: Minimum value of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup Min
+ * @{
+ */
+
+
+/**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult minimum value returned here
+ * @param[out] *pIndex index of minimum value returned here
+ * @return none.
+ *
+ */
+
+void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q7_t minVal1, minVal2, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex, count; /* loop counter */
+
+ /* Initialise the count value. */
+ count = 0u;
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ /* Loop unrolling */
+ blkCnt = (blockSize - 1u) >> 2u;
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 1u;
+ }
+
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 2u;
+ }
+
+ minVal2 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and its index */
+ out = minVal1;
+ outIndex = count + 3u;
+ }
+
+ /* compare for the minimum value */
+ if(out > minVal2)
+ {
+ /* Update the minimum value and its index */
+ out = minVal2;
+ outIndex = count + 4u;
+ }
+
+ count += 4u;
+
+ blkCnt--;
+ }
+
+ /* if (blockSize - 1u ) is not multiple of 4 */
+ blkCnt = (blockSize - 1u) % 4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q7_t minVal1, out; /* Temporary variables to store the output value. */
+ uint32_t blkCnt, outIndex; /* loop counter */
+
+ /* Initialise the index value to zero. */
+ outIndex = 0u;
+ /* Load first input value that act as reference value for comparision */
+ out = *pSrc++;
+
+ blkCnt = (blockSize - 1u);
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+ while(blkCnt > 0)
+ {
+ /* Initialize minVal to the next consecutive values one by one */
+ minVal1 = *pSrc++;
+
+ /* compare for the minimum value */
+ if(out > minVal1)
+ {
+ /* Update the minimum value and it's index */
+ out = minVal1;
+ outIndex = blockSize - blkCnt;
+ }
+
+ blkCnt--;
+
+ }
+
+ /* Store the minimum value and its index into destination pointers */
+ *pResult = out;
+ *pIndex = outIndex;
+
+
+}
+
+/**
+ * @} end of Min group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_f32.c
new file mode 100644
index 000000000..464265e16
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_f32.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_power_f32.c
+*
+* Description: Sum of the squares of the elements of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup power Power
+ *
+ * Calculates the sum of the squares of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];
+ * </pre>
+ *
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+
+/**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult sum of the squares value returned here
+ * @return none.
+ *
+ */
+
+
+void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* accumulator */
+ float32_t in; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* compute power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Store the result to the destination */
+ *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q15.c
new file mode 100644
index 000000000..9005e3d97
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q15.c
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_power_q15.c
+*
+* Description: Sum of the squares of the elements of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+/**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult sum of the squares value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the return result is in 34.30 format.
+ *
+ */
+
+void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult)
+{
+ q63_t sum = 0; /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in32; /* Temporary variable to store input value */
+ q15_t in16; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in32 = *__SIMD32(pSrc)++;
+ sum = __SMLALD(in32, in32, sum);
+ in32 = *__SIMD32(pSrc)++;
+ sum = __SMLALD(in32, in32, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in16 = *pSrc++;
+ sum = __SMLALD(in16, in16, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t in; /* Temporary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Store the results in 34.30 format */
+ *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q31.c
new file mode 100644
index 000000000..344a3a369
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q31.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_power_q31.c
+*
+* Description: Sum of the squares of the elements of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+/**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult sum of the squares value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.31 format.
+ * Intermediate multiplication yields a 2.62 format, and this
+ * result is truncated to 2.48 format by discarding the lower 14 bits.
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.
+ * With 15 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the return result is in 16.48 format.
+ *
+ */
+
+void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult)
+{
+ q63_t sum = 0; /* Temporary result storage */
+ q31_t in;
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += ((q63_t) in * in) >> 14u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Store the results in 16.48 format */
+ *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q7.c
new file mode 100644
index 000000000..872e36b4c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_power_q7.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_power_q7.c
+*
+* Description: Sum of the squares of the elements of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup power
+ * @{
+ */
+
+/**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult sum of the squares value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 32-bit internal accumulator.
+ * The input is represented in 1.7 format.
+ * Intermediate multiplication yields a 2.14 format, and this
+ * result is added without saturation to an accumulator in 18.14 format.
+ * With 17 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the return result is in 18.14 format.
+ *
+ */
+
+void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q31_t sum = 0; /* Temporary result storage */
+ q7_t in; /* Temporary variable to store input */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t input1; /* Temporary variable to store packed input */
+ q31_t in1, in2; /* Temporary variables to store input */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* Reading two inputs of pSrc vector and packing */
+ input1 = *__SIMD32(pSrc)++;
+
+ in1 = __SXTB16(__ROR(input1, 8));
+ in2 = __SXTB16(input1);
+
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* calculate power and accumulate to accumulator */
+ sum = __SMLAD(in1, in1, sum);
+ sum = __SMLAD(in2, in2, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute Power and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += ((q15_t) in * in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Store the result in 18.14 format */
+ *pResult = sum;
+}
+
+/**
+ * @} end of power group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_f32.c
new file mode 100644
index 000000000..b3f67db03
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_f32.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rms_f32.c
+*
+* Description: Root mean square value of an array of F32 type
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup RMS Root mean square (RMS)
+ *
+ *
+ * Calculates the Root Mean Sqaure of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));
+ * </pre>
+ *
+ * There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ * @addtogroup RMS
+ * @{
+ */
+
+
+/**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult rms value returned here
+ * @return none.
+ *
+ */
+
+void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* Accumulator */
+ float32_t in; /* Tempoprary variable to store input value */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute sum of the squares and then store the result in a temporary variable, sum */
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in = *pSrc++;
+ sum += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Rms and store the result in the destination */
+ arm_sqrt_f32(sum / (float32_t) blockSize, pResult);
+}
+
+/**
+ * @} end of RMS group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_q15.c
new file mode 100644
index 000000000..5de2f2a8a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_q15.c
@@ -0,0 +1,162 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rms_q15.c
+*
+* Description: Root Mean Square of the elements of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup RMS
+ * @{
+ */
+
+/**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult rms value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ * 15 bits, and then saturated to yield a result in 1.15 format.
+ *
+ */
+
+void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ q63_t sum = 0; /* accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in; /* temporary variable to store the input value */
+ q15_t in1; /* temporary variable to store the input value */
+ uint32_t blkCnt; /* loop counter */
+
+ /* loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in = *__SIMD32(pSrc)++;
+ sum = __SMLALD(in, in, sum);
+ in = *__SIMD32(pSrc)++;
+ sum = __SMLALD(in, in, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in1 = *pSrc++;
+ sum = __SMLALD(in1, in1, sum);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Truncating and saturating the accumulator to 1.15 format */
+ in = (q31_t)(sum >> 15);
+
+ in1 = __SSAT(in / blockSize, 16);
+
+ /* Store the result in the destination */
+ arm_sqrt_q15(in1, pResult);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t in; /* temporary variable to store the input value */
+ q31_t tmp; /* temporary variable to store the input value */
+ uint32_t blkCnt; /* loop counter */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in = *pSrc++;
+ sum += ((q31_t) in * in);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Truncating and saturating the accumulator to 1.15 format */
+ tmp = (q31_t)(sum >> 15);
+
+ in = __SSAT(tmp / blockSize, 16);
+
+ /* Store the result in the destination */
+ arm_sqrt_q15(in, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of RMS group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_q31.c
new file mode 100644
index 000000000..0a8bf1f73
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_rms_q31.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rms_q31.c
+*
+* Description: Root Mean Square of the elements of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup RMS
+ * @{
+ */
+
+
+/**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult rms value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ *\par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The input is represented in 1.31 format, and intermediate multiplication
+ * yields a 2.62 format.
+ * The accumulator maintains full precision of the intermediate multiplication results,
+ * but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * If the accumulator overflows, it wraps around and distorts the result.
+ * In order to avoid overflows completely, the input signal must be scaled down by
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.
+ *
+ */
+
+void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q63_t sum = 0; /* accumulator */
+ q31_t in; /* Temporary variable to store the input */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in1, in2, in3, in4; /* Temporary input variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 8 outputs at a time.
+ ** a second loop below computes the remaining 1 to 7 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute sum of the squares and then store the result in a temporary variable, sum */
+ /* read two samples from source buffer */
+ in1 = pSrc[0];
+ in2 = pSrc[1];
+
+ /* calculate power and accumulate to accumulator */
+ sum += (q63_t) in1 *in1;
+ sum += (q63_t) in2 *in2;
+
+ /* read two samples from source buffer */
+ in3 = pSrc[2];
+ in4 = pSrc[3];
+
+ /* calculate power and accumulate to accumulator */
+ sum += (q63_t) in3 *in3;
+ sum += (q63_t) in4 *in4;
+
+
+ /* update source buffer to process next samples */
+ pSrc += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 8, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+ /* Compute sum of the squares and then store the results in a temporary variable, sum */
+ in = *pSrc++;
+ sum += (q63_t) in *in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Convert data in 2.62 to 1.31 by 31 right shifts and saturate */
+
+ sum = __SSAT(sum >> 31, 31);
+
+
+ /* Compute Rms and store the result in the destination vector */
+ arm_sqrt_q31((q31_t) ((q31_t) sum / (int32_t) blockSize), pResult);
+}
+
+/**
+ * @} end of RMS group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_f32.c
new file mode 100644
index 000000000..135eb74d6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_f32.c
@@ -0,0 +1,196 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_std_f32.c
+*
+* Description: Standard deviation of the elements of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup STD Standard deviation
+ *
+ * Calculates the standard deviation of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * Result = sqrt((sumOfSquares - sum<sup>2</sup> / blockSize) / (blockSize - 1))
+ *
+ * where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
+ *
+ * sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]
+ * </pre>
+ *
+ * There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ * @addtogroup STD
+ * @{
+ */
+
+
+/**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult standard deviation value returned here
+ * @return none.
+ *
+ */
+
+
+void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+ float32_t sum = 0.0f; /* Temporary result storage */
+ float32_t sumOfSquares = 0.0f; /* Sum of squares */
+ float32_t in; /* input value */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t meanOfSquares, mean, squareOfMean;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
+
+ /* Compute mean of all input values */
+ mean = sum / (float32_t) blockSize;
+
+ /* Compute square of mean */
+ squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+ ((float32_t) blockSize - 1.0f));
+
+ /* Compute standard deviation and then store the result to the destination */
+ arm_sqrt_f32((meanOfSquares - squareOfMean), pResult);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ float32_t squareOfSum; /* Square of Sum */
+ float32_t var; /* Temporary varaince storage */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++;
+ sumOfSquares += in * in;
+
+ /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+ /* Compute Sum of the input samples
+ * and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute the square of sum */
+ squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+ /* Compute the variance */
+ var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+ /* Compute standard deviation and then store the result to the destination */
+ arm_sqrt_f32(var, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of STD group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_q15.c
new file mode 100644
index 000000000..b6c2d13d2
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_q15.c
@@ -0,0 +1,205 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_std_q15.c
+*
+* Description: Standard deviation of an array of Q15 type.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup STD
+ * @{
+ */
+
+/**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult standard deviation value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ * 15 bits, and then saturated to yield a result in 1.15 format.
+ */
+
+void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult)
+{
+ q31_t sum = 0; /* Accumulator */
+ q31_t meanOfSquares, squareOfMean; /* square of mean and mean of square */
+ q15_t mean; /* mean */
+ uint32_t blkCnt; /* loop counter */
+ q15_t t; /* Temporary variable */
+ q63_t sumOfSquares = 0; /* Accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in; /* input value */
+ q15_t in1; /* input value */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ sumOfSquares = __SMLALD(in, in, sumOfSquares);
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ sumOfSquares = __SMLALD(in, in, sumOfSquares);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in1 = *pSrc++;
+ sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
+ sum += in1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);
+ sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+
+ meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+ /* Compute mean of all input values */
+ t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);
+ mean = (q15_t) __SSAT(sum, 16u);
+
+ /* Compute square of mean */
+ squareOfMean = ((q31_t) mean * mean) >> 15;
+ squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+ /* mean of the squares minus the square of the mean. */
+ in1 = (q15_t) (meanOfSquares - squareOfMean);
+
+ /* Compute standard deviation and store the result to the destination */
+ arm_sqrt_q15(in1, pResult);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ q15_t in; /* input value */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++;
+ sumOfSquares += (in * in);
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);
+ sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+ meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+ /* Compute mean of all input values */
+ mean = (q15_t) __SSAT(sum, 16u);
+
+ /* Compute square of mean of the input samples
+ * and then store the result in a temporary variable, squareOfMean.*/
+ t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);
+ squareOfMean = ((q31_t) mean * mean) >> 15;
+ squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+ /* mean of the squares minus the square of the mean. */
+ in = (q15_t) (meanOfSquares - squareOfMean);
+
+ /* Compute standard deviation and store the result to the destination */
+ arm_sqrt_q15(in, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+}
+
+/**
+ * @} end of STD group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_q31.c
new file mode 100644
index 000000000..ae830e772
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_std_q31.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_std_q31.c
+*
+* Description: Standard deviation of an array of Q31 type.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup STD
+ * @{
+ */
+
+
+/**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult standard deviation value returned here
+ * @return none.
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ *\par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The input is represented in 1.31 format, and intermediate multiplication
+ * yields a 2.62 format.
+ * The accumulator maintains full precision of the intermediate multiplication results,
+ * but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * If the accumulator overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.
+ *
+ */
+
+
+void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q63_t sum = 0; /* Accumulator */
+ q31_t meanOfSquares, squareOfMean; /* square of mean and mean of square */
+ q31_t mean; /* mean */
+ q31_t in; /* input value */
+ q31_t t; /* Temporary variable */
+ uint32_t blkCnt; /* loop counter */
+ q63_t sumOfSquares = 0; /* Accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += ((q63_t) (in) * (in));
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ sumOfSquares = (sumOfSquares >> 31);
+ meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++;
+ sumOfSquares += ((q63_t) (in) * (in));
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+ sumOfSquares = (sumOfSquares >> 31);
+ meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Compute mean of all input values */
+ t = (q31_t) ((1.0f / (blockSize * (blockSize - 1u))) * 2147483648.0f);
+ mean = (q31_t) (sum);
+
+ /* Compute square of mean */
+ squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);
+ squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);
+
+
+ /* Compute standard deviation and then store the result to the destination */
+ arm_sqrt_q31(meanOfSquares - squareOfMean, pResult);
+
+}
+
+/**
+ * @} end of STD group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_f32.c
new file mode 100644
index 000000000..e3e46ff01
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_f32.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_var_f32.c
+*
+* Description: Variance of the elements of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @defgroup variance Variance
+ *
+ * Calculates the variance of the elements in the input vector.
+ * The underlying algorithm is used:
+ *
+ * <pre>
+ * Result = (sumOfSquares - sum<sup>2</sup> / blockSize) / (blockSize - 1)
+ *
+ * where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]
+ *
+ * sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]
+ * </pre>
+ *
+ * There are separate functions for floating point, Q31, and Q15 data types.
+ */
+
+/**
+ * @addtogroup variance
+ * @{
+ */
+
+
+/**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult variance value returned here
+ * @return none.
+ *
+ */
+
+
+void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult)
+{
+
+ float32_t sum = 0.0f; /* Temporary result storage */
+ float32_t sumOfSquares = 0.0f; /* Sum of squares */
+ float32_t in; /* input value */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t meanOfSquares, mean, squareOfMean; /* Temporary variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sum += in;
+ sumOfSquares += in * in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ meanOfSquares = sumOfSquares / ((float32_t) blockSize - 1.0f);
+
+ /* Compute mean of all input values */
+ mean = sum / (float32_t) blockSize;
+
+ /* Compute square of mean */
+ squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+ ((float32_t) blockSize - 1.0f));
+
+ /* Compute variance and then store the result to the destination */
+ *pResult = meanOfSquares - squareOfMean;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ float32_t squareOfSum; /* Square of Sum */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++;
+ sumOfSquares += in * in;
+
+ /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+ /* Compute Sum of the input samples
+ * and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute the square of sum */
+ squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+ /* Compute the variance */
+ *pResult = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of variance group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_q15.c
new file mode 100644
index 000000000..695f08e50
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_q15.c
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_var_q15.c
+*
+* Description: Variance of an array of Q15 type.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup variance
+ * @{
+ */
+
+/**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult variance value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * The input is represented in 1.15 format.
+ * Intermediate multiplication yields a 2.30 format, and this
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the
+ * full precision of the intermediate multiplication is preserved.
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower
+ * 15 bits, and then saturated to yield a result in 1.15 format.
+ *
+ */
+
+
+void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult)
+{
+ q31_t sum = 0; /* Accumulator */
+ q31_t meanOfSquares, squareOfMean; /* Mean of square and square of mean */
+ q15_t mean; /* mean */
+ uint32_t blkCnt; /* loop counter */
+ q15_t t; /* Temporary variable */
+ q63_t sumOfSquares = 0; /* Accumulator */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t in; /* Input variable */
+ q15_t in1; /* Temporary variable */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ sumOfSquares = __SMLALD(in, in, sumOfSquares);
+ in = *__SIMD32(pSrc)++;
+ sum += ((in << 16) >> 16);
+ sum += (in >> 16);
+ sumOfSquares = __SMLALD(in, in, sumOfSquares);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in1 = *pSrc++;
+ sum += in1;
+ sumOfSquares = __SMLALD(in1, in1, sumOfSquares);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);
+ sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+
+ meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t in; /* Temporary variable */
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sumOfSquares. */
+ in = *pSrc++;
+ sumOfSquares += (in * in);
+
+ /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+ /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);
+ sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+ meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ /* Compute mean of all input values */
+ t = (q15_t) ((1.0f / (float32_t) (blockSize * (blockSize - 1u))) * 32768);
+ mean = __SSAT(sum, 16u);
+
+ /* Compute square of mean */
+ squareOfMean = ((q31_t) mean * mean) >> 15;
+ squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+ /* Compute variance and then store the result to the destination */
+ *pResult = (meanOfSquares - squareOfMean);
+
+}
+
+/**
+ * @} end of variance group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_q31.c
new file mode 100644
index 000000000..3d6492ab0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/StatisticsFunctions/arm_var_q31.c
@@ -0,0 +1,178 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_var_q31.c
+*
+* Description: Variance of an array of Q31 type.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupStats
+ */
+
+/**
+ * @addtogroup variance
+ * @{
+ */
+
+/**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult variance value returned here
+ * @return none.
+ *
+ * @details
+ * <b>Scaling and Overflow Behavior:</b>
+ *
+ *\par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The input is represented in 1.31 format, and intermediate multiplication
+ * yields a 2.62 format.
+ * The accumulator maintains full precision of the intermediate multiplication results,
+ * but provides only a single guard bit.
+ * There is no saturation on intermediate additions.
+ * If the accumulator overflows it wraps around and distorts the result.
+ * In order to avoid overflows completely the input signal must be scaled down by
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.
+ *
+ */
+
+
+void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult)
+{
+ q63_t sum = 0, sumSquare = 0; /* Accumulator */
+ q31_t meanOfSquares, squareOfMean; /* square of mean and mean of square */
+ q31_t mean; /* mean */
+ q31_t in; /* input value */
+ q31_t t; /* Temporary variable */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q63_t sumSquare1 = 0; /* Accumulator */
+ q31_t in1, in2, in3, in4; /* Temporary input variables */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ /* read input samples from source buffer */
+ in1 = pSrc[0];
+ in2 = pSrc[1];
+
+ /* calculate sum of inputs */
+ sum += in1;
+ /* calculate sum of squares */
+ sumSquare += ((q63_t) (in1) * (in1));
+ in3 = pSrc[2];
+ sum += in2;
+ sumSquare1 += ((q63_t) (in2) * (in2));
+ in4 = pSrc[3];
+ sum += in3;
+ sumSquare += ((q63_t) (in3) * (in3));
+ sum += in4;
+ sumSquare1 += ((q63_t) (in4) * (in4));
+
+ /* update input pointer to process next samples */
+ pSrc += 4u;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* add two accumulators */
+ sumSquare = sumSquare + sumSquare1;
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+ /* Compute Sum of squares of the input samples
+ * and then store the result in a temporary variable, sum. */
+ in = *pSrc++;
+ sumSquare += ((q63_t) (in) * (in));
+ sum += in;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+
+ /* Compute Mean of squares of the input samples
+ * and then store the result in a temporary variable, meanOfSquares. */
+ sumSquare = (sumSquare >> 31);
+ meanOfSquares = (q31_t) ((sumSquare * t) >> 30);
+
+ /* Compute mean of all input values */
+ t = (q31_t) ((1.0f / (blockSize * (blockSize - 1u))) * 2147483648.0f);
+ mean = (q31_t) (sum);
+
+ /* Compute square of mean */
+ squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);
+ squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);
+
+ /* Compute variance and then store the result to the destination */
+ *pResult = (q63_t) meanOfSquares - squareOfMean;
+
+}
+
+/**
+ * @} end of variance group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_f32.c
new file mode 100644
index 000000000..f50cb532f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_f32.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_copy_f32.c
+*
+* Description: Copies the elements of a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup copy Vector Copy
+ *
+ * Copies sample by sample from source vector to destination vector.
+ *
+ * <pre>
+ * pDst[n] = pSrc[n]; 0 <= n < blockSize.
+ * </pre>
+ *
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+
+/**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] *pSrc points to input vector
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+
+void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the results in the destination buffer */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = in1;
+ *pDst++ = in2;
+ *pDst++ = in3;
+ *pDst++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the results in the destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q15.c
new file mode 100644
index 000000000..b60e68ac1
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q15.c
@@ -0,0 +1,114 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_copy_q15.c
+*
+* Description: Copies the elements of a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+/**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] *pSrc points to input vector
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Read two inputs */
+ *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+ *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the value in the destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q31.c
new file mode 100644
index 000000000..3654d3d30
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q31.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_copy_q31.c
+*
+* Description: Copies the elements of a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+
+/**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] *pSrc points to input vector
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the values in the destination buffer */
+ in1 = *pSrc++;
+ in2 = *pSrc++;
+ in3 = *pSrc++;
+ in4 = *pSrc++;
+
+ *pDst++ = in1;
+ *pDst++ = in2;
+ *pDst++ = in3;
+ *pDst++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the value in the destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q7.c
new file mode 100644
index 000000000..303286fe5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_copy_q7.c
@@ -0,0 +1,115 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_copy_q7.c
+*
+* Description: Copies the elements of a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup copy
+ * @{
+ */
+
+/**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] *pSrc points to input vector
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ */
+
+void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the results in the destination buffer */
+ /* 4 samples are copied and stored at a time using SIMD */
+ *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = A */
+ /* Copy and then store the results in the destination buffer */
+ *pDst++ = *pSrc++;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of BasicCopy group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_f32.c
new file mode 100644
index 000000000..3f5f86e0e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_f32.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fill_f32.c
+*
+* Description: Fills a constant value into a floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup Fill Vector Fill
+ *
+ * Fills the destination vector with a constant value.
+ *
+ * <pre>
+ * pDst[n] = value; 0 <= n < blockSize.
+ * </pre>
+ *
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+
+void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ float32_t in1 = value;
+ float32_t in2 = value;
+ float32_t in3 = value;
+ float32_t in4 = value;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = in1;
+ *pDst++ = in2;
+ *pDst++ = in3;
+ *pDst++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = value;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q15.c
new file mode 100644
index 000000000..5c73cf627
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q15.c
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fill_q15.c
+*
+* Description: Fills a constant value into a Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t packedValue; /* value packed to 32 bits */
+
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Packing two 16 bit values to 32 bit value in order to use SIMD */
+ packedValue = __PKHBT(value, value, 16u);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *__SIMD32(pDst)++ = packedValue;
+ *__SIMD32(pDst)++ = packedValue;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = value;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q31.c
new file mode 100644
index 000000000..2e8c133ae
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q31.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fill_q31.c
+*
+* Description: Fills a constant value into a Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1 = value;
+ q31_t in2 = value;
+ q31_t in3 = value;
+ q31_t in4 = value;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = in1;
+ *pDst++ = in2;
+ *pDst++ = in3;
+ *pDst++ = in4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = value;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q7.c
new file mode 100644
index 000000000..376b7a588
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_fill_q7.c
@@ -0,0 +1,118 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_fill_q7.c
+*
+* Description: Fills a constant value into a Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup Fill
+ * @{
+ */
+
+/**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst points to output vector
+ * @param[in] blockSize length of the output vector
+ * @return none.
+ *
+ */
+
+void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t packedValue; /* value packed to 32 bits */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* Packing four 8 bit values to 32 bit value in order to use SIMD */
+ packedValue = __PACKq7(value, value, value, value);
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *__SIMD32(pDst)++ = packedValue;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = value */
+ /* Fill the value in the destination buffer */
+ *pDst++ = value;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of Fill group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q15.c
new file mode 100644
index 000000000..cfa5ec651
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q15.c
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_float_to_q15.c
+*
+* Description: Converts the elements of the floating-point vector to Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup float_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ * \par
+ * The equation used for the conversion process is:
+ * <pre>
+ * pDst[n] = (q15_t)(pSrc[n] * 32768); 0 <= n < blockSize.
+ * </pre>
+ * \par Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.
+ * \note
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ * defined in the preprocessor section of project options.
+ *
+ */
+
+
+void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+ float32_t in;
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 32768.0f);
+ in += in > 0 ? 0.5f : -0.5f;
+ *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+ /* C = A * 32768 */
+ /* convert from float to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of float_to_x group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q31.c
new file mode 100644
index 000000000..a39fbe7e3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q31.c
@@ -0,0 +1,211 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_float_to_q31.c
+*
+* Description: Converts the elements of the floating-point vector to Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup float_to_x Convert 32-bit floating point value
+ */
+
+/**
+ * @addtogroup float_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ *\par Description:
+ * \par
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (q31_t)(pSrc[n] * 2147483648); 0 <= n < blockSize.
+ * </pre>
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.
+ *
+ * \note In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ * defined in the preprocessor section of project options.
+ */
+
+
+void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+ float32_t in;
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+
+ /* C = A * 32768 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 2147483648.0f);
+ in += in > 0 ? 0.5f : -0.5f;
+ *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+ /* C = A * 2147483648 */
+ /* convert from float to Q31 and then store the results in the destination buffer */
+ *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of float_to_x group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q7.c
new file mode 100644
index 000000000..2820af7e6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_float_to_q7.c
@@ -0,0 +1,203 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_float_to_q7.c
+*
+* Description: Converts the elements of the floating-point vector to Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup float_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ *\par Description:
+ * \par
+ * The equation used for the conversion process is:
+ * <pre>
+ * pDst[n] = (q7_t)(pSrc[n] * 128); 0 <= n < blockSize.
+ * </pre>
+ * \par Scaling and Overflow Behavior:
+ * \par
+ * The function uses saturating arithmetic.
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.
+ * \note
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro
+ * defined in the preprocessor section of project options.
+ */
+
+
+void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ float32_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+ float32_t in;
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+ while(blkCnt > 0u)
+ {
+
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 128);
+ in += in > 0 ? 0.5 : -0.5;
+ *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+ while(blkCnt > 0u)
+ {
+#ifdef ARM_MATH_ROUNDING
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ in = *pIn++;
+ in = (in * 128.0f);
+ in += in > 0 ? 0.5f : -0.5f;
+ *pDst++ = (q7_t) (__SSAT((q31_t) (in), 8));
+
+#else
+
+ /* C = A * 128 */
+ /* convert from float to q7 and then store the results in the destination buffer */
+ *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /* #ifdef ARM_MATH_ROUNDING */
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of float_to_x group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_float.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_float.c
new file mode 100644
index 000000000..2310b909d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_float.c
@@ -0,0 +1,134 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q15_to_float.c
+*
+* Description: Converts the elements of the Q15 vector to floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q15_to_x Convert 16-bit Integer value
+ */
+
+/**
+ * @addtogroup q15_to_x
+ * @{
+ */
+
+
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] *pSrc points to the Q15 input vector
+ * @param[out] *pDst points to the floating-point output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (float32_t) pSrc[n] / 32768; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 32768 */
+ /* convert from q15 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 32768 */
+ /* convert from q15 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of q15_to_x group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_q31.c
new file mode 100644
index 000000000..2d5c86e22
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_q31.c
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q15_to_q31.c
+*
+* Description: Converts the elements of the Q15 vector to Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q15_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] *pSrc points to the Q15 input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (q31_t) pSrc[n] << 16; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2;
+ q31_t out1, out2, out3, out4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q31_t)A << 16 */
+ /* convert from q15 to q31 and then store the results in the destination buffer */
+ in1 = *__SIMD32(pIn)++;
+ in2 = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* extract lower 16 bits to 32 bit result */
+ out1 = in1 << 16u;
+ /* extract upper 16 bits to 32 bit result */
+ out2 = in1 & 0xFFFF0000;
+ /* extract lower 16 bits to 32 bit result */
+ out3 = in2 << 16u;
+ /* extract upper 16 bits to 32 bit result */
+ out4 = in2 & 0xFFFF0000;
+
+#else
+
+ /* extract upper 16 bits to 32 bit result */
+ out1 = in1 & 0xFFFF0000;
+ /* extract lower 16 bits to 32 bit result */
+ out2 = in1 << 16u;
+ /* extract upper 16 bits to 32 bit result */
+ out3 = in2 & 0xFFFF0000;
+ /* extract lower 16 bits to 32 bit result */
+ out4 = in2 << 16u;
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ *pDst++ = out1;
+ *pDst++ = out2;
+ *pDst++ = out3;
+ *pDst++ = out4;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q31_t)A << 16 */
+ /* convert from q15 to q31 and then store the results in the destination buffer */
+ *pDst++ = (q31_t) * pIn++ << 16;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q15_to_x group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_q7.c
new file mode 100644
index 000000000..d26122150
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q15_to_q7.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q15_to_q7.c
+*
+* Description: Converts the elements of the Q15 vector to Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q15_to_x
+ * @{
+ */
+
+
+/**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] *pSrc points to the Q15 input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (q7_t) pSrc[n] >> 8; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ q15_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2;
+ q31_t out1, out2;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q7_t) A >> 8 */
+ /* convert from q15 to q7 and then store the results in the destination buffer */
+ in1 = *__SIMD32(pIn)++;
+ in2 = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __PKHTB(in2, in1, 16);
+ out2 = __PKHBT(in2, in1, 16);
+
+#else
+
+ out1 = __PKHTB(in1, in2, 16);
+ out2 = __PKHBT(in1, in2, 16);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ /* rotate packed value by 24 */
+ out2 = ((uint32_t) out2 << 8) | ((uint32_t) out2 >> 24);
+
+ /* anding with 0xff00ff00 to get two 8 bit values */
+ out1 = out1 & 0xFF00FF00;
+ /* anding with 0x00ff00ff to get two 8 bit values */
+ out2 = out2 & 0x00FF00FF;
+
+ /* oring two values(contains two 8 bit values) to get four packed 8 bit values */
+ out1 = out1 | out2;
+
+ /* store 4 samples at a time to destiantion buffer */
+ *__SIMD32(pDst)++ = out1;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q7_t) A >> 8 */
+ /* convert from q15 to q7 and then store the results in the destination buffer */
+ *pDst++ = (q7_t) (*pIn++ >> 8);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q15_to_x group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_float.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_float.c
new file mode 100644
index 000000000..4f60511c2
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_float.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q31_to_float.c
+*
+* Description: Converts the elements of the Q31 vector to floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q31_to_x Convert 32-bit Integer value
+ */
+
+/**
+ * @addtogroup q31_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] *pSrc points to the Q31 input vector
+ * @param[out] *pDst points to the floating-point output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (float32_t) pSrc[n] / 2147483648; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 2147483648 */
+ /* convert from q31 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 2147483648 */
+ /* convert from q31 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of q31_to_x group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_q15.c
new file mode 100644
index 000000000..a2b9fde74
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_q15.c
@@ -0,0 +1,145 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q31_to_q15.c
+*
+* Description: Converts the elements of the Q31 vector to Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q31_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] *pSrc points to the Q31 input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (q15_t) pSrc[n] >> 16; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+ q31_t out1, out2;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q15_t) A >> 16 */
+ /* convert from q31 to q15 and then store the results in the destination buffer */
+ in1 = *pIn++;
+ in2 = *pIn++;
+ in3 = *pIn++;
+ in4 = *pIn++;
+
+ /* pack two higher 16-bit values from two 32-bit values */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __PKHTB(in2, in1, 16);
+ out2 = __PKHTB(in4, in3, 16);
+
+#else
+
+ out1 = __PKHTB(in1, in2, 16);
+ out2 = __PKHTB(in3, in4, 16);
+
+#endif // #ifdef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst)++ = out1;
+ *__SIMD32(pDst)++ = out2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q15_t) A >> 16 */
+ /* convert from q31 to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) (*pIn++ >> 16);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q31_to_x group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_q7.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_q7.c
new file mode 100644
index 000000000..c2f9b9a04
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q31_to_q7.c
@@ -0,0 +1,136 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q31_to_q7.c
+*
+* Description: Converts the elements of the Q31 vector to Q7 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q31_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] *pSrc points to the Q31 input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (q7_t) pSrc[n] >> 24; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize)
+{
+ q31_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+ q31_t in1, in2, in3, in4;
+ q7_t out1, out2, out3, out4;
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q7_t) A >> 24 */
+ /* convert from q31 to q7 and then store the results in the destination buffer */
+ in1 = *pIn++;
+ in2 = *pIn++;
+ in3 = *pIn++;
+ in4 = *pIn++;
+
+ out1 = (q7_t) (in1 >> 24);
+ out2 = (q7_t) (in2 >> 24);
+ out3 = (q7_t) (in3 >> 24);
+ out4 = (q7_t) (in4 >> 24);
+
+ *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q7_t) A >> 24 */
+ /* convert from q31 to q7 and then store the results in the destination buffer */
+ *pDst++ = (q7_t) (*pIn++ >> 24);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q31_to_x group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_float.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_float.c
new file mode 100644
index 000000000..3b7f586a5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_float.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q7_to_float.c
+*
+* Description: Converts the elements of the Q7 vector to floating-point vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @defgroup q7_to_x Convert 8-bit Integer value
+ */
+
+/**
+ * @addtogroup q7_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] *pSrc points to the Q7 input vector
+ * @param[out] *pDst points to the floating-point output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (float32_t) pSrc[n] / 128; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize)
+{
+ q7_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 128 */
+ /* convert from q7 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (float32_t) A / 128 */
+ /* convert from q7 to float and then store the results in the destination buffer */
+ *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+}
+
+/**
+ * @} end of q7_to_x group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_q15.c
new file mode 100644
index 000000000..444321c60
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_q15.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q7_to_q15.c
+*
+* Description: Converts the elements of the Q7 vector to Q15 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q7_to_x
+ * @{
+ */
+
+
+
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] *pSrc points to the Q7 input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (q15_t) pSrc[n] << 8; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize)
+{
+ q7_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+ q31_t in;
+ q31_t in1, in2;
+ q31_t out1, out2;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q15_t) A << 8 */
+ /* convert from q7 to q15 and then store the results in the destination buffer */
+ in = *__SIMD32(pIn)++;
+
+ /* rotatate in by 8 and extend two q7_t values to q15_t values */
+ in1 = __SXTB16(__ROR(in, 8));
+
+ /* extend remainig two q7_t values to q15_t values */
+ in2 = __SXTB16(in);
+
+ in1 = in1 << 8u;
+ in2 = in2 << 8u;
+
+ in1 = in1 & 0xFF00FF00;
+ in2 = in2 & 0xFF00FF00;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out2 = __PKHTB(in1, in2, 16);
+ out1 = __PKHBT(in2, in1, 16);
+
+#else
+
+ out1 = __PKHTB(in1, in2, 16);
+ out2 = __PKHBT(in2, in1, 16);
+
+#endif
+
+ *__SIMD32(pDst)++ = out1;
+ *__SIMD32(pDst)++ = out2;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q15_t) A << 8 */
+ /* convert from q7 to q15 and then store the results in the destination buffer */
+ *pDst++ = (q15_t) * pIn++ << 8;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q7_to_x group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_q31.c
new file mode 100644
index 000000000..fefd78a01
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/arm_q7_to_q31.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_q7_to_q31.c
+*
+* Description: Converts the elements of the Q7 vector to Q31 vector.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupSupport
+ */
+
+/**
+ * @addtogroup q7_to_x
+ * @{
+ */
+
+/**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] *pSrc points to the Q7 input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ *
+ * \par Description:
+ *
+ * The equation used for the conversion process is:
+ *
+ * <pre>
+ * pDst[n] = (q31_t) pSrc[n] << 24; 0 <= n < blockSize.
+ * </pre>
+ *
+ */
+
+
+void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize)
+{
+ q7_t *pIn = pSrc; /* Src pointer */
+ uint32_t blkCnt; /* loop counter */
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ q31_t in;
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /*loop Unrolling */
+ blkCnt = blockSize >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ while(blkCnt > 0u)
+ {
+ /* C = (q31_t) A << 24 */
+ /* convert from q7 to q31 and then store the results in the destination buffer */
+ in = *__SIMD32(pIn)++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *pDst++ = (__ROR(in, 8)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 16)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 24)) & 0xFF000000;
+ *pDst++ = (in & 0xFF000000);
+
+#else
+
+ *pDst++ = (in & 0xFF000000);
+ *pDst++ = (__ROR(in, 24)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 16)) & 0xFF000000;
+ *pDst++ = (__ROR(in, 8)) & 0xFF000000;
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ blkCnt = blockSize % 0x4u;
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Loop over blockSize number of values */
+ blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+ while(blkCnt > 0u)
+ {
+ /* C = (q31_t) A << 24 */
+ /* convert from q7 to q31 and then store the results in the destination buffer */
+ *pDst++ = (q31_t) * pIn++ << 24;
+
+ /* Decrement the loop counter */
+ blkCnt--;
+ }
+
+}
+
+/**
+ * @} end of q7_to_x group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/math_helper.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/math_helper.c
new file mode 100644
index 000000000..522f5a676
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/SupportFunctions/math_helper.c
@@ -0,0 +1,460 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.c
+*
+* Description: Definition of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+/* ----------------------------------------------------------------------
+* Include standard header files
+* -------------------------------------------------------------------- */
+#include<math.h>
+
+/* ----------------------------------------------------------------------
+* Include project header files
+* -------------------------------------------------------------------- */
+#include "math_helper.h"
+
+/**
+ * @brief Caluclation of SNR
+ * @param float* Pointer to the reference buffer
+ * @param float* Pointer to the test buffer
+ * @param uint32_t total number of samples
+ * @return float SNR
+ * The function Caluclates signal to noise ratio for the reference output
+ * and test output
+ */
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize)
+{
+ float EnergySignal = 0.0, EnergyError = 0.0;
+ uint32_t i;
+ float SNR;
+ int temp;
+ int *test;
+
+ for (i = 0; i < buffSize; i++)
+ {
+ /* Checking for a NAN value in pRef array */
+ test = (int *)(&pRef[i]);
+ temp = *test;
+
+ if(temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+ /* Checking for a NAN value in pTest array */
+ test = (int *)(&pTest[i]);
+ temp = *test;
+
+ if(temp == 0x7FC00000)
+ {
+ return(0);
+ }
+ EnergySignal += pRef[i] * pRef[i];
+ EnergyError += (pRef[i] - pTest[i]) * (pRef[i] - pTest[i]);
+ }
+
+ /* Checking for a NAN value in EnergyError */
+ test = (int *)(&EnergyError);
+ temp = *test;
+
+ if(temp == 0x7FC00000)
+ {
+ return(0);
+ }
+
+
+ SNR = 10 * log10 (EnergySignal / EnergyError);
+
+ return (SNR);
+
+}
+
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param q15_t* Pointer to input buffer
+ * @param uint32_t blockSize
+ * @param uint32_t guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q15 (q15_t * input_buf, uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Converts float to fixed in q12.20 format
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point(q12.20) values
+ */
+
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1048576.0f corresponds to pow(2, 20) */
+ pOut[i] = (q31_t) (pIn[i] * 1048576.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 1.0)
+ {
+ pOut[i] = 0x000FFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param q15_t* Pointer to Ref buffer
+ * @param q15_t* Pointer to Test buffer
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ */
+
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff;
+ uint32_t diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if(diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Compare MATLAB Reference Output and ARM Test output
+ * @param q31_t* Pointer to Ref buffer
+ * @param q31_t* Pointer to Test buffer
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ */
+
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t * pOut, uint32_t numSamples)
+{
+ uint32_t i;
+ int32_t diff;
+ uint32_t diffCrnt = 0;
+ uint32_t maxDiff = 0;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ diff = pIn[i] - pOut[i];
+ diffCrnt = (diff > 0) ? diff : -diff;
+
+ if(diffCrnt > maxDiff)
+ {
+ maxDiff = diffCrnt;
+ }
+ }
+
+ return(maxDiff);
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param q31_t* Pointer to input buffer
+ * @param uint32_t blockSize
+ * @param uint32_t guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q31 (q31_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+/**
+ * @brief Provide guard bits for Input buffer
+ * @param q31_t* Pointer to input buffer
+ * @param uint32_t blockSize
+ * @param uint32_t guard_bits
+ * @return none
+ * The function Provides the guard bits for the buffer
+ * to avoid overflow
+ */
+
+void arm_provide_guard_bits_q7 (q7_t * input_buf,
+ uint32_t blockSize,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < blockSize; i++)
+ {
+ input_buf[i] = input_buf[i] >> guard_bits;
+ }
+}
+
+
+
+/**
+ * @brief Caluclates number of guard bits
+ * @param uint32_t number of additions
+ * @return none
+ * The function Caluclates the number of guard bits
+ * depending on the numtaps
+ */
+
+uint32_t arm_calc_guard_bits (uint32_t num_adds)
+{
+ uint32_t i = 1, j = 0;
+
+ if (num_adds == 1)
+ {
+ return (0);
+ }
+
+ while (i < num_adds)
+ {
+ i = i * 2;
+ j++;
+ }
+
+ return (j);
+}
+
+/**
+ * @brief Converts Q15 to floating-point
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ */
+
+void arm_apply_guard_bits (float32_t * pIn,
+ uint32_t numSamples,
+ uint32_t guard_bits)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ pIn[i] = pIn[i] * arm_calc_2pow(guard_bits);
+ }
+}
+
+/**
+ * @brief Calculates pow(2, numShifts)
+ * @param uint32_t number of shifts
+ * @return pow(2, numShifts)
+ */
+uint32_t arm_calc_2pow(uint32_t numShifts)
+{
+
+ uint32_t i, val = 1;
+
+ for (i = 0; i < numShifts; i++)
+ {
+ val = val * 2;
+ }
+
+ return(val);
+}
+
+
+
+/**
+ * @brief Converts float to fixed q14
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q14 (float *pIn, q15_t * pOut,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 16384.0f corresponds to pow(2, 14) */
+ pOut[i] = (q15_t) (pIn[i] * 16384.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFF;
+ }
+
+ }
+
+}
+
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q30 (float *pIn, q31_t * pOut,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 1073741824.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 2.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Converts float to fixed q30 format
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q29 (float *pIn, q31_t * pOut,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 1073741824.0f corresponds to pow(2, 30) */
+ pOut[i] = (q31_t) (pIn[i] * 536870912.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 4.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+
+/**
+ * @brief Converts float to fixed q28 format
+ * @param uint32_t number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_float_to_q28 (float *pIn, q31_t * pOut,
+ uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ /* 268435456.0f corresponds to pow(2, 28) */
+ pOut[i] = (q31_t) (pIn[i] * 268435456.0f);
+
+ pOut[i] += pIn[i] > 0 ? 0.5 : -0.5;
+
+ if (pIn[i] == (float) 8.0)
+ {
+ pOut[i] = 0x7FFFFFFF;
+ }
+ }
+}
+
+/**
+ * @brief Clip the float values to +/- 1
+ * @param pIn input buffer
+ * @param numSamples number of samples in the buffer
+ * @return none
+ * The function converts floating point values to fixed point values
+ */
+
+void arm_clip_f32 (float *pIn, uint32_t numSamples)
+{
+ uint32_t i;
+
+ for (i = 0; i < numSamples; i++)
+ {
+ if(pIn[i] > 1.0f)
+ {
+ pIn[i] = 1.0;
+ }
+ else if( pIn[i] < -1.0f)
+ {
+ pIn[i] = -1.0;
+ }
+
+ }
+}
+
+
+
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_bitreversal.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_bitreversal.c
new file mode 100644
index 000000000..7e1795db3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_bitreversal.c
@@ -0,0 +1,242 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_bitreversal.c
+*
+* Description: This file has common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/*
+* @brief In-place bit reversal function.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftSize length of the FFT.
+* @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
+* @param[in] *pBitRevTab points to the bit reversal table.
+* @return none.
+*/
+
+void arm_bitreversal_f32(
+float32_t * pSrc,
+uint16_t fftSize,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab)
+{
+ uint16_t fftLenBy2, fftLenBy2p1;
+ uint16_t i, j;
+ float32_t in;
+
+ /* Initializations */
+ j = 0u;
+ fftLenBy2 = fftSize >> 1u;
+ fftLenBy2p1 = (fftSize >> 1u) + 1u;
+
+ /* Bit Reversal Implementation */
+ for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+ {
+ if(i < j)
+ {
+ /* pSrc[i] <-> pSrc[j]; */
+ in = pSrc[2u * i];
+ pSrc[2u * i] = pSrc[2u * j];
+ pSrc[2u * j] = in;
+
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[(2u * i) + 1u];
+ pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+ pSrc[(2u * j) + 1u] = in;
+
+ /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+ in = pSrc[2u * (i + fftLenBy2p1)];
+ pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+ pSrc[2u * (j + fftLenBy2p1)] = in;
+
+ /* pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+ in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+ pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+ pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+ pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+ }
+
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[2u * (i + 1u)];
+ pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+ pSrc[2u * (j + fftLenBy2)] = in;
+
+ /* pSrc[i+2u] <-> pSrc[j+2u] */
+ in = pSrc[(2u * (i + 1u)) + 1u];
+ pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+ pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+ /* Reading the index for the bit reversal */
+ j = *pBitRevTab;
+
+ /* Updating the bit reversal index depending on the fft length */
+ pBitRevTab += bitRevFactor;
+ }
+}
+
+
+
+/*
+* @brief In-place bit reversal function.
+* @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+* @param[in] *pBitRevTab points to bit reversal table.
+* @return none.
+*/
+
+void arm_bitreversal_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTable)
+{
+ uint32_t fftLenBy2, fftLenBy2p1, i, j;
+ q31_t in;
+
+ /* Initializations */
+ j = 0u;
+ fftLenBy2 = fftLen / 2u;
+ fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+ /* Bit Reversal Implementation */
+ for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+ {
+ if(i < j)
+ {
+ /* pSrc[i] <-> pSrc[j]; */
+ in = pSrc[2u * i];
+ pSrc[2u * i] = pSrc[2u * j];
+ pSrc[2u * j] = in;
+
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[(2u * i) + 1u];
+ pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+ pSrc[(2u * j) + 1u] = in;
+
+ /* pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+ in = pSrc[2u * (i + fftLenBy2p1)];
+ pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+ pSrc[2u * (j + fftLenBy2p1)] = in;
+
+ /* pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+ in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+ pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+ pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+ pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+ }
+
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[2u * (i + 1u)];
+ pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+ pSrc[2u * (j + fftLenBy2)] = in;
+
+ /* pSrc[i+2u] <-> pSrc[j+2u] */
+ in = pSrc[(2u * (i + 1u)) + 1u];
+ pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+ pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+ /* Reading the index for the bit reversal */
+ j = *pBitRevTable;
+
+ /* Updating the bit reversal index depending on the fft length */
+ pBitRevTable += bitRevFactor;
+ }
+}
+
+
+
+/*
+ * @brief In-place bit reversal function.
+ * @param[in, out] *pSrc points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+ * @param[in] *pBitRevTab points to bit reversal table.
+ * @return none.
+*/
+
+void arm_bitreversal_q15(
+q15_t * pSrc16,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab)
+{
+ q31_t *pSrc = (q31_t *) pSrc16;
+ q31_t in;
+ uint32_t fftLenBy2, fftLenBy2p1;
+ uint32_t i, j;
+
+ /* Initializations */
+ j = 0u;
+ fftLenBy2 = fftLen / 2u;
+ fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+ /* Bit Reversal Implementation */
+ for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+ {
+ if(i < j)
+ {
+ /* pSrc[i] <-> pSrc[j]; */
+ /* pSrc[i+1u] <-> pSrc[j+1u] */
+ in = pSrc[i];
+ pSrc[i] = pSrc[j];
+ pSrc[j] = in;
+
+ /* pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1]; */
+ /* pSrc[i + fftLenBy2p1+1u] <-> pSrc[j + fftLenBy2p1+1u] */
+ in = pSrc[i + fftLenBy2p1];
+ pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1];
+ pSrc[j + fftLenBy2p1] = in;
+ }
+
+ /* pSrc[i+1u] <-> pSrc[j+fftLenBy2]; */
+ /* pSrc[i+2] <-> pSrc[j+fftLenBy2+1u] */
+ in = pSrc[i + 1u];
+ pSrc[i + 1u] = pSrc[j + fftLenBy2];
+ pSrc[j + fftLenBy2] = in;
+
+ /* Reading the index for the bit reversal */
+ j = *pBitRevTab;
+
+ /* Updating the bit reversal index depending on the fft length */
+ pBitRevTab += bitRevFactor;
+ }
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_bitreversal2.S b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_bitreversal2.S
new file mode 100644
index 000000000..7a2885b1e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_bitreversal2.S
@@ -0,0 +1,148 @@
+;/* ----------------------------------------------------------------------
+;* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+;*
+;* $Date: 17. January 2013
+;* $Revision: V1.4.1
+;*
+;* Project: CMSIS DSP Library
+;* Title: arm_bitreversal2.S
+;*
+;* Description: This is the arm_bitreversal_32 function done in
+;* assembly for maximum speed. This function is called
+;* after doing an fft to reorder the output. The function
+;* is loop unrolled by 2.
+;*
+;* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+;*
+;* Redistribution and use in source and binary forms, with or without
+;* modification, are permitted provided that the following conditions
+;* are met:
+;* - Redistributions of source code must retain the above copyright
+;* notice, this list of conditions and the following disclaimer.
+;* - Redistributions in binary form must reproduce the above copyright
+;* notice, this list of conditions and the following disclaimer in
+;* the documentation and/or other materials provided with the
+;* distribution.
+;* - Neither the name of ARM LIMITED nor the names of its contributors
+;* may be used to endorse or promote products derived from this
+;* software without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+;* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+;* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+;* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+;* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+;* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+;* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+;* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+;* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;* POSSIBILITY OF SUCH DAMAGE.
+;* -------------------------------------------------------------------- */
+#if defined(__CC_ARM) //Keil
+ #define CODESECT AREA ||.text||, CODE, READONLY, ALIGN=2
+ #define LABEL
+#elif defined(__IASMARM__) //IAR
+ #define CODESECT SECTION `.text`:CODE
+ #define PROC
+ #define LABEL
+ #define ENDP
+ #define EXPORT PUBLIC
+#elif defined (__GNUC__) //GCC
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ #define THUMB .thumb
+ #define CODESECT .section text
+ #define EXPORT .global
+ #define PROC :
+ #define LABEL :
+ #define ENDP
+ #define END
+#endif
+
+ CODESECT
+ THUMB
+
+;/*
+;* @brief In-place bit reversal function.
+;* @param[in, out] *pSrc points to the in-place buffer of unknown 32-bit data type.
+;* @param[in] bitRevLen bit reversal table length
+;* @param[in] *pBitRevTab points to bit reversal table.
+;* @return none.
+;*/
+ EXPORT arm_bitreversal_32
+
+#if defined(ARM_MATH_CM0) || defined(ARM_MATH_CM0PLUS)
+
+arm_bitreversal_32 PROC
+ ADDS r3,r1,#1
+ PUSH {r4-r6}
+ ADDS r1,r2,#0
+ LSRS r3,r3,#1
+arm_bitreversal_32_0 LABEL
+ LDRH r2,[r1,#2]
+ LDRH r6,[r1,#0]
+ ADD r2,r0,r2
+ ADD r6,r0,r6
+ LDR r5,[r2,#0]
+ LDR r4,[r6,#0]
+ STR r5,[r6,#0]
+ STR r4,[r2,#0]
+ LDR r5,[r2,#4]
+ LDR r4,[r6,#4]
+ STR r5,[r6,#4]
+ STR r4,[r2,#4]
+ ADDS r1,r1,#4
+ SUBS r3,r3,#1
+ BNE arm_bitreversal_32_0
+ POP {r4-r6}
+ BX lr
+ ENDP
+
+#else
+
+arm_bitreversal_32 PROC
+ ADDS r3,r1,#1
+ CMP r3,#1
+ IT LS
+ BXLS lr
+ PUSH {r4-r9}
+ ADDS r1,r2,#2
+ LSRS r3,r3,#2
+arm_bitreversal_32_0 LABEL ;/* loop unrolled by 2 */
+ LDRH r8,[r1,#4]
+ LDRH r9,[r1,#2]
+ LDRH r2,[r1,#0]
+ LDRH r12,[r1,#-2]
+ ADD r8,r0,r8
+ ADD r9,r0,r9
+ ADD r2,r0,r2
+ ADD r12,r0,r12
+ LDR r7,[r9,#0]
+ LDR r6,[r8,#0]
+ LDR r5,[r2,#0]
+ LDR r4,[r12,#0]
+ STR r6,[r9,#0]
+ STR r7,[r8,#0]
+ STR r5,[r12,#0]
+ STR r4,[r2,#0]
+ LDR r7,[r9,#4]
+ LDR r6,[r8,#4]
+ LDR r5,[r2,#4]
+ LDR r4,[r12,#4]
+ STR r6,[r9,#4]
+ STR r7,[r8,#4]
+ STR r5,[r12,#4]
+ STR r4,[r2,#4]
+ ADDS r1,r1,#8
+ SUBS r3,r3,#1
+ BNE arm_bitreversal_32_0
+ POP {r4-r9}
+ BX lr
+ ENDP
+
+#endif
+
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_f32.c
new file mode 100644
index 000000000..8a13dfa95
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_f32.c
@@ -0,0 +1,616 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_f32.c
+*
+* Description: Combined Radix Decimation in Frequency CFFT Floating point processing function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+extern void arm_radix8_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ const float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+extern void arm_bitreversal_32(
+ uint32_t * pSrc,
+ const uint16_t bitRevLen,
+ const uint16_t * pBitRevTable);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @defgroup ComplexFFT Complex FFT Functions
+*
+* \par
+* The Fast Fourier Transform (FFT) is an efficient algorithm for computing the
+* Discrete Fourier Transform (DFT). The FFT can be orders of magnitude faster
+* than the DFT, especially for long lengths.
+* The algorithms described in this section
+* operate on complex data. A separate set of functions is devoted to handling
+* of real sequences.
+* \par
+* There are separate algorithms for handling floating-point, Q15, and Q31 data
+* types. The algorithms available for each data type are described next.
+* \par
+* The FFT functions operate in-place. That is, the array holding the input data
+* will also be used to hold the corresponding result. The input data is complex
+* and contains <code>2*fftLen</code> interleaved values as shown below.
+* <pre> {real[0], imag[0], real[1], imag[1],..} </pre>
+* The FFT result will be contained in the same array and the frequency domain
+* values will have the same interleaving.
+*
+* \par Floating-point
+* The floating-point complex FFT uses a mixed-radix algorithm. Multiple radix-8
+* stages are performed along with a single radix-2 or radix-4 stage, as needed.
+* The algorithm supports lengths of [16, 32, 64, ..., 4096] and each length uses
+* a different twiddle factor table.
+* \par
+* The function uses the standard FFT definition and output values may grow by a
+* factor of <code>fftLen</code> when computing the forward transform. The
+* inverse transform includes a scale of <code>1/fftLen</code> as part of the
+* calculation and this matches the textbook definition of the inverse FFT.
+* \par
+* Preinitialized data structures containing twiddle factors and bit reversal
+* tables are provided and defined in <code>arm_const_structs.h</code>. Include
+* this header in your function and then pass one of the constant structures as
+* an argument to arm_cfft_f32. For example:
+* \par
+* <code>arm_cfft_f32(arm_cfft_sR_f32_len64, pSrc, 1, 1)</code>
+* \par
+* computes a 64-point inverse complex FFT including bit reversal.
+* The data structures are treated as constant data and not modified during the
+* calculation. The same data structure can be reused for multiple transforms
+* including mixing forward and inverse transforms.
+* \par
+* Earlier releases of the library provided separate radix-2 and radix-4
+* algorithms that operated on floating-point data. These functions are still
+* provided but are deprecated. The older functions are slower and less general
+* than the new functions.
+* \par
+* An example of initialization of the constants for the arm_cfft_f32 function follows:
+* \par
+* const static arm_cfft_instance_f32 *S;
+* ...
+* switch (length) {
+* case 16:
+* S = & arm_cfft_sR_f32_len16;
+* break;
+* case 32:
+* S = & arm_cfft_sR_f32_len32;
+* break;
+* case 64:
+* S = & arm_cfft_sR_f32_len64;
+* break;
+* case 128:
+* S = & arm_cfft_sR_f32_len128;
+* break;
+* case 256:
+* S = & arm_cfft_sR_f32_len256;
+* break;
+* case 512:
+* S = & arm_cfft_sR_f32_len512;
+* break;
+* case 1024:
+* S = & arm_cfft_sR_f32_len1024;
+* break;
+* case 2048:
+* S = & arm_cfft_sR_f32_len2048;
+* break;
+* case 4096:
+* S = & arm_cfft_sR_f32_len4096;
+* break;
+* }
+* \par Q15 and Q31
+* The library provides radix-2 and radix-4 FFT algorithms for fixed-point data. The
+* radix-2 algorithm supports lengths of [16, 32, 64, ..., 4096]. The radix-4
+* algorithm supports lengths of [16, 64, 256, ..., 4096]. When possible, you
+* should use the radix-4 algorithm since it is faster than the radix-2 of the
+* same length.
+* \par
+* The forward FFTs include scaling in order to prevent results from overflowing.
+* Intermediate results are scaled down during each butterfly stage. In the
+* radix-2 algorithm, a scale of 0.5 is applied during each butterfly. In the
+* radix-4 algorithm, a scale of 0.25 is applied. The scaling applies to both
+* the forward and the inverse FFTs. Thus the forward FFT contains an additional
+* scale factor of <code>1/fftLen</code> as compared to the standard textbook
+* definition of the FFT. The inverse FFT also scales down during each butterfly
+* stage and this corresponds to the standard textbook definition.
+* \par
+* A separate instance structure must be defined for each transform used but
+* twiddle factor and bit reversal tables can be reused.
+* \par
+* There is also an associated initialization function for each data type.
+* The initialization function performs the following operations:
+* - Sets the values of the internal structure fields.
+* - Initializes twiddle factor table and bit reversal table pointers.
+* \par
+* Use of the initialization function is optional.
+* However, if the initialization function is used, then the instance structure
+* cannot be placed into a const data section. To place an instance structure
+* into a const data section, the instance structure should be manually
+* initialized as follows:
+* <pre>
+*arm_cfft_radix2_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};
+*arm_cfft_radix2_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};
+*arm_cfft_radix4_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};
+*arm_cfft_radix4_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};
+*arm_cfft_instance_f32 S = {fftLen, pTwiddle, pBitRevTable, bitRevLength};
+* </pre>
+* \par
+* where <code>fftLen</code> length of CFFT/CIFFT; <code>ifftFlag</code> Flag for
+* selection of forward or inverse transform. When ifftFlag is set the inverse
+* transform is calculated.
+* <code>bitReverseFlag</code> Flag for selection of output order (Set bitReverseFlag to output in normal order otherwise output in bit reversed order);
+* <code>pTwiddle</code>points to array of twiddle coefficients; <code>pBitRevTable</code> points to the bit reversal table.
+* <code>twidCoefModifier</code> modifier for twiddle factor table which supports all FFT lengths with same table;
+* <code>pBitRevTable</code> modifier for bit reversal table which supports all FFT lengths with same table.
+* <code>onebyfftLen</code> value of 1/fftLen to calculate CIFFT;
+* \par
+* The Q15 and Q31 FFT functions use a large bit reversal and twiddle factor
+* table. The tables are defined for the maximum length transform and a subset
+* of the coefficients are used in shorter transforms.
+*
+*/
+
+void arm_cfft_radix8by2_f32( arm_cfft_instance_f32 * S, float32_t * p1)
+{
+ uint32_t L = S->fftLen;
+ float32_t * pCol1, * pCol2, * pMid1, * pMid2;
+ float32_t * p2 = p1 + L;
+ const float32_t * tw = (float32_t *) S->pTwiddle;
+ float32_t t1[4], t2[4], t3[4], t4[4], twR, twI;
+ float32_t m0, m1, m2, m3;
+ uint32_t l;
+
+ pCol1 = p1;
+ pCol2 = p2;
+
+ // Define new length
+ L >>= 1;
+ // Initialize mid pointers
+ pMid1 = p1 + L;
+ pMid2 = p2 + L;
+
+ // do two dot Fourier transform
+ for ( l = L >> 2; l > 0; l-- )
+ {
+ t1[0] = p1[0];
+ t1[1] = p1[1];
+ t1[2] = p1[2];
+ t1[3] = p1[3];
+
+ t2[0] = p2[0];
+ t2[1] = p2[1];
+ t2[2] = p2[2];
+ t2[3] = p2[3];
+
+ t3[0] = pMid1[0];
+ t3[1] = pMid1[1];
+ t3[2] = pMid1[2];
+ t3[3] = pMid1[3];
+
+ t4[0] = pMid2[0];
+ t4[1] = pMid2[1];
+ t4[2] = pMid2[2];
+ t4[3] = pMid2[3];
+
+ *p1++ = t1[0] + t2[0];
+ *p1++ = t1[1] + t2[1];
+ *p1++ = t1[2] + t2[2];
+ *p1++ = t1[3] + t2[3]; // col 1
+
+ t2[0] = t1[0] - t2[0];
+ t2[1] = t1[1] - t2[1];
+ t2[2] = t1[2] - t2[2];
+ t2[3] = t1[3] - t2[3]; // for col 2
+
+ *pMid1++ = t3[0] + t4[0];
+ *pMid1++ = t3[1] + t4[1];
+ *pMid1++ = t3[2] + t4[2];
+ *pMid1++ = t3[3] + t4[3]; // col 1
+
+ t4[0] = t4[0] - t3[0];
+ t4[1] = t4[1] - t3[1];
+ t4[2] = t4[2] - t3[2];
+ t4[3] = t4[3] - t3[3]; // for col 2
+
+ twR = *tw++;
+ twI = *tw++;
+
+ // multiply by twiddle factors
+ m0 = t2[0] * twR;
+ m1 = t2[1] * twI;
+ m2 = t2[1] * twR;
+ m3 = t2[0] * twI;
+
+ // R = R * Tr - I * Ti
+ *p2++ = m0 + m1;
+ // I = I * Tr + R * Ti
+ *p2++ = m2 - m3;
+
+ // use vertical symmetry
+ // 0.9988 - 0.0491i <==> -0.0491 - 0.9988i
+ m0 = t4[0] * twI;
+ m1 = t4[1] * twR;
+ m2 = t4[1] * twI;
+ m3 = t4[0] * twR;
+
+ *pMid2++ = m0 - m1;
+ *pMid2++ = m2 + m3;
+
+ twR = *tw++;
+ twI = *tw++;
+
+ m0 = t2[2] * twR;
+ m1 = t2[3] * twI;
+ m2 = t2[3] * twR;
+ m3 = t2[2] * twI;
+
+ *p2++ = m0 + m1;
+ *p2++ = m2 - m3;
+
+ m0 = t4[2] * twI;
+ m1 = t4[3] * twR;
+ m2 = t4[3] * twI;
+ m3 = t4[2] * twR;
+
+ *pMid2++ = m0 - m1;
+ *pMid2++ = m2 + m3;
+ }
+
+ // first col
+ arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 2u);
+ // second col
+ arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 2u);
+
+}
+
+void arm_cfft_radix8by4_f32( arm_cfft_instance_f32 * S, float32_t * p1)
+{
+ uint32_t L = S->fftLen >> 1;
+ float32_t * pCol1, *pCol2, *pCol3, *pCol4, *pEnd1, *pEnd2, *pEnd3, *pEnd4;
+ const float32_t *tw2, *tw3, *tw4;
+ float32_t * p2 = p1 + L;
+ float32_t * p3 = p2 + L;
+ float32_t * p4 = p3 + L;
+ float32_t t2[4], t3[4], t4[4], twR, twI;
+ float32_t p1ap3_0, p1sp3_0, p1ap3_1, p1sp3_1;
+ float32_t m0, m1, m2, m3;
+ uint32_t l, twMod2, twMod3, twMod4;
+
+ pCol1 = p1; // points to real values by default
+ pCol2 = p2;
+ pCol3 = p3;
+ pCol4 = p4;
+ pEnd1 = p2 - 1; // points to imaginary values by default
+ pEnd2 = p3 - 1;
+ pEnd3 = p4 - 1;
+ pEnd4 = pEnd3 + L;
+
+ tw2 = tw3 = tw4 = (float32_t *) S->pTwiddle;
+
+ L >>= 1;
+
+ // do four dot Fourier transform
+
+ twMod2 = 2;
+ twMod3 = 4;
+ twMod4 = 6;
+
+ // TOP
+ p1ap3_0 = p1[0] + p3[0];
+ p1sp3_0 = p1[0] - p3[0];
+ p1ap3_1 = p1[1] + p3[1];
+ p1sp3_1 = p1[1] - p3[1];
+
+ // col 2
+ t2[0] = p1sp3_0 + p2[1] - p4[1];
+ t2[1] = p1sp3_1 - p2[0] + p4[0];
+ // col 3
+ t3[0] = p1ap3_0 - p2[0] - p4[0];
+ t3[1] = p1ap3_1 - p2[1] - p4[1];
+ // col 4
+ t4[0] = p1sp3_0 - p2[1] + p4[1];
+ t4[1] = p1sp3_1 + p2[0] - p4[0];
+ // col 1
+ *p1++ = p1ap3_0 + p2[0] + p4[0];
+ *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+ // Twiddle factors are ones
+ *p2++ = t2[0];
+ *p2++ = t2[1];
+ *p3++ = t3[0];
+ *p3++ = t3[1];
+ *p4++ = t4[0];
+ *p4++ = t4[1];
+
+ tw2 += twMod2;
+ tw3 += twMod3;
+ tw4 += twMod4;
+
+ for (l = (L - 2) >> 1; l > 0; l-- )
+ {
+
+ // TOP
+ p1ap3_0 = p1[0] + p3[0];
+ p1sp3_0 = p1[0] - p3[0];
+ p1ap3_1 = p1[1] + p3[1];
+ p1sp3_1 = p1[1] - p3[1];
+ // col 2
+ t2[0] = p1sp3_0 + p2[1] - p4[1];
+ t2[1] = p1sp3_1 - p2[0] + p4[0];
+ // col 3
+ t3[0] = p1ap3_0 - p2[0] - p4[0];
+ t3[1] = p1ap3_1 - p2[1] - p4[1];
+ // col 4
+ t4[0] = p1sp3_0 - p2[1] + p4[1];
+ t4[1] = p1sp3_1 + p2[0] - p4[0];
+ // col 1 - top
+ *p1++ = p1ap3_0 + p2[0] + p4[0];
+ *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+ // BOTTOM
+ p1ap3_1 = pEnd1[-1] + pEnd3[-1];
+ p1sp3_1 = pEnd1[-1] - pEnd3[-1];
+ p1ap3_0 = pEnd1[0] + pEnd3[0];
+ p1sp3_0 = pEnd1[0] - pEnd3[0];
+ // col 2
+ t2[2] = pEnd2[0] - pEnd4[0] + p1sp3_1;
+ t2[3] = pEnd1[0] - pEnd3[0] - pEnd2[-1] + pEnd4[-1];
+ // col 3
+ t3[2] = p1ap3_1 - pEnd2[-1] - pEnd4[-1];
+ t3[3] = p1ap3_0 - pEnd2[0] - pEnd4[0];
+ // col 4
+ t4[2] = pEnd2[0] - pEnd4[0] - p1sp3_1;
+ t4[3] = pEnd4[-1] - pEnd2[-1] - p1sp3_0;
+ // col 1 - Bottom
+ *pEnd1-- = p1ap3_0 + pEnd2[0] + pEnd4[0];
+ *pEnd1-- = p1ap3_1 + pEnd2[-1] + pEnd4[-1];
+
+ // COL 2
+ // read twiddle factors
+ twR = *tw2++;
+ twI = *tw2++;
+ // multiply by twiddle factors
+ // let Z1 = a + i(b), Z2 = c + i(d)
+ // => Z1 * Z2 = (a*c - b*d) + i(b*c + a*d)
+ // Top
+ m0 = t2[0] * twR;
+ m1 = t2[1] * twI;
+ m2 = t2[1] * twR;
+ m3 = t2[0] * twI;
+
+ *p2++ = m0 + m1;
+ *p2++ = m2 - m3;
+ // use vertical symmetry col 2
+ // 0.9997 - 0.0245i <==> 0.0245 - 0.9997i
+ // Bottom
+ m0 = t2[3] * twI;
+ m1 = t2[2] * twR;
+ m2 = t2[2] * twI;
+ m3 = t2[3] * twR;
+
+ *pEnd2-- = m0 - m1;
+ *pEnd2-- = m2 + m3;
+
+ // COL 3
+ twR = tw3[0];
+ twI = tw3[1];
+ tw3 += twMod3;
+ // Top
+ m0 = t3[0] * twR;
+ m1 = t3[1] * twI;
+ m2 = t3[1] * twR;
+ m3 = t3[0] * twI;
+
+ *p3++ = m0 + m1;
+ *p3++ = m2 - m3;
+ // use vertical symmetry col 3
+ // 0.9988 - 0.0491i <==> -0.9988 - 0.0491i
+ // Bottom
+ m0 = -t3[3] * twR;
+ m1 = t3[2] * twI;
+ m2 = t3[2] * twR;
+ m3 = t3[3] * twI;
+
+ *pEnd3-- = m0 - m1;
+ *pEnd3-- = m3 - m2;
+
+ // COL 4
+ twR = tw4[0];
+ twI = tw4[1];
+ tw4 += twMod4;
+ // Top
+ m0 = t4[0] * twR;
+ m1 = t4[1] * twI;
+ m2 = t4[1] * twR;
+ m3 = t4[0] * twI;
+
+ *p4++ = m0 + m1;
+ *p4++ = m2 - m3;
+ // use vertical symmetry col 4
+ // 0.9973 - 0.0736i <==> -0.0736 + 0.9973i
+ // Bottom
+ m0 = t4[3] * twI;
+ m1 = t4[2] * twR;
+ m2 = t4[2] * twI;
+ m3 = t4[3] * twR;
+
+ *pEnd4-- = m0 - m1;
+ *pEnd4-- = m2 + m3;
+ }
+
+ //MIDDLE
+ // Twiddle factors are
+ // 1.0000 0.7071-0.7071i -1.0000i -0.7071-0.7071i
+ p1ap3_0 = p1[0] + p3[0];
+ p1sp3_0 = p1[0] - p3[0];
+ p1ap3_1 = p1[1] + p3[1];
+ p1sp3_1 = p1[1] - p3[1];
+
+ // col 2
+ t2[0] = p1sp3_0 + p2[1] - p4[1];
+ t2[1] = p1sp3_1 - p2[0] + p4[0];
+ // col 3
+ t3[0] = p1ap3_0 - p2[0] - p4[0];
+ t3[1] = p1ap3_1 - p2[1] - p4[1];
+ // col 4
+ t4[0] = p1sp3_0 - p2[1] + p4[1];
+ t4[1] = p1sp3_1 + p2[0] - p4[0];
+ // col 1 - Top
+ *p1++ = p1ap3_0 + p2[0] + p4[0];
+ *p1++ = p1ap3_1 + p2[1] + p4[1];
+
+ // COL 2
+ twR = tw2[0];
+ twI = tw2[1];
+
+ m0 = t2[0] * twR;
+ m1 = t2[1] * twI;
+ m2 = t2[1] * twR;
+ m3 = t2[0] * twI;
+
+ *p2++ = m0 + m1;
+ *p2++ = m2 - m3;
+ // COL 3
+ twR = tw3[0];
+ twI = tw3[1];
+
+ m0 = t3[0] * twR;
+ m1 = t3[1] * twI;
+ m2 = t3[1] * twR;
+ m3 = t3[0] * twI;
+
+ *p3++ = m0 + m1;
+ *p3++ = m2 - m3;
+ // COL 4
+ twR = tw4[0];
+ twI = tw4[1];
+
+ m0 = t4[0] * twR;
+ m1 = t4[1] * twI;
+ m2 = t4[1] * twR;
+ m3 = t4[0] * twI;
+
+ *p4++ = m0 + m1;
+ *p4++ = m2 - m3;
+
+ // first col
+ arm_radix8_butterfly_f32( pCol1, L, (float32_t *) S->pTwiddle, 4u);
+ // second col
+ arm_radix8_butterfly_f32( pCol2, L, (float32_t *) S->pTwiddle, 4u);
+ // third col
+ arm_radix8_butterfly_f32( pCol3, L, (float32_t *) S->pTwiddle, 4u);
+ // fourth col
+ arm_radix8_butterfly_f32( pCol4, L, (float32_t *) S->pTwiddle, 4u);
+
+}
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Processing function for the floating-point complex FFT.
+* @param[in] *S points to an instance of the floating-point CFFT structure.
+* @param[in, out] *p1 points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return none.
+*/
+
+void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+
+ uint32_t L = S->fftLen, l;
+ float32_t invL, * pSrc;
+
+ if(ifftFlag == 1u)
+ {
+ /* Conjugate input data */
+ pSrc = p1 + 1;
+ for(l=0; l<L; l++) {
+ *pSrc = -*pSrc;
+ pSrc += 2;
+ }
+ }
+
+ switch (L) {
+ case 16:
+ case 128:
+ case 1024:
+ arm_cfft_radix8by2_f32 ( (arm_cfft_instance_f32 *) S, p1);
+ break;
+ case 32:
+ case 256:
+ case 2048:
+ arm_cfft_radix8by4_f32 ( (arm_cfft_instance_f32 *) S, p1);
+ break;
+ case 64:
+ case 512:
+ case 4096:
+ arm_radix8_butterfly_f32( p1, L, (float32_t *) S->pTwiddle, 1);
+ break;
+ }
+
+ if( bitReverseFlag )
+ arm_bitreversal_32((uint32_t*)p1,S->bitRevLength,S->pBitRevTable);
+
+ if(ifftFlag == 1u)
+ {
+ invL = 1.0f/(float32_t)L;
+ /* Conjugate and scale output data */
+ pSrc = p1;
+ for(l=0; l<L; l++) {
+ *pSrc++ *= invL ;
+ *pSrc = -(*pSrc) * invL;
+ pSrc++;
+ }
+ }
+}
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_f32.c
new file mode 100644
index 000000000..b5b3eb51a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_f32.c
@@ -0,0 +1,485 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_f32.c
+*
+* Description: Radix-2 Decimation in Frequency CFFT & CIFFT Floating point processing function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+extern void arm_bitreversal_f32(
+ float32_t * pSrc,
+ uint16_t fftSize,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Radix-2 CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in] *S points to an instance of the floating-point Radix-2 CFFT/CIFFT structure.
+* @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.
+* @return none.
+*/
+
+void arm_cfft_radix2_f32(
+const arm_cfft_radix2_instance_f32 * S,
+float32_t * pSrc)
+{
+
+ if(S->ifftFlag == 1u)
+ {
+ /* Complex IFFT radix-2 */
+ arm_radix2_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier, S->onebyfftLen);
+ }
+ else
+ {
+ /* Complex FFT radix-2 */
+ arm_radix2_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+
+ if(S->bitReverseFlag == 1u)
+ {
+ /* Bit Reversal */
+ arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+ }
+
+}
+
+
+/**
+* @} end of ComplexFFT group
+*/
+
+
+
+/* ----------------------------------------------------------------------
+** Internal helper function used by the FFTs
+** ------------------------------------------------------------------- */
+
+/*
+* @brief Core function for the floating-point CFFT butterfly process.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] *pCoef points to the twiddle coefficient buffer.
+* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+
+void arm_radix2_butterfly_f32(
+float32_t * pSrc,
+uint32_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+ uint32_t i, j, k, l;
+ uint32_t n1, n2, ia;
+ float32_t xt, yt, cosVal, sinVal;
+ float32_t p0, p1, p2, p3;
+ float32_t a0, a1;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Initializations for the first stage */
+ n2 = fftLen >> 1;
+ ia = 0;
+ i = 0;
+
+ // loop for groups
+ for (k = n2; k > 0; k--)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+
+ /* Twiddle coefficients index modifier */
+ ia += twidCoefModifier;
+
+ /* index calculation for the input as, */
+ /* pSrc[i + 0], pSrc[i + fftLen/1] */
+ l = i + n2;
+
+ /* Butterfly implementation */
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 + p1;
+ pSrc[2 * l + 1] = p2 - p3;
+
+ i++;
+ } // groups loop end
+
+ twidCoefModifier <<= 1u;
+
+ // loop for stage
+ for (k = n2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 + p1;
+ pSrc[2 * l + 1] = p2 - p3;
+
+ i += n1;
+ } while( i < fftLen ); // butterfly loop end
+ j++;
+ } while( j < n2); // groups loop end
+ twidCoefModifier <<= 1u;
+ } // stages loop end
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += 2)
+ {
+ a0 = pSrc[2 * i] + pSrc[2 * i + 2];
+ xt = pSrc[2 * i] - pSrc[2 * i + 2];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
+ a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+ pSrc[2 * i + 2] = xt;
+ pSrc[2 * i + 3] = yt;
+ } // groups loop end
+
+#else
+
+ n2 = fftLen;
+
+ // loop for stage
+ for (k = fftLen; k > 1; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 + p1;
+ pSrc[2 * l + 1] = p2 - p3;
+
+ i += n1;
+ } while(i < fftLen);
+ j++;
+ } while(j < n2);
+ twidCoefModifier <<= 1u;
+ }
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+}
+
+
+void arm_radix2_butterfly_inverse_f32(
+float32_t * pSrc,
+uint32_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier,
+float32_t onebyfftLen)
+{
+
+ uint32_t i, j, k, l;
+ uint32_t n1, n2, ia;
+ float32_t xt, yt, cosVal, sinVal;
+ float32_t p0, p1, p2, p3;
+ float32_t a0, a1;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ n2 = fftLen >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 - p1;
+ pSrc[2 * l + 1] = p2 + p3;
+ } // groups loop end
+
+ twidCoefModifier <<= 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia += twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 - p1;
+ pSrc[2 * l + 1] = p2 + p3;
+
+ i += n1;
+ } while( i < fftLen ); // butterfly loop end
+ j++;
+ } while(j < n2); // groups loop end
+
+ twidCoefModifier <<= 1u;
+ } // stages loop end
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += 2)
+ {
+ a0 = pSrc[2 * i] + pSrc[2 * i + 2];
+ xt = pSrc[2 * i] - pSrc[2 * i + 2];
+
+ a1 = pSrc[2 * i + 3] + pSrc[2 * i + 1];
+ yt = pSrc[2 * i + 1] - pSrc[2 * i + 3];
+
+ p0 = a0 * onebyfftLen;
+ p2 = xt * onebyfftLen;
+ p1 = a1 * onebyfftLen;
+ p3 = yt * onebyfftLen;
+
+ pSrc[2 * i] = p0;
+ pSrc[2 * i + 1] = p1;
+ pSrc[2 * i + 2] = p2;
+ pSrc[2 * i + 3] = p3;
+ } // butterfly loop end
+
+#else
+
+ n2 = fftLen;
+
+ // loop for stage
+ for (k = fftLen; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ j = 0;
+ do
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ do
+ {
+ l = i + n2;
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+
+ p0 = xt * cosVal;
+ p1 = yt * sinVal;
+ p2 = yt * cosVal;
+ p3 = xt * sinVal;
+
+ pSrc[2 * i] = a0;
+ pSrc[2 * i + 1] = a1;
+
+ pSrc[2 * l] = p0 - p1;
+ pSrc[2 * l + 1] = p2 + p3;
+
+ i += n1;
+ } while( i < fftLen ); // butterfly loop end
+ j++;
+ } while( j < n2 ); // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ a0 = pSrc[2 * i] + pSrc[2 * l];
+ xt = pSrc[2 * i] - pSrc[2 * l];
+
+ a1 = pSrc[2 * l + 1] + pSrc[2 * i + 1];
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+
+ p0 = a0 * onebyfftLen;
+ p2 = xt * onebyfftLen;
+ p1 = a1 * onebyfftLen;
+ p3 = yt * onebyfftLen;
+
+ pSrc[2 * i] = p0;
+ pSrc[2u * l] = p2;
+
+ pSrc[2 * i + 1] = p1;
+ pSrc[2u * l + 1u] = p3;
+ } // butterfly loop end
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_f32.c
new file mode 100644
index 000000000..81932bc1e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_f32.c
@@ -0,0 +1,205 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_init_f32.c
+*
+* Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+* @brief Initialization function for the floating-point CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter <code>fftLen</code> Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (float32_t *) twiddleCoef;
+
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLen)
+ {
+
+ case 4096u:
+ /* Initializations of structure parameters for 4096 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.000244140625;
+ break;
+
+ case 2048u:
+ /* Initializations of structure parameters for 2048 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 2u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 2u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.00048828125;
+ break;
+
+ case 1024u:
+ /* Initializations of structure parameters for 1024 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 4u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 4u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.0009765625f;
+ break;
+
+ case 512u:
+ /* Initializations of structure parameters for 512 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 8u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 8u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.001953125;
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+ S->onebyfftLen = 0.00390625f;
+ break;
+
+ case 128u:
+ /* Initializations of structure parameters for 128 point FFT */
+ S->twidCoefModifier = 32u;
+ S->bitRevFactor = 32u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+ S->onebyfftLen = 0.0078125;
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+ S->onebyfftLen = 0.015625f;
+ break;
+
+ case 32u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 128u;
+ S->bitRevFactor = 128u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+ S->onebyfftLen = 0.03125;
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+ S->onebyfftLen = 0.0625f;
+ break;
+
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_q15.c
new file mode 100644
index 000000000..e96ba3f16
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_q15.c
@@ -0,0 +1,188 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_init_q15.c
+*
+* Description: Radix-2 Decimation in Frequency Q15 FFT & IFFT initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+* @brief Initialization function for the Q15 CFFT/CIFFT.
+* @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter <code>fftLen</code> Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (q15_t *) twiddleCoefQ15;
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLen)
+ {
+ case 4096u:
+ /* Initializations of structure parameters for 4096 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+
+ break;
+
+ case 2048u:
+ /* Initializations of structure parameters for 2048 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 2u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 2u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+
+ break;
+
+ case 1024u:
+ /* Initializations of structure parameters for 1024 point FFT */
+ S->twidCoefModifier = 4u;
+ S->bitRevFactor = 4u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+
+ break;
+
+ case 512u:
+ /* Initializations of structure parameters for 512 point FFT */
+ S->twidCoefModifier = 8u;
+ S->bitRevFactor = 8u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+
+ break;
+
+ case 128u:
+ /* Initializations of structure parameters for 128 point FFT */
+ S->twidCoefModifier = 32u;
+ S->bitRevFactor = 32u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+
+ break;
+
+ case 32u:
+ /* Initializations of structure parameters for 32 point FFT */
+ S->twidCoefModifier = 128u;
+ S->bitRevFactor = 128u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+
+ break;
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_q31.c
new file mode 100644
index 000000000..d2e84d586
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_init_q31.c
@@ -0,0 +1,186 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_init_q31.c
+*
+* Description: Radix-2 Decimation in Frequency Fixed-point CFFT & CIFFT Initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+
+/**
+*
+* @brief Initialization function for the Q31 CFFT/CIFFT.
+* @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter <code>fftLen</code> Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (q31_t *) twiddleCoefQ31;
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of Instance structure depending on the FFT length */
+ switch (S->fftLen)
+ {
+ /* Initializations of structure parameters for 4096 point FFT */
+ case 4096u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+ break;
+
+ /* Initializations of structure parameters for 2048 point FFT */
+ case 2048u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 2u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 2u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[1];
+ break;
+
+ /* Initializations of structure parameters for 1024 point FFT */
+ case 1024u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 4u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 4u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+ break;
+
+ /* Initializations of structure parameters for 512 point FFT */
+ case 512u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 8u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 8u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[7];
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+ break;
+
+ case 128u:
+ /* Initializations of structure parameters for 128 point FFT */
+ S->twidCoefModifier = 32u;
+ S->bitRevFactor = 32u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[31];
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+ break;
+
+ case 32u:
+ /* Initializations of structure parameters for 32 point FFT */
+ S->twidCoefModifier = 128u;
+ S->bitRevFactor = 128u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[127];
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+ break;
+
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_q15.c
new file mode 100644
index 000000000..0caf6021d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_q15.c
@@ -0,0 +1,741 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_q15.c
+*
+* Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_bitreversal_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+ * @details
+ * @brief Processing function for the fixed-point CFFT/CIFFT.
+ * @param[in] *S points to an instance of the fixed-point CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.
+ * @return none.
+ */
+
+void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc)
+{
+
+ if(S->ifftFlag == 1u)
+ {
+ arm_radix2_butterfly_inverse_q15(pSrc, S->fftLen,
+ S->pTwiddle, S->twidCoefModifier);
+ }
+ else
+ {
+ arm_radix2_butterfly_q15(pSrc, S->fftLen,
+ S->pTwiddle, S->twidCoefModifier);
+ }
+
+ arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
+
+void arm_radix2_butterfly_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q15_t in;
+ q31_t T, S, R;
+ q31_t coeff, out1, out2;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+ in = ((int16_t) (S & 0xFFFF)) >> 2;
+ S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(coeff, R) >> 16;
+ out2 = __SMUSDX(coeff, R);
+
+#else
+
+ out1 = __SMUSDX(R, coeff) >> 16u;
+ out2 = __SMUAD(coeff, R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ i++;
+ l++;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+ in = ((int16_t) (S & 0xFFFF)) >> 2;
+ S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(coeff, R) >> 16;
+ out2 = __SMUSDX(coeff, R);
+
+#else
+
+ out1 = __SMUSDX(R, coeff) >> 16u;
+ out2 = __SMUAD(coeff, R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(coeff, R) >> 16;
+ out2 = __SMUSDX(coeff, R);
+
+#else
+
+ out1 = __SMUSDX(R, coeff) >> 16u;
+ out2 = __SMUAD(coeff, R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ i += n1;
+
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(coeff, R) >> 16;
+ out2 = __SMUSDX(coeff, R);
+
+#else
+
+ out1 = __SMUSDX(R, coeff) >> 16u;
+ out2 = __SMUAD(coeff, R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+ i += n1;
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+ } // groups loop end
+
+
+#else
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q15_t xt, yt, cosVal, sinVal;
+
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
+ pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
+
+ yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
+ pSrc[2 * i + 1] =
+ ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
+
+ pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+ ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+ pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+ ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+ pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) +
+ ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+ pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) -
+ ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+}
+
+
+void arm_radix2_butterfly_inverse_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pCoef,
+ uint16_t twidCoefModifier)
+{
+#ifndef ARM_MATH_CM0_FAMILY
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q15_t in;
+ q31_t T, S, R;
+ q31_t coeff, out1, out2;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+ in = ((int16_t) (S & 0xFFFF)) >> 2;
+ S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(coeff, R) >> 16;
+ out2 = __SMUADX(coeff, R);
+#else
+
+ out1 = __SMUADX(R, coeff) >> 16u;
+ out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ i++;
+ l++;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+ in = ((int16_t) (S & 0xFFFF)) >> 2;
+ S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(coeff, R) >> 16;
+ out2 = __SMUADX(coeff, R);
+#else
+
+ out1 = __SMUADX(R, coeff) >> 16u;
+ out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(coeff, R) >> 16;
+ out2 = __SMUADX(coeff, R);
+
+#else
+
+ out1 = __SMUADX(R, coeff) >> 16u;
+ out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ i += n1;
+
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __SHADD16(T, S);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(coeff, R) >> 16;
+ out2 = __SMUADX(coeff, R);
+#else
+
+ out1 = __SMUADX(R, coeff) >> 16u;
+ out2 = __SMUSD(__QSUB(0, coeff), R);
+
+#endif // #ifndef ARM_MATH_BIG_ENDIAN
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ coeff = _SIMD32_OFFSET(pCoef + (ia * 2u));
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+
+ T = _SIMD32_OFFSET(pSrc + (2 * i));
+
+ S = _SIMD32_OFFSET(pSrc + (2 * l));
+
+ R = __QSUB16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2 * i)) = __QADD16(T, S);
+
+ _SIMD32_OFFSET(pSrc + (2u * l)) = R;
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+#else
+
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q15_t xt, yt, cosVal, sinVal;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
+ pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
+
+ yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
+ pSrc[2 * i + 1] =
+ ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
+
+ pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+ ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+ pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+ ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+ pSrc[2u * l] = (((int16_t) (((q31_t) xt * cosVal) >> 16)) -
+ ((int16_t) (((q31_t) yt * sinVal) >> 16)));
+
+ pSrc[2u * l + 1u] = (((int16_t) (((q31_t) yt * cosVal) >> 16)) +
+ ((int16_t) (((q31_t) xt * sinVal) >> 16)));
+
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ } // groups loop end
+
+
+#endif // #ifndef ARM_MATH_CM0_FAMILY
+
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_q31.c
new file mode 100644
index 000000000..bda6a3906
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix2_q31.c
@@ -0,0 +1,350 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix2_q31.c
+*
+* Description: Radix-2 Decimation in Frequency CFFT & CIFFT Fixed point processing function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix2_butterfly_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_radix2_butterfly_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint16_t twidCoefModifier);
+
+void arm_bitreversal_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Processing function for the fixed-point CFFT/CIFFT.
+* @param[in] *S points to an instance of the fixed-point CFFT/CIFFT structure.
+* @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.
+* @return none.
+*/
+
+void arm_cfft_radix2_q31(
+const arm_cfft_radix2_instance_q31 * S,
+q31_t * pSrc)
+{
+
+ if(S->ifftFlag == 1u)
+ {
+ arm_radix2_butterfly_inverse_q31(pSrc, S->fftLen,
+ S->pTwiddle, S->twidCoefModifier);
+ }
+ else
+ {
+ arm_radix2_butterfly_q31(pSrc, S->fftLen,
+ S->pTwiddle, S->twidCoefModifier);
+ }
+
+ arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+}
+
+/**
+* @} end of ComplexFFT group
+*/
+
+void arm_radix2_butterfly_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+ unsigned i, j, k, l, m;
+ unsigned n1, n2, ia;
+ q31_t xt, yt, cosVal, sinVal;
+ q31_t p0, p1;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
+ pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
+
+ yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
+ pSrc[2 * i + 1] =
+ ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
+
+ mult_32x32_keep32_R(p0, xt, cosVal);
+ mult_32x32_keep32_R(p1, yt, cosVal);
+ multAcc_32x32_keep32_R(p0, yt, sinVal);
+ multSub_32x32_keep32_R(p1, xt, sinVal);
+
+ pSrc[2u * l] = p0;
+ pSrc[2u * l + 1u] = p1;
+
+ } // groups loop end
+
+ twidCoefModifier <<= 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ i = j;
+ m = fftLen / n1;
+ do
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+ mult_32x32_keep32_R(p0, xt, cosVal);
+ mult_32x32_keep32_R(p1, yt, cosVal);
+ multAcc_32x32_keep32_R(p0, yt, sinVal);
+ multSub_32x32_keep32_R(p1, xt, sinVal);
+
+ pSrc[2u * l] = p0;
+ pSrc[2u * l + 1u] = p1;
+ i += n1;
+ m--;
+ } while( m > 0); // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier <<= 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ i += n1;
+ l = i + n2;
+
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ } // butterfly loop end
+
+}
+
+
+void arm_radix2_butterfly_inverse_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+ unsigned i, j, k, l;
+ unsigned n1, n2, ia;
+ q31_t xt, yt, cosVal, sinVal;
+ q31_t p0, p1;
+
+ //N = fftLen;
+ n2 = fftLen;
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (i = 0; i < n2; i++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ l = i + n2;
+ xt = (pSrc[2 * i] >> 2u) - (pSrc[2 * l] >> 2u);
+ pSrc[2 * i] = ((pSrc[2 * i] >> 2u) + (pSrc[2 * l] >> 2u)) >> 1u;
+
+ yt = (pSrc[2 * i + 1] >> 2u) - (pSrc[2 * l + 1] >> 2u);
+ pSrc[2 * i + 1] =
+ ((pSrc[2 * l + 1] >> 2u) + (pSrc[2 * i + 1] >> 2u)) >> 1u;
+
+ mult_32x32_keep32_R(p0, xt, cosVal);
+ mult_32x32_keep32_R(p1, yt, cosVal);
+ multSub_32x32_keep32_R(p0, yt, sinVal);
+ multAcc_32x32_keep32_R(p1, xt, sinVal);
+
+ pSrc[2u * l] = p0;
+ pSrc[2u * l + 1u] = p1;
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+
+ // loop for stage
+ for (k = fftLen / 2; k > 2; k = k >> 1)
+ {
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ // loop for groups
+ for (j = 0; j < n2; j++)
+ {
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = j; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]) >> 1u;
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]) >> 1u;
+
+ mult_32x32_keep32_R(p0, xt, cosVal);
+ mult_32x32_keep32_R(p1, yt, cosVal);
+ multSub_32x32_keep32_R(p0, yt, sinVal);
+ multAcc_32x32_keep32_R(p1, xt, sinVal);
+
+ pSrc[2u * l] = p0;
+ pSrc[2u * l + 1u] = p1;
+ } // butterfly loop end
+
+ } // groups loop end
+
+ twidCoefModifier = twidCoefModifier << 1u;
+ } // stages loop end
+
+ n1 = n2;
+ n2 = n2 >> 1;
+ ia = 0;
+
+ cosVal = pCoef[ia * 2];
+ sinVal = pCoef[(ia * 2) + 1];
+ ia = ia + twidCoefModifier;
+
+ // loop for butterfly
+ for (i = 0; i < fftLen; i += n1)
+ {
+ l = i + n2;
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ i += n1;
+ l = i + n2;
+
+ xt = pSrc[2 * i] - pSrc[2 * l];
+ pSrc[2 * i] = (pSrc[2 * i] + pSrc[2 * l]);
+
+ yt = pSrc[2 * i + 1] - pSrc[2 * l + 1];
+ pSrc[2 * i + 1] = (pSrc[2 * l + 1] + pSrc[2 * i + 1]);
+
+ pSrc[2u * l] = xt;
+
+ pSrc[2u * l + 1u] = yt;
+
+ } // butterfly loop end
+
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_f32.c
new file mode 100644
index 000000000..5acaf768b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_f32.c
@@ -0,0 +1,1210 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_f32.c
+*
+* Description: Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+extern void arm_bitreversal_f32(
+float32_t * pSrc,
+uint16_t fftSize,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab);
+
+/**
+* @ingroup groupTransforms
+*/
+
+/* ----------------------------------------------------------------------
+** Internal helper function used by the FFTs
+** ------------------------------------------------------------------- */
+
+/*
+* @brief Core function for the floating-point CFFT butterfly process.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] *pCoef points to the twiddle coefficient buffer.
+* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+
+void arm_radix4_butterfly_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+
+ float32_t co1, co2, co3, si1, si2, si3;
+ uint32_t ia1, ia2, ia3;
+ uint32_t i0, i1, i2, i3;
+ uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0_FAMILY_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
+ float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
+ Ybminusd;
+ float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
+ float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
+ float32_t *ptr1;
+ float32_t p0,p1,p2,p3,p4,p5;
+ float32_t a0,a1,a2,a3,a4,a5,a6,a7;
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+ i0 = 0u;
+ ia1 = 0u;
+
+ j = n2;
+
+ /* Calculation of first stage */
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ xaIn = pSrc[(2u * i0)];
+ yaIn = pSrc[(2u * i0) + 1u];
+
+ xbIn = pSrc[(2u * i1)];
+ ybIn = pSrc[(2u * i1) + 1u];
+
+ xcIn = pSrc[(2u * i2)];
+ ycIn = pSrc[(2u * i2) + 1u];
+
+ xdIn = pSrc[(2u * i3)];
+ ydIn = pSrc[(2u * i3) + 1u];
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* xb - xd */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* yb - yd */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+ /* (xa - xc) + (yb - yd) */
+ Xb12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yb12C_out = (Yaminusc - Xbminusd);
+ /* (xa + xc) - (xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) - (yb - yd) */
+ Xd12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yd12C_out = (Xbminusd + Yaminusc);
+
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+
+ /* index calculation for the coefficients */
+ ia3 = ia2 + ia1;
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out += p0;
+ Yb12_out -= p1;
+ Xc12_out += p2;
+ Yc12_out -= p3;
+ Xd12_out += p4;
+ Yd12_out -= p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = Yd12_out;
+
+ /* Twiddle coefficients index modifier */
+ ia1 += twidCoefModifier;
+
+ /* Updating input index */
+ i0++;
+
+ }
+ while(--j);
+
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of second stage to excluding last stage */
+ for (k = fftLen >> 2u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* Calculation of first stage */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ia1 += twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ xaIn = pSrc[(2u * i0)];
+ yaIn = pSrc[(2u * i0) + 1u];
+
+ xbIn = pSrc[(2u * i1)];
+ ybIn = pSrc[(2u * i1) + 1u];
+
+ xcIn = pSrc[(2u * i2)];
+ ycIn = pSrc[(2u * i2) + 1u];
+
+ xdIn = pSrc[(2u * i3)];
+ ydIn = pSrc[(2u * i3) + 1u];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* (xb - xd) */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* (yb - yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xa - xc) + (yb - yd) */
+ Xb12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) - (xb - xd) */
+ Yb12C_out = (Yaminusc - Xbminusd);
+ /* xa + xc -(xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) - (yb - yd) */
+ Xd12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yd12C_out = (Xbminusd + Yaminusc);
+
+ pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+ pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out += p0;
+ Yb12_out -= p1;
+ Xc12_out += p2;
+ Yc12_out -= p3;
+ Xd12_out += p4;
+ Yd12_out -= p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = Yd12_out;
+
+ i0 += n1;
+ } while(i0 < fftLen);
+ j++;
+ } while(j <= (n2 - 1u));
+ twidCoefModifier <<= 2u;
+ }
+
+ j = fftLen >> 2;
+ ptr1 = &pSrc[0];
+
+ /* Calculations of last stage */
+ do
+ {
+ xaIn = ptr1[0];
+ yaIn = ptr1[1];
+ xbIn = ptr1[2];
+ ybIn = ptr1[3];
+ xcIn = ptr1[4];
+ ycIn = ptr1[5];
+ xdIn = ptr1[6];
+ ydIn = ptr1[7];
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xb-xd) */
+ Xbminusd = xbIn - xdIn;
+
+ /* (yb-yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = xa + xb + xc + xd */
+ a0 = (Xaplusc + Xbplusd);
+ /* ya' = ya + yb + yc + yd */
+ a1 = (Yaplusc + Ybplusd);
+ /* xc' = (xa-xb+xc-xd) */
+ a2 = (Xaplusc - Xbplusd);
+ /* yc' = (ya-yb+yc-yd) */
+ a3 = (Yaplusc - Ybplusd);
+ /* xb' = (xa+yb-xc-yd) */
+ a4 = (Xaminusc + Ybminusd);
+ /* yb' = (ya-xb-yc+xd) */
+ a5 = (Yaminusc - Xbminusd);
+ /* xd' = (xa-yb-xc+yd)) */
+ a6 = (Xaminusc - Ybminusd);
+ /* yd' = (ya+xb-yc-xd) */
+ a7 = (Xbminusd + Yaminusc);
+
+ ptr1[0] = a0;
+ ptr1[1] = a1;
+ ptr1[2] = a2;
+ ptr1[3] = a3;
+ ptr1[4] = a4;
+ ptr1[5] = a5;
+ ptr1[6] = a6;
+ ptr1[7] = a7;
+
+ /* increment pointer by 8 */
+ ptr1 += 8u;
+ } while(--j);
+
+#else
+
+ float32_t t1, t2, r1, r2, s1, s2;
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializations for the fft calculation */
+ n2 = fftLen;
+ n1 = n2;
+ for (k = fftLen; k > 1u; k >>= 2u)
+ {
+ /* Initializations for the fft calculation */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* FFT Calculation */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* xa + xc */
+ r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+ /* xa - xc */
+ r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xb + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = r1 + t1;
+
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = s1 + t2;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+ /* (xb - xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
+
+ /* (xa - xc) + (yb - yd) */
+ r1 = r2 + t1;
+
+ /* (xa - xc) - (yb - yd) */
+ r2 = r2 - t1;
+
+ /* (ya - yc) - (xb - xd) */
+ s1 = s2 - t2;
+
+ /* (ya - yc) + (xb - xd) */
+ s2 = s2 + t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
+
+ i0 += n1;
+ } while( i0 < fftLen);
+ j++;
+ } while(j <= (n2 - 1u));
+ twidCoefModifier <<= 2u;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */
+
+}
+
+/*
+* @brief Core function for the floating-point CIFFT butterfly process.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] *pCoef points to twiddle coefficient buffer.
+* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @param[in] onebyfftLen value of 1/fftLen.
+* @return none.
+*/
+
+void arm_radix4_butterfly_inverse_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+float32_t * pCoef,
+uint16_t twidCoefModifier,
+float32_t onebyfftLen)
+{
+ float32_t co1, co2, co3, si1, si2, si3;
+ uint32_t ia1, ia2, ia3;
+ uint32_t i0, i1, i2, i3;
+ uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0_FAMILY_FAMILY
+
+ float32_t xaIn, yaIn, xbIn, ybIn, xcIn, ycIn, xdIn, ydIn;
+ float32_t Xaplusc, Xbplusd, Yaplusc, Ybplusd, Xaminusc, Xbminusd, Yaminusc,
+ Ybminusd;
+ float32_t Xb12C_out, Yb12C_out, Xc12C_out, Yc12C_out, Xd12C_out, Yd12C_out;
+ float32_t Xb12_out, Yb12_out, Xc12_out, Yc12_out, Xd12_out, Yd12_out;
+ float32_t *ptr1;
+ float32_t p0,p1,p2,p3,p4,p5,p6,p7;
+ float32_t a0,a1,a2,a3,a4,a5,a6,a7;
+
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+ i0 = 0u;
+ ia1 = 0u;
+
+ j = n2;
+
+ /* Calculation of first stage */
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ xaIn = pSrc[(2u * i0)];
+ yaIn = pSrc[(2u * i0) + 1u];
+
+ xcIn = pSrc[(2u * i2)];
+ ycIn = pSrc[(2u * i2) + 1u];
+
+ xbIn = pSrc[(2u * i1)];
+ ybIn = pSrc[(2u * i1) + 1u];
+
+ xdIn = pSrc[(2u * i3)];
+ ydIn = pSrc[(2u * i3) + 1u];
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* xb - xd */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* yb - yd */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+ /* (xa - xc) - (yb - yd) */
+ Xb12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yb12C_out = (Yaminusc + Xbminusd);
+ /* (xa + xc) - (xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) + (yb - yd) */
+ Xd12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) - (xb - xd) */
+ Yd12C_out = (Yaminusc - Xbminusd);
+
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+
+ /* index calculation for the coefficients */
+ ia3 = ia2 + ia1;
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out -= p0;
+ Yb12_out += p1;
+ Xc12_out -= p2;
+ Yc12_out += p3;
+ Xd12_out -= p4;
+ Yd12_out += p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = Yd12_out;
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of second stage to excluding last stage */
+ for (k = fftLen >> 2u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* Calculation of first stage */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ xaIn = pSrc[(2u * i0)];
+ yaIn = pSrc[(2u * i0) + 1u];
+
+ xbIn = pSrc[(2u * i1)];
+ ybIn = pSrc[(2u * i1) + 1u];
+
+ xcIn = pSrc[(2u * i2)];
+ ycIn = pSrc[(2u * i2) + 1u];
+
+ xdIn = pSrc[(2u * i3)];
+ ydIn = pSrc[(2u * i3) + 1u];
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+ /* (xb - xd) */
+ Xbminusd = xbIn - xdIn;
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+ /* (yb - yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xa - xc) - (yb - yd) */
+ Xb12C_out = (Xaminusc - Ybminusd);
+ /* (ya - yc) + (xb - xd) */
+ Yb12C_out = (Yaminusc + Xbminusd);
+ /* xa + xc -(xb + xd) */
+ Xc12C_out = (Xaplusc - Xbplusd);
+ /* (ya + yc) - (yb + yd) */
+ Yc12C_out = (Yaplusc - Ybplusd);
+ /* (xa - xc) + (yb - yd) */
+ Xd12C_out = (Xaminusc + Ybminusd);
+ /* (ya - yc) - (xb - xd) */
+ Yd12C_out = (Yaminusc - Xbminusd);
+
+ pSrc[(2u * i0)] = Xaplusc + Xbplusd;
+ pSrc[(2u * i0) + 1u] = Yaplusc + Ybplusd;
+
+ Xb12_out = Xb12C_out * co1;
+ Yb12_out = Yb12C_out * co1;
+ Xc12_out = Xc12C_out * co2;
+ Yc12_out = Yc12C_out * co2;
+ Xd12_out = Xd12C_out * co3;
+ Yd12_out = Yd12C_out * co3;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ //Xb12_out -= Yb12C_out * si1;
+ p0 = Yb12C_out * si1;
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ //Yb12_out += Xb12C_out * si1;
+ p1 = Xb12C_out * si1;
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ //Xc12_out -= Yc12C_out * si2;
+ p2 = Yc12C_out * si2;
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ //Yc12_out += Xc12C_out * si2;
+ p3 = Xc12C_out * si2;
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ //Xd12_out -= Yd12C_out * si3;
+ p4 = Yd12C_out * si3;
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ //Yd12_out += Xd12C_out * si3;
+ p5 = Xd12C_out * si3;
+
+ Xb12_out -= p0;
+ Yb12_out += p1;
+ Xc12_out -= p2;
+ Yc12_out += p3;
+ Xd12_out -= p4;
+ Yd12_out += p5;
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = Xc12_out;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = Yc12_out;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = Xb12_out;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = Yb12_out;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = Xd12_out;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = Yd12_out;
+
+ i0 += n1;
+ } while(i0 < fftLen);
+ j++;
+ } while(j <= (n2 - 1u));
+ twidCoefModifier <<= 2u;
+ }
+ /* Initializations of last stage */
+
+ j = fftLen >> 2;
+ ptr1 = &pSrc[0];
+
+ /* Calculations of last stage */
+ do
+ {
+ xaIn = ptr1[0];
+ yaIn = ptr1[1];
+ xbIn = ptr1[2];
+ ybIn = ptr1[3];
+ xcIn = ptr1[4];
+ ycIn = ptr1[5];
+ xdIn = ptr1[6];
+ ydIn = ptr1[7];
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ Xaplusc = xaIn + xcIn;
+
+ /* xa - xc */
+ Xaminusc = xaIn - xcIn;
+
+ /* ya + yc */
+ Yaplusc = yaIn + ycIn;
+
+ /* ya - yc */
+ Yaminusc = yaIn - ycIn;
+
+ /* xb + xd */
+ Xbplusd = xbIn + xdIn;
+
+ /* yb + yd */
+ Ybplusd = ybIn + ydIn;
+
+ /* (xb-xd) */
+ Xbminusd = xbIn - xdIn;
+
+ /* (yb-yd) */
+ Ybminusd = ybIn - ydIn;
+
+ /* xa' = (xa+xb+xc+xd) * onebyfftLen */
+ a0 = (Xaplusc + Xbplusd);
+ /* ya' = (ya+yb+yc+yd) * onebyfftLen */
+ a1 = (Yaplusc + Ybplusd);
+ /* xc' = (xa-xb+xc-xd) * onebyfftLen */
+ a2 = (Xaplusc - Xbplusd);
+ /* yc' = (ya-yb+yc-yd) * onebyfftLen */
+ a3 = (Yaplusc - Ybplusd);
+ /* xb' = (xa-yb-xc+yd) * onebyfftLen */
+ a4 = (Xaminusc - Ybminusd);
+ /* yb' = (ya+xb-yc-xd) * onebyfftLen */
+ a5 = (Yaminusc + Xbminusd);
+ /* xd' = (xa-yb-xc+yd) * onebyfftLen */
+ a6 = (Xaminusc + Ybminusd);
+ /* yd' = (ya-xb-yc+xd) * onebyfftLen */
+ a7 = (Yaminusc - Xbminusd);
+
+ p0 = a0 * onebyfftLen;
+ p1 = a1 * onebyfftLen;
+ p2 = a2 * onebyfftLen;
+ p3 = a3 * onebyfftLen;
+ p4 = a4 * onebyfftLen;
+ p5 = a5 * onebyfftLen;
+ p6 = a6 * onebyfftLen;
+ p7 = a7 * onebyfftLen;
+
+ /* xa' = (xa+xb+xc+xd) * onebyfftLen */
+ ptr1[0] = p0;
+ /* ya' = (ya+yb+yc+yd) * onebyfftLen */
+ ptr1[1] = p1;
+ /* xc' = (xa-xb+xc-xd) * onebyfftLen */
+ ptr1[2] = p2;
+ /* yc' = (ya-yb+yc-yd) * onebyfftLen */
+ ptr1[3] = p3;
+ /* xb' = (xa-yb-xc+yd) * onebyfftLen */
+ ptr1[4] = p4;
+ /* yb' = (ya+xb-yc-xd) * onebyfftLen */
+ ptr1[5] = p5;
+ /* xd' = (xa-yb-xc+yd) * onebyfftLen */
+ ptr1[6] = p6;
+ /* yd' = (ya-xb-yc+xd) * onebyfftLen */
+ ptr1[7] = p7;
+
+ /* increment source pointer by 8 for next calculations */
+ ptr1 = ptr1 + 8u;
+
+ } while(--j);
+
+#else
+
+ float32_t t1, t2, r1, r2, s1, s2;
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* Calculation of first stage */
+ for (k = fftLen; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* Calculation of first stage */
+ j = 0;
+ do
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ i0 = j;
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* xa + xc */
+ r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+ /* xa - xc */
+ r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xb + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = r1 + t1;
+
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = s1 + t2;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+ /* (xb - xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
+
+ /* (xa - xc) - (yb - yd) */
+ r1 = r2 - t1;
+
+ /* (xa - xc) + (yb - yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb - xd) */
+ s1 = s2 + t2;
+
+ /* (ya - yc) - (xb - xd) */
+ s2 = s2 - t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
+
+ i0 += n1;
+ } while( i0 < fftLen);
+ j++;
+ } while(j <= (n2 - 1u));
+ twidCoefModifier <<= 2u;
+ }
+ /* Initializations of last stage */
+ n1 = n2;
+ n2 >>= 2u;
+
+ /* Calculations of last stage */
+ for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = pSrc[2u * i0] + pSrc[2u * i2];
+
+ /* xa - xc */
+ r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xc + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1) * onebyfftLen;
+
+ /* (xa + xb) - (xc + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb-yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+ /* (xb-xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = r1 * onebyfftLen;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;
+
+ /* (xa - xc) - (yb-yd) */
+ r1 = r2 - t1;
+
+ /* (xa - xc) + (yb-yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb-xd) */
+ s1 = s2 + t2;
+
+ /* (ya - yc) - (xb-xd) */
+ s2 = s2 - t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = r1 * onebyfftLen;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = r2 * onebyfftLen;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY_FAMILY */
+}
+
+/**
+* @addtogroup ComplexFFT
+* @{
+*/
+
+/**
+* @details
+* @brief Processing function for the floating-point Radix-4 CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in] *S points to an instance of the floating-point Radix-4 CFFT/CIFFT structure.
+* @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.
+* @return none.
+*/
+
+void arm_cfft_radix4_f32(
+const arm_cfft_radix4_instance_f32 * S,
+float32_t * pSrc)
+{
+
+ if(S->ifftFlag == 1u)
+ {
+ /* Complex IFFT radix-4 */
+ arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier, S->onebyfftLen);
+ }
+ else
+ {
+ /* Complex FFT radix-4 */
+ arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+
+ if(S->bitReverseFlag == 1u)
+ {
+ /* Bit Reversal */
+ arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+ }
+
+}
+
+/**
+* @} end of ComplexFFT group
+*/
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_f32.c
new file mode 100644
index 000000000..18f93f169
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_f32.c
@@ -0,0 +1,165 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_init_f32.c
+*
+* Description: Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+* @brief Initialization function for the floating-point CFFT/CIFFT.
+* @deprecated Do not use this function. It has been superceded by \ref arm_cfft_f32 and will be removed
+* in the future.
+* @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter <code>fftLen</code> Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (float32_t *) twiddleCoef;
+
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLen)
+ {
+
+ case 4096u:
+ /* Initializations of structure parameters for 4096 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.000244140625;
+ break;
+
+ case 1024u:
+ /* Initializations of structure parameters for 1024 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 4u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 4u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+ /* Initialise the 1/fftLen Value */
+ S->onebyfftLen = 0.0009765625f;
+ break;
+
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+ S->onebyfftLen = 0.00390625f;
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+ S->onebyfftLen = 0.015625f;
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+ S->onebyfftLen = 0.0625f;
+ break;
+
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_q15.c
new file mode 100644
index 000000000..10c9fad75
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_q15.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_init_q15.c
+*
+* Description: Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+
+/**
+* @brief Initialization function for the Q15 CFFT/CIFFT.
+* @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter <code>fftLen</code> Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (q15_t *) twiddleCoefQ15;
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLen)
+ {
+ case 4096u:
+ /* Initializations of structure parameters for 4096 point FFT */
+
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+
+ break;
+
+ case 1024u:
+ /* Initializations of structure parameters for 1024 point FFT */
+ S->twidCoefModifier = 4u;
+ S->bitRevFactor = 4u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+
+ break;
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_q31.c
new file mode 100644
index 000000000..8d4e792e6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_init_q31.c
@@ -0,0 +1,147 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_init_q31.c
+*
+* Description: Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+*
+* @brief Initialization function for the Q31 CFFT/CIFFT.
+* @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure.
+* @param[in] fftLen length of the FFT.
+* @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise CFFT is calculated
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter <code>fftLen</code> Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+
+arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+ /* Initialise the FFT length */
+ S->fftLen = fftLen;
+ /* Initialise the Twiddle coefficient pointer */
+ S->pTwiddle = (q31_t *) twiddleCoefQ31;
+ /* Initialise the Flag for selection of CFFT or CIFFT */
+ S->ifftFlag = ifftFlag;
+ /* Initialise the Flag for calculation Bit reversal or not */
+ S->bitReverseFlag = bitReverseFlag;
+
+ /* Initializations of Instance structure depending on the FFT length */
+ switch (S->fftLen)
+ {
+ /* Initializations of structure parameters for 4096 point FFT */
+ case 4096u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 1u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 1u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) armBitRevTable;
+ break;
+
+ /* Initializations of structure parameters for 1024 point FFT */
+ case 1024u:
+ /* Initialise the twiddle coef modifier value */
+ S->twidCoefModifier = 4u;
+ /* Initialise the bit reversal table modifier */
+ S->bitRevFactor = 4u;
+ /* Initialise the bit reversal table pointer */
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+ break;
+
+ case 256u:
+ /* Initializations of structure parameters for 256 point FFT */
+ S->twidCoefModifier = 16u;
+ S->bitRevFactor = 16u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[15];
+ break;
+
+ case 64u:
+ /* Initializations of structure parameters for 64 point FFT */
+ S->twidCoefModifier = 64u;
+ S->bitRevFactor = 64u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[63];
+ break;
+
+ case 16u:
+ /* Initializations of structure parameters for 16 point FFT */
+ S->twidCoefModifier = 256u;
+ S->bitRevFactor = 256u;
+ S->pBitRevTable = (uint16_t *) & armBitRevTable[255];
+ break;
+
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_q15.c
new file mode 100644
index 000000000..567603257
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_q15.c
@@ -0,0 +1,1917 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_q15.c
+*
+* Description: This file has function definition of Radix-4 FFT & IFFT function and
+* In-place bit reversal using bit reversal table
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+
+void arm_radix4_butterfly_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
+void arm_radix4_butterfly_inverse_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
+void arm_bitreversal_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+
+/**
+ * @details
+ * @brief Processing function for the Q15 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+ * @return none.
+ *
+ * \par Input and output formats:
+ * \par
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+ * Hence the output format is different for different FFT sizes.
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:
+ * \par
+ * \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT"
+ * \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT"
+ */
+
+void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc)
+{
+ if(S->ifftFlag == 1u)
+ {
+ /* Complex IFFT radix-4 */
+ arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+ else
+ {
+ /* Complex FFT radix-4 */
+ arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+
+ if(S->bitReverseFlag == 1u)
+ {
+ /* Bit Reversal */
+ arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+ }
+
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
+
+/*
+* Radix-4 FFT algorithm used is :
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 FFT:
+* Wn = co1 + j * (- si1)
+* W2n = co2 + j * (- si2)
+* W3n = co3 + j * (- si3)
+
+* The real and imaginary output values for the radix-4 butterfly are
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)
+*
+*/
+
+/**
+ * @brief Core function for the Q15 CFFT butterfly process.
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_radix4_butterfly_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t R, S, T, U;
+ q31_t C1, C2, C3, out1, out2;
+ uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+ q15_t in;
+
+ q15_t *ptr1;
+
+
+
+ q31_t xaya, xbyb, xcyc, xdyd;
+
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+
+ /* Index for twiddle coefficient */
+ ic = 0u;
+
+ /* Index for input read and output write */
+ i0 = 0u;
+ j = n2;
+
+ /* Input is in 1.15(q15) format */
+
+ /* start of first stage process */
+ do
+ {
+ /* Butterfly implementation */
+
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* Read yc (real), xc(imag) input */
+ S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
+ in = ((int16_t) (S & 0xFFFF)) >> 2;
+ S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* R = packed((ya + yc), (xa + xc) ) */
+ R = __QADD16(T, S);
+
+ /* S = packed((ya - yc), (xa - xc) ) */
+ S = __QSUB16(T, S);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+ in = ((int16_t) (U & 0xFFFF)) >> 2;
+ U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* T = packed((yb + yd), (xb + xd) ) */
+ T = __QADD16(T, U);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ _SIMD32_OFFSET(pSrc16 + (2u * i0)) = __SHADD16(R, T);
+
+ /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+ R = __QSUB16(R, T);
+
+ /* co2 & si2 are read from SIMD Coefficient pointer */
+ C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out1 = __SMUAD(C2, R) >> 16u;
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = __SMUSDX(C2, R);
+
+#else
+
+ /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out1 = __SMUSDX(R, C2) >> 16u;
+ /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out2 = __SMUAD(C2, R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Reading i0+fftLen/4 */
+ /* T = packed(yb, xb) */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* writing output(xc', yc') in little endian format */
+ _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Butterfly calculations */
+ /* U = packed(yd, xd) */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+ in = ((int16_t) (U & 0xFFFF)) >> 2;
+ U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* T = packed(yb-yd, xb-xd) */
+ T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __QASX(S, T);
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __QSAX(S, T);
+
+#else
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __QSAX(S, T);
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __QASX(S, T);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* co1 & si1 are read from SIMD Coefficient pointer */
+ C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+ /* Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out1 = __SMUAD(C1, S) >> 16u;
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out2 = __SMUSDX(C1, S);
+
+#else
+
+ /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out1 = __SMUSDX(S, C1) >> 16u;
+ /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out2 = __SMUAD(C1, S);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* writing output(xb', yb') in little endian format */
+ _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
+ ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+
+
+ /* co3 & si3 are read from SIMD Coefficient pointer */
+ C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+ /* Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ out1 = __SMUAD(C3, R) >> 16u;
+ /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ out2 = __SMUSDX(C3, R);
+
+#else
+
+ /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ out1 = __SMUSDX(R, C3) >> 16u;
+ /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ out2 = __SMUAD(C3, R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* writing output(xd', yd') in little endian format */
+ _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+ /* data is in 4.11(q11) format */
+
+ /* end of first stage process */
+
+
+ /* start of middle stage process */
+
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of Middle stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the middle stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ic = 0u;
+
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+ C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+ C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Butterfly implementation */
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
+
+ /* Read yc (real), xc(imag) input */
+ S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
+
+ /* R = packed( (ya + yc), (xa + xc)) */
+ R = __QADD16(T, S);
+
+ /* S = packed((ya - yc), (xa - xc)) */
+ S = __QSUB16(T, S);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+
+ /* T = packed( (yb + yd), (xb + xd)) */
+ T = __QADD16(T, U);
+
+ /* writing the butterfly processed i0 sample */
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ out1 = __SHADD16(R, T);
+ in = ((int16_t) (out1 & 0xFFFF)) >> 1;
+ out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+ _SIMD32_OFFSET(pSrc16 + (2u * i0)) = out1;
+
+ /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+ R = __SHSUB16(R, T);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out1 = __SMUAD(C2, R) >> 16u;
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = __SMUSDX(C2, R);
+
+#else
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out1 = __SMUSDX(R, C2) >> 16u;
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out2 = __SMUAD(C2, R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Reading i0+3fftLen/4 */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Butterfly calculations */
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+
+ /* T = packed(yb-yd, xb-xd) */
+ T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __SHASX(S, T);
+
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __SHSAX(S, T);
+
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = __SMUAD(C1, S) >> 16u;
+ out2 = __SMUSDX(C1, S);
+
+#else
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __SHSAX(S, T);
+
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __SHASX(S, T);
+
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = __SMUSDX(S, C1) >> 16u;
+ out2 = __SMUAD(C1, S);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUAD(C3, R) >> 16u;
+ out2 = __SMUSDX(C3, R);
+
+#else
+
+ out1 = __SMUSDX(R, C3) >> 16u;
+ out2 = __SMUAD(C3, R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ }
+ }
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+ }
+ /* end of middle stage process */
+
+
+ /* data is in 10.6(q6) format for the 1024 point */
+ /* data is in 8.8(q8) format for the 256 point */
+ /* data is in 6.10(q10) format for the 64 point */
+ /* data is in 4.12(q12) format for the 16 point */
+
+ /* Initializations for the last stage */
+ j = fftLen >> 2;
+
+ ptr1 = &pSrc16[0];
+
+ /* start of last stage process */
+
+ /* Butterfly implementation */
+ do
+ {
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD32(ptr1)++;
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD32(ptr1)++;
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD32(ptr1)++;
+
+ /* Read xd (real), yd(imag) input */
+ xdyd = *__SIMD32(ptr1)++;
+
+ /* R = packed((ya + yc), (xa + xc)) */
+ R = __QADD16(xaya, xcyc);
+
+ /* T = packed((yb + yd), (xb + xd)) */
+ T = __QADD16(xbyb, xdyd);
+
+ /* pointer updation for writing */
+ ptr1 = ptr1 - 8u;
+
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ *__SIMD32(ptr1)++ = __SHADD16(R, T);
+
+ /* T = packed((yb + yd), (xb + xd)) */
+ T = __QADD16(xbyb, xdyd);
+
+ /* xc' = (xa-xb+xc-xd) */
+ /* yc' = (ya-yb+yc-yd) */
+ *__SIMD32(ptr1)++ = __SHSUB16(R, T);
+
+ /* S = packed((ya - yc), (xa - xc)) */
+ S = __QSUB16(xaya, xcyc);
+
+ /* Read yd (real), xd(imag) input */
+ /* T = packed( (yb - yd), (xb - xd)) */
+ U = __QSUB16(xbyb, xdyd);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+#else
+
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ } while(--j);
+
+ /* end of last stage process */
+
+ /* output is in 11.5(q5) format for the 1024 point */
+ /* output is in 9.7(q7) format for the 256 point */
+ /* output is in 7.9(q9) format for the 64 point */
+ /* output is in 5.11(q11) format for the 16 point */
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+ q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+ uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+
+ /* Index for twiddle coefficient */
+ ic = 0u;
+
+ /* Index for input read and output write */
+ i0 = 0u;
+ j = n2;
+
+ /* Input is in 1.15(q15) format */
+
+ /* start of first stage process */
+ do
+ {
+ /* Butterfly implementation */
+
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+
+ /* input is down scale by 4 to avoid overflow */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u] >> 2u;
+ T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u] >> 2u;
+ S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+ /* R0 = (ya + yc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ /* R1 = (xa + xc) */
+ R1 = __SSAT(T1 + S1, 16u);
+
+ /* S0 = (ya - yc) */
+ S0 = __SSAT(T0 - S0, 16);
+ /* S1 = (xa - xc) */
+ S1 = __SSAT(T1 - S1, 16);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u] >> 2u;
+ T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u] >> 2u;
+ U1 = pSrc16[(i3 * 2u) + 1] >> 2u;
+
+ /* T0 = (yb + yd) */
+ T0 = __SSAT(T0 + U0, 16u);
+ /* T1 = (xb + xd) */
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* ya' = ya + yb + yc + yd */
+ /* xa' = xa + xb + xc + xd */
+ pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+ pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+ /* R0 = (ya + yc) - (yb + yd) */
+ /* R1 = (xa + xc) - (xb + xd) */
+ R0 = __SSAT(R0 - T0, 16u);
+ R1 = __SSAT(R1 - T1, 16u);
+
+ /* co2 & si2 are read from Coefficient pointer */
+ Co2 = pCoef16[2u * ic * 2u];
+ Si2 = pCoef16[(2u * ic * 2u) + 1];
+
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+ /* Reading i0+fftLen/4 */
+ /* input is down scale by 4 to avoid overflow */
+ /* T0 = yb, T1 = xb */
+ T0 = pSrc16[i1 * 2u] >> 2;
+ T1 = pSrc16[(i1 * 2u) + 1] >> 2;
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* writing output(xc', yc') in little endian format */
+ pSrc16[i1 * 2u] = out1;
+ pSrc16[(i1 * 2u) + 1] = out2;
+
+ /* Butterfly calculations */
+ /* input is down scale by 4 to avoid overflow */
+ /* U0 = yd, U1 = xd */
+ U0 = pSrc16[i3 * 2u] >> 2;
+ U1 = pSrc16[(i3 * 2u) + 1] >> 2;
+ /* T0 = yb-yd */
+ T0 = __SSAT(T0 - U0, 16);
+ /* T1 = xb-xd */
+ T1 = __SSAT(T1 - U1, 16);
+
+ /* R1 = (ya-yc) + (xb- xd), R0 = (xa-xc) - (yb-yd)) */
+ R0 = (short) __SSAT((q31_t) (S0 - T1), 16);
+ R1 = (short) __SSAT((q31_t) (S1 + T0), 16);
+
+ /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */
+ S0 = (short) __SSAT(((q31_t) S0 + T1), 16u);
+ S1 = (short) __SSAT(((q31_t) S1 - T0), 16u);
+
+ /* co1 & si1 are read from Coefficient pointer */
+ Co1 = pCoef16[ic * 2u];
+ Si1 = pCoef16[(ic * 2u) + 1];
+ /* Butterfly process for the i0+fftLen/2 sample */
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out1 = (short) ((Si1 * S1 + Co1 * S0) >> 16);
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16);
+
+ /* writing output(xb', yb') in little endian format */
+ pSrc16[i2 * 2u] = out1;
+ pSrc16[(i2 * 2u) + 1] = out2;
+
+ /* Co3 & si3 are read from Coefficient pointer */
+ Co3 = pCoef16[3u * (ic * 2u)];
+ Si3 = pCoef16[(3u * (ic * 2u)) + 1];
+ /* Butterfly process for the i0+3fftLen/4 sample */
+ /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+ out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);
+ /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+ out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);
+ /* writing output(xd', yd') in little endian format */
+ pSrc16[i3 * 2u] = out1;
+ pSrc16[(i3 * 2u) + 1] = out2;
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+ /* data is in 4.11(q11) format */
+
+ /* end of first stage process */
+
+
+ /* start of middle stage process */
+
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of Middle stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the middle stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ic = 0u;
+
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ Co1 = pCoef16[ic * 2u];
+ Si1 = pCoef16[(ic * 2u) + 1u];
+ Co2 = pCoef16[2u * (ic * 2u)];
+ Si2 = pCoef16[(2u * (ic * 2u)) + 1u];
+ Co3 = pCoef16[3u * (ic * 2u)];
+ Si3 = pCoef16[(3u * (ic * 2u)) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Butterfly implementation */
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u];
+ T1 = pSrc16[(i0 * 2u) + 1u];
+
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u];
+ S1 = pSrc16[(i2 * 2u) + 1u];
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16);
+ R1 = __SSAT(T1 + S1, 16);
+
+ /* S0 = (ya - yc), S1 =(xa - xc) */
+ S0 = __SSAT(T0 - S0, 16);
+ S1 = __SSAT(T1 - S1, 16);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+
+ /* T0 = (yb + yd), T1 = (xb + xd) */
+ T0 = __SSAT(T0 + U0, 16);
+ T1 = __SSAT(T1 + U1, 16);
+
+ /* writing the butterfly processed i0 sample */
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ out1 = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+ out2 = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+ pSrc16[i0 * 2u] = out1;
+ pSrc16[(2u * i0) + 1u] = out2;
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+ R0 = (R0 >> 1u) - (T0 >> 1u);
+ R1 = (R1 >> 1u) - (T1 >> 1u);
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+ /* Reading i0+3fftLen/4 */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ pSrc16[i1 * 2u] = out1;
+ pSrc16[(i1 * 2u) + 1u] = out2;
+
+ /* Butterfly calculations */
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = yb-yd, T1 = xb-xd */
+ T0 = __SSAT(T0 - U0, 16);
+ T1 = __SSAT(T1 - U1, 16);
+
+ /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */
+ R0 = (S0 >> 1u) - (T1 >> 1u);
+ R1 = (S1 >> 1u) + (T0 >> 1u);
+
+ /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */
+ S0 = (S0 >> 1u) + (T1 >> 1u);
+ S1 = (S1 >> 1u) - (T0 >> 1u);
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = (short) ((Co1 * S0 + Si1 * S1) >> 16u);
+
+ out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16u);
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ pSrc16[i2 * 2u] = out1;
+ pSrc16[(i2 * 2u) + 1u] = out2;
+
+ /* Butterfly process for the i0+3fftLen/4 sample */
+ out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);
+
+ out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);
+ /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+ /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+ pSrc16[i3 * 2u] = out1;
+ pSrc16[(i3 * 2u) + 1u] = out2;
+ }
+ }
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+ }
+ /* end of middle stage process */
+
+
+ /* data is in 10.6(q6) format for the 1024 point */
+ /* data is in 8.8(q8) format for the 256 point */
+ /* data is in 6.10(q10) format for the 64 point */
+ /* data is in 4.12(q12) format for the 16 point */
+
+ /* Initializations for the last stage */
+ n1 = n2;
+ n2 >>= 2u;
+
+ /* start of last stage process */
+
+ /* Butterfly implementation */
+ for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u];
+ T1 = pSrc16[(i0 * 2u) + 1u];
+
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u];
+ S1 = pSrc16[(i2 * 2u) + 1u];
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ R1 = __SSAT(T1 + S1, 16u);
+
+ /* S0 = (ya - yc), S1 = (xa - xc) */
+ S0 = __SSAT(T0 - S0, 16u);
+ S1 = __SSAT(T1 - S1, 16u);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = (yb + yd), T1 = (xb + xd)) */
+ T0 = __SSAT(T0 + U0, 16u);
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+ pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+ R0 = (R0 >> 1u) - (T0 >> 1u);
+ R1 = (R1 >> 1u) - (T1 >> 1u);
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd) */
+ /* yc' = (ya-yb+yc-yd) */
+ pSrc16[i1 * 2u] = R0;
+ pSrc16[(i1 * 2u) + 1u] = R1;
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+ /* T0 = (yb - yd), T1 = (xb - xd) */
+ T0 = __SSAT(T0 - U0, 16u);
+ T1 = __SSAT(T1 - U1, 16u);
+
+ /* writing the butterfly processed i0 + fftLen/2 sample */
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ pSrc16[i2 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+ pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+
+ /* writing the butterfly processed i0 + 3fftLen/4 sample */
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ pSrc16[i3 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+ pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+ }
+
+ /* end of last stage process */
+
+ /* output is in 11.5(q5) format for the 1024 point */
+ /* output is in 9.7(q7) format for the 256 point */
+ /* output is in 7.9(q9) format for the 64 point */
+ /* output is in 5.11(q11) format for the 16 point */
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+/**
+ * @brief Core function for the Q15 CIFFT butterfly process.
+ * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef16 points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+/*
+* Radix-4 IFFT algorithm used is :
+*
+* CIFFT uses same twiddle coefficients as CFFT function
+* x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]
+*
+*
+* IFFT is implemented with following changes in equations from FFT
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 IFFT:
+* Wn = co1 + j * (si1)
+* W2n = co2 + j * (si2)
+* W3n = co3 + j * (si3)
+
+* The real and imaginary output values for the radix-4 butterfly are
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)
+*
+*/
+
+void arm_radix4_butterfly_inverse_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ q31_t R, S, T, U;
+ q31_t C1, C2, C3, out1, out2;
+ uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+ q15_t in;
+
+ q15_t *ptr1;
+
+
+
+ q31_t xaya, xbyb, xcyc, xdyd;
+
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+
+ /* Index for twiddle coefficient */
+ ic = 0u;
+
+ /* Index for input read and output write */
+ i0 = 0u;
+ j = n2;
+
+ /* Input is in 1.15(q15) format */
+
+ /* start of first stage process */
+ do
+ {
+ /* Butterfly implementation */
+
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* Read yc (real), xc(imag) input */
+ S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
+ in = ((int16_t) (S & 0xFFFF)) >> 2;
+ S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* R = packed((ya + yc), (xa + xc) ) */
+ R = __QADD16(T, S);
+
+ /* S = packed((ya - yc), (xa - xc) ) */
+ S = __QSUB16(T, S);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+ in = ((int16_t) (U & 0xFFFF)) >> 2;
+ U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* T = packed((yb + yd), (xb + xd) ) */
+ T = __QADD16(T, U);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ _SIMD32_OFFSET(pSrc16 + (2u * i0)) = __SHADD16(R, T);
+
+ /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+ R = __QSUB16(R, T);
+
+ /* co2 & si2 are read from SIMD Coefficient pointer */
+ C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out1 = __SMUSD(C2, R) >> 16u;
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = __SMUADX(C2, R);
+
+#else
+
+ /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out1 = __SMUADX(C2, R) >> 16u;
+ /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ out2 = __SMUSD(__QSUB16(0, C2), R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Reading i0+fftLen/4 */
+ /* T = packed(yb, xb) */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+ in = ((int16_t) (T & 0xFFFF)) >> 2;
+ T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* writing output(xc', yc') in little endian format */
+ _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
+ (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Butterfly calculations */
+ /* U = packed(yd, xd) */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+ in = ((int16_t) (U & 0xFFFF)) >> 2;
+ U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+ /* T = packed(yb-yd, xb-xd) */
+ T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __QSAX(S, T);
+ /* S = packed((ya-yc) + (xb- xd), (xa-xc) - (yb-yd)) */
+ S = __QASX(S, T);
+
+#else
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __QASX(S, T);
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __QSAX(S, T);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* co1 & si1 are read from SIMD Coefficient pointer */
+ C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+ /* Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out1 = __SMUSD(C1, S) >> 16u;
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out2 = __SMUADX(C1, S);
+
+#else
+
+ /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ out1 = __SMUADX(C1, S) >> 16u;
+ /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ out2 = __SMUSD(__QSUB16(0, C1), S);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* writing output(xb', yb') in little endian format */
+ _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
+ ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+
+
+ /* co3 & si3 are read from SIMD Coefficient pointer */
+ C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+ /* Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ out1 = __SMUSD(C3, R) >> 16u;
+ /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ out2 = __SMUADX(C3, R);
+
+#else
+
+ /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ out1 = __SMUADX(C3, R) >> 16u;
+ /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ out2 = __SMUSD(__QSUB16(0, C3), R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* writing output(xd', yd') in little endian format */
+ _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+ /* data is in 4.11(q11) format */
+
+ /* end of first stage process */
+
+
+ /* start of middle stage process */
+
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of Middle stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the middle stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ic = 0u;
+
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ C1 = _SIMD32_OFFSET(pCoef16 + (2u * ic));
+ C2 = _SIMD32_OFFSET(pCoef16 + (4u * ic));
+ C3 = _SIMD32_OFFSET(pCoef16 + (6u * ic));
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Butterfly implementation */
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i0));
+
+ /* Read yc (real), xc(imag) input */
+ S = _SIMD32_OFFSET(pSrc16 + (2u * i2));
+
+ /* R = packed( (ya + yc), (xa + xc)) */
+ R = __QADD16(T, S);
+
+ /* S = packed((ya - yc), (xa - xc)) */
+ S = __QSUB16(T, S);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+
+ /* T = packed( (yb + yd), (xb + xd)) */
+ T = __QADD16(T, U);
+
+ /* writing the butterfly processed i0 sample */
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ out1 = __SHADD16(R, T);
+ in = ((int16_t) (out1 & 0xFFFF)) >> 1;
+ out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+ _SIMD32_OFFSET(pSrc16 + (2u * i0)) = out1;
+
+ /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+ R = __SHSUB16(R, T);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out1 = __SMUSD(C2, R) >> 16u;
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out2 = __SMUADX(C2, R);
+
+#else
+
+ /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ out1 = __SMUADX(R, C2) >> 16u;
+
+ /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+ out2 = __SMUSD(__QSUB16(0, C2), R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* Reading i0+3fftLen/4 */
+ /* Read yb (real), xb(imag) input */
+ T = _SIMD32_OFFSET(pSrc16 + (2u * i1));
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+ /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+ _SIMD32_OFFSET(pSrc16 + (2u * i1)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Butterfly calculations */
+
+ /* Read yd (real), xd(imag) input */
+ U = _SIMD32_OFFSET(pSrc16 + (2u * i3));
+
+ /* T = packed(yb-yd, xb-xd) */
+ T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __SHSAX(S, T);
+
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __SHASX(S, T);
+
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = __SMUSD(C1, S) >> 16u;
+ out2 = __SMUADX(C1, S);
+
+#else
+
+ /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+ R = __SHASX(S, T);
+
+ /* S = packed((ya-yc) - (xb- xd), (xa-xc) + (yb-yd)) */
+ S = __SHSAX(S, T);
+
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = __SMUADX(S, C1) >> 16u;
+ out2 = __SMUSD(__QSUB16(0, C1), S);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+ /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+ _SIMD32_OFFSET(pSrc16 + (2u * i2)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+ /* Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ out1 = __SMUSD(C3, R) >> 16u;
+ out2 = __SMUADX(C3, R);
+
+#else
+
+ out1 = __SMUADX(C3, R) >> 16u;
+ out2 = __SMUSD(__QSUB16(0, C3), R);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+ /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+ _SIMD32_OFFSET(pSrc16 + (2u * i3)) =
+ ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+ }
+ }
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+ }
+ /* end of middle stage process */
+
+ /* data is in 10.6(q6) format for the 1024 point */
+ /* data is in 8.8(q8) format for the 256 point */
+ /* data is in 6.10(q10) format for the 64 point */
+ /* data is in 4.12(q12) format for the 16 point */
+
+ /* Initializations for the last stage */
+ j = fftLen >> 2;
+
+ ptr1 = &pSrc16[0];
+
+ /* start of last stage process */
+
+ /* Butterfly implementation */
+ do
+ {
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD32(ptr1)++;
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD32(ptr1)++;
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD32(ptr1)++;
+
+ /* Read xd (real), yd(imag) input */
+ xdyd = *__SIMD32(ptr1)++;
+
+ /* R = packed((ya + yc), (xa + xc)) */
+ R = __QADD16(xaya, xcyc);
+
+ /* T = packed((yb + yd), (xb + xd)) */
+ T = __QADD16(xbyb, xdyd);
+
+ /* pointer updation for writing */
+ ptr1 = ptr1 - 8u;
+
+
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ *__SIMD32(ptr1)++ = __SHADD16(R, T);
+
+ /* T = packed((yb + yd), (xb + xd)) */
+ T = __QADD16(xbyb, xdyd);
+
+ /* xc' = (xa-xb+xc-xd) */
+ /* yc' = (ya-yb+yc-yd) */
+ *__SIMD32(ptr1)++ = __SHSUB16(R, T);
+
+ /* S = packed((ya - yc), (xa - xc)) */
+ S = __QSUB16(xaya, xcyc);
+
+ /* Read yd (real), xd(imag) input */
+ /* T = packed( (yb - yd), (xb - xd)) */
+ U = __QSUB16(xbyb, xdyd);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+#else
+
+ /* xb' = (xa+yb-xc-yd) */
+ /* yb' = (ya-xb-yc+xd) */
+ *__SIMD32(ptr1)++ = __SHSAX(S, U);
+
+
+ /* xd' = (xa-yb-xc+yd) */
+ /* yd' = (ya+xb-yc-xd) */
+ *__SIMD32(ptr1)++ = __SHASX(S, U);
+
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ } while(--j);
+
+ /* end of last stage process */
+
+ /* output is in 11.5(q5) format for the 1024 point */
+ /* output is in 9.7(q7) format for the 256 point */
+ /* output is in 7.9(q9) format for the 64 point */
+ /* output is in 5.11(q11) format for the 16 point */
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+ q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+ uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+
+ /* Index for twiddle coefficient */
+ ic = 0u;
+
+ /* Index for input read and output write */
+ i0 = 0u;
+
+ j = n2;
+
+ /* Input is in 1.15(q15) format */
+
+ /* Start of first stage process */
+ do
+ {
+ /* Butterfly implementation */
+
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* input is down scale by 4 to avoid overflow */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u] >> 2u;
+ T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u] >> 2u;
+ S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ R1 = __SSAT(T1 + S1, 16u);
+ /* S0 = (ya - yc), S1 = (xa - xc) */
+ S0 = __SSAT(T0 - S0, 16u);
+ S1 = __SSAT(T1 - S1, 16u);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* input is down scale by 4 to avoid overflow */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u] >> 2u;
+ T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+ /* Read yd (real), xd(imag) input */
+ /* input is down scale by 4 to avoid overflow */
+ U0 = pSrc16[i3 * 2u] >> 2u;
+ U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+ /* T0 = (yb + yd), T1 = (xb + xd) */
+ T0 = __SSAT(T0 + U0, 16u);
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+ pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */
+ R0 = __SSAT(R0 - T0, 16u);
+ R1 = __SSAT(R1 - T1, 16u);
+ /* co2 & si2 are read from Coefficient pointer */
+ Co2 = pCoef16[2u * ic * 2u];
+ Si2 = pCoef16[(2u * ic * 2u) + 1u];
+ /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+ out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16u);
+ /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+ out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16u);
+
+ /* Reading i0+fftLen/4 */
+ /* input is down scale by 4 to avoid overflow */
+ /* T0 = yb, T1 = xb */
+ T0 = pSrc16[i1 * 2u] >> 2u;
+ T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* writing output(xc', yc') in little endian format */
+ pSrc16[i1 * 2u] = out1;
+ pSrc16[(i1 * 2u) + 1u] = out2;
+
+ /* Butterfly calculations */
+ /* input is down scale by 4 to avoid overflow */
+ /* U0 = yd, U1 = xd) */
+ U0 = pSrc16[i3 * 2u] >> 2u;
+ U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+ /* T0 = yb-yd, T1 = xb-xd) */
+ T0 = __SSAT(T0 - U0, 16u);
+ T1 = __SSAT(T1 - U1, 16u);
+ /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+ R0 = (short) __SSAT((q31_t) (S0 + T1), 16);
+ R1 = (short) __SSAT((q31_t) (S1 - T0), 16);
+ /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+ S0 = (short) __SSAT((q31_t) (S0 - T1), 16);
+ S1 = (short) __SSAT((q31_t) (S1 + T0), 16);
+
+ /* co1 & si1 are read from Coefficient pointer */
+ Co1 = pCoef16[ic * 2u];
+ Si1 = pCoef16[(ic * 2u) + 1u];
+ /* Butterfly process for the i0+fftLen/2 sample */
+ /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+ out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);
+ /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+ out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);
+ /* writing output(xb', yb') in little endian format */
+ pSrc16[i2 * 2u] = out1;
+ pSrc16[(i2 * 2u) + 1u] = out2;
+
+ /* Co3 & si3 are read from Coefficient pointer */
+ Co3 = pCoef16[3u * ic * 2u];
+ Si3 = pCoef16[(3u * ic * 2u) + 1u];
+ /* Butterfly process for the i0+3fftLen/4 sample */
+ /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+ out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);
+ /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+ out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);
+ /* writing output(xd', yd') in little endian format */
+ pSrc16[i3 * 2u] = out1;
+ pSrc16[(i3 * 2u) + 1u] = out2;
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+
+ /* End of first stage process */
+
+ /* data is in 4.11(q11) format */
+
+
+ /* Start of Middle stage process */
+
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of Middle stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the middle stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ic = 0u;
+
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ Co1 = pCoef16[ic * 2u];
+ Si1 = pCoef16[(ic * 2u) + 1u];
+ Co2 = pCoef16[2u * ic * 2u];
+ Si2 = pCoef16[2u * ic * 2u + 1u];
+ Co3 = pCoef16[3u * ic * 2u];
+ Si3 = pCoef16[(3u * ic * 2u) + 1u];
+
+ /* Twiddle coefficients index modifier */
+ ic = ic + twidCoefModifier;
+
+ /* Butterfly implementation */
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u];
+ T1 = pSrc16[(i0 * 2u) + 1u];
+
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u];
+ S1 = pSrc16[(i2 * 2u) + 1u];
+
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ R1 = __SSAT(T1 + S1, 16u);
+ /* S0 = (ya - yc), S1 = (xa - xc) */
+ S0 = __SSAT(T0 - S0, 16u);
+ S1 = __SSAT(T1 - S1, 16u);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = (yb + yd), T1 = (xb + xd) */
+ T0 = __SSAT(T0 + U0, 16u);
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ pSrc16[i0 * 2u] = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+ pSrc16[(i0 * 2u) + 1u] = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+ R0 = (R0 >> 1u) - (T0 >> 1u);
+ R1 = (R1 >> 1u) - (T1 >> 1u);
+
+ /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+ out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16);
+ /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+ out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16);
+
+ /* Reading i0+3fftLen/4 */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+ /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+ pSrc16[i1 * 2u] = out1;
+ pSrc16[(i1 * 2u) + 1u] = out2;
+
+ /* Butterfly calculations */
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = yb-yd, T1 = xb-xd) */
+ T0 = __SSAT(T0 - U0, 16u);
+ T1 = __SSAT(T1 - U1, 16u);
+
+ /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+ R0 = (S0 >> 1u) + (T1 >> 1u);
+ R1 = (S1 >> 1u) - (T0 >> 1u);
+
+ /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+ S0 = (S0 >> 1u) - (T1 >> 1u);
+ S1 = (S1 >> 1u) + (T0 >> 1u);
+
+ /* Butterfly process for the i0+fftLen/2 sample */
+ out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);
+ out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);
+ /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+ /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+ pSrc16[i2 * 2u] = out1;
+ pSrc16[(i2 * 2u) + 1u] = out2;
+
+ /* Butterfly process for the i0+3fftLen/4 sample */
+ out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);
+
+ out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);
+ /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+ /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+ pSrc16[i3 * 2u] = out1;
+ pSrc16[(i3 * 2u) + 1u] = out2;
+
+
+ }
+ }
+ /* Twiddle coefficients index modifier */
+ twidCoefModifier <<= 2u;
+ }
+ /* End of Middle stages process */
+
+
+ /* data is in 10.6(q6) format for the 1024 point */
+ /* data is in 8.8(q8) format for the 256 point */
+ /* data is in 6.10(q10) format for the 64 point */
+ /* data is in 4.12(q12) format for the 16 point */
+
+ /* start of last stage process */
+
+
+ /* Initializations for the last stage */
+ n1 = n2;
+ n2 >>= 2u;
+
+ /* Butterfly implementation */
+ for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Reading i0, i0+fftLen/2 inputs */
+ /* Read ya (real), xa(imag) input */
+ T0 = pSrc16[i0 * 2u];
+ T1 = pSrc16[(i0 * 2u) + 1u];
+ /* Read yc (real), xc(imag) input */
+ S0 = pSrc16[i2 * 2u];
+ S1 = pSrc16[(i2 * 2u) + 1u];
+
+ /* R0 = (ya + yc), R1 = (xa + xc) */
+ R0 = __SSAT(T0 + S0, 16u);
+ R1 = __SSAT(T1 + S1, 16u);
+ /* S0 = (ya - yc), S1 = (xa - xc) */
+ S0 = __SSAT(T0 - S0, 16u);
+ S1 = __SSAT(T1 - S1, 16u);
+
+ /* Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+
+ /* T0 = (yb + yd), T1 = (xb + xd) */
+ T0 = __SSAT(T0 + U0, 16u);
+ T1 = __SSAT(T1 + U1, 16u);
+
+ /* writing the butterfly processed i0 sample */
+ /* xa' = xa + xb + xc + xd */
+ /* ya' = ya + yb + yc + yd */
+ pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+ pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+ /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+ R0 = (R0 >> 1u) - (T0 >> 1u);
+ R1 = (R1 >> 1u) - (T1 >> 1u);
+
+ /* Read yb (real), xb(imag) input */
+ T0 = pSrc16[i1 * 2u];
+ T1 = pSrc16[(i1 * 2u) + 1u];
+
+ /* writing the butterfly processed i0 + fftLen/4 sample */
+ /* xc' = (xa-xb+xc-xd) */
+ /* yc' = (ya-yb+yc-yd) */
+ pSrc16[i1 * 2u] = R0;
+ pSrc16[(i1 * 2u) + 1u] = R1;
+
+ /* Read yd (real), xd(imag) input */
+ U0 = pSrc16[i3 * 2u];
+ U1 = pSrc16[(i3 * 2u) + 1u];
+ /* T0 = (yb - yd), T1 = (xb - xd) */
+ T0 = __SSAT(T0 - U0, 16u);
+ T1 = __SSAT(T1 - U1, 16u);
+
+ /* writing the butterfly processed i0 + fftLen/2 sample */
+ /* xb' = (xa-yb-xc+yd) */
+ /* yb' = (ya+xb-yc-xd) */
+ pSrc16[i2 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+ pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+
+ /* writing the butterfly processed i0 + 3fftLen/4 sample */
+ /* xd' = (xa+yb-xc-yd) */
+ /* yd' = (ya-xb-yc+xd) */
+ pSrc16[i3 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+ pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+ }
+ /* end of last stage process */
+
+ /* output is in 11.5(q5) format for the 1024 point */
+ /* output is in 9.7(q7) format for the 256 point */
+ /* output is in 7.9(q9) format for the 64 point */
+ /* output is in 5.11(q11) format for the 16 point */
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_q31.c
new file mode 100644
index 000000000..b56a0e082
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix4_q31.c
@@ -0,0 +1,911 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix4_q31.c
+*
+* Description: This file has function definition of Radix-4 FFT & IFFT function and
+* In-place bit reversal using bit reversal table
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix4_butterfly_inverse_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint32_t twidCoefModifier);
+
+void arm_radix4_butterfly_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint32_t twidCoefModifier);
+
+void arm_bitreversal_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup ComplexFFT
+ * @{
+ */
+
+/**
+ * @details
+ * @brief Processing function for the Q31 CFFT/CIFFT.
+ * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure.
+ * @param[in, out] *pSrc points to the complex data buffer of size <code>2*fftLen</code>. Processing occurs in-place.
+ * @return none.
+ *
+ * \par Input and output formats:
+ * \par
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+ * Hence the output format is different for different FFT sizes.
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:
+ * \par
+ * \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT"
+ * \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT"
+ *
+ */
+
+void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc)
+{
+ if(S->ifftFlag == 1u)
+ {
+ /* Complex IFFT radix-4 */
+ arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+ else
+ {
+ /* Complex FFT radix-4 */
+ arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle,
+ S->twidCoefModifier);
+ }
+
+
+ if(S->bitReverseFlag == 1u)
+ {
+ /* Bit Reversal */
+ arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+ }
+
+}
+
+/**
+ * @} end of ComplexFFT group
+ */
+
+/*
+* Radix-4 FFT algorithm used is :
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 FFT:
+* Wn = co1 + j * (- si1)
+* W2n = co2 + j * (- si2)
+* W3n = co3 + j * (- si3)
+*
+* Butterfly implementation:
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)
+*
+*/
+
+/**
+ * @brief Core function for the Q31 CFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_radix4_butterfly_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier)
+{
+ uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+ q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+ q31_t xa, xb, xc, xd;
+ q31_t ya, yb, yc, yd;
+ q31_t xa_out, xb_out, xc_out, xd_out;
+ q31_t ya_out, yb_out, yc_out, yd_out;
+
+ q31_t *ptr1;
+ q63_t xaya, xbyb, xcyc, xdyd;
+ /* Total process is divided into three stages */
+
+ /* process first stage, middle stages, & last stage */
+
+
+ /* start of first stage process */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+ i0 = 0u;
+ ia1 = 0u;
+
+ j = n2;
+
+ /* Calculation of first stage */
+ do
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = (pSrc[(2u * i0)] >> 4u) + (pSrc[(2u * i2)] >> 4u);
+ /* xa - xc */
+ r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+ /* xb + xd */
+ t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+ /* ya + yc */
+ s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+ /* ya - yc */
+ s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1);
+ /* (xa + xc) - (xb + xd) */
+ r1 = r1 - t1;
+ /* yb + yd */
+ t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* yb - yd */
+ t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+ /* xb - xd */
+ t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+ /* index calculation for the coefficients */
+ ia2 = 2u * ia1;
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+ /* (xa - xc) + (yb - yd) */
+ r1 = r2 + t1;
+ /* (xa - xc) - (yb - yd) */
+ r2 = r2 - t1;
+
+ /* (ya - yc) - (xb - xd) */
+ s1 = s2 - t2;
+ /* (ya - yc) + (xb - xd) */
+ s2 = s2 + t2;
+
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+ /* index calculation for the coefficients */
+ ia3 = 3u * ia1;
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+
+ /* end of first stage process */
+
+ /* data is in 5.27(q27) format */
+
+
+ /* start of Middle stages process */
+
+
+ /* each stage in middle stages provides two down scaling of the input */
+
+ twidCoefModifier <<= 2u;
+
+
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ /* Calculation of first stage */
+ for (j = 0u; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = pSrc[2u * i0] + pSrc[2u * i2];
+ /* xa - xc */
+ r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xb + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1) >> 2u;
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+ /* (xb - xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
+
+ /* (xa - xc) + (yb - yd) */
+ r1 = r2 + t1;
+ /* (xa - xc) - (yb - yd) */
+ r2 = r2 - t1;
+
+ /* (ya - yc) - (xb - xd) */
+ s1 = s2 - t2;
+ /* (ya - yc) + (xb - xd) */
+ s2 = s2 + t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+ /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+ }
+ }
+ twidCoefModifier <<= 2u;
+ }
+
+ /* End of Middle stages process */
+
+ /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+ /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+ /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+ /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+ /* start of Last stage process */
+ /* Initializations for the last stage */
+ j = fftLen >> 2;
+ ptr1 = &pSrc[0];
+
+ /* Calculations of last stage */
+ do
+ {
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD64(ptr1)++;
+ xa = (q31_t) xaya;
+ ya = (q31_t) (xaya >> 32);
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD64(ptr1)++;
+ xb = (q31_t) xbyb;
+ yb = (q31_t) (xbyb >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD64(ptr1)++;
+ xc = (q31_t) xcyc;
+ yc = (q31_t) (xcyc >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xdyd = *__SIMD64(ptr1)++;
+ xd = (q31_t) xdyd;
+ yd = (q31_t) (xdyd >> 32);
+
+#else
+
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD64(ptr1)++;
+ ya = (q31_t) xaya;
+ xa = (q31_t) (xaya >> 32);
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD64(ptr1)++;
+ yb = (q31_t) xbyb;
+ xb = (q31_t) (xbyb >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD64(ptr1)++;
+ yc = (q31_t) xcyc;
+ xc = (q31_t) (xcyc >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xdyd = *__SIMD64(ptr1)++;
+ yd = (q31_t) xdyd;
+ xd = (q31_t) (xdyd >> 32);
+
+
+#endif
+
+ /* xa' = xa + xb + xc + xd */
+ xa_out = xa + xb + xc + xd;
+
+ /* ya' = ya + yb + yc + yd */
+ ya_out = ya + yb + yc + yd;
+
+ /* pointer updation for writing */
+ ptr1 = ptr1 - 8u;
+
+ /* writing xa' and ya' */
+ *ptr1++ = xa_out;
+ *ptr1++ = ya_out;
+
+ xc_out = (xa - xb + xc - xd);
+ yc_out = (ya - yb + yc - yd);
+
+ /* writing xc' and yc' */
+ *ptr1++ = xc_out;
+ *ptr1++ = yc_out;
+
+ xb_out = (xa + yb - xc - yd);
+ yb_out = (ya - xb - yc + xd);
+
+ /* writing xb' and yb' */
+ *ptr1++ = xb_out;
+ *ptr1++ = yb_out;
+
+ xd_out = (xa - yb - xc + yd);
+ yd_out = (ya + xb - yc - xd);
+
+ /* writing xd' and yd' */
+ *ptr1++ = xd_out;
+ *ptr1++ = yd_out;
+
+
+ } while(--j);
+
+ /* output is in 11.21(q21) format for the 1024 point */
+ /* output is in 9.23(q23) format for the 256 point */
+ /* output is in 7.25(q25) format for the 64 point */
+ /* output is in 5.27(q27) format for the 16 point */
+
+ /* End of last stage process */
+
+}
+
+
+/**
+ * @brief Core function for the Q31 CIFFT butterfly process.
+ * @param[in, out] *pSrc points to the in-place buffer of Q31 data type.
+ * @param[in] fftLen length of the FFT.
+ * @param[in] *pCoef points to twiddle coefficient buffer.
+ * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+
+/*
+* Radix-4 IFFT algorithm used is :
+*
+* CIFFT uses same twiddle coefficients as CFFT Function
+* x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]
+*
+*
+* IFFT is implemented with following changes in equations from FFT
+*
+* Input real and imaginary data:
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+*
+*
+* Output real and imaginary data:
+* x(4r) = xa'+ j * ya'
+* x(4r+1) = xb'+ j * yb'
+* x(4r+2) = xc'+ j * yc'
+* x(4r+3) = xd'+ j * yd'
+*
+*
+* Twiddle factors for radix-4 IFFT:
+* Wn = co1 + j * (si1)
+* W2n = co2 + j * (si2)
+* W3n = co3 + j * (si3)
+
+* The real and imaginary output values for the radix-4 butterfly are
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)
+*
+*/
+
+void arm_radix4_butterfly_inverse_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pCoef,
+ uint32_t twidCoefModifier)
+{
+ uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+ q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+ q31_t xa, xb, xc, xd;
+ q31_t ya, yb, yc, yd;
+ q31_t xa_out, xb_out, xc_out, xd_out;
+ q31_t ya_out, yb_out, yc_out, yd_out;
+
+ q31_t *ptr1;
+ q63_t xaya, xbyb, xcyc, xdyd;
+
+ /* input is be 1.31(q31) format for all FFT sizes */
+ /* Total process is divided into three stages */
+ /* process first stage, middle stages, & last stage */
+
+ /* Start of first stage process */
+
+ /* Initializations for the first stage */
+ n2 = fftLen;
+ n1 = n2;
+ /* n2 = fftLen/4 */
+ n2 >>= 2u;
+ i0 = 0u;
+ ia1 = 0u;
+
+ j = n2;
+
+ do
+ {
+
+ /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = (pSrc[2u * i0] >> 4u) + (pSrc[2u * i2] >> 4u);
+ /* xa - xc */
+ r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+ /* xb + xd */
+ t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+ /* ya + yc */
+ s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+ /* ya - yc */
+ s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1);
+ /* (xa + xc) - (xb + xd) */
+ r1 = r1 - t1;
+ /* yb + yd */
+ t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* yb - yd */
+ t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+ /* xb - xd */
+ t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+ /* index calculation for the coefficients */
+ ia2 = 2u * ia1;
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
+ ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[2u * i1 + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
+ ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+ /* (xa - xc) - (yb - yd) */
+ r1 = r2 - t1;
+ /* (xa - xc) + (yb - yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb - xd) */
+ s1 = s2 + t2;
+ /* (ya - yc) - (xb - xd) */
+ s2 = s2 - t2;
+
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+ /* index calculation for the coefficients */
+ ia3 = 3u * ia1;
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ /* Updating input index */
+ i0 = i0 + 1u;
+
+ } while(--j);
+
+ /* data is in 5.27(q27) format */
+ /* each stage provides two down scaling of the input */
+
+
+ /* Start of Middle stages process */
+
+ twidCoefModifier <<= 2u;
+
+ /* Calculation of second stage to excluding last stage */
+ for (k = fftLen / 4u; k > 4u; k >>= 2u)
+ {
+ /* Initializations for the first stage */
+ n1 = n2;
+ n2 >>= 2u;
+ ia1 = 0u;
+
+ for (j = 0; j <= (n2 - 1u); j++)
+ {
+ /* index calculation for the coefficients */
+ ia2 = ia1 + ia1;
+ ia3 = ia2 + ia1;
+ co1 = pCoef[ia1 * 2u];
+ si1 = pCoef[(ia1 * 2u) + 1u];
+ co2 = pCoef[ia2 * 2u];
+ si2 = pCoef[(ia2 * 2u) + 1u];
+ co3 = pCoef[ia3 * 2u];
+ si3 = pCoef[(ia3 * 2u) + 1u];
+ /* Twiddle coefficients index modifier */
+ ia1 = ia1 + twidCoefModifier;
+
+ for (i0 = j; i0 < fftLen; i0 += n1)
+ {
+ /* index calculation for the input as, */
+ /* pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+ i1 = i0 + n2;
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+
+ /* Butterfly implementation */
+ /* xa + xc */
+ r1 = pSrc[2u * i0] + pSrc[2u * i2];
+ /* xa - xc */
+ r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+ /* ya + yc */
+ s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+ /* ya - yc */
+ s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+ /* xb + xd */
+ t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+ /* xa' = xa + xb + xc + xd */
+ pSrc[2u * i0] = (r1 + t1) >> 2u;
+ /* xa + xc -(xb + xd) */
+ r1 = r1 - t1;
+ /* yb + yd */
+ t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+ /* ya' = ya + yb + yc + yd */
+ pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+ /* (ya + yc) - (yb + yd) */
+ s1 = s1 - t2;
+
+ /* (yb - yd) */
+ t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+ /* (xb - xd) */
+ t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+ /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+ pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
+ ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
+
+ /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+ pSrc[(2u * i1) + 1u] =
+ (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
+ ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
+
+ /* (xa - xc) - (yb - yd) */
+ r1 = r2 - t1;
+ /* (xa - xc) + (yb - yd) */
+ r2 = r2 + t1;
+
+ /* (ya - yc) + (xb - xd) */
+ s1 = s2 + t2;
+ /* (ya - yc) - (xb - xd) */
+ s2 = s2 - t2;
+
+ /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+ pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+ ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+ /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+ pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+ ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+ /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+ pSrc[(2u * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+ ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+ /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+ pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+ ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+ }
+ }
+ twidCoefModifier <<= 2u;
+ }
+
+ /* End of Middle stages process */
+
+ /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+ /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+ /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+ /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+ /* Start of last stage process */
+
+
+ /* Initializations for the last stage */
+ j = fftLen >> 2;
+ ptr1 = &pSrc[0];
+
+ /* Calculations of last stage */
+ do
+ {
+#ifndef ARM_MATH_BIG_ENDIAN
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD64(ptr1)++;
+ xa = (q31_t) xaya;
+ ya = (q31_t) (xaya >> 32);
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD64(ptr1)++;
+ xb = (q31_t) xbyb;
+ yb = (q31_t) (xbyb >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD64(ptr1)++;
+ xc = (q31_t) xcyc;
+ yc = (q31_t) (xcyc >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xdyd = *__SIMD64(ptr1)++;
+ xd = (q31_t) xdyd;
+ yd = (q31_t) (xdyd >> 32);
+
+#else
+
+ /* Read xa (real), ya(imag) input */
+ xaya = *__SIMD64(ptr1)++;
+ ya = (q31_t) xaya;
+ xa = (q31_t) (xaya >> 32);
+
+ /* Read xb (real), yb(imag) input */
+ xbyb = *__SIMD64(ptr1)++;
+ yb = (q31_t) xbyb;
+ xb = (q31_t) (xbyb >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xcyc = *__SIMD64(ptr1)++;
+ yc = (q31_t) xcyc;
+ xc = (q31_t) (xcyc >> 32);
+
+ /* Read xc (real), yc(imag) input */
+ xdyd = *__SIMD64(ptr1)++;
+ yd = (q31_t) xdyd;
+ xd = (q31_t) (xdyd >> 32);
+
+
+#endif
+
+ /* xa' = xa + xb + xc + xd */
+ xa_out = xa + xb + xc + xd;
+
+ /* ya' = ya + yb + yc + yd */
+ ya_out = ya + yb + yc + yd;
+
+ /* pointer updation for writing */
+ ptr1 = ptr1 - 8u;
+
+ /* writing xa' and ya' */
+ *ptr1++ = xa_out;
+ *ptr1++ = ya_out;
+
+ xc_out = (xa - xb + xc - xd);
+ yc_out = (ya - yb + yc - yd);
+
+ /* writing xc' and yc' */
+ *ptr1++ = xc_out;
+ *ptr1++ = yc_out;
+
+ xb_out = (xa - yb - xc + yd);
+ yb_out = (ya + xb - yc - xd);
+
+ /* writing xb' and yb' */
+ *ptr1++ = xb_out;
+ *ptr1++ = yb_out;
+
+ xd_out = (xa + yb - xc - yd);
+ yd_out = (ya - xb - yc + xd);
+
+ /* writing xd' and yd' */
+ *ptr1++ = xd_out;
+ *ptr1++ = yd_out;
+
+
+ } while(--j);
+
+ /* output is in 11.21(q21) format for the 1024 point */
+ /* output is in 9.23(q23) format for the 256 point */
+ /* output is in 7.25(q25) format for the 64 point */
+ /* output is in 5.27(q27) format for the 16 point */
+
+ /* End of last stage process */
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix8_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix8_f32.c
new file mode 100644
index 000000000..7ae0bfda5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_cfft_radix8_f32.c
@@ -0,0 +1,384 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_radix8_f32.c
+*
+* Description: Radix-8 Decimation in Frequency CFFT & CIFFT Floating point processing function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+* @defgroup Radix8_CFFT_CIFFT Radix-8 Complex FFT Functions
+*
+* \par
+* Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).
+* Computational complexity of CFFT reduces drastically when compared to DFT.
+* \par
+* This set of functions implements CFFT/CIFFT
+* for floating-point data types. The functions operates on in-place buffer which uses same buffer for input and output.
+* Complex input is stored in input buffer in an interleaved fashion.
+*
+* \par
+* The functions operate on blocks of input and output data and each call to the function processes
+* <code>2*fftLen</code> samples through the transform. <code>pSrc</code> points to In-place arrays containing <code>2*fftLen</code> values.
+* \par
+* The <code>pSrc</code> points to the array of in-place buffer of size <code>2*fftLen</code> and inputs and outputs are stored in an interleaved fashion as shown below.
+* <pre> {real[0], imag[0], real[1], imag[1],..} </pre>
+*
+* \par Lengths supported by the transform:
+* \par
+* Internally, the function utilize a Radix-8 decimation in frequency(DIF) algorithm
+* and the size of the FFT supported are of the lengths [ 64, 512, 4096].
+*
+*
+* \par Algorithm:
+*
+* <b>Complex Fast Fourier Transform:</b>
+* \par
+* Input real and imaginary data:
+* <pre>
+* x(n) = xa + j * ya
+* x(n+N/4 ) = xb + j * yb
+* x(n+N/2 ) = xc + j * yc
+* x(n+3N 4) = xd + j * yd
+* </pre>
+* where N is length of FFT
+* \par
+* Output real and imaginary data:
+* <pre>
+* X(4r) = xa'+ j * ya'
+* X(4r+1) = xb'+ j * yb'
+* X(4r+2) = xc'+ j * yc'
+* X(4r+3) = xd'+ j * yd'
+* </pre>
+* \par
+* Twiddle factors for Radix-8 FFT:
+* <pre>
+* Wn = co1 + j * (- si1)
+* W2n = co2 + j * (- si2)
+* W3n = co3 + j * (- si3)
+* </pre>
+*
+* \par
+* \image html CFFT.gif "Radix-8 Decimation-in Frequency Complex Fast Fourier Transform"
+*
+* \par
+* Output from Radix-8 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output.
+* \par
+* <b> Butterfly CFFT equations:</b>
+* <pre>
+* xa' = xa + xb + xc + xd
+* ya' = ya + yb + yc + yd
+* xc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)
+* yc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)
+* xb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)
+* yb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)
+* </pre>
+*
+* \par
+* where <code>fftLen</code> length of CFFT/CIFFT; <code>ifftFlag</code> Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT);
+* <code>bitReverseFlag</code> Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order);
+* <code>pTwiddle</code>points to array of twiddle coefficients; <code>pBitRevTable</code> points to the array of bit reversal table.
+* <code>twidCoefModifier</code> modifier for twiddle factor table which supports all FFT lengths with same table;
+* <code>pBitRevTable</code> modifier for bit reversal table which supports all FFT lengths with same table.
+* <code>onebyfftLen</code> value of 1/fftLen to calculate CIFFT;
+*
+* \par Fixed-Point Behavior
+* Care must be taken when using the fixed-point versions of the CFFT/CIFFT function.
+* Refer to the function specific documentation below for usage guidelines.
+*/
+
+
+/*
+* @brief Core function for the floating-point CFFT butterfly process.
+* @param[in, out] *pSrc points to the in-place buffer of floating-point data type.
+* @param[in] fftLen length of the FFT.
+* @param[in] *pCoef points to the twiddle coefficient buffer.
+* @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+* @return none.
+*/
+
+void arm_radix8_butterfly_f32(
+float32_t * pSrc,
+uint16_t fftLen,
+const float32_t * pCoef,
+uint16_t twidCoefModifier)
+{
+ uint32_t ia1, ia2, ia3, ia4, ia5, ia6, ia7;
+ uint32_t i1, i2, i3, i4, i5, i6, i7, i8;
+ uint32_t id;
+ uint32_t n1, n2, j;
+
+ float32_t r1, r2, r3, r4, r5, r6, r7, r8;
+ float32_t t1, t2;
+ float32_t s1, s2, s3, s4, s5, s6, s7, s8;
+ float32_t p1, p2, p3, p4;
+ float32_t co2, co3, co4, co5, co6, co7, co8;
+ float32_t si2, si3, si4, si5, si6, si7, si8;
+ const float32_t C81 = 0.70710678118f;
+
+ n2 = fftLen;
+
+ do
+ {
+ n1 = n2;
+ n2 = n2 >> 3;
+ i1 = 0;
+
+ do
+ {
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+ i4 = i3 + n2;
+ i5 = i4 + n2;
+ i6 = i5 + n2;
+ i7 = i6 + n2;
+ i8 = i7 + n2;
+ r1 = pSrc[2 * i1] + pSrc[2 * i5];
+ r5 = pSrc[2 * i1] - pSrc[2 * i5];
+ r2 = pSrc[2 * i2] + pSrc[2 * i6];
+ r6 = pSrc[2 * i2] - pSrc[2 * i6];
+ r3 = pSrc[2 * i3] + pSrc[2 * i7];
+ r7 = pSrc[2 * i3] - pSrc[2 * i7];
+ r4 = pSrc[2 * i4] + pSrc[2 * i8];
+ r8 = pSrc[2 * i4] - pSrc[2 * i8];
+ t1 = r1 - r3;
+ r1 = r1 + r3;
+ r3 = r2 - r4;
+ r2 = r2 + r4;
+ pSrc[2 * i1] = r1 + r2;
+ pSrc[2 * i5] = r1 - r2;
+ r1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
+ s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
+ r2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
+ s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
+ s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
+ s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
+ r4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
+ s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
+ t2 = r1 - s3;
+ r1 = r1 + s3;
+ s3 = r2 - r4;
+ r2 = r2 + r4;
+ pSrc[2 * i1 + 1] = r1 + r2;
+ pSrc[2 * i5 + 1] = r1 - r2;
+ pSrc[2 * i3] = t1 + s3;
+ pSrc[2 * i7] = t1 - s3;
+ pSrc[2 * i3 + 1] = t2 - r3;
+ pSrc[2 * i7 + 1] = t2 + r3;
+ r1 = (r6 - r8) * C81;
+ r6 = (r6 + r8) * C81;
+ r2 = (s6 - s8) * C81;
+ s6 = (s6 + s8) * C81;
+ t1 = r5 - r1;
+ r5 = r5 + r1;
+ r8 = r7 - r6;
+ r7 = r7 + r6;
+ t2 = s5 - r2;
+ s5 = s5 + r2;
+ s8 = s7 - s6;
+ s7 = s7 + s6;
+ pSrc[2 * i2] = r5 + s7;
+ pSrc[2 * i8] = r5 - s7;
+ pSrc[2 * i6] = t1 + s8;
+ pSrc[2 * i4] = t1 - s8;
+ pSrc[2 * i2 + 1] = s5 - r7;
+ pSrc[2 * i8 + 1] = s5 + r7;
+ pSrc[2 * i6 + 1] = t2 - r8;
+ pSrc[2 * i4 + 1] = t2 + r8;
+
+ i1 += n1;
+ } while(i1 < fftLen);
+
+ if(n2 < 8)
+ break;
+
+ ia1 = 0;
+ j = 1;
+
+ do
+ {
+ /* index calculation for the coefficients */
+ id = ia1 + twidCoefModifier;
+ ia1 = id;
+ ia2 = ia1 + id;
+ ia3 = ia2 + id;
+ ia4 = ia3 + id;
+ ia5 = ia4 + id;
+ ia6 = ia5 + id;
+ ia7 = ia6 + id;
+
+ co2 = pCoef[2 * ia1];
+ co3 = pCoef[2 * ia2];
+ co4 = pCoef[2 * ia3];
+ co5 = pCoef[2 * ia4];
+ co6 = pCoef[2 * ia5];
+ co7 = pCoef[2 * ia6];
+ co8 = pCoef[2 * ia7];
+ si2 = pCoef[2 * ia1 + 1];
+ si3 = pCoef[2 * ia2 + 1];
+ si4 = pCoef[2 * ia3 + 1];
+ si5 = pCoef[2 * ia4 + 1];
+ si6 = pCoef[2 * ia5 + 1];
+ si7 = pCoef[2 * ia6 + 1];
+ si8 = pCoef[2 * ia7 + 1];
+
+ i1 = j;
+
+ do
+ {
+ /* index calculation for the input */
+ i2 = i1 + n2;
+ i3 = i2 + n2;
+ i4 = i3 + n2;
+ i5 = i4 + n2;
+ i6 = i5 + n2;
+ i7 = i6 + n2;
+ i8 = i7 + n2;
+ r1 = pSrc[2 * i1] + pSrc[2 * i5];
+ r5 = pSrc[2 * i1] - pSrc[2 * i5];
+ r2 = pSrc[2 * i2] + pSrc[2 * i6];
+ r6 = pSrc[2 * i2] - pSrc[2 * i6];
+ r3 = pSrc[2 * i3] + pSrc[2 * i7];
+ r7 = pSrc[2 * i3] - pSrc[2 * i7];
+ r4 = pSrc[2 * i4] + pSrc[2 * i8];
+ r8 = pSrc[2 * i4] - pSrc[2 * i8];
+ t1 = r1 - r3;
+ r1 = r1 + r3;
+ r3 = r2 - r4;
+ r2 = r2 + r4;
+ pSrc[2 * i1] = r1 + r2;
+ r2 = r1 - r2;
+ s1 = pSrc[2 * i1 + 1] + pSrc[2 * i5 + 1];
+ s5 = pSrc[2 * i1 + 1] - pSrc[2 * i5 + 1];
+ s2 = pSrc[2 * i2 + 1] + pSrc[2 * i6 + 1];
+ s6 = pSrc[2 * i2 + 1] - pSrc[2 * i6 + 1];
+ s3 = pSrc[2 * i3 + 1] + pSrc[2 * i7 + 1];
+ s7 = pSrc[2 * i3 + 1] - pSrc[2 * i7 + 1];
+ s4 = pSrc[2 * i4 + 1] + pSrc[2 * i8 + 1];
+ s8 = pSrc[2 * i4 + 1] - pSrc[2 * i8 + 1];
+ t2 = s1 - s3;
+ s1 = s1 + s3;
+ s3 = s2 - s4;
+ s2 = s2 + s4;
+ r1 = t1 + s3;
+ t1 = t1 - s3;
+ pSrc[2 * i1 + 1] = s1 + s2;
+ s2 = s1 - s2;
+ s1 = t2 - r3;
+ t2 = t2 + r3;
+ p1 = co5 * r2;
+ p2 = si5 * s2;
+ p3 = co5 * s2;
+ p4 = si5 * r2;
+ pSrc[2 * i5] = p1 + p2;
+ pSrc[2 * i5 + 1] = p3 - p4;
+ p1 = co3 * r1;
+ p2 = si3 * s1;
+ p3 = co3 * s1;
+ p4 = si3 * r1;
+ pSrc[2 * i3] = p1 + p2;
+ pSrc[2 * i3 + 1] = p3 - p4;
+ p1 = co7 * t1;
+ p2 = si7 * t2;
+ p3 = co7 * t2;
+ p4 = si7 * t1;
+ pSrc[2 * i7] = p1 + p2;
+ pSrc[2 * i7 + 1] = p3 - p4;
+ r1 = (r6 - r8) * C81;
+ r6 = (r6 + r8) * C81;
+ s1 = (s6 - s8) * C81;
+ s6 = (s6 + s8) * C81;
+ t1 = r5 - r1;
+ r5 = r5 + r1;
+ r8 = r7 - r6;
+ r7 = r7 + r6;
+ t2 = s5 - s1;
+ s5 = s5 + s1;
+ s8 = s7 - s6;
+ s7 = s7 + s6;
+ r1 = r5 + s7;
+ r5 = r5 - s7;
+ r6 = t1 + s8;
+ t1 = t1 - s8;
+ s1 = s5 - r7;
+ s5 = s5 + r7;
+ s6 = t2 - r8;
+ t2 = t2 + r8;
+ p1 = co2 * r1;
+ p2 = si2 * s1;
+ p3 = co2 * s1;
+ p4 = si2 * r1;
+ pSrc[2 * i2] = p1 + p2;
+ pSrc[2 * i2 + 1] = p3 - p4;
+ p1 = co8 * r5;
+ p2 = si8 * s5;
+ p3 = co8 * s5;
+ p4 = si8 * r5;
+ pSrc[2 * i8] = p1 + p2;
+ pSrc[2 * i8 + 1] = p3 - p4;
+ p1 = co6 * r6;
+ p2 = si6 * s6;
+ p3 = co6 * s6;
+ p4 = si6 * r6;
+ pSrc[2 * i6] = p1 + p2;
+ pSrc[2 * i6 + 1] = p3 - p4;
+ p1 = co4 * t1;
+ p2 = si4 * t2;
+ p3 = co4 * t2;
+ p4 = si4 * t1;
+ pSrc[2 * i4] = p1 + p2;
+ pSrc[2 * i4 + 1] = p3 - p4;
+
+ i1 += n1;
+ } while(i1 < fftLen);
+
+ j++;
+ } while(j < n2);
+
+ twidCoefModifier <<= 3;
+ } while(n2 > 7);
+}
+
+/**
+* @} end of Radix8_CFFT_CIFFT group
+*/
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_f32.c
new file mode 100644
index 000000000..9c61a6167
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_f32.c
@@ -0,0 +1,461 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_f32.c
+*
+* Description: Processing function of DCT4 & IDCT4 F32.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @defgroup DCT4_IDCT4 DCT Type IV Functions
+ * Representation of signals by minimum number of values is important for storage and transmission.
+ * The possibility of large discontinuity between the beginning and end of a period of a signal
+ * in DFT can be avoided by extending the signal so that it is even-symmetric.
+ * Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the
+ * spectrum and is very widely used in signal and image coding applications.
+ * The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions.
+ * DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.
+ *
+ * DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal.
+ * Reordering of the input data makes the computation of DCT just a problem of
+ * computing the DFT of a real signal with a few additional operations.
+ * This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.
+ *
+ * DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used.
+ * DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing.
+ * DCT2 implementation can be described in the following steps:
+ * - Re-ordering input
+ * - Calculating Real FFT
+ * - Multiplication of weights and Real FFT output and getting real part from the product.
+ *
+ * This process is explained by the block diagram below:
+ * \image html DCT4.gif "Discrete Cosine Transform - type-IV"
+ *
+ * \par Algorithm:
+ * The N-point type-IV DCT is defined as a real, linear transformation by the formula:
+ * \image html DCT4Equation.gif
+ * where <code>k = 0,1,2,.....N-1</code>
+ *\par
+ * Its inverse is defined as follows:
+ * \image html IDCT4Equation.gif
+ * where <code>n = 0,1,2,.....N-1</code>
+ *\par
+ * The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N).
+ * The symmetry of the transform matrix indicates that the fast algorithms for the forward
+ * and inverse transform computation are identical.
+ * Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.
+ *
+ * \par Lengths supported by the transform:
+ * As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32().
+ * The library provides separate functions for Q15, Q31, and floating-point data types.
+ * \par Instance Structure
+ * The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure.
+ * A separate instance structure must be defined for each transform.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32().
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.
+ * Manually initialize the instance structure as follows:
+ * <pre>
+ *arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+ *arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+ *arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};
+ * </pre>
+ * where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4;
+ * \c normalize is normalizing factor used and is equal to <code>sqrt(2/N)</code>;
+ * \c pTwiddle points to the twiddle factor table;
+ * \c pCosFactor points to the cosFactor table;
+ * \c pRfft points to the real FFT instance;
+ * \c pCfft points to the complex FFT instance;
+ * The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32()
+ * and arm_rfft_f32() respectively for details regarding static initialization.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the DCT4 transform functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer)
+{
+ uint32_t i; /* Loop counter */
+ float32_t *weights = S->pTwiddle; /* Pointer to the Weights table */
+ float32_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */
+ float32_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */
+ float32_t in; /* Temporary variable */
+
+
+ /* DCT4 computation involves DCT2 (which is calculated using RFFT)
+ * along with some pre-processing and post-processing.
+ * Computational procedure is explained as follows:
+ * (a) Pre-processing involves multiplying input with cos factor,
+ * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
+ * where,
+ * r(n) -- output of preprocessing
+ * u(n) -- input to preprocessing(actual Source buffer)
+ * (b) Calculation of DCT2 using FFT is divided into three steps:
+ * Step1: Re-ordering of even and odd elements of input.
+ * Step2: Calculating FFT of the re-ordered input.
+ * Step3: Taking the real part of the product of FFT output and weights.
+ * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * where,
+ * Y4 -- DCT4 output, Y2 -- DCT2 output
+ * (d) Multiplying the output with the normalizing factor sqrt(2/N).
+ */
+
+ /*-------- Pre-processing ------------*/
+ /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+ arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N);
+ arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+
+ /* ----------------------------------------------------------------
+ * Step1: Re-ordering of even and odd elements as,
+ * pState[i] = pInlineBuffer[2*i] and
+ * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
+ ---------------------------------------------------------------------*/
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+ pS2 = pState + (S->N - 1u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+ i = (uint32_t) S->Nby2 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = (uint32_t) S->N >> 2u;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4.
+ * Compute 4 outputs at a time */
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+ i = ((uint32_t) S->N - 1u) >> 2u;
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ * (float32_t) 0.5;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ i = ((uint32_t) S->N - 1u) % 0x4u;
+
+ while(i > 0u)
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = (uint32_t) S->N >> 2u;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializing the loop counter to N/2 */
+ i = (uint32_t) S->Nby2;
+
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter */
+ i = (uint32_t) S->N;
+
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ * (float32_t) 0.5;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* Initializing the loop counter */
+ i = ((uint32_t) S->N - 1u);
+
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter */
+ i = (uint32_t) S->N;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = in * S->normalize;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_f32.c
new file mode 100644
index 000000000..eade6eeba
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_f32.c
@@ -0,0 +1,16519 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_init_f32.c
+*
+* Description: Initialization function of DCT-4 & IDCT4 F32
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/*
+* @brief Weights Table
+*/
+
+/**
+* \par
+* Weights tables are generated using the formula : <pre>weights[n] = e^(-j*n*pi/(2*N))</pre>
+* \par
+* C command to generate the table
+* <pre>
+* for(i = 0; i< N; i++)
+* {
+* weights[2*i]= cos(i*c);
+* weights[(2*i)+1]= -sin(i * c);
+* } </pre>
+* \par
+* Where <code>N</code> is the Number of weights to be calculated and <code>c</code> is <code>pi/(2*N)</code>
+* \par
+* In the tables below the real and imaginary values are placed alternatively, hence the
+* array length is <code>2*N</code>.
+*/
+
+static const float32_t Weights_128[256] = {
+ 1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f,
+ -0.012271538285719925f,
+ 0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f,
+ -0.036807222941358832f,
+ 0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f,
+ -0.061320736302208578f,
+ 0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f,
+ -0.085797312344439894f,
+ 0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f,
+ -0.110222207293883060f,
+ 0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f,
+ -0.134580708507126170f,
+ 0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f,
+ -0.158858143333861450f,
+ 0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f,
+ -0.183039887955140950f,
+ 0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f,
+ -0.207111376192218560f,
+ 0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f,
+ -0.231058108280671110f,
+ 0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f,
+ -0.254865659604514570f,
+ 0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f,
+ -0.278519689385053060f,
+ 0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f,
+ -0.302005949319228080f,
+ 0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f,
+ -0.325310292162262930f,
+ 0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f,
+ -0.348418680249434560f,
+ 0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f,
+ -0.371317193951837540f,
+ 0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f,
+ -0.393992040061048100f,
+ 0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f,
+ -0.416429560097637150f,
+ 0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f,
+ -0.438616238538527660f,
+ 0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f,
+ -0.460538710958240010f,
+ 0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f,
+ -0.482183772079122720f,
+ 0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f,
+ -0.503538383725717580f,
+ 0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f,
+ -0.524589682678468950f,
+ 0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f,
+ -0.545324988422046460f,
+ 0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f,
+ -0.565731810783613120f,
+ 0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f,
+ -0.585797857456438860f,
+ 0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f,
+ -0.605511041404325550f,
+ 0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f,
+ -0.624859488142386340f,
+ 0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f,
+ -0.643831542889791390f,
+ 0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f,
+ -0.662415777590171780f,
+ 0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f,
+ -0.680600997795453020f,
+ 0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f,
+ -0.698376249408972920f,
+ 0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f,
+ -0.715730825283818590f,
+ 0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f,
+ -0.732654271672412820f,
+ 0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f,
+ -0.749136394523459260f,
+ 0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f,
+ -0.765167265622458960f,
+ 0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f,
+ -0.780737228572094380f,
+ 0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f,
+ -0.795836904608883460f,
+ 0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f,
+ -0.810457198252594770f,
+ 0.575808191417845340f, -0.817584813151583710f, 0.565731810783613230f,
+ -0.824589302785025290f,
+ 0.555570233019602290f, -0.831469612302545240f, 0.545324988422046460f,
+ -0.838224705554837970f,
+ 0.534997619887097260f, -0.844853565249707010f, 0.524589682678468840f,
+ -0.851355193105265200f,
+ 0.514102744193221660f, -0.857728610000272120f, 0.503538383725717580f,
+ -0.863972856121586700f,
+ 0.492898192229784090f, -0.870086991108711350f, 0.482183772079122830f,
+ -0.876070094195406600f,
+ 0.471396736825997810f, -0.881921264348354940f, 0.460538710958240010f,
+ -0.887639620402853930f,
+ 0.449611329654606600f, -0.893224301195515320f, 0.438616238538527710f,
+ -0.898674465693953820f,
+ 0.427555093430282200f, -0.903989293123443340f, 0.416429560097637320f,
+ -0.909167983090522270f,
+ 0.405241314004989860f, -0.914209755703530690f, 0.393992040061048100f,
+ -0.919113851690057770f,
+ 0.382683432365089840f, -0.923879532511286740f, 0.371317193951837600f,
+ -0.928506080473215480f,
+ 0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f,
+ -0.937339011912574960f,
+ 0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f,
+ -0.945607325380521280f,
+ 0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f,
+ -0.953306040354193750f,
+ 0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f,
+ -0.960430519415565790f,
+ 0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f,
+ -0.966976471044852070f,
+ 0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f,
+ -0.972939952205560070f,
+ 0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f,
+ -0.978317370719627650f,
+ 0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f,
+ -0.983105487431216290f,
+ 0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f,
+ -0.987301418157858430f,
+ 0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f,
+ -0.990902635427780010f,
+ 0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f,
+ -0.993906970002356060f,
+ 0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f,
+ -0.996312612182778000f,
+ 0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f,
+ -0.998118112900149180f,
+ 0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f,
+ -0.999322384588349540f,
+ 0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f,
+ -0.999924701839144500f
+};
+
+static const float32_t Weights_512[1024] = {
+ 1.000000000000000000f, 0.000000000000000000f, 0.999995293809576190f,
+ -0.003067956762965976f,
+ 0.999981175282601110f, -0.006135884649154475f, 0.999957644551963900f,
+ -0.009203754782059819f,
+ 0.999924701839144500f, -0.012271538285719925f, 0.999882347454212560f,
+ -0.015339206284988100f,
+ 0.999830581795823400f, -0.018406729905804820f, 0.999769405351215280f,
+ -0.021474080275469508f,
+ 0.999698818696204250f, -0.024541228522912288f, 0.999618822495178640f,
+ -0.027608145778965740f,
+ 0.999529417501093140f, -0.030674803176636626f, 0.999430604555461730f,
+ -0.033741171851377580f,
+ 0.999322384588349540f, -0.036807222941358832f, 0.999204758618363890f,
+ -0.039872927587739811f,
+ 0.999077727752645360f, -0.042938256934940820f, 0.998941293186856870f,
+ -0.046003182130914623f,
+ 0.998795456205172410f, -0.049067674327418015f, 0.998640218180265270f,
+ -0.052131704680283324f,
+ 0.998475580573294770f, -0.055195244349689934f, 0.998301544933892890f,
+ -0.058258264500435752f,
+ 0.998118112900149180f, -0.061320736302208578f, 0.997925286198596000f,
+ -0.064382630929857465f,
+ 0.997723066644191640f, -0.067443919563664051f, 0.997511456140303450f,
+ -0.070504573389613856f,
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+ 0.022624286105092803, -0.999744038080865430, 0.022432587171950024,
+ -0.999748357854501780,
+ 0.022240887414024919, -0.999752640870248840, 0.022049186838366180,
+ -0.999756887127949080,
+ 0.021857485452021874, -0.999761096627446610, 0.021665783262040089,
+ -0.999765269368586450,
+ 0.021474080275469605, -0.999769405351215280, 0.021282376499358355,
+ -0.999773504575180990,
+ 0.021090671940755180, -0.999777567040332940, 0.020898966606708289,
+ -0.999781592746521670,
+ 0.020707260504265912, -0.999785581693599210, 0.020515553640476986,
+ -0.999789533881418780,
+ 0.020323846022389572, -0.999793449309835270, 0.020132137657052664,
+ -0.999797327978704690,
+ 0.019940428551514598, -0.999801169887884260, 0.019748718712823757,
+ -0.999804975037232870,
+ 0.019557008148029204, -0.999808743426610520, 0.019365296864179146,
+ -0.999812475055878780,
+ 0.019173584868322699, -0.999816169924900410, 0.018981872167508348,
+ -0.999819828033539420,
+ 0.018790158768784596, -0.999823449381661570, 0.018598444679200642,
+ -0.999827033969133420,
+ 0.018406729905804820, -0.999830581795823400, 0.018215014455646376,
+ -0.999834092861600960,
+ 0.018023298335773701, -0.999837567166337090, 0.017831581553236088,
+ -0.999841004709904000,
+ 0.017639864115082195, -0.999844405492175240, 0.017448146028360704,
+ -0.999847769513025900,
+ 0.017256427300120978, -0.999851096772332190, 0.017064707937411529,
+ -0.999854387269971890,
+ 0.016872987947281773, -0.999857641005823860, 0.016681267336780482,
+ -0.999860857979768540,
+ 0.016489546112956454, -0.999864038191687680, 0.016297824282859176,
+ -0.999867181641464380,
+ 0.016106101853537263, -0.999870288328982950, 0.015914378832040249,
+ -0.999873358254129260,
+ 0.015722655225417017, -0.999876391416790410, 0.015530931040716478,
+ -0.999879387816854930,
+ 0.015339206284988220, -0.999882347454212560, 0.015147480965280975,
+ -0.999885270328754520,
+ 0.014955755088644378, -0.999888156440373320, 0.014764028662127416,
+ -0.999891005788962950,
+ 0.014572301692779104, -0.999893818374418490, 0.014380574187649138,
+ -0.999896594196636680,
+ 0.014188846153786343, -0.999899333255515390, 0.013997117598240459,
+ -0.999902035550953920,
+ 0.013805388528060349, -0.999904701082852900, 0.013613658950295789,
+ -0.999907329851114300,
+ 0.013421928871995907, -0.999909921855641540, 0.013230198300209845,
+ -0.999912477096339240,
+ 0.013038467241987433, -0.999914995573113470, 0.012846735704377631,
+ -0.999917477285871770,
+ 0.012655003694430301, -0.999919922234522750, 0.012463271219194662,
+ -0.999922330418976490,
+ 0.012271538285719944, -0.999924701839144500, 0.012079804901056066,
+ -0.999927036494939640,
+ 0.011888071072252072, -0.999929334386276070, 0.011696336806357907,
+ -0.999931595513069200,
+ 0.011504602110422875, -0.999933819875236000, 0.011312866991496287,
+ -0.999936007472694620,
+ 0.011121131456628141, -0.999938158305364590, 0.010929395512867561,
+ -0.999940272373166960,
+ 0.010737659167264572, -0.999942349676023910, 0.010545922426868548,
+ -0.999944390213859060,
+ 0.010354185298728884, -0.999946393986597460, 0.010162447789895645,
+ -0.999948360994165400,
+ 0.009970709907418029, -0.999950291236490480, 0.009778971658346134,
+ -0.999952184713501780,
+ 0.009587233049729183, -0.999954041425129780, 0.009395494088617302,
+ -0.999955861371306100,
+ 0.009203754782059960, -0.999957644551963900, 0.009012015137106642,
+ -0.999959390967037450,
+ 0.008820275160807512, -0.999961100616462820, 0.008628534860211857,
+ -0.999962773500176930,
+ 0.008436794242369860, -0.999964409618118280, 0.008245053314331058,
+ -0.999966008970226920,
+ 0.008053312083144991, -0.999967571556443780, 0.007861570555861883,
+ -0.999969097376711580,
+ 0.007669828739531077, -0.999970586430974140, 0.007478086641202815,
+ -0.999972038719176730,
+ 0.007286344267926684, -0.999973454241265940, 0.007094601626752279,
+ -0.999974832997189810,
+ 0.006902858724729877, -0.999976174986897610, 0.006711115568908869,
+ -0.999977480210339940,
+ 0.006519372166339549, -0.999978748667468830, 0.006327628524071549,
+ -0.999979980358237650,
+ 0.006135884649154515, -0.999981175282601110, 0.005944140548638765,
+ -0.999982333440515350,
+ 0.005752396229573737, -0.999983454831937730, 0.005560651699009764,
+ -0.999984539456826970,
+ 0.005368906963996303, -0.999985587315143200, 0.005177162031583702,
+ -0.999986598406848000,
+ 0.004985416908821652, -0.999987572731904080, 0.004793671602759852,
+ -0.999988510290275690,
+ 0.004601926120448672, -0.999989411081928400, 0.004410180468937601,
+ -0.999990275106828920,
+ 0.004218434655277024, -0.999991102364945590, 0.004026688686516664,
+ -0.999991892856248010,
+ 0.003834942569706248, -0.999992646580707190, 0.003643196311896179,
+ -0.999993363538295150,
+ 0.003451449920135975, -0.999994043728985820, 0.003259703401476044,
+ -0.999994687152754080,
+ 0.003067956762966138, -0.999995293809576190, 0.002876210011656010,
+ -0.999995863699429940,
+ 0.002684463154596083, -0.999996396822294350, 0.002492716198835898,
+ -0.999996893178149880,
+ 0.002300969151425887, -0.999997352766978210, 0.002109222019415816,
+ -0.999997775588762350,
+ 0.001917474809855460, -0.999998161643486980, 0.001725727529795258,
+ -0.999998510931137790,
+ 0.001533980186284766, -0.999998823451701880, 0.001342232786374430,
+ -0.999999099205167830,
+ 0.001150485337113809, -0.999999338191525530, 0.000958737845553352,
+ -0.999999540410766110,
+ 0.000766990318742846, -0.999999705862882230, 0.000575242763732077,
+ -0.999999834547867670,
+ 0.000383495187571497, -0.999999926465717890, 0.000191747597310674,
+ -0.999999981616429330,
+
+};
+
+/**
+* \par
+* cosFactor tables are generated using the formula : <pre>cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))</pre>
+* \par
+* C command to generate the table
+* \par
+* <pre> for(i = 0; i< N; i++)
+* {
+* cos_factors[i]= 2 * cos((2*i+1)*c/2);
+* } </pre>
+* \par
+* where <code>N</code> is the number of factors to generate and <code>c</code> is <code>pi/(2*N)</code>
+*/
+static const float32_t cos_factors_128[128] = {
+ 0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f,
+ 0.999077727752645360f,
+ 0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f,
+ 0.995767414467659820f,
+ 0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f,
+ 0.990058210262297120f,
+ 0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f,
+ 0.981963869109555240f,
+ 0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f,
+ 0.971503890986251780f,
+ 0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f,
+ 0.958703474895871600f,
+ 0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f,
+ 0.943593458161960390f,
+ 0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f,
+ 0.926210242138311380f,
+ 0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f,
+ 0.906595704514915330f,
+ 0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f,
+ 0.884797098430937790f,
+ 0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f,
+ 0.860866938637767310f,
+ 0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f,
+ 0.834862874986380010f,
+ 0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f,
+ 0.806847553543799330f,
+ 0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f,
+ 0.776888465673232440f,
+ 0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f,
+ 0.745057785441466060f,
+ 0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f,
+ 0.711432195745216430f,
+ 0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f,
+ 0.676092703575316030f,
+ 0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f,
+ 0.639124444863775730f,
+ 0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f,
+ 0.600616479383868970f,
+ 0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f,
+ 0.560661576197336030f,
+ 0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f,
+ 0.519355990165589530f,
+ 0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f,
+ 0.476799230063322250f,
+ 0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f,
+ 0.433093818853152010f,
+ 0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f,
+ 0.388345046698826300f,
+ 0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f,
+ 0.342660717311994380f,
+ 0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f,
+ 0.296150888243623960f,
+ 0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f,
+ 0.248927605745720260f,
+ 0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f,
+ 0.201104634842091960f,
+ 0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f,
+ 0.152797185258443410f,
+ 0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f,
+ 0.104121633872054730f,
+ 0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f,
+ 0.055195244349690031f,
+ 0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f,
+ 0.006135884649154515f
+};
+
+static const float32_t cos_factors_512[512] = {
+ 0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f,
+ 0.999942349676023910f,
+ 0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f,
+ 0.999735288260561680f,
+ 0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f,
+ 0.999377670388002850f,
+ 0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f,
+ 0.998869549914283560f,
+ 0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f,
+ 0.998211003360478190f,
+ 0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f,
+ 0.997402129901275300f,
+ 0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f,
+ 0.996443051350042630f,
+ 0.996179828595696980f, 0.995907229417411720f, 0.995625256380994310f,
+ 0.995333912140482280f,
+ 0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f,
+ 0.994074879304879370f,
+ 0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f,
+ 0.992666142448948020f,
+ 0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f,
+ 0.991107913723276890f,
+ 0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f,
+ 0.989400427791380380f,
+ 0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f,
+ 0.987543941794359230f,
+ 0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f,
+ 0.985538735312176060f,
+ 0.985014231012239840f, 0.984480455383220930f, 0.983937413449218920f,
+ 0.983385110321551180f,
+ 0.982823551198705240f, 0.982252741366289370f, 0.981672686196983110f,
+ 0.981083391150486710f,
+ 0.980484861773469380f, 0.979877103699517640f, 0.979260122649082020f,
+ 0.978633924429423210f,
+ 0.977998514934557140f, 0.977353900145199960f, 0.976700086128711840f,
+ 0.976037079039039020f,
+ 0.975364885116656980f, 0.974683510688510670f, 0.973992962167955830f,
+ 0.973293246054698250f,
+ 0.972584368934732210f, 0.971866337480279400f, 0.971139158449725090f,
+ 0.970402838687555500f,
+ 0.969657385124292450f, 0.968902804776428870f, 0.968139104746362440f,
+ 0.967366292222328510f,
+ 0.966584374478333120f, 0.965793358874083680f, 0.964993252854920320f,
+ 0.964184063951745830f,
+ 0.963365799780954050f, 0.962538468044359160f, 0.961702076529122540f,
+ 0.960856633107679660f,
+ 0.960002145737665960f, 0.959138622461841890f, 0.958266071408017670f,
+ 0.957384500788975860f,
+ 0.956493918902395100f, 0.955594334130771110f, 0.954685754941338340f,
+ 0.953768189885990330f,
+ 0.952841647601198720f, 0.951906136807932350f, 0.950961666311575080f,
+ 0.950008245001843000f,
+ 0.949045881852700560f, 0.948074585922276230f, 0.947094366352777220f,
+ 0.946105232370403450f,
+ 0.945107193285260610f, 0.944100258491272660f, 0.943084437466093490f,
+ 0.942059739771017310f,
+ 0.941026175050889260f, 0.939983753034014050f, 0.938932483532064600f,
+ 0.937872376439989890f,
+ 0.936803441735921560f, 0.935725689481080370f, 0.934639129819680780f,
+ 0.933543772978836170f,
+ 0.932439629268462360f, 0.931326709081180430f, 0.930205022892219070f,
+ 0.929074581259315860f,
+ 0.927935394822617890f, 0.926787474304581750f, 0.925630830509872720f,
+ 0.924465474325262600f,
+ 0.923291416719527640f, 0.922108668743345180f, 0.920917241529189520f,
+ 0.919717146291227360f,
+ 0.918508394325212250f, 0.917290997008377910f, 0.916064965799331720f,
+ 0.914830312237946200f,
+ 0.913587047945250810f, 0.912335184623322750f, 0.911074734055176360f,
+ 0.909805708104652220f,
+ 0.908528118716306120f, 0.907241977915295820f, 0.905947297807268460f,
+ 0.904644090578246240f,
+ 0.903332368494511820f, 0.902012143902493180f, 0.900683429228646970f,
+ 0.899346236979341570f,
+ 0.898000579740739880f, 0.896646470178680150f, 0.895283921038557580f,
+ 0.893912945145203250f,
+ 0.892533555402764580f, 0.891145764794583180f, 0.889749586383072780f,
+ 0.888345033309596350f,
+ 0.886932118794342190f, 0.885510856136199950f, 0.884081258712634990f,
+ 0.882643339979562790f,
+ 0.881197113471222090f, 0.879742592800047410f, 0.878279791656541580f,
+ 0.876808723809145650f,
+ 0.875329403104110890f, 0.873841843465366860f, 0.872346058894391540f,
+ 0.870842063470078980f,
+ 0.869329871348606840f, 0.867809496763303320f, 0.866280954024512990f,
+ 0.864744257519462380f,
+ 0.863199421712124160f, 0.861646461143081300f, 0.860085390429390140f,
+ 0.858516224264442740f,
+ 0.856938977417828760f, 0.855353664735196030f, 0.853760301138111410f,
+ 0.852158901623919830f,
+ 0.850549481265603480f, 0.848932055211639610f, 0.847306638685858320f,
+ 0.845673246987299070f,
+ 0.844031895490066410f, 0.842382599643185850f, 0.840725374970458070f,
+ 0.839060237070312740f,
+ 0.837387201615661940f, 0.835706284353752600f, 0.834017501106018130f,
+ 0.832320867767929680f,
+ 0.830616400308846310f, 0.828904114771864870f, 0.827184027273669130f,
+ 0.825456154004377550f,
+ 0.823720511227391430f, 0.821977115279241550f, 0.820225982569434690f,
+ 0.818467129580298660f,
+ 0.816700572866827850f, 0.814926329056526620f, 0.813144414849253590f,
+ 0.811354847017063730f,
+ 0.809557642404051260f, 0.807752817926190360f, 0.805940390571176280f,
+ 0.804120377398265810f,
+ 0.802292795538115720f, 0.800457662192622820f, 0.798614994634760820f,
+ 0.796764810208418830f,
+ 0.794907126328237010f, 0.793041960479443640f, 0.791169330217690200f,
+ 0.789289253168885650f,
+ 0.787401747029031430f, 0.785506829564053930f, 0.783604518609638200f,
+ 0.781694832071059390f,
+ 0.779777787923014550f, 0.777853404209453150f, 0.775921699043407690f,
+ 0.773982690606822900f,
+ 0.772036397150384520f, 0.770082836993347900f, 0.768122028523365420f,
+ 0.766153990196312920f,
+ 0.764178740536116670f, 0.762196298134578900f, 0.760206681651202420f,
+ 0.758209909813015280f,
+ 0.756206001414394540f, 0.754194975316889170f, 0.752176850449042810f,
+ 0.750151645806215070f,
+ 0.748119380450403600f, 0.746080073510063780f, 0.744033744179929290f,
+ 0.741980411720831070f,
+ 0.739920095459516200f, 0.737852814788465980f, 0.735778589165713590f,
+ 0.733697438114660370f,
+ 0.731609381223892630f, 0.729514438146997010f, 0.727412628602375770f,
+ 0.725303972373060770f,
+ 0.723188489306527460f, 0.721066199314508110f, 0.718937122372804490f,
+ 0.716801278521099540f,
+ 0.714658687862769090f, 0.712509370564692320f, 0.710353346857062420f,
+ 0.708190637033195400f,
+ 0.706021261449339740f, 0.703845240524484940f, 0.701662594740168570f,
+ 0.699473344640283770f,
+ 0.697277510830886630f, 0.695075113980000880f, 0.692866174817424740f,
+ 0.690650714134534720f,
+ 0.688428752784090550f, 0.686200311680038700f, 0.683965411797315510f,
+ 0.681724074171649820f,
+ 0.679476319899365080f, 0.677222170137180450f, 0.674961646102012040f,
+ 0.672694769070772970f,
+ 0.670421560380173090f, 0.668142041426518560f, 0.665856233665509720f,
+ 0.663564158612039880f,
+ 0.661265837839992270f, 0.658961292982037320f, 0.656650545729429050f,
+ 0.654333617831800550f,
+ 0.652010531096959500f, 0.649681307390683190f, 0.647345968636512060f,
+ 0.645004536815544040f,
+ 0.642657033966226860f, 0.640303482184151670f, 0.637943903621844170f,
+ 0.635578320488556230f,
+ 0.633206755050057190f, 0.630829229628424470f, 0.628445766601832710f,
+ 0.626056388404343520f,
+ 0.623661117525694640f, 0.621259976511087660f, 0.618852987960976320f,
+ 0.616440174530853650f,
+ 0.614021558931038490f, 0.611597163926462020f, 0.609167012336453210f,
+ 0.606731127034524480f,
+ 0.604289530948156070f, 0.601842247058580030f, 0.599389298400564540f,
+ 0.596930708062196500f,
+ 0.594466499184664540f, 0.591996694962040990f, 0.589521318641063940f,
+ 0.587040393520918080f,
+ 0.584553942953015330f, 0.582061990340775550f, 0.579564559139405740f,
+ 0.577061672855679550f,
+ 0.574553355047715760f, 0.572039629324757050f, 0.569520519346947250f,
+ 0.566996048825108680f,
+ 0.564466241520519500f, 0.561931121244689470f, 0.559390711859136140f,
+ 0.556845037275160100f,
+ 0.554294121453620110f, 0.551737988404707450f, 0.549176662187719770f,
+ 0.546610166910834860f,
+ 0.544038526730883930f, 0.541461765853123560f, 0.538879908531008420f,
+ 0.536292979065963180f,
+ 0.533701001807152960f, 0.531104001151255000f, 0.528502001542228480f,
+ 0.525895027471084740f,
+ 0.523283103475656430f, 0.520666254140367270f, 0.518044504095999340f,
+ 0.515417878019463150f,
+ 0.512786400633563070f, 0.510150096706766700f, 0.507508991052970870f,
+ 0.504863108531267480f,
+ 0.502212474045710900f, 0.499557112545081890f, 0.496897049022654640f,
+ 0.494232308515959730f,
+ 0.491562916106550060f, 0.488888896919763230f, 0.486210276124486530f,
+ 0.483527078932918740f,
+ 0.480839330600333900f, 0.478147056424843120f, 0.475450281747155870f,
+ 0.472749031950342900f,
+ 0.470043332459595620f, 0.467333208741988530f, 0.464618686306237820f,
+ 0.461899790702462840f,
+ 0.459176547521944150f, 0.456448982396883860f, 0.453717121000163930f,
+ 0.450980989045103810f,
+ 0.448240612285220000f, 0.445496016513981740f, 0.442747227564570130f,
+ 0.439994271309633260f,
+ 0.437237173661044200f, 0.434475960569655710f, 0.431710658025057370f,
+ 0.428941292055329550f,
+ 0.426167888726799620f, 0.423390474143796100f, 0.420609074448402510f,
+ 0.417823715820212380f,
+ 0.415034424476081630f, 0.412241226669883000f, 0.409444148692257590f,
+ 0.406643216870369140f,
+ 0.403838457567654130f, 0.401029897183575790f, 0.398217562153373620f,
+ 0.395401478947816300f,
+ 0.392581674072951530f, 0.389758174069856410f, 0.386931005514388690f,
+ 0.384100195016935040f,
+ 0.381265769222162490f, 0.378427754808765620f, 0.375586178489217330f,
+ 0.372741067009515810f,
+ 0.369892447148934270f, 0.367040345719767240f, 0.364184789567079840f,
+ 0.361325805568454340f,
+ 0.358463420633736540f, 0.355597661704783960f, 0.352728555755210730f,
+ 0.349856129790135030f,
+ 0.346980410845923680f, 0.344101425989938980f, 0.341219202320282410f,
+ 0.338333766965541290f,
+ 0.335445147084531660f, 0.332553369866044220f, 0.329658462528587550f,
+ 0.326760452320131790f,
+ 0.323859366517852960f, 0.320955232427875210f, 0.318048077385015060f,
+ 0.315137928752522440f,
+ 0.312224813921825050f, 0.309308760312268780f, 0.306389795370861080f,
+ 0.303467946572011370f,
+ 0.300543241417273400f, 0.297615707435086310f, 0.294685372180514330f,
+ 0.291752263234989370f,
+ 0.288816408206049480f, 0.285877834727080730f, 0.282936570457055390f,
+ 0.279992643080273380f,
+ 0.277046080306099950f, 0.274096909868706330f, 0.271145159526808070f,
+ 0.268190857063403180f,
+ 0.265234030285511900f, 0.262274707023913590f, 0.259312915132886350f,
+ 0.256348682489942910f,
+ 0.253382036995570270f, 0.250413006572965280f, 0.247441619167773440f,
+ 0.244467902747824210f,
+ 0.241491885302869300f, 0.238513594844318500f, 0.235533059404975460f,
+ 0.232550307038775330f,
+ 0.229565365820518870f, 0.226578263845610110f, 0.223589029229790020f,
+ 0.220597690108873650f,
+ 0.217604274638483670f, 0.214608810993786920f, 0.211611327369227610f,
+ 0.208611851978263460f,
+ 0.205610413053099320f, 0.202607038844421110f, 0.199601757621131050f,
+ 0.196594597670080220f,
+ 0.193585587295803750f, 0.190574754820252800f, 0.187562128582529740f,
+ 0.184547736938619640f,
+ 0.181531608261125130f, 0.178513770938997590f, 0.175494253377271400f,
+ 0.172473083996796030f,
+ 0.169450291233967930f, 0.166425903540464220f, 0.163399949382973230f,
+ 0.160372457242928400f,
+ 0.157343455616238280f, 0.154312973013020240f, 0.151281037957330250f,
+ 0.148247678986896200f,
+ 0.145212924652847520f, 0.142176803519448000f, 0.139139344163826280f,
+ 0.136100575175706200f,
+ 0.133060525157139180f, 0.130019222722233350f, 0.126976696496885980f,
+ 0.123932975118512200f,
+ 0.120888087235777220f, 0.117842061508325020f, 0.114794926606510250f,
+ 0.111746711211126660f,
+ 0.108697444013138670f, 0.105647153713410700f, 0.102595869022436280f,
+ 0.099543618660069444f,
+ 0.096490431355252607f, 0.093436335845747912f, 0.090381360877865011f,
+ 0.087325535206192226f,
+ 0.084268887593324127f, 0.081211446809592386f, 0.078153241632794315f,
+ 0.075094300847921291f,
+ 0.072034653246889416f, 0.068974327628266732f, 0.065913352797003930f,
+ 0.062851757564161420f,
+ 0.059789570746640007f, 0.056726821166907783f, 0.053663537652730679f,
+ 0.050599749036899337f,
+ 0.047535484156959261f, 0.044470771854938744f, 0.041405640977076712f,
+ 0.038340120373552791f,
+ 0.035274238898213947f, 0.032208025408304704f, 0.029141508764193740f,
+ 0.026074717829104040f,
+ 0.023007681468839410f, 0.019940428551514598f, 0.016872987947281773f,
+ 0.013805388528060349f,
+ 0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f,
+ 0.001533980186284766f
+};
+
+static const float32_t cos_factors_2048[2048] = {
+ 0.999999926465717890f, 0.999999338191525530f, 0.999998161643486980f,
+ 0.999996396822294350f,
+ 0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f,
+ 0.999983454831937730f,
+ 0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f,
+ 0.999961100616462820f,
+ 0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f,
+ 0.999929334386276070f,
+ 0.999919922234522750f, 0.999909921855641540f, 0.999899333255515390f,
+ 0.999888156440373320f,
+ 0.999876391416790410f, 0.999864038191687680f, 0.999851096772332190f,
+ 0.999837567166337090f,
+ 0.999823449381661570f, 0.999808743426610520f, 0.999793449309835270f,
+ 0.999777567040332940f,
+ 0.999761096627446610f, 0.999744038080865430f, 0.999726391410624470f,
+ 0.999708156627104880f,
+ 0.999689333741033640f, 0.999669922763483760f, 0.999649923705874240f,
+ 0.999629336579970110f,
+ 0.999608161397882110f, 0.999586398172067070f, 0.999564046915327740f,
+ 0.999541107640812940f,
+ 0.999517580362016990f, 0.999493465092780590f, 0.999468761847290050f,
+ 0.999443470640077770f,
+ 0.999417591486021720f, 0.999391124400346050f, 0.999364069398620550f,
+ 0.999336426496761240f,
+ 0.999308195711029470f, 0.999279377058032710f, 0.999249970554724420f,
+ 0.999219976218403530f,
+ 0.999189394066714920f, 0.999158224117649430f, 0.999126466389543390f,
+ 0.999094120901079070f,
+ 0.999061187671284600f, 0.999027666719533690f, 0.998993558065545680f,
+ 0.998958861729386080f,
+ 0.998923577731465780f, 0.998887706092541290f, 0.998851246833715180f,
+ 0.998814199976435390f,
+ 0.998776565542495610f, 0.998738343554035230f, 0.998699534033539280f,
+ 0.998660137003838490f,
+ 0.998620152488108870f, 0.998579580509872500f, 0.998538421092996730f,
+ 0.998496674261694640f,
+ 0.998454340040524800f, 0.998411418454391300f, 0.998367909528543820f,
+ 0.998323813288577560f,
+ 0.998279129760433200f, 0.998233858970396850f, 0.998188000945100300f,
+ 0.998141555711520520f,
+ 0.998094523296980010f, 0.998046903729146840f, 0.997998697036034390f,
+ 0.997949903246001190f,
+ 0.997900522387751620f, 0.997850554490335110f, 0.997799999583146470f,
+ 0.997748857695925690f,
+ 0.997697128858758500f, 0.997644813102075420f, 0.997591910456652630f,
+ 0.997538420953611340f,
+ 0.997484344624417930f, 0.997429681500884180f, 0.997374431615167150f,
+ 0.997318594999768600f,
+ 0.997262171687536170f, 0.997205161711661850f, 0.997147565105683480f,
+ 0.997089381903483400f,
+ 0.997030612139289450f, 0.996971255847674320f, 0.996911313063555740f,
+ 0.996850783822196610f,
+ 0.996789668159204560f, 0.996727966110532490f, 0.996665677712478160f,
+ 0.996602803001684130f,
+ 0.996539342015137940f, 0.996475294790172160f, 0.996410661364464100f,
+ 0.996345441776035900f,
+ 0.996279636063254650f, 0.996213244264832040f, 0.996146266419824620f,
+ 0.996078702567633980f,
+ 0.996010552748005870f, 0.995941817001031350f, 0.995872495367145730f,
+ 0.995802587887129160f,
+ 0.995732094602106430f, 0.995661015553546910f, 0.995589350783264600f,
+ 0.995517100333418110f,
+ 0.995444264246510340f, 0.995370842565388990f, 0.995296835333246090f,
+ 0.995222242593618360f,
+ 0.995147064390386470f, 0.995071300767776170f, 0.994994951770357020f,
+ 0.994918017443043200f,
+ 0.994840497831093180f, 0.994762392980109930f, 0.994683702936040250f,
+ 0.994604427745175660f,
+ 0.994524567454151740f, 0.994444122109948040f, 0.994363091759888570f,
+ 0.994281476451641550f,
+ 0.994199276233218910f, 0.994116491152977070f, 0.994033121259616400f,
+ 0.993949166602181130f,
+ 0.993864627230059750f, 0.993779503192984580f, 0.993693794541031790f,
+ 0.993607501324621610f,
+ 0.993520623594518090f, 0.993433161401829360f, 0.993345114798006910f,
+ 0.993256483834846440f,
+ 0.993167268564487230f, 0.993077469039412300f, 0.992987085312448390f,
+ 0.992896117436765980f,
+ 0.992804565465879140f, 0.992712429453645460f, 0.992619709454266140f,
+ 0.992526405522286100f,
+ 0.992432517712593660f, 0.992338046080420420f, 0.992242990681341700f,
+ 0.992147351571276090f,
+ 0.992051128806485720f, 0.991954322443575950f, 0.991856932539495470f,
+ 0.991758959151536110f,
+ 0.991660402337333210f, 0.991561262154865290f, 0.991461538662453790f,
+ 0.991361231918763460f,
+ 0.991260341982802440f, 0.991158868913921350f, 0.991056812771814340f,
+ 0.990954173616518500f,
+ 0.990850951508413620f, 0.990747146508222710f, 0.990642758677011570f,
+ 0.990537788076188750f,
+ 0.990432234767505970f, 0.990326098813057330f, 0.990219380275280000f,
+ 0.990112079216953770f,
+ 0.990004195701200910f, 0.989895729791486660f, 0.989786681551618640f,
+ 0.989677051045747210f,
+ 0.989566838338365120f, 0.989456043494307710f, 0.989344666578752640f,
+ 0.989232707657220050f,
+ 0.989120166795572690f, 0.989007044060015270f, 0.988893339517095130f,
+ 0.988779053233701520f,
+ 0.988664185277066230f, 0.988548735714763200f, 0.988432704614708340f,
+ 0.988316092045159690f,
+ 0.988198898074717610f, 0.988081122772324070f, 0.987962766207263420f,
+ 0.987843828449161740f,
+ 0.987724309567986960f, 0.987604209634049160f, 0.987483528717999710f,
+ 0.987362266890832400f,
+ 0.987240424223882250f, 0.987118000788826280f, 0.986994996657682980f,
+ 0.986871411902812470f,
+ 0.986747246596916590f, 0.986622500813038480f, 0.986497174624562880f,
+ 0.986371268105216030f,
+ 0.986244781329065460f, 0.986117714370520090f, 0.985990067304330140f,
+ 0.985861840205586980f,
+ 0.985733033149723490f, 0.985603646212513400f, 0.985473679470071810f,
+ 0.985343132998854790f,
+ 0.985212006875659350f, 0.985080301177623800f, 0.984948015982227030f,
+ 0.984815151367289140f,
+ 0.984681707410970940f, 0.984547684191773960f, 0.984413081788540700f,
+ 0.984277900280454370f,
+ 0.984142139747038570f, 0.984005800268157870f, 0.983868881924017220f,
+ 0.983731384795162090f,
+ 0.983593308962478650f, 0.983454654507193270f, 0.983315421510872810f,
+ 0.983175610055424420f,
+ 0.983035220223095640f, 0.982894252096474070f, 0.982752705758487830f,
+ 0.982610581292404750f,
+ 0.982467878781833170f, 0.982324598310721280f, 0.982180739963357090f,
+ 0.982036303824369020f,
+ 0.981891289978725100f, 0.981745698511732990f, 0.981599529509040720f,
+ 0.981452783056635520f,
+ 0.981305459240844670f, 0.981157558148334830f, 0.981009079866112630f,
+ 0.980860024481523870f,
+ 0.980710392082253970f, 0.980560182756327840f, 0.980409396592109910f,
+ 0.980258033678303550f,
+ 0.980106094103951770f, 0.979953577958436740f, 0.979800485331479790f,
+ 0.979646816313141210f,
+ 0.979492570993820810f, 0.979337749464256780f, 0.979182351815526930f,
+ 0.979026378139047580f,
+ 0.978869828526574120f, 0.978712703070200420f, 0.978555001862359550f,
+ 0.978396724995823090f,
+ 0.978237872563701090f, 0.978078444659442380f, 0.977918441376834370f,
+ 0.977757862810002760f,
+ 0.977596709053411890f, 0.977434980201864260f, 0.977272676350500860f,
+ 0.977109797594800880f,
+ 0.976946344030581670f, 0.976782315753998650f, 0.976617712861545640f,
+ 0.976452535450054060f,
+ 0.976286783616693630f, 0.976120457458971910f, 0.975953557074734300f,
+ 0.975786082562163930f,
+ 0.975618034019781750f, 0.975449411546446380f, 0.975280215241354220f,
+ 0.975110445204038890f,
+ 0.974940101534371830f, 0.974769184332561770f, 0.974597693699155050f,
+ 0.974425629735034990f,
+ 0.974252992541422500f, 0.974079782219875680f, 0.973905998872289570f,
+ 0.973731642600896400f,
+ 0.973556713508265560f, 0.973381211697303290f, 0.973205137271252800f,
+ 0.973028490333694210f,
+ 0.972851270988544180f, 0.972673479340056430f, 0.972495115492821190f,
+ 0.972316179551765300f,
+ 0.972136671622152230f, 0.971956591809581720f, 0.971775940219990140f,
+ 0.971594716959650160f,
+ 0.971412922135170940f, 0.971230555853497380f, 0.971047618221911100f,
+ 0.970864109348029470f,
+ 0.970680029339806130f, 0.970495378305530560f, 0.970310156353828110f,
+ 0.970124363593660280f,
+ 0.969938000134323960f, 0.969751066085452140f, 0.969563561557013180f,
+ 0.969375486659311280f,
+ 0.969186841502985950f, 0.968997626199012420f, 0.968807840858700970f,
+ 0.968617485593697540f,
+ 0.968426560515983190f, 0.968235065737874320f, 0.968043001372022260f,
+ 0.967850367531413620f,
+ 0.967657164329369880f, 0.967463391879547550f, 0.967269050295937790f,
+ 0.967074139692867040f,
+ 0.966878660184995910f, 0.966682611887320080f, 0.966485994915169840f,
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+ 0.086179387127484922f,
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+ 0.083122438703613077f,
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+ 0.080064707899690932f,
+ 0.079300156324387569f, 0.078535558098845590f, 0.077770913672857989f,
+ 0.077006223496245585f,
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+ 0.073947014280897269f,
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+ 0.070887109048087787f,
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+ 0.067826536598810966f,
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+ 0.064765325740339871f,
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+ 0.061703505285957416f,
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+ 0.058641104054683348f,
+ 0.057875416378229017f, 0.057109694655158132f, 0.056343939335925283f,
+ 0.055578150871004817f,
+ 0.054812329710889909f, 0.054046476306093640f, 0.053280591107148056f,
+ 0.052514674564603257f,
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+ 0.049450703970084824f,
+ 0.048684637468439020f, 0.047918542326875327f, 0.047152418996068000f,
+ 0.046386267926707213f,
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+ 0.043321395278109784f,
+ 0.042555112276904117f, 0.041788804241622082f, 0.041022471623063397f,
+ 0.040256114872041358f,
+ 0.039489734439384118f, 0.038723330775933762f, 0.037956904332545366f,
+ 0.037190455560088091f,
+ 0.036423984909444228f, 0.035657492831508264f, 0.034890979777187955f,
+ 0.034124446197403423f,
+ 0.033357892543086159f, 0.032591319265180385f, 0.031824726814640963f,
+ 0.031058115642434700f,
+ 0.030291486199539423f, 0.029524838936943035f, 0.028758174305644590f,
+ 0.027991492756653365f,
+ 0.027224794740987910f, 0.026458080709677145f, 0.025691351113759395f,
+ 0.024924606404281485f,
+ 0.024157847032300020f, 0.023391073448879338f, 0.022624286105092803f,
+ 0.021857485452021874f,
+ 0.021090671940755180f, 0.020323846022389572f, 0.019557008148029204f,
+ 0.018790158768784596f,
+ 0.018023298335773701f, 0.017256427300120978f, 0.016489546112956454f,
+ 0.015722655225417017f,
+ 0.014955755088644378f, 0.014188846153786343f, 0.013421928871995907f,
+ 0.012655003694430301f,
+ 0.011888071072252072f, 0.011121131456628141f, 0.010354185298728884f,
+ 0.009587233049729183f,
+ 0.008820275160807512f, 0.008053312083144991f, 0.007286344267926684f,
+ 0.006519372166339549f,
+ 0.005752396229573737f, 0.004985416908821652f, 0.004218434655277024f,
+ 0.003451449920135975f,
+ 0.002684463154596083f, 0.001917474809855460f, 0.001150485337113809f,
+ 0.000383495187571497f
+};
+
+static const float32_t cos_factors_8192[8192] = {
+ 1.999999990808214700, 1.999999917273932200, 1.999999770205369800,
+ 1.999999549602533100,
+ 1.999999255465430200, 1.999998887794072000, 1.999998446588471700,
+ 1.999997931848645600,
+ 1.999997343574612800, 1.999996681766395000, 1.999995946424016200,
+ 1.999995137547503600,
+ 1.999994255136887000, 1.999993299192198700, 1.999992269713474200,
+ 1.999991166700750800,
+ 1.999989990154069600, 1.999988740073473500, 1.999987416459008600,
+ 1.999986019310723500,
+ 1.999984548628669600, 1.999983004412901000, 1.999981386663474400,
+ 1.999979695380449400,
+ 1.999977930563888100, 1.999976092213855400, 1.999974180330418700,
+ 1.999972194913648900,
+ 1.999970135963618400, 1.999968003480403000, 1.999965797464081200,
+ 1.999963517914734100,
+ 1.999961164832445800, 1.999958738217302300, 1.999956238069392900,
+ 1.999953664388809800,
+ 1.999951017175647600, 1.999948296430003500, 1.999945502151977600,
+ 1.999942634341672600,
+ 1.999939692999193900, 1.999936678124649700, 1.999933589718150700,
+ 1.999930427779810900,
+ 1.999927192309745900, 1.999923883308075200, 1.999920500774920300,
+ 1.999917044710405500,
+ 1.999913515114657900, 1.999909911987807200, 1.999906235329986100,
+ 1.999902485141329400,
+ 1.999898661421975400, 1.999894764172064600, 1.999890793391740000,
+ 1.999886749081147800,
+ 1.999882631240436700, 1.999878439869758200, 1.999874174969266300,
+ 1.999869836539117700,
+ 1.999865424579472000, 1.999860939090491600, 1.999856380072341000,
+ 1.999851747525188200,
+ 1.999847041449203300, 1.999842261844559700, 1.999837408711432600,
+ 1.999832482050000900,
+ 1.999827481860445300, 1.999822408142949900, 1.999817260897701400,
+ 1.999812040124888700,
+ 1.999806745824704000, 1.999801377997341800, 1.999795936642999600,
+ 1.999790421761877400,
+ 1.999784833354177900, 1.999779171420106700, 1.999773435959872000,
+ 1.999767626973684400,
+ 1.999761744461757700, 1.999755788424308200, 1.999749758861554900,
+ 1.999743655773719400,
+ 1.999737479161026100, 1.999731229023702200, 1.999724905361977200,
+ 1.999718508176084000,
+ 1.999712037466257600, 1.999705493232735800, 1.999698875475759600,
+ 1.999692184195571900,
+ 1.999685419392419000, 1.999678581066549400, 1.999671669218214600,
+ 1.999664683847668800,
+ 1.999657624955168700, 1.999650492540973900, 1.999643286605346800,
+ 1.999636007148552400,
+ 1.999628654170857900, 1.999621227672533800, 1.999613727653853500,
+ 1.999606154115092500,
+ 1.999598507056529000, 1.999590786478444600, 1.999582992381123000,
+ 1.999575124764850800,
+ 1.999567183629917100, 1.999559168976613900, 1.999551080805236100,
+ 1.999542919116081000,
+ 1.999534683909448600, 1.999526375185641800, 1.999517992944965800,
+ 1.999509537187729200,
+ 1.999501007914242600, 1.999492405124819700, 1.999483728819776900,
+ 1.999474978999432800,
+ 1.999466155664109600, 1.999457258814131500, 1.999448288449825500,
+ 1.999439244571521700,
+ 1.999430127179552500, 1.999420936274252800, 1.999411671855960900,
+ 1.999402333925017300,
+ 1.999392922481765500, 1.999383437526551300, 1.999373879059723500,
+ 1.999364247081633500,
+ 1.999354541592635500, 1.999344762593086500, 1.999334910083345700,
+ 1.999324984063775700,
+ 1.999314984534741100, 1.999304911496609700, 1.999294764949752100,
+ 1.999284544894541100,
+ 1.999274251331352400, 1.999263884260564600, 1.999253443682558900,
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+ 0.024351343298691951, 0.023967876083461924, 0.023584407987001611,
+ 0.023200939023409587,
+ 0.022817469206785804, 0.022433998551228459, 0.022050527070837558,
+ 0.021667054779711814,
+ 0.021283581691949955, 0.020900107821652084, 0.020516633182916549,
+ 0.020133157789843505,
+ 0.019749681656531803, 0.019366204797080316, 0.018982727225589285,
+ 0.018599248956157190,
+ 0.018215770002884327, 0.017832290379869671, 0.017448810101212228,
+ 0.017065329181012358,
+ 0.016681847633368677, 0.016298365472381587, 0.015914882712149747,
+ 0.015531399366773606,
+ 0.015147915450352307, 0.014764430976985016, 0.014380945960772247,
+ 0.013997460415812761,
+ 0.013613974356207112, 0.013230487796054543, 0.012847000749454314,
+ 0.012463513230507034,
+ 0.012080025253311559, 0.011696536831968529, 0.011313047980577277,
+ 0.010929558713237145,
+ 0.010546069044048827, 0.010162578987111254, 0.009779088556525145,
+ 0.009395597766389905,
+ 0.009012106630804949, 0.008628615163871038, 0.008245123379687167,
+ 0.007861631292354124,
+ 0.007478138915970929, 0.007094646264638386, 0.006711153352455981,
+ 0.006327660193523208,
+ 0.005944166801940901, 0.005560673191808128, 0.005177179377225743,
+ 0.004793685372293270,
+ 0.004410191191110246, 0.004026696847777542, 0.003643202356394263,
+ 0.003259707731061291,
+ 0.002876212985878184, 0.002492718134944503, 0.002109223192361147,
+ 0.001725728172227238,
+ 0.001342233088643682, 0.000958737955710053, 0.000575242787525925,
+ 0.000191747598192208,
+
+};
+
+/**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ * \par Normalizing factor:
+ * The normalizing factor is <code>sqrt(2/N)</code>, which depends on the size of transform <code>N</code>.
+ * Floating-point normalizing factors are mentioned in the table below for different DCT sizes:
+ * \image html dct4NormalizingF32Table.gif
+ */
+
+arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize)
+{
+ /* Initialize the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initializing the pointer array with the weight table base addresses of different lengths */
+ float32_t *twiddlePtr[4] =
+ { (float32_t *) Weights_128, (float32_t *) Weights_512,
+ (float32_t *) Weights_2048, (float32_t *) Weights_8192
+ };
+
+ /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+ float32_t *pCosFactor[4] =
+ { (float32_t *) cos_factors_128, (float32_t *) cos_factors_512,
+ (float32_t *) cos_factors_2048, (float32_t *) cos_factors_8192
+ };
+
+ /* Initialize the DCT4 length */
+ S->N = N;
+
+ /* Initialize the half of DCT4 length */
+ S->Nby2 = Nby2;
+
+ /* Initialize the DCT4 Normalizing factor */
+ S->normalize = normalize;
+
+ /* Initialize Real FFT Instance */
+ S->pRfft = S_RFFT;
+
+ /* Initialize Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ switch (N)
+ {
+ /* Initialize the table modifier values */
+ case 8192u:
+ S->pTwiddle = twiddlePtr[3];
+ S->pCosFactor = pCosFactor[3];
+ break;
+ case 2048u:
+ S->pTwiddle = twiddlePtr[2];
+ S->pCosFactor = pCosFactor[2];
+ break;
+ case 512u:
+ S->pTwiddle = twiddlePtr[1];
+ S->pCosFactor = pCosFactor[1];
+ break;
+ case 128u:
+ S->pTwiddle = twiddlePtr[0];
+ S->pCosFactor = pCosFactor[0];
+ break;
+ default:
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+
+ /* Initialize the RFFT/RIFFT */
+ arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0u, 1u);
+
+ /* return the status of DCT4 Init function */
+ return (status);
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_q15.c
new file mode 100644
index 000000000..1e0ad73d4
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_q15.c
@@ -0,0 +1,4284 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_init_q15.c
+*
+* Description: Initialization function of DCT-4 & IDCT4 Q15
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/*
+* @brief Weights Table
+*/
+
+/**
+* \par
+* Weights tables are generated using the formula : <pre>weights[n] = e^(-j*n*pi/(2*N))</pre>
+* \par
+* C command to generate the table
+* <pre>
+* for(i = 0; i< N; i++)
+* {
+* weights[2*i]= cos(i*c);
+* weights[(2*i)+1]= -sin(i * c);
+* } </pre>
+* \par
+* where <code>N</code> is the Number of weights to be calculated and <code>c</code> is <code>pi/(2*N)</code>
+* \par
+* Converted the output to q15 format by multiplying with 2^31 and saturated if required.
+* \par
+* In the tables below the real and imaginary values are placed alternatively, hence the
+* array length is <code>2*N</code>.
+*/
+
+static const q15_t ALIGN4 WeightsQ15_128[256] = {
+ 0x7fff, 0x0, 0x7ffd, 0xfe6e, 0x7ff6, 0xfcdc, 0x7fe9, 0xfb4a,
+ 0x7fd8, 0xf9b9, 0x7fc2, 0xf827, 0x7fa7, 0xf696, 0x7f87, 0xf505,
+ 0x7f62, 0xf375, 0x7f38, 0xf1e5, 0x7f09, 0xf055, 0x7ed5, 0xeec7,
+ 0x7e9d, 0xed38, 0x7e5f, 0xebab, 0x7e1d, 0xea1e, 0x7dd6, 0xe893,
+ 0x7d8a, 0xe708, 0x7d39, 0xe57e, 0x7ce3, 0xe3f5, 0x7c89, 0xe26d,
+ 0x7c29, 0xe0e7, 0x7bc5, 0xdf61, 0x7b5d, 0xdddd, 0x7aef, 0xdc5a,
+ 0x7a7d, 0xdad8, 0x7a05, 0xd958, 0x798a, 0xd7da, 0x7909, 0xd65d,
+ 0x7884, 0xd4e1, 0x77fa, 0xd368, 0x776c, 0xd1ef, 0x76d9, 0xd079,
+ 0x7641, 0xcf05, 0x75a5, 0xcd92, 0x7504, 0xcc22, 0x745f, 0xcab3,
+ 0x73b5, 0xc946, 0x7307, 0xc7dc, 0x7255, 0xc674, 0x719e, 0xc50e,
+ 0x70e2, 0xc3aa, 0x7023, 0xc248, 0x6f5f, 0xc0e9, 0x6e96, 0xbf8d,
+ 0x6dca, 0xbe32, 0x6cf9, 0xbcdb, 0x6c24, 0xbb86, 0x6b4a, 0xba33,
+ 0x6a6d, 0xb8e4, 0x698c, 0xb797, 0x68a6, 0xb64c, 0x67bd, 0xb505,
+ 0x66cf, 0xb3c1, 0x65dd, 0xb27f, 0x64e8, 0xb141, 0x63ef, 0xb005,
+ 0x62f2, 0xaecd, 0x61f1, 0xad97, 0x60ec, 0xac65, 0x5fe3, 0xab36,
+ 0x5ed7, 0xaa0b, 0x5dc7, 0xa8e3, 0x5cb4, 0xa7be, 0x5b9d, 0xa69c,
+ 0x5a82, 0xa57e, 0x5964, 0xa463, 0x5842, 0xa34c, 0x571d, 0xa239,
+ 0x55f5, 0xa129, 0x54ca, 0xa01d, 0x539b, 0x9f14, 0x5269, 0x9e0f,
+ 0x5133, 0x9d0e, 0x4ffb, 0x9c11, 0x4ebf, 0x9b18, 0x4d81, 0x9a23,
+ 0x4c3f, 0x9931, 0x4afb, 0x9843, 0x49b4, 0x975a, 0x4869, 0x9674,
+ 0x471c, 0x9593, 0x45cd, 0x94b6, 0x447a, 0x93dc, 0x4325, 0x9307,
+ 0x41ce, 0x9236, 0x4073, 0x916a, 0x3f17, 0x90a1, 0x3db8, 0x8fdd,
+ 0x3c56, 0x8f1e, 0x3af2, 0x8e62, 0x398c, 0x8dab, 0x3824, 0x8cf9,
+ 0x36ba, 0x8c4b, 0x354d, 0x8ba1, 0x33de, 0x8afc, 0x326e, 0x8a5b,
+ 0x30fb, 0x89bf, 0x2f87, 0x8927, 0x2e11, 0x8894, 0x2c98, 0x8806,
+ 0x2b1f, 0x877c, 0x29a3, 0x86f7, 0x2826, 0x8676, 0x26a8, 0x85fb,
+ 0x2528, 0x8583, 0x23a6, 0x8511, 0x2223, 0x84a3, 0x209f, 0x843b,
+ 0x1f19, 0x83d7, 0x1d93, 0x8377, 0x1c0b, 0x831d, 0x1a82, 0x82c7,
+ 0x18f8, 0x8276, 0x176d, 0x822a, 0x15e2, 0x81e3, 0x1455, 0x81a1,
+ 0x12c8, 0x8163, 0x1139, 0x812b, 0xfab, 0x80f7, 0xe1b, 0x80c8,
+ 0xc8b, 0x809e, 0xafb, 0x8079, 0x96a, 0x8059, 0x7d9, 0x803e,
+ 0x647, 0x8028, 0x4b6, 0x8017, 0x324, 0x800a, 0x192, 0x8003,
+};
+
+static const q15_t ALIGN4 WeightsQ15_512[1024] = {
+ 0x7fff, 0x0, 0x7fff, 0xff9c, 0x7fff, 0xff37, 0x7ffe, 0xfed3,
+ 0x7ffd, 0xfe6e, 0x7ffc, 0xfe0a, 0x7ffa, 0xfda5, 0x7ff8, 0xfd41,
+ 0x7ff6, 0xfcdc, 0x7ff3, 0xfc78, 0x7ff0, 0xfc13, 0x7fed, 0xfbaf,
+ 0x7fe9, 0xfb4a, 0x7fe5, 0xfae6, 0x7fe1, 0xfa81, 0x7fdd, 0xfa1d,
+ 0x7fd8, 0xf9b9, 0x7fd3, 0xf954, 0x7fce, 0xf8f0, 0x7fc8, 0xf88b,
+ 0x7fc2, 0xf827, 0x7fbc, 0xf7c3, 0x7fb5, 0xf75e, 0x7fae, 0xf6fa,
+ 0x7fa7, 0xf696, 0x7f9f, 0xf632, 0x7f97, 0xf5cd, 0x7f8f, 0xf569,
+ 0x7f87, 0xf505, 0x7f7e, 0xf4a1, 0x7f75, 0xf43d, 0x7f6b, 0xf3d9,
+ 0x7f62, 0xf375, 0x7f58, 0xf311, 0x7f4d, 0xf2ad, 0x7f43, 0xf249,
+ 0x7f38, 0xf1e5, 0x7f2d, 0xf181, 0x7f21, 0xf11d, 0x7f15, 0xf0b9,
+ 0x7f09, 0xf055, 0x7efd, 0xeff2, 0x7ef0, 0xef8e, 0x7ee3, 0xef2a,
+ 0x7ed5, 0xeec7, 0x7ec8, 0xee63, 0x7eba, 0xedff, 0x7eab, 0xed9c,
+ 0x7e9d, 0xed38, 0x7e8e, 0xecd5, 0x7e7f, 0xec72, 0x7e6f, 0xec0e,
+ 0x7e5f, 0xebab, 0x7e4f, 0xeb48, 0x7e3f, 0xeae5, 0x7e2e, 0xea81,
+ 0x7e1d, 0xea1e, 0x7e0c, 0xe9bb, 0x7dfa, 0xe958, 0x7de8, 0xe8f6,
+ 0x7dd6, 0xe893, 0x7dc3, 0xe830, 0x7db0, 0xe7cd, 0x7d9d, 0xe76a,
+ 0x7d8a, 0xe708, 0x7d76, 0xe6a5, 0x7d62, 0xe643, 0x7d4e, 0xe5e0,
+ 0x7d39, 0xe57e, 0x7d24, 0xe51c, 0x7d0f, 0xe4b9, 0x7cf9, 0xe457,
+ 0x7ce3, 0xe3f5, 0x7ccd, 0xe393, 0x7cb7, 0xe331, 0x7ca0, 0xe2cf,
+ 0x7c89, 0xe26d, 0x7c71, 0xe20b, 0x7c5a, 0xe1aa, 0x7c42, 0xe148,
+ 0x7c29, 0xe0e7, 0x7c11, 0xe085, 0x7bf8, 0xe024, 0x7bdf, 0xdfc2,
+ 0x7bc5, 0xdf61, 0x7bac, 0xdf00, 0x7b92, 0xde9f, 0x7b77, 0xde3e,
+ 0x7b5d, 0xdddd, 0x7b42, 0xdd7c, 0x7b26, 0xdd1b, 0x7b0b, 0xdcbb,
+ 0x7aef, 0xdc5a, 0x7ad3, 0xdbf9, 0x7ab6, 0xdb99, 0x7a9a, 0xdb39,
+ 0x7a7d, 0xdad8, 0x7a5f, 0xda78, 0x7a42, 0xda18, 0x7a24, 0xd9b8,
+ 0x7a05, 0xd958, 0x79e7, 0xd8f9, 0x79c8, 0xd899, 0x79a9, 0xd839,
+ 0x798a, 0xd7da, 0x796a, 0xd77a, 0x794a, 0xd71b, 0x792a, 0xd6bc,
+ 0x7909, 0xd65d, 0x78e8, 0xd5fe, 0x78c7, 0xd59f, 0x78a6, 0xd540,
+ 0x7884, 0xd4e1, 0x7862, 0xd483, 0x7840, 0xd424, 0x781d, 0xd3c6,
+ 0x77fa, 0xd368, 0x77d7, 0xd309, 0x77b4, 0xd2ab, 0x7790, 0xd24d,
+ 0x776c, 0xd1ef, 0x7747, 0xd192, 0x7723, 0xd134, 0x76fe, 0xd0d7,
+ 0x76d9, 0xd079, 0x76b3, 0xd01c, 0x768e, 0xcfbf, 0x7668, 0xcf62,
+ 0x7641, 0xcf05, 0x761b, 0xcea8, 0x75f4, 0xce4b, 0x75cc, 0xcdef,
+ 0x75a5, 0xcd92, 0x757d, 0xcd36, 0x7555, 0xccda, 0x752d, 0xcc7e,
+ 0x7504, 0xcc22, 0x74db, 0xcbc6, 0x74b2, 0xcb6a, 0x7489, 0xcb0e,
+ 0x745f, 0xcab3, 0x7435, 0xca58, 0x740b, 0xc9fc, 0x73e0, 0xc9a1,
+ 0x73b5, 0xc946, 0x738a, 0xc8ec, 0x735f, 0xc891, 0x7333, 0xc836,
+ 0x7307, 0xc7dc, 0x72db, 0xc782, 0x72af, 0xc728, 0x7282, 0xc6ce,
+ 0x7255, 0xc674, 0x7227, 0xc61a, 0x71fa, 0xc5c0, 0x71cc, 0xc567,
+ 0x719e, 0xc50e, 0x716f, 0xc4b4, 0x7141, 0xc45b, 0x7112, 0xc403,
+ 0x70e2, 0xc3aa, 0x70b3, 0xc351, 0x7083, 0xc2f9, 0x7053, 0xc2a0,
+ 0x7023, 0xc248, 0x6ff2, 0xc1f0, 0x6fc1, 0xc198, 0x6f90, 0xc141,
+ 0x6f5f, 0xc0e9, 0x6f2d, 0xc092, 0x6efb, 0xc03b, 0x6ec9, 0xbfe3,
+ 0x6e96, 0xbf8d, 0x6e63, 0xbf36, 0x6e30, 0xbedf, 0x6dfd, 0xbe89,
+ 0x6dca, 0xbe32, 0x6d96, 0xbddc, 0x6d62, 0xbd86, 0x6d2d, 0xbd30,
+ 0x6cf9, 0xbcdb, 0x6cc4, 0xbc85, 0x6c8f, 0xbc30, 0x6c59, 0xbbdb,
+ 0x6c24, 0xbb86, 0x6bee, 0xbb31, 0x6bb8, 0xbadc, 0x6b81, 0xba88,
+ 0x6b4a, 0xba33, 0x6b13, 0xb9df, 0x6adc, 0xb98b, 0x6aa5, 0xb937,
+ 0x6a6d, 0xb8e4, 0x6a35, 0xb890, 0x69fd, 0xb83d, 0x69c4, 0xb7ea,
+ 0x698c, 0xb797, 0x6953, 0xb744, 0x6919, 0xb6f1, 0x68e0, 0xb69f,
+ 0x68a6, 0xb64c, 0x686c, 0xb5fa, 0x6832, 0xb5a8, 0x67f7, 0xb557,
+ 0x67bd, 0xb505, 0x6782, 0xb4b4, 0x6746, 0xb462, 0x670b, 0xb411,
+ 0x66cf, 0xb3c1, 0x6693, 0xb370, 0x6657, 0xb31f, 0x661a, 0xb2cf,
+ 0x65dd, 0xb27f, 0x65a0, 0xb22f, 0x6563, 0xb1df, 0x6526, 0xb190,
+ 0x64e8, 0xb141, 0x64aa, 0xb0f1, 0x646c, 0xb0a2, 0x642d, 0xb054,
+ 0x63ef, 0xb005, 0x63b0, 0xafb7, 0x6371, 0xaf69, 0x6331, 0xaf1b,
+ 0x62f2, 0xaecd, 0x62b2, 0xae7f, 0x6271, 0xae32, 0x6231, 0xade4,
+ 0x61f1, 0xad97, 0x61b0, 0xad4b, 0x616f, 0xacfe, 0x612d, 0xacb2,
+ 0x60ec, 0xac65, 0x60aa, 0xac19, 0x6068, 0xabcd, 0x6026, 0xab82,
+ 0x5fe3, 0xab36, 0x5fa0, 0xaaeb, 0x5f5e, 0xaaa0, 0x5f1a, 0xaa55,
+ 0x5ed7, 0xaa0b, 0x5e93, 0xa9c0, 0x5e50, 0xa976, 0x5e0b, 0xa92c,
+ 0x5dc7, 0xa8e3, 0x5d83, 0xa899, 0x5d3e, 0xa850, 0x5cf9, 0xa807,
+ 0x5cb4, 0xa7be, 0x5c6e, 0xa775, 0x5c29, 0xa72c, 0x5be3, 0xa6e4,
+ 0x5b9d, 0xa69c, 0x5b56, 0xa654, 0x5b10, 0xa60d, 0x5ac9, 0xa5c5,
+ 0x5a82, 0xa57e, 0x5a3b, 0xa537, 0x59f3, 0xa4f0, 0x59ac, 0xa4aa,
+ 0x5964, 0xa463, 0x591c, 0xa41d, 0x58d4, 0xa3d7, 0x588b, 0xa392,
+ 0x5842, 0xa34c, 0x57f9, 0xa307, 0x57b0, 0xa2c2, 0x5767, 0xa27d,
+ 0x571d, 0xa239, 0x56d4, 0xa1f5, 0x568a, 0xa1b0, 0x5640, 0xa16d,
+ 0x55f5, 0xa129, 0x55ab, 0xa0e6, 0x5560, 0xa0a2, 0x5515, 0xa060,
+ 0x54ca, 0xa01d, 0x547e, 0x9fda, 0x5433, 0x9f98, 0x53e7, 0x9f56,
+ 0x539b, 0x9f14, 0x534e, 0x9ed3, 0x5302, 0x9e91, 0x52b5, 0x9e50,
+ 0x5269, 0x9e0f, 0x521c, 0x9dcf, 0x51ce, 0x9d8f, 0x5181, 0x9d4e,
+ 0x5133, 0x9d0e, 0x50e5, 0x9ccf, 0x5097, 0x9c8f, 0x5049, 0x9c50,
+ 0x4ffb, 0x9c11, 0x4fac, 0x9bd3, 0x4f5e, 0x9b94, 0x4f0f, 0x9b56,
+ 0x4ebf, 0x9b18, 0x4e70, 0x9ada, 0x4e21, 0x9a9d, 0x4dd1, 0x9a60,
+ 0x4d81, 0x9a23, 0x4d31, 0x99e6, 0x4ce1, 0x99a9, 0x4c90, 0x996d,
+ 0x4c3f, 0x9931, 0x4bef, 0x98f5, 0x4b9e, 0x98ba, 0x4b4c, 0x987e,
+ 0x4afb, 0x9843, 0x4aa9, 0x9809, 0x4a58, 0x97ce, 0x4a06, 0x9794,
+ 0x49b4, 0x975a, 0x4961, 0x9720, 0x490f, 0x96e7, 0x48bc, 0x96ad,
+ 0x4869, 0x9674, 0x4816, 0x963c, 0x47c3, 0x9603, 0x4770, 0x95cb,
+ 0x471c, 0x9593, 0x46c9, 0x955b, 0x4675, 0x9524, 0x4621, 0x94ed,
+ 0x45cd, 0x94b6, 0x4578, 0x947f, 0x4524, 0x9448, 0x44cf, 0x9412,
+ 0x447a, 0x93dc, 0x4425, 0x93a7, 0x43d0, 0x9371, 0x437b, 0x933c,
+ 0x4325, 0x9307, 0x42d0, 0x92d3, 0x427a, 0x929e, 0x4224, 0x926a,
+ 0x41ce, 0x9236, 0x4177, 0x9203, 0x4121, 0x91d0, 0x40ca, 0x919d,
+ 0x4073, 0x916a, 0x401d, 0x9137, 0x3fc5, 0x9105, 0x3f6e, 0x90d3,
+ 0x3f17, 0x90a1, 0x3ebf, 0x9070, 0x3e68, 0x903f, 0x3e10, 0x900e,
+ 0x3db8, 0x8fdd, 0x3d60, 0x8fad, 0x3d07, 0x8f7d, 0x3caf, 0x8f4d,
+ 0x3c56, 0x8f1e, 0x3bfd, 0x8eee, 0x3ba5, 0x8ebf, 0x3b4c, 0x8e91,
+ 0x3af2, 0x8e62, 0x3a99, 0x8e34, 0x3a40, 0x8e06, 0x39e6, 0x8dd9,
+ 0x398c, 0x8dab, 0x3932, 0x8d7e, 0x38d8, 0x8d51, 0x387e, 0x8d25,
+ 0x3824, 0x8cf9, 0x37ca, 0x8ccd, 0x376f, 0x8ca1, 0x3714, 0x8c76,
+ 0x36ba, 0x8c4b, 0x365f, 0x8c20, 0x3604, 0x8bf5, 0x35a8, 0x8bcb,
+ 0x354d, 0x8ba1, 0x34f2, 0x8b77, 0x3496, 0x8b4e, 0x343a, 0x8b25,
+ 0x33de, 0x8afc, 0x3382, 0x8ad3, 0x3326, 0x8aab, 0x32ca, 0x8a83,
+ 0x326e, 0x8a5b, 0x3211, 0x8a34, 0x31b5, 0x8a0c, 0x3158, 0x89e5,
+ 0x30fb, 0x89bf, 0x309e, 0x8998, 0x3041, 0x8972, 0x2fe4, 0x894d,
+ 0x2f87, 0x8927, 0x2f29, 0x8902, 0x2ecc, 0x88dd, 0x2e6e, 0x88b9,
+ 0x2e11, 0x8894, 0x2db3, 0x8870, 0x2d55, 0x884c, 0x2cf7, 0x8829,
+ 0x2c98, 0x8806, 0x2c3a, 0x87e3, 0x2bdc, 0x87c0, 0x2b7d, 0x879e,
+ 0x2b1f, 0x877c, 0x2ac0, 0x875a, 0x2a61, 0x8739, 0x2a02, 0x8718,
+ 0x29a3, 0x86f7, 0x2944, 0x86d6, 0x28e5, 0x86b6, 0x2886, 0x8696,
+ 0x2826, 0x8676, 0x27c7, 0x8657, 0x2767, 0x8638, 0x2707, 0x8619,
+ 0x26a8, 0x85fb, 0x2648, 0x85dc, 0x25e8, 0x85be, 0x2588, 0x85a1,
+ 0x2528, 0x8583, 0x24c7, 0x8566, 0x2467, 0x854a, 0x2407, 0x852d,
+ 0x23a6, 0x8511, 0x2345, 0x84f5, 0x22e5, 0x84da, 0x2284, 0x84be,
+ 0x2223, 0x84a3, 0x21c2, 0x8489, 0x2161, 0x846e, 0x2100, 0x8454,
+ 0x209f, 0x843b, 0x203e, 0x8421, 0x1fdc, 0x8408, 0x1f7b, 0x83ef,
+ 0x1f19, 0x83d7, 0x1eb8, 0x83be, 0x1e56, 0x83a6, 0x1df5, 0x838f,
+ 0x1d93, 0x8377, 0x1d31, 0x8360, 0x1ccf, 0x8349, 0x1c6d, 0x8333,
+ 0x1c0b, 0x831d, 0x1ba9, 0x8307, 0x1b47, 0x82f1, 0x1ae4, 0x82dc,
+ 0x1a82, 0x82c7, 0x1a20, 0x82b2, 0x19bd, 0x829e, 0x195b, 0x828a,
+ 0x18f8, 0x8276, 0x1896, 0x8263, 0x1833, 0x8250, 0x17d0, 0x823d,
+ 0x176d, 0x822a, 0x170a, 0x8218, 0x16a8, 0x8206, 0x1645, 0x81f4,
+ 0x15e2, 0x81e3, 0x157f, 0x81d2, 0x151b, 0x81c1, 0x14b8, 0x81b1,
+ 0x1455, 0x81a1, 0x13f2, 0x8191, 0x138e, 0x8181, 0x132b, 0x8172,
+ 0x12c8, 0x8163, 0x1264, 0x8155, 0x1201, 0x8146, 0x119d, 0x8138,
+ 0x1139, 0x812b, 0x10d6, 0x811d, 0x1072, 0x8110, 0x100e, 0x8103,
+ 0xfab, 0x80f7, 0xf47, 0x80eb, 0xee3, 0x80df, 0xe7f, 0x80d3,
+ 0xe1b, 0x80c8, 0xdb7, 0x80bd, 0xd53, 0x80b3, 0xcef, 0x80a8,
+ 0xc8b, 0x809e, 0xc27, 0x8095, 0xbc3, 0x808b, 0xb5f, 0x8082,
+ 0xafb, 0x8079, 0xa97, 0x8071, 0xa33, 0x8069, 0x9ce, 0x8061,
+ 0x96a, 0x8059, 0x906, 0x8052, 0x8a2, 0x804b, 0x83d, 0x8044,
+ 0x7d9, 0x803e, 0x775, 0x8038, 0x710, 0x8032, 0x6ac, 0x802d,
+ 0x647, 0x8028, 0x5e3, 0x8023, 0x57f, 0x801f, 0x51a, 0x801b,
+ 0x4b6, 0x8017, 0x451, 0x8013, 0x3ed, 0x8010, 0x388, 0x800d,
+ 0x324, 0x800a, 0x2bf, 0x8008, 0x25b, 0x8006, 0x1f6, 0x8004,
+ 0x192, 0x8003, 0x12d, 0x8002, 0xc9, 0x8001, 0x64, 0x8001,
+};
+
+static const q15_t ALIGN4 WeightsQ15_2048[4096] = {
+ 0x7fff, 0x0, 0x7fff, 0xffe7, 0x7fff, 0xffce, 0x7fff, 0xffb5,
+ 0x7fff, 0xff9c, 0x7fff, 0xff83, 0x7fff, 0xff6a, 0x7fff, 0xff51,
+ 0x7fff, 0xff37, 0x7fff, 0xff1e, 0x7fff, 0xff05, 0x7ffe, 0xfeec,
+ 0x7ffe, 0xfed3, 0x7ffe, 0xfeba, 0x7ffe, 0xfea1, 0x7ffd, 0xfe88,
+ 0x7ffd, 0xfe6e, 0x7ffd, 0xfe55, 0x7ffc, 0xfe3c, 0x7ffc, 0xfe23,
+ 0x7ffc, 0xfe0a, 0x7ffb, 0xfdf1, 0x7ffb, 0xfdd8, 0x7ffa, 0xfdbe,
+ 0x7ffa, 0xfda5, 0x7ff9, 0xfd8c, 0x7ff9, 0xfd73, 0x7ff8, 0xfd5a,
+ 0x7ff8, 0xfd41, 0x7ff7, 0xfd28, 0x7ff7, 0xfd0f, 0x7ff6, 0xfcf5,
+ 0x7ff6, 0xfcdc, 0x7ff5, 0xfcc3, 0x7ff4, 0xfcaa, 0x7ff4, 0xfc91,
+ 0x7ff3, 0xfc78, 0x7ff2, 0xfc5f, 0x7ff2, 0xfc46, 0x7ff1, 0xfc2c,
+ 0x7ff0, 0xfc13, 0x7fef, 0xfbfa, 0x7fee, 0xfbe1, 0x7fee, 0xfbc8,
+ 0x7fed, 0xfbaf, 0x7fec, 0xfb96, 0x7feb, 0xfb7d, 0x7fea, 0xfb64,
+ 0x7fe9, 0xfb4a, 0x7fe8, 0xfb31, 0x7fe7, 0xfb18, 0x7fe6, 0xfaff,
+ 0x7fe5, 0xfae6, 0x7fe4, 0xfacd, 0x7fe3, 0xfab4, 0x7fe2, 0xfa9b,
+ 0x7fe1, 0xfa81, 0x7fe0, 0xfa68, 0x7fdf, 0xfa4f, 0x7fde, 0xfa36,
+ 0x7fdd, 0xfa1d, 0x7fdc, 0xfa04, 0x7fda, 0xf9eb, 0x7fd9, 0xf9d2,
+ 0x7fd8, 0xf9b9, 0x7fd7, 0xf9a0, 0x7fd6, 0xf986, 0x7fd4, 0xf96d,
+ 0x7fd3, 0xf954, 0x7fd2, 0xf93b, 0x7fd0, 0xf922, 0x7fcf, 0xf909,
+ 0x7fce, 0xf8f0, 0x7fcc, 0xf8d7, 0x7fcb, 0xf8be, 0x7fc9, 0xf8a5,
+ 0x7fc8, 0xf88b, 0x7fc6, 0xf872, 0x7fc5, 0xf859, 0x7fc3, 0xf840,
+ 0x7fc2, 0xf827, 0x7fc0, 0xf80e, 0x7fbf, 0xf7f5, 0x7fbd, 0xf7dc,
+ 0x7fbc, 0xf7c3, 0x7fba, 0xf7aa, 0x7fb8, 0xf791, 0x7fb7, 0xf778,
+ 0x7fb5, 0xf75e, 0x7fb3, 0xf745, 0x7fb1, 0xf72c, 0x7fb0, 0xf713,
+ 0x7fae, 0xf6fa, 0x7fac, 0xf6e1, 0x7faa, 0xf6c8, 0x7fa9, 0xf6af,
+ 0x7fa7, 0xf696, 0x7fa5, 0xf67d, 0x7fa3, 0xf664, 0x7fa1, 0xf64b,
+ 0x7f9f, 0xf632, 0x7f9d, 0xf619, 0x7f9b, 0xf600, 0x7f99, 0xf5e7,
+ 0x7f97, 0xf5cd, 0x7f95, 0xf5b4, 0x7f93, 0xf59b, 0x7f91, 0xf582,
+ 0x7f8f, 0xf569, 0x7f8d, 0xf550, 0x7f8b, 0xf537, 0x7f89, 0xf51e,
+ 0x7f87, 0xf505, 0x7f85, 0xf4ec, 0x7f82, 0xf4d3, 0x7f80, 0xf4ba,
+ 0x7f7e, 0xf4a1, 0x7f7c, 0xf488, 0x7f79, 0xf46f, 0x7f77, 0xf456,
+ 0x7f75, 0xf43d, 0x7f72, 0xf424, 0x7f70, 0xf40b, 0x7f6e, 0xf3f2,
+ 0x7f6b, 0xf3d9, 0x7f69, 0xf3c0, 0x7f67, 0xf3a7, 0x7f64, 0xf38e,
+ 0x7f62, 0xf375, 0x7f5f, 0xf35c, 0x7f5d, 0xf343, 0x7f5a, 0xf32a,
+ 0x7f58, 0xf311, 0x7f55, 0xf2f8, 0x7f53, 0xf2df, 0x7f50, 0xf2c6,
+ 0x7f4d, 0xf2ad, 0x7f4b, 0xf294, 0x7f48, 0xf27b, 0x7f45, 0xf262,
+ 0x7f43, 0xf249, 0x7f40, 0xf230, 0x7f3d, 0xf217, 0x7f3b, 0xf1fe,
+ 0x7f38, 0xf1e5, 0x7f35, 0xf1cc, 0x7f32, 0xf1b3, 0x7f2f, 0xf19a,
+ 0x7f2d, 0xf181, 0x7f2a, 0xf168, 0x7f27, 0xf14f, 0x7f24, 0xf136,
+ 0x7f21, 0xf11d, 0x7f1e, 0xf104, 0x7f1b, 0xf0eb, 0x7f18, 0xf0d2,
+ 0x7f15, 0xf0b9, 0x7f12, 0xf0a0, 0x7f0f, 0xf087, 0x7f0c, 0xf06e,
+ 0x7f09, 0xf055, 0x7f06, 0xf03c, 0x7f03, 0xf023, 0x7f00, 0xf00b,
+ 0x7efd, 0xeff2, 0x7ef9, 0xefd9, 0x7ef6, 0xefc0, 0x7ef3, 0xefa7,
+ 0x7ef0, 0xef8e, 0x7eed, 0xef75, 0x7ee9, 0xef5c, 0x7ee6, 0xef43,
+ 0x7ee3, 0xef2a, 0x7edf, 0xef11, 0x7edc, 0xeef8, 0x7ed9, 0xeedf,
+ 0x7ed5, 0xeec7, 0x7ed2, 0xeeae, 0x7ecf, 0xee95, 0x7ecb, 0xee7c,
+ 0x7ec8, 0xee63, 0x7ec4, 0xee4a, 0x7ec1, 0xee31, 0x7ebd, 0xee18,
+ 0x7eba, 0xedff, 0x7eb6, 0xede7, 0x7eb3, 0xedce, 0x7eaf, 0xedb5,
+ 0x7eab, 0xed9c, 0x7ea8, 0xed83, 0x7ea4, 0xed6a, 0x7ea1, 0xed51,
+ 0x7e9d, 0xed38, 0x7e99, 0xed20, 0x7e95, 0xed07, 0x7e92, 0xecee,
+ 0x7e8e, 0xecd5, 0x7e8a, 0xecbc, 0x7e86, 0xeca3, 0x7e83, 0xec8a,
+ 0x7e7f, 0xec72, 0x7e7b, 0xec59, 0x7e77, 0xec40, 0x7e73, 0xec27,
+ 0x7e6f, 0xec0e, 0x7e6b, 0xebf5, 0x7e67, 0xebdd, 0x7e63, 0xebc4,
+ 0x7e5f, 0xebab, 0x7e5b, 0xeb92, 0x7e57, 0xeb79, 0x7e53, 0xeb61,
+ 0x7e4f, 0xeb48, 0x7e4b, 0xeb2f, 0x7e47, 0xeb16, 0x7e43, 0xeafd,
+ 0x7e3f, 0xeae5, 0x7e3b, 0xeacc, 0x7e37, 0xeab3, 0x7e32, 0xea9a,
+ 0x7e2e, 0xea81, 0x7e2a, 0xea69, 0x7e26, 0xea50, 0x7e21, 0xea37,
+ 0x7e1d, 0xea1e, 0x7e19, 0xea06, 0x7e14, 0xe9ed, 0x7e10, 0xe9d4,
+ 0x7e0c, 0xe9bb, 0x7e07, 0xe9a3, 0x7e03, 0xe98a, 0x7dff, 0xe971,
+ 0x7dfa, 0xe958, 0x7df6, 0xe940, 0x7df1, 0xe927, 0x7ded, 0xe90e,
+ 0x7de8, 0xe8f6, 0x7de4, 0xe8dd, 0x7ddf, 0xe8c4, 0x7dda, 0xe8ab,
+ 0x7dd6, 0xe893, 0x7dd1, 0xe87a, 0x7dcd, 0xe861, 0x7dc8, 0xe849,
+ 0x7dc3, 0xe830, 0x7dbf, 0xe817, 0x7dba, 0xe7fe, 0x7db5, 0xe7e6,
+ 0x7db0, 0xe7cd, 0x7dac, 0xe7b4, 0x7da7, 0xe79c, 0x7da2, 0xe783,
+ 0x7d9d, 0xe76a, 0x7d98, 0xe752, 0x7d94, 0xe739, 0x7d8f, 0xe720,
+ 0x7d8a, 0xe708, 0x7d85, 0xe6ef, 0x7d80, 0xe6d6, 0x7d7b, 0xe6be,
+ 0x7d76, 0xe6a5, 0x7d71, 0xe68d, 0x7d6c, 0xe674, 0x7d67, 0xe65b,
+ 0x7d62, 0xe643, 0x7d5d, 0xe62a, 0x7d58, 0xe611, 0x7d53, 0xe5f9,
+ 0x7d4e, 0xe5e0, 0x7d49, 0xe5c8, 0x7d43, 0xe5af, 0x7d3e, 0xe596,
+ 0x7d39, 0xe57e, 0x7d34, 0xe565, 0x7d2f, 0xe54d, 0x7d29, 0xe534,
+ 0x7d24, 0xe51c, 0x7d1f, 0xe503, 0x7d19, 0xe4ea, 0x7d14, 0xe4d2,
+ 0x7d0f, 0xe4b9, 0x7d09, 0xe4a1, 0x7d04, 0xe488, 0x7cff, 0xe470,
+ 0x7cf9, 0xe457, 0x7cf4, 0xe43f, 0x7cee, 0xe426, 0x7ce9, 0xe40e,
+ 0x7ce3, 0xe3f5, 0x7cde, 0xe3dc, 0x7cd8, 0xe3c4, 0x7cd3, 0xe3ab,
+ 0x7ccd, 0xe393, 0x7cc8, 0xe37a, 0x7cc2, 0xe362, 0x7cbc, 0xe349,
+ 0x7cb7, 0xe331, 0x7cb1, 0xe318, 0x7cab, 0xe300, 0x7ca6, 0xe2e8,
+ 0x7ca0, 0xe2cf, 0x7c9a, 0xe2b7, 0x7c94, 0xe29e, 0x7c8f, 0xe286,
+ 0x7c89, 0xe26d, 0x7c83, 0xe255, 0x7c7d, 0xe23c, 0x7c77, 0xe224,
+ 0x7c71, 0xe20b, 0x7c6c, 0xe1f3, 0x7c66, 0xe1db, 0x7c60, 0xe1c2,
+ 0x7c5a, 0xe1aa, 0x7c54, 0xe191, 0x7c4e, 0xe179, 0x7c48, 0xe160,
+ 0x7c42, 0xe148, 0x7c3c, 0xe130, 0x7c36, 0xe117, 0x7c30, 0xe0ff,
+ 0x7c29, 0xe0e7, 0x7c23, 0xe0ce, 0x7c1d, 0xe0b6, 0x7c17, 0xe09d,
+ 0x7c11, 0xe085, 0x7c0b, 0xe06d, 0x7c05, 0xe054, 0x7bfe, 0xe03c,
+ 0x7bf8, 0xe024, 0x7bf2, 0xe00b, 0x7beb, 0xdff3, 0x7be5, 0xdfdb,
+ 0x7bdf, 0xdfc2, 0x7bd9, 0xdfaa, 0x7bd2, 0xdf92, 0x7bcc, 0xdf79,
+ 0x7bc5, 0xdf61, 0x7bbf, 0xdf49, 0x7bb9, 0xdf30, 0x7bb2, 0xdf18,
+ 0x7bac, 0xdf00, 0x7ba5, 0xdee8, 0x7b9f, 0xdecf, 0x7b98, 0xdeb7,
+ 0x7b92, 0xde9f, 0x7b8b, 0xde87, 0x7b84, 0xde6e, 0x7b7e, 0xde56,
+ 0x7b77, 0xde3e, 0x7b71, 0xde26, 0x7b6a, 0xde0d, 0x7b63, 0xddf5,
+ 0x7b5d, 0xdddd, 0x7b56, 0xddc5, 0x7b4f, 0xddac, 0x7b48, 0xdd94,
+ 0x7b42, 0xdd7c, 0x7b3b, 0xdd64, 0x7b34, 0xdd4c, 0x7b2d, 0xdd33,
+ 0x7b26, 0xdd1b, 0x7b1f, 0xdd03, 0x7b19, 0xdceb, 0x7b12, 0xdcd3,
+ 0x7b0b, 0xdcbb, 0x7b04, 0xdca2, 0x7afd, 0xdc8a, 0x7af6, 0xdc72,
+ 0x7aef, 0xdc5a, 0x7ae8, 0xdc42, 0x7ae1, 0xdc2a, 0x7ada, 0xdc12,
+ 0x7ad3, 0xdbf9, 0x7acc, 0xdbe1, 0x7ac5, 0xdbc9, 0x7abd, 0xdbb1,
+ 0x7ab6, 0xdb99, 0x7aaf, 0xdb81, 0x7aa8, 0xdb69, 0x7aa1, 0xdb51,
+ 0x7a9a, 0xdb39, 0x7a92, 0xdb21, 0x7a8b, 0xdb09, 0x7a84, 0xdaf1,
+ 0x7a7d, 0xdad8, 0x7a75, 0xdac0, 0x7a6e, 0xdaa8, 0x7a67, 0xda90,
+ 0x7a5f, 0xda78, 0x7a58, 0xda60, 0x7a50, 0xda48, 0x7a49, 0xda30,
+ 0x7a42, 0xda18, 0x7a3a, 0xda00, 0x7a33, 0xd9e8, 0x7a2b, 0xd9d0,
+ 0x7a24, 0xd9b8, 0x7a1c, 0xd9a0, 0x7a15, 0xd988, 0x7a0d, 0xd970,
+ 0x7a05, 0xd958, 0x79fe, 0xd940, 0x79f6, 0xd928, 0x79ef, 0xd911,
+ 0x79e7, 0xd8f9, 0x79df, 0xd8e1, 0x79d8, 0xd8c9, 0x79d0, 0xd8b1,
+ 0x79c8, 0xd899, 0x79c0, 0xd881, 0x79b9, 0xd869, 0x79b1, 0xd851,
+ 0x79a9, 0xd839, 0x79a1, 0xd821, 0x7999, 0xd80a, 0x7992, 0xd7f2,
+ 0x798a, 0xd7da, 0x7982, 0xd7c2, 0x797a, 0xd7aa, 0x7972, 0xd792,
+ 0x796a, 0xd77a, 0x7962, 0xd763, 0x795a, 0xd74b, 0x7952, 0xd733,
+ 0x794a, 0xd71b, 0x7942, 0xd703, 0x793a, 0xd6eb, 0x7932, 0xd6d4,
+ 0x792a, 0xd6bc, 0x7922, 0xd6a4, 0x7919, 0xd68c, 0x7911, 0xd675,
+ 0x7909, 0xd65d, 0x7901, 0xd645, 0x78f9, 0xd62d, 0x78f1, 0xd615,
+ 0x78e8, 0xd5fe, 0x78e0, 0xd5e6, 0x78d8, 0xd5ce, 0x78cf, 0xd5b7,
+ 0x78c7, 0xd59f, 0x78bf, 0xd587, 0x78b6, 0xd56f, 0x78ae, 0xd558,
+ 0x78a6, 0xd540, 0x789d, 0xd528, 0x7895, 0xd511, 0x788c, 0xd4f9,
+ 0x7884, 0xd4e1, 0x787c, 0xd4ca, 0x7873, 0xd4b2, 0x786b, 0xd49a,
+ 0x7862, 0xd483, 0x7859, 0xd46b, 0x7851, 0xd453, 0x7848, 0xd43c,
+ 0x7840, 0xd424, 0x7837, 0xd40d, 0x782e, 0xd3f5, 0x7826, 0xd3dd,
+ 0x781d, 0xd3c6, 0x7814, 0xd3ae, 0x780c, 0xd397, 0x7803, 0xd37f,
+ 0x77fa, 0xd368, 0x77f1, 0xd350, 0x77e9, 0xd338, 0x77e0, 0xd321,
+ 0x77d7, 0xd309, 0x77ce, 0xd2f2, 0x77c5, 0xd2da, 0x77bc, 0xd2c3,
+ 0x77b4, 0xd2ab, 0x77ab, 0xd294, 0x77a2, 0xd27c, 0x7799, 0xd265,
+ 0x7790, 0xd24d, 0x7787, 0xd236, 0x777e, 0xd21e, 0x7775, 0xd207,
+ 0x776c, 0xd1ef, 0x7763, 0xd1d8, 0x775a, 0xd1c1, 0x7751, 0xd1a9,
+ 0x7747, 0xd192, 0x773e, 0xd17a, 0x7735, 0xd163, 0x772c, 0xd14b,
+ 0x7723, 0xd134, 0x771a, 0xd11d, 0x7710, 0xd105, 0x7707, 0xd0ee,
+ 0x76fe, 0xd0d7, 0x76f5, 0xd0bf, 0x76eb, 0xd0a8, 0x76e2, 0xd091,
+ 0x76d9, 0xd079, 0x76cf, 0xd062, 0x76c6, 0xd04b, 0x76bd, 0xd033,
+ 0x76b3, 0xd01c, 0x76aa, 0xd005, 0x76a0, 0xcfed, 0x7697, 0xcfd6,
+ 0x768e, 0xcfbf, 0x7684, 0xcfa7, 0x767b, 0xcf90, 0x7671, 0xcf79,
+ 0x7668, 0xcf62, 0x765e, 0xcf4a, 0x7654, 0xcf33, 0x764b, 0xcf1c,
+ 0x7641, 0xcf05, 0x7638, 0xceee, 0x762e, 0xced6, 0x7624, 0xcebf,
+ 0x761b, 0xcea8, 0x7611, 0xce91, 0x7607, 0xce7a, 0x75fd, 0xce62,
+ 0x75f4, 0xce4b, 0x75ea, 0xce34, 0x75e0, 0xce1d, 0x75d6, 0xce06,
+ 0x75cc, 0xcdef, 0x75c3, 0xcdd8, 0x75b9, 0xcdc0, 0x75af, 0xcda9,
+ 0x75a5, 0xcd92, 0x759b, 0xcd7b, 0x7591, 0xcd64, 0x7587, 0xcd4d,
+ 0x757d, 0xcd36, 0x7573, 0xcd1f, 0x7569, 0xcd08, 0x755f, 0xccf1,
+ 0x7555, 0xccda, 0x754b, 0xccc3, 0x7541, 0xccac, 0x7537, 0xcc95,
+ 0x752d, 0xcc7e, 0x7523, 0xcc67, 0x7519, 0xcc50, 0x750f, 0xcc39,
+ 0x7504, 0xcc22, 0x74fa, 0xcc0b, 0x74f0, 0xcbf4, 0x74e6, 0xcbdd,
+ 0x74db, 0xcbc6, 0x74d1, 0xcbaf, 0x74c7, 0xcb98, 0x74bd, 0xcb81,
+ 0x74b2, 0xcb6a, 0x74a8, 0xcb53, 0x749e, 0xcb3c, 0x7493, 0xcb25,
+ 0x7489, 0xcb0e, 0x747e, 0xcaf8, 0x7474, 0xcae1, 0x746a, 0xcaca,
+ 0x745f, 0xcab3, 0x7455, 0xca9c, 0x744a, 0xca85, 0x7440, 0xca6e,
+ 0x7435, 0xca58, 0x742b, 0xca41, 0x7420, 0xca2a, 0x7415, 0xca13,
+ 0x740b, 0xc9fc, 0x7400, 0xc9e6, 0x73f6, 0xc9cf, 0x73eb, 0xc9b8,
+ 0x73e0, 0xc9a1, 0x73d6, 0xc98b, 0x73cb, 0xc974, 0x73c0, 0xc95d,
+ 0x73b5, 0xc946, 0x73ab, 0xc930, 0x73a0, 0xc919, 0x7395, 0xc902,
+ 0x738a, 0xc8ec, 0x737f, 0xc8d5, 0x7375, 0xc8be, 0x736a, 0xc8a8,
+ 0x735f, 0xc891, 0x7354, 0xc87a, 0x7349, 0xc864, 0x733e, 0xc84d,
+ 0x7333, 0xc836, 0x7328, 0xc820, 0x731d, 0xc809, 0x7312, 0xc7f3,
+ 0x7307, 0xc7dc, 0x72fc, 0xc7c5, 0x72f1, 0xc7af, 0x72e6, 0xc798,
+ 0x72db, 0xc782, 0x72d0, 0xc76b, 0x72c5, 0xc755, 0x72ba, 0xc73e,
+ 0x72af, 0xc728, 0x72a3, 0xc711, 0x7298, 0xc6fa, 0x728d, 0xc6e4,
+ 0x7282, 0xc6ce, 0x7276, 0xc6b7, 0x726b, 0xc6a1, 0x7260, 0xc68a,
+ 0x7255, 0xc674, 0x7249, 0xc65d, 0x723e, 0xc647, 0x7233, 0xc630,
+ 0x7227, 0xc61a, 0x721c, 0xc603, 0x7211, 0xc5ed, 0x7205, 0xc5d7,
+ 0x71fa, 0xc5c0, 0x71ee, 0xc5aa, 0x71e3, 0xc594, 0x71d7, 0xc57d,
+ 0x71cc, 0xc567, 0x71c0, 0xc551, 0x71b5, 0xc53a, 0x71a9, 0xc524,
+ 0x719e, 0xc50e, 0x7192, 0xc4f7, 0x7186, 0xc4e1, 0x717b, 0xc4cb,
+ 0x716f, 0xc4b4, 0x7164, 0xc49e, 0x7158, 0xc488, 0x714c, 0xc472,
+ 0x7141, 0xc45b, 0x7135, 0xc445, 0x7129, 0xc42f, 0x711d, 0xc419,
+ 0x7112, 0xc403, 0x7106, 0xc3ec, 0x70fa, 0xc3d6, 0x70ee, 0xc3c0,
+ 0x70e2, 0xc3aa, 0x70d6, 0xc394, 0x70cb, 0xc37d, 0x70bf, 0xc367,
+ 0x70b3, 0xc351, 0x70a7, 0xc33b, 0x709b, 0xc325, 0x708f, 0xc30f,
+ 0x7083, 0xc2f9, 0x7077, 0xc2e3, 0x706b, 0xc2cd, 0x705f, 0xc2b7,
+ 0x7053, 0xc2a0, 0x7047, 0xc28a, 0x703b, 0xc274, 0x702f, 0xc25e,
+ 0x7023, 0xc248, 0x7016, 0xc232, 0x700a, 0xc21c, 0x6ffe, 0xc206,
+ 0x6ff2, 0xc1f0, 0x6fe6, 0xc1da, 0x6fda, 0xc1c4, 0x6fcd, 0xc1ae,
+ 0x6fc1, 0xc198, 0x6fb5, 0xc183, 0x6fa9, 0xc16d, 0x6f9c, 0xc157,
+ 0x6f90, 0xc141, 0x6f84, 0xc12b, 0x6f77, 0xc115, 0x6f6b, 0xc0ff,
+ 0x6f5f, 0xc0e9, 0x6f52, 0xc0d3, 0x6f46, 0xc0bd, 0x6f39, 0xc0a8,
+ 0x6f2d, 0xc092, 0x6f20, 0xc07c, 0x6f14, 0xc066, 0x6f07, 0xc050,
+ 0x6efb, 0xc03b, 0x6eee, 0xc025, 0x6ee2, 0xc00f, 0x6ed5, 0xbff9,
+ 0x6ec9, 0xbfe3, 0x6ebc, 0xbfce, 0x6eaf, 0xbfb8, 0x6ea3, 0xbfa2,
+ 0x6e96, 0xbf8d, 0x6e89, 0xbf77, 0x6e7d, 0xbf61, 0x6e70, 0xbf4b,
+ 0x6e63, 0xbf36, 0x6e57, 0xbf20, 0x6e4a, 0xbf0a, 0x6e3d, 0xbef5,
+ 0x6e30, 0xbedf, 0x6e24, 0xbeca, 0x6e17, 0xbeb4, 0x6e0a, 0xbe9e,
+ 0x6dfd, 0xbe89, 0x6df0, 0xbe73, 0x6de3, 0xbe5e, 0x6dd6, 0xbe48,
+ 0x6dca, 0xbe32, 0x6dbd, 0xbe1d, 0x6db0, 0xbe07, 0x6da3, 0xbdf2,
+ 0x6d96, 0xbddc, 0x6d89, 0xbdc7, 0x6d7c, 0xbdb1, 0x6d6f, 0xbd9c,
+ 0x6d62, 0xbd86, 0x6d55, 0xbd71, 0x6d48, 0xbd5b, 0x6d3a, 0xbd46,
+ 0x6d2d, 0xbd30, 0x6d20, 0xbd1b, 0x6d13, 0xbd06, 0x6d06, 0xbcf0,
+ 0x6cf9, 0xbcdb, 0x6cec, 0xbcc5, 0x6cde, 0xbcb0, 0x6cd1, 0xbc9b,
+ 0x6cc4, 0xbc85, 0x6cb7, 0xbc70, 0x6ca9, 0xbc5b, 0x6c9c, 0xbc45,
+ 0x6c8f, 0xbc30, 0x6c81, 0xbc1b, 0x6c74, 0xbc05, 0x6c67, 0xbbf0,
+ 0x6c59, 0xbbdb, 0x6c4c, 0xbbc5, 0x6c3f, 0xbbb0, 0x6c31, 0xbb9b,
+ 0x6c24, 0xbb86, 0x6c16, 0xbb70, 0x6c09, 0xbb5b, 0x6bfb, 0xbb46,
+ 0x6bee, 0xbb31, 0x6be0, 0xbb1c, 0x6bd3, 0xbb06, 0x6bc5, 0xbaf1,
+ 0x6bb8, 0xbadc, 0x6baa, 0xbac7, 0x6b9c, 0xbab2, 0x6b8f, 0xba9d,
+ 0x6b81, 0xba88, 0x6b73, 0xba73, 0x6b66, 0xba5d, 0x6b58, 0xba48,
+ 0x6b4a, 0xba33, 0x6b3d, 0xba1e, 0x6b2f, 0xba09, 0x6b21, 0xb9f4,
+ 0x6b13, 0xb9df, 0x6b06, 0xb9ca, 0x6af8, 0xb9b5, 0x6aea, 0xb9a0,
+ 0x6adc, 0xb98b, 0x6ace, 0xb976, 0x6ac1, 0xb961, 0x6ab3, 0xb94c,
+ 0x6aa5, 0xb937, 0x6a97, 0xb922, 0x6a89, 0xb90d, 0x6a7b, 0xb8f8,
+ 0x6a6d, 0xb8e4, 0x6a5f, 0xb8cf, 0x6a51, 0xb8ba, 0x6a43, 0xb8a5,
+ 0x6a35, 0xb890, 0x6a27, 0xb87b, 0x6a19, 0xb866, 0x6a0b, 0xb852,
+ 0x69fd, 0xb83d, 0x69ef, 0xb828, 0x69e1, 0xb813, 0x69d3, 0xb7fe,
+ 0x69c4, 0xb7ea, 0x69b6, 0xb7d5, 0x69a8, 0xb7c0, 0x699a, 0xb7ab,
+ 0x698c, 0xb797, 0x697d, 0xb782, 0x696f, 0xb76d, 0x6961, 0xb758,
+ 0x6953, 0xb744, 0x6944, 0xb72f, 0x6936, 0xb71a, 0x6928, 0xb706,
+ 0x6919, 0xb6f1, 0x690b, 0xb6dd, 0x68fd, 0xb6c8, 0x68ee, 0xb6b3,
+ 0x68e0, 0xb69f, 0x68d1, 0xb68a, 0x68c3, 0xb676, 0x68b5, 0xb661,
+ 0x68a6, 0xb64c, 0x6898, 0xb638, 0x6889, 0xb623, 0x687b, 0xb60f,
+ 0x686c, 0xb5fa, 0x685e, 0xb5e6, 0x684f, 0xb5d1, 0x6840, 0xb5bd,
+ 0x6832, 0xb5a8, 0x6823, 0xb594, 0x6815, 0xb57f, 0x6806, 0xb56b,
+ 0x67f7, 0xb557, 0x67e9, 0xb542, 0x67da, 0xb52e, 0x67cb, 0xb519,
+ 0x67bd, 0xb505, 0x67ae, 0xb4f1, 0x679f, 0xb4dc, 0x6790, 0xb4c8,
+ 0x6782, 0xb4b4, 0x6773, 0xb49f, 0x6764, 0xb48b, 0x6755, 0xb477,
+ 0x6746, 0xb462, 0x6737, 0xb44e, 0x6729, 0xb43a, 0x671a, 0xb426,
+ 0x670b, 0xb411, 0x66fc, 0xb3fd, 0x66ed, 0xb3e9, 0x66de, 0xb3d5,
+ 0x66cf, 0xb3c1, 0x66c0, 0xb3ac, 0x66b1, 0xb398, 0x66a2, 0xb384,
+ 0x6693, 0xb370, 0x6684, 0xb35c, 0x6675, 0xb348, 0x6666, 0xb334,
+ 0x6657, 0xb31f, 0x6648, 0xb30b, 0x6639, 0xb2f7, 0x6629, 0xb2e3,
+ 0x661a, 0xb2cf, 0x660b, 0xb2bb, 0x65fc, 0xb2a7, 0x65ed, 0xb293,
+ 0x65dd, 0xb27f, 0x65ce, 0xb26b, 0x65bf, 0xb257, 0x65b0, 0xb243,
+ 0x65a0, 0xb22f, 0x6591, 0xb21b, 0x6582, 0xb207, 0x6573, 0xb1f3,
+ 0x6563, 0xb1df, 0x6554, 0xb1cc, 0x6545, 0xb1b8, 0x6535, 0xb1a4,
+ 0x6526, 0xb190, 0x6516, 0xb17c, 0x6507, 0xb168, 0x64f7, 0xb154,
+ 0x64e8, 0xb141, 0x64d9, 0xb12d, 0x64c9, 0xb119, 0x64ba, 0xb105,
+ 0x64aa, 0xb0f1, 0x649b, 0xb0de, 0x648b, 0xb0ca, 0x647b, 0xb0b6,
+ 0x646c, 0xb0a2, 0x645c, 0xb08f, 0x644d, 0xb07b, 0x643d, 0xb067,
+ 0x642d, 0xb054, 0x641e, 0xb040, 0x640e, 0xb02c, 0x63fe, 0xb019,
+ 0x63ef, 0xb005, 0x63df, 0xaff1, 0x63cf, 0xafde, 0x63c0, 0xafca,
+ 0x63b0, 0xafb7, 0x63a0, 0xafa3, 0x6390, 0xaf90, 0x6380, 0xaf7c,
+ 0x6371, 0xaf69, 0x6361, 0xaf55, 0x6351, 0xaf41, 0x6341, 0xaf2e,
+ 0x6331, 0xaf1b, 0x6321, 0xaf07, 0x6311, 0xaef4, 0x6301, 0xaee0,
+ 0x62f2, 0xaecd, 0x62e2, 0xaeb9, 0x62d2, 0xaea6, 0x62c2, 0xae92,
+ 0x62b2, 0xae7f, 0x62a2, 0xae6c, 0x6292, 0xae58, 0x6282, 0xae45,
+ 0x6271, 0xae32, 0x6261, 0xae1e, 0x6251, 0xae0b, 0x6241, 0xadf8,
+ 0x6231, 0xade4, 0x6221, 0xadd1, 0x6211, 0xadbe, 0x6201, 0xadab,
+ 0x61f1, 0xad97, 0x61e0, 0xad84, 0x61d0, 0xad71, 0x61c0, 0xad5e,
+ 0x61b0, 0xad4b, 0x619f, 0xad37, 0x618f, 0xad24, 0x617f, 0xad11,
+ 0x616f, 0xacfe, 0x615e, 0xaceb, 0x614e, 0xacd8, 0x613e, 0xacc5,
+ 0x612d, 0xacb2, 0x611d, 0xac9e, 0x610d, 0xac8b, 0x60fc, 0xac78,
+ 0x60ec, 0xac65, 0x60db, 0xac52, 0x60cb, 0xac3f, 0x60ba, 0xac2c,
+ 0x60aa, 0xac19, 0x6099, 0xac06, 0x6089, 0xabf3, 0x6078, 0xabe0,
+ 0x6068, 0xabcd, 0x6057, 0xabbb, 0x6047, 0xaba8, 0x6036, 0xab95,
+ 0x6026, 0xab82, 0x6015, 0xab6f, 0x6004, 0xab5c, 0x5ff4, 0xab49,
+ 0x5fe3, 0xab36, 0x5fd3, 0xab24, 0x5fc2, 0xab11, 0x5fb1, 0xaafe,
+ 0x5fa0, 0xaaeb, 0x5f90, 0xaad8, 0x5f7f, 0xaac6, 0x5f6e, 0xaab3,
+ 0x5f5e, 0xaaa0, 0x5f4d, 0xaa8e, 0x5f3c, 0xaa7b, 0x5f2b, 0xaa68,
+ 0x5f1a, 0xaa55, 0x5f0a, 0xaa43, 0x5ef9, 0xaa30, 0x5ee8, 0xaa1d,
+ 0x5ed7, 0xaa0b, 0x5ec6, 0xa9f8, 0x5eb5, 0xa9e6, 0x5ea4, 0xa9d3,
+ 0x5e93, 0xa9c0, 0x5e82, 0xa9ae, 0x5e71, 0xa99b, 0x5e60, 0xa989,
+ 0x5e50, 0xa976, 0x5e3f, 0xa964, 0x5e2d, 0xa951, 0x5e1c, 0xa93f,
+ 0x5e0b, 0xa92c, 0x5dfa, 0xa91a, 0x5de9, 0xa907, 0x5dd8, 0xa8f5,
+ 0x5dc7, 0xa8e3, 0x5db6, 0xa8d0, 0x5da5, 0xa8be, 0x5d94, 0xa8ab,
+ 0x5d83, 0xa899, 0x5d71, 0xa887, 0x5d60, 0xa874, 0x5d4f, 0xa862,
+ 0x5d3e, 0xa850, 0x5d2d, 0xa83d, 0x5d1b, 0xa82b, 0x5d0a, 0xa819,
+ 0x5cf9, 0xa807, 0x5ce8, 0xa7f4, 0x5cd6, 0xa7e2, 0x5cc5, 0xa7d0,
+ 0x5cb4, 0xa7be, 0x5ca2, 0xa7ab, 0x5c91, 0xa799, 0x5c80, 0xa787,
+ 0x5c6e, 0xa775, 0x5c5d, 0xa763, 0x5c4b, 0xa751, 0x5c3a, 0xa73f,
+ 0x5c29, 0xa72c, 0x5c17, 0xa71a, 0x5c06, 0xa708, 0x5bf4, 0xa6f6,
+ 0x5be3, 0xa6e4, 0x5bd1, 0xa6d2, 0x5bc0, 0xa6c0, 0x5bae, 0xa6ae,
+ 0x5b9d, 0xa69c, 0x5b8b, 0xa68a, 0x5b79, 0xa678, 0x5b68, 0xa666,
+ 0x5b56, 0xa654, 0x5b45, 0xa642, 0x5b33, 0xa630, 0x5b21, 0xa61f,
+ 0x5b10, 0xa60d, 0x5afe, 0xa5fb, 0x5aec, 0xa5e9, 0x5adb, 0xa5d7,
+ 0x5ac9, 0xa5c5, 0x5ab7, 0xa5b3, 0x5aa5, 0xa5a2, 0x5a94, 0xa590,
+ 0x5a82, 0xa57e, 0x5a70, 0xa56c, 0x5a5e, 0xa55b, 0x5a4d, 0xa549,
+ 0x5a3b, 0xa537, 0x5a29, 0xa525, 0x5a17, 0xa514, 0x5a05, 0xa502,
+ 0x59f3, 0xa4f0, 0x59e1, 0xa4df, 0x59d0, 0xa4cd, 0x59be, 0xa4bb,
+ 0x59ac, 0xa4aa, 0x599a, 0xa498, 0x5988, 0xa487, 0x5976, 0xa475,
+ 0x5964, 0xa463, 0x5952, 0xa452, 0x5940, 0xa440, 0x592e, 0xa42f,
+ 0x591c, 0xa41d, 0x590a, 0xa40c, 0x58f8, 0xa3fa, 0x58e6, 0xa3e9,
+ 0x58d4, 0xa3d7, 0x58c1, 0xa3c6, 0x58af, 0xa3b5, 0x589d, 0xa3a3,
+ 0x588b, 0xa392, 0x5879, 0xa380, 0x5867, 0xa36f, 0x5855, 0xa35e,
+ 0x5842, 0xa34c, 0x5830, 0xa33b, 0x581e, 0xa32a, 0x580c, 0xa318,
+ 0x57f9, 0xa307, 0x57e7, 0xa2f6, 0x57d5, 0xa2e5, 0x57c3, 0xa2d3,
+ 0x57b0, 0xa2c2, 0x579e, 0xa2b1, 0x578c, 0xa2a0, 0x5779, 0xa28f,
+ 0x5767, 0xa27d, 0x5755, 0xa26c, 0x5742, 0xa25b, 0x5730, 0xa24a,
+ 0x571d, 0xa239, 0x570b, 0xa228, 0x56f9, 0xa217, 0x56e6, 0xa206,
+ 0x56d4, 0xa1f5, 0x56c1, 0xa1e4, 0x56af, 0xa1d3, 0x569c, 0xa1c1,
+ 0x568a, 0xa1b0, 0x5677, 0xa1a0, 0x5665, 0xa18f, 0x5652, 0xa17e,
+ 0x5640, 0xa16d, 0x562d, 0xa15c, 0x561a, 0xa14b, 0x5608, 0xa13a,
+ 0x55f5, 0xa129, 0x55e3, 0xa118, 0x55d0, 0xa107, 0x55bd, 0xa0f6,
+ 0x55ab, 0xa0e6, 0x5598, 0xa0d5, 0x5585, 0xa0c4, 0x5572, 0xa0b3,
+ 0x5560, 0xa0a2, 0x554d, 0xa092, 0x553a, 0xa081, 0x5528, 0xa070,
+ 0x5515, 0xa060, 0x5502, 0xa04f, 0x54ef, 0xa03e, 0x54dc, 0xa02d,
+ 0x54ca, 0xa01d, 0x54b7, 0xa00c, 0x54a4, 0x9ffc, 0x5491, 0x9feb,
+ 0x547e, 0x9fda, 0x546b, 0x9fca, 0x5458, 0x9fb9, 0x5445, 0x9fa9,
+ 0x5433, 0x9f98, 0x5420, 0x9f88, 0x540d, 0x9f77, 0x53fa, 0x9f67,
+ 0x53e7, 0x9f56, 0x53d4, 0x9f46, 0x53c1, 0x9f35, 0x53ae, 0x9f25,
+ 0x539b, 0x9f14, 0x5388, 0x9f04, 0x5375, 0x9ef3, 0x5362, 0x9ee3,
+ 0x534e, 0x9ed3, 0x533b, 0x9ec2, 0x5328, 0x9eb2, 0x5315, 0x9ea2,
+ 0x5302, 0x9e91, 0x52ef, 0x9e81, 0x52dc, 0x9e71, 0x52c9, 0x9e61,
+ 0x52b5, 0x9e50, 0x52a2, 0x9e40, 0x528f, 0x9e30, 0x527c, 0x9e20,
+ 0x5269, 0x9e0f, 0x5255, 0x9dff, 0x5242, 0x9def, 0x522f, 0x9ddf,
+ 0x521c, 0x9dcf, 0x5208, 0x9dbf, 0x51f5, 0x9daf, 0x51e2, 0x9d9f,
+ 0x51ce, 0x9d8f, 0x51bb, 0x9d7e, 0x51a8, 0x9d6e, 0x5194, 0x9d5e,
+ 0x5181, 0x9d4e, 0x516e, 0x9d3e, 0x515a, 0x9d2e, 0x5147, 0x9d1e,
+ 0x5133, 0x9d0e, 0x5120, 0x9cff, 0x510c, 0x9cef, 0x50f9, 0x9cdf,
+ 0x50e5, 0x9ccf, 0x50d2, 0x9cbf, 0x50bf, 0x9caf, 0x50ab, 0x9c9f,
+ 0x5097, 0x9c8f, 0x5084, 0x9c80, 0x5070, 0x9c70, 0x505d, 0x9c60,
+ 0x5049, 0x9c50, 0x5036, 0x9c40, 0x5022, 0x9c31, 0x500f, 0x9c21,
+ 0x4ffb, 0x9c11, 0x4fe7, 0x9c02, 0x4fd4, 0x9bf2, 0x4fc0, 0x9be2,
+ 0x4fac, 0x9bd3, 0x4f99, 0x9bc3, 0x4f85, 0x9bb3, 0x4f71, 0x9ba4,
+ 0x4f5e, 0x9b94, 0x4f4a, 0x9b85, 0x4f36, 0x9b75, 0x4f22, 0x9b65,
+ 0x4f0f, 0x9b56, 0x4efb, 0x9b46, 0x4ee7, 0x9b37, 0x4ed3, 0x9b27,
+ 0x4ebf, 0x9b18, 0x4eac, 0x9b09, 0x4e98, 0x9af9, 0x4e84, 0x9aea,
+ 0x4e70, 0x9ada, 0x4e5c, 0x9acb, 0x4e48, 0x9abb, 0x4e34, 0x9aac,
+ 0x4e21, 0x9a9d, 0x4e0d, 0x9a8d, 0x4df9, 0x9a7e, 0x4de5, 0x9a6f,
+ 0x4dd1, 0x9a60, 0x4dbd, 0x9a50, 0x4da9, 0x9a41, 0x4d95, 0x9a32,
+ 0x4d81, 0x9a23, 0x4d6d, 0x9a13, 0x4d59, 0x9a04, 0x4d45, 0x99f5,
+ 0x4d31, 0x99e6, 0x4d1d, 0x99d7, 0x4d09, 0x99c7, 0x4cf5, 0x99b8,
+ 0x4ce1, 0x99a9, 0x4ccc, 0x999a, 0x4cb8, 0x998b, 0x4ca4, 0x997c,
+ 0x4c90, 0x996d, 0x4c7c, 0x995e, 0x4c68, 0x994f, 0x4c54, 0x9940,
+ 0x4c3f, 0x9931, 0x4c2b, 0x9922, 0x4c17, 0x9913, 0x4c03, 0x9904,
+ 0x4bef, 0x98f5, 0x4bda, 0x98e6, 0x4bc6, 0x98d7, 0x4bb2, 0x98c9,
+ 0x4b9e, 0x98ba, 0x4b89, 0x98ab, 0x4b75, 0x989c, 0x4b61, 0x988d,
+ 0x4b4c, 0x987e, 0x4b38, 0x9870, 0x4b24, 0x9861, 0x4b0f, 0x9852,
+ 0x4afb, 0x9843, 0x4ae7, 0x9835, 0x4ad2, 0x9826, 0x4abe, 0x9817,
+ 0x4aa9, 0x9809, 0x4a95, 0x97fa, 0x4a81, 0x97eb, 0x4a6c, 0x97dd,
+ 0x4a58, 0x97ce, 0x4a43, 0x97c0, 0x4a2f, 0x97b1, 0x4a1a, 0x97a2,
+ 0x4a06, 0x9794, 0x49f1, 0x9785, 0x49dd, 0x9777, 0x49c8, 0x9768,
+ 0x49b4, 0x975a, 0x499f, 0x974b, 0x498a, 0x973d, 0x4976, 0x972f,
+ 0x4961, 0x9720, 0x494d, 0x9712, 0x4938, 0x9703, 0x4923, 0x96f5,
+ 0x490f, 0x96e7, 0x48fa, 0x96d8, 0x48e6, 0x96ca, 0x48d1, 0x96bc,
+ 0x48bc, 0x96ad, 0x48a8, 0x969f, 0x4893, 0x9691, 0x487e, 0x9683,
+ 0x4869, 0x9674, 0x4855, 0x9666, 0x4840, 0x9658, 0x482b, 0x964a,
+ 0x4816, 0x963c, 0x4802, 0x962d, 0x47ed, 0x961f, 0x47d8, 0x9611,
+ 0x47c3, 0x9603, 0x47ae, 0x95f5, 0x479a, 0x95e7, 0x4785, 0x95d9,
+ 0x4770, 0x95cb, 0x475b, 0x95bd, 0x4746, 0x95af, 0x4731, 0x95a1,
+ 0x471c, 0x9593, 0x4708, 0x9585, 0x46f3, 0x9577, 0x46de, 0x9569,
+ 0x46c9, 0x955b, 0x46b4, 0x954d, 0x469f, 0x953f, 0x468a, 0x9532,
+ 0x4675, 0x9524, 0x4660, 0x9516, 0x464b, 0x9508, 0x4636, 0x94fa,
+ 0x4621, 0x94ed, 0x460c, 0x94df, 0x45f7, 0x94d1, 0x45e2, 0x94c3,
+ 0x45cd, 0x94b6, 0x45b8, 0x94a8, 0x45a3, 0x949a, 0x458d, 0x948d,
+ 0x4578, 0x947f, 0x4563, 0x9471, 0x454e, 0x9464, 0x4539, 0x9456,
+ 0x4524, 0x9448, 0x450f, 0x943b, 0x44fa, 0x942d, 0x44e4, 0x9420,
+ 0x44cf, 0x9412, 0x44ba, 0x9405, 0x44a5, 0x93f7, 0x4490, 0x93ea,
+ 0x447a, 0x93dc, 0x4465, 0x93cf, 0x4450, 0x93c1, 0x443b, 0x93b4,
+ 0x4425, 0x93a7, 0x4410, 0x9399, 0x43fb, 0x938c, 0x43e5, 0x937f,
+ 0x43d0, 0x9371, 0x43bb, 0x9364, 0x43a5, 0x9357, 0x4390, 0x9349,
+ 0x437b, 0x933c, 0x4365, 0x932f, 0x4350, 0x9322, 0x433b, 0x9314,
+ 0x4325, 0x9307, 0x4310, 0x92fa, 0x42fa, 0x92ed, 0x42e5, 0x92e0,
+ 0x42d0, 0x92d3, 0x42ba, 0x92c6, 0x42a5, 0x92b8, 0x428f, 0x92ab,
+ 0x427a, 0x929e, 0x4264, 0x9291, 0x424f, 0x9284, 0x4239, 0x9277,
+ 0x4224, 0x926a, 0x420e, 0x925d, 0x41f9, 0x9250, 0x41e3, 0x9243,
+ 0x41ce, 0x9236, 0x41b8, 0x922a, 0x41a2, 0x921d, 0x418d, 0x9210,
+ 0x4177, 0x9203, 0x4162, 0x91f6, 0x414c, 0x91e9, 0x4136, 0x91dc,
+ 0x4121, 0x91d0, 0x410b, 0x91c3, 0x40f6, 0x91b6, 0x40e0, 0x91a9,
+ 0x40ca, 0x919d, 0x40b5, 0x9190, 0x409f, 0x9183, 0x4089, 0x9177,
+ 0x4073, 0x916a, 0x405e, 0x915d, 0x4048, 0x9151, 0x4032, 0x9144,
+ 0x401d, 0x9137, 0x4007, 0x912b, 0x3ff1, 0x911e, 0x3fdb, 0x9112,
+ 0x3fc5, 0x9105, 0x3fb0, 0x90f9, 0x3f9a, 0x90ec, 0x3f84, 0x90e0,
+ 0x3f6e, 0x90d3, 0x3f58, 0x90c7, 0x3f43, 0x90ba, 0x3f2d, 0x90ae,
+ 0x3f17, 0x90a1, 0x3f01, 0x9095, 0x3eeb, 0x9089, 0x3ed5, 0x907c,
+ 0x3ebf, 0x9070, 0x3ea9, 0x9064, 0x3e93, 0x9057, 0x3e7d, 0x904b,
+ 0x3e68, 0x903f, 0x3e52, 0x9033, 0x3e3c, 0x9026, 0x3e26, 0x901a,
+ 0x3e10, 0x900e, 0x3dfa, 0x9002, 0x3de4, 0x8ff6, 0x3dce, 0x8fea,
+ 0x3db8, 0x8fdd, 0x3da2, 0x8fd1, 0x3d8c, 0x8fc5, 0x3d76, 0x8fb9,
+ 0x3d60, 0x8fad, 0x3d49, 0x8fa1, 0x3d33, 0x8f95, 0x3d1d, 0x8f89,
+ 0x3d07, 0x8f7d, 0x3cf1, 0x8f71, 0x3cdb, 0x8f65, 0x3cc5, 0x8f59,
+ 0x3caf, 0x8f4d, 0x3c99, 0x8f41, 0x3c83, 0x8f35, 0x3c6c, 0x8f2a,
+ 0x3c56, 0x8f1e, 0x3c40, 0x8f12, 0x3c2a, 0x8f06, 0x3c14, 0x8efa,
+ 0x3bfd, 0x8eee, 0x3be7, 0x8ee3, 0x3bd1, 0x8ed7, 0x3bbb, 0x8ecb,
+ 0x3ba5, 0x8ebf, 0x3b8e, 0x8eb4, 0x3b78, 0x8ea8, 0x3b62, 0x8e9c,
+ 0x3b4c, 0x8e91, 0x3b35, 0x8e85, 0x3b1f, 0x8e7a, 0x3b09, 0x8e6e,
+ 0x3af2, 0x8e62, 0x3adc, 0x8e57, 0x3ac6, 0x8e4b, 0x3aaf, 0x8e40,
+ 0x3a99, 0x8e34, 0x3a83, 0x8e29, 0x3a6c, 0x8e1d, 0x3a56, 0x8e12,
+ 0x3a40, 0x8e06, 0x3a29, 0x8dfb, 0x3a13, 0x8def, 0x39fd, 0x8de4,
+ 0x39e6, 0x8dd9, 0x39d0, 0x8dcd, 0x39b9, 0x8dc2, 0x39a3, 0x8db7,
+ 0x398c, 0x8dab, 0x3976, 0x8da0, 0x395f, 0x8d95, 0x3949, 0x8d8a,
+ 0x3932, 0x8d7e, 0x391c, 0x8d73, 0x3906, 0x8d68, 0x38ef, 0x8d5d,
+ 0x38d8, 0x8d51, 0x38c2, 0x8d46, 0x38ab, 0x8d3b, 0x3895, 0x8d30,
+ 0x387e, 0x8d25, 0x3868, 0x8d1a, 0x3851, 0x8d0f, 0x383b, 0x8d04,
+ 0x3824, 0x8cf9, 0x380d, 0x8cee, 0x37f7, 0x8ce3, 0x37e0, 0x8cd8,
+ 0x37ca, 0x8ccd, 0x37b3, 0x8cc2, 0x379c, 0x8cb7, 0x3786, 0x8cac,
+ 0x376f, 0x8ca1, 0x3758, 0x8c96, 0x3742, 0x8c8b, 0x372b, 0x8c81,
+ 0x3714, 0x8c76, 0x36fe, 0x8c6b, 0x36e7, 0x8c60, 0x36d0, 0x8c55,
+ 0x36ba, 0x8c4b, 0x36a3, 0x8c40, 0x368c, 0x8c35, 0x3675, 0x8c2a,
+ 0x365f, 0x8c20, 0x3648, 0x8c15, 0x3631, 0x8c0a, 0x361a, 0x8c00,
+ 0x3604, 0x8bf5, 0x35ed, 0x8beb, 0x35d6, 0x8be0, 0x35bf, 0x8bd5,
+ 0x35a8, 0x8bcb, 0x3592, 0x8bc0, 0x357b, 0x8bb6, 0x3564, 0x8bab,
+ 0x354d, 0x8ba1, 0x3536, 0x8b96, 0x351f, 0x8b8c, 0x3508, 0x8b82,
+ 0x34f2, 0x8b77, 0x34db, 0x8b6d, 0x34c4, 0x8b62, 0x34ad, 0x8b58,
+ 0x3496, 0x8b4e, 0x347f, 0x8b43, 0x3468, 0x8b39, 0x3451, 0x8b2f,
+ 0x343a, 0x8b25, 0x3423, 0x8b1a, 0x340c, 0x8b10, 0x33f5, 0x8b06,
+ 0x33de, 0x8afc, 0x33c7, 0x8af1, 0x33b0, 0x8ae7, 0x3399, 0x8add,
+ 0x3382, 0x8ad3, 0x336b, 0x8ac9, 0x3354, 0x8abf, 0x333d, 0x8ab5,
+ 0x3326, 0x8aab, 0x330f, 0x8aa1, 0x32f8, 0x8a97, 0x32e1, 0x8a8d,
+ 0x32ca, 0x8a83, 0x32b3, 0x8a79, 0x329c, 0x8a6f, 0x3285, 0x8a65,
+ 0x326e, 0x8a5b, 0x3257, 0x8a51, 0x3240, 0x8a47, 0x3228, 0x8a3d,
+ 0x3211, 0x8a34, 0x31fa, 0x8a2a, 0x31e3, 0x8a20, 0x31cc, 0x8a16,
+ 0x31b5, 0x8a0c, 0x319e, 0x8a03, 0x3186, 0x89f9, 0x316f, 0x89ef,
+ 0x3158, 0x89e5, 0x3141, 0x89dc, 0x312a, 0x89d2, 0x3112, 0x89c8,
+ 0x30fb, 0x89bf, 0x30e4, 0x89b5, 0x30cd, 0x89ac, 0x30b6, 0x89a2,
+ 0x309e, 0x8998, 0x3087, 0x898f, 0x3070, 0x8985, 0x3059, 0x897c,
+ 0x3041, 0x8972, 0x302a, 0x8969, 0x3013, 0x8960, 0x2ffb, 0x8956,
+ 0x2fe4, 0x894d, 0x2fcd, 0x8943, 0x2fb5, 0x893a, 0x2f9e, 0x8931,
+ 0x2f87, 0x8927, 0x2f6f, 0x891e, 0x2f58, 0x8915, 0x2f41, 0x890b,
+ 0x2f29, 0x8902, 0x2f12, 0x88f9, 0x2efb, 0x88f0, 0x2ee3, 0x88e6,
+ 0x2ecc, 0x88dd, 0x2eb5, 0x88d4, 0x2e9d, 0x88cb, 0x2e86, 0x88c2,
+ 0x2e6e, 0x88b9, 0x2e57, 0x88af, 0x2e3f, 0x88a6, 0x2e28, 0x889d,
+ 0x2e11, 0x8894, 0x2df9, 0x888b, 0x2de2, 0x8882, 0x2dca, 0x8879,
+ 0x2db3, 0x8870, 0x2d9b, 0x8867, 0x2d84, 0x885e, 0x2d6c, 0x8855,
+ 0x2d55, 0x884c, 0x2d3d, 0x8844, 0x2d26, 0x883b, 0x2d0e, 0x8832,
+ 0x2cf7, 0x8829, 0x2cdf, 0x8820, 0x2cc8, 0x8817, 0x2cb0, 0x880f,
+ 0x2c98, 0x8806, 0x2c81, 0x87fd, 0x2c69, 0x87f4, 0x2c52, 0x87ec,
+ 0x2c3a, 0x87e3, 0x2c23, 0x87da, 0x2c0b, 0x87d2, 0x2bf3, 0x87c9,
+ 0x2bdc, 0x87c0, 0x2bc4, 0x87b8, 0x2bad, 0x87af, 0x2b95, 0x87a7,
+ 0x2b7d, 0x879e, 0x2b66, 0x8795, 0x2b4e, 0x878d, 0x2b36, 0x8784,
+ 0x2b1f, 0x877c, 0x2b07, 0x8774, 0x2aef, 0x876b, 0x2ad8, 0x8763,
+ 0x2ac0, 0x875a, 0x2aa8, 0x8752, 0x2a91, 0x874a, 0x2a79, 0x8741,
+ 0x2a61, 0x8739, 0x2a49, 0x8731, 0x2a32, 0x8728, 0x2a1a, 0x8720,
+ 0x2a02, 0x8718, 0x29eb, 0x870f, 0x29d3, 0x8707, 0x29bb, 0x86ff,
+ 0x29a3, 0x86f7, 0x298b, 0x86ef, 0x2974, 0x86e7, 0x295c, 0x86de,
+ 0x2944, 0x86d6, 0x292c, 0x86ce, 0x2915, 0x86c6, 0x28fd, 0x86be,
+ 0x28e5, 0x86b6, 0x28cd, 0x86ae, 0x28b5, 0x86a6, 0x289d, 0x869e,
+ 0x2886, 0x8696, 0x286e, 0x868e, 0x2856, 0x8686, 0x283e, 0x867e,
+ 0x2826, 0x8676, 0x280e, 0x866e, 0x27f6, 0x8667, 0x27df, 0x865f,
+ 0x27c7, 0x8657, 0x27af, 0x864f, 0x2797, 0x8647, 0x277f, 0x8640,
+ 0x2767, 0x8638, 0x274f, 0x8630, 0x2737, 0x8628, 0x271f, 0x8621,
+ 0x2707, 0x8619, 0x26ef, 0x8611, 0x26d8, 0x860a, 0x26c0, 0x8602,
+ 0x26a8, 0x85fb, 0x2690, 0x85f3, 0x2678, 0x85eb, 0x2660, 0x85e4,
+ 0x2648, 0x85dc, 0x2630, 0x85d5, 0x2618, 0x85cd, 0x2600, 0x85c6,
+ 0x25e8, 0x85be, 0x25d0, 0x85b7, 0x25b8, 0x85b0, 0x25a0, 0x85a8,
+ 0x2588, 0x85a1, 0x2570, 0x8599, 0x2558, 0x8592, 0x2540, 0x858b,
+ 0x2528, 0x8583, 0x250f, 0x857c, 0x24f7, 0x8575, 0x24df, 0x856e,
+ 0x24c7, 0x8566, 0x24af, 0x855f, 0x2497, 0x8558, 0x247f, 0x8551,
+ 0x2467, 0x854a, 0x244f, 0x8543, 0x2437, 0x853b, 0x241f, 0x8534,
+ 0x2407, 0x852d, 0x23ee, 0x8526, 0x23d6, 0x851f, 0x23be, 0x8518,
+ 0x23a6, 0x8511, 0x238e, 0x850a, 0x2376, 0x8503, 0x235e, 0x84fc,
+ 0x2345, 0x84f5, 0x232d, 0x84ee, 0x2315, 0x84e7, 0x22fd, 0x84e1,
+ 0x22e5, 0x84da, 0x22cd, 0x84d3, 0x22b4, 0x84cc, 0x229c, 0x84c5,
+ 0x2284, 0x84be, 0x226c, 0x84b8, 0x2254, 0x84b1, 0x223b, 0x84aa,
+ 0x2223, 0x84a3, 0x220b, 0x849d, 0x21f3, 0x8496, 0x21da, 0x848f,
+ 0x21c2, 0x8489, 0x21aa, 0x8482, 0x2192, 0x847c, 0x2179, 0x8475,
+ 0x2161, 0x846e, 0x2149, 0x8468, 0x2131, 0x8461, 0x2118, 0x845b,
+ 0x2100, 0x8454, 0x20e8, 0x844e, 0x20d0, 0x8447, 0x20b7, 0x8441,
+ 0x209f, 0x843b, 0x2087, 0x8434, 0x206e, 0x842e, 0x2056, 0x8427,
+ 0x203e, 0x8421, 0x2025, 0x841b, 0x200d, 0x8415, 0x1ff5, 0x840e,
+ 0x1fdc, 0x8408, 0x1fc4, 0x8402, 0x1fac, 0x83fb, 0x1f93, 0x83f5,
+ 0x1f7b, 0x83ef, 0x1f63, 0x83e9, 0x1f4a, 0x83e3, 0x1f32, 0x83dd,
+ 0x1f19, 0x83d7, 0x1f01, 0x83d0, 0x1ee9, 0x83ca, 0x1ed0, 0x83c4,
+ 0x1eb8, 0x83be, 0x1ea0, 0x83b8, 0x1e87, 0x83b2, 0x1e6f, 0x83ac,
+ 0x1e56, 0x83a6, 0x1e3e, 0x83a0, 0x1e25, 0x839a, 0x1e0d, 0x8394,
+ 0x1df5, 0x838f, 0x1ddc, 0x8389, 0x1dc4, 0x8383, 0x1dab, 0x837d,
+ 0x1d93, 0x8377, 0x1d7a, 0x8371, 0x1d62, 0x836c, 0x1d49, 0x8366,
+ 0x1d31, 0x8360, 0x1d18, 0x835a, 0x1d00, 0x8355, 0x1ce8, 0x834f,
+ 0x1ccf, 0x8349, 0x1cb7, 0x8344, 0x1c9e, 0x833e, 0x1c86, 0x8338,
+ 0x1c6d, 0x8333, 0x1c55, 0x832d, 0x1c3c, 0x8328, 0x1c24, 0x8322,
+ 0x1c0b, 0x831d, 0x1bf2, 0x8317, 0x1bda, 0x8312, 0x1bc1, 0x830c,
+ 0x1ba9, 0x8307, 0x1b90, 0x8301, 0x1b78, 0x82fc, 0x1b5f, 0x82f7,
+ 0x1b47, 0x82f1, 0x1b2e, 0x82ec, 0x1b16, 0x82e7, 0x1afd, 0x82e1,
+ 0x1ae4, 0x82dc, 0x1acc, 0x82d7, 0x1ab3, 0x82d1, 0x1a9b, 0x82cc,
+ 0x1a82, 0x82c7, 0x1a6a, 0x82c2, 0x1a51, 0x82bd, 0x1a38, 0x82b7,
+ 0x1a20, 0x82b2, 0x1a07, 0x82ad, 0x19ef, 0x82a8, 0x19d6, 0x82a3,
+ 0x19bd, 0x829e, 0x19a5, 0x8299, 0x198c, 0x8294, 0x1973, 0x828f,
+ 0x195b, 0x828a, 0x1942, 0x8285, 0x192a, 0x8280, 0x1911, 0x827b,
+ 0x18f8, 0x8276, 0x18e0, 0x8271, 0x18c7, 0x826c, 0x18ae, 0x8268,
+ 0x1896, 0x8263, 0x187d, 0x825e, 0x1864, 0x8259, 0x184c, 0x8254,
+ 0x1833, 0x8250, 0x181a, 0x824b, 0x1802, 0x8246, 0x17e9, 0x8241,
+ 0x17d0, 0x823d, 0x17b7, 0x8238, 0x179f, 0x8233, 0x1786, 0x822f,
+ 0x176d, 0x822a, 0x1755, 0x8226, 0x173c, 0x8221, 0x1723, 0x821c,
+ 0x170a, 0x8218, 0x16f2, 0x8213, 0x16d9, 0x820f, 0x16c0, 0x820a,
+ 0x16a8, 0x8206, 0x168f, 0x8201, 0x1676, 0x81fd, 0x165d, 0x81f9,
+ 0x1645, 0x81f4, 0x162c, 0x81f0, 0x1613, 0x81ec, 0x15fa, 0x81e7,
+ 0x15e2, 0x81e3, 0x15c9, 0x81df, 0x15b0, 0x81da, 0x1597, 0x81d6,
+ 0x157f, 0x81d2, 0x1566, 0x81ce, 0x154d, 0x81c9, 0x1534, 0x81c5,
+ 0x151b, 0x81c1, 0x1503, 0x81bd, 0x14ea, 0x81b9, 0x14d1, 0x81b5,
+ 0x14b8, 0x81b1, 0x149f, 0x81ad, 0x1487, 0x81a9, 0x146e, 0x81a5,
+ 0x1455, 0x81a1, 0x143c, 0x819d, 0x1423, 0x8199, 0x140b, 0x8195,
+ 0x13f2, 0x8191, 0x13d9, 0x818d, 0x13c0, 0x8189, 0x13a7, 0x8185,
+ 0x138e, 0x8181, 0x1376, 0x817d, 0x135d, 0x817a, 0x1344, 0x8176,
+ 0x132b, 0x8172, 0x1312, 0x816e, 0x12f9, 0x816b, 0x12e0, 0x8167,
+ 0x12c8, 0x8163, 0x12af, 0x815f, 0x1296, 0x815c, 0x127d, 0x8158,
+ 0x1264, 0x8155, 0x124b, 0x8151, 0x1232, 0x814d, 0x1219, 0x814a,
+ 0x1201, 0x8146, 0x11e8, 0x8143, 0x11cf, 0x813f, 0x11b6, 0x813c,
+ 0x119d, 0x8138, 0x1184, 0x8135, 0x116b, 0x8131, 0x1152, 0x812e,
+ 0x1139, 0x812b, 0x1121, 0x8127, 0x1108, 0x8124, 0x10ef, 0x8121,
+ 0x10d6, 0x811d, 0x10bd, 0x811a, 0x10a4, 0x8117, 0x108b, 0x8113,
+ 0x1072, 0x8110, 0x1059, 0x810d, 0x1040, 0x810a, 0x1027, 0x8107,
+ 0x100e, 0x8103, 0xff5, 0x8100, 0xfdd, 0x80fd, 0xfc4, 0x80fa,
+ 0xfab, 0x80f7, 0xf92, 0x80f4, 0xf79, 0x80f1, 0xf60, 0x80ee,
+ 0xf47, 0x80eb, 0xf2e, 0x80e8, 0xf15, 0x80e5, 0xefc, 0x80e2,
+ 0xee3, 0x80df, 0xeca, 0x80dc, 0xeb1, 0x80d9, 0xe98, 0x80d6,
+ 0xe7f, 0x80d3, 0xe66, 0x80d1, 0xe4d, 0x80ce, 0xe34, 0x80cb,
+ 0xe1b, 0x80c8, 0xe02, 0x80c5, 0xde9, 0x80c3, 0xdd0, 0x80c0,
+ 0xdb7, 0x80bd, 0xd9e, 0x80bb, 0xd85, 0x80b8, 0xd6c, 0x80b5,
+ 0xd53, 0x80b3, 0xd3a, 0x80b0, 0xd21, 0x80ad, 0xd08, 0x80ab,
+ 0xcef, 0x80a8, 0xcd6, 0x80a6, 0xcbd, 0x80a3, 0xca4, 0x80a1,
+ 0xc8b, 0x809e, 0xc72, 0x809c, 0xc59, 0x8099, 0xc40, 0x8097,
+ 0xc27, 0x8095, 0xc0e, 0x8092, 0xbf5, 0x8090, 0xbdc, 0x808e,
+ 0xbc3, 0x808b, 0xbaa, 0x8089, 0xb91, 0x8087, 0xb78, 0x8084,
+ 0xb5f, 0x8082, 0xb46, 0x8080, 0xb2d, 0x807e, 0xb14, 0x807b,
+ 0xafb, 0x8079, 0xae2, 0x8077, 0xac9, 0x8075, 0xab0, 0x8073,
+ 0xa97, 0x8071, 0xa7e, 0x806f, 0xa65, 0x806d, 0xa4c, 0x806b,
+ 0xa33, 0x8069, 0xa19, 0x8067, 0xa00, 0x8065, 0x9e7, 0x8063,
+ 0x9ce, 0x8061, 0x9b5, 0x805f, 0x99c, 0x805d, 0x983, 0x805b,
+ 0x96a, 0x8059, 0x951, 0x8057, 0x938, 0x8056, 0x91f, 0x8054,
+ 0x906, 0x8052, 0x8ed, 0x8050, 0x8d4, 0x804f, 0x8bb, 0x804d,
+ 0x8a2, 0x804b, 0x888, 0x8049, 0x86f, 0x8048, 0x856, 0x8046,
+ 0x83d, 0x8044, 0x824, 0x8043, 0x80b, 0x8041, 0x7f2, 0x8040,
+ 0x7d9, 0x803e, 0x7c0, 0x803d, 0x7a7, 0x803b, 0x78e, 0x803a,
+ 0x775, 0x8038, 0x75b, 0x8037, 0x742, 0x8035, 0x729, 0x8034,
+ 0x710, 0x8032, 0x6f7, 0x8031, 0x6de, 0x8030, 0x6c5, 0x802e,
+ 0x6ac, 0x802d, 0x693, 0x802c, 0x67a, 0x802a, 0x660, 0x8029,
+ 0x647, 0x8028, 0x62e, 0x8027, 0x615, 0x8026, 0x5fc, 0x8024,
+ 0x5e3, 0x8023, 0x5ca, 0x8022, 0x5b1, 0x8021, 0x598, 0x8020,
+ 0x57f, 0x801f, 0x565, 0x801e, 0x54c, 0x801d, 0x533, 0x801c,
+ 0x51a, 0x801b, 0x501, 0x801a, 0x4e8, 0x8019, 0x4cf, 0x8018,
+ 0x4b6, 0x8017, 0x49c, 0x8016, 0x483, 0x8015, 0x46a, 0x8014,
+ 0x451, 0x8013, 0x438, 0x8012, 0x41f, 0x8012, 0x406, 0x8011,
+ 0x3ed, 0x8010, 0x3d4, 0x800f, 0x3ba, 0x800e, 0x3a1, 0x800e,
+ 0x388, 0x800d, 0x36f, 0x800c, 0x356, 0x800c, 0x33d, 0x800b,
+ 0x324, 0x800a, 0x30b, 0x800a, 0x2f1, 0x8009, 0x2d8, 0x8009,
+ 0x2bf, 0x8008, 0x2a6, 0x8008, 0x28d, 0x8007, 0x274, 0x8007,
+ 0x25b, 0x8006, 0x242, 0x8006, 0x228, 0x8005, 0x20f, 0x8005,
+ 0x1f6, 0x8004, 0x1dd, 0x8004, 0x1c4, 0x8004, 0x1ab, 0x8003,
+ 0x192, 0x8003, 0x178, 0x8003, 0x15f, 0x8002, 0x146, 0x8002,
+ 0x12d, 0x8002, 0x114, 0x8002, 0xfb, 0x8001, 0xe2, 0x8001,
+ 0xc9, 0x8001, 0xaf, 0x8001, 0x96, 0x8001, 0x7d, 0x8001,
+ 0x64, 0x8001, 0x4b, 0x8001, 0x32, 0x8001, 0x19, 0x8001,
+};
+
+static const q15_t ALIGN4 WeightsQ15_8192[16384] = {
+ 0x7fff, 0x0, 0x7fff, 0xfffa, 0x7fff, 0xfff4, 0x7fff, 0xffee,
+ 0x7fff, 0xffe7, 0x7fff, 0xffe1, 0x7fff, 0xffdb, 0x7fff, 0xffd5,
+ 0x7fff, 0xffce, 0x7fff, 0xffc8, 0x7fff, 0xffc2, 0x7fff, 0xffbb,
+ 0x7fff, 0xffb5, 0x7fff, 0xffaf, 0x7fff, 0xffa9, 0x7fff, 0xffa2,
+ 0x7fff, 0xff9c, 0x7fff, 0xff96, 0x7fff, 0xff8f, 0x7fff, 0xff89,
+ 0x7fff, 0xff83, 0x7fff, 0xff7d, 0x7fff, 0xff76, 0x7fff, 0xff70,
+ 0x7fff, 0xff6a, 0x7fff, 0xff63, 0x7fff, 0xff5d, 0x7fff, 0xff57,
+ 0x7fff, 0xff51, 0x7fff, 0xff4a, 0x7fff, 0xff44, 0x7fff, 0xff3e,
+ 0x7fff, 0xff37, 0x7fff, 0xff31, 0x7fff, 0xff2b, 0x7fff, 0xff25,
+ 0x7fff, 0xff1e, 0x7fff, 0xff18, 0x7fff, 0xff12, 0x7fff, 0xff0b,
+ 0x7fff, 0xff05, 0x7ffe, 0xfeff, 0x7ffe, 0xfef9, 0x7ffe, 0xfef2,
+ 0x7ffe, 0xfeec, 0x7ffe, 0xfee6, 0x7ffe, 0xfedf, 0x7ffe, 0xfed9,
+ 0x7ffe, 0xfed3, 0x7ffe, 0xfecd, 0x7ffe, 0xfec6, 0x7ffe, 0xfec0,
+ 0x7ffe, 0xfeba, 0x7ffe, 0xfeb3, 0x7ffe, 0xfead, 0x7ffe, 0xfea7,
+ 0x7ffe, 0xfea1, 0x7ffe, 0xfe9a, 0x7ffd, 0xfe94, 0x7ffd, 0xfe8e,
+ 0x7ffd, 0xfe88, 0x7ffd, 0xfe81, 0x7ffd, 0xfe7b, 0x7ffd, 0xfe75,
+ 0x7ffd, 0xfe6e, 0x7ffd, 0xfe68, 0x7ffd, 0xfe62, 0x7ffd, 0xfe5c,
+ 0x7ffd, 0xfe55, 0x7ffd, 0xfe4f, 0x7ffd, 0xfe49, 0x7ffc, 0xfe42,
+ 0x7ffc, 0xfe3c, 0x7ffc, 0xfe36, 0x7ffc, 0xfe30, 0x7ffc, 0xfe29,
+ 0x7ffc, 0xfe23, 0x7ffc, 0xfe1d, 0x7ffc, 0xfe16, 0x7ffc, 0xfe10,
+ 0x7ffc, 0xfe0a, 0x7ffc, 0xfe04, 0x7ffb, 0xfdfd, 0x7ffb, 0xfdf7,
+ 0x7ffb, 0xfdf1, 0x7ffb, 0xfdea, 0x7ffb, 0xfde4, 0x7ffb, 0xfdde,
+ 0x7ffb, 0xfdd8, 0x7ffb, 0xfdd1, 0x7ffb, 0xfdcb, 0x7ffb, 0xfdc5,
+ 0x7ffa, 0xfdbe, 0x7ffa, 0xfdb8, 0x7ffa, 0xfdb2, 0x7ffa, 0xfdac,
+ 0x7ffa, 0xfda5, 0x7ffa, 0xfd9f, 0x7ffa, 0xfd99, 0x7ffa, 0xfd93,
+ 0x7ff9, 0xfd8c, 0x7ff9, 0xfd86, 0x7ff9, 0xfd80, 0x7ff9, 0xfd79,
+ 0x7ff9, 0xfd73, 0x7ff9, 0xfd6d, 0x7ff9, 0xfd67, 0x7ff9, 0xfd60,
+ 0x7ff8, 0xfd5a, 0x7ff8, 0xfd54, 0x7ff8, 0xfd4d, 0x7ff8, 0xfd47,
+ 0x7ff8, 0xfd41, 0x7ff8, 0xfd3b, 0x7ff8, 0xfd34, 0x7ff8, 0xfd2e,
+ 0x7ff7, 0xfd28, 0x7ff7, 0xfd21, 0x7ff7, 0xfd1b, 0x7ff7, 0xfd15,
+ 0x7ff7, 0xfd0f, 0x7ff7, 0xfd08, 0x7ff7, 0xfd02, 0x7ff6, 0xfcfc,
+ 0x7ff6, 0xfcf5, 0x7ff6, 0xfcef, 0x7ff6, 0xfce9, 0x7ff6, 0xfce3,
+ 0x7ff6, 0xfcdc, 0x7ff5, 0xfcd6, 0x7ff5, 0xfcd0, 0x7ff5, 0xfcc9,
+ 0x7ff5, 0xfcc3, 0x7ff5, 0xfcbd, 0x7ff5, 0xfcb7, 0x7ff5, 0xfcb0,
+ 0x7ff4, 0xfcaa, 0x7ff4, 0xfca4, 0x7ff4, 0xfc9e, 0x7ff4, 0xfc97,
+ 0x7ff4, 0xfc91, 0x7ff4, 0xfc8b, 0x7ff3, 0xfc84, 0x7ff3, 0xfc7e,
+ 0x7ff3, 0xfc78, 0x7ff3, 0xfc72, 0x7ff3, 0xfc6b, 0x7ff2, 0xfc65,
+ 0x7ff2, 0xfc5f, 0x7ff2, 0xfc58, 0x7ff2, 0xfc52, 0x7ff2, 0xfc4c,
+ 0x7ff2, 0xfc46, 0x7ff1, 0xfc3f, 0x7ff1, 0xfc39, 0x7ff1, 0xfc33,
+ 0x7ff1, 0xfc2c, 0x7ff1, 0xfc26, 0x7ff0, 0xfc20, 0x7ff0, 0xfc1a,
+ 0x7ff0, 0xfc13, 0x7ff0, 0xfc0d, 0x7ff0, 0xfc07, 0x7fef, 0xfc01,
+ 0x7fef, 0xfbfa, 0x7fef, 0xfbf4, 0x7fef, 0xfbee, 0x7fef, 0xfbe7,
+ 0x7fee, 0xfbe1, 0x7fee, 0xfbdb, 0x7fee, 0xfbd5, 0x7fee, 0xfbce,
+ 0x7fee, 0xfbc8, 0x7fed, 0xfbc2, 0x7fed, 0xfbbb, 0x7fed, 0xfbb5,
+ 0x7fed, 0xfbaf, 0x7fed, 0xfba9, 0x7fec, 0xfba2, 0x7fec, 0xfb9c,
+ 0x7fec, 0xfb96, 0x7fec, 0xfb8f, 0x7fec, 0xfb89, 0x7feb, 0xfb83,
+ 0x7feb, 0xfb7d, 0x7feb, 0xfb76, 0x7feb, 0xfb70, 0x7fea, 0xfb6a,
+ 0x7fea, 0xfb64, 0x7fea, 0xfb5d, 0x7fea, 0xfb57, 0x7fea, 0xfb51,
+ 0x7fe9, 0xfb4a, 0x7fe9, 0xfb44, 0x7fe9, 0xfb3e, 0x7fe9, 0xfb38,
+ 0x7fe8, 0xfb31, 0x7fe8, 0xfb2b, 0x7fe8, 0xfb25, 0x7fe8, 0xfb1e,
+ 0x7fe7, 0xfb18, 0x7fe7, 0xfb12, 0x7fe7, 0xfb0c, 0x7fe7, 0xfb05,
+ 0x7fe6, 0xfaff, 0x7fe6, 0xfaf9, 0x7fe6, 0xfaf3, 0x7fe6, 0xfaec,
+ 0x7fe5, 0xfae6, 0x7fe5, 0xfae0, 0x7fe5, 0xfad9, 0x7fe5, 0xfad3,
+ 0x7fe4, 0xfacd, 0x7fe4, 0xfac7, 0x7fe4, 0xfac0, 0x7fe4, 0xfaba,
+ 0x7fe3, 0xfab4, 0x7fe3, 0xfaad, 0x7fe3, 0xfaa7, 0x7fe3, 0xfaa1,
+ 0x7fe2, 0xfa9b, 0x7fe2, 0xfa94, 0x7fe2, 0xfa8e, 0x7fe2, 0xfa88,
+ 0x7fe1, 0xfa81, 0x7fe1, 0xfa7b, 0x7fe1, 0xfa75, 0x7fe0, 0xfa6f,
+ 0x7fe0, 0xfa68, 0x7fe0, 0xfa62, 0x7fe0, 0xfa5c, 0x7fdf, 0xfa56,
+ 0x7fdf, 0xfa4f, 0x7fdf, 0xfa49, 0x7fdf, 0xfa43, 0x7fde, 0xfa3c,
+ 0x7fde, 0xfa36, 0x7fde, 0xfa30, 0x7fdd, 0xfa2a, 0x7fdd, 0xfa23,
+ 0x7fdd, 0xfa1d, 0x7fdd, 0xfa17, 0x7fdc, 0xfa11, 0x7fdc, 0xfa0a,
+ 0x7fdc, 0xfa04, 0x7fdb, 0xf9fe, 0x7fdb, 0xf9f7, 0x7fdb, 0xf9f1,
+ 0x7fda, 0xf9eb, 0x7fda, 0xf9e5, 0x7fda, 0xf9de, 0x7fda, 0xf9d8,
+ 0x7fd9, 0xf9d2, 0x7fd9, 0xf9cb, 0x7fd9, 0xf9c5, 0x7fd8, 0xf9bf,
+ 0x7fd8, 0xf9b9, 0x7fd8, 0xf9b2, 0x7fd7, 0xf9ac, 0x7fd7, 0xf9a6,
+ 0x7fd7, 0xf9a0, 0x7fd6, 0xf999, 0x7fd6, 0xf993, 0x7fd6, 0xf98d,
+ 0x7fd6, 0xf986, 0x7fd5, 0xf980, 0x7fd5, 0xf97a, 0x7fd5, 0xf974,
+ 0x7fd4, 0xf96d, 0x7fd4, 0xf967, 0x7fd4, 0xf961, 0x7fd3, 0xf95b,
+ 0x7fd3, 0xf954, 0x7fd3, 0xf94e, 0x7fd2, 0xf948, 0x7fd2, 0xf941,
+ 0x7fd2, 0xf93b, 0x7fd1, 0xf935, 0x7fd1, 0xf92f, 0x7fd1, 0xf928,
+ 0x7fd0, 0xf922, 0x7fd0, 0xf91c, 0x7fd0, 0xf916, 0x7fcf, 0xf90f,
+ 0x7fcf, 0xf909, 0x7fcf, 0xf903, 0x7fce, 0xf8fc, 0x7fce, 0xf8f6,
+ 0x7fce, 0xf8f0, 0x7fcd, 0xf8ea, 0x7fcd, 0xf8e3, 0x7fcd, 0xf8dd,
+ 0x7fcc, 0xf8d7, 0x7fcc, 0xf8d0, 0x7fcb, 0xf8ca, 0x7fcb, 0xf8c4,
+ 0x7fcb, 0xf8be, 0x7fca, 0xf8b7, 0x7fca, 0xf8b1, 0x7fca, 0xf8ab,
+ 0x7fc9, 0xf8a5, 0x7fc9, 0xf89e, 0x7fc9, 0xf898, 0x7fc8, 0xf892,
+ 0x7fc8, 0xf88b, 0x7fc7, 0xf885, 0x7fc7, 0xf87f, 0x7fc7, 0xf879,
+ 0x7fc6, 0xf872, 0x7fc6, 0xf86c, 0x7fc6, 0xf866, 0x7fc5, 0xf860,
+ 0x7fc5, 0xf859, 0x7fc5, 0xf853, 0x7fc4, 0xf84d, 0x7fc4, 0xf846,
+ 0x7fc3, 0xf840, 0x7fc3, 0xf83a, 0x7fc3, 0xf834, 0x7fc2, 0xf82d,
+ 0x7fc2, 0xf827, 0x7fc1, 0xf821, 0x7fc1, 0xf81b, 0x7fc1, 0xf814,
+ 0x7fc0, 0xf80e, 0x7fc0, 0xf808, 0x7fc0, 0xf802, 0x7fbf, 0xf7fb,
+ 0x7fbf, 0xf7f5, 0x7fbe, 0xf7ef, 0x7fbe, 0xf7e8, 0x7fbe, 0xf7e2,
+ 0x7fbd, 0xf7dc, 0x7fbd, 0xf7d6, 0x7fbc, 0xf7cf, 0x7fbc, 0xf7c9,
+ 0x7fbc, 0xf7c3, 0x7fbb, 0xf7bd, 0x7fbb, 0xf7b6, 0x7fba, 0xf7b0,
+ 0x7fba, 0xf7aa, 0x7fb9, 0xf7a3, 0x7fb9, 0xf79d, 0x7fb9, 0xf797,
+ 0x7fb8, 0xf791, 0x7fb8, 0xf78a, 0x7fb7, 0xf784, 0x7fb7, 0xf77e,
+ 0x7fb7, 0xf778, 0x7fb6, 0xf771, 0x7fb6, 0xf76b, 0x7fb5, 0xf765,
+ 0x7fb5, 0xf75e, 0x7fb4, 0xf758, 0x7fb4, 0xf752, 0x7fb4, 0xf74c,
+ 0x7fb3, 0xf745, 0x7fb3, 0xf73f, 0x7fb2, 0xf739, 0x7fb2, 0xf733,
+ 0x7fb1, 0xf72c, 0x7fb1, 0xf726, 0x7fb1, 0xf720, 0x7fb0, 0xf71a,
+ 0x7fb0, 0xf713, 0x7faf, 0xf70d, 0x7faf, 0xf707, 0x7fae, 0xf700,
+ 0x7fae, 0xf6fa, 0x7fae, 0xf6f4, 0x7fad, 0xf6ee, 0x7fad, 0xf6e7,
+ 0x7fac, 0xf6e1, 0x7fac, 0xf6db, 0x7fab, 0xf6d5, 0x7fab, 0xf6ce,
+ 0x7faa, 0xf6c8, 0x7faa, 0xf6c2, 0x7fa9, 0xf6bc, 0x7fa9, 0xf6b5,
+ 0x7fa9, 0xf6af, 0x7fa8, 0xf6a9, 0x7fa8, 0xf6a2, 0x7fa7, 0xf69c,
+ 0x7fa7, 0xf696, 0x7fa6, 0xf690, 0x7fa6, 0xf689, 0x7fa5, 0xf683,
+ 0x7fa5, 0xf67d, 0x7fa4, 0xf677, 0x7fa4, 0xf670, 0x7fa3, 0xf66a,
+ 0x7fa3, 0xf664, 0x7fa3, 0xf65e, 0x7fa2, 0xf657, 0x7fa2, 0xf651,
+ 0x7fa1, 0xf64b, 0x7fa1, 0xf644, 0x7fa0, 0xf63e, 0x7fa0, 0xf638,
+ 0x7f9f, 0xf632, 0x7f9f, 0xf62b, 0x7f9e, 0xf625, 0x7f9e, 0xf61f,
+ 0x7f9d, 0xf619, 0x7f9d, 0xf612, 0x7f9c, 0xf60c, 0x7f9c, 0xf606,
+ 0x7f9b, 0xf600, 0x7f9b, 0xf5f9, 0x7f9a, 0xf5f3, 0x7f9a, 0xf5ed,
+ 0x7f99, 0xf5e7, 0x7f99, 0xf5e0, 0x7f98, 0xf5da, 0x7f98, 0xf5d4,
+ 0x7f97, 0xf5cd, 0x7f97, 0xf5c7, 0x7f96, 0xf5c1, 0x7f96, 0xf5bb,
+ 0x7f95, 0xf5b4, 0x7f95, 0xf5ae, 0x7f94, 0xf5a8, 0x7f94, 0xf5a2,
+ 0x7f93, 0xf59b, 0x7f93, 0xf595, 0x7f92, 0xf58f, 0x7f92, 0xf589,
+ 0x7f91, 0xf582, 0x7f91, 0xf57c, 0x7f90, 0xf576, 0x7f90, 0xf570,
+ 0x7f8f, 0xf569, 0x7f8f, 0xf563, 0x7f8e, 0xf55d, 0x7f8e, 0xf556,
+ 0x7f8d, 0xf550, 0x7f8d, 0xf54a, 0x7f8c, 0xf544, 0x7f8b, 0xf53d,
+ 0x7f8b, 0xf537, 0x7f8a, 0xf531, 0x7f8a, 0xf52b, 0x7f89, 0xf524,
+ 0x7f89, 0xf51e, 0x7f88, 0xf518, 0x7f88, 0xf512, 0x7f87, 0xf50b,
+ 0x7f87, 0xf505, 0x7f86, 0xf4ff, 0x7f86, 0xf4f9, 0x7f85, 0xf4f2,
+ 0x7f85, 0xf4ec, 0x7f84, 0xf4e6, 0x7f83, 0xf4e0, 0x7f83, 0xf4d9,
+ 0x7f82, 0xf4d3, 0x7f82, 0xf4cd, 0x7f81, 0xf4c6, 0x7f81, 0xf4c0,
+ 0x7f80, 0xf4ba, 0x7f80, 0xf4b4, 0x7f7f, 0xf4ad, 0x7f7e, 0xf4a7,
+ 0x7f7e, 0xf4a1, 0x7f7d, 0xf49b, 0x7f7d, 0xf494, 0x7f7c, 0xf48e,
+ 0x7f7c, 0xf488, 0x7f7b, 0xf482, 0x7f7b, 0xf47b, 0x7f7a, 0xf475,
+ 0x7f79, 0xf46f, 0x7f79, 0xf469, 0x7f78, 0xf462, 0x7f78, 0xf45c,
+ 0x7f77, 0xf456, 0x7f77, 0xf450, 0x7f76, 0xf449, 0x7f75, 0xf443,
+ 0x7f75, 0xf43d, 0x7f74, 0xf437, 0x7f74, 0xf430, 0x7f73, 0xf42a,
+ 0x7f72, 0xf424, 0x7f72, 0xf41e, 0x7f71, 0xf417, 0x7f71, 0xf411,
+ 0x7f70, 0xf40b, 0x7f70, 0xf405, 0x7f6f, 0xf3fe, 0x7f6e, 0xf3f8,
+ 0x7f6e, 0xf3f2, 0x7f6d, 0xf3ec, 0x7f6d, 0xf3e5, 0x7f6c, 0xf3df,
+ 0x7f6b, 0xf3d9, 0x7f6b, 0xf3d2, 0x7f6a, 0xf3cc, 0x7f6a, 0xf3c6,
+ 0x7f69, 0xf3c0, 0x7f68, 0xf3b9, 0x7f68, 0xf3b3, 0x7f67, 0xf3ad,
+ 0x7f67, 0xf3a7, 0x7f66, 0xf3a0, 0x7f65, 0xf39a, 0x7f65, 0xf394,
+ 0x7f64, 0xf38e, 0x7f64, 0xf387, 0x7f63, 0xf381, 0x7f62, 0xf37b,
+ 0x7f62, 0xf375, 0x7f61, 0xf36e, 0x7f60, 0xf368, 0x7f60, 0xf362,
+ 0x7f5f, 0xf35c, 0x7f5f, 0xf355, 0x7f5e, 0xf34f, 0x7f5d, 0xf349,
+ 0x7f5d, 0xf343, 0x7f5c, 0xf33c, 0x7f5b, 0xf336, 0x7f5b, 0xf330,
+ 0x7f5a, 0xf32a, 0x7f5a, 0xf323, 0x7f59, 0xf31d, 0x7f58, 0xf317,
+ 0x7f58, 0xf311, 0x7f57, 0xf30a, 0x7f56, 0xf304, 0x7f56, 0xf2fe,
+ 0x7f55, 0xf2f8, 0x7f55, 0xf2f1, 0x7f54, 0xf2eb, 0x7f53, 0xf2e5,
+ 0x7f53, 0xf2df, 0x7f52, 0xf2d8, 0x7f51, 0xf2d2, 0x7f51, 0xf2cc,
+ 0x7f50, 0xf2c6, 0x7f4f, 0xf2bf, 0x7f4f, 0xf2b9, 0x7f4e, 0xf2b3,
+ 0x7f4d, 0xf2ad, 0x7f4d, 0xf2a6, 0x7f4c, 0xf2a0, 0x7f4b, 0xf29a,
+ 0x7f4b, 0xf294, 0x7f4a, 0xf28d, 0x7f49, 0xf287, 0x7f49, 0xf281,
+ 0x7f48, 0xf27b, 0x7f47, 0xf274, 0x7f47, 0xf26e, 0x7f46, 0xf268,
+ 0x7f45, 0xf262, 0x7f45, 0xf25b, 0x7f44, 0xf255, 0x7f43, 0xf24f,
+ 0x7f43, 0xf249, 0x7f42, 0xf242, 0x7f41, 0xf23c, 0x7f41, 0xf236,
+ 0x7f40, 0xf230, 0x7f3f, 0xf229, 0x7f3f, 0xf223, 0x7f3e, 0xf21d,
+ 0x7f3d, 0xf217, 0x7f3d, 0xf210, 0x7f3c, 0xf20a, 0x7f3b, 0xf204,
+ 0x7f3b, 0xf1fe, 0x7f3a, 0xf1f7, 0x7f39, 0xf1f1, 0x7f39, 0xf1eb,
+ 0x7f38, 0xf1e5, 0x7f37, 0xf1de, 0x7f36, 0xf1d8, 0x7f36, 0xf1d2,
+ 0x7f35, 0xf1cc, 0x7f34, 0xf1c6, 0x7f34, 0xf1bf, 0x7f33, 0xf1b9,
+ 0x7f32, 0xf1b3, 0x7f32, 0xf1ad, 0x7f31, 0xf1a6, 0x7f30, 0xf1a0,
+ 0x7f2f, 0xf19a, 0x7f2f, 0xf194, 0x7f2e, 0xf18d, 0x7f2d, 0xf187,
+ 0x7f2d, 0xf181, 0x7f2c, 0xf17b, 0x7f2b, 0xf174, 0x7f2a, 0xf16e,
+ 0x7f2a, 0xf168, 0x7f29, 0xf162, 0x7f28, 0xf15b, 0x7f28, 0xf155,
+ 0x7f27, 0xf14f, 0x7f26, 0xf149, 0x7f25, 0xf142, 0x7f25, 0xf13c,
+ 0x7f24, 0xf136, 0x7f23, 0xf130, 0x7f23, 0xf129, 0x7f22, 0xf123,
+ 0x7f21, 0xf11d, 0x7f20, 0xf117, 0x7f20, 0xf110, 0x7f1f, 0xf10a,
+ 0x7f1e, 0xf104, 0x7f1d, 0xf0fe, 0x7f1d, 0xf0f8, 0x7f1c, 0xf0f1,
+ 0x7f1b, 0xf0eb, 0x7f1a, 0xf0e5, 0x7f1a, 0xf0df, 0x7f19, 0xf0d8,
+ 0x7f18, 0xf0d2, 0x7f17, 0xf0cc, 0x7f17, 0xf0c6, 0x7f16, 0xf0bf,
+ 0x7f15, 0xf0b9, 0x7f14, 0xf0b3, 0x7f14, 0xf0ad, 0x7f13, 0xf0a6,
+ 0x7f12, 0xf0a0, 0x7f11, 0xf09a, 0x7f11, 0xf094, 0x7f10, 0xf08d,
+ 0x7f0f, 0xf087, 0x7f0e, 0xf081, 0x7f0e, 0xf07b, 0x7f0d, 0xf075,
+ 0x7f0c, 0xf06e, 0x7f0b, 0xf068, 0x7f0b, 0xf062, 0x7f0a, 0xf05c,
+ 0x7f09, 0xf055, 0x7f08, 0xf04f, 0x7f08, 0xf049, 0x7f07, 0xf043,
+ 0x7f06, 0xf03c, 0x7f05, 0xf036, 0x7f04, 0xf030, 0x7f04, 0xf02a,
+ 0x7f03, 0xf023, 0x7f02, 0xf01d, 0x7f01, 0xf017, 0x7f01, 0xf011,
+ 0x7f00, 0xf00b, 0x7eff, 0xf004, 0x7efe, 0xeffe, 0x7efd, 0xeff8,
+ 0x7efd, 0xeff2, 0x7efc, 0xefeb, 0x7efb, 0xefe5, 0x7efa, 0xefdf,
+ 0x7ef9, 0xefd9, 0x7ef9, 0xefd2, 0x7ef8, 0xefcc, 0x7ef7, 0xefc6,
+ 0x7ef6, 0xefc0, 0x7ef5, 0xefb9, 0x7ef5, 0xefb3, 0x7ef4, 0xefad,
+ 0x7ef3, 0xefa7, 0x7ef2, 0xefa1, 0x7ef1, 0xef9a, 0x7ef1, 0xef94,
+ 0x7ef0, 0xef8e, 0x7eef, 0xef88, 0x7eee, 0xef81, 0x7eed, 0xef7b,
+ 0x7eed, 0xef75, 0x7eec, 0xef6f, 0x7eeb, 0xef68, 0x7eea, 0xef62,
+ 0x7ee9, 0xef5c, 0x7ee9, 0xef56, 0x7ee8, 0xef50, 0x7ee7, 0xef49,
+ 0x7ee6, 0xef43, 0x7ee5, 0xef3d, 0x7ee4, 0xef37, 0x7ee4, 0xef30,
+ 0x7ee3, 0xef2a, 0x7ee2, 0xef24, 0x7ee1, 0xef1e, 0x7ee0, 0xef18,
+ 0x7edf, 0xef11, 0x7edf, 0xef0b, 0x7ede, 0xef05, 0x7edd, 0xeeff,
+ 0x7edc, 0xeef8, 0x7edb, 0xeef2, 0x7eda, 0xeeec, 0x7eda, 0xeee6,
+ 0x7ed9, 0xeedf, 0x7ed8, 0xeed9, 0x7ed7, 0xeed3, 0x7ed6, 0xeecd,
+ 0x7ed5, 0xeec7, 0x7ed5, 0xeec0, 0x7ed4, 0xeeba, 0x7ed3, 0xeeb4,
+ 0x7ed2, 0xeeae, 0x7ed1, 0xeea7, 0x7ed0, 0xeea1, 0x7ecf, 0xee9b,
+ 0x7ecf, 0xee95, 0x7ece, 0xee8f, 0x7ecd, 0xee88, 0x7ecc, 0xee82,
+ 0x7ecb, 0xee7c, 0x7eca, 0xee76, 0x7ec9, 0xee6f, 0x7ec9, 0xee69,
+ 0x7ec8, 0xee63, 0x7ec7, 0xee5d, 0x7ec6, 0xee57, 0x7ec5, 0xee50,
+ 0x7ec4, 0xee4a, 0x7ec3, 0xee44, 0x7ec3, 0xee3e, 0x7ec2, 0xee37,
+ 0x7ec1, 0xee31, 0x7ec0, 0xee2b, 0x7ebf, 0xee25, 0x7ebe, 0xee1f,
+ 0x7ebd, 0xee18, 0x7ebc, 0xee12, 0x7ebb, 0xee0c, 0x7ebb, 0xee06,
+ 0x7eba, 0xedff, 0x7eb9, 0xedf9, 0x7eb8, 0xedf3, 0x7eb7, 0xeded,
+ 0x7eb6, 0xede7, 0x7eb5, 0xede0, 0x7eb4, 0xedda, 0x7eb4, 0xedd4,
+ 0x7eb3, 0xedce, 0x7eb2, 0xedc7, 0x7eb1, 0xedc1, 0x7eb0, 0xedbb,
+ 0x7eaf, 0xedb5, 0x7eae, 0xedaf, 0x7ead, 0xeda8, 0x7eac, 0xeda2,
+ 0x7eab, 0xed9c, 0x7eab, 0xed96, 0x7eaa, 0xed8f, 0x7ea9, 0xed89,
+ 0x7ea8, 0xed83, 0x7ea7, 0xed7d, 0x7ea6, 0xed77, 0x7ea5, 0xed70,
+ 0x7ea4, 0xed6a, 0x7ea3, 0xed64, 0x7ea2, 0xed5e, 0x7ea1, 0xed58,
+ 0x7ea1, 0xed51, 0x7ea0, 0xed4b, 0x7e9f, 0xed45, 0x7e9e, 0xed3f,
+ 0x7e9d, 0xed38, 0x7e9c, 0xed32, 0x7e9b, 0xed2c, 0x7e9a, 0xed26,
+ 0x7e99, 0xed20, 0x7e98, 0xed19, 0x7e97, 0xed13, 0x7e96, 0xed0d,
+ 0x7e95, 0xed07, 0x7e94, 0xed01, 0x7e94, 0xecfa, 0x7e93, 0xecf4,
+ 0x7e92, 0xecee, 0x7e91, 0xece8, 0x7e90, 0xece1, 0x7e8f, 0xecdb,
+ 0x7e8e, 0xecd5, 0x7e8d, 0xeccf, 0x7e8c, 0xecc9, 0x7e8b, 0xecc2,
+ 0x7e8a, 0xecbc, 0x7e89, 0xecb6, 0x7e88, 0xecb0, 0x7e87, 0xecaa,
+ 0x7e86, 0xeca3, 0x7e85, 0xec9d, 0x7e84, 0xec97, 0x7e84, 0xec91,
+ 0x7e83, 0xec8a, 0x7e82, 0xec84, 0x7e81, 0xec7e, 0x7e80, 0xec78,
+ 0x7e7f, 0xec72, 0x7e7e, 0xec6b, 0x7e7d, 0xec65, 0x7e7c, 0xec5f,
+ 0x7e7b, 0xec59, 0x7e7a, 0xec53, 0x7e79, 0xec4c, 0x7e78, 0xec46,
+ 0x7e77, 0xec40, 0x7e76, 0xec3a, 0x7e75, 0xec34, 0x7e74, 0xec2d,
+ 0x7e73, 0xec27, 0x7e72, 0xec21, 0x7e71, 0xec1b, 0x7e70, 0xec15,
+ 0x7e6f, 0xec0e, 0x7e6e, 0xec08, 0x7e6d, 0xec02, 0x7e6c, 0xebfc,
+ 0x7e6b, 0xebf5, 0x7e6a, 0xebef, 0x7e69, 0xebe9, 0x7e68, 0xebe3,
+ 0x7e67, 0xebdd, 0x7e66, 0xebd6, 0x7e65, 0xebd0, 0x7e64, 0xebca,
+ 0x7e63, 0xebc4, 0x7e62, 0xebbe, 0x7e61, 0xebb7, 0x7e60, 0xebb1,
+ 0x7e5f, 0xebab, 0x7e5e, 0xeba5, 0x7e5d, 0xeb9f, 0x7e5c, 0xeb98,
+ 0x7e5b, 0xeb92, 0x7e5a, 0xeb8c, 0x7e59, 0xeb86, 0x7e58, 0xeb80,
+ 0x7e57, 0xeb79, 0x7e56, 0xeb73, 0x7e55, 0xeb6d, 0x7e54, 0xeb67,
+ 0x7e53, 0xeb61, 0x7e52, 0xeb5a, 0x7e51, 0xeb54, 0x7e50, 0xeb4e,
+ 0x7e4f, 0xeb48, 0x7e4e, 0xeb42, 0x7e4d, 0xeb3b, 0x7e4c, 0xeb35,
+ 0x7e4b, 0xeb2f, 0x7e4a, 0xeb29, 0x7e49, 0xeb23, 0x7e48, 0xeb1c,
+ 0x7e47, 0xeb16, 0x7e46, 0xeb10, 0x7e45, 0xeb0a, 0x7e44, 0xeb04,
+ 0x7e43, 0xeafd, 0x7e42, 0xeaf7, 0x7e41, 0xeaf1, 0x7e40, 0xeaeb,
+ 0x7e3f, 0xeae5, 0x7e3e, 0xeade, 0x7e3d, 0xead8, 0x7e3c, 0xead2,
+ 0x7e3b, 0xeacc, 0x7e3a, 0xeac6, 0x7e39, 0xeabf, 0x7e38, 0xeab9,
+ 0x7e37, 0xeab3, 0x7e35, 0xeaad, 0x7e34, 0xeaa7, 0x7e33, 0xeaa0,
+ 0x7e32, 0xea9a, 0x7e31, 0xea94, 0x7e30, 0xea8e, 0x7e2f, 0xea88,
+ 0x7e2e, 0xea81, 0x7e2d, 0xea7b, 0x7e2c, 0xea75, 0x7e2b, 0xea6f,
+ 0x7e2a, 0xea69, 0x7e29, 0xea63, 0x7e28, 0xea5c, 0x7e27, 0xea56,
+ 0x7e26, 0xea50, 0x7e25, 0xea4a, 0x7e24, 0xea44, 0x7e22, 0xea3d,
+ 0x7e21, 0xea37, 0x7e20, 0xea31, 0x7e1f, 0xea2b, 0x7e1e, 0xea25,
+ 0x7e1d, 0xea1e, 0x7e1c, 0xea18, 0x7e1b, 0xea12, 0x7e1a, 0xea0c,
+ 0x7e19, 0xea06, 0x7e18, 0xe9ff, 0x7e17, 0xe9f9, 0x7e16, 0xe9f3,
+ 0x7e14, 0xe9ed, 0x7e13, 0xe9e7, 0x7e12, 0xe9e1, 0x7e11, 0xe9da,
+ 0x7e10, 0xe9d4, 0x7e0f, 0xe9ce, 0x7e0e, 0xe9c8, 0x7e0d, 0xe9c2,
+ 0x7e0c, 0xe9bb, 0x7e0b, 0xe9b5, 0x7e0a, 0xe9af, 0x7e08, 0xe9a9,
+ 0x7e07, 0xe9a3, 0x7e06, 0xe99c, 0x7e05, 0xe996, 0x7e04, 0xe990,
+ 0x7e03, 0xe98a, 0x7e02, 0xe984, 0x7e01, 0xe97e, 0x7e00, 0xe977,
+ 0x7dff, 0xe971, 0x7dfd, 0xe96b, 0x7dfc, 0xe965, 0x7dfb, 0xe95f,
+ 0x7dfa, 0xe958, 0x7df9, 0xe952, 0x7df8, 0xe94c, 0x7df7, 0xe946,
+ 0x7df6, 0xe940, 0x7df5, 0xe93a, 0x7df3, 0xe933, 0x7df2, 0xe92d,
+ 0x7df1, 0xe927, 0x7df0, 0xe921, 0x7def, 0xe91b, 0x7dee, 0xe914,
+ 0x7ded, 0xe90e, 0x7dec, 0xe908, 0x7dea, 0xe902, 0x7de9, 0xe8fc,
+ 0x7de8, 0xe8f6, 0x7de7, 0xe8ef, 0x7de6, 0xe8e9, 0x7de5, 0xe8e3,
+ 0x7de4, 0xe8dd, 0x7de2, 0xe8d7, 0x7de1, 0xe8d0, 0x7de0, 0xe8ca,
+ 0x7ddf, 0xe8c4, 0x7dde, 0xe8be, 0x7ddd, 0xe8b8, 0x7ddc, 0xe8b2,
+ 0x7dda, 0xe8ab, 0x7dd9, 0xe8a5, 0x7dd8, 0xe89f, 0x7dd7, 0xe899,
+ 0x7dd6, 0xe893, 0x7dd5, 0xe88c, 0x7dd4, 0xe886, 0x7dd2, 0xe880,
+ 0x7dd1, 0xe87a, 0x7dd0, 0xe874, 0x7dcf, 0xe86e, 0x7dce, 0xe867,
+ 0x7dcd, 0xe861, 0x7dcc, 0xe85b, 0x7dca, 0xe855, 0x7dc9, 0xe84f,
+ 0x7dc8, 0xe849, 0x7dc7, 0xe842, 0x7dc6, 0xe83c, 0x7dc5, 0xe836,
+ 0x7dc3, 0xe830, 0x7dc2, 0xe82a, 0x7dc1, 0xe823, 0x7dc0, 0xe81d,
+ 0x7dbf, 0xe817, 0x7dbd, 0xe811, 0x7dbc, 0xe80b, 0x7dbb, 0xe805,
+ 0x7dba, 0xe7fe, 0x7db9, 0xe7f8, 0x7db8, 0xe7f2, 0x7db6, 0xe7ec,
+ 0x7db5, 0xe7e6, 0x7db4, 0xe7e0, 0x7db3, 0xe7d9, 0x7db2, 0xe7d3,
+ 0x7db0, 0xe7cd, 0x7daf, 0xe7c7, 0x7dae, 0xe7c1, 0x7dad, 0xe7bb,
+ 0x7dac, 0xe7b4, 0x7dab, 0xe7ae, 0x7da9, 0xe7a8, 0x7da8, 0xe7a2,
+ 0x7da7, 0xe79c, 0x7da6, 0xe796, 0x7da5, 0xe78f, 0x7da3, 0xe789,
+ 0x7da2, 0xe783, 0x7da1, 0xe77d, 0x7da0, 0xe777, 0x7d9f, 0xe771,
+ 0x7d9d, 0xe76a, 0x7d9c, 0xe764, 0x7d9b, 0xe75e, 0x7d9a, 0xe758,
+ 0x7d98, 0xe752, 0x7d97, 0xe74c, 0x7d96, 0xe745, 0x7d95, 0xe73f,
+ 0x7d94, 0xe739, 0x7d92, 0xe733, 0x7d91, 0xe72d, 0x7d90, 0xe727,
+ 0x7d8f, 0xe720, 0x7d8e, 0xe71a, 0x7d8c, 0xe714, 0x7d8b, 0xe70e,
+ 0x7d8a, 0xe708, 0x7d89, 0xe702, 0x7d87, 0xe6fb, 0x7d86, 0xe6f5,
+ 0x7d85, 0xe6ef, 0x7d84, 0xe6e9, 0x7d82, 0xe6e3, 0x7d81, 0xe6dd,
+ 0x7d80, 0xe6d6, 0x7d7f, 0xe6d0, 0x7d7e, 0xe6ca, 0x7d7c, 0xe6c4,
+ 0x7d7b, 0xe6be, 0x7d7a, 0xe6b8, 0x7d79, 0xe6b2, 0x7d77, 0xe6ab,
+ 0x7d76, 0xe6a5, 0x7d75, 0xe69f, 0x7d74, 0xe699, 0x7d72, 0xe693,
+ 0x7d71, 0xe68d, 0x7d70, 0xe686, 0x7d6f, 0xe680, 0x7d6d, 0xe67a,
+ 0x7d6c, 0xe674, 0x7d6b, 0xe66e, 0x7d6a, 0xe668, 0x7d68, 0xe661,
+ 0x7d67, 0xe65b, 0x7d66, 0xe655, 0x7d65, 0xe64f, 0x7d63, 0xe649,
+ 0x7d62, 0xe643, 0x7d61, 0xe63d, 0x7d60, 0xe636, 0x7d5e, 0xe630,
+ 0x7d5d, 0xe62a, 0x7d5c, 0xe624, 0x7d5a, 0xe61e, 0x7d59, 0xe618,
+ 0x7d58, 0xe611, 0x7d57, 0xe60b, 0x7d55, 0xe605, 0x7d54, 0xe5ff,
+ 0x7d53, 0xe5f9, 0x7d52, 0xe5f3, 0x7d50, 0xe5ed, 0x7d4f, 0xe5e6,
+ 0x7d4e, 0xe5e0, 0x7d4c, 0xe5da, 0x7d4b, 0xe5d4, 0x7d4a, 0xe5ce,
+ 0x7d49, 0xe5c8, 0x7d47, 0xe5c2, 0x7d46, 0xe5bb, 0x7d45, 0xe5b5,
+ 0x7d43, 0xe5af, 0x7d42, 0xe5a9, 0x7d41, 0xe5a3, 0x7d3f, 0xe59d,
+ 0x7d3e, 0xe596, 0x7d3d, 0xe590, 0x7d3c, 0xe58a, 0x7d3a, 0xe584,
+ 0x7d39, 0xe57e, 0x7d38, 0xe578, 0x7d36, 0xe572, 0x7d35, 0xe56b,
+ 0x7d34, 0xe565, 0x7d32, 0xe55f, 0x7d31, 0xe559, 0x7d30, 0xe553,
+ 0x7d2f, 0xe54d, 0x7d2d, 0xe547, 0x7d2c, 0xe540, 0x7d2b, 0xe53a,
+ 0x7d29, 0xe534, 0x7d28, 0xe52e, 0x7d27, 0xe528, 0x7d25, 0xe522,
+ 0x7d24, 0xe51c, 0x7d23, 0xe515, 0x7d21, 0xe50f, 0x7d20, 0xe509,
+ 0x7d1f, 0xe503, 0x7d1d, 0xe4fd, 0x7d1c, 0xe4f7, 0x7d1b, 0xe4f1,
+ 0x7d19, 0xe4ea, 0x7d18, 0xe4e4, 0x7d17, 0xe4de, 0x7d15, 0xe4d8,
+ 0x7d14, 0xe4d2, 0x7d13, 0xe4cc, 0x7d11, 0xe4c6, 0x7d10, 0xe4bf,
+ 0x7d0f, 0xe4b9, 0x7d0d, 0xe4b3, 0x7d0c, 0xe4ad, 0x7d0b, 0xe4a7,
+ 0x7d09, 0xe4a1, 0x7d08, 0xe49b, 0x7d07, 0xe494, 0x7d05, 0xe48e,
+ 0x7d04, 0xe488, 0x7d03, 0xe482, 0x7d01, 0xe47c, 0x7d00, 0xe476,
+ 0x7cff, 0xe470, 0x7cfd, 0xe46a, 0x7cfc, 0xe463, 0x7cfb, 0xe45d,
+ 0x7cf9, 0xe457, 0x7cf8, 0xe451, 0x7cf6, 0xe44b, 0x7cf5, 0xe445,
+ 0x7cf4, 0xe43f, 0x7cf2, 0xe438, 0x7cf1, 0xe432, 0x7cf0, 0xe42c,
+ 0x7cee, 0xe426, 0x7ced, 0xe420, 0x7cec, 0xe41a, 0x7cea, 0xe414,
+ 0x7ce9, 0xe40e, 0x7ce7, 0xe407, 0x7ce6, 0xe401, 0x7ce5, 0xe3fb,
+ 0x7ce3, 0xe3f5, 0x7ce2, 0xe3ef, 0x7ce1, 0xe3e9, 0x7cdf, 0xe3e3,
+ 0x7cde, 0xe3dc, 0x7cdc, 0xe3d6, 0x7cdb, 0xe3d0, 0x7cda, 0xe3ca,
+ 0x7cd8, 0xe3c4, 0x7cd7, 0xe3be, 0x7cd5, 0xe3b8, 0x7cd4, 0xe3b2,
+ 0x7cd3, 0xe3ab, 0x7cd1, 0xe3a5, 0x7cd0, 0xe39f, 0x7ccf, 0xe399,
+ 0x7ccd, 0xe393, 0x7ccc, 0xe38d, 0x7cca, 0xe387, 0x7cc9, 0xe381,
+ 0x7cc8, 0xe37a, 0x7cc6, 0xe374, 0x7cc5, 0xe36e, 0x7cc3, 0xe368,
+ 0x7cc2, 0xe362, 0x7cc1, 0xe35c, 0x7cbf, 0xe356, 0x7cbe, 0xe350,
+ 0x7cbc, 0xe349, 0x7cbb, 0xe343, 0x7cb9, 0xe33d, 0x7cb8, 0xe337,
+ 0x7cb7, 0xe331, 0x7cb5, 0xe32b, 0x7cb4, 0xe325, 0x7cb2, 0xe31f,
+ 0x7cb1, 0xe318, 0x7cb0, 0xe312, 0x7cae, 0xe30c, 0x7cad, 0xe306,
+ 0x7cab, 0xe300, 0x7caa, 0xe2fa, 0x7ca8, 0xe2f4, 0x7ca7, 0xe2ee,
+ 0x7ca6, 0xe2e8, 0x7ca4, 0xe2e1, 0x7ca3, 0xe2db, 0x7ca1, 0xe2d5,
+ 0x7ca0, 0xe2cf, 0x7c9e, 0xe2c9, 0x7c9d, 0xe2c3, 0x7c9c, 0xe2bd,
+ 0x7c9a, 0xe2b7, 0x7c99, 0xe2b0, 0x7c97, 0xe2aa, 0x7c96, 0xe2a4,
+ 0x7c94, 0xe29e, 0x7c93, 0xe298, 0x7c91, 0xe292, 0x7c90, 0xe28c,
+ 0x7c8f, 0xe286, 0x7c8d, 0xe280, 0x7c8c, 0xe279, 0x7c8a, 0xe273,
+ 0x7c89, 0xe26d, 0x7c87, 0xe267, 0x7c86, 0xe261, 0x7c84, 0xe25b,
+ 0x7c83, 0xe255, 0x7c82, 0xe24f, 0x7c80, 0xe249, 0x7c7f, 0xe242,
+ 0x7c7d, 0xe23c, 0x7c7c, 0xe236, 0x7c7a, 0xe230, 0x7c79, 0xe22a,
+ 0x7c77, 0xe224, 0x7c76, 0xe21e, 0x7c74, 0xe218, 0x7c73, 0xe212,
+ 0x7c71, 0xe20b, 0x7c70, 0xe205, 0x7c6e, 0xe1ff, 0x7c6d, 0xe1f9,
+ 0x7c6c, 0xe1f3, 0x7c6a, 0xe1ed, 0x7c69, 0xe1e7, 0x7c67, 0xe1e1,
+ 0x7c66, 0xe1db, 0x7c64, 0xe1d4, 0x7c63, 0xe1ce, 0x7c61, 0xe1c8,
+ 0x7c60, 0xe1c2, 0x7c5e, 0xe1bc, 0x7c5d, 0xe1b6, 0x7c5b, 0xe1b0,
+ 0x7c5a, 0xe1aa, 0x7c58, 0xe1a4, 0x7c57, 0xe19e, 0x7c55, 0xe197,
+ 0x7c54, 0xe191, 0x7c52, 0xe18b, 0x7c51, 0xe185, 0x7c4f, 0xe17f,
+ 0x7c4e, 0xe179, 0x7c4c, 0xe173, 0x7c4b, 0xe16d, 0x7c49, 0xe167,
+ 0x7c48, 0xe160, 0x7c46, 0xe15a, 0x7c45, 0xe154, 0x7c43, 0xe14e,
+ 0x7c42, 0xe148, 0x7c40, 0xe142, 0x7c3f, 0xe13c, 0x7c3d, 0xe136,
+ 0x7c3c, 0xe130, 0x7c3a, 0xe12a, 0x7c39, 0xe123, 0x7c37, 0xe11d,
+ 0x7c36, 0xe117, 0x7c34, 0xe111, 0x7c33, 0xe10b, 0x7c31, 0xe105,
+ 0x7c30, 0xe0ff, 0x7c2e, 0xe0f9, 0x7c2d, 0xe0f3, 0x7c2b, 0xe0ed,
+ 0x7c29, 0xe0e7, 0x7c28, 0xe0e0, 0x7c26, 0xe0da, 0x7c25, 0xe0d4,
+ 0x7c23, 0xe0ce, 0x7c22, 0xe0c8, 0x7c20, 0xe0c2, 0x7c1f, 0xe0bc,
+ 0x7c1d, 0xe0b6, 0x7c1c, 0xe0b0, 0x7c1a, 0xe0aa, 0x7c19, 0xe0a3,
+ 0x7c17, 0xe09d, 0x7c16, 0xe097, 0x7c14, 0xe091, 0x7c12, 0xe08b,
+ 0x7c11, 0xe085, 0x7c0f, 0xe07f, 0x7c0e, 0xe079, 0x7c0c, 0xe073,
+ 0x7c0b, 0xe06d, 0x7c09, 0xe067, 0x7c08, 0xe061, 0x7c06, 0xe05a,
+ 0x7c05, 0xe054, 0x7c03, 0xe04e, 0x7c01, 0xe048, 0x7c00, 0xe042,
+ 0x7bfe, 0xe03c, 0x7bfd, 0xe036, 0x7bfb, 0xe030, 0x7bfa, 0xe02a,
+ 0x7bf8, 0xe024, 0x7bf6, 0xe01e, 0x7bf5, 0xe017, 0x7bf3, 0xe011,
+ 0x7bf2, 0xe00b, 0x7bf0, 0xe005, 0x7bef, 0xdfff, 0x7bed, 0xdff9,
+ 0x7beb, 0xdff3, 0x7bea, 0xdfed, 0x7be8, 0xdfe7, 0x7be7, 0xdfe1,
+ 0x7be5, 0xdfdb, 0x7be4, 0xdfd5, 0x7be2, 0xdfce, 0x7be0, 0xdfc8,
+ 0x7bdf, 0xdfc2, 0x7bdd, 0xdfbc, 0x7bdc, 0xdfb6, 0x7bda, 0xdfb0,
+ 0x7bd9, 0xdfaa, 0x7bd7, 0xdfa4, 0x7bd5, 0xdf9e, 0x7bd4, 0xdf98,
+ 0x7bd2, 0xdf92, 0x7bd1, 0xdf8c, 0x7bcf, 0xdf86, 0x7bcd, 0xdf7f,
+ 0x7bcc, 0xdf79, 0x7bca, 0xdf73, 0x7bc9, 0xdf6d, 0x7bc7, 0xdf67,
+ 0x7bc5, 0xdf61, 0x7bc4, 0xdf5b, 0x7bc2, 0xdf55, 0x7bc1, 0xdf4f,
+ 0x7bbf, 0xdf49, 0x7bbd, 0xdf43, 0x7bbc, 0xdf3d, 0x7bba, 0xdf37,
+ 0x7bb9, 0xdf30, 0x7bb7, 0xdf2a, 0x7bb5, 0xdf24, 0x7bb4, 0xdf1e,
+ 0x7bb2, 0xdf18, 0x7bb0, 0xdf12, 0x7baf, 0xdf0c, 0x7bad, 0xdf06,
+ 0x7bac, 0xdf00, 0x7baa, 0xdefa, 0x7ba8, 0xdef4, 0x7ba7, 0xdeee,
+ 0x7ba5, 0xdee8, 0x7ba3, 0xdee2, 0x7ba2, 0xdedb, 0x7ba0, 0xded5,
+ 0x7b9f, 0xdecf, 0x7b9d, 0xdec9, 0x7b9b, 0xdec3, 0x7b9a, 0xdebd,
+ 0x7b98, 0xdeb7, 0x7b96, 0xdeb1, 0x7b95, 0xdeab, 0x7b93, 0xdea5,
+ 0x7b92, 0xde9f, 0x7b90, 0xde99, 0x7b8e, 0xde93, 0x7b8d, 0xde8d,
+ 0x7b8b, 0xde87, 0x7b89, 0xde80, 0x7b88, 0xde7a, 0x7b86, 0xde74,
+ 0x7b84, 0xde6e, 0x7b83, 0xde68, 0x7b81, 0xde62, 0x7b7f, 0xde5c,
+ 0x7b7e, 0xde56, 0x7b7c, 0xde50, 0x7b7a, 0xde4a, 0x7b79, 0xde44,
+ 0x7b77, 0xde3e, 0x7b76, 0xde38, 0x7b74, 0xde32, 0x7b72, 0xde2c,
+ 0x7b71, 0xde26, 0x7b6f, 0xde1f, 0x7b6d, 0xde19, 0x7b6c, 0xde13,
+ 0x7b6a, 0xde0d, 0x7b68, 0xde07, 0x7b67, 0xde01, 0x7b65, 0xddfb,
+ 0x7b63, 0xddf5, 0x7b62, 0xddef, 0x7b60, 0xdde9, 0x7b5e, 0xdde3,
+ 0x7b5d, 0xdddd, 0x7b5b, 0xddd7, 0x7b59, 0xddd1, 0x7b57, 0xddcb,
+ 0x7b56, 0xddc5, 0x7b54, 0xddbf, 0x7b52, 0xddb9, 0x7b51, 0xddb2,
+ 0x7b4f, 0xddac, 0x7b4d, 0xdda6, 0x7b4c, 0xdda0, 0x7b4a, 0xdd9a,
+ 0x7b48, 0xdd94, 0x7b47, 0xdd8e, 0x7b45, 0xdd88, 0x7b43, 0xdd82,
+ 0x7b42, 0xdd7c, 0x7b40, 0xdd76, 0x7b3e, 0xdd70, 0x7b3c, 0xdd6a,
+ 0x7b3b, 0xdd64, 0x7b39, 0xdd5e, 0x7b37, 0xdd58, 0x7b36, 0xdd52,
+ 0x7b34, 0xdd4c, 0x7b32, 0xdd46, 0x7b31, 0xdd40, 0x7b2f, 0xdd39,
+ 0x7b2d, 0xdd33, 0x7b2b, 0xdd2d, 0x7b2a, 0xdd27, 0x7b28, 0xdd21,
+ 0x7b26, 0xdd1b, 0x7b25, 0xdd15, 0x7b23, 0xdd0f, 0x7b21, 0xdd09,
+ 0x7b1f, 0xdd03, 0x7b1e, 0xdcfd, 0x7b1c, 0xdcf7, 0x7b1a, 0xdcf1,
+ 0x7b19, 0xdceb, 0x7b17, 0xdce5, 0x7b15, 0xdcdf, 0x7b13, 0xdcd9,
+ 0x7b12, 0xdcd3, 0x7b10, 0xdccd, 0x7b0e, 0xdcc7, 0x7b0c, 0xdcc1,
+ 0x7b0b, 0xdcbb, 0x7b09, 0xdcb5, 0x7b07, 0xdcae, 0x7b06, 0xdca8,
+ 0x7b04, 0xdca2, 0x7b02, 0xdc9c, 0x7b00, 0xdc96, 0x7aff, 0xdc90,
+ 0x7afd, 0xdc8a, 0x7afb, 0xdc84, 0x7af9, 0xdc7e, 0x7af8, 0xdc78,
+ 0x7af6, 0xdc72, 0x7af4, 0xdc6c, 0x7af2, 0xdc66, 0x7af1, 0xdc60,
+ 0x7aef, 0xdc5a, 0x7aed, 0xdc54, 0x7aeb, 0xdc4e, 0x7aea, 0xdc48,
+ 0x7ae8, 0xdc42, 0x7ae6, 0xdc3c, 0x7ae4, 0xdc36, 0x7ae3, 0xdc30,
+ 0x7ae1, 0xdc2a, 0x7adf, 0xdc24, 0x7add, 0xdc1e, 0x7adc, 0xdc18,
+ 0x7ada, 0xdc12, 0x7ad8, 0xdc0c, 0x7ad6, 0xdc06, 0x7ad5, 0xdbff,
+ 0x7ad3, 0xdbf9, 0x7ad1, 0xdbf3, 0x7acf, 0xdbed, 0x7acd, 0xdbe7,
+ 0x7acc, 0xdbe1, 0x7aca, 0xdbdb, 0x7ac8, 0xdbd5, 0x7ac6, 0xdbcf,
+ 0x7ac5, 0xdbc9, 0x7ac3, 0xdbc3, 0x7ac1, 0xdbbd, 0x7abf, 0xdbb7,
+ 0x7abd, 0xdbb1, 0x7abc, 0xdbab, 0x7aba, 0xdba5, 0x7ab8, 0xdb9f,
+ 0x7ab6, 0xdb99, 0x7ab5, 0xdb93, 0x7ab3, 0xdb8d, 0x7ab1, 0xdb87,
+ 0x7aaf, 0xdb81, 0x7aad, 0xdb7b, 0x7aac, 0xdb75, 0x7aaa, 0xdb6f,
+ 0x7aa8, 0xdb69, 0x7aa6, 0xdb63, 0x7aa4, 0xdb5d, 0x7aa3, 0xdb57,
+ 0x7aa1, 0xdb51, 0x7a9f, 0xdb4b, 0x7a9d, 0xdb45, 0x7a9b, 0xdb3f,
+ 0x7a9a, 0xdb39, 0x7a98, 0xdb33, 0x7a96, 0xdb2d, 0x7a94, 0xdb27,
+ 0x7a92, 0xdb21, 0x7a91, 0xdb1b, 0x7a8f, 0xdb15, 0x7a8d, 0xdb0f,
+ 0x7a8b, 0xdb09, 0x7a89, 0xdb03, 0x7a87, 0xdafd, 0x7a86, 0xdaf7,
+ 0x7a84, 0xdaf1, 0x7a82, 0xdaea, 0x7a80, 0xdae4, 0x7a7e, 0xdade,
+ 0x7a7d, 0xdad8, 0x7a7b, 0xdad2, 0x7a79, 0xdacc, 0x7a77, 0xdac6,
+ 0x7a75, 0xdac0, 0x7a73, 0xdaba, 0x7a72, 0xdab4, 0x7a70, 0xdaae,
+ 0x7a6e, 0xdaa8, 0x7a6c, 0xdaa2, 0x7a6a, 0xda9c, 0x7a68, 0xda96,
+ 0x7a67, 0xda90, 0x7a65, 0xda8a, 0x7a63, 0xda84, 0x7a61, 0xda7e,
+ 0x7a5f, 0xda78, 0x7a5d, 0xda72, 0x7a5c, 0xda6c, 0x7a5a, 0xda66,
+ 0x7a58, 0xda60, 0x7a56, 0xda5a, 0x7a54, 0xda54, 0x7a52, 0xda4e,
+ 0x7a50, 0xda48, 0x7a4f, 0xda42, 0x7a4d, 0xda3c, 0x7a4b, 0xda36,
+ 0x7a49, 0xda30, 0x7a47, 0xda2a, 0x7a45, 0xda24, 0x7a43, 0xda1e,
+ 0x7a42, 0xda18, 0x7a40, 0xda12, 0x7a3e, 0xda0c, 0x7a3c, 0xda06,
+ 0x7a3a, 0xda00, 0x7a38, 0xd9fa, 0x7a36, 0xd9f4, 0x7a35, 0xd9ee,
+ 0x7a33, 0xd9e8, 0x7a31, 0xd9e2, 0x7a2f, 0xd9dc, 0x7a2d, 0xd9d6,
+ 0x7a2b, 0xd9d0, 0x7a29, 0xd9ca, 0x7a27, 0xd9c4, 0x7a26, 0xd9be,
+ 0x7a24, 0xd9b8, 0x7a22, 0xd9b2, 0x7a20, 0xd9ac, 0x7a1e, 0xd9a6,
+ 0x7a1c, 0xd9a0, 0x7a1a, 0xd99a, 0x7a18, 0xd994, 0x7a16, 0xd98e,
+ 0x7a15, 0xd988, 0x7a13, 0xd982, 0x7a11, 0xd97c, 0x7a0f, 0xd976,
+ 0x7a0d, 0xd970, 0x7a0b, 0xd96a, 0x7a09, 0xd964, 0x7a07, 0xd95e,
+ 0x7a05, 0xd958, 0x7a04, 0xd952, 0x7a02, 0xd94c, 0x7a00, 0xd946,
+ 0x79fe, 0xd940, 0x79fc, 0xd93a, 0x79fa, 0xd934, 0x79f8, 0xd92e,
+ 0x79f6, 0xd928, 0x79f4, 0xd922, 0x79f2, 0xd91c, 0x79f0, 0xd917,
+ 0x79ef, 0xd911, 0x79ed, 0xd90b, 0x79eb, 0xd905, 0x79e9, 0xd8ff,
+ 0x79e7, 0xd8f9, 0x79e5, 0xd8f3, 0x79e3, 0xd8ed, 0x79e1, 0xd8e7,
+ 0x79df, 0xd8e1, 0x79dd, 0xd8db, 0x79db, 0xd8d5, 0x79d9, 0xd8cf,
+ 0x79d8, 0xd8c9, 0x79d6, 0xd8c3, 0x79d4, 0xd8bd, 0x79d2, 0xd8b7,
+ 0x79d0, 0xd8b1, 0x79ce, 0xd8ab, 0x79cc, 0xd8a5, 0x79ca, 0xd89f,
+ 0x79c8, 0xd899, 0x79c6, 0xd893, 0x79c4, 0xd88d, 0x79c2, 0xd887,
+ 0x79c0, 0xd881, 0x79be, 0xd87b, 0x79bc, 0xd875, 0x79bb, 0xd86f,
+ 0x79b9, 0xd869, 0x79b7, 0xd863, 0x79b5, 0xd85d, 0x79b3, 0xd857,
+ 0x79b1, 0xd851, 0x79af, 0xd84b, 0x79ad, 0xd845, 0x79ab, 0xd83f,
+ 0x79a9, 0xd839, 0x79a7, 0xd833, 0x79a5, 0xd82d, 0x79a3, 0xd827,
+ 0x79a1, 0xd821, 0x799f, 0xd81b, 0x799d, 0xd815, 0x799b, 0xd80f,
+ 0x7999, 0xd80a, 0x7997, 0xd804, 0x7995, 0xd7fe, 0x7993, 0xd7f8,
+ 0x7992, 0xd7f2, 0x7990, 0xd7ec, 0x798e, 0xd7e6, 0x798c, 0xd7e0,
+ 0x798a, 0xd7da, 0x7988, 0xd7d4, 0x7986, 0xd7ce, 0x7984, 0xd7c8,
+ 0x7982, 0xd7c2, 0x7980, 0xd7bc, 0x797e, 0xd7b6, 0x797c, 0xd7b0,
+ 0x797a, 0xd7aa, 0x7978, 0xd7a4, 0x7976, 0xd79e, 0x7974, 0xd798,
+ 0x7972, 0xd792, 0x7970, 0xd78c, 0x796e, 0xd786, 0x796c, 0xd780,
+ 0x796a, 0xd77a, 0x7968, 0xd774, 0x7966, 0xd76e, 0x7964, 0xd768,
+ 0x7962, 0xd763, 0x7960, 0xd75d, 0x795e, 0xd757, 0x795c, 0xd751,
+ 0x795a, 0xd74b, 0x7958, 0xd745, 0x7956, 0xd73f, 0x7954, 0xd739,
+ 0x7952, 0xd733, 0x7950, 0xd72d, 0x794e, 0xd727, 0x794c, 0xd721,
+ 0x794a, 0xd71b, 0x7948, 0xd715, 0x7946, 0xd70f, 0x7944, 0xd709,
+ 0x7942, 0xd703, 0x7940, 0xd6fd, 0x793e, 0xd6f7, 0x793c, 0xd6f1,
+ 0x793a, 0xd6eb, 0x7938, 0xd6e5, 0x7936, 0xd6e0, 0x7934, 0xd6da,
+ 0x7932, 0xd6d4, 0x7930, 0xd6ce, 0x792e, 0xd6c8, 0x792c, 0xd6c2,
+ 0x792a, 0xd6bc, 0x7928, 0xd6b6, 0x7926, 0xd6b0, 0x7924, 0xd6aa,
+ 0x7922, 0xd6a4, 0x7920, 0xd69e, 0x791e, 0xd698, 0x791c, 0xd692,
+ 0x7919, 0xd68c, 0x7917, 0xd686, 0x7915, 0xd680, 0x7913, 0xd67a,
+ 0x7911, 0xd675, 0x790f, 0xd66f, 0x790d, 0xd669, 0x790b, 0xd663,
+ 0x7909, 0xd65d, 0x7907, 0xd657, 0x7905, 0xd651, 0x7903, 0xd64b,
+ 0x7901, 0xd645, 0x78ff, 0xd63f, 0x78fd, 0xd639, 0x78fb, 0xd633,
+ 0x78f9, 0xd62d, 0x78f7, 0xd627, 0x78f5, 0xd621, 0x78f3, 0xd61b,
+ 0x78f1, 0xd615, 0x78ee, 0xd610, 0x78ec, 0xd60a, 0x78ea, 0xd604,
+ 0x78e8, 0xd5fe, 0x78e6, 0xd5f8, 0x78e4, 0xd5f2, 0x78e2, 0xd5ec,
+ 0x78e0, 0xd5e6, 0x78de, 0xd5e0, 0x78dc, 0xd5da, 0x78da, 0xd5d4,
+ 0x78d8, 0xd5ce, 0x78d6, 0xd5c8, 0x78d4, 0xd5c2, 0x78d2, 0xd5bc,
+ 0x78cf, 0xd5b7, 0x78cd, 0xd5b1, 0x78cb, 0xd5ab, 0x78c9, 0xd5a5,
+ 0x78c7, 0xd59f, 0x78c5, 0xd599, 0x78c3, 0xd593, 0x78c1, 0xd58d,
+ 0x78bf, 0xd587, 0x78bd, 0xd581, 0x78bb, 0xd57b, 0x78b9, 0xd575,
+ 0x78b6, 0xd56f, 0x78b4, 0xd569, 0x78b2, 0xd564, 0x78b0, 0xd55e,
+ 0x78ae, 0xd558, 0x78ac, 0xd552, 0x78aa, 0xd54c, 0x78a8, 0xd546,
+ 0x78a6, 0xd540, 0x78a4, 0xd53a, 0x78a2, 0xd534, 0x789f, 0xd52e,
+ 0x789d, 0xd528, 0x789b, 0xd522, 0x7899, 0xd51c, 0x7897, 0xd517,
+ 0x7895, 0xd511, 0x7893, 0xd50b, 0x7891, 0xd505, 0x788f, 0xd4ff,
+ 0x788c, 0xd4f9, 0x788a, 0xd4f3, 0x7888, 0xd4ed, 0x7886, 0xd4e7,
+ 0x7884, 0xd4e1, 0x7882, 0xd4db, 0x7880, 0xd4d5, 0x787e, 0xd4d0,
+ 0x787c, 0xd4ca, 0x7879, 0xd4c4, 0x7877, 0xd4be, 0x7875, 0xd4b8,
+ 0x7873, 0xd4b2, 0x7871, 0xd4ac, 0x786f, 0xd4a6, 0x786d, 0xd4a0,
+ 0x786b, 0xd49a, 0x7868, 0xd494, 0x7866, 0xd48f, 0x7864, 0xd489,
+ 0x7862, 0xd483, 0x7860, 0xd47d, 0x785e, 0xd477, 0x785c, 0xd471,
+ 0x7859, 0xd46b, 0x7857, 0xd465, 0x7855, 0xd45f, 0x7853, 0xd459,
+ 0x7851, 0xd453, 0x784f, 0xd44e, 0x784d, 0xd448, 0x784a, 0xd442,
+ 0x7848, 0xd43c, 0x7846, 0xd436, 0x7844, 0xd430, 0x7842, 0xd42a,
+ 0x7840, 0xd424, 0x783e, 0xd41e, 0x783b, 0xd418, 0x7839, 0xd412,
+ 0x7837, 0xd40d, 0x7835, 0xd407, 0x7833, 0xd401, 0x7831, 0xd3fb,
+ 0x782e, 0xd3f5, 0x782c, 0xd3ef, 0x782a, 0xd3e9, 0x7828, 0xd3e3,
+ 0x7826, 0xd3dd, 0x7824, 0xd3d7, 0x7821, 0xd3d2, 0x781f, 0xd3cc,
+ 0x781d, 0xd3c6, 0x781b, 0xd3c0, 0x7819, 0xd3ba, 0x7817, 0xd3b4,
+ 0x7814, 0xd3ae, 0x7812, 0xd3a8, 0x7810, 0xd3a2, 0x780e, 0xd39d,
+ 0x780c, 0xd397, 0x780a, 0xd391, 0x7807, 0xd38b, 0x7805, 0xd385,
+ 0x7803, 0xd37f, 0x7801, 0xd379, 0x77ff, 0xd373, 0x77fc, 0xd36d,
+ 0x77fa, 0xd368, 0x77f8, 0xd362, 0x77f6, 0xd35c, 0x77f4, 0xd356,
+ 0x77f1, 0xd350, 0x77ef, 0xd34a, 0x77ed, 0xd344, 0x77eb, 0xd33e,
+ 0x77e9, 0xd338, 0x77e6, 0xd333, 0x77e4, 0xd32d, 0x77e2, 0xd327,
+ 0x77e0, 0xd321, 0x77de, 0xd31b, 0x77db, 0xd315, 0x77d9, 0xd30f,
+ 0x77d7, 0xd309, 0x77d5, 0xd303, 0x77d3, 0xd2fe, 0x77d0, 0xd2f8,
+ 0x77ce, 0xd2f2, 0x77cc, 0xd2ec, 0x77ca, 0xd2e6, 0x77c8, 0xd2e0,
+ 0x77c5, 0xd2da, 0x77c3, 0xd2d4, 0x77c1, 0xd2cf, 0x77bf, 0xd2c9,
+ 0x77bc, 0xd2c3, 0x77ba, 0xd2bd, 0x77b8, 0xd2b7, 0x77b6, 0xd2b1,
+ 0x77b4, 0xd2ab, 0x77b1, 0xd2a5, 0x77af, 0xd2a0, 0x77ad, 0xd29a,
+ 0x77ab, 0xd294, 0x77a8, 0xd28e, 0x77a6, 0xd288, 0x77a4, 0xd282,
+ 0x77a2, 0xd27c, 0x77a0, 0xd276, 0x779d, 0xd271, 0x779b, 0xd26b,
+ 0x7799, 0xd265, 0x7797, 0xd25f, 0x7794, 0xd259, 0x7792, 0xd253,
+ 0x7790, 0xd24d, 0x778e, 0xd247, 0x778b, 0xd242, 0x7789, 0xd23c,
+ 0x7787, 0xd236, 0x7785, 0xd230, 0x7782, 0xd22a, 0x7780, 0xd224,
+ 0x777e, 0xd21e, 0x777c, 0xd219, 0x7779, 0xd213, 0x7777, 0xd20d,
+ 0x7775, 0xd207, 0x7773, 0xd201, 0x7770, 0xd1fb, 0x776e, 0xd1f5,
+ 0x776c, 0xd1ef, 0x776a, 0xd1ea, 0x7767, 0xd1e4, 0x7765, 0xd1de,
+ 0x7763, 0xd1d8, 0x7760, 0xd1d2, 0x775e, 0xd1cc, 0x775c, 0xd1c6,
+ 0x775a, 0xd1c1, 0x7757, 0xd1bb, 0x7755, 0xd1b5, 0x7753, 0xd1af,
+ 0x7751, 0xd1a9, 0x774e, 0xd1a3, 0x774c, 0xd19d, 0x774a, 0xd198,
+ 0x7747, 0xd192, 0x7745, 0xd18c, 0x7743, 0xd186, 0x7741, 0xd180,
+ 0x773e, 0xd17a, 0x773c, 0xd174, 0x773a, 0xd16f, 0x7738, 0xd169,
+ 0x7735, 0xd163, 0x7733, 0xd15d, 0x7731, 0xd157, 0x772e, 0xd151,
+ 0x772c, 0xd14b, 0x772a, 0xd146, 0x7727, 0xd140, 0x7725, 0xd13a,
+ 0x7723, 0xd134, 0x7721, 0xd12e, 0x771e, 0xd128, 0x771c, 0xd123,
+ 0x771a, 0xd11d, 0x7717, 0xd117, 0x7715, 0xd111, 0x7713, 0xd10b,
+ 0x7710, 0xd105, 0x770e, 0xd0ff, 0x770c, 0xd0fa, 0x770a, 0xd0f4,
+ 0x7707, 0xd0ee, 0x7705, 0xd0e8, 0x7703, 0xd0e2, 0x7700, 0xd0dc,
+ 0x76fe, 0xd0d7, 0x76fc, 0xd0d1, 0x76f9, 0xd0cb, 0x76f7, 0xd0c5,
+ 0x76f5, 0xd0bf, 0x76f2, 0xd0b9, 0x76f0, 0xd0b4, 0x76ee, 0xd0ae,
+ 0x76eb, 0xd0a8, 0x76e9, 0xd0a2, 0x76e7, 0xd09c, 0x76e4, 0xd096,
+ 0x76e2, 0xd091, 0x76e0, 0xd08b, 0x76dd, 0xd085, 0x76db, 0xd07f,
+ 0x76d9, 0xd079, 0x76d6, 0xd073, 0x76d4, 0xd06e, 0x76d2, 0xd068,
+ 0x76cf, 0xd062, 0x76cd, 0xd05c, 0x76cb, 0xd056, 0x76c8, 0xd050,
+ 0x76c6, 0xd04b, 0x76c4, 0xd045, 0x76c1, 0xd03f, 0x76bf, 0xd039,
+ 0x76bd, 0xd033, 0x76ba, 0xd02d, 0x76b8, 0xd028, 0x76b6, 0xd022,
+ 0x76b3, 0xd01c, 0x76b1, 0xd016, 0x76af, 0xd010, 0x76ac, 0xd00a,
+ 0x76aa, 0xd005, 0x76a8, 0xcfff, 0x76a5, 0xcff9, 0x76a3, 0xcff3,
+ 0x76a0, 0xcfed, 0x769e, 0xcfe7, 0x769c, 0xcfe2, 0x7699, 0xcfdc,
+ 0x7697, 0xcfd6, 0x7695, 0xcfd0, 0x7692, 0xcfca, 0x7690, 0xcfc5,
+ 0x768e, 0xcfbf, 0x768b, 0xcfb9, 0x7689, 0xcfb3, 0x7686, 0xcfad,
+ 0x7684, 0xcfa7, 0x7682, 0xcfa2, 0x767f, 0xcf9c, 0x767d, 0xcf96,
+ 0x767b, 0xcf90, 0x7678, 0xcf8a, 0x7676, 0xcf85, 0x7673, 0xcf7f,
+ 0x7671, 0xcf79, 0x766f, 0xcf73, 0x766c, 0xcf6d, 0x766a, 0xcf67,
+ 0x7668, 0xcf62, 0x7665, 0xcf5c, 0x7663, 0xcf56, 0x7660, 0xcf50,
+ 0x765e, 0xcf4a, 0x765c, 0xcf45, 0x7659, 0xcf3f, 0x7657, 0xcf39,
+ 0x7654, 0xcf33, 0x7652, 0xcf2d, 0x7650, 0xcf28, 0x764d, 0xcf22,
+ 0x764b, 0xcf1c, 0x7648, 0xcf16, 0x7646, 0xcf10, 0x7644, 0xcf0b,
+ 0x7641, 0xcf05, 0x763f, 0xceff, 0x763c, 0xcef9, 0x763a, 0xcef3,
+ 0x7638, 0xceee, 0x7635, 0xcee8, 0x7633, 0xcee2, 0x7630, 0xcedc,
+ 0x762e, 0xced6, 0x762b, 0xced1, 0x7629, 0xcecb, 0x7627, 0xcec5,
+ 0x7624, 0xcebf, 0x7622, 0xceb9, 0x761f, 0xceb4, 0x761d, 0xceae,
+ 0x761b, 0xcea8, 0x7618, 0xcea2, 0x7616, 0xce9c, 0x7613, 0xce97,
+ 0x7611, 0xce91, 0x760e, 0xce8b, 0x760c, 0xce85, 0x760a, 0xce7f,
+ 0x7607, 0xce7a, 0x7605, 0xce74, 0x7602, 0xce6e, 0x7600, 0xce68,
+ 0x75fd, 0xce62, 0x75fb, 0xce5d, 0x75f9, 0xce57, 0x75f6, 0xce51,
+ 0x75f4, 0xce4b, 0x75f1, 0xce45, 0x75ef, 0xce40, 0x75ec, 0xce3a,
+ 0x75ea, 0xce34, 0x75e7, 0xce2e, 0x75e5, 0xce28, 0x75e3, 0xce23,
+ 0x75e0, 0xce1d, 0x75de, 0xce17, 0x75db, 0xce11, 0x75d9, 0xce0c,
+ 0x75d6, 0xce06, 0x75d4, 0xce00, 0x75d1, 0xcdfa, 0x75cf, 0xcdf4,
+ 0x75cc, 0xcdef, 0x75ca, 0xcde9, 0x75c8, 0xcde3, 0x75c5, 0xcddd,
+ 0x75c3, 0xcdd8, 0x75c0, 0xcdd2, 0x75be, 0xcdcc, 0x75bb, 0xcdc6,
+ 0x75b9, 0xcdc0, 0x75b6, 0xcdbb, 0x75b4, 0xcdb5, 0x75b1, 0xcdaf,
+ 0x75af, 0xcda9, 0x75ac, 0xcda3, 0x75aa, 0xcd9e, 0x75a7, 0xcd98,
+ 0x75a5, 0xcd92, 0x75a3, 0xcd8c, 0x75a0, 0xcd87, 0x759e, 0xcd81,
+ 0x759b, 0xcd7b, 0x7599, 0xcd75, 0x7596, 0xcd70, 0x7594, 0xcd6a,
+ 0x7591, 0xcd64, 0x758f, 0xcd5e, 0x758c, 0xcd58, 0x758a, 0xcd53,
+ 0x7587, 0xcd4d, 0x7585, 0xcd47, 0x7582, 0xcd41, 0x7580, 0xcd3c,
+ 0x757d, 0xcd36, 0x757b, 0xcd30, 0x7578, 0xcd2a, 0x7576, 0xcd25,
+ 0x7573, 0xcd1f, 0x7571, 0xcd19, 0x756e, 0xcd13, 0x756c, 0xcd0d,
+ 0x7569, 0xcd08, 0x7567, 0xcd02, 0x7564, 0xccfc, 0x7562, 0xccf6,
+ 0x755f, 0xccf1, 0x755d, 0xcceb, 0x755a, 0xcce5, 0x7558, 0xccdf,
+ 0x7555, 0xccda, 0x7553, 0xccd4, 0x7550, 0xccce, 0x754e, 0xccc8,
+ 0x754b, 0xccc3, 0x7549, 0xccbd, 0x7546, 0xccb7, 0x7544, 0xccb1,
+ 0x7541, 0xccac, 0x753f, 0xcca6, 0x753c, 0xcca0, 0x753a, 0xcc9a,
+ 0x7537, 0xcc95, 0x7535, 0xcc8f, 0x7532, 0xcc89, 0x752f, 0xcc83,
+ 0x752d, 0xcc7e, 0x752a, 0xcc78, 0x7528, 0xcc72, 0x7525, 0xcc6c,
+ 0x7523, 0xcc67, 0x7520, 0xcc61, 0x751e, 0xcc5b, 0x751b, 0xcc55,
+ 0x7519, 0xcc50, 0x7516, 0xcc4a, 0x7514, 0xcc44, 0x7511, 0xcc3e,
+ 0x750f, 0xcc39, 0x750c, 0xcc33, 0x7509, 0xcc2d, 0x7507, 0xcc27,
+ 0x7504, 0xcc22, 0x7502, 0xcc1c, 0x74ff, 0xcc16, 0x74fd, 0xcc10,
+ 0x74fa, 0xcc0b, 0x74f8, 0xcc05, 0x74f5, 0xcbff, 0x74f2, 0xcbf9,
+ 0x74f0, 0xcbf4, 0x74ed, 0xcbee, 0x74eb, 0xcbe8, 0x74e8, 0xcbe2,
+ 0x74e6, 0xcbdd, 0x74e3, 0xcbd7, 0x74e1, 0xcbd1, 0x74de, 0xcbcb,
+ 0x74db, 0xcbc6, 0x74d9, 0xcbc0, 0x74d6, 0xcbba, 0x74d4, 0xcbb5,
+ 0x74d1, 0xcbaf, 0x74cf, 0xcba9, 0x74cc, 0xcba3, 0x74c9, 0xcb9e,
+ 0x74c7, 0xcb98, 0x74c4, 0xcb92, 0x74c2, 0xcb8c, 0x74bf, 0xcb87,
+ 0x74bd, 0xcb81, 0x74ba, 0xcb7b, 0x74b7, 0xcb75, 0x74b5, 0xcb70,
+ 0x74b2, 0xcb6a, 0x74b0, 0xcb64, 0x74ad, 0xcb5f, 0x74ab, 0xcb59,
+ 0x74a8, 0xcb53, 0x74a5, 0xcb4d, 0x74a3, 0xcb48, 0x74a0, 0xcb42,
+ 0x749e, 0xcb3c, 0x749b, 0xcb36, 0x7498, 0xcb31, 0x7496, 0xcb2b,
+ 0x7493, 0xcb25, 0x7491, 0xcb20, 0x748e, 0xcb1a, 0x748b, 0xcb14,
+ 0x7489, 0xcb0e, 0x7486, 0xcb09, 0x7484, 0xcb03, 0x7481, 0xcafd,
+ 0x747e, 0xcaf8, 0x747c, 0xcaf2, 0x7479, 0xcaec, 0x7477, 0xcae6,
+ 0x7474, 0xcae1, 0x7471, 0xcadb, 0x746f, 0xcad5, 0x746c, 0xcad0,
+ 0x746a, 0xcaca, 0x7467, 0xcac4, 0x7464, 0xcabe, 0x7462, 0xcab9,
+ 0x745f, 0xcab3, 0x745c, 0xcaad, 0x745a, 0xcaa8, 0x7457, 0xcaa2,
+ 0x7455, 0xca9c, 0x7452, 0xca96, 0x744f, 0xca91, 0x744d, 0xca8b,
+ 0x744a, 0xca85, 0x7448, 0xca80, 0x7445, 0xca7a, 0x7442, 0xca74,
+ 0x7440, 0xca6e, 0x743d, 0xca69, 0x743a, 0xca63, 0x7438, 0xca5d,
+ 0x7435, 0xca58, 0x7432, 0xca52, 0x7430, 0xca4c, 0x742d, 0xca46,
+ 0x742b, 0xca41, 0x7428, 0xca3b, 0x7425, 0xca35, 0x7423, 0xca30,
+ 0x7420, 0xca2a, 0x741d, 0xca24, 0x741b, 0xca1f, 0x7418, 0xca19,
+ 0x7415, 0xca13, 0x7413, 0xca0d, 0x7410, 0xca08, 0x740d, 0xca02,
+ 0x740b, 0xc9fc, 0x7408, 0xc9f7, 0x7406, 0xc9f1, 0x7403, 0xc9eb,
+ 0x7400, 0xc9e6, 0x73fe, 0xc9e0, 0x73fb, 0xc9da, 0x73f8, 0xc9d5,
+ 0x73f6, 0xc9cf, 0x73f3, 0xc9c9, 0x73f0, 0xc9c3, 0x73ee, 0xc9be,
+ 0x73eb, 0xc9b8, 0x73e8, 0xc9b2, 0x73e6, 0xc9ad, 0x73e3, 0xc9a7,
+ 0x73e0, 0xc9a1, 0x73de, 0xc99c, 0x73db, 0xc996, 0x73d8, 0xc990,
+ 0x73d6, 0xc98b, 0x73d3, 0xc985, 0x73d0, 0xc97f, 0x73ce, 0xc97a,
+ 0x73cb, 0xc974, 0x73c8, 0xc96e, 0x73c6, 0xc968, 0x73c3, 0xc963,
+ 0x73c0, 0xc95d, 0x73bd, 0xc957, 0x73bb, 0xc952, 0x73b8, 0xc94c,
+ 0x73b5, 0xc946, 0x73b3, 0xc941, 0x73b0, 0xc93b, 0x73ad, 0xc935,
+ 0x73ab, 0xc930, 0x73a8, 0xc92a, 0x73a5, 0xc924, 0x73a3, 0xc91f,
+ 0x73a0, 0xc919, 0x739d, 0xc913, 0x739b, 0xc90e, 0x7398, 0xc908,
+ 0x7395, 0xc902, 0x7392, 0xc8fd, 0x7390, 0xc8f7, 0x738d, 0xc8f1,
+ 0x738a, 0xc8ec, 0x7388, 0xc8e6, 0x7385, 0xc8e0, 0x7382, 0xc8db,
+ 0x737f, 0xc8d5, 0x737d, 0xc8cf, 0x737a, 0xc8ca, 0x7377, 0xc8c4,
+ 0x7375, 0xc8be, 0x7372, 0xc8b9, 0x736f, 0xc8b3, 0x736c, 0xc8ad,
+ 0x736a, 0xc8a8, 0x7367, 0xc8a2, 0x7364, 0xc89c, 0x7362, 0xc897,
+ 0x735f, 0xc891, 0x735c, 0xc88b, 0x7359, 0xc886, 0x7357, 0xc880,
+ 0x7354, 0xc87a, 0x7351, 0xc875, 0x734f, 0xc86f, 0x734c, 0xc869,
+ 0x7349, 0xc864, 0x7346, 0xc85e, 0x7344, 0xc858, 0x7341, 0xc853,
+ 0x733e, 0xc84d, 0x733b, 0xc847, 0x7339, 0xc842, 0x7336, 0xc83c,
+ 0x7333, 0xc836, 0x7330, 0xc831, 0x732e, 0xc82b, 0x732b, 0xc825,
+ 0x7328, 0xc820, 0x7326, 0xc81a, 0x7323, 0xc814, 0x7320, 0xc80f,
+ 0x731d, 0xc809, 0x731b, 0xc803, 0x7318, 0xc7fe, 0x7315, 0xc7f8,
+ 0x7312, 0xc7f3, 0x7310, 0xc7ed, 0x730d, 0xc7e7, 0x730a, 0xc7e2,
+ 0x7307, 0xc7dc, 0x7305, 0xc7d6, 0x7302, 0xc7d1, 0x72ff, 0xc7cb,
+ 0x72fc, 0xc7c5, 0x72f9, 0xc7c0, 0x72f7, 0xc7ba, 0x72f4, 0xc7b4,
+ 0x72f1, 0xc7af, 0x72ee, 0xc7a9, 0x72ec, 0xc7a3, 0x72e9, 0xc79e,
+ 0x72e6, 0xc798, 0x72e3, 0xc793, 0x72e1, 0xc78d, 0x72de, 0xc787,
+ 0x72db, 0xc782, 0x72d8, 0xc77c, 0x72d5, 0xc776, 0x72d3, 0xc771,
+ 0x72d0, 0xc76b, 0x72cd, 0xc765, 0x72ca, 0xc760, 0x72c8, 0xc75a,
+ 0x72c5, 0xc755, 0x72c2, 0xc74f, 0x72bf, 0xc749, 0x72bc, 0xc744,
+ 0x72ba, 0xc73e, 0x72b7, 0xc738, 0x72b4, 0xc733, 0x72b1, 0xc72d,
+ 0x72af, 0xc728, 0x72ac, 0xc722, 0x72a9, 0xc71c, 0x72a6, 0xc717,
+ 0x72a3, 0xc711, 0x72a1, 0xc70b, 0x729e, 0xc706, 0x729b, 0xc700,
+ 0x7298, 0xc6fa, 0x7295, 0xc6f5, 0x7293, 0xc6ef, 0x7290, 0xc6ea,
+ 0x728d, 0xc6e4, 0x728a, 0xc6de, 0x7287, 0xc6d9, 0x7285, 0xc6d3,
+ 0x7282, 0xc6ce, 0x727f, 0xc6c8, 0x727c, 0xc6c2, 0x7279, 0xc6bd,
+ 0x7276, 0xc6b7, 0x7274, 0xc6b1, 0x7271, 0xc6ac, 0x726e, 0xc6a6,
+ 0x726b, 0xc6a1, 0x7268, 0xc69b, 0x7266, 0xc695, 0x7263, 0xc690,
+ 0x7260, 0xc68a, 0x725d, 0xc684, 0x725a, 0xc67f, 0x7257, 0xc679,
+ 0x7255, 0xc674, 0x7252, 0xc66e, 0x724f, 0xc668, 0x724c, 0xc663,
+ 0x7249, 0xc65d, 0x7247, 0xc658, 0x7244, 0xc652, 0x7241, 0xc64c,
+ 0x723e, 0xc647, 0x723b, 0xc641, 0x7238, 0xc63c, 0x7236, 0xc636,
+ 0x7233, 0xc630, 0x7230, 0xc62b, 0x722d, 0xc625, 0x722a, 0xc620,
+ 0x7227, 0xc61a, 0x7224, 0xc614, 0x7222, 0xc60f, 0x721f, 0xc609,
+ 0x721c, 0xc603, 0x7219, 0xc5fe, 0x7216, 0xc5f8, 0x7213, 0xc5f3,
+ 0x7211, 0xc5ed, 0x720e, 0xc5e7, 0x720b, 0xc5e2, 0x7208, 0xc5dc,
+ 0x7205, 0xc5d7, 0x7202, 0xc5d1, 0x71ff, 0xc5cc, 0x71fd, 0xc5c6,
+ 0x71fa, 0xc5c0, 0x71f7, 0xc5bb, 0x71f4, 0xc5b5, 0x71f1, 0xc5b0,
+ 0x71ee, 0xc5aa, 0x71eb, 0xc5a4, 0x71e9, 0xc59f, 0x71e6, 0xc599,
+ 0x71e3, 0xc594, 0x71e0, 0xc58e, 0x71dd, 0xc588, 0x71da, 0xc583,
+ 0x71d7, 0xc57d, 0x71d4, 0xc578, 0x71d2, 0xc572, 0x71cf, 0xc56c,
+ 0x71cc, 0xc567, 0x71c9, 0xc561, 0x71c6, 0xc55c, 0x71c3, 0xc556,
+ 0x71c0, 0xc551, 0x71bd, 0xc54b, 0x71bb, 0xc545, 0x71b8, 0xc540,
+ 0x71b5, 0xc53a, 0x71b2, 0xc535, 0x71af, 0xc52f, 0x71ac, 0xc529,
+ 0x71a9, 0xc524, 0x71a6, 0xc51e, 0x71a3, 0xc519, 0x71a1, 0xc513,
+ 0x719e, 0xc50e, 0x719b, 0xc508, 0x7198, 0xc502, 0x7195, 0xc4fd,
+ 0x7192, 0xc4f7, 0x718f, 0xc4f2, 0x718c, 0xc4ec, 0x7189, 0xc4e7,
+ 0x7186, 0xc4e1, 0x7184, 0xc4db, 0x7181, 0xc4d6, 0x717e, 0xc4d0,
+ 0x717b, 0xc4cb, 0x7178, 0xc4c5, 0x7175, 0xc4c0, 0x7172, 0xc4ba,
+ 0x716f, 0xc4b4, 0x716c, 0xc4af, 0x7169, 0xc4a9, 0x7167, 0xc4a4,
+ 0x7164, 0xc49e, 0x7161, 0xc499, 0x715e, 0xc493, 0x715b, 0xc48d,
+ 0x7158, 0xc488, 0x7155, 0xc482, 0x7152, 0xc47d, 0x714f, 0xc477,
+ 0x714c, 0xc472, 0x7149, 0xc46c, 0x7146, 0xc467, 0x7143, 0xc461,
+ 0x7141, 0xc45b, 0x713e, 0xc456, 0x713b, 0xc450, 0x7138, 0xc44b,
+ 0x7135, 0xc445, 0x7132, 0xc440, 0x712f, 0xc43a, 0x712c, 0xc434,
+ 0x7129, 0xc42f, 0x7126, 0xc429, 0x7123, 0xc424, 0x7120, 0xc41e,
+ 0x711d, 0xc419, 0x711a, 0xc413, 0x7117, 0xc40e, 0x7114, 0xc408,
+ 0x7112, 0xc403, 0x710f, 0xc3fd, 0x710c, 0xc3f7, 0x7109, 0xc3f2,
+ 0x7106, 0xc3ec, 0x7103, 0xc3e7, 0x7100, 0xc3e1, 0x70fd, 0xc3dc,
+ 0x70fa, 0xc3d6, 0x70f7, 0xc3d1, 0x70f4, 0xc3cb, 0x70f1, 0xc3c5,
+ 0x70ee, 0xc3c0, 0x70eb, 0xc3ba, 0x70e8, 0xc3b5, 0x70e5, 0xc3af,
+ 0x70e2, 0xc3aa, 0x70df, 0xc3a4, 0x70dc, 0xc39f, 0x70d9, 0xc399,
+ 0x70d6, 0xc394, 0x70d3, 0xc38e, 0x70d1, 0xc389, 0x70ce, 0xc383,
+ 0x70cb, 0xc37d, 0x70c8, 0xc378, 0x70c5, 0xc372, 0x70c2, 0xc36d,
+ 0x70bf, 0xc367, 0x70bc, 0xc362, 0x70b9, 0xc35c, 0x70b6, 0xc357,
+ 0x70b3, 0xc351, 0x70b0, 0xc34c, 0x70ad, 0xc346, 0x70aa, 0xc341,
+ 0x70a7, 0xc33b, 0x70a4, 0xc336, 0x70a1, 0xc330, 0x709e, 0xc32a,
+ 0x709b, 0xc325, 0x7098, 0xc31f, 0x7095, 0xc31a, 0x7092, 0xc314,
+ 0x708f, 0xc30f, 0x708c, 0xc309, 0x7089, 0xc304, 0x7086, 0xc2fe,
+ 0x7083, 0xc2f9, 0x7080, 0xc2f3, 0x707d, 0xc2ee, 0x707a, 0xc2e8,
+ 0x7077, 0xc2e3, 0x7074, 0xc2dd, 0x7071, 0xc2d8, 0x706e, 0xc2d2,
+ 0x706b, 0xc2cd, 0x7068, 0xc2c7, 0x7065, 0xc2c2, 0x7062, 0xc2bc,
+ 0x705f, 0xc2b7, 0x705c, 0xc2b1, 0x7059, 0xc2ab, 0x7056, 0xc2a6,
+ 0x7053, 0xc2a0, 0x7050, 0xc29b, 0x704d, 0xc295, 0x704a, 0xc290,
+ 0x7047, 0xc28a, 0x7044, 0xc285, 0x7041, 0xc27f, 0x703e, 0xc27a,
+ 0x703b, 0xc274, 0x7038, 0xc26f, 0x7035, 0xc269, 0x7032, 0xc264,
+ 0x702f, 0xc25e, 0x702c, 0xc259, 0x7029, 0xc253, 0x7026, 0xc24e,
+ 0x7023, 0xc248, 0x7020, 0xc243, 0x701d, 0xc23d, 0x7019, 0xc238,
+ 0x7016, 0xc232, 0x7013, 0xc22d, 0x7010, 0xc227, 0x700d, 0xc222,
+ 0x700a, 0xc21c, 0x7007, 0xc217, 0x7004, 0xc211, 0x7001, 0xc20c,
+ 0x6ffe, 0xc206, 0x6ffb, 0xc201, 0x6ff8, 0xc1fb, 0x6ff5, 0xc1f6,
+ 0x6ff2, 0xc1f0, 0x6fef, 0xc1eb, 0x6fec, 0xc1e5, 0x6fe9, 0xc1e0,
+ 0x6fe6, 0xc1da, 0x6fe3, 0xc1d5, 0x6fe0, 0xc1cf, 0x6fdd, 0xc1ca,
+ 0x6fda, 0xc1c4, 0x6fd6, 0xc1bf, 0x6fd3, 0xc1b9, 0x6fd0, 0xc1b4,
+ 0x6fcd, 0xc1ae, 0x6fca, 0xc1a9, 0x6fc7, 0xc1a3, 0x6fc4, 0xc19e,
+ 0x6fc1, 0xc198, 0x6fbe, 0xc193, 0x6fbb, 0xc18d, 0x6fb8, 0xc188,
+ 0x6fb5, 0xc183, 0x6fb2, 0xc17d, 0x6faf, 0xc178, 0x6fac, 0xc172,
+ 0x6fa9, 0xc16d, 0x6fa5, 0xc167, 0x6fa2, 0xc162, 0x6f9f, 0xc15c,
+ 0x6f9c, 0xc157, 0x6f99, 0xc151, 0x6f96, 0xc14c, 0x6f93, 0xc146,
+ 0x6f90, 0xc141, 0x6f8d, 0xc13b, 0x6f8a, 0xc136, 0x6f87, 0xc130,
+ 0x6f84, 0xc12b, 0x6f81, 0xc125, 0x6f7d, 0xc120, 0x6f7a, 0xc11a,
+ 0x6f77, 0xc115, 0x6f74, 0xc10f, 0x6f71, 0xc10a, 0x6f6e, 0xc105,
+ 0x6f6b, 0xc0ff, 0x6f68, 0xc0fa, 0x6f65, 0xc0f4, 0x6f62, 0xc0ef,
+ 0x6f5f, 0xc0e9, 0x6f5b, 0xc0e4, 0x6f58, 0xc0de, 0x6f55, 0xc0d9,
+ 0x6f52, 0xc0d3, 0x6f4f, 0xc0ce, 0x6f4c, 0xc0c8, 0x6f49, 0xc0c3,
+ 0x6f46, 0xc0bd, 0x6f43, 0xc0b8, 0x6f3f, 0xc0b3, 0x6f3c, 0xc0ad,
+ 0x6f39, 0xc0a8, 0x6f36, 0xc0a2, 0x6f33, 0xc09d, 0x6f30, 0xc097,
+ 0x6f2d, 0xc092, 0x6f2a, 0xc08c, 0x6f27, 0xc087, 0x6f23, 0xc081,
+ 0x6f20, 0xc07c, 0x6f1d, 0xc077, 0x6f1a, 0xc071, 0x6f17, 0xc06c,
+ 0x6f14, 0xc066, 0x6f11, 0xc061, 0x6f0e, 0xc05b, 0x6f0b, 0xc056,
+ 0x6f07, 0xc050, 0x6f04, 0xc04b, 0x6f01, 0xc045, 0x6efe, 0xc040,
+ 0x6efb, 0xc03b, 0x6ef8, 0xc035, 0x6ef5, 0xc030, 0x6ef1, 0xc02a,
+ 0x6eee, 0xc025, 0x6eeb, 0xc01f, 0x6ee8, 0xc01a, 0x6ee5, 0xc014,
+ 0x6ee2, 0xc00f, 0x6edf, 0xc00a, 0x6edc, 0xc004, 0x6ed8, 0xbfff,
+ 0x6ed5, 0xbff9, 0x6ed2, 0xbff4, 0x6ecf, 0xbfee, 0x6ecc, 0xbfe9,
+ 0x6ec9, 0xbfe3, 0x6ec6, 0xbfde, 0x6ec2, 0xbfd9, 0x6ebf, 0xbfd3,
+ 0x6ebc, 0xbfce, 0x6eb9, 0xbfc8, 0x6eb6, 0xbfc3, 0x6eb3, 0xbfbd,
+ 0x6eaf, 0xbfb8, 0x6eac, 0xbfb3, 0x6ea9, 0xbfad, 0x6ea6, 0xbfa8,
+ 0x6ea3, 0xbfa2, 0x6ea0, 0xbf9d, 0x6e9c, 0xbf97, 0x6e99, 0xbf92,
+ 0x6e96, 0xbf8d, 0x6e93, 0xbf87, 0x6e90, 0xbf82, 0x6e8d, 0xbf7c,
+ 0x6e89, 0xbf77, 0x6e86, 0xbf71, 0x6e83, 0xbf6c, 0x6e80, 0xbf67,
+ 0x6e7d, 0xbf61, 0x6e7a, 0xbf5c, 0x6e76, 0xbf56, 0x6e73, 0xbf51,
+ 0x6e70, 0xbf4b, 0x6e6d, 0xbf46, 0x6e6a, 0xbf41, 0x6e67, 0xbf3b,
+ 0x6e63, 0xbf36, 0x6e60, 0xbf30, 0x6e5d, 0xbf2b, 0x6e5a, 0xbf26,
+ 0x6e57, 0xbf20, 0x6e53, 0xbf1b, 0x6e50, 0xbf15, 0x6e4d, 0xbf10,
+ 0x6e4a, 0xbf0a, 0x6e47, 0xbf05, 0x6e44, 0xbf00, 0x6e40, 0xbefa,
+ 0x6e3d, 0xbef5, 0x6e3a, 0xbeef, 0x6e37, 0xbeea, 0x6e34, 0xbee5,
+ 0x6e30, 0xbedf, 0x6e2d, 0xbeda, 0x6e2a, 0xbed4, 0x6e27, 0xbecf,
+ 0x6e24, 0xbeca, 0x6e20, 0xbec4, 0x6e1d, 0xbebf, 0x6e1a, 0xbeb9,
+ 0x6e17, 0xbeb4, 0x6e14, 0xbeae, 0x6e10, 0xbea9, 0x6e0d, 0xbea4,
+ 0x6e0a, 0xbe9e, 0x6e07, 0xbe99, 0x6e04, 0xbe93, 0x6e00, 0xbe8e,
+ 0x6dfd, 0xbe89, 0x6dfa, 0xbe83, 0x6df7, 0xbe7e, 0x6df3, 0xbe78,
+ 0x6df0, 0xbe73, 0x6ded, 0xbe6e, 0x6dea, 0xbe68, 0x6de7, 0xbe63,
+ 0x6de3, 0xbe5e, 0x6de0, 0xbe58, 0x6ddd, 0xbe53, 0x6dda, 0xbe4d,
+ 0x6dd6, 0xbe48, 0x6dd3, 0xbe43, 0x6dd0, 0xbe3d, 0x6dcd, 0xbe38,
+ 0x6dca, 0xbe32, 0x6dc6, 0xbe2d, 0x6dc3, 0xbe28, 0x6dc0, 0xbe22,
+ 0x6dbd, 0xbe1d, 0x6db9, 0xbe17, 0x6db6, 0xbe12, 0x6db3, 0xbe0d,
+ 0x6db0, 0xbe07, 0x6dac, 0xbe02, 0x6da9, 0xbdfd, 0x6da6, 0xbdf7,
+ 0x6da3, 0xbdf2, 0x6d9f, 0xbdec, 0x6d9c, 0xbde7, 0x6d99, 0xbde2,
+ 0x6d96, 0xbddc, 0x6d92, 0xbdd7, 0x6d8f, 0xbdd1, 0x6d8c, 0xbdcc,
+ 0x6d89, 0xbdc7, 0x6d85, 0xbdc1, 0x6d82, 0xbdbc, 0x6d7f, 0xbdb7,
+ 0x6d7c, 0xbdb1, 0x6d78, 0xbdac, 0x6d75, 0xbda6, 0x6d72, 0xbda1,
+ 0x6d6f, 0xbd9c, 0x6d6b, 0xbd96, 0x6d68, 0xbd91, 0x6d65, 0xbd8c,
+ 0x6d62, 0xbd86, 0x6d5e, 0xbd81, 0x6d5b, 0xbd7c, 0x6d58, 0xbd76,
+ 0x6d55, 0xbd71, 0x6d51, 0xbd6b, 0x6d4e, 0xbd66, 0x6d4b, 0xbd61,
+ 0x6d48, 0xbd5b, 0x6d44, 0xbd56, 0x6d41, 0xbd51, 0x6d3e, 0xbd4b,
+ 0x6d3a, 0xbd46, 0x6d37, 0xbd40, 0x6d34, 0xbd3b, 0x6d31, 0xbd36,
+ 0x6d2d, 0xbd30, 0x6d2a, 0xbd2b, 0x6d27, 0xbd26, 0x6d23, 0xbd20,
+ 0x6d20, 0xbd1b, 0x6d1d, 0xbd16, 0x6d1a, 0xbd10, 0x6d16, 0xbd0b,
+ 0x6d13, 0xbd06, 0x6d10, 0xbd00, 0x6d0c, 0xbcfb, 0x6d09, 0xbcf5,
+ 0x6d06, 0xbcf0, 0x6d03, 0xbceb, 0x6cff, 0xbce5, 0x6cfc, 0xbce0,
+ 0x6cf9, 0xbcdb, 0x6cf5, 0xbcd5, 0x6cf2, 0xbcd0, 0x6cef, 0xbccb,
+ 0x6cec, 0xbcc5, 0x6ce8, 0xbcc0, 0x6ce5, 0xbcbb, 0x6ce2, 0xbcb5,
+ 0x6cde, 0xbcb0, 0x6cdb, 0xbcab, 0x6cd8, 0xbca5, 0x6cd4, 0xbca0,
+ 0x6cd1, 0xbc9b, 0x6cce, 0xbc95, 0x6cca, 0xbc90, 0x6cc7, 0xbc8b,
+ 0x6cc4, 0xbc85, 0x6cc1, 0xbc80, 0x6cbd, 0xbc7b, 0x6cba, 0xbc75,
+ 0x6cb7, 0xbc70, 0x6cb3, 0xbc6b, 0x6cb0, 0xbc65, 0x6cad, 0xbc60,
+ 0x6ca9, 0xbc5b, 0x6ca6, 0xbc55, 0x6ca3, 0xbc50, 0x6c9f, 0xbc4b,
+ 0x6c9c, 0xbc45, 0x6c99, 0xbc40, 0x6c95, 0xbc3b, 0x6c92, 0xbc35,
+ 0x6c8f, 0xbc30, 0x6c8b, 0xbc2b, 0x6c88, 0xbc25, 0x6c85, 0xbc20,
+ 0x6c81, 0xbc1b, 0x6c7e, 0xbc15, 0x6c7b, 0xbc10, 0x6c77, 0xbc0b,
+ 0x6c74, 0xbc05, 0x6c71, 0xbc00, 0x6c6d, 0xbbfb, 0x6c6a, 0xbbf5,
+ 0x6c67, 0xbbf0, 0x6c63, 0xbbeb, 0x6c60, 0xbbe5, 0x6c5d, 0xbbe0,
+ 0x6c59, 0xbbdb, 0x6c56, 0xbbd5, 0x6c53, 0xbbd0, 0x6c4f, 0xbbcb,
+ 0x6c4c, 0xbbc5, 0x6c49, 0xbbc0, 0x6c45, 0xbbbb, 0x6c42, 0xbbb5,
+ 0x6c3f, 0xbbb0, 0x6c3b, 0xbbab, 0x6c38, 0xbba6, 0x6c34, 0xbba0,
+ 0x6c31, 0xbb9b, 0x6c2e, 0xbb96, 0x6c2a, 0xbb90, 0x6c27, 0xbb8b,
+ 0x6c24, 0xbb86, 0x6c20, 0xbb80, 0x6c1d, 0xbb7b, 0x6c1a, 0xbb76,
+ 0x6c16, 0xbb70, 0x6c13, 0xbb6b, 0x6c0f, 0xbb66, 0x6c0c, 0xbb61,
+ 0x6c09, 0xbb5b, 0x6c05, 0xbb56, 0x6c02, 0xbb51, 0x6bff, 0xbb4b,
+ 0x6bfb, 0xbb46, 0x6bf8, 0xbb41, 0x6bf5, 0xbb3b, 0x6bf1, 0xbb36,
+ 0x6bee, 0xbb31, 0x6bea, 0xbb2c, 0x6be7, 0xbb26, 0x6be4, 0xbb21,
+ 0x6be0, 0xbb1c, 0x6bdd, 0xbb16, 0x6bd9, 0xbb11, 0x6bd6, 0xbb0c,
+ 0x6bd3, 0xbb06, 0x6bcf, 0xbb01, 0x6bcc, 0xbafc, 0x6bc9, 0xbaf7,
+ 0x6bc5, 0xbaf1, 0x6bc2, 0xbaec, 0x6bbe, 0xbae7, 0x6bbb, 0xbae1,
+ 0x6bb8, 0xbadc, 0x6bb4, 0xbad7, 0x6bb1, 0xbad2, 0x6bad, 0xbacc,
+ 0x6baa, 0xbac7, 0x6ba7, 0xbac2, 0x6ba3, 0xbabc, 0x6ba0, 0xbab7,
+ 0x6b9c, 0xbab2, 0x6b99, 0xbaad, 0x6b96, 0xbaa7, 0x6b92, 0xbaa2,
+ 0x6b8f, 0xba9d, 0x6b8b, 0xba97, 0x6b88, 0xba92, 0x6b85, 0xba8d,
+ 0x6b81, 0xba88, 0x6b7e, 0xba82, 0x6b7a, 0xba7d, 0x6b77, 0xba78,
+ 0x6b73, 0xba73, 0x6b70, 0xba6d, 0x6b6d, 0xba68, 0x6b69, 0xba63,
+ 0x6b66, 0xba5d, 0x6b62, 0xba58, 0x6b5f, 0xba53, 0x6b5c, 0xba4e,
+ 0x6b58, 0xba48, 0x6b55, 0xba43, 0x6b51, 0xba3e, 0x6b4e, 0xba39,
+ 0x6b4a, 0xba33, 0x6b47, 0xba2e, 0x6b44, 0xba29, 0x6b40, 0xba23,
+ 0x6b3d, 0xba1e, 0x6b39, 0xba19, 0x6b36, 0xba14, 0x6b32, 0xba0e,
+ 0x6b2f, 0xba09, 0x6b2c, 0xba04, 0x6b28, 0xb9ff, 0x6b25, 0xb9f9,
+ 0x6b21, 0xb9f4, 0x6b1e, 0xb9ef, 0x6b1a, 0xb9ea, 0x6b17, 0xb9e4,
+ 0x6b13, 0xb9df, 0x6b10, 0xb9da, 0x6b0d, 0xb9d5, 0x6b09, 0xb9cf,
+ 0x6b06, 0xb9ca, 0x6b02, 0xb9c5, 0x6aff, 0xb9c0, 0x6afb, 0xb9ba,
+ 0x6af8, 0xb9b5, 0x6af4, 0xb9b0, 0x6af1, 0xb9ab, 0x6aee, 0xb9a5,
+ 0x6aea, 0xb9a0, 0x6ae7, 0xb99b, 0x6ae3, 0xb996, 0x6ae0, 0xb990,
+ 0x6adc, 0xb98b, 0x6ad9, 0xb986, 0x6ad5, 0xb981, 0x6ad2, 0xb97b,
+ 0x6ace, 0xb976, 0x6acb, 0xb971, 0x6ac8, 0xb96c, 0x6ac4, 0xb966,
+ 0x6ac1, 0xb961, 0x6abd, 0xb95c, 0x6aba, 0xb957, 0x6ab6, 0xb951,
+ 0x6ab3, 0xb94c, 0x6aaf, 0xb947, 0x6aac, 0xb942, 0x6aa8, 0xb93c,
+ 0x6aa5, 0xb937, 0x6aa1, 0xb932, 0x6a9e, 0xb92d, 0x6a9a, 0xb928,
+ 0x6a97, 0xb922, 0x6a93, 0xb91d, 0x6a90, 0xb918, 0x6a8c, 0xb913,
+ 0x6a89, 0xb90d, 0x6a86, 0xb908, 0x6a82, 0xb903, 0x6a7f, 0xb8fe,
+ 0x6a7b, 0xb8f8, 0x6a78, 0xb8f3, 0x6a74, 0xb8ee, 0x6a71, 0xb8e9,
+ 0x6a6d, 0xb8e4, 0x6a6a, 0xb8de, 0x6a66, 0xb8d9, 0x6a63, 0xb8d4,
+ 0x6a5f, 0xb8cf, 0x6a5c, 0xb8c9, 0x6a58, 0xb8c4, 0x6a55, 0xb8bf,
+ 0x6a51, 0xb8ba, 0x6a4e, 0xb8b5, 0x6a4a, 0xb8af, 0x6a47, 0xb8aa,
+ 0x6a43, 0xb8a5, 0x6a40, 0xb8a0, 0x6a3c, 0xb89b, 0x6a39, 0xb895,
+ 0x6a35, 0xb890, 0x6a32, 0xb88b, 0x6a2e, 0xb886, 0x6a2b, 0xb880,
+ 0x6a27, 0xb87b, 0x6a24, 0xb876, 0x6a20, 0xb871, 0x6a1d, 0xb86c,
+ 0x6a19, 0xb866, 0x6a16, 0xb861, 0x6a12, 0xb85c, 0x6a0e, 0xb857,
+ 0x6a0b, 0xb852, 0x6a07, 0xb84c, 0x6a04, 0xb847, 0x6a00, 0xb842,
+ 0x69fd, 0xb83d, 0x69f9, 0xb838, 0x69f6, 0xb832, 0x69f2, 0xb82d,
+ 0x69ef, 0xb828, 0x69eb, 0xb823, 0x69e8, 0xb81e, 0x69e4, 0xb818,
+ 0x69e1, 0xb813, 0x69dd, 0xb80e, 0x69da, 0xb809, 0x69d6, 0xb804,
+ 0x69d3, 0xb7fe, 0x69cf, 0xb7f9, 0x69cb, 0xb7f4, 0x69c8, 0xb7ef,
+ 0x69c4, 0xb7ea, 0x69c1, 0xb7e4, 0x69bd, 0xb7df, 0x69ba, 0xb7da,
+ 0x69b6, 0xb7d5, 0x69b3, 0xb7d0, 0x69af, 0xb7ca, 0x69ac, 0xb7c5,
+ 0x69a8, 0xb7c0, 0x69a5, 0xb7bb, 0x69a1, 0xb7b6, 0x699d, 0xb7b1,
+ 0x699a, 0xb7ab, 0x6996, 0xb7a6, 0x6993, 0xb7a1, 0x698f, 0xb79c,
+ 0x698c, 0xb797, 0x6988, 0xb791, 0x6985, 0xb78c, 0x6981, 0xb787,
+ 0x697d, 0xb782, 0x697a, 0xb77d, 0x6976, 0xb778, 0x6973, 0xb772,
+ 0x696f, 0xb76d, 0x696c, 0xb768, 0x6968, 0xb763, 0x6964, 0xb75e,
+ 0x6961, 0xb758, 0x695d, 0xb753, 0x695a, 0xb74e, 0x6956, 0xb749,
+ 0x6953, 0xb744, 0x694f, 0xb73f, 0x694b, 0xb739, 0x6948, 0xb734,
+ 0x6944, 0xb72f, 0x6941, 0xb72a, 0x693d, 0xb725, 0x693a, 0xb720,
+ 0x6936, 0xb71a, 0x6932, 0xb715, 0x692f, 0xb710, 0x692b, 0xb70b,
+ 0x6928, 0xb706, 0x6924, 0xb701, 0x6921, 0xb6fb, 0x691d, 0xb6f6,
+ 0x6919, 0xb6f1, 0x6916, 0xb6ec, 0x6912, 0xb6e7, 0x690f, 0xb6e2,
+ 0x690b, 0xb6dd, 0x6907, 0xb6d7, 0x6904, 0xb6d2, 0x6900, 0xb6cd,
+ 0x68fd, 0xb6c8, 0x68f9, 0xb6c3, 0x68f5, 0xb6be, 0x68f2, 0xb6b8,
+ 0x68ee, 0xb6b3, 0x68eb, 0xb6ae, 0x68e7, 0xb6a9, 0x68e3, 0xb6a4,
+ 0x68e0, 0xb69f, 0x68dc, 0xb69a, 0x68d9, 0xb694, 0x68d5, 0xb68f,
+ 0x68d1, 0xb68a, 0x68ce, 0xb685, 0x68ca, 0xb680, 0x68c7, 0xb67b,
+ 0x68c3, 0xb676, 0x68bf, 0xb670, 0x68bc, 0xb66b, 0x68b8, 0xb666,
+ 0x68b5, 0xb661, 0x68b1, 0xb65c, 0x68ad, 0xb657, 0x68aa, 0xb652,
+ 0x68a6, 0xb64c, 0x68a3, 0xb647, 0x689f, 0xb642, 0x689b, 0xb63d,
+ 0x6898, 0xb638, 0x6894, 0xb633, 0x6890, 0xb62e, 0x688d, 0xb628,
+ 0x6889, 0xb623, 0x6886, 0xb61e, 0x6882, 0xb619, 0x687e, 0xb614,
+ 0x687b, 0xb60f, 0x6877, 0xb60a, 0x6873, 0xb605, 0x6870, 0xb5ff,
+ 0x686c, 0xb5fa, 0x6868, 0xb5f5, 0x6865, 0xb5f0, 0x6861, 0xb5eb,
+ 0x685e, 0xb5e6, 0x685a, 0xb5e1, 0x6856, 0xb5dc, 0x6853, 0xb5d6,
+ 0x684f, 0xb5d1, 0x684b, 0xb5cc, 0x6848, 0xb5c7, 0x6844, 0xb5c2,
+ 0x6840, 0xb5bd, 0x683d, 0xb5b8, 0x6839, 0xb5b3, 0x6835, 0xb5ae,
+ 0x6832, 0xb5a8, 0x682e, 0xb5a3, 0x682b, 0xb59e, 0x6827, 0xb599,
+ 0x6823, 0xb594, 0x6820, 0xb58f, 0x681c, 0xb58a, 0x6818, 0xb585,
+ 0x6815, 0xb57f, 0x6811, 0xb57a, 0x680d, 0xb575, 0x680a, 0xb570,
+ 0x6806, 0xb56b, 0x6802, 0xb566, 0x67ff, 0xb561, 0x67fb, 0xb55c,
+ 0x67f7, 0xb557, 0x67f4, 0xb552, 0x67f0, 0xb54c, 0x67ec, 0xb547,
+ 0x67e9, 0xb542, 0x67e5, 0xb53d, 0x67e1, 0xb538, 0x67de, 0xb533,
+ 0x67da, 0xb52e, 0x67d6, 0xb529, 0x67d3, 0xb524, 0x67cf, 0xb51f,
+ 0x67cb, 0xb519, 0x67c8, 0xb514, 0x67c4, 0xb50f, 0x67c0, 0xb50a,
+ 0x67bd, 0xb505, 0x67b9, 0xb500, 0x67b5, 0xb4fb, 0x67b2, 0xb4f6,
+ 0x67ae, 0xb4f1, 0x67aa, 0xb4ec, 0x67a6, 0xb4e7, 0x67a3, 0xb4e1,
+ 0x679f, 0xb4dc, 0x679b, 0xb4d7, 0x6798, 0xb4d2, 0x6794, 0xb4cd,
+ 0x6790, 0xb4c8, 0x678d, 0xb4c3, 0x6789, 0xb4be, 0x6785, 0xb4b9,
+ 0x6782, 0xb4b4, 0x677e, 0xb4af, 0x677a, 0xb4aa, 0x6776, 0xb4a4,
+ 0x6773, 0xb49f, 0x676f, 0xb49a, 0x676b, 0xb495, 0x6768, 0xb490,
+ 0x6764, 0xb48b, 0x6760, 0xb486, 0x675d, 0xb481, 0x6759, 0xb47c,
+ 0x6755, 0xb477, 0x6751, 0xb472, 0x674e, 0xb46d, 0x674a, 0xb468,
+ 0x6746, 0xb462, 0x6743, 0xb45d, 0x673f, 0xb458, 0x673b, 0xb453,
+ 0x6737, 0xb44e, 0x6734, 0xb449, 0x6730, 0xb444, 0x672c, 0xb43f,
+ 0x6729, 0xb43a, 0x6725, 0xb435, 0x6721, 0xb430, 0x671d, 0xb42b,
+ 0x671a, 0xb426, 0x6716, 0xb421, 0x6712, 0xb41c, 0x670e, 0xb417,
+ 0x670b, 0xb411, 0x6707, 0xb40c, 0x6703, 0xb407, 0x6700, 0xb402,
+ 0x66fc, 0xb3fd, 0x66f8, 0xb3f8, 0x66f4, 0xb3f3, 0x66f1, 0xb3ee,
+ 0x66ed, 0xb3e9, 0x66e9, 0xb3e4, 0x66e5, 0xb3df, 0x66e2, 0xb3da,
+ 0x66de, 0xb3d5, 0x66da, 0xb3d0, 0x66d6, 0xb3cb, 0x66d3, 0xb3c6,
+ 0x66cf, 0xb3c1, 0x66cb, 0xb3bc, 0x66c8, 0xb3b7, 0x66c4, 0xb3b1,
+ 0x66c0, 0xb3ac, 0x66bc, 0xb3a7, 0x66b9, 0xb3a2, 0x66b5, 0xb39d,
+ 0x66b1, 0xb398, 0x66ad, 0xb393, 0x66aa, 0xb38e, 0x66a6, 0xb389,
+ 0x66a2, 0xb384, 0x669e, 0xb37f, 0x669b, 0xb37a, 0x6697, 0xb375,
+ 0x6693, 0xb370, 0x668f, 0xb36b, 0x668b, 0xb366, 0x6688, 0xb361,
+ 0x6684, 0xb35c, 0x6680, 0xb357, 0x667c, 0xb352, 0x6679, 0xb34d,
+ 0x6675, 0xb348, 0x6671, 0xb343, 0x666d, 0xb33e, 0x666a, 0xb339,
+ 0x6666, 0xb334, 0x6662, 0xb32f, 0x665e, 0xb32a, 0x665b, 0xb325,
+ 0x6657, 0xb31f, 0x6653, 0xb31a, 0x664f, 0xb315, 0x664b, 0xb310,
+ 0x6648, 0xb30b, 0x6644, 0xb306, 0x6640, 0xb301, 0x663c, 0xb2fc,
+ 0x6639, 0xb2f7, 0x6635, 0xb2f2, 0x6631, 0xb2ed, 0x662d, 0xb2e8,
+ 0x6629, 0xb2e3, 0x6626, 0xb2de, 0x6622, 0xb2d9, 0x661e, 0xb2d4,
+ 0x661a, 0xb2cf, 0x6616, 0xb2ca, 0x6613, 0xb2c5, 0x660f, 0xb2c0,
+ 0x660b, 0xb2bb, 0x6607, 0xb2b6, 0x6603, 0xb2b1, 0x6600, 0xb2ac,
+ 0x65fc, 0xb2a7, 0x65f8, 0xb2a2, 0x65f4, 0xb29d, 0x65f0, 0xb298,
+ 0x65ed, 0xb293, 0x65e9, 0xb28e, 0x65e5, 0xb289, 0x65e1, 0xb284,
+ 0x65dd, 0xb27f, 0x65da, 0xb27a, 0x65d6, 0xb275, 0x65d2, 0xb270,
+ 0x65ce, 0xb26b, 0x65ca, 0xb266, 0x65c7, 0xb261, 0x65c3, 0xb25c,
+ 0x65bf, 0xb257, 0x65bb, 0xb252, 0x65b7, 0xb24d, 0x65b4, 0xb248,
+ 0x65b0, 0xb243, 0x65ac, 0xb23e, 0x65a8, 0xb239, 0x65a4, 0xb234,
+ 0x65a0, 0xb22f, 0x659d, 0xb22a, 0x6599, 0xb225, 0x6595, 0xb220,
+ 0x6591, 0xb21b, 0x658d, 0xb216, 0x658a, 0xb211, 0x6586, 0xb20c,
+ 0x6582, 0xb207, 0x657e, 0xb202, 0x657a, 0xb1fd, 0x6576, 0xb1f8,
+ 0x6573, 0xb1f3, 0x656f, 0xb1ee, 0x656b, 0xb1e9, 0x6567, 0xb1e4,
+ 0x6563, 0xb1df, 0x655f, 0xb1da, 0x655c, 0xb1d6, 0x6558, 0xb1d1,
+ 0x6554, 0xb1cc, 0x6550, 0xb1c7, 0x654c, 0xb1c2, 0x6548, 0xb1bd,
+ 0x6545, 0xb1b8, 0x6541, 0xb1b3, 0x653d, 0xb1ae, 0x6539, 0xb1a9,
+ 0x6535, 0xb1a4, 0x6531, 0xb19f, 0x652d, 0xb19a, 0x652a, 0xb195,
+ 0x6526, 0xb190, 0x6522, 0xb18b, 0x651e, 0xb186, 0x651a, 0xb181,
+ 0x6516, 0xb17c, 0x6513, 0xb177, 0x650f, 0xb172, 0x650b, 0xb16d,
+ 0x6507, 0xb168, 0x6503, 0xb163, 0x64ff, 0xb15e, 0x64fb, 0xb159,
+ 0x64f7, 0xb154, 0x64f4, 0xb14f, 0x64f0, 0xb14a, 0x64ec, 0xb146,
+ 0x64e8, 0xb141, 0x64e4, 0xb13c, 0x64e0, 0xb137, 0x64dc, 0xb132,
+ 0x64d9, 0xb12d, 0x64d5, 0xb128, 0x64d1, 0xb123, 0x64cd, 0xb11e,
+ 0x64c9, 0xb119, 0x64c5, 0xb114, 0x64c1, 0xb10f, 0x64bd, 0xb10a,
+ 0x64ba, 0xb105, 0x64b6, 0xb100, 0x64b2, 0xb0fb, 0x64ae, 0xb0f6,
+ 0x64aa, 0xb0f1, 0x64a6, 0xb0ec, 0x64a2, 0xb0e8, 0x649e, 0xb0e3,
+ 0x649b, 0xb0de, 0x6497, 0xb0d9, 0x6493, 0xb0d4, 0x648f, 0xb0cf,
+ 0x648b, 0xb0ca, 0x6487, 0xb0c5, 0x6483, 0xb0c0, 0x647f, 0xb0bb,
+ 0x647b, 0xb0b6, 0x6478, 0xb0b1, 0x6474, 0xb0ac, 0x6470, 0xb0a7,
+ 0x646c, 0xb0a2, 0x6468, 0xb09e, 0x6464, 0xb099, 0x6460, 0xb094,
+ 0x645c, 0xb08f, 0x6458, 0xb08a, 0x6454, 0xb085, 0x6451, 0xb080,
+ 0x644d, 0xb07b, 0x6449, 0xb076, 0x6445, 0xb071, 0x6441, 0xb06c,
+ 0x643d, 0xb067, 0x6439, 0xb062, 0x6435, 0xb05e, 0x6431, 0xb059,
+ 0x642d, 0xb054, 0x6429, 0xb04f, 0x6426, 0xb04a, 0x6422, 0xb045,
+ 0x641e, 0xb040, 0x641a, 0xb03b, 0x6416, 0xb036, 0x6412, 0xb031,
+ 0x640e, 0xb02c, 0x640a, 0xb027, 0x6406, 0xb023, 0x6402, 0xb01e,
+ 0x63fe, 0xb019, 0x63fa, 0xb014, 0x63f7, 0xb00f, 0x63f3, 0xb00a,
+ 0x63ef, 0xb005, 0x63eb, 0xb000, 0x63e7, 0xaffb, 0x63e3, 0xaff6,
+ 0x63df, 0xaff1, 0x63db, 0xafed, 0x63d7, 0xafe8, 0x63d3, 0xafe3,
+ 0x63cf, 0xafde, 0x63cb, 0xafd9, 0x63c7, 0xafd4, 0x63c3, 0xafcf,
+ 0x63c0, 0xafca, 0x63bc, 0xafc5, 0x63b8, 0xafc1, 0x63b4, 0xafbc,
+ 0x63b0, 0xafb7, 0x63ac, 0xafb2, 0x63a8, 0xafad, 0x63a4, 0xafa8,
+ 0x63a0, 0xafa3, 0x639c, 0xaf9e, 0x6398, 0xaf99, 0x6394, 0xaf94,
+ 0x6390, 0xaf90, 0x638c, 0xaf8b, 0x6388, 0xaf86, 0x6384, 0xaf81,
+ 0x6380, 0xaf7c, 0x637c, 0xaf77, 0x6378, 0xaf72, 0x6375, 0xaf6d,
+ 0x6371, 0xaf69, 0x636d, 0xaf64, 0x6369, 0xaf5f, 0x6365, 0xaf5a,
+ 0x6361, 0xaf55, 0x635d, 0xaf50, 0x6359, 0xaf4b, 0x6355, 0xaf46,
+ 0x6351, 0xaf41, 0x634d, 0xaf3d, 0x6349, 0xaf38, 0x6345, 0xaf33,
+ 0x6341, 0xaf2e, 0x633d, 0xaf29, 0x6339, 0xaf24, 0x6335, 0xaf1f,
+ 0x6331, 0xaf1b, 0x632d, 0xaf16, 0x6329, 0xaf11, 0x6325, 0xaf0c,
+ 0x6321, 0xaf07, 0x631d, 0xaf02, 0x6319, 0xaefd, 0x6315, 0xaef8,
+ 0x6311, 0xaef4, 0x630d, 0xaeef, 0x6309, 0xaeea, 0x6305, 0xaee5,
+ 0x6301, 0xaee0, 0x62fd, 0xaedb, 0x62f9, 0xaed6, 0x62f5, 0xaed2,
+ 0x62f2, 0xaecd, 0x62ee, 0xaec8, 0x62ea, 0xaec3, 0x62e6, 0xaebe,
+ 0x62e2, 0xaeb9, 0x62de, 0xaeb4, 0x62da, 0xaeb0, 0x62d6, 0xaeab,
+ 0x62d2, 0xaea6, 0x62ce, 0xaea1, 0x62ca, 0xae9c, 0x62c6, 0xae97,
+ 0x62c2, 0xae92, 0x62be, 0xae8e, 0x62ba, 0xae89, 0x62b6, 0xae84,
+ 0x62b2, 0xae7f, 0x62ae, 0xae7a, 0x62aa, 0xae75, 0x62a6, 0xae71,
+ 0x62a2, 0xae6c, 0x629e, 0xae67, 0x629a, 0xae62, 0x6296, 0xae5d,
+ 0x6292, 0xae58, 0x628e, 0xae54, 0x628a, 0xae4f, 0x6286, 0xae4a,
+ 0x6282, 0xae45, 0x627e, 0xae40, 0x627a, 0xae3b, 0x6275, 0xae37,
+ 0x6271, 0xae32, 0x626d, 0xae2d, 0x6269, 0xae28, 0x6265, 0xae23,
+ 0x6261, 0xae1e, 0x625d, 0xae1a, 0x6259, 0xae15, 0x6255, 0xae10,
+ 0x6251, 0xae0b, 0x624d, 0xae06, 0x6249, 0xae01, 0x6245, 0xadfd,
+ 0x6241, 0xadf8, 0x623d, 0xadf3, 0x6239, 0xadee, 0x6235, 0xade9,
+ 0x6231, 0xade4, 0x622d, 0xade0, 0x6229, 0xaddb, 0x6225, 0xadd6,
+ 0x6221, 0xadd1, 0x621d, 0xadcc, 0x6219, 0xadc8, 0x6215, 0xadc3,
+ 0x6211, 0xadbe, 0x620d, 0xadb9, 0x6209, 0xadb4, 0x6205, 0xadaf,
+ 0x6201, 0xadab, 0x61fd, 0xada6, 0x61f9, 0xada1, 0x61f5, 0xad9c,
+ 0x61f1, 0xad97, 0x61ec, 0xad93, 0x61e8, 0xad8e, 0x61e4, 0xad89,
+ 0x61e0, 0xad84, 0x61dc, 0xad7f, 0x61d8, 0xad7b, 0x61d4, 0xad76,
+ 0x61d0, 0xad71, 0x61cc, 0xad6c, 0x61c8, 0xad67, 0x61c4, 0xad63,
+ 0x61c0, 0xad5e, 0x61bc, 0xad59, 0x61b8, 0xad54, 0x61b4, 0xad4f,
+ 0x61b0, 0xad4b, 0x61ac, 0xad46, 0x61a8, 0xad41, 0x61a3, 0xad3c,
+ 0x619f, 0xad37, 0x619b, 0xad33, 0x6197, 0xad2e, 0x6193, 0xad29,
+ 0x618f, 0xad24, 0x618b, 0xad1f, 0x6187, 0xad1b, 0x6183, 0xad16,
+ 0x617f, 0xad11, 0x617b, 0xad0c, 0x6177, 0xad08, 0x6173, 0xad03,
+ 0x616f, 0xacfe, 0x616b, 0xacf9, 0x6166, 0xacf4, 0x6162, 0xacf0,
+ 0x615e, 0xaceb, 0x615a, 0xace6, 0x6156, 0xace1, 0x6152, 0xacdd,
+ 0x614e, 0xacd8, 0x614a, 0xacd3, 0x6146, 0xacce, 0x6142, 0xacc9,
+ 0x613e, 0xacc5, 0x613a, 0xacc0, 0x6135, 0xacbb, 0x6131, 0xacb6,
+ 0x612d, 0xacb2, 0x6129, 0xacad, 0x6125, 0xaca8, 0x6121, 0xaca3,
+ 0x611d, 0xac9e, 0x6119, 0xac9a, 0x6115, 0xac95, 0x6111, 0xac90,
+ 0x610d, 0xac8b, 0x6108, 0xac87, 0x6104, 0xac82, 0x6100, 0xac7d,
+ 0x60fc, 0xac78, 0x60f8, 0xac74, 0x60f4, 0xac6f, 0x60f0, 0xac6a,
+ 0x60ec, 0xac65, 0x60e8, 0xac61, 0x60e4, 0xac5c, 0x60df, 0xac57,
+ 0x60db, 0xac52, 0x60d7, 0xac4e, 0x60d3, 0xac49, 0x60cf, 0xac44,
+ 0x60cb, 0xac3f, 0x60c7, 0xac3b, 0x60c3, 0xac36, 0x60bf, 0xac31,
+ 0x60ba, 0xac2c, 0x60b6, 0xac28, 0x60b2, 0xac23, 0x60ae, 0xac1e,
+ 0x60aa, 0xac19, 0x60a6, 0xac15, 0x60a2, 0xac10, 0x609e, 0xac0b,
+ 0x6099, 0xac06, 0x6095, 0xac02, 0x6091, 0xabfd, 0x608d, 0xabf8,
+ 0x6089, 0xabf3, 0x6085, 0xabef, 0x6081, 0xabea, 0x607d, 0xabe5,
+ 0x6078, 0xabe0, 0x6074, 0xabdc, 0x6070, 0xabd7, 0x606c, 0xabd2,
+ 0x6068, 0xabcd, 0x6064, 0xabc9, 0x6060, 0xabc4, 0x605c, 0xabbf,
+ 0x6057, 0xabbb, 0x6053, 0xabb6, 0x604f, 0xabb1, 0x604b, 0xabac,
+ 0x6047, 0xaba8, 0x6043, 0xaba3, 0x603f, 0xab9e, 0x603a, 0xab99,
+ 0x6036, 0xab95, 0x6032, 0xab90, 0x602e, 0xab8b, 0x602a, 0xab87,
+ 0x6026, 0xab82, 0x6022, 0xab7d, 0x601d, 0xab78, 0x6019, 0xab74,
+ 0x6015, 0xab6f, 0x6011, 0xab6a, 0x600d, 0xab66, 0x6009, 0xab61,
+ 0x6004, 0xab5c, 0x6000, 0xab57, 0x5ffc, 0xab53, 0x5ff8, 0xab4e,
+ 0x5ff4, 0xab49, 0x5ff0, 0xab45, 0x5fec, 0xab40, 0x5fe7, 0xab3b,
+ 0x5fe3, 0xab36, 0x5fdf, 0xab32, 0x5fdb, 0xab2d, 0x5fd7, 0xab28,
+ 0x5fd3, 0xab24, 0x5fce, 0xab1f, 0x5fca, 0xab1a, 0x5fc6, 0xab16,
+ 0x5fc2, 0xab11, 0x5fbe, 0xab0c, 0x5fba, 0xab07, 0x5fb5, 0xab03,
+ 0x5fb1, 0xaafe, 0x5fad, 0xaaf9, 0x5fa9, 0xaaf5, 0x5fa5, 0xaaf0,
+ 0x5fa0, 0xaaeb, 0x5f9c, 0xaae7, 0x5f98, 0xaae2, 0x5f94, 0xaadd,
+ 0x5f90, 0xaad8, 0x5f8c, 0xaad4, 0x5f87, 0xaacf, 0x5f83, 0xaaca,
+ 0x5f7f, 0xaac6, 0x5f7b, 0xaac1, 0x5f77, 0xaabc, 0x5f72, 0xaab8,
+ 0x5f6e, 0xaab3, 0x5f6a, 0xaaae, 0x5f66, 0xaaaa, 0x5f62, 0xaaa5,
+ 0x5f5e, 0xaaa0, 0x5f59, 0xaa9c, 0x5f55, 0xaa97, 0x5f51, 0xaa92,
+ 0x5f4d, 0xaa8e, 0x5f49, 0xaa89, 0x5f44, 0xaa84, 0x5f40, 0xaa7f,
+ 0x5f3c, 0xaa7b, 0x5f38, 0xaa76, 0x5f34, 0xaa71, 0x5f2f, 0xaa6d,
+ 0x5f2b, 0xaa68, 0x5f27, 0xaa63, 0x5f23, 0xaa5f, 0x5f1f, 0xaa5a,
+ 0x5f1a, 0xaa55, 0x5f16, 0xaa51, 0x5f12, 0xaa4c, 0x5f0e, 0xaa47,
+ 0x5f0a, 0xaa43, 0x5f05, 0xaa3e, 0x5f01, 0xaa39, 0x5efd, 0xaa35,
+ 0x5ef9, 0xaa30, 0x5ef5, 0xaa2b, 0x5ef0, 0xaa27, 0x5eec, 0xaa22,
+ 0x5ee8, 0xaa1d, 0x5ee4, 0xaa19, 0x5edf, 0xaa14, 0x5edb, 0xaa10,
+ 0x5ed7, 0xaa0b, 0x5ed3, 0xaa06, 0x5ecf, 0xaa02, 0x5eca, 0xa9fd,
+ 0x5ec6, 0xa9f8, 0x5ec2, 0xa9f4, 0x5ebe, 0xa9ef, 0x5eb9, 0xa9ea,
+ 0x5eb5, 0xa9e6, 0x5eb1, 0xa9e1, 0x5ead, 0xa9dc, 0x5ea9, 0xa9d8,
+ 0x5ea4, 0xa9d3, 0x5ea0, 0xa9ce, 0x5e9c, 0xa9ca, 0x5e98, 0xa9c5,
+ 0x5e93, 0xa9c0, 0x5e8f, 0xa9bc, 0x5e8b, 0xa9b7, 0x5e87, 0xa9b3,
+ 0x5e82, 0xa9ae, 0x5e7e, 0xa9a9, 0x5e7a, 0xa9a5, 0x5e76, 0xa9a0,
+ 0x5e71, 0xa99b, 0x5e6d, 0xa997, 0x5e69, 0xa992, 0x5e65, 0xa98d,
+ 0x5e60, 0xa989, 0x5e5c, 0xa984, 0x5e58, 0xa980, 0x5e54, 0xa97b,
+ 0x5e50, 0xa976, 0x5e4b, 0xa972, 0x5e47, 0xa96d, 0x5e43, 0xa968,
+ 0x5e3f, 0xa964, 0x5e3a, 0xa95f, 0x5e36, 0xa95b, 0x5e32, 0xa956,
+ 0x5e2d, 0xa951, 0x5e29, 0xa94d, 0x5e25, 0xa948, 0x5e21, 0xa943,
+ 0x5e1c, 0xa93f, 0x5e18, 0xa93a, 0x5e14, 0xa936, 0x5e10, 0xa931,
+ 0x5e0b, 0xa92c, 0x5e07, 0xa928, 0x5e03, 0xa923, 0x5dff, 0xa91e,
+ 0x5dfa, 0xa91a, 0x5df6, 0xa915, 0x5df2, 0xa911, 0x5dee, 0xa90c,
+ 0x5de9, 0xa907, 0x5de5, 0xa903, 0x5de1, 0xa8fe, 0x5ddc, 0xa8fa,
+ 0x5dd8, 0xa8f5, 0x5dd4, 0xa8f0, 0x5dd0, 0xa8ec, 0x5dcb, 0xa8e7,
+ 0x5dc7, 0xa8e3, 0x5dc3, 0xa8de, 0x5dbf, 0xa8d9, 0x5dba, 0xa8d5,
+ 0x5db6, 0xa8d0, 0x5db2, 0xa8cc, 0x5dad, 0xa8c7, 0x5da9, 0xa8c2,
+ 0x5da5, 0xa8be, 0x5da1, 0xa8b9, 0x5d9c, 0xa8b5, 0x5d98, 0xa8b0,
+ 0x5d94, 0xa8ab, 0x5d8f, 0xa8a7, 0x5d8b, 0xa8a2, 0x5d87, 0xa89e,
+ 0x5d83, 0xa899, 0x5d7e, 0xa894, 0x5d7a, 0xa890, 0x5d76, 0xa88b,
+ 0x5d71, 0xa887, 0x5d6d, 0xa882, 0x5d69, 0xa87d, 0x5d65, 0xa879,
+ 0x5d60, 0xa874, 0x5d5c, 0xa870, 0x5d58, 0xa86b, 0x5d53, 0xa867,
+ 0x5d4f, 0xa862, 0x5d4b, 0xa85d, 0x5d46, 0xa859, 0x5d42, 0xa854,
+ 0x5d3e, 0xa850, 0x5d3a, 0xa84b, 0x5d35, 0xa847, 0x5d31, 0xa842,
+ 0x5d2d, 0xa83d, 0x5d28, 0xa839, 0x5d24, 0xa834, 0x5d20, 0xa830,
+ 0x5d1b, 0xa82b, 0x5d17, 0xa827, 0x5d13, 0xa822, 0x5d0e, 0xa81d,
+ 0x5d0a, 0xa819, 0x5d06, 0xa814, 0x5d01, 0xa810, 0x5cfd, 0xa80b,
+ 0x5cf9, 0xa807, 0x5cf5, 0xa802, 0x5cf0, 0xa7fd, 0x5cec, 0xa7f9,
+ 0x5ce8, 0xa7f4, 0x5ce3, 0xa7f0, 0x5cdf, 0xa7eb, 0x5cdb, 0xa7e7,
+ 0x5cd6, 0xa7e2, 0x5cd2, 0xa7de, 0x5cce, 0xa7d9, 0x5cc9, 0xa7d4,
+ 0x5cc5, 0xa7d0, 0x5cc1, 0xa7cb, 0x5cbc, 0xa7c7, 0x5cb8, 0xa7c2,
+ 0x5cb4, 0xa7be, 0x5caf, 0xa7b9, 0x5cab, 0xa7b5, 0x5ca7, 0xa7b0,
+ 0x5ca2, 0xa7ab, 0x5c9e, 0xa7a7, 0x5c9a, 0xa7a2, 0x5c95, 0xa79e,
+ 0x5c91, 0xa799, 0x5c8d, 0xa795, 0x5c88, 0xa790, 0x5c84, 0xa78c,
+ 0x5c80, 0xa787, 0x5c7b, 0xa783, 0x5c77, 0xa77e, 0x5c73, 0xa779,
+ 0x5c6e, 0xa775, 0x5c6a, 0xa770, 0x5c66, 0xa76c, 0x5c61, 0xa767,
+ 0x5c5d, 0xa763, 0x5c58, 0xa75e, 0x5c54, 0xa75a, 0x5c50, 0xa755,
+ 0x5c4b, 0xa751, 0x5c47, 0xa74c, 0x5c43, 0xa748, 0x5c3e, 0xa743,
+ 0x5c3a, 0xa73f, 0x5c36, 0xa73a, 0x5c31, 0xa735, 0x5c2d, 0xa731,
+ 0x5c29, 0xa72c, 0x5c24, 0xa728, 0x5c20, 0xa723, 0x5c1b, 0xa71f,
+ 0x5c17, 0xa71a, 0x5c13, 0xa716, 0x5c0e, 0xa711, 0x5c0a, 0xa70d,
+ 0x5c06, 0xa708, 0x5c01, 0xa704, 0x5bfd, 0xa6ff, 0x5bf9, 0xa6fb,
+ 0x5bf4, 0xa6f6, 0x5bf0, 0xa6f2, 0x5beb, 0xa6ed, 0x5be7, 0xa6e9,
+ 0x5be3, 0xa6e4, 0x5bde, 0xa6e0, 0x5bda, 0xa6db, 0x5bd6, 0xa6d7,
+ 0x5bd1, 0xa6d2, 0x5bcd, 0xa6ce, 0x5bc8, 0xa6c9, 0x5bc4, 0xa6c5,
+ 0x5bc0, 0xa6c0, 0x5bbb, 0xa6bc, 0x5bb7, 0xa6b7, 0x5bb2, 0xa6b3,
+ 0x5bae, 0xa6ae, 0x5baa, 0xa6aa, 0x5ba5, 0xa6a5, 0x5ba1, 0xa6a1,
+ 0x5b9d, 0xa69c, 0x5b98, 0xa698, 0x5b94, 0xa693, 0x5b8f, 0xa68f,
+ 0x5b8b, 0xa68a, 0x5b87, 0xa686, 0x5b82, 0xa681, 0x5b7e, 0xa67d,
+ 0x5b79, 0xa678, 0x5b75, 0xa674, 0x5b71, 0xa66f, 0x5b6c, 0xa66b,
+ 0x5b68, 0xa666, 0x5b63, 0xa662, 0x5b5f, 0xa65d, 0x5b5b, 0xa659,
+ 0x5b56, 0xa654, 0x5b52, 0xa650, 0x5b4d, 0xa64b, 0x5b49, 0xa647,
+ 0x5b45, 0xa642, 0x5b40, 0xa63e, 0x5b3c, 0xa639, 0x5b37, 0xa635,
+ 0x5b33, 0xa630, 0x5b2f, 0xa62c, 0x5b2a, 0xa627, 0x5b26, 0xa623,
+ 0x5b21, 0xa61f, 0x5b1d, 0xa61a, 0x5b19, 0xa616, 0x5b14, 0xa611,
+ 0x5b10, 0xa60d, 0x5b0b, 0xa608, 0x5b07, 0xa604, 0x5b02, 0xa5ff,
+ 0x5afe, 0xa5fb, 0x5afa, 0xa5f6, 0x5af5, 0xa5f2, 0x5af1, 0xa5ed,
+ 0x5aec, 0xa5e9, 0x5ae8, 0xa5e4, 0x5ae4, 0xa5e0, 0x5adf, 0xa5dc,
+ 0x5adb, 0xa5d7, 0x5ad6, 0xa5d3, 0x5ad2, 0xa5ce, 0x5acd, 0xa5ca,
+ 0x5ac9, 0xa5c5, 0x5ac5, 0xa5c1, 0x5ac0, 0xa5bc, 0x5abc, 0xa5b8,
+ 0x5ab7, 0xa5b3, 0x5ab3, 0xa5af, 0x5aae, 0xa5aa, 0x5aaa, 0xa5a6,
+ 0x5aa5, 0xa5a2, 0x5aa1, 0xa59d, 0x5a9d, 0xa599, 0x5a98, 0xa594,
+ 0x5a94, 0xa590, 0x5a8f, 0xa58b, 0x5a8b, 0xa587, 0x5a86, 0xa582,
+ 0x5a82, 0xa57e, 0x5a7e, 0xa57a, 0x5a79, 0xa575, 0x5a75, 0xa571,
+ 0x5a70, 0xa56c, 0x5a6c, 0xa568, 0x5a67, 0xa563, 0x5a63, 0xa55f,
+ 0x5a5e, 0xa55b, 0x5a5a, 0xa556, 0x5a56, 0xa552, 0x5a51, 0xa54d,
+ 0x5a4d, 0xa549, 0x5a48, 0xa544, 0x5a44, 0xa540, 0x5a3f, 0xa53b,
+ 0x5a3b, 0xa537, 0x5a36, 0xa533, 0x5a32, 0xa52e, 0x5a2d, 0xa52a,
+ 0x5a29, 0xa525, 0x5a24, 0xa521, 0x5a20, 0xa51c, 0x5a1c, 0xa518,
+ 0x5a17, 0xa514, 0x5a13, 0xa50f, 0x5a0e, 0xa50b, 0x5a0a, 0xa506,
+ 0x5a05, 0xa502, 0x5a01, 0xa4fe, 0x59fc, 0xa4f9, 0x59f8, 0xa4f5,
+ 0x59f3, 0xa4f0, 0x59ef, 0xa4ec, 0x59ea, 0xa4e7, 0x59e6, 0xa4e3,
+ 0x59e1, 0xa4df, 0x59dd, 0xa4da, 0x59d9, 0xa4d6, 0x59d4, 0xa4d1,
+ 0x59d0, 0xa4cd, 0x59cb, 0xa4c9, 0x59c7, 0xa4c4, 0x59c2, 0xa4c0,
+ 0x59be, 0xa4bb, 0x59b9, 0xa4b7, 0x59b5, 0xa4b3, 0x59b0, 0xa4ae,
+ 0x59ac, 0xa4aa, 0x59a7, 0xa4a5, 0x59a3, 0xa4a1, 0x599e, 0xa49d,
+ 0x599a, 0xa498, 0x5995, 0xa494, 0x5991, 0xa48f, 0x598c, 0xa48b,
+ 0x5988, 0xa487, 0x5983, 0xa482, 0x597f, 0xa47e, 0x597a, 0xa479,
+ 0x5976, 0xa475, 0x5971, 0xa471, 0x596d, 0xa46c, 0x5968, 0xa468,
+ 0x5964, 0xa463, 0x595f, 0xa45f, 0x595b, 0xa45b, 0x5956, 0xa456,
+ 0x5952, 0xa452, 0x594d, 0xa44e, 0x5949, 0xa449, 0x5944, 0xa445,
+ 0x5940, 0xa440, 0x593b, 0xa43c, 0x5937, 0xa438, 0x5932, 0xa433,
+ 0x592e, 0xa42f, 0x5929, 0xa42a, 0x5925, 0xa426, 0x5920, 0xa422,
+ 0x591c, 0xa41d, 0x5917, 0xa419, 0x5913, 0xa415, 0x590e, 0xa410,
+ 0x590a, 0xa40c, 0x5905, 0xa407, 0x5901, 0xa403, 0x58fc, 0xa3ff,
+ 0x58f8, 0xa3fa, 0x58f3, 0xa3f6, 0x58ef, 0xa3f2, 0x58ea, 0xa3ed,
+ 0x58e6, 0xa3e9, 0x58e1, 0xa3e5, 0x58dd, 0xa3e0, 0x58d8, 0xa3dc,
+ 0x58d4, 0xa3d7, 0x58cf, 0xa3d3, 0x58cb, 0xa3cf, 0x58c6, 0xa3ca,
+ 0x58c1, 0xa3c6, 0x58bd, 0xa3c2, 0x58b8, 0xa3bd, 0x58b4, 0xa3b9,
+ 0x58af, 0xa3b5, 0x58ab, 0xa3b0, 0x58a6, 0xa3ac, 0x58a2, 0xa3a8,
+ 0x589d, 0xa3a3, 0x5899, 0xa39f, 0x5894, 0xa39a, 0x5890, 0xa396,
+ 0x588b, 0xa392, 0x5887, 0xa38d, 0x5882, 0xa389, 0x587d, 0xa385,
+ 0x5879, 0xa380, 0x5874, 0xa37c, 0x5870, 0xa378, 0x586b, 0xa373,
+ 0x5867, 0xa36f, 0x5862, 0xa36b, 0x585e, 0xa366, 0x5859, 0xa362,
+ 0x5855, 0xa35e, 0x5850, 0xa359, 0x584b, 0xa355, 0x5847, 0xa351,
+ 0x5842, 0xa34c, 0x583e, 0xa348, 0x5839, 0xa344, 0x5835, 0xa33f,
+ 0x5830, 0xa33b, 0x582c, 0xa337, 0x5827, 0xa332, 0x5822, 0xa32e,
+ 0x581e, 0xa32a, 0x5819, 0xa325, 0x5815, 0xa321, 0x5810, 0xa31d,
+ 0x580c, 0xa318, 0x5807, 0xa314, 0x5803, 0xa310, 0x57fe, 0xa30b,
+ 0x57f9, 0xa307, 0x57f5, 0xa303, 0x57f0, 0xa2ff, 0x57ec, 0xa2fa,
+ 0x57e7, 0xa2f6, 0x57e3, 0xa2f2, 0x57de, 0xa2ed, 0x57d9, 0xa2e9,
+ 0x57d5, 0xa2e5, 0x57d0, 0xa2e0, 0x57cc, 0xa2dc, 0x57c7, 0xa2d8,
+ 0x57c3, 0xa2d3, 0x57be, 0xa2cf, 0x57b9, 0xa2cb, 0x57b5, 0xa2c6,
+ 0x57b0, 0xa2c2, 0x57ac, 0xa2be, 0x57a7, 0xa2ba, 0x57a3, 0xa2b5,
+ 0x579e, 0xa2b1, 0x5799, 0xa2ad, 0x5795, 0xa2a8, 0x5790, 0xa2a4,
+ 0x578c, 0xa2a0, 0x5787, 0xa29b, 0x5783, 0xa297, 0x577e, 0xa293,
+ 0x5779, 0xa28f, 0x5775, 0xa28a, 0x5770, 0xa286, 0x576c, 0xa282,
+ 0x5767, 0xa27d, 0x5762, 0xa279, 0x575e, 0xa275, 0x5759, 0xa271,
+ 0x5755, 0xa26c, 0x5750, 0xa268, 0x574b, 0xa264, 0x5747, 0xa25f,
+ 0x5742, 0xa25b, 0x573e, 0xa257, 0x5739, 0xa253, 0x5734, 0xa24e,
+ 0x5730, 0xa24a, 0x572b, 0xa246, 0x5727, 0xa241, 0x5722, 0xa23d,
+ 0x571d, 0xa239, 0x5719, 0xa235, 0x5714, 0xa230, 0x5710, 0xa22c,
+ 0x570b, 0xa228, 0x5706, 0xa224, 0x5702, 0xa21f, 0x56fd, 0xa21b,
+ 0x56f9, 0xa217, 0x56f4, 0xa212, 0x56ef, 0xa20e, 0x56eb, 0xa20a,
+ 0x56e6, 0xa206, 0x56e2, 0xa201, 0x56dd, 0xa1fd, 0x56d8, 0xa1f9,
+ 0x56d4, 0xa1f5, 0x56cf, 0xa1f0, 0x56ca, 0xa1ec, 0x56c6, 0xa1e8,
+ 0x56c1, 0xa1e4, 0x56bd, 0xa1df, 0x56b8, 0xa1db, 0x56b3, 0xa1d7,
+ 0x56af, 0xa1d3, 0x56aa, 0xa1ce, 0x56a5, 0xa1ca, 0x56a1, 0xa1c6,
+ 0x569c, 0xa1c1, 0x5698, 0xa1bd, 0x5693, 0xa1b9, 0x568e, 0xa1b5,
+ 0x568a, 0xa1b0, 0x5685, 0xa1ac, 0x5680, 0xa1a8, 0x567c, 0xa1a4,
+ 0x5677, 0xa1a0, 0x5673, 0xa19b, 0x566e, 0xa197, 0x5669, 0xa193,
+ 0x5665, 0xa18f, 0x5660, 0xa18a, 0x565b, 0xa186, 0x5657, 0xa182,
+ 0x5652, 0xa17e, 0x564d, 0xa179, 0x5649, 0xa175, 0x5644, 0xa171,
+ 0x5640, 0xa16d, 0x563b, 0xa168, 0x5636, 0xa164, 0x5632, 0xa160,
+ 0x562d, 0xa15c, 0x5628, 0xa157, 0x5624, 0xa153, 0x561f, 0xa14f,
+ 0x561a, 0xa14b, 0x5616, 0xa147, 0x5611, 0xa142, 0x560c, 0xa13e,
+ 0x5608, 0xa13a, 0x5603, 0xa136, 0x55fe, 0xa131, 0x55fa, 0xa12d,
+ 0x55f5, 0xa129, 0x55f0, 0xa125, 0x55ec, 0xa121, 0x55e7, 0xa11c,
+ 0x55e3, 0xa118, 0x55de, 0xa114, 0x55d9, 0xa110, 0x55d5, 0xa10b,
+ 0x55d0, 0xa107, 0x55cb, 0xa103, 0x55c7, 0xa0ff, 0x55c2, 0xa0fb,
+ 0x55bd, 0xa0f6, 0x55b9, 0xa0f2, 0x55b4, 0xa0ee, 0x55af, 0xa0ea,
+ 0x55ab, 0xa0e6, 0x55a6, 0xa0e1, 0x55a1, 0xa0dd, 0x559d, 0xa0d9,
+ 0x5598, 0xa0d5, 0x5593, 0xa0d1, 0x558f, 0xa0cc, 0x558a, 0xa0c8,
+ 0x5585, 0xa0c4, 0x5581, 0xa0c0, 0x557c, 0xa0bc, 0x5577, 0xa0b7,
+ 0x5572, 0xa0b3, 0x556e, 0xa0af, 0x5569, 0xa0ab, 0x5564, 0xa0a7,
+ 0x5560, 0xa0a2, 0x555b, 0xa09e, 0x5556, 0xa09a, 0x5552, 0xa096,
+ 0x554d, 0xa092, 0x5548, 0xa08e, 0x5544, 0xa089, 0x553f, 0xa085,
+ 0x553a, 0xa081, 0x5536, 0xa07d, 0x5531, 0xa079, 0x552c, 0xa074,
+ 0x5528, 0xa070, 0x5523, 0xa06c, 0x551e, 0xa068, 0x5519, 0xa064,
+ 0x5515, 0xa060, 0x5510, 0xa05b, 0x550b, 0xa057, 0x5507, 0xa053,
+ 0x5502, 0xa04f, 0x54fd, 0xa04b, 0x54f9, 0xa046, 0x54f4, 0xa042,
+ 0x54ef, 0xa03e, 0x54ea, 0xa03a, 0x54e6, 0xa036, 0x54e1, 0xa032,
+ 0x54dc, 0xa02d, 0x54d8, 0xa029, 0x54d3, 0xa025, 0x54ce, 0xa021,
+ 0x54ca, 0xa01d, 0x54c5, 0xa019, 0x54c0, 0xa014, 0x54bb, 0xa010,
+ 0x54b7, 0xa00c, 0x54b2, 0xa008, 0x54ad, 0xa004, 0x54a9, 0xa000,
+ 0x54a4, 0x9ffc, 0x549f, 0x9ff7, 0x549a, 0x9ff3, 0x5496, 0x9fef,
+ 0x5491, 0x9feb, 0x548c, 0x9fe7, 0x5488, 0x9fe3, 0x5483, 0x9fde,
+ 0x547e, 0x9fda, 0x5479, 0x9fd6, 0x5475, 0x9fd2, 0x5470, 0x9fce,
+ 0x546b, 0x9fca, 0x5467, 0x9fc6, 0x5462, 0x9fc1, 0x545d, 0x9fbd,
+ 0x5458, 0x9fb9, 0x5454, 0x9fb5, 0x544f, 0x9fb1, 0x544a, 0x9fad,
+ 0x5445, 0x9fa9, 0x5441, 0x9fa4, 0x543c, 0x9fa0, 0x5437, 0x9f9c,
+ 0x5433, 0x9f98, 0x542e, 0x9f94, 0x5429, 0x9f90, 0x5424, 0x9f8c,
+ 0x5420, 0x9f88, 0x541b, 0x9f83, 0x5416, 0x9f7f, 0x5411, 0x9f7b,
+ 0x540d, 0x9f77, 0x5408, 0x9f73, 0x5403, 0x9f6f, 0x53fe, 0x9f6b,
+ 0x53fa, 0x9f67, 0x53f5, 0x9f62, 0x53f0, 0x9f5e, 0x53eb, 0x9f5a,
+ 0x53e7, 0x9f56, 0x53e2, 0x9f52, 0x53dd, 0x9f4e, 0x53d8, 0x9f4a,
+ 0x53d4, 0x9f46, 0x53cf, 0x9f41, 0x53ca, 0x9f3d, 0x53c5, 0x9f39,
+ 0x53c1, 0x9f35, 0x53bc, 0x9f31, 0x53b7, 0x9f2d, 0x53b2, 0x9f29,
+ 0x53ae, 0x9f25, 0x53a9, 0x9f21, 0x53a4, 0x9f1c, 0x539f, 0x9f18,
+ 0x539b, 0x9f14, 0x5396, 0x9f10, 0x5391, 0x9f0c, 0x538c, 0x9f08,
+ 0x5388, 0x9f04, 0x5383, 0x9f00, 0x537e, 0x9efc, 0x5379, 0x9ef8,
+ 0x5375, 0x9ef3, 0x5370, 0x9eef, 0x536b, 0x9eeb, 0x5366, 0x9ee7,
+ 0x5362, 0x9ee3, 0x535d, 0x9edf, 0x5358, 0x9edb, 0x5353, 0x9ed7,
+ 0x534e, 0x9ed3, 0x534a, 0x9ecf, 0x5345, 0x9ecb, 0x5340, 0x9ec6,
+ 0x533b, 0x9ec2, 0x5337, 0x9ebe, 0x5332, 0x9eba, 0x532d, 0x9eb6,
+ 0x5328, 0x9eb2, 0x5323, 0x9eae, 0x531f, 0x9eaa, 0x531a, 0x9ea6,
+ 0x5315, 0x9ea2, 0x5310, 0x9e9e, 0x530c, 0x9e9a, 0x5307, 0x9e95,
+ 0x5302, 0x9e91, 0x52fd, 0x9e8d, 0x52f8, 0x9e89, 0x52f4, 0x9e85,
+ 0x52ef, 0x9e81, 0x52ea, 0x9e7d, 0x52e5, 0x9e79, 0x52e1, 0x9e75,
+ 0x52dc, 0x9e71, 0x52d7, 0x9e6d, 0x52d2, 0x9e69, 0x52cd, 0x9e65,
+ 0x52c9, 0x9e61, 0x52c4, 0x9e5d, 0x52bf, 0x9e58, 0x52ba, 0x9e54,
+ 0x52b5, 0x9e50, 0x52b1, 0x9e4c, 0x52ac, 0x9e48, 0x52a7, 0x9e44,
+ 0x52a2, 0x9e40, 0x529d, 0x9e3c, 0x5299, 0x9e38, 0x5294, 0x9e34,
+ 0x528f, 0x9e30, 0x528a, 0x9e2c, 0x5285, 0x9e28, 0x5281, 0x9e24,
+ 0x527c, 0x9e20, 0x5277, 0x9e1c, 0x5272, 0x9e18, 0x526d, 0x9e14,
+ 0x5269, 0x9e0f, 0x5264, 0x9e0b, 0x525f, 0x9e07, 0x525a, 0x9e03,
+ 0x5255, 0x9dff, 0x5251, 0x9dfb, 0x524c, 0x9df7, 0x5247, 0x9df3,
+ 0x5242, 0x9def, 0x523d, 0x9deb, 0x5238, 0x9de7, 0x5234, 0x9de3,
+ 0x522f, 0x9ddf, 0x522a, 0x9ddb, 0x5225, 0x9dd7, 0x5220, 0x9dd3,
+ 0x521c, 0x9dcf, 0x5217, 0x9dcb, 0x5212, 0x9dc7, 0x520d, 0x9dc3,
+ 0x5208, 0x9dbf, 0x5203, 0x9dbb, 0x51ff, 0x9db7, 0x51fa, 0x9db3,
+ 0x51f5, 0x9daf, 0x51f0, 0x9dab, 0x51eb, 0x9da7, 0x51e6, 0x9da3,
+ 0x51e2, 0x9d9f, 0x51dd, 0x9d9b, 0x51d8, 0x9d97, 0x51d3, 0x9d93,
+ 0x51ce, 0x9d8f, 0x51c9, 0x9d8b, 0x51c5, 0x9d86, 0x51c0, 0x9d82,
+ 0x51bb, 0x9d7e, 0x51b6, 0x9d7a, 0x51b1, 0x9d76, 0x51ac, 0x9d72,
+ 0x51a8, 0x9d6e, 0x51a3, 0x9d6a, 0x519e, 0x9d66, 0x5199, 0x9d62,
+ 0x5194, 0x9d5e, 0x518f, 0x9d5a, 0x518b, 0x9d56, 0x5186, 0x9d52,
+ 0x5181, 0x9d4e, 0x517c, 0x9d4a, 0x5177, 0x9d46, 0x5172, 0x9d42,
+ 0x516e, 0x9d3e, 0x5169, 0x9d3a, 0x5164, 0x9d36, 0x515f, 0x9d32,
+ 0x515a, 0x9d2e, 0x5155, 0x9d2a, 0x5150, 0x9d26, 0x514c, 0x9d22,
+ 0x5147, 0x9d1e, 0x5142, 0x9d1a, 0x513d, 0x9d16, 0x5138, 0x9d12,
+ 0x5133, 0x9d0e, 0x512e, 0x9d0b, 0x512a, 0x9d07, 0x5125, 0x9d03,
+ 0x5120, 0x9cff, 0x511b, 0x9cfb, 0x5116, 0x9cf7, 0x5111, 0x9cf3,
+ 0x510c, 0x9cef, 0x5108, 0x9ceb, 0x5103, 0x9ce7, 0x50fe, 0x9ce3,
+ 0x50f9, 0x9cdf, 0x50f4, 0x9cdb, 0x50ef, 0x9cd7, 0x50ea, 0x9cd3,
+ 0x50e5, 0x9ccf, 0x50e1, 0x9ccb, 0x50dc, 0x9cc7, 0x50d7, 0x9cc3,
+ 0x50d2, 0x9cbf, 0x50cd, 0x9cbb, 0x50c8, 0x9cb7, 0x50c3, 0x9cb3,
+ 0x50bf, 0x9caf, 0x50ba, 0x9cab, 0x50b5, 0x9ca7, 0x50b0, 0x9ca3,
+ 0x50ab, 0x9c9f, 0x50a6, 0x9c9b, 0x50a1, 0x9c97, 0x509c, 0x9c93,
+ 0x5097, 0x9c8f, 0x5093, 0x9c8b, 0x508e, 0x9c88, 0x5089, 0x9c84,
+ 0x5084, 0x9c80, 0x507f, 0x9c7c, 0x507a, 0x9c78, 0x5075, 0x9c74,
+ 0x5070, 0x9c70, 0x506c, 0x9c6c, 0x5067, 0x9c68, 0x5062, 0x9c64,
+ 0x505d, 0x9c60, 0x5058, 0x9c5c, 0x5053, 0x9c58, 0x504e, 0x9c54,
+ 0x5049, 0x9c50, 0x5044, 0x9c4c, 0x503f, 0x9c48, 0x503b, 0x9c44,
+ 0x5036, 0x9c40, 0x5031, 0x9c3d, 0x502c, 0x9c39, 0x5027, 0x9c35,
+ 0x5022, 0x9c31, 0x501d, 0x9c2d, 0x5018, 0x9c29, 0x5013, 0x9c25,
+ 0x500f, 0x9c21, 0x500a, 0x9c1d, 0x5005, 0x9c19, 0x5000, 0x9c15,
+ 0x4ffb, 0x9c11, 0x4ff6, 0x9c0d, 0x4ff1, 0x9c09, 0x4fec, 0x9c06,
+ 0x4fe7, 0x9c02, 0x4fe2, 0x9bfe, 0x4fdd, 0x9bfa, 0x4fd9, 0x9bf6,
+ 0x4fd4, 0x9bf2, 0x4fcf, 0x9bee, 0x4fca, 0x9bea, 0x4fc5, 0x9be6,
+ 0x4fc0, 0x9be2, 0x4fbb, 0x9bde, 0x4fb6, 0x9bda, 0x4fb1, 0x9bd7,
+ 0x4fac, 0x9bd3, 0x4fa7, 0x9bcf, 0x4fa2, 0x9bcb, 0x4f9e, 0x9bc7,
+ 0x4f99, 0x9bc3, 0x4f94, 0x9bbf, 0x4f8f, 0x9bbb, 0x4f8a, 0x9bb7,
+ 0x4f85, 0x9bb3, 0x4f80, 0x9baf, 0x4f7b, 0x9bac, 0x4f76, 0x9ba8,
+ 0x4f71, 0x9ba4, 0x4f6c, 0x9ba0, 0x4f67, 0x9b9c, 0x4f62, 0x9b98,
+ 0x4f5e, 0x9b94, 0x4f59, 0x9b90, 0x4f54, 0x9b8c, 0x4f4f, 0x9b88,
+ 0x4f4a, 0x9b85, 0x4f45, 0x9b81, 0x4f40, 0x9b7d, 0x4f3b, 0x9b79,
+ 0x4f36, 0x9b75, 0x4f31, 0x9b71, 0x4f2c, 0x9b6d, 0x4f27, 0x9b69,
+ 0x4f22, 0x9b65, 0x4f1d, 0x9b62, 0x4f18, 0x9b5e, 0x4f14, 0x9b5a,
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+ 0x4177, 0x9203, 0x4172, 0x9200, 0x416d, 0x91fc, 0x4167, 0x91f9,
+ 0x4162, 0x91f6, 0x415c, 0x91f3, 0x4157, 0x91f0, 0x4152, 0x91ec,
+ 0x414c, 0x91e9, 0x4147, 0x91e6, 0x4141, 0x91e3, 0x413c, 0x91e0,
+ 0x4136, 0x91dc, 0x4131, 0x91d9, 0x412c, 0x91d6, 0x4126, 0x91d3,
+ 0x4121, 0x91d0, 0x411b, 0x91cc, 0x4116, 0x91c9, 0x4111, 0x91c6,
+ 0x410b, 0x91c3, 0x4106, 0x91c0, 0x4100, 0x91bc, 0x40fb, 0x91b9,
+ 0x40f6, 0x91b6, 0x40f0, 0x91b3, 0x40eb, 0x91b0, 0x40e5, 0x91ad,
+ 0x40e0, 0x91a9, 0x40da, 0x91a6, 0x40d5, 0x91a3, 0x40d0, 0x91a0,
+ 0x40ca, 0x919d, 0x40c5, 0x9199, 0x40bf, 0x9196, 0x40ba, 0x9193,
+ 0x40b5, 0x9190, 0x40af, 0x918d, 0x40aa, 0x918a, 0x40a4, 0x9186,
+ 0x409f, 0x9183, 0x4099, 0x9180, 0x4094, 0x917d, 0x408f, 0x917a,
+ 0x4089, 0x9177, 0x4084, 0x9173, 0x407e, 0x9170, 0x4079, 0x916d,
+ 0x4073, 0x916a, 0x406e, 0x9167, 0x4069, 0x9164, 0x4063, 0x9160,
+ 0x405e, 0x915d, 0x4058, 0x915a, 0x4053, 0x9157, 0x404d, 0x9154,
+ 0x4048, 0x9151, 0x4043, 0x914d, 0x403d, 0x914a, 0x4038, 0x9147,
+ 0x4032, 0x9144, 0x402d, 0x9141, 0x4027, 0x913e, 0x4022, 0x913a,
+ 0x401d, 0x9137, 0x4017, 0x9134, 0x4012, 0x9131, 0x400c, 0x912e,
+ 0x4007, 0x912b, 0x4001, 0x9128, 0x3ffc, 0x9124, 0x3ff6, 0x9121,
+ 0x3ff1, 0x911e, 0x3fec, 0x911b, 0x3fe6, 0x9118, 0x3fe1, 0x9115,
+ 0x3fdb, 0x9112, 0x3fd6, 0x910f, 0x3fd0, 0x910b, 0x3fcb, 0x9108,
+ 0x3fc5, 0x9105, 0x3fc0, 0x9102, 0x3fbb, 0x90ff, 0x3fb5, 0x90fc,
+ 0x3fb0, 0x90f9, 0x3faa, 0x90f5, 0x3fa5, 0x90f2, 0x3f9f, 0x90ef,
+ 0x3f9a, 0x90ec, 0x3f94, 0x90e9, 0x3f8f, 0x90e6, 0x3f89, 0x90e3,
+ 0x3f84, 0x90e0, 0x3f7f, 0x90dd, 0x3f79, 0x90d9, 0x3f74, 0x90d6,
+ 0x3f6e, 0x90d3, 0x3f69, 0x90d0, 0x3f63, 0x90cd, 0x3f5e, 0x90ca,
+ 0x3f58, 0x90c7, 0x3f53, 0x90c4, 0x3f4d, 0x90c1, 0x3f48, 0x90bd,
+ 0x3f43, 0x90ba, 0x3f3d, 0x90b7, 0x3f38, 0x90b4, 0x3f32, 0x90b1,
+ 0x3f2d, 0x90ae, 0x3f27, 0x90ab, 0x3f22, 0x90a8, 0x3f1c, 0x90a5,
+ 0x3f17, 0x90a1, 0x3f11, 0x909e, 0x3f0c, 0x909b, 0x3f06, 0x9098,
+ 0x3f01, 0x9095, 0x3efb, 0x9092, 0x3ef6, 0x908f, 0x3ef1, 0x908c,
+ 0x3eeb, 0x9089, 0x3ee6, 0x9086, 0x3ee0, 0x9083, 0x3edb, 0x907f,
+ 0x3ed5, 0x907c, 0x3ed0, 0x9079, 0x3eca, 0x9076, 0x3ec5, 0x9073,
+ 0x3ebf, 0x9070, 0x3eba, 0x906d, 0x3eb4, 0x906a, 0x3eaf, 0x9067,
+ 0x3ea9, 0x9064, 0x3ea4, 0x9061, 0x3e9e, 0x905e, 0x3e99, 0x905b,
+ 0x3e93, 0x9057, 0x3e8e, 0x9054, 0x3e88, 0x9051, 0x3e83, 0x904e,
+ 0x3e7d, 0x904b, 0x3e78, 0x9048, 0x3e73, 0x9045, 0x3e6d, 0x9042,
+ 0x3e68, 0x903f, 0x3e62, 0x903c, 0x3e5d, 0x9039, 0x3e57, 0x9036,
+ 0x3e52, 0x9033, 0x3e4c, 0x9030, 0x3e47, 0x902d, 0x3e41, 0x902a,
+ 0x3e3c, 0x9026, 0x3e36, 0x9023, 0x3e31, 0x9020, 0x3e2b, 0x901d,
+ 0x3e26, 0x901a, 0x3e20, 0x9017, 0x3e1b, 0x9014, 0x3e15, 0x9011,
+ 0x3e10, 0x900e, 0x3e0a, 0x900b, 0x3e05, 0x9008, 0x3dff, 0x9005,
+ 0x3dfa, 0x9002, 0x3df4, 0x8fff, 0x3def, 0x8ffc, 0x3de9, 0x8ff9,
+ 0x3de4, 0x8ff6, 0x3dde, 0x8ff3, 0x3dd9, 0x8ff0, 0x3dd3, 0x8fed,
+ 0x3dce, 0x8fea, 0x3dc8, 0x8fe7, 0x3dc3, 0x8fe3, 0x3dbd, 0x8fe0,
+ 0x3db8, 0x8fdd, 0x3db2, 0x8fda, 0x3dad, 0x8fd7, 0x3da7, 0x8fd4,
+ 0x3da2, 0x8fd1, 0x3d9c, 0x8fce, 0x3d97, 0x8fcb, 0x3d91, 0x8fc8,
+ 0x3d8c, 0x8fc5, 0x3d86, 0x8fc2, 0x3d81, 0x8fbf, 0x3d7b, 0x8fbc,
+ 0x3d76, 0x8fb9, 0x3d70, 0x8fb6, 0x3d6b, 0x8fb3, 0x3d65, 0x8fb0,
+ 0x3d60, 0x8fad, 0x3d5a, 0x8faa, 0x3d55, 0x8fa7, 0x3d4f, 0x8fa4,
+ 0x3d49, 0x8fa1, 0x3d44, 0x8f9e, 0x3d3e, 0x8f9b, 0x3d39, 0x8f98,
+ 0x3d33, 0x8f95, 0x3d2e, 0x8f92, 0x3d28, 0x8f8f, 0x3d23, 0x8f8c,
+ 0x3d1d, 0x8f89, 0x3d18, 0x8f86, 0x3d12, 0x8f83, 0x3d0d, 0x8f80,
+ 0x3d07, 0x8f7d, 0x3d02, 0x8f7a, 0x3cfc, 0x8f77, 0x3cf7, 0x8f74,
+ 0x3cf1, 0x8f71, 0x3cec, 0x8f6e, 0x3ce6, 0x8f6b, 0x3ce1, 0x8f68,
+ 0x3cdb, 0x8f65, 0x3cd6, 0x8f62, 0x3cd0, 0x8f5f, 0x3cca, 0x8f5c,
+ 0x3cc5, 0x8f59, 0x3cbf, 0x8f56, 0x3cba, 0x8f53, 0x3cb4, 0x8f50,
+ 0x3caf, 0x8f4d, 0x3ca9, 0x8f4a, 0x3ca4, 0x8f47, 0x3c9e, 0x8f44,
+ 0x3c99, 0x8f41, 0x3c93, 0x8f3e, 0x3c8e, 0x8f3b, 0x3c88, 0x8f38,
+ 0x3c83, 0x8f35, 0x3c7d, 0x8f32, 0x3c77, 0x8f2f, 0x3c72, 0x8f2d,
+ 0x3c6c, 0x8f2a, 0x3c67, 0x8f27, 0x3c61, 0x8f24, 0x3c5c, 0x8f21,
+ 0x3c56, 0x8f1e, 0x3c51, 0x8f1b, 0x3c4b, 0x8f18, 0x3c46, 0x8f15,
+ 0x3c40, 0x8f12, 0x3c3b, 0x8f0f, 0x3c35, 0x8f0c, 0x3c2f, 0x8f09,
+ 0x3c2a, 0x8f06, 0x3c24, 0x8f03, 0x3c1f, 0x8f00, 0x3c19, 0x8efd,
+ 0x3c14, 0x8efa, 0x3c0e, 0x8ef7, 0x3c09, 0x8ef4, 0x3c03, 0x8ef1,
+ 0x3bfd, 0x8eee, 0x3bf8, 0x8eec, 0x3bf2, 0x8ee9, 0x3bed, 0x8ee6,
+ 0x3be7, 0x8ee3, 0x3be2, 0x8ee0, 0x3bdc, 0x8edd, 0x3bd7, 0x8eda,
+ 0x3bd1, 0x8ed7, 0x3bcc, 0x8ed4, 0x3bc6, 0x8ed1, 0x3bc0, 0x8ece,
+ 0x3bbb, 0x8ecb, 0x3bb5, 0x8ec8, 0x3bb0, 0x8ec5, 0x3baa, 0x8ec2,
+ 0x3ba5, 0x8ebf, 0x3b9f, 0x8ebd, 0x3b99, 0x8eba, 0x3b94, 0x8eb7,
+ 0x3b8e, 0x8eb4, 0x3b89, 0x8eb1, 0x3b83, 0x8eae, 0x3b7e, 0x8eab,
+ 0x3b78, 0x8ea8, 0x3b73, 0x8ea5, 0x3b6d, 0x8ea2, 0x3b67, 0x8e9f,
+ 0x3b62, 0x8e9c, 0x3b5c, 0x8e99, 0x3b57, 0x8e97, 0x3b51, 0x8e94,
+ 0x3b4c, 0x8e91, 0x3b46, 0x8e8e, 0x3b40, 0x8e8b, 0x3b3b, 0x8e88,
+ 0x3b35, 0x8e85, 0x3b30, 0x8e82, 0x3b2a, 0x8e7f, 0x3b25, 0x8e7c,
+ 0x3b1f, 0x8e7a, 0x3b19, 0x8e77, 0x3b14, 0x8e74, 0x3b0e, 0x8e71,
+ 0x3b09, 0x8e6e, 0x3b03, 0x8e6b, 0x3afe, 0x8e68, 0x3af8, 0x8e65,
+ 0x3af2, 0x8e62, 0x3aed, 0x8e5f, 0x3ae7, 0x8e5d, 0x3ae2, 0x8e5a,
+ 0x3adc, 0x8e57, 0x3ad7, 0x8e54, 0x3ad1, 0x8e51, 0x3acb, 0x8e4e,
+ 0x3ac6, 0x8e4b, 0x3ac0, 0x8e48, 0x3abb, 0x8e45, 0x3ab5, 0x8e43,
+ 0x3aaf, 0x8e40, 0x3aaa, 0x8e3d, 0x3aa4, 0x8e3a, 0x3a9f, 0x8e37,
+ 0x3a99, 0x8e34, 0x3a94, 0x8e31, 0x3a8e, 0x8e2e, 0x3a88, 0x8e2c,
+ 0x3a83, 0x8e29, 0x3a7d, 0x8e26, 0x3a78, 0x8e23, 0x3a72, 0x8e20,
+ 0x3a6c, 0x8e1d, 0x3a67, 0x8e1a, 0x3a61, 0x8e17, 0x3a5c, 0x8e15,
+ 0x3a56, 0x8e12, 0x3a50, 0x8e0f, 0x3a4b, 0x8e0c, 0x3a45, 0x8e09,
+ 0x3a40, 0x8e06, 0x3a3a, 0x8e03, 0x3a34, 0x8e01, 0x3a2f, 0x8dfe,
+ 0x3a29, 0x8dfb, 0x3a24, 0x8df8, 0x3a1e, 0x8df5, 0x3a19, 0x8df2,
+ 0x3a13, 0x8def, 0x3a0d, 0x8ded, 0x3a08, 0x8dea, 0x3a02, 0x8de7,
+ 0x39fd, 0x8de4, 0x39f7, 0x8de1, 0x39f1, 0x8dde, 0x39ec, 0x8ddc,
+ 0x39e6, 0x8dd9, 0x39e0, 0x8dd6, 0x39db, 0x8dd3, 0x39d5, 0x8dd0,
+ 0x39d0, 0x8dcd, 0x39ca, 0x8dca, 0x39c4, 0x8dc8, 0x39bf, 0x8dc5,
+ 0x39b9, 0x8dc2, 0x39b4, 0x8dbf, 0x39ae, 0x8dbc, 0x39a8, 0x8db9,
+ 0x39a3, 0x8db7, 0x399d, 0x8db4, 0x3998, 0x8db1, 0x3992, 0x8dae,
+ 0x398c, 0x8dab, 0x3987, 0x8da9, 0x3981, 0x8da6, 0x397c, 0x8da3,
+ 0x3976, 0x8da0, 0x3970, 0x8d9d, 0x396b, 0x8d9a, 0x3965, 0x8d98,
+ 0x395f, 0x8d95, 0x395a, 0x8d92, 0x3954, 0x8d8f, 0x394f, 0x8d8c,
+ 0x3949, 0x8d8a, 0x3943, 0x8d87, 0x393e, 0x8d84, 0x3938, 0x8d81,
+ 0x3932, 0x8d7e, 0x392d, 0x8d7b, 0x3927, 0x8d79, 0x3922, 0x8d76,
+ 0x391c, 0x8d73, 0x3916, 0x8d70, 0x3911, 0x8d6d, 0x390b, 0x8d6b,
+ 0x3906, 0x8d68, 0x3900, 0x8d65, 0x38fa, 0x8d62, 0x38f5, 0x8d5f,
+ 0x38ef, 0x8d5d, 0x38e9, 0x8d5a, 0x38e4, 0x8d57, 0x38de, 0x8d54,
+ 0x38d8, 0x8d51, 0x38d3, 0x8d4f, 0x38cd, 0x8d4c, 0x38c8, 0x8d49,
+ 0x38c2, 0x8d46, 0x38bc, 0x8d44, 0x38b7, 0x8d41, 0x38b1, 0x8d3e,
+ 0x38ab, 0x8d3b, 0x38a6, 0x8d38, 0x38a0, 0x8d36, 0x389b, 0x8d33,
+ 0x3895, 0x8d30, 0x388f, 0x8d2d, 0x388a, 0x8d2b, 0x3884, 0x8d28,
+ 0x387e, 0x8d25, 0x3879, 0x8d22, 0x3873, 0x8d1f, 0x386d, 0x8d1d,
+ 0x3868, 0x8d1a, 0x3862, 0x8d17, 0x385d, 0x8d14, 0x3857, 0x8d12,
+ 0x3851, 0x8d0f, 0x384c, 0x8d0c, 0x3846, 0x8d09, 0x3840, 0x8d07,
+ 0x383b, 0x8d04, 0x3835, 0x8d01, 0x382f, 0x8cfe, 0x382a, 0x8cfb,
+ 0x3824, 0x8cf9, 0x381e, 0x8cf6, 0x3819, 0x8cf3, 0x3813, 0x8cf0,
+ 0x380d, 0x8cee, 0x3808, 0x8ceb, 0x3802, 0x8ce8, 0x37fd, 0x8ce5,
+ 0x37f7, 0x8ce3, 0x37f1, 0x8ce0, 0x37ec, 0x8cdd, 0x37e6, 0x8cda,
+ 0x37e0, 0x8cd8, 0x37db, 0x8cd5, 0x37d5, 0x8cd2, 0x37cf, 0x8cd0,
+ 0x37ca, 0x8ccd, 0x37c4, 0x8cca, 0x37be, 0x8cc7, 0x37b9, 0x8cc5,
+ 0x37b3, 0x8cc2, 0x37ad, 0x8cbf, 0x37a8, 0x8cbc, 0x37a2, 0x8cba,
+ 0x379c, 0x8cb7, 0x3797, 0x8cb4, 0x3791, 0x8cb1, 0x378b, 0x8caf,
+ 0x3786, 0x8cac, 0x3780, 0x8ca9, 0x377a, 0x8ca7, 0x3775, 0x8ca4,
+ 0x376f, 0x8ca1, 0x3769, 0x8c9e, 0x3764, 0x8c9c, 0x375e, 0x8c99,
+ 0x3758, 0x8c96, 0x3753, 0x8c94, 0x374d, 0x8c91, 0x3747, 0x8c8e,
+ 0x3742, 0x8c8b, 0x373c, 0x8c89, 0x3736, 0x8c86, 0x3731, 0x8c83,
+ 0x372b, 0x8c81, 0x3725, 0x8c7e, 0x3720, 0x8c7b, 0x371a, 0x8c78,
+ 0x3714, 0x8c76, 0x370f, 0x8c73, 0x3709, 0x8c70, 0x3703, 0x8c6e,
+ 0x36fe, 0x8c6b, 0x36f8, 0x8c68, 0x36f2, 0x8c65, 0x36ed, 0x8c63,
+ 0x36e7, 0x8c60, 0x36e1, 0x8c5d, 0x36dc, 0x8c5b, 0x36d6, 0x8c58,
+ 0x36d0, 0x8c55, 0x36cb, 0x8c53, 0x36c5, 0x8c50, 0x36bf, 0x8c4d,
+ 0x36ba, 0x8c4b, 0x36b4, 0x8c48, 0x36ae, 0x8c45, 0x36a9, 0x8c43,
+ 0x36a3, 0x8c40, 0x369d, 0x8c3d, 0x3698, 0x8c3a, 0x3692, 0x8c38,
+ 0x368c, 0x8c35, 0x3686, 0x8c32, 0x3681, 0x8c30, 0x367b, 0x8c2d,
+ 0x3675, 0x8c2a, 0x3670, 0x8c28, 0x366a, 0x8c25, 0x3664, 0x8c22,
+ 0x365f, 0x8c20, 0x3659, 0x8c1d, 0x3653, 0x8c1a, 0x364e, 0x8c18,
+ 0x3648, 0x8c15, 0x3642, 0x8c12, 0x363d, 0x8c10, 0x3637, 0x8c0d,
+ 0x3631, 0x8c0a, 0x362b, 0x8c08, 0x3626, 0x8c05, 0x3620, 0x8c02,
+ 0x361a, 0x8c00, 0x3615, 0x8bfd, 0x360f, 0x8bfa, 0x3609, 0x8bf8,
+ 0x3604, 0x8bf5, 0x35fe, 0x8bf3, 0x35f8, 0x8bf0, 0x35f3, 0x8bed,
+ 0x35ed, 0x8beb, 0x35e7, 0x8be8, 0x35e1, 0x8be5, 0x35dc, 0x8be3,
+ 0x35d6, 0x8be0, 0x35d0, 0x8bdd, 0x35cb, 0x8bdb, 0x35c5, 0x8bd8,
+ 0x35bf, 0x8bd5, 0x35ba, 0x8bd3, 0x35b4, 0x8bd0, 0x35ae, 0x8bce,
+ 0x35a8, 0x8bcb, 0x35a3, 0x8bc8, 0x359d, 0x8bc6, 0x3597, 0x8bc3,
+ 0x3592, 0x8bc0, 0x358c, 0x8bbe, 0x3586, 0x8bbb, 0x3580, 0x8bb8,
+ 0x357b, 0x8bb6, 0x3575, 0x8bb3, 0x356f, 0x8bb1, 0x356a, 0x8bae,
+ 0x3564, 0x8bab, 0x355e, 0x8ba9, 0x3558, 0x8ba6, 0x3553, 0x8ba4,
+ 0x354d, 0x8ba1, 0x3547, 0x8b9e, 0x3542, 0x8b9c, 0x353c, 0x8b99,
+ 0x3536, 0x8b96, 0x3530, 0x8b94, 0x352b, 0x8b91, 0x3525, 0x8b8f,
+ 0x351f, 0x8b8c, 0x351a, 0x8b89, 0x3514, 0x8b87, 0x350e, 0x8b84,
+ 0x3508, 0x8b82, 0x3503, 0x8b7f, 0x34fd, 0x8b7c, 0x34f7, 0x8b7a,
+ 0x34f2, 0x8b77, 0x34ec, 0x8b75, 0x34e6, 0x8b72, 0x34e0, 0x8b6f,
+ 0x34db, 0x8b6d, 0x34d5, 0x8b6a, 0x34cf, 0x8b68, 0x34ca, 0x8b65,
+ 0x34c4, 0x8b62, 0x34be, 0x8b60, 0x34b8, 0x8b5d, 0x34b3, 0x8b5b,
+ 0x34ad, 0x8b58, 0x34a7, 0x8b55, 0x34a1, 0x8b53, 0x349c, 0x8b50,
+ 0x3496, 0x8b4e, 0x3490, 0x8b4b, 0x348b, 0x8b49, 0x3485, 0x8b46,
+ 0x347f, 0x8b43, 0x3479, 0x8b41, 0x3474, 0x8b3e, 0x346e, 0x8b3c,
+ 0x3468, 0x8b39, 0x3462, 0x8b37, 0x345d, 0x8b34, 0x3457, 0x8b31,
+ 0x3451, 0x8b2f, 0x344b, 0x8b2c, 0x3446, 0x8b2a, 0x3440, 0x8b27,
+ 0x343a, 0x8b25, 0x3435, 0x8b22, 0x342f, 0x8b1f, 0x3429, 0x8b1d,
+ 0x3423, 0x8b1a, 0x341e, 0x8b18, 0x3418, 0x8b15, 0x3412, 0x8b13,
+ 0x340c, 0x8b10, 0x3407, 0x8b0e, 0x3401, 0x8b0b, 0x33fb, 0x8b08,
+ 0x33f5, 0x8b06, 0x33f0, 0x8b03, 0x33ea, 0x8b01, 0x33e4, 0x8afe,
+ 0x33de, 0x8afc, 0x33d9, 0x8af9, 0x33d3, 0x8af7, 0x33cd, 0x8af4,
+ 0x33c7, 0x8af1, 0x33c2, 0x8aef, 0x33bc, 0x8aec, 0x33b6, 0x8aea,
+ 0x33b0, 0x8ae7, 0x33ab, 0x8ae5, 0x33a5, 0x8ae2, 0x339f, 0x8ae0,
+ 0x3399, 0x8add, 0x3394, 0x8adb, 0x338e, 0x8ad8, 0x3388, 0x8ad6,
+ 0x3382, 0x8ad3, 0x337d, 0x8ad1, 0x3377, 0x8ace, 0x3371, 0x8acb,
+ 0x336b, 0x8ac9, 0x3366, 0x8ac6, 0x3360, 0x8ac4, 0x335a, 0x8ac1,
+ 0x3354, 0x8abf, 0x334f, 0x8abc, 0x3349, 0x8aba, 0x3343, 0x8ab7,
+ 0x333d, 0x8ab5, 0x3338, 0x8ab2, 0x3332, 0x8ab0, 0x332c, 0x8aad,
+ 0x3326, 0x8aab, 0x3321, 0x8aa8, 0x331b, 0x8aa6, 0x3315, 0x8aa3,
+ 0x330f, 0x8aa1, 0x330a, 0x8a9e, 0x3304, 0x8a9c, 0x32fe, 0x8a99,
+ 0x32f8, 0x8a97, 0x32f3, 0x8a94, 0x32ed, 0x8a92, 0x32e7, 0x8a8f,
+ 0x32e1, 0x8a8d, 0x32db, 0x8a8a, 0x32d6, 0x8a88, 0x32d0, 0x8a85,
+ 0x32ca, 0x8a83, 0x32c4, 0x8a80, 0x32bf, 0x8a7e, 0x32b9, 0x8a7b,
+ 0x32b3, 0x8a79, 0x32ad, 0x8a76, 0x32a8, 0x8a74, 0x32a2, 0x8a71,
+ 0x329c, 0x8a6f, 0x3296, 0x8a6c, 0x3290, 0x8a6a, 0x328b, 0x8a67,
+ 0x3285, 0x8a65, 0x327f, 0x8a62, 0x3279, 0x8a60, 0x3274, 0x8a5d,
+ 0x326e, 0x8a5b, 0x3268, 0x8a59, 0x3262, 0x8a56, 0x325d, 0x8a54,
+ 0x3257, 0x8a51, 0x3251, 0x8a4f, 0x324b, 0x8a4c, 0x3245, 0x8a4a,
+ 0x3240, 0x8a47, 0x323a, 0x8a45, 0x3234, 0x8a42, 0x322e, 0x8a40,
+ 0x3228, 0x8a3d, 0x3223, 0x8a3b, 0x321d, 0x8a38, 0x3217, 0x8a36,
+ 0x3211, 0x8a34, 0x320c, 0x8a31, 0x3206, 0x8a2f, 0x3200, 0x8a2c,
+ 0x31fa, 0x8a2a, 0x31f4, 0x8a27, 0x31ef, 0x8a25, 0x31e9, 0x8a22,
+ 0x31e3, 0x8a20, 0x31dd, 0x8a1d, 0x31d8, 0x8a1b, 0x31d2, 0x8a19,
+ 0x31cc, 0x8a16, 0x31c6, 0x8a14, 0x31c0, 0x8a11, 0x31bb, 0x8a0f,
+ 0x31b5, 0x8a0c, 0x31af, 0x8a0a, 0x31a9, 0x8a07, 0x31a3, 0x8a05,
+ 0x319e, 0x8a03, 0x3198, 0x8a00, 0x3192, 0x89fe, 0x318c, 0x89fb,
+ 0x3186, 0x89f9, 0x3181, 0x89f6, 0x317b, 0x89f4, 0x3175, 0x89f2,
+ 0x316f, 0x89ef, 0x3169, 0x89ed, 0x3164, 0x89ea, 0x315e, 0x89e8,
+ 0x3158, 0x89e5, 0x3152, 0x89e3, 0x314c, 0x89e1, 0x3147, 0x89de,
+ 0x3141, 0x89dc, 0x313b, 0x89d9, 0x3135, 0x89d7, 0x312f, 0x89d5,
+ 0x312a, 0x89d2, 0x3124, 0x89d0, 0x311e, 0x89cd, 0x3118, 0x89cb,
+ 0x3112, 0x89c8, 0x310d, 0x89c6, 0x3107, 0x89c4, 0x3101, 0x89c1,
+ 0x30fb, 0x89bf, 0x30f5, 0x89bc, 0x30f0, 0x89ba, 0x30ea, 0x89b8,
+ 0x30e4, 0x89b5, 0x30de, 0x89b3, 0x30d8, 0x89b0, 0x30d3, 0x89ae,
+ 0x30cd, 0x89ac, 0x30c7, 0x89a9, 0x30c1, 0x89a7, 0x30bb, 0x89a4,
+ 0x30b6, 0x89a2, 0x30b0, 0x89a0, 0x30aa, 0x899d, 0x30a4, 0x899b,
+ 0x309e, 0x8998, 0x3099, 0x8996, 0x3093, 0x8994, 0x308d, 0x8991,
+ 0x3087, 0x898f, 0x3081, 0x898d, 0x307b, 0x898a, 0x3076, 0x8988,
+ 0x3070, 0x8985, 0x306a, 0x8983, 0x3064, 0x8981, 0x305e, 0x897e,
+ 0x3059, 0x897c, 0x3053, 0x897a, 0x304d, 0x8977, 0x3047, 0x8975,
+ 0x3041, 0x8972, 0x303b, 0x8970, 0x3036, 0x896e, 0x3030, 0x896b,
+ 0x302a, 0x8969, 0x3024, 0x8967, 0x301e, 0x8964, 0x3019, 0x8962,
+ 0x3013, 0x8960, 0x300d, 0x895d, 0x3007, 0x895b, 0x3001, 0x8958,
+ 0x2ffb, 0x8956, 0x2ff6, 0x8954, 0x2ff0, 0x8951, 0x2fea, 0x894f,
+ 0x2fe4, 0x894d, 0x2fde, 0x894a, 0x2fd8, 0x8948, 0x2fd3, 0x8946,
+ 0x2fcd, 0x8943, 0x2fc7, 0x8941, 0x2fc1, 0x893f, 0x2fbb, 0x893c,
+ 0x2fb5, 0x893a, 0x2fb0, 0x8938, 0x2faa, 0x8935, 0x2fa4, 0x8933,
+ 0x2f9e, 0x8931, 0x2f98, 0x892e, 0x2f92, 0x892c, 0x2f8d, 0x892a,
+ 0x2f87, 0x8927, 0x2f81, 0x8925, 0x2f7b, 0x8923, 0x2f75, 0x8920,
+ 0x2f6f, 0x891e, 0x2f6a, 0x891c, 0x2f64, 0x8919, 0x2f5e, 0x8917,
+ 0x2f58, 0x8915, 0x2f52, 0x8912, 0x2f4c, 0x8910, 0x2f47, 0x890e,
+ 0x2f41, 0x890b, 0x2f3b, 0x8909, 0x2f35, 0x8907, 0x2f2f, 0x8904,
+ 0x2f29, 0x8902, 0x2f24, 0x8900, 0x2f1e, 0x88fd, 0x2f18, 0x88fb,
+ 0x2f12, 0x88f9, 0x2f0c, 0x88f6, 0x2f06, 0x88f4, 0x2f01, 0x88f2,
+ 0x2efb, 0x88f0, 0x2ef5, 0x88ed, 0x2eef, 0x88eb, 0x2ee9, 0x88e9,
+ 0x2ee3, 0x88e6, 0x2edd, 0x88e4, 0x2ed8, 0x88e2, 0x2ed2, 0x88df,
+ 0x2ecc, 0x88dd, 0x2ec6, 0x88db, 0x2ec0, 0x88d9, 0x2eba, 0x88d6,
+ 0x2eb5, 0x88d4, 0x2eaf, 0x88d2, 0x2ea9, 0x88cf, 0x2ea3, 0x88cd,
+ 0x2e9d, 0x88cb, 0x2e97, 0x88c8, 0x2e91, 0x88c6, 0x2e8c, 0x88c4,
+ 0x2e86, 0x88c2, 0x2e80, 0x88bf, 0x2e7a, 0x88bd, 0x2e74, 0x88bb,
+ 0x2e6e, 0x88b9, 0x2e68, 0x88b6, 0x2e63, 0x88b4, 0x2e5d, 0x88b2,
+ 0x2e57, 0x88af, 0x2e51, 0x88ad, 0x2e4b, 0x88ab, 0x2e45, 0x88a9,
+ 0x2e3f, 0x88a6, 0x2e3a, 0x88a4, 0x2e34, 0x88a2, 0x2e2e, 0x88a0,
+ 0x2e28, 0x889d, 0x2e22, 0x889b, 0x2e1c, 0x8899, 0x2e16, 0x8896,
+ 0x2e11, 0x8894, 0x2e0b, 0x8892, 0x2e05, 0x8890, 0x2dff, 0x888d,
+ 0x2df9, 0x888b, 0x2df3, 0x8889, 0x2ded, 0x8887, 0x2de7, 0x8884,
+ 0x2de2, 0x8882, 0x2ddc, 0x8880, 0x2dd6, 0x887e, 0x2dd0, 0x887b,
+ 0x2dca, 0x8879, 0x2dc4, 0x8877, 0x2dbe, 0x8875, 0x2db9, 0x8872,
+ 0x2db3, 0x8870, 0x2dad, 0x886e, 0x2da7, 0x886c, 0x2da1, 0x8869,
+ 0x2d9b, 0x8867, 0x2d95, 0x8865, 0x2d8f, 0x8863, 0x2d8a, 0x8860,
+ 0x2d84, 0x885e, 0x2d7e, 0x885c, 0x2d78, 0x885a, 0x2d72, 0x8858,
+ 0x2d6c, 0x8855, 0x2d66, 0x8853, 0x2d60, 0x8851, 0x2d5b, 0x884f,
+ 0x2d55, 0x884c, 0x2d4f, 0x884a, 0x2d49, 0x8848, 0x2d43, 0x8846,
+ 0x2d3d, 0x8844, 0x2d37, 0x8841, 0x2d31, 0x883f, 0x2d2c, 0x883d,
+ 0x2d26, 0x883b, 0x2d20, 0x8838, 0x2d1a, 0x8836, 0x2d14, 0x8834,
+ 0x2d0e, 0x8832, 0x2d08, 0x8830, 0x2d02, 0x882d, 0x2cfd, 0x882b,
+ 0x2cf7, 0x8829, 0x2cf1, 0x8827, 0x2ceb, 0x8825, 0x2ce5, 0x8822,
+ 0x2cdf, 0x8820, 0x2cd9, 0x881e, 0x2cd3, 0x881c, 0x2ccd, 0x881a,
+ 0x2cc8, 0x8817, 0x2cc2, 0x8815, 0x2cbc, 0x8813, 0x2cb6, 0x8811,
+ 0x2cb0, 0x880f, 0x2caa, 0x880c, 0x2ca4, 0x880a, 0x2c9e, 0x8808,
+ 0x2c98, 0x8806, 0x2c93, 0x8804, 0x2c8d, 0x8801, 0x2c87, 0x87ff,
+ 0x2c81, 0x87fd, 0x2c7b, 0x87fb, 0x2c75, 0x87f9, 0x2c6f, 0x87f6,
+ 0x2c69, 0x87f4, 0x2c63, 0x87f2, 0x2c5e, 0x87f0, 0x2c58, 0x87ee,
+ 0x2c52, 0x87ec, 0x2c4c, 0x87e9, 0x2c46, 0x87e7, 0x2c40, 0x87e5,
+ 0x2c3a, 0x87e3, 0x2c34, 0x87e1, 0x2c2e, 0x87df, 0x2c29, 0x87dc,
+ 0x2c23, 0x87da, 0x2c1d, 0x87d8, 0x2c17, 0x87d6, 0x2c11, 0x87d4,
+ 0x2c0b, 0x87d2, 0x2c05, 0x87cf, 0x2bff, 0x87cd, 0x2bf9, 0x87cb,
+ 0x2bf3, 0x87c9, 0x2bee, 0x87c7, 0x2be8, 0x87c5, 0x2be2, 0x87c2,
+ 0x2bdc, 0x87c0, 0x2bd6, 0x87be, 0x2bd0, 0x87bc, 0x2bca, 0x87ba,
+ 0x2bc4, 0x87b8, 0x2bbe, 0x87b6, 0x2bb8, 0x87b3, 0x2bb2, 0x87b1,
+ 0x2bad, 0x87af, 0x2ba7, 0x87ad, 0x2ba1, 0x87ab, 0x2b9b, 0x87a9,
+ 0x2b95, 0x87a7, 0x2b8f, 0x87a4, 0x2b89, 0x87a2, 0x2b83, 0x87a0,
+ 0x2b7d, 0x879e, 0x2b77, 0x879c, 0x2b71, 0x879a, 0x2b6c, 0x8798,
+ 0x2b66, 0x8795, 0x2b60, 0x8793, 0x2b5a, 0x8791, 0x2b54, 0x878f,
+ 0x2b4e, 0x878d, 0x2b48, 0x878b, 0x2b42, 0x8789, 0x2b3c, 0x8787,
+ 0x2b36, 0x8784, 0x2b30, 0x8782, 0x2b2b, 0x8780, 0x2b25, 0x877e,
+ 0x2b1f, 0x877c, 0x2b19, 0x877a, 0x2b13, 0x8778, 0x2b0d, 0x8776,
+ 0x2b07, 0x8774, 0x2b01, 0x8771, 0x2afb, 0x876f, 0x2af5, 0x876d,
+ 0x2aef, 0x876b, 0x2ae9, 0x8769, 0x2ae4, 0x8767, 0x2ade, 0x8765,
+ 0x2ad8, 0x8763, 0x2ad2, 0x8761, 0x2acc, 0x875e, 0x2ac6, 0x875c,
+ 0x2ac0, 0x875a, 0x2aba, 0x8758, 0x2ab4, 0x8756, 0x2aae, 0x8754,
+ 0x2aa8, 0x8752, 0x2aa2, 0x8750, 0x2a9c, 0x874e, 0x2a97, 0x874c,
+ 0x2a91, 0x874a, 0x2a8b, 0x8747, 0x2a85, 0x8745, 0x2a7f, 0x8743,
+ 0x2a79, 0x8741, 0x2a73, 0x873f, 0x2a6d, 0x873d, 0x2a67, 0x873b,
+ 0x2a61, 0x8739, 0x2a5b, 0x8737, 0x2a55, 0x8735, 0x2a4f, 0x8733,
+ 0x2a49, 0x8731, 0x2a44, 0x872e, 0x2a3e, 0x872c, 0x2a38, 0x872a,
+ 0x2a32, 0x8728, 0x2a2c, 0x8726, 0x2a26, 0x8724, 0x2a20, 0x8722,
+ 0x2a1a, 0x8720, 0x2a14, 0x871e, 0x2a0e, 0x871c, 0x2a08, 0x871a,
+ 0x2a02, 0x8718, 0x29fc, 0x8716, 0x29f6, 0x8714, 0x29f0, 0x8712,
+ 0x29eb, 0x870f, 0x29e5, 0x870d, 0x29df, 0x870b, 0x29d9, 0x8709,
+ 0x29d3, 0x8707, 0x29cd, 0x8705, 0x29c7, 0x8703, 0x29c1, 0x8701,
+ 0x29bb, 0x86ff, 0x29b5, 0x86fd, 0x29af, 0x86fb, 0x29a9, 0x86f9,
+ 0x29a3, 0x86f7, 0x299d, 0x86f5, 0x2997, 0x86f3, 0x2991, 0x86f1,
+ 0x298b, 0x86ef, 0x2986, 0x86ed, 0x2980, 0x86eb, 0x297a, 0x86e9,
+ 0x2974, 0x86e7, 0x296e, 0x86e4, 0x2968, 0x86e2, 0x2962, 0x86e0,
+ 0x295c, 0x86de, 0x2956, 0x86dc, 0x2950, 0x86da, 0x294a, 0x86d8,
+ 0x2944, 0x86d6, 0x293e, 0x86d4, 0x2938, 0x86d2, 0x2932, 0x86d0,
+ 0x292c, 0x86ce, 0x2926, 0x86cc, 0x2920, 0x86ca, 0x291b, 0x86c8,
+ 0x2915, 0x86c6, 0x290f, 0x86c4, 0x2909, 0x86c2, 0x2903, 0x86c0,
+ 0x28fd, 0x86be, 0x28f7, 0x86bc, 0x28f1, 0x86ba, 0x28eb, 0x86b8,
+ 0x28e5, 0x86b6, 0x28df, 0x86b4, 0x28d9, 0x86b2, 0x28d3, 0x86b0,
+ 0x28cd, 0x86ae, 0x28c7, 0x86ac, 0x28c1, 0x86aa, 0x28bb, 0x86a8,
+ 0x28b5, 0x86a6, 0x28af, 0x86a4, 0x28a9, 0x86a2, 0x28a3, 0x86a0,
+ 0x289d, 0x869e, 0x2898, 0x869c, 0x2892, 0x869a, 0x288c, 0x8698,
+ 0x2886, 0x8696, 0x2880, 0x8694, 0x287a, 0x8692, 0x2874, 0x8690,
+ 0x286e, 0x868e, 0x2868, 0x868c, 0x2862, 0x868a, 0x285c, 0x8688,
+ 0x2856, 0x8686, 0x2850, 0x8684, 0x284a, 0x8682, 0x2844, 0x8680,
+ 0x283e, 0x867e, 0x2838, 0x867c, 0x2832, 0x867a, 0x282c, 0x8678,
+ 0x2826, 0x8676, 0x2820, 0x8674, 0x281a, 0x8672, 0x2814, 0x8670,
+ 0x280e, 0x866e, 0x2808, 0x866d, 0x2802, 0x866b, 0x27fc, 0x8669,
+ 0x27f6, 0x8667, 0x27f1, 0x8665, 0x27eb, 0x8663, 0x27e5, 0x8661,
+ 0x27df, 0x865f, 0x27d9, 0x865d, 0x27d3, 0x865b, 0x27cd, 0x8659,
+ 0x27c7, 0x8657, 0x27c1, 0x8655, 0x27bb, 0x8653, 0x27b5, 0x8651,
+ 0x27af, 0x864f, 0x27a9, 0x864d, 0x27a3, 0x864b, 0x279d, 0x8649,
+ 0x2797, 0x8647, 0x2791, 0x8645, 0x278b, 0x8644, 0x2785, 0x8642,
+ 0x277f, 0x8640, 0x2779, 0x863e, 0x2773, 0x863c, 0x276d, 0x863a,
+ 0x2767, 0x8638, 0x2761, 0x8636, 0x275b, 0x8634, 0x2755, 0x8632,
+ 0x274f, 0x8630, 0x2749, 0x862e, 0x2743, 0x862c, 0x273d, 0x862a,
+ 0x2737, 0x8628, 0x2731, 0x8627, 0x272b, 0x8625, 0x2725, 0x8623,
+ 0x271f, 0x8621, 0x2719, 0x861f, 0x2713, 0x861d, 0x270d, 0x861b,
+ 0x2707, 0x8619, 0x2701, 0x8617, 0x26fb, 0x8615, 0x26f5, 0x8613,
+ 0x26ef, 0x8611, 0x26e9, 0x8610, 0x26e4, 0x860e, 0x26de, 0x860c,
+ 0x26d8, 0x860a, 0x26d2, 0x8608, 0x26cc, 0x8606, 0x26c6, 0x8604,
+ 0x26c0, 0x8602, 0x26ba, 0x8600, 0x26b4, 0x85fe, 0x26ae, 0x85fc,
+ 0x26a8, 0x85fb, 0x26a2, 0x85f9, 0x269c, 0x85f7, 0x2696, 0x85f5,
+ 0x2690, 0x85f3, 0x268a, 0x85f1, 0x2684, 0x85ef, 0x267e, 0x85ed,
+ 0x2678, 0x85eb, 0x2672, 0x85ea, 0x266c, 0x85e8, 0x2666, 0x85e6,
+ 0x2660, 0x85e4, 0x265a, 0x85e2, 0x2654, 0x85e0, 0x264e, 0x85de,
+ 0x2648, 0x85dc, 0x2642, 0x85da, 0x263c, 0x85d9, 0x2636, 0x85d7,
+ 0x2630, 0x85d5, 0x262a, 0x85d3, 0x2624, 0x85d1, 0x261e, 0x85cf,
+ 0x2618, 0x85cd, 0x2612, 0x85cb, 0x260c, 0x85ca, 0x2606, 0x85c8,
+ 0x2600, 0x85c6, 0x25fa, 0x85c4, 0x25f4, 0x85c2, 0x25ee, 0x85c0,
+ 0x25e8, 0x85be, 0x25e2, 0x85bd, 0x25dc, 0x85bb, 0x25d6, 0x85b9,
+ 0x25d0, 0x85b7, 0x25ca, 0x85b5, 0x25c4, 0x85b3, 0x25be, 0x85b1,
+ 0x25b8, 0x85b0, 0x25b2, 0x85ae, 0x25ac, 0x85ac, 0x25a6, 0x85aa,
+ 0x25a0, 0x85a8, 0x259a, 0x85a6, 0x2594, 0x85a4, 0x258e, 0x85a3,
+ 0x2588, 0x85a1, 0x2582, 0x859f, 0x257c, 0x859d, 0x2576, 0x859b,
+ 0x2570, 0x8599, 0x256a, 0x8598, 0x2564, 0x8596, 0x255e, 0x8594,
+ 0x2558, 0x8592, 0x2552, 0x8590, 0x254c, 0x858e, 0x2546, 0x858d,
+ 0x2540, 0x858b, 0x253a, 0x8589, 0x2534, 0x8587, 0x252e, 0x8585,
+ 0x2528, 0x8583, 0x2522, 0x8582, 0x251c, 0x8580, 0x2516, 0x857e,
+ 0x250f, 0x857c, 0x2509, 0x857a, 0x2503, 0x8579, 0x24fd, 0x8577,
+ 0x24f7, 0x8575, 0x24f1, 0x8573, 0x24eb, 0x8571, 0x24e5, 0x856f,
+ 0x24df, 0x856e, 0x24d9, 0x856c, 0x24d3, 0x856a, 0x24cd, 0x8568,
+ 0x24c7, 0x8566, 0x24c1, 0x8565, 0x24bb, 0x8563, 0x24b5, 0x8561,
+ 0x24af, 0x855f, 0x24a9, 0x855d, 0x24a3, 0x855c, 0x249d, 0x855a,
+ 0x2497, 0x8558, 0x2491, 0x8556, 0x248b, 0x8554, 0x2485, 0x8553,
+ 0x247f, 0x8551, 0x2479, 0x854f, 0x2473, 0x854d, 0x246d, 0x854b,
+ 0x2467, 0x854a, 0x2461, 0x8548, 0x245b, 0x8546, 0x2455, 0x8544,
+ 0x244f, 0x8543, 0x2449, 0x8541, 0x2443, 0x853f, 0x243d, 0x853d,
+ 0x2437, 0x853b, 0x2431, 0x853a, 0x242b, 0x8538, 0x2425, 0x8536,
+ 0x241f, 0x8534, 0x2419, 0x8533, 0x2413, 0x8531, 0x240d, 0x852f,
+ 0x2407, 0x852d, 0x2401, 0x852b, 0x23fa, 0x852a, 0x23f4, 0x8528,
+ 0x23ee, 0x8526, 0x23e8, 0x8524, 0x23e2, 0x8523, 0x23dc, 0x8521,
+ 0x23d6, 0x851f, 0x23d0, 0x851d, 0x23ca, 0x851c, 0x23c4, 0x851a,
+ 0x23be, 0x8518, 0x23b8, 0x8516, 0x23b2, 0x8515, 0x23ac, 0x8513,
+ 0x23a6, 0x8511, 0x23a0, 0x850f, 0x239a, 0x850e, 0x2394, 0x850c,
+ 0x238e, 0x850a, 0x2388, 0x8508, 0x2382, 0x8507, 0x237c, 0x8505,
+ 0x2376, 0x8503, 0x2370, 0x8501, 0x236a, 0x8500, 0x2364, 0x84fe,
+ 0x235e, 0x84fc, 0x2358, 0x84fa, 0x2352, 0x84f9, 0x234b, 0x84f7,
+ 0x2345, 0x84f5, 0x233f, 0x84f4, 0x2339, 0x84f2, 0x2333, 0x84f0,
+ 0x232d, 0x84ee, 0x2327, 0x84ed, 0x2321, 0x84eb, 0x231b, 0x84e9,
+ 0x2315, 0x84e7, 0x230f, 0x84e6, 0x2309, 0x84e4, 0x2303, 0x84e2,
+ 0x22fd, 0x84e1, 0x22f7, 0x84df, 0x22f1, 0x84dd, 0x22eb, 0x84db,
+ 0x22e5, 0x84da, 0x22df, 0x84d8, 0x22d9, 0x84d6, 0x22d3, 0x84d5,
+ 0x22cd, 0x84d3, 0x22c7, 0x84d1, 0x22c0, 0x84cf, 0x22ba, 0x84ce,
+ 0x22b4, 0x84cc, 0x22ae, 0x84ca, 0x22a8, 0x84c9, 0x22a2, 0x84c7,
+ 0x229c, 0x84c5, 0x2296, 0x84c4, 0x2290, 0x84c2, 0x228a, 0x84c0,
+ 0x2284, 0x84be, 0x227e, 0x84bd, 0x2278, 0x84bb, 0x2272, 0x84b9,
+ 0x226c, 0x84b8, 0x2266, 0x84b6, 0x2260, 0x84b4, 0x225a, 0x84b3,
+ 0x2254, 0x84b1, 0x224e, 0x84af, 0x2247, 0x84ae, 0x2241, 0x84ac,
+ 0x223b, 0x84aa, 0x2235, 0x84a9, 0x222f, 0x84a7, 0x2229, 0x84a5,
+ 0x2223, 0x84a3, 0x221d, 0x84a2, 0x2217, 0x84a0, 0x2211, 0x849e,
+ 0x220b, 0x849d, 0x2205, 0x849b, 0x21ff, 0x8499, 0x21f9, 0x8498,
+ 0x21f3, 0x8496, 0x21ed, 0x8494, 0x21e7, 0x8493, 0x21e1, 0x8491,
+ 0x21da, 0x848f, 0x21d4, 0x848e, 0x21ce, 0x848c, 0x21c8, 0x848a,
+ 0x21c2, 0x8489, 0x21bc, 0x8487, 0x21b6, 0x8486, 0x21b0, 0x8484,
+ 0x21aa, 0x8482, 0x21a4, 0x8481, 0x219e, 0x847f, 0x2198, 0x847d,
+ 0x2192, 0x847c, 0x218c, 0x847a, 0x2186, 0x8478, 0x2180, 0x8477,
+ 0x2179, 0x8475, 0x2173, 0x8473, 0x216d, 0x8472, 0x2167, 0x8470,
+ 0x2161, 0x846e, 0x215b, 0x846d, 0x2155, 0x846b, 0x214f, 0x846a,
+ 0x2149, 0x8468, 0x2143, 0x8466, 0x213d, 0x8465, 0x2137, 0x8463,
+ 0x2131, 0x8461, 0x212b, 0x8460, 0x2125, 0x845e, 0x211e, 0x845d,
+ 0x2118, 0x845b, 0x2112, 0x8459, 0x210c, 0x8458, 0x2106, 0x8456,
+ 0x2100, 0x8454, 0x20fa, 0x8453, 0x20f4, 0x8451, 0x20ee, 0x8450,
+ 0x20e8, 0x844e, 0x20e2, 0x844c, 0x20dc, 0x844b, 0x20d6, 0x8449,
+ 0x20d0, 0x8447, 0x20c9, 0x8446, 0x20c3, 0x8444, 0x20bd, 0x8443,
+ 0x20b7, 0x8441, 0x20b1, 0x843f, 0x20ab, 0x843e, 0x20a5, 0x843c,
+ 0x209f, 0x843b, 0x2099, 0x8439, 0x2093, 0x8437, 0x208d, 0x8436,
+ 0x2087, 0x8434, 0x2081, 0x8433, 0x207a, 0x8431, 0x2074, 0x842f,
+ 0x206e, 0x842e, 0x2068, 0x842c, 0x2062, 0x842b, 0x205c, 0x8429,
+ 0x2056, 0x8427, 0x2050, 0x8426, 0x204a, 0x8424, 0x2044, 0x8423,
+ 0x203e, 0x8421, 0x2038, 0x8420, 0x2032, 0x841e, 0x202b, 0x841c,
+ 0x2025, 0x841b, 0x201f, 0x8419, 0x2019, 0x8418, 0x2013, 0x8416,
+ 0x200d, 0x8415, 0x2007, 0x8413, 0x2001, 0x8411, 0x1ffb, 0x8410,
+ 0x1ff5, 0x840e, 0x1fef, 0x840d, 0x1fe9, 0x840b, 0x1fe2, 0x840a,
+ 0x1fdc, 0x8408, 0x1fd6, 0x8406, 0x1fd0, 0x8405, 0x1fca, 0x8403,
+ 0x1fc4, 0x8402, 0x1fbe, 0x8400, 0x1fb8, 0x83ff, 0x1fb2, 0x83fd,
+ 0x1fac, 0x83fb, 0x1fa6, 0x83fa, 0x1f9f, 0x83f8, 0x1f99, 0x83f7,
+ 0x1f93, 0x83f5, 0x1f8d, 0x83f4, 0x1f87, 0x83f2, 0x1f81, 0x83f1,
+ 0x1f7b, 0x83ef, 0x1f75, 0x83ee, 0x1f6f, 0x83ec, 0x1f69, 0x83ea,
+ 0x1f63, 0x83e9, 0x1f5d, 0x83e7, 0x1f56, 0x83e6, 0x1f50, 0x83e4,
+ 0x1f4a, 0x83e3, 0x1f44, 0x83e1, 0x1f3e, 0x83e0, 0x1f38, 0x83de,
+ 0x1f32, 0x83dd, 0x1f2c, 0x83db, 0x1f26, 0x83da, 0x1f20, 0x83d8,
+ 0x1f19, 0x83d7, 0x1f13, 0x83d5, 0x1f0d, 0x83d3, 0x1f07, 0x83d2,
+ 0x1f01, 0x83d0, 0x1efb, 0x83cf, 0x1ef5, 0x83cd, 0x1eef, 0x83cc,
+ 0x1ee9, 0x83ca, 0x1ee3, 0x83c9, 0x1edd, 0x83c7, 0x1ed6, 0x83c6,
+ 0x1ed0, 0x83c4, 0x1eca, 0x83c3, 0x1ec4, 0x83c1, 0x1ebe, 0x83c0,
+ 0x1eb8, 0x83be, 0x1eb2, 0x83bd, 0x1eac, 0x83bb, 0x1ea6, 0x83ba,
+ 0x1ea0, 0x83b8, 0x1e99, 0x83b7, 0x1e93, 0x83b5, 0x1e8d, 0x83b4,
+ 0x1e87, 0x83b2, 0x1e81, 0x83b1, 0x1e7b, 0x83af, 0x1e75, 0x83ae,
+ 0x1e6f, 0x83ac, 0x1e69, 0x83ab, 0x1e62, 0x83a9, 0x1e5c, 0x83a8,
+ 0x1e56, 0x83a6, 0x1e50, 0x83a5, 0x1e4a, 0x83a3, 0x1e44, 0x83a2,
+ 0x1e3e, 0x83a0, 0x1e38, 0x839f, 0x1e32, 0x839d, 0x1e2c, 0x839c,
+ 0x1e25, 0x839a, 0x1e1f, 0x8399, 0x1e19, 0x8397, 0x1e13, 0x8396,
+ 0x1e0d, 0x8394, 0x1e07, 0x8393, 0x1e01, 0x8392, 0x1dfb, 0x8390,
+ 0x1df5, 0x838f, 0x1dee, 0x838d, 0x1de8, 0x838c, 0x1de2, 0x838a,
+ 0x1ddc, 0x8389, 0x1dd6, 0x8387, 0x1dd0, 0x8386, 0x1dca, 0x8384,
+ 0x1dc4, 0x8383, 0x1dbe, 0x8381, 0x1db7, 0x8380, 0x1db1, 0x837e,
+ 0x1dab, 0x837d, 0x1da5, 0x837c, 0x1d9f, 0x837a, 0x1d99, 0x8379,
+ 0x1d93, 0x8377, 0x1d8d, 0x8376, 0x1d87, 0x8374, 0x1d80, 0x8373,
+ 0x1d7a, 0x8371, 0x1d74, 0x8370, 0x1d6e, 0x836f, 0x1d68, 0x836d,
+ 0x1d62, 0x836c, 0x1d5c, 0x836a, 0x1d56, 0x8369, 0x1d50, 0x8367,
+ 0x1d49, 0x8366, 0x1d43, 0x8364, 0x1d3d, 0x8363, 0x1d37, 0x8362,
+ 0x1d31, 0x8360, 0x1d2b, 0x835f, 0x1d25, 0x835d, 0x1d1f, 0x835c,
+ 0x1d18, 0x835a, 0x1d12, 0x8359, 0x1d0c, 0x8358, 0x1d06, 0x8356,
+ 0x1d00, 0x8355, 0x1cfa, 0x8353, 0x1cf4, 0x8352, 0x1cee, 0x8350,
+ 0x1ce8, 0x834f, 0x1ce1, 0x834e, 0x1cdb, 0x834c, 0x1cd5, 0x834b,
+ 0x1ccf, 0x8349, 0x1cc9, 0x8348, 0x1cc3, 0x8347, 0x1cbd, 0x8345,
+ 0x1cb7, 0x8344, 0x1cb0, 0x8342, 0x1caa, 0x8341, 0x1ca4, 0x833f,
+ 0x1c9e, 0x833e, 0x1c98, 0x833d, 0x1c92, 0x833b, 0x1c8c, 0x833a,
+ 0x1c86, 0x8338, 0x1c7f, 0x8337, 0x1c79, 0x8336, 0x1c73, 0x8334,
+ 0x1c6d, 0x8333, 0x1c67, 0x8331, 0x1c61, 0x8330, 0x1c5b, 0x832f,
+ 0x1c55, 0x832d, 0x1c4e, 0x832c, 0x1c48, 0x832b, 0x1c42, 0x8329,
+ 0x1c3c, 0x8328, 0x1c36, 0x8326, 0x1c30, 0x8325, 0x1c2a, 0x8324,
+ 0x1c24, 0x8322, 0x1c1d, 0x8321, 0x1c17, 0x831f, 0x1c11, 0x831e,
+ 0x1c0b, 0x831d, 0x1c05, 0x831b, 0x1bff, 0x831a, 0x1bf9, 0x8319,
+ 0x1bf2, 0x8317, 0x1bec, 0x8316, 0x1be6, 0x8314, 0x1be0, 0x8313,
+ 0x1bda, 0x8312, 0x1bd4, 0x8310, 0x1bce, 0x830f, 0x1bc8, 0x830e,
+ 0x1bc1, 0x830c, 0x1bbb, 0x830b, 0x1bb5, 0x830a, 0x1baf, 0x8308,
+ 0x1ba9, 0x8307, 0x1ba3, 0x8305, 0x1b9d, 0x8304, 0x1b96, 0x8303,
+ 0x1b90, 0x8301, 0x1b8a, 0x8300, 0x1b84, 0x82ff, 0x1b7e, 0x82fd,
+ 0x1b78, 0x82fc, 0x1b72, 0x82fb, 0x1b6c, 0x82f9, 0x1b65, 0x82f8,
+ 0x1b5f, 0x82f7, 0x1b59, 0x82f5, 0x1b53, 0x82f4, 0x1b4d, 0x82f3,
+ 0x1b47, 0x82f1, 0x1b41, 0x82f0, 0x1b3a, 0x82ef, 0x1b34, 0x82ed,
+ 0x1b2e, 0x82ec, 0x1b28, 0x82eb, 0x1b22, 0x82e9, 0x1b1c, 0x82e8,
+ 0x1b16, 0x82e7, 0x1b0f, 0x82e5, 0x1b09, 0x82e4, 0x1b03, 0x82e3,
+ 0x1afd, 0x82e1, 0x1af7, 0x82e0, 0x1af1, 0x82df, 0x1aeb, 0x82dd,
+ 0x1ae4, 0x82dc, 0x1ade, 0x82db, 0x1ad8, 0x82d9, 0x1ad2, 0x82d8,
+ 0x1acc, 0x82d7, 0x1ac6, 0x82d5, 0x1ac0, 0x82d4, 0x1ab9, 0x82d3,
+ 0x1ab3, 0x82d1, 0x1aad, 0x82d0, 0x1aa7, 0x82cf, 0x1aa1, 0x82ce,
+ 0x1a9b, 0x82cc, 0x1a95, 0x82cb, 0x1a8e, 0x82ca, 0x1a88, 0x82c8,
+ 0x1a82, 0x82c7, 0x1a7c, 0x82c6, 0x1a76, 0x82c4, 0x1a70, 0x82c3,
+ 0x1a6a, 0x82c2, 0x1a63, 0x82c1, 0x1a5d, 0x82bf, 0x1a57, 0x82be,
+ 0x1a51, 0x82bd, 0x1a4b, 0x82bb, 0x1a45, 0x82ba, 0x1a3e, 0x82b9,
+ 0x1a38, 0x82b7, 0x1a32, 0x82b6, 0x1a2c, 0x82b5, 0x1a26, 0x82b4,
+ 0x1a20, 0x82b2, 0x1a1a, 0x82b1, 0x1a13, 0x82b0, 0x1a0d, 0x82ae,
+ 0x1a07, 0x82ad, 0x1a01, 0x82ac, 0x19fb, 0x82ab, 0x19f5, 0x82a9,
+ 0x19ef, 0x82a8, 0x19e8, 0x82a7, 0x19e2, 0x82a6, 0x19dc, 0x82a4,
+ 0x19d6, 0x82a3, 0x19d0, 0x82a2, 0x19ca, 0x82a0, 0x19c3, 0x829f,
+ 0x19bd, 0x829e, 0x19b7, 0x829d, 0x19b1, 0x829b, 0x19ab, 0x829a,
+ 0x19a5, 0x8299, 0x199f, 0x8298, 0x1998, 0x8296, 0x1992, 0x8295,
+ 0x198c, 0x8294, 0x1986, 0x8293, 0x1980, 0x8291, 0x197a, 0x8290,
+ 0x1973, 0x828f, 0x196d, 0x828e, 0x1967, 0x828c, 0x1961, 0x828b,
+ 0x195b, 0x828a, 0x1955, 0x8289, 0x194e, 0x8287, 0x1948, 0x8286,
+ 0x1942, 0x8285, 0x193c, 0x8284, 0x1936, 0x8282, 0x1930, 0x8281,
+ 0x192a, 0x8280, 0x1923, 0x827f, 0x191d, 0x827e, 0x1917, 0x827c,
+ 0x1911, 0x827b, 0x190b, 0x827a, 0x1905, 0x8279, 0x18fe, 0x8277,
+ 0x18f8, 0x8276, 0x18f2, 0x8275, 0x18ec, 0x8274, 0x18e6, 0x8272,
+ 0x18e0, 0x8271, 0x18d9, 0x8270, 0x18d3, 0x826f, 0x18cd, 0x826e,
+ 0x18c7, 0x826c, 0x18c1, 0x826b, 0x18bb, 0x826a, 0x18b4, 0x8269,
+ 0x18ae, 0x8268, 0x18a8, 0x8266, 0x18a2, 0x8265, 0x189c, 0x8264,
+ 0x1896, 0x8263, 0x188f, 0x8261, 0x1889, 0x8260, 0x1883, 0x825f,
+ 0x187d, 0x825e, 0x1877, 0x825d, 0x1871, 0x825b, 0x186a, 0x825a,
+ 0x1864, 0x8259, 0x185e, 0x8258, 0x1858, 0x8257, 0x1852, 0x8255,
+ 0x184c, 0x8254, 0x1845, 0x8253, 0x183f, 0x8252, 0x1839, 0x8251,
+ 0x1833, 0x8250, 0x182d, 0x824e, 0x1827, 0x824d, 0x1820, 0x824c,
+ 0x181a, 0x824b, 0x1814, 0x824a, 0x180e, 0x8248, 0x1808, 0x8247,
+ 0x1802, 0x8246, 0x17fb, 0x8245, 0x17f5, 0x8244, 0x17ef, 0x8243,
+ 0x17e9, 0x8241, 0x17e3, 0x8240, 0x17dd, 0x823f, 0x17d6, 0x823e,
+ 0x17d0, 0x823d, 0x17ca, 0x823b, 0x17c4, 0x823a, 0x17be, 0x8239,
+ 0x17b7, 0x8238, 0x17b1, 0x8237, 0x17ab, 0x8236, 0x17a5, 0x8234,
+ 0x179f, 0x8233, 0x1799, 0x8232, 0x1792, 0x8231, 0x178c, 0x8230,
+ 0x1786, 0x822f, 0x1780, 0x822e, 0x177a, 0x822c, 0x1774, 0x822b,
+ 0x176d, 0x822a, 0x1767, 0x8229, 0x1761, 0x8228, 0x175b, 0x8227,
+ 0x1755, 0x8226, 0x174e, 0x8224, 0x1748, 0x8223, 0x1742, 0x8222,
+ 0x173c, 0x8221, 0x1736, 0x8220, 0x1730, 0x821f, 0x1729, 0x821e,
+ 0x1723, 0x821c, 0x171d, 0x821b, 0x1717, 0x821a, 0x1711, 0x8219,
+ 0x170a, 0x8218, 0x1704, 0x8217, 0x16fe, 0x8216, 0x16f8, 0x8214,
+ 0x16f2, 0x8213, 0x16ec, 0x8212, 0x16e5, 0x8211, 0x16df, 0x8210,
+ 0x16d9, 0x820f, 0x16d3, 0x820e, 0x16cd, 0x820d, 0x16c6, 0x820b,
+ 0x16c0, 0x820a, 0x16ba, 0x8209, 0x16b4, 0x8208, 0x16ae, 0x8207,
+ 0x16a8, 0x8206, 0x16a1, 0x8205, 0x169b, 0x8204, 0x1695, 0x8203,
+ 0x168f, 0x8201, 0x1689, 0x8200, 0x1682, 0x81ff, 0x167c, 0x81fe,
+ 0x1676, 0x81fd, 0x1670, 0x81fc, 0x166a, 0x81fb, 0x1664, 0x81fa,
+ 0x165d, 0x81f9, 0x1657, 0x81f8, 0x1651, 0x81f6, 0x164b, 0x81f5,
+ 0x1645, 0x81f4, 0x163e, 0x81f3, 0x1638, 0x81f2, 0x1632, 0x81f1,
+ 0x162c, 0x81f0, 0x1626, 0x81ef, 0x161f, 0x81ee, 0x1619, 0x81ed,
+ 0x1613, 0x81ec, 0x160d, 0x81ea, 0x1607, 0x81e9, 0x1601, 0x81e8,
+ 0x15fa, 0x81e7, 0x15f4, 0x81e6, 0x15ee, 0x81e5, 0x15e8, 0x81e4,
+ 0x15e2, 0x81e3, 0x15db, 0x81e2, 0x15d5, 0x81e1, 0x15cf, 0x81e0,
+ 0x15c9, 0x81df, 0x15c3, 0x81de, 0x15bc, 0x81dc, 0x15b6, 0x81db,
+ 0x15b0, 0x81da, 0x15aa, 0x81d9, 0x15a4, 0x81d8, 0x159d, 0x81d7,
+ 0x1597, 0x81d6, 0x1591, 0x81d5, 0x158b, 0x81d4, 0x1585, 0x81d3,
+ 0x157f, 0x81d2, 0x1578, 0x81d1, 0x1572, 0x81d0, 0x156c, 0x81cf,
+ 0x1566, 0x81ce, 0x1560, 0x81cd, 0x1559, 0x81cc, 0x1553, 0x81cb,
+ 0x154d, 0x81c9, 0x1547, 0x81c8, 0x1541, 0x81c7, 0x153a, 0x81c6,
+ 0x1534, 0x81c5, 0x152e, 0x81c4, 0x1528, 0x81c3, 0x1522, 0x81c2,
+ 0x151b, 0x81c1, 0x1515, 0x81c0, 0x150f, 0x81bf, 0x1509, 0x81be,
+ 0x1503, 0x81bd, 0x14fc, 0x81bc, 0x14f6, 0x81bb, 0x14f0, 0x81ba,
+ 0x14ea, 0x81b9, 0x14e4, 0x81b8, 0x14dd, 0x81b7, 0x14d7, 0x81b6,
+ 0x14d1, 0x81b5, 0x14cb, 0x81b4, 0x14c5, 0x81b3, 0x14be, 0x81b2,
+ 0x14b8, 0x81b1, 0x14b2, 0x81b0, 0x14ac, 0x81af, 0x14a6, 0x81ae,
+ 0x149f, 0x81ad, 0x1499, 0x81ac, 0x1493, 0x81ab, 0x148d, 0x81aa,
+ 0x1487, 0x81a9, 0x1480, 0x81a8, 0x147a, 0x81a7, 0x1474, 0x81a6,
+ 0x146e, 0x81a5, 0x1468, 0x81a4, 0x1461, 0x81a3, 0x145b, 0x81a2,
+ 0x1455, 0x81a1, 0x144f, 0x81a0, 0x1449, 0x819f, 0x1442, 0x819e,
+ 0x143c, 0x819d, 0x1436, 0x819c, 0x1430, 0x819b, 0x142a, 0x819a,
+ 0x1423, 0x8199, 0x141d, 0x8198, 0x1417, 0x8197, 0x1411, 0x8196,
+ 0x140b, 0x8195, 0x1404, 0x8194, 0x13fe, 0x8193, 0x13f8, 0x8192,
+ 0x13f2, 0x8191, 0x13eb, 0x8190, 0x13e5, 0x818f, 0x13df, 0x818e,
+ 0x13d9, 0x818d, 0x13d3, 0x818c, 0x13cc, 0x818b, 0x13c6, 0x818a,
+ 0x13c0, 0x8189, 0x13ba, 0x8188, 0x13b4, 0x8187, 0x13ad, 0x8186,
+ 0x13a7, 0x8185, 0x13a1, 0x8184, 0x139b, 0x8183, 0x1395, 0x8182,
+ 0x138e, 0x8181, 0x1388, 0x8180, 0x1382, 0x817f, 0x137c, 0x817e,
+ 0x1376, 0x817d, 0x136f, 0x817c, 0x1369, 0x817c, 0x1363, 0x817b,
+ 0x135d, 0x817a, 0x1356, 0x8179, 0x1350, 0x8178, 0x134a, 0x8177,
+ 0x1344, 0x8176, 0x133e, 0x8175, 0x1337, 0x8174, 0x1331, 0x8173,
+ 0x132b, 0x8172, 0x1325, 0x8171, 0x131f, 0x8170, 0x1318, 0x816f,
+ 0x1312, 0x816e, 0x130c, 0x816d, 0x1306, 0x816c, 0x12ff, 0x816c,
+ 0x12f9, 0x816b, 0x12f3, 0x816a, 0x12ed, 0x8169, 0x12e7, 0x8168,
+ 0x12e0, 0x8167, 0x12da, 0x8166, 0x12d4, 0x8165, 0x12ce, 0x8164,
+ 0x12c8, 0x8163, 0x12c1, 0x8162, 0x12bb, 0x8161, 0x12b5, 0x8160,
+ 0x12af, 0x815f, 0x12a8, 0x815f, 0x12a2, 0x815e, 0x129c, 0x815d,
+ 0x1296, 0x815c, 0x1290, 0x815b, 0x1289, 0x815a, 0x1283, 0x8159,
+ 0x127d, 0x8158, 0x1277, 0x8157, 0x1271, 0x8156, 0x126a, 0x8155,
+ 0x1264, 0x8155, 0x125e, 0x8154, 0x1258, 0x8153, 0x1251, 0x8152,
+ 0x124b, 0x8151, 0x1245, 0x8150, 0x123f, 0x814f, 0x1239, 0x814e,
+ 0x1232, 0x814d, 0x122c, 0x814c, 0x1226, 0x814c, 0x1220, 0x814b,
+ 0x1219, 0x814a, 0x1213, 0x8149, 0x120d, 0x8148, 0x1207, 0x8147,
+ 0x1201, 0x8146, 0x11fa, 0x8145, 0x11f4, 0x8145, 0x11ee, 0x8144,
+ 0x11e8, 0x8143, 0x11e1, 0x8142, 0x11db, 0x8141, 0x11d5, 0x8140,
+ 0x11cf, 0x813f, 0x11c9, 0x813e, 0x11c2, 0x813d, 0x11bc, 0x813d,
+ 0x11b6, 0x813c, 0x11b0, 0x813b, 0x11a9, 0x813a, 0x11a3, 0x8139,
+ 0x119d, 0x8138, 0x1197, 0x8137, 0x1191, 0x8137, 0x118a, 0x8136,
+ 0x1184, 0x8135, 0x117e, 0x8134, 0x1178, 0x8133, 0x1171, 0x8132,
+ 0x116b, 0x8131, 0x1165, 0x8131, 0x115f, 0x8130, 0x1159, 0x812f,
+ 0x1152, 0x812e, 0x114c, 0x812d, 0x1146, 0x812c, 0x1140, 0x812b,
+ 0x1139, 0x812b, 0x1133, 0x812a, 0x112d, 0x8129, 0x1127, 0x8128,
+ 0x1121, 0x8127, 0x111a, 0x8126, 0x1114, 0x8126, 0x110e, 0x8125,
+ 0x1108, 0x8124, 0x1101, 0x8123, 0x10fb, 0x8122, 0x10f5, 0x8121,
+ 0x10ef, 0x8121, 0x10e8, 0x8120, 0x10e2, 0x811f, 0x10dc, 0x811e,
+ 0x10d6, 0x811d, 0x10d0, 0x811c, 0x10c9, 0x811c, 0x10c3, 0x811b,
+ 0x10bd, 0x811a, 0x10b7, 0x8119, 0x10b0, 0x8118, 0x10aa, 0x8117,
+ 0x10a4, 0x8117, 0x109e, 0x8116, 0x1098, 0x8115, 0x1091, 0x8114,
+ 0x108b, 0x8113, 0x1085, 0x8113, 0x107f, 0x8112, 0x1078, 0x8111,
+ 0x1072, 0x8110, 0x106c, 0x810f, 0x1066, 0x810f, 0x105f, 0x810e,
+ 0x1059, 0x810d, 0x1053, 0x810c, 0x104d, 0x810b, 0x1047, 0x810b,
+ 0x1040, 0x810a, 0x103a, 0x8109, 0x1034, 0x8108, 0x102e, 0x8107,
+ 0x1027, 0x8107, 0x1021, 0x8106, 0x101b, 0x8105, 0x1015, 0x8104,
+ 0x100e, 0x8103, 0x1008, 0x8103, 0x1002, 0x8102, 0xffc, 0x8101,
+ 0xff5, 0x8100, 0xfef, 0x80ff, 0xfe9, 0x80ff, 0xfe3, 0x80fe,
+ 0xfdd, 0x80fd, 0xfd6, 0x80fc, 0xfd0, 0x80fc, 0xfca, 0x80fb,
+ 0xfc4, 0x80fa, 0xfbd, 0x80f9, 0xfb7, 0x80f8, 0xfb1, 0x80f8,
+ 0xfab, 0x80f7, 0xfa4, 0x80f6, 0xf9e, 0x80f5, 0xf98, 0x80f5,
+ 0xf92, 0x80f4, 0xf8b, 0x80f3, 0xf85, 0x80f2, 0xf7f, 0x80f2,
+ 0xf79, 0x80f1, 0xf73, 0x80f0, 0xf6c, 0x80ef, 0xf66, 0x80ef,
+ 0xf60, 0x80ee, 0xf5a, 0x80ed, 0xf53, 0x80ec, 0xf4d, 0x80ec,
+ 0xf47, 0x80eb, 0xf41, 0x80ea, 0xf3a, 0x80e9, 0xf34, 0x80e9,
+ 0xf2e, 0x80e8, 0xf28, 0x80e7, 0xf21, 0x80e6, 0xf1b, 0x80e6,
+ 0xf15, 0x80e5, 0xf0f, 0x80e4, 0xf08, 0x80e3, 0xf02, 0x80e3,
+ 0xefc, 0x80e2, 0xef6, 0x80e1, 0xef0, 0x80e0, 0xee9, 0x80e0,
+ 0xee3, 0x80df, 0xedd, 0x80de, 0xed7, 0x80dd, 0xed0, 0x80dd,
+ 0xeca, 0x80dc, 0xec4, 0x80db, 0xebe, 0x80db, 0xeb7, 0x80da,
+ 0xeb1, 0x80d9, 0xeab, 0x80d8, 0xea5, 0x80d8, 0xe9e, 0x80d7,
+ 0xe98, 0x80d6, 0xe92, 0x80d6, 0xe8c, 0x80d5, 0xe85, 0x80d4,
+ 0xe7f, 0x80d3, 0xe79, 0x80d3, 0xe73, 0x80d2, 0xe6c, 0x80d1,
+ 0xe66, 0x80d1, 0xe60, 0x80d0, 0xe5a, 0x80cf, 0xe53, 0x80ce,
+ 0xe4d, 0x80ce, 0xe47, 0x80cd, 0xe41, 0x80cc, 0xe3a, 0x80cc,
+ 0xe34, 0x80cb, 0xe2e, 0x80ca, 0xe28, 0x80ca, 0xe22, 0x80c9,
+ 0xe1b, 0x80c8, 0xe15, 0x80c7, 0xe0f, 0x80c7, 0xe09, 0x80c6,
+ 0xe02, 0x80c5, 0xdfc, 0x80c5, 0xdf6, 0x80c4, 0xdf0, 0x80c3,
+ 0xde9, 0x80c3, 0xde3, 0x80c2, 0xddd, 0x80c1, 0xdd7, 0x80c1,
+ 0xdd0, 0x80c0, 0xdca, 0x80bf, 0xdc4, 0x80bf, 0xdbe, 0x80be,
+ 0xdb7, 0x80bd, 0xdb1, 0x80bd, 0xdab, 0x80bc, 0xda5, 0x80bb,
+ 0xd9e, 0x80bb, 0xd98, 0x80ba, 0xd92, 0x80b9, 0xd8c, 0x80b9,
+ 0xd85, 0x80b8, 0xd7f, 0x80b7, 0xd79, 0x80b7, 0xd73, 0x80b6,
+ 0xd6c, 0x80b5, 0xd66, 0x80b5, 0xd60, 0x80b4, 0xd5a, 0x80b3,
+ 0xd53, 0x80b3, 0xd4d, 0x80b2, 0xd47, 0x80b1, 0xd41, 0x80b1,
+ 0xd3a, 0x80b0, 0xd34, 0x80af, 0xd2e, 0x80af, 0xd28, 0x80ae,
+ 0xd21, 0x80ad, 0xd1b, 0x80ad, 0xd15, 0x80ac, 0xd0f, 0x80ab,
+ 0xd08, 0x80ab, 0xd02, 0x80aa, 0xcfc, 0x80aa, 0xcf6, 0x80a9,
+ 0xcef, 0x80a8, 0xce9, 0x80a8, 0xce3, 0x80a7, 0xcdd, 0x80a6,
+ 0xcd6, 0x80a6, 0xcd0, 0x80a5, 0xcca, 0x80a5, 0xcc4, 0x80a4,
+ 0xcbd, 0x80a3, 0xcb7, 0x80a3, 0xcb1, 0x80a2, 0xcab, 0x80a1,
+ 0xca4, 0x80a1, 0xc9e, 0x80a0, 0xc98, 0x80a0, 0xc92, 0x809f,
+ 0xc8b, 0x809e, 0xc85, 0x809e, 0xc7f, 0x809d, 0xc79, 0x809c,
+ 0xc72, 0x809c, 0xc6c, 0x809b, 0xc66, 0x809b, 0xc60, 0x809a,
+ 0xc59, 0x8099, 0xc53, 0x8099, 0xc4d, 0x8098, 0xc47, 0x8098,
+ 0xc40, 0x8097, 0xc3a, 0x8096, 0xc34, 0x8096, 0xc2e, 0x8095,
+ 0xc27, 0x8095, 0xc21, 0x8094, 0xc1b, 0x8093, 0xc14, 0x8093,
+ 0xc0e, 0x8092, 0xc08, 0x8092, 0xc02, 0x8091, 0xbfb, 0x8090,
+ 0xbf5, 0x8090, 0xbef, 0x808f, 0xbe9, 0x808f, 0xbe2, 0x808e,
+ 0xbdc, 0x808e, 0xbd6, 0x808d, 0xbd0, 0x808c, 0xbc9, 0x808c,
+ 0xbc3, 0x808b, 0xbbd, 0x808b, 0xbb7, 0x808a, 0xbb0, 0x8089,
+ 0xbaa, 0x8089, 0xba4, 0x8088, 0xb9e, 0x8088, 0xb97, 0x8087,
+ 0xb91, 0x8087, 0xb8b, 0x8086, 0xb85, 0x8085, 0xb7e, 0x8085,
+ 0xb78, 0x8084, 0xb72, 0x8084, 0xb6c, 0x8083, 0xb65, 0x8083,
+ 0xb5f, 0x8082, 0xb59, 0x8082, 0xb53, 0x8081, 0xb4c, 0x8080,
+ 0xb46, 0x8080, 0xb40, 0x807f, 0xb3a, 0x807f, 0xb33, 0x807e,
+ 0xb2d, 0x807e, 0xb27, 0x807d, 0xb20, 0x807d, 0xb1a, 0x807c,
+ 0xb14, 0x807b, 0xb0e, 0x807b, 0xb07, 0x807a, 0xb01, 0x807a,
+ 0xafb, 0x8079, 0xaf5, 0x8079, 0xaee, 0x8078, 0xae8, 0x8078,
+ 0xae2, 0x8077, 0xadc, 0x8077, 0xad5, 0x8076, 0xacf, 0x8076,
+ 0xac9, 0x8075, 0xac3, 0x8075, 0xabc, 0x8074, 0xab6, 0x8073,
+ 0xab0, 0x8073, 0xaaa, 0x8072, 0xaa3, 0x8072, 0xa9d, 0x8071,
+ 0xa97, 0x8071, 0xa90, 0x8070, 0xa8a, 0x8070, 0xa84, 0x806f,
+ 0xa7e, 0x806f, 0xa77, 0x806e, 0xa71, 0x806e, 0xa6b, 0x806d,
+ 0xa65, 0x806d, 0xa5e, 0x806c, 0xa58, 0x806c, 0xa52, 0x806b,
+ 0xa4c, 0x806b, 0xa45, 0x806a, 0xa3f, 0x806a, 0xa39, 0x8069,
+ 0xa33, 0x8069, 0xa2c, 0x8068, 0xa26, 0x8068, 0xa20, 0x8067,
+ 0xa19, 0x8067, 0xa13, 0x8066, 0xa0d, 0x8066, 0xa07, 0x8065,
+ 0xa00, 0x8065, 0x9fa, 0x8064, 0x9f4, 0x8064, 0x9ee, 0x8063,
+ 0x9e7, 0x8063, 0x9e1, 0x8062, 0x9db, 0x8062, 0x9d5, 0x8061,
+ 0x9ce, 0x8061, 0x9c8, 0x8060, 0x9c2, 0x8060, 0x9bc, 0x805f,
+ 0x9b5, 0x805f, 0x9af, 0x805e, 0x9a9, 0x805e, 0x9a2, 0x805d,
+ 0x99c, 0x805d, 0x996, 0x805d, 0x990, 0x805c, 0x989, 0x805c,
+ 0x983, 0x805b, 0x97d, 0x805b, 0x977, 0x805a, 0x970, 0x805a,
+ 0x96a, 0x8059, 0x964, 0x8059, 0x95e, 0x8058, 0x957, 0x8058,
+ 0x951, 0x8057, 0x94b, 0x8057, 0x944, 0x8057, 0x93e, 0x8056,
+ 0x938, 0x8056, 0x932, 0x8055, 0x92b, 0x8055, 0x925, 0x8054,
+ 0x91f, 0x8054, 0x919, 0x8053, 0x912, 0x8053, 0x90c, 0x8052,
+ 0x906, 0x8052, 0x900, 0x8052, 0x8f9, 0x8051, 0x8f3, 0x8051,
+ 0x8ed, 0x8050, 0x8e6, 0x8050, 0x8e0, 0x804f, 0x8da, 0x804f,
+ 0x8d4, 0x804f, 0x8cd, 0x804e, 0x8c7, 0x804e, 0x8c1, 0x804d,
+ 0x8bb, 0x804d, 0x8b4, 0x804c, 0x8ae, 0x804c, 0x8a8, 0x804c,
+ 0x8a2, 0x804b, 0x89b, 0x804b, 0x895, 0x804a, 0x88f, 0x804a,
+ 0x888, 0x8049, 0x882, 0x8049, 0x87c, 0x8049, 0x876, 0x8048,
+ 0x86f, 0x8048, 0x869, 0x8047, 0x863, 0x8047, 0x85d, 0x8047,
+ 0x856, 0x8046, 0x850, 0x8046, 0x84a, 0x8045, 0x843, 0x8045,
+ 0x83d, 0x8044, 0x837, 0x8044, 0x831, 0x8044, 0x82a, 0x8043,
+ 0x824, 0x8043, 0x81e, 0x8042, 0x818, 0x8042, 0x811, 0x8042,
+ 0x80b, 0x8041, 0x805, 0x8041, 0x7fe, 0x8040, 0x7f8, 0x8040,
+ 0x7f2, 0x8040, 0x7ec, 0x803f, 0x7e5, 0x803f, 0x7df, 0x803f,
+ 0x7d9, 0x803e, 0x7d3, 0x803e, 0x7cc, 0x803d, 0x7c6, 0x803d,
+ 0x7c0, 0x803d, 0x7ba, 0x803c, 0x7b3, 0x803c, 0x7ad, 0x803b,
+ 0x7a7, 0x803b, 0x7a0, 0x803b, 0x79a, 0x803a, 0x794, 0x803a,
+ 0x78e, 0x803a, 0x787, 0x8039, 0x781, 0x8039, 0x77b, 0x8039,
+ 0x775, 0x8038, 0x76e, 0x8038, 0x768, 0x8037, 0x762, 0x8037,
+ 0x75b, 0x8037, 0x755, 0x8036, 0x74f, 0x8036, 0x749, 0x8036,
+ 0x742, 0x8035, 0x73c, 0x8035, 0x736, 0x8035, 0x730, 0x8034,
+ 0x729, 0x8034, 0x723, 0x8033, 0x71d, 0x8033, 0x716, 0x8033,
+ 0x710, 0x8032, 0x70a, 0x8032, 0x704, 0x8032, 0x6fd, 0x8031,
+ 0x6f7, 0x8031, 0x6f1, 0x8031, 0x6ea, 0x8030, 0x6e4, 0x8030,
+ 0x6de, 0x8030, 0x6d8, 0x802f, 0x6d1, 0x802f, 0x6cb, 0x802f,
+ 0x6c5, 0x802e, 0x6bf, 0x802e, 0x6b8, 0x802e, 0x6b2, 0x802d,
+ 0x6ac, 0x802d, 0x6a5, 0x802d, 0x69f, 0x802c, 0x699, 0x802c,
+ 0x693, 0x802c, 0x68c, 0x802b, 0x686, 0x802b, 0x680, 0x802b,
+ 0x67a, 0x802a, 0x673, 0x802a, 0x66d, 0x802a, 0x667, 0x802a,
+ 0x660, 0x8029, 0x65a, 0x8029, 0x654, 0x8029, 0x64e, 0x8028,
+ 0x647, 0x8028, 0x641, 0x8028, 0x63b, 0x8027, 0x635, 0x8027,
+ 0x62e, 0x8027, 0x628, 0x8026, 0x622, 0x8026, 0x61b, 0x8026,
+ 0x615, 0x8026, 0x60f, 0x8025, 0x609, 0x8025, 0x602, 0x8025,
+ 0x5fc, 0x8024, 0x5f6, 0x8024, 0x5ef, 0x8024, 0x5e9, 0x8023,
+ 0x5e3, 0x8023, 0x5dd, 0x8023, 0x5d6, 0x8023, 0x5d0, 0x8022,
+ 0x5ca, 0x8022, 0x5c4, 0x8022, 0x5bd, 0x8021, 0x5b7, 0x8021,
+ 0x5b1, 0x8021, 0x5aa, 0x8021, 0x5a4, 0x8020, 0x59e, 0x8020,
+ 0x598, 0x8020, 0x591, 0x8020, 0x58b, 0x801f, 0x585, 0x801f,
+ 0x57f, 0x801f, 0x578, 0x801e, 0x572, 0x801e, 0x56c, 0x801e,
+ 0x565, 0x801e, 0x55f, 0x801d, 0x559, 0x801d, 0x553, 0x801d,
+ 0x54c, 0x801d, 0x546, 0x801c, 0x540, 0x801c, 0x539, 0x801c,
+ 0x533, 0x801c, 0x52d, 0x801b, 0x527, 0x801b, 0x520, 0x801b,
+ 0x51a, 0x801b, 0x514, 0x801a, 0x50d, 0x801a, 0x507, 0x801a,
+ 0x501, 0x801a, 0x4fb, 0x8019, 0x4f4, 0x8019, 0x4ee, 0x8019,
+ 0x4e8, 0x8019, 0x4e2, 0x8018, 0x4db, 0x8018, 0x4d5, 0x8018,
+ 0x4cf, 0x8018, 0x4c8, 0x8017, 0x4c2, 0x8017, 0x4bc, 0x8017,
+ 0x4b6, 0x8017, 0x4af, 0x8016, 0x4a9, 0x8016, 0x4a3, 0x8016,
+ 0x49c, 0x8016, 0x496, 0x8016, 0x490, 0x8015, 0x48a, 0x8015,
+ 0x483, 0x8015, 0x47d, 0x8015, 0x477, 0x8014, 0x471, 0x8014,
+ 0x46a, 0x8014, 0x464, 0x8014, 0x45e, 0x8014, 0x457, 0x8013,
+ 0x451, 0x8013, 0x44b, 0x8013, 0x445, 0x8013, 0x43e, 0x8013,
+ 0x438, 0x8012, 0x432, 0x8012, 0x42b, 0x8012, 0x425, 0x8012,
+ 0x41f, 0x8012, 0x419, 0x8011, 0x412, 0x8011, 0x40c, 0x8011,
+ 0x406, 0x8011, 0x3ff, 0x8011, 0x3f9, 0x8010, 0x3f3, 0x8010,
+ 0x3ed, 0x8010, 0x3e6, 0x8010, 0x3e0, 0x8010, 0x3da, 0x800f,
+ 0x3d4, 0x800f, 0x3cd, 0x800f, 0x3c7, 0x800f, 0x3c1, 0x800f,
+ 0x3ba, 0x800e, 0x3b4, 0x800e, 0x3ae, 0x800e, 0x3a8, 0x800e,
+ 0x3a1, 0x800e, 0x39b, 0x800e, 0x395, 0x800d, 0x38e, 0x800d,
+ 0x388, 0x800d, 0x382, 0x800d, 0x37c, 0x800d, 0x375, 0x800c,
+ 0x36f, 0x800c, 0x369, 0x800c, 0x362, 0x800c, 0x35c, 0x800c,
+ 0x356, 0x800c, 0x350, 0x800b, 0x349, 0x800b, 0x343, 0x800b,
+ 0x33d, 0x800b, 0x337, 0x800b, 0x330, 0x800b, 0x32a, 0x800b,
+ 0x324, 0x800a, 0x31d, 0x800a, 0x317, 0x800a, 0x311, 0x800a,
+ 0x30b, 0x800a, 0x304, 0x800a, 0x2fe, 0x8009, 0x2f8, 0x8009,
+ 0x2f1, 0x8009, 0x2eb, 0x8009, 0x2e5, 0x8009, 0x2df, 0x8009,
+ 0x2d8, 0x8009, 0x2d2, 0x8008, 0x2cc, 0x8008, 0x2c5, 0x8008,
+ 0x2bf, 0x8008, 0x2b9, 0x8008, 0x2b3, 0x8008, 0x2ac, 0x8008,
+ 0x2a6, 0x8008, 0x2a0, 0x8007, 0x299, 0x8007, 0x293, 0x8007,
+ 0x28d, 0x8007, 0x287, 0x8007, 0x280, 0x8007, 0x27a, 0x8007,
+ 0x274, 0x8007, 0x26d, 0x8006, 0x267, 0x8006, 0x261, 0x8006,
+ 0x25b, 0x8006, 0x254, 0x8006, 0x24e, 0x8006, 0x248, 0x8006,
+ 0x242, 0x8006, 0x23b, 0x8005, 0x235, 0x8005, 0x22f, 0x8005,
+ 0x228, 0x8005, 0x222, 0x8005, 0x21c, 0x8005, 0x216, 0x8005,
+ 0x20f, 0x8005, 0x209, 0x8005, 0x203, 0x8005, 0x1fc, 0x8004,
+ 0x1f6, 0x8004, 0x1f0, 0x8004, 0x1ea, 0x8004, 0x1e3, 0x8004,
+ 0x1dd, 0x8004, 0x1d7, 0x8004, 0x1d0, 0x8004, 0x1ca, 0x8004,
+ 0x1c4, 0x8004, 0x1be, 0x8004, 0x1b7, 0x8003, 0x1b1, 0x8003,
+ 0x1ab, 0x8003, 0x1a4, 0x8003, 0x19e, 0x8003, 0x198, 0x8003,
+ 0x192, 0x8003, 0x18b, 0x8003, 0x185, 0x8003, 0x17f, 0x8003,
+ 0x178, 0x8003, 0x172, 0x8003, 0x16c, 0x8003, 0x166, 0x8002,
+ 0x15f, 0x8002, 0x159, 0x8002, 0x153, 0x8002, 0x14d, 0x8002,
+ 0x146, 0x8002, 0x140, 0x8002, 0x13a, 0x8002, 0x133, 0x8002,
+ 0x12d, 0x8002, 0x127, 0x8002, 0x121, 0x8002, 0x11a, 0x8002,
+ 0x114, 0x8002, 0x10e, 0x8002, 0x107, 0x8002, 0x101, 0x8002,
+ 0xfb, 0x8001, 0xf5, 0x8001, 0xee, 0x8001, 0xe8, 0x8001,
+ 0xe2, 0x8001, 0xdb, 0x8001, 0xd5, 0x8001, 0xcf, 0x8001,
+ 0xc9, 0x8001, 0xc2, 0x8001, 0xbc, 0x8001, 0xb6, 0x8001,
+ 0xaf, 0x8001, 0xa9, 0x8001, 0xa3, 0x8001, 0x9d, 0x8001,
+ 0x96, 0x8001, 0x90, 0x8001, 0x8a, 0x8001, 0x83, 0x8001,
+ 0x7d, 0x8001, 0x77, 0x8001, 0x71, 0x8001, 0x6a, 0x8001,
+ 0x64, 0x8001, 0x5e, 0x8001, 0x57, 0x8001, 0x51, 0x8001,
+ 0x4b, 0x8001, 0x45, 0x8001, 0x3e, 0x8001, 0x38, 0x8001,
+ 0x32, 0x8001, 0x2b, 0x8001, 0x25, 0x8001, 0x1f, 0x8001,
+ 0x19, 0x8001, 0x12, 0x8001, 0xc, 0x8001, 0x6, 0x8001,
+};
+
+
+/**
+* \par
+* cosFactor tables are generated using the formula : <pre> cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) </pre>
+* \par
+* C command to generate the table
+* <pre>
+* for(i = 0; i< N; i++)
+* {
+* cos_factors[i]= 2 * cos((2*i+1)*c/2);
+* } </pre>
+* \par
+* where <code>N</code> is the number of factors to generate and <code>c</code> is <code>pi/(2*N)</code>
+* \par
+* Then converted to q15 format by multiplying with 2^31 and saturated if required.
+
+*/
+
+static const q15_t ALIGN4 cos_factorsQ15_128[128] = {
+ 0x7fff, 0x7ffa, 0x7ff0, 0x7fe1, 0x7fce, 0x7fb5, 0x7f97, 0x7f75,
+ 0x7f4d, 0x7f21, 0x7ef0, 0x7eba, 0x7e7f, 0x7e3f, 0x7dfa, 0x7db0,
+ 0x7d62, 0x7d0f, 0x7cb7, 0x7c5a, 0x7bf8, 0x7b92, 0x7b26, 0x7ab6,
+ 0x7a42, 0x79c8, 0x794a, 0x78c7, 0x7840, 0x77b4, 0x7723, 0x768e,
+ 0x75f4, 0x7555, 0x74b2, 0x740b, 0x735f, 0x72af, 0x71fa, 0x7141,
+ 0x7083, 0x6fc1, 0x6efb, 0x6e30, 0x6d62, 0x6c8f, 0x6bb8, 0x6adc,
+ 0x69fd, 0x6919, 0x6832, 0x6746, 0x6657, 0x6563, 0x646c, 0x6371,
+ 0x6271, 0x616f, 0x6068, 0x5f5e, 0x5e50, 0x5d3e, 0x5c29, 0x5b10,
+ 0x59f3, 0x58d4, 0x57b0, 0x568a, 0x5560, 0x5433, 0x5302, 0x51ce,
+ 0x5097, 0x4f5e, 0x4e21, 0x4ce1, 0x4b9e, 0x4a58, 0x490f, 0x47c3,
+ 0x4675, 0x4524, 0x43d0, 0x427a, 0x4121, 0x3fc5, 0x3e68, 0x3d07,
+ 0x3ba5, 0x3a40, 0x38d8, 0x376f, 0x3604, 0x3496, 0x3326, 0x31b5,
+ 0x3041, 0x2ecc, 0x2d55, 0x2bdc, 0x2a61, 0x28e5, 0x2767, 0x25e8,
+ 0x2467, 0x22e5, 0x2161, 0x1fdc, 0x1e56, 0x1ccf, 0x1b47, 0x19bd,
+ 0x1833, 0x16a8, 0x151b, 0x138e, 0x1201, 0x1072, 0xee3, 0xd53,
+ 0xbc3, 0xa33, 0x8a2, 0x710, 0x57f, 0x3ed, 0x25b, 0xc9
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_512[512] = {
+ 0x7fff, 0x7fff, 0x7fff, 0x7ffe, 0x7ffc, 0x7ffb, 0x7ff9, 0x7ff7,
+ 0x7ff4, 0x7ff2, 0x7fee, 0x7feb, 0x7fe7, 0x7fe3, 0x7fdf, 0x7fda,
+ 0x7fd6, 0x7fd0, 0x7fcb, 0x7fc5, 0x7fbf, 0x7fb8, 0x7fb1, 0x7faa,
+ 0x7fa3, 0x7f9b, 0x7f93, 0x7f8b, 0x7f82, 0x7f79, 0x7f70, 0x7f67,
+ 0x7f5d, 0x7f53, 0x7f48, 0x7f3d, 0x7f32, 0x7f27, 0x7f1b, 0x7f0f,
+ 0x7f03, 0x7ef6, 0x7ee9, 0x7edc, 0x7ecf, 0x7ec1, 0x7eb3, 0x7ea4,
+ 0x7e95, 0x7e86, 0x7e77, 0x7e67, 0x7e57, 0x7e47, 0x7e37, 0x7e26,
+ 0x7e14, 0x7e03, 0x7df1, 0x7ddf, 0x7dcd, 0x7dba, 0x7da7, 0x7d94,
+ 0x7d80, 0x7d6c, 0x7d58, 0x7d43, 0x7d2f, 0x7d19, 0x7d04, 0x7cee,
+ 0x7cd8, 0x7cc2, 0x7cab, 0x7c94, 0x7c7d, 0x7c66, 0x7c4e, 0x7c36,
+ 0x7c1d, 0x7c05, 0x7beb, 0x7bd2, 0x7bb9, 0x7b9f, 0x7b84, 0x7b6a,
+ 0x7b4f, 0x7b34, 0x7b19, 0x7afd, 0x7ae1, 0x7ac5, 0x7aa8, 0x7a8b,
+ 0x7a6e, 0x7a50, 0x7a33, 0x7a15, 0x79f6, 0x79d8, 0x79b9, 0x7999,
+ 0x797a, 0x795a, 0x793a, 0x7919, 0x78f9, 0x78d8, 0x78b6, 0x7895,
+ 0x7873, 0x7851, 0x782e, 0x780c, 0x77e9, 0x77c5, 0x77a2, 0x777e,
+ 0x775a, 0x7735, 0x7710, 0x76eb, 0x76c6, 0x76a0, 0x767b, 0x7654,
+ 0x762e, 0x7607, 0x75e0, 0x75b9, 0x7591, 0x7569, 0x7541, 0x7519,
+ 0x74f0, 0x74c7, 0x749e, 0x7474, 0x744a, 0x7420, 0x73f6, 0x73cb,
+ 0x73a0, 0x7375, 0x7349, 0x731d, 0x72f1, 0x72c5, 0x7298, 0x726b,
+ 0x723e, 0x7211, 0x71e3, 0x71b5, 0x7186, 0x7158, 0x7129, 0x70fa,
+ 0x70cb, 0x709b, 0x706b, 0x703b, 0x700a, 0x6fda, 0x6fa9, 0x6f77,
+ 0x6f46, 0x6f14, 0x6ee2, 0x6eaf, 0x6e7d, 0x6e4a, 0x6e17, 0x6de3,
+ 0x6db0, 0x6d7c, 0x6d48, 0x6d13, 0x6cde, 0x6ca9, 0x6c74, 0x6c3f,
+ 0x6c09, 0x6bd3, 0x6b9c, 0x6b66, 0x6b2f, 0x6af8, 0x6ac1, 0x6a89,
+ 0x6a51, 0x6a19, 0x69e1, 0x69a8, 0x696f, 0x6936, 0x68fd, 0x68c3,
+ 0x6889, 0x684f, 0x6815, 0x67da, 0x679f, 0x6764, 0x6729, 0x66ed,
+ 0x66b1, 0x6675, 0x6639, 0x65fc, 0x65bf, 0x6582, 0x6545, 0x6507,
+ 0x64c9, 0x648b, 0x644d, 0x640e, 0x63cf, 0x6390, 0x6351, 0x6311,
+ 0x62d2, 0x6292, 0x6251, 0x6211, 0x61d0, 0x618f, 0x614e, 0x610d,
+ 0x60cb, 0x6089, 0x6047, 0x6004, 0x5fc2, 0x5f7f, 0x5f3c, 0x5ef9,
+ 0x5eb5, 0x5e71, 0x5e2d, 0x5de9, 0x5da5, 0x5d60, 0x5d1b, 0x5cd6,
+ 0x5c91, 0x5c4b, 0x5c06, 0x5bc0, 0x5b79, 0x5b33, 0x5aec, 0x5aa5,
+ 0x5a5e, 0x5a17, 0x59d0, 0x5988, 0x5940, 0x58f8, 0x58af, 0x5867,
+ 0x581e, 0x57d5, 0x578c, 0x5742, 0x56f9, 0x56af, 0x5665, 0x561a,
+ 0x55d0, 0x5585, 0x553a, 0x54ef, 0x54a4, 0x5458, 0x540d, 0x53c1,
+ 0x5375, 0x5328, 0x52dc, 0x528f, 0x5242, 0x51f5, 0x51a8, 0x515a,
+ 0x510c, 0x50bf, 0x5070, 0x5022, 0x4fd4, 0x4f85, 0x4f36, 0x4ee7,
+ 0x4e98, 0x4e48, 0x4df9, 0x4da9, 0x4d59, 0x4d09, 0x4cb8, 0x4c68,
+ 0x4c17, 0x4bc6, 0x4b75, 0x4b24, 0x4ad2, 0x4a81, 0x4a2f, 0x49dd,
+ 0x498a, 0x4938, 0x48e6, 0x4893, 0x4840, 0x47ed, 0x479a, 0x4746,
+ 0x46f3, 0x469f, 0x464b, 0x45f7, 0x45a3, 0x454e, 0x44fa, 0x44a5,
+ 0x4450, 0x43fb, 0x43a5, 0x4350, 0x42fa, 0x42a5, 0x424f, 0x41f9,
+ 0x41a2, 0x414c, 0x40f6, 0x409f, 0x4048, 0x3ff1, 0x3f9a, 0x3f43,
+ 0x3eeb, 0x3e93, 0x3e3c, 0x3de4, 0x3d8c, 0x3d33, 0x3cdb, 0x3c83,
+ 0x3c2a, 0x3bd1, 0x3b78, 0x3b1f, 0x3ac6, 0x3a6c, 0x3a13, 0x39b9,
+ 0x395f, 0x3906, 0x38ab, 0x3851, 0x37f7, 0x379c, 0x3742, 0x36e7,
+ 0x368c, 0x3631, 0x35d6, 0x357b, 0x351f, 0x34c4, 0x3468, 0x340c,
+ 0x33b0, 0x3354, 0x32f8, 0x329c, 0x3240, 0x31e3, 0x3186, 0x312a,
+ 0x30cd, 0x3070, 0x3013, 0x2fb5, 0x2f58, 0x2efb, 0x2e9d, 0x2e3f,
+ 0x2de2, 0x2d84, 0x2d26, 0x2cc8, 0x2c69, 0x2c0b, 0x2bad, 0x2b4e,
+ 0x2aef, 0x2a91, 0x2a32, 0x29d3, 0x2974, 0x2915, 0x28b5, 0x2856,
+ 0x27f6, 0x2797, 0x2737, 0x26d8, 0x2678, 0x2618, 0x25b8, 0x2558,
+ 0x24f7, 0x2497, 0x2437, 0x23d6, 0x2376, 0x2315, 0x22b4, 0x2254,
+ 0x21f3, 0x2192, 0x2131, 0x20d0, 0x206e, 0x200d, 0x1fac, 0x1f4a,
+ 0x1ee9, 0x1e87, 0x1e25, 0x1dc4, 0x1d62, 0x1d00, 0x1c9e, 0x1c3c,
+ 0x1bda, 0x1b78, 0x1b16, 0x1ab3, 0x1a51, 0x19ef, 0x198c, 0x192a,
+ 0x18c7, 0x1864, 0x1802, 0x179f, 0x173c, 0x16d9, 0x1676, 0x1613,
+ 0x15b0, 0x154d, 0x14ea, 0x1487, 0x1423, 0x13c0, 0x135d, 0x12f9,
+ 0x1296, 0x1232, 0x11cf, 0x116b, 0x1108, 0x10a4, 0x1040, 0xfdd,
+ 0xf79, 0xf15, 0xeb1, 0xe4d, 0xde9, 0xd85, 0xd21, 0xcbd,
+ 0xc59, 0xbf5, 0xb91, 0xb2d, 0xac9, 0xa65, 0xa00, 0x99c,
+ 0x938, 0x8d4, 0x86f, 0x80b, 0x7a7, 0x742, 0x6de, 0x67a,
+ 0x615, 0x5b1, 0x54c, 0x4e8, 0x483, 0x41f, 0x3ba, 0x356,
+ 0x2f1, 0x28d, 0x228, 0x1c4, 0x15f, 0xfb, 0x96, 0x32,
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_2048[2048] = {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd,
+ 0x7ffd, 0x7ffd, 0x7ffc, 0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa,
+ 0x7ffa, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff6,
+ 0x7ff5, 0x7ff5, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff1, 0x7ff0,
+ 0x7ff0, 0x7fef, 0x7fee, 0x7fed, 0x7fec, 0x7fec, 0x7feb, 0x7fea,
+ 0x7fe9, 0x7fe8, 0x7fe7, 0x7fe6, 0x7fe5, 0x7fe4, 0x7fe3, 0x7fe2,
+ 0x7fe1, 0x7fe0, 0x7fdf, 0x7fdd, 0x7fdc, 0x7fdb, 0x7fda, 0x7fd9,
+ 0x7fd7, 0x7fd6, 0x7fd5, 0x7fd4, 0x7fd2, 0x7fd1, 0x7fd0, 0x7fce,
+ 0x7fcd, 0x7fcb, 0x7fca, 0x7fc9, 0x7fc7, 0x7fc6, 0x7fc4, 0x7fc3,
+ 0x7fc1, 0x7fc0, 0x7fbe, 0x7fbc, 0x7fbb, 0x7fb9, 0x7fb7, 0x7fb6,
+ 0x7fb4, 0x7fb2, 0x7fb1, 0x7faf, 0x7fad, 0x7fab, 0x7fa9, 0x7fa8,
+ 0x7fa6, 0x7fa4, 0x7fa2, 0x7fa0, 0x7f9e, 0x7f9c, 0x7f9a, 0x7f98,
+ 0x7f96, 0x7f94, 0x7f92, 0x7f90, 0x7f8e, 0x7f8c, 0x7f8a, 0x7f88,
+ 0x7f86, 0x7f83, 0x7f81, 0x7f7f, 0x7f7d, 0x7f7b, 0x7f78, 0x7f76,
+ 0x7f74, 0x7f71, 0x7f6f, 0x7f6d, 0x7f6a, 0x7f68, 0x7f65, 0x7f63,
+ 0x7f60, 0x7f5e, 0x7f5b, 0x7f59, 0x7f56, 0x7f54, 0x7f51, 0x7f4f,
+ 0x7f4c, 0x7f49, 0x7f47, 0x7f44, 0x7f41, 0x7f3f, 0x7f3c, 0x7f39,
+ 0x7f36, 0x7f34, 0x7f31, 0x7f2e, 0x7f2b, 0x7f28, 0x7f25, 0x7f23,
+ 0x7f20, 0x7f1d, 0x7f1a, 0x7f17, 0x7f14, 0x7f11, 0x7f0e, 0x7f0b,
+ 0x7f08, 0x7f04, 0x7f01, 0x7efe, 0x7efb, 0x7ef8, 0x7ef5, 0x7ef1,
+ 0x7eee, 0x7eeb, 0x7ee8, 0x7ee4, 0x7ee1, 0x7ede, 0x7eda, 0x7ed7,
+ 0x7ed4, 0x7ed0, 0x7ecd, 0x7ec9, 0x7ec6, 0x7ec3, 0x7ebf, 0x7ebb,
+ 0x7eb8, 0x7eb4, 0x7eb1, 0x7ead, 0x7eaa, 0x7ea6, 0x7ea2, 0x7e9f,
+ 0x7e9b, 0x7e97, 0x7e94, 0x7e90, 0x7e8c, 0x7e88, 0x7e84, 0x7e81,
+ 0x7e7d, 0x7e79, 0x7e75, 0x7e71, 0x7e6d, 0x7e69, 0x7e65, 0x7e61,
+ 0x7e5d, 0x7e59, 0x7e55, 0x7e51, 0x7e4d, 0x7e49, 0x7e45, 0x7e41,
+ 0x7e3d, 0x7e39, 0x7e34, 0x7e30, 0x7e2c, 0x7e28, 0x7e24, 0x7e1f,
+ 0x7e1b, 0x7e17, 0x7e12, 0x7e0e, 0x7e0a, 0x7e05, 0x7e01, 0x7dfc,
+ 0x7df8, 0x7df3, 0x7def, 0x7dea, 0x7de6, 0x7de1, 0x7ddd, 0x7dd8,
+ 0x7dd4, 0x7dcf, 0x7dca, 0x7dc6, 0x7dc1, 0x7dbc, 0x7db8, 0x7db3,
+ 0x7dae, 0x7da9, 0x7da5, 0x7da0, 0x7d9b, 0x7d96, 0x7d91, 0x7d8c,
+ 0x7d87, 0x7d82, 0x7d7e, 0x7d79, 0x7d74, 0x7d6f, 0x7d6a, 0x7d65,
+ 0x7d60, 0x7d5a, 0x7d55, 0x7d50, 0x7d4b, 0x7d46, 0x7d41, 0x7d3c,
+ 0x7d36, 0x7d31, 0x7d2c, 0x7d27, 0x7d21, 0x7d1c, 0x7d17, 0x7d11,
+ 0x7d0c, 0x7d07, 0x7d01, 0x7cfc, 0x7cf6, 0x7cf1, 0x7cec, 0x7ce6,
+ 0x7ce1, 0x7cdb, 0x7cd5, 0x7cd0, 0x7cca, 0x7cc5, 0x7cbf, 0x7cb9,
+ 0x7cb4, 0x7cae, 0x7ca8, 0x7ca3, 0x7c9d, 0x7c97, 0x7c91, 0x7c8c,
+ 0x7c86, 0x7c80, 0x7c7a, 0x7c74, 0x7c6e, 0x7c69, 0x7c63, 0x7c5d,
+ 0x7c57, 0x7c51, 0x7c4b, 0x7c45, 0x7c3f, 0x7c39, 0x7c33, 0x7c2d,
+ 0x7c26, 0x7c20, 0x7c1a, 0x7c14, 0x7c0e, 0x7c08, 0x7c01, 0x7bfb,
+ 0x7bf5, 0x7bef, 0x7be8, 0x7be2, 0x7bdc, 0x7bd5, 0x7bcf, 0x7bc9,
+ 0x7bc2, 0x7bbc, 0x7bb5, 0x7baf, 0x7ba8, 0x7ba2, 0x7b9b, 0x7b95,
+ 0x7b8e, 0x7b88, 0x7b81, 0x7b7a, 0x7b74, 0x7b6d, 0x7b67, 0x7b60,
+ 0x7b59, 0x7b52, 0x7b4c, 0x7b45, 0x7b3e, 0x7b37, 0x7b31, 0x7b2a,
+ 0x7b23, 0x7b1c, 0x7b15, 0x7b0e, 0x7b07, 0x7b00, 0x7af9, 0x7af2,
+ 0x7aeb, 0x7ae4, 0x7add, 0x7ad6, 0x7acf, 0x7ac8, 0x7ac1, 0x7aba,
+ 0x7ab3, 0x7aac, 0x7aa4, 0x7a9d, 0x7a96, 0x7a8f, 0x7a87, 0x7a80,
+ 0x7a79, 0x7a72, 0x7a6a, 0x7a63, 0x7a5c, 0x7a54, 0x7a4d, 0x7a45,
+ 0x7a3e, 0x7a36, 0x7a2f, 0x7a27, 0x7a20, 0x7a18, 0x7a11, 0x7a09,
+ 0x7a02, 0x79fa, 0x79f2, 0x79eb, 0x79e3, 0x79db, 0x79d4, 0x79cc,
+ 0x79c4, 0x79bc, 0x79b5, 0x79ad, 0x79a5, 0x799d, 0x7995, 0x798e,
+ 0x7986, 0x797e, 0x7976, 0x796e, 0x7966, 0x795e, 0x7956, 0x794e,
+ 0x7946, 0x793e, 0x7936, 0x792e, 0x7926, 0x791e, 0x7915, 0x790d,
+ 0x7905, 0x78fd, 0x78f5, 0x78ec, 0x78e4, 0x78dc, 0x78d4, 0x78cb,
+ 0x78c3, 0x78bb, 0x78b2, 0x78aa, 0x78a2, 0x7899, 0x7891, 0x7888,
+ 0x7880, 0x7877, 0x786f, 0x7866, 0x785e, 0x7855, 0x784d, 0x7844,
+ 0x783b, 0x7833, 0x782a, 0x7821, 0x7819, 0x7810, 0x7807, 0x77ff,
+ 0x77f6, 0x77ed, 0x77e4, 0x77db, 0x77d3, 0x77ca, 0x77c1, 0x77b8,
+ 0x77af, 0x77a6, 0x779d, 0x7794, 0x778b, 0x7782, 0x7779, 0x7770,
+ 0x7767, 0x775e, 0x7755, 0x774c, 0x7743, 0x773a, 0x7731, 0x7727,
+ 0x771e, 0x7715, 0x770c, 0x7703, 0x76f9, 0x76f0, 0x76e7, 0x76dd,
+ 0x76d4, 0x76cb, 0x76c1, 0x76b8, 0x76af, 0x76a5, 0x769c, 0x7692,
+ 0x7689, 0x767f, 0x7676, 0x766c, 0x7663, 0x7659, 0x7650, 0x7646,
+ 0x763c, 0x7633, 0x7629, 0x761f, 0x7616, 0x760c, 0x7602, 0x75f9,
+ 0x75ef, 0x75e5, 0x75db, 0x75d1, 0x75c8, 0x75be, 0x75b4, 0x75aa,
+ 0x75a0, 0x7596, 0x758c, 0x7582, 0x7578, 0x756e, 0x7564, 0x755a,
+ 0x7550, 0x7546, 0x753c, 0x7532, 0x7528, 0x751e, 0x7514, 0x7509,
+ 0x74ff, 0x74f5, 0x74eb, 0x74e1, 0x74d6, 0x74cc, 0x74c2, 0x74b7,
+ 0x74ad, 0x74a3, 0x7498, 0x748e, 0x7484, 0x7479, 0x746f, 0x7464,
+ 0x745a, 0x744f, 0x7445, 0x743a, 0x7430, 0x7425, 0x741b, 0x7410,
+ 0x7406, 0x73fb, 0x73f0, 0x73e6, 0x73db, 0x73d0, 0x73c6, 0x73bb,
+ 0x73b0, 0x73a5, 0x739b, 0x7390, 0x7385, 0x737a, 0x736f, 0x7364,
+ 0x7359, 0x734f, 0x7344, 0x7339, 0x732e, 0x7323, 0x7318, 0x730d,
+ 0x7302, 0x72f7, 0x72ec, 0x72e1, 0x72d5, 0x72ca, 0x72bf, 0x72b4,
+ 0x72a9, 0x729e, 0x7293, 0x7287, 0x727c, 0x7271, 0x7266, 0x725a,
+ 0x724f, 0x7244, 0x7238, 0x722d, 0x7222, 0x7216, 0x720b, 0x71ff,
+ 0x71f4, 0x71e9, 0x71dd, 0x71d2, 0x71c6, 0x71bb, 0x71af, 0x71a3,
+ 0x7198, 0x718c, 0x7181, 0x7175, 0x7169, 0x715e, 0x7152, 0x7146,
+ 0x713b, 0x712f, 0x7123, 0x7117, 0x710c, 0x7100, 0x70f4, 0x70e8,
+ 0x70dc, 0x70d1, 0x70c5, 0x70b9, 0x70ad, 0x70a1, 0x7095, 0x7089,
+ 0x707d, 0x7071, 0x7065, 0x7059, 0x704d, 0x7041, 0x7035, 0x7029,
+ 0x701d, 0x7010, 0x7004, 0x6ff8, 0x6fec, 0x6fe0, 0x6fd3, 0x6fc7,
+ 0x6fbb, 0x6faf, 0x6fa2, 0x6f96, 0x6f8a, 0x6f7d, 0x6f71, 0x6f65,
+ 0x6f58, 0x6f4c, 0x6f3f, 0x6f33, 0x6f27, 0x6f1a, 0x6f0e, 0x6f01,
+ 0x6ef5, 0x6ee8, 0x6edc, 0x6ecf, 0x6ec2, 0x6eb6, 0x6ea9, 0x6e9c,
+ 0x6e90, 0x6e83, 0x6e76, 0x6e6a, 0x6e5d, 0x6e50, 0x6e44, 0x6e37,
+ 0x6e2a, 0x6e1d, 0x6e10, 0x6e04, 0x6df7, 0x6dea, 0x6ddd, 0x6dd0,
+ 0x6dc3, 0x6db6, 0x6da9, 0x6d9c, 0x6d8f, 0x6d82, 0x6d75, 0x6d68,
+ 0x6d5b, 0x6d4e, 0x6d41, 0x6d34, 0x6d27, 0x6d1a, 0x6d0c, 0x6cff,
+ 0x6cf2, 0x6ce5, 0x6cd8, 0x6cca, 0x6cbd, 0x6cb0, 0x6ca3, 0x6c95,
+ 0x6c88, 0x6c7b, 0x6c6d, 0x6c60, 0x6c53, 0x6c45, 0x6c38, 0x6c2a,
+ 0x6c1d, 0x6c0f, 0x6c02, 0x6bf5, 0x6be7, 0x6bd9, 0x6bcc, 0x6bbe,
+ 0x6bb1, 0x6ba3, 0x6b96, 0x6b88, 0x6b7a, 0x6b6d, 0x6b5f, 0x6b51,
+ 0x6b44, 0x6b36, 0x6b28, 0x6b1a, 0x6b0d, 0x6aff, 0x6af1, 0x6ae3,
+ 0x6ad5, 0x6ac8, 0x6aba, 0x6aac, 0x6a9e, 0x6a90, 0x6a82, 0x6a74,
+ 0x6a66, 0x6a58, 0x6a4a, 0x6a3c, 0x6a2e, 0x6a20, 0x6a12, 0x6a04,
+ 0x69f6, 0x69e8, 0x69da, 0x69cb, 0x69bd, 0x69af, 0x69a1, 0x6993,
+ 0x6985, 0x6976, 0x6968, 0x695a, 0x694b, 0x693d, 0x692f, 0x6921,
+ 0x6912, 0x6904, 0x68f5, 0x68e7, 0x68d9, 0x68ca, 0x68bc, 0x68ad,
+ 0x689f, 0x6890, 0x6882, 0x6873, 0x6865, 0x6856, 0x6848, 0x6839,
+ 0x682b, 0x681c, 0x680d, 0x67ff, 0x67f0, 0x67e1, 0x67d3, 0x67c4,
+ 0x67b5, 0x67a6, 0x6798, 0x6789, 0x677a, 0x676b, 0x675d, 0x674e,
+ 0x673f, 0x6730, 0x6721, 0x6712, 0x6703, 0x66f4, 0x66e5, 0x66d6,
+ 0x66c8, 0x66b9, 0x66aa, 0x669b, 0x668b, 0x667c, 0x666d, 0x665e,
+ 0x664f, 0x6640, 0x6631, 0x6622, 0x6613, 0x6603, 0x65f4, 0x65e5,
+ 0x65d6, 0x65c7, 0x65b7, 0x65a8, 0x6599, 0x658a, 0x657a, 0x656b,
+ 0x655c, 0x654c, 0x653d, 0x652d, 0x651e, 0x650f, 0x64ff, 0x64f0,
+ 0x64e0, 0x64d1, 0x64c1, 0x64b2, 0x64a2, 0x6493, 0x6483, 0x6474,
+ 0x6464, 0x6454, 0x6445, 0x6435, 0x6426, 0x6416, 0x6406, 0x63f7,
+ 0x63e7, 0x63d7, 0x63c7, 0x63b8, 0x63a8, 0x6398, 0x6388, 0x6378,
+ 0x6369, 0x6359, 0x6349, 0x6339, 0x6329, 0x6319, 0x6309, 0x62f9,
+ 0x62ea, 0x62da, 0x62ca, 0x62ba, 0x62aa, 0x629a, 0x628a, 0x627a,
+ 0x6269, 0x6259, 0x6249, 0x6239, 0x6229, 0x6219, 0x6209, 0x61f9,
+ 0x61e8, 0x61d8, 0x61c8, 0x61b8, 0x61a8, 0x6197, 0x6187, 0x6177,
+ 0x6166, 0x6156, 0x6146, 0x6135, 0x6125, 0x6115, 0x6104, 0x60f4,
+ 0x60e4, 0x60d3, 0x60c3, 0x60b2, 0x60a2, 0x6091, 0x6081, 0x6070,
+ 0x6060, 0x604f, 0x603f, 0x602e, 0x601d, 0x600d, 0x5ffc, 0x5fec,
+ 0x5fdb, 0x5fca, 0x5fba, 0x5fa9, 0x5f98, 0x5f87, 0x5f77, 0x5f66,
+ 0x5f55, 0x5f44, 0x5f34, 0x5f23, 0x5f12, 0x5f01, 0x5ef0, 0x5edf,
+ 0x5ecf, 0x5ebe, 0x5ead, 0x5e9c, 0x5e8b, 0x5e7a, 0x5e69, 0x5e58,
+ 0x5e47, 0x5e36, 0x5e25, 0x5e14, 0x5e03, 0x5df2, 0x5de1, 0x5dd0,
+ 0x5dbf, 0x5dad, 0x5d9c, 0x5d8b, 0x5d7a, 0x5d69, 0x5d58, 0x5d46,
+ 0x5d35, 0x5d24, 0x5d13, 0x5d01, 0x5cf0, 0x5cdf, 0x5cce, 0x5cbc,
+ 0x5cab, 0x5c9a, 0x5c88, 0x5c77, 0x5c66, 0x5c54, 0x5c43, 0x5c31,
+ 0x5c20, 0x5c0e, 0x5bfd, 0x5beb, 0x5bda, 0x5bc8, 0x5bb7, 0x5ba5,
+ 0x5b94, 0x5b82, 0x5b71, 0x5b5f, 0x5b4d, 0x5b3c, 0x5b2a, 0x5b19,
+ 0x5b07, 0x5af5, 0x5ae4, 0x5ad2, 0x5ac0, 0x5aae, 0x5a9d, 0x5a8b,
+ 0x5a79, 0x5a67, 0x5a56, 0x5a44, 0x5a32, 0x5a20, 0x5a0e, 0x59fc,
+ 0x59ea, 0x59d9, 0x59c7, 0x59b5, 0x59a3, 0x5991, 0x597f, 0x596d,
+ 0x595b, 0x5949, 0x5937, 0x5925, 0x5913, 0x5901, 0x58ef, 0x58dd,
+ 0x58cb, 0x58b8, 0x58a6, 0x5894, 0x5882, 0x5870, 0x585e, 0x584b,
+ 0x5839, 0x5827, 0x5815, 0x5803, 0x57f0, 0x57de, 0x57cc, 0x57b9,
+ 0x57a7, 0x5795, 0x5783, 0x5770, 0x575e, 0x574b, 0x5739, 0x5727,
+ 0x5714, 0x5702, 0x56ef, 0x56dd, 0x56ca, 0x56b8, 0x56a5, 0x5693,
+ 0x5680, 0x566e, 0x565b, 0x5649, 0x5636, 0x5624, 0x5611, 0x55fe,
+ 0x55ec, 0x55d9, 0x55c7, 0x55b4, 0x55a1, 0x558f, 0x557c, 0x5569,
+ 0x5556, 0x5544, 0x5531, 0x551e, 0x550b, 0x54f9, 0x54e6, 0x54d3,
+ 0x54c0, 0x54ad, 0x549a, 0x5488, 0x5475, 0x5462, 0x544f, 0x543c,
+ 0x5429, 0x5416, 0x5403, 0x53f0, 0x53dd, 0x53ca, 0x53b7, 0x53a4,
+ 0x5391, 0x537e, 0x536b, 0x5358, 0x5345, 0x5332, 0x531f, 0x530c,
+ 0x52f8, 0x52e5, 0x52d2, 0x52bf, 0x52ac, 0x5299, 0x5285, 0x5272,
+ 0x525f, 0x524c, 0x5238, 0x5225, 0x5212, 0x51ff, 0x51eb, 0x51d8,
+ 0x51c5, 0x51b1, 0x519e, 0x518b, 0x5177, 0x5164, 0x5150, 0x513d,
+ 0x512a, 0x5116, 0x5103, 0x50ef, 0x50dc, 0x50c8, 0x50b5, 0x50a1,
+ 0x508e, 0x507a, 0x5067, 0x5053, 0x503f, 0x502c, 0x5018, 0x5005,
+ 0x4ff1, 0x4fdd, 0x4fca, 0x4fb6, 0x4fa2, 0x4f8f, 0x4f7b, 0x4f67,
+ 0x4f54, 0x4f40, 0x4f2c, 0x4f18, 0x4f05, 0x4ef1, 0x4edd, 0x4ec9,
+ 0x4eb6, 0x4ea2, 0x4e8e, 0x4e7a, 0x4e66, 0x4e52, 0x4e3e, 0x4e2a,
+ 0x4e17, 0x4e03, 0x4def, 0x4ddb, 0x4dc7, 0x4db3, 0x4d9f, 0x4d8b,
+ 0x4d77, 0x4d63, 0x4d4f, 0x4d3b, 0x4d27, 0x4d13, 0x4cff, 0x4ceb,
+ 0x4cd6, 0x4cc2, 0x4cae, 0x4c9a, 0x4c86, 0x4c72, 0x4c5e, 0x4c49,
+ 0x4c35, 0x4c21, 0x4c0d, 0x4bf9, 0x4be4, 0x4bd0, 0x4bbc, 0x4ba8,
+ 0x4b93, 0x4b7f, 0x4b6b, 0x4b56, 0x4b42, 0x4b2e, 0x4b19, 0x4b05,
+ 0x4af1, 0x4adc, 0x4ac8, 0x4ab4, 0x4a9f, 0x4a8b, 0x4a76, 0x4a62,
+ 0x4a4d, 0x4a39, 0x4a24, 0x4a10, 0x49fb, 0x49e7, 0x49d2, 0x49be,
+ 0x49a9, 0x4995, 0x4980, 0x496c, 0x4957, 0x4942, 0x492e, 0x4919,
+ 0x4905, 0x48f0, 0x48db, 0x48c7, 0x48b2, 0x489d, 0x4888, 0x4874,
+ 0x485f, 0x484a, 0x4836, 0x4821, 0x480c, 0x47f7, 0x47e2, 0x47ce,
+ 0x47b9, 0x47a4, 0x478f, 0x477a, 0x4765, 0x4751, 0x473c, 0x4727,
+ 0x4712, 0x46fd, 0x46e8, 0x46d3, 0x46be, 0x46a9, 0x4694, 0x467f,
+ 0x466a, 0x4655, 0x4640, 0x462b, 0x4616, 0x4601, 0x45ec, 0x45d7,
+ 0x45c2, 0x45ad, 0x4598, 0x4583, 0x456e, 0x4559, 0x4544, 0x452e,
+ 0x4519, 0x4504, 0x44ef, 0x44da, 0x44c5, 0x44af, 0x449a, 0x4485,
+ 0x4470, 0x445a, 0x4445, 0x4430, 0x441b, 0x4405, 0x43f0, 0x43db,
+ 0x43c5, 0x43b0, 0x439b, 0x4385, 0x4370, 0x435b, 0x4345, 0x4330,
+ 0x431b, 0x4305, 0x42f0, 0x42da, 0x42c5, 0x42af, 0x429a, 0x4284,
+ 0x426f, 0x425a, 0x4244, 0x422f, 0x4219, 0x4203, 0x41ee, 0x41d8,
+ 0x41c3, 0x41ad, 0x4198, 0x4182, 0x416d, 0x4157, 0x4141, 0x412c,
+ 0x4116, 0x4100, 0x40eb, 0x40d5, 0x40bf, 0x40aa, 0x4094, 0x407e,
+ 0x4069, 0x4053, 0x403d, 0x4027, 0x4012, 0x3ffc, 0x3fe6, 0x3fd0,
+ 0x3fbb, 0x3fa5, 0x3f8f, 0x3f79, 0x3f63, 0x3f4d, 0x3f38, 0x3f22,
+ 0x3f0c, 0x3ef6, 0x3ee0, 0x3eca, 0x3eb4, 0x3e9e, 0x3e88, 0x3e73,
+ 0x3e5d, 0x3e47, 0x3e31, 0x3e1b, 0x3e05, 0x3def, 0x3dd9, 0x3dc3,
+ 0x3dad, 0x3d97, 0x3d81, 0x3d6b, 0x3d55, 0x3d3e, 0x3d28, 0x3d12,
+ 0x3cfc, 0x3ce6, 0x3cd0, 0x3cba, 0x3ca4, 0x3c8e, 0x3c77, 0x3c61,
+ 0x3c4b, 0x3c35, 0x3c1f, 0x3c09, 0x3bf2, 0x3bdc, 0x3bc6, 0x3bb0,
+ 0x3b99, 0x3b83, 0x3b6d, 0x3b57, 0x3b40, 0x3b2a, 0x3b14, 0x3afe,
+ 0x3ae7, 0x3ad1, 0x3abb, 0x3aa4, 0x3a8e, 0x3a78, 0x3a61, 0x3a4b,
+ 0x3a34, 0x3a1e, 0x3a08, 0x39f1, 0x39db, 0x39c4, 0x39ae, 0x3998,
+ 0x3981, 0x396b, 0x3954, 0x393e, 0x3927, 0x3911, 0x38fa, 0x38e4,
+ 0x38cd, 0x38b7, 0x38a0, 0x388a, 0x3873, 0x385d, 0x3846, 0x382f,
+ 0x3819, 0x3802, 0x37ec, 0x37d5, 0x37be, 0x37a8, 0x3791, 0x377a,
+ 0x3764, 0x374d, 0x3736, 0x3720, 0x3709, 0x36f2, 0x36dc, 0x36c5,
+ 0x36ae, 0x3698, 0x3681, 0x366a, 0x3653, 0x363d, 0x3626, 0x360f,
+ 0x35f8, 0x35e1, 0x35cb, 0x35b4, 0x359d, 0x3586, 0x356f, 0x3558,
+ 0x3542, 0x352b, 0x3514, 0x34fd, 0x34e6, 0x34cf, 0x34b8, 0x34a1,
+ 0x348b, 0x3474, 0x345d, 0x3446, 0x342f, 0x3418, 0x3401, 0x33ea,
+ 0x33d3, 0x33bc, 0x33a5, 0x338e, 0x3377, 0x3360, 0x3349, 0x3332,
+ 0x331b, 0x3304, 0x32ed, 0x32d6, 0x32bf, 0x32a8, 0x3290, 0x3279,
+ 0x3262, 0x324b, 0x3234, 0x321d, 0x3206, 0x31ef, 0x31d8, 0x31c0,
+ 0x31a9, 0x3192, 0x317b, 0x3164, 0x314c, 0x3135, 0x311e, 0x3107,
+ 0x30f0, 0x30d8, 0x30c1, 0x30aa, 0x3093, 0x307b, 0x3064, 0x304d,
+ 0x3036, 0x301e, 0x3007, 0x2ff0, 0x2fd8, 0x2fc1, 0x2faa, 0x2f92,
+ 0x2f7b, 0x2f64, 0x2f4c, 0x2f35, 0x2f1e, 0x2f06, 0x2eef, 0x2ed8,
+ 0x2ec0, 0x2ea9, 0x2e91, 0x2e7a, 0x2e63, 0x2e4b, 0x2e34, 0x2e1c,
+ 0x2e05, 0x2ded, 0x2dd6, 0x2dbe, 0x2da7, 0x2d8f, 0x2d78, 0x2d60,
+ 0x2d49, 0x2d31, 0x2d1a, 0x2d02, 0x2ceb, 0x2cd3, 0x2cbc, 0x2ca4,
+ 0x2c8d, 0x2c75, 0x2c5e, 0x2c46, 0x2c2e, 0x2c17, 0x2bff, 0x2be8,
+ 0x2bd0, 0x2bb8, 0x2ba1, 0x2b89, 0x2b71, 0x2b5a, 0x2b42, 0x2b2b,
+ 0x2b13, 0x2afb, 0x2ae4, 0x2acc, 0x2ab4, 0x2a9c, 0x2a85, 0x2a6d,
+ 0x2a55, 0x2a3e, 0x2a26, 0x2a0e, 0x29f6, 0x29df, 0x29c7, 0x29af,
+ 0x2997, 0x2980, 0x2968, 0x2950, 0x2938, 0x2920, 0x2909, 0x28f1,
+ 0x28d9, 0x28c1, 0x28a9, 0x2892, 0x287a, 0x2862, 0x284a, 0x2832,
+ 0x281a, 0x2802, 0x27eb, 0x27d3, 0x27bb, 0x27a3, 0x278b, 0x2773,
+ 0x275b, 0x2743, 0x272b, 0x2713, 0x26fb, 0x26e4, 0x26cc, 0x26b4,
+ 0x269c, 0x2684, 0x266c, 0x2654, 0x263c, 0x2624, 0x260c, 0x25f4,
+ 0x25dc, 0x25c4, 0x25ac, 0x2594, 0x257c, 0x2564, 0x254c, 0x2534,
+ 0x251c, 0x2503, 0x24eb, 0x24d3, 0x24bb, 0x24a3, 0x248b, 0x2473,
+ 0x245b, 0x2443, 0x242b, 0x2413, 0x23fa, 0x23e2, 0x23ca, 0x23b2,
+ 0x239a, 0x2382, 0x236a, 0x2352, 0x2339, 0x2321, 0x2309, 0x22f1,
+ 0x22d9, 0x22c0, 0x22a8, 0x2290, 0x2278, 0x2260, 0x2247, 0x222f,
+ 0x2217, 0x21ff, 0x21e7, 0x21ce, 0x21b6, 0x219e, 0x2186, 0x216d,
+ 0x2155, 0x213d, 0x2125, 0x210c, 0x20f4, 0x20dc, 0x20c3, 0x20ab,
+ 0x2093, 0x207a, 0x2062, 0x204a, 0x2032, 0x2019, 0x2001, 0x1fe9,
+ 0x1fd0, 0x1fb8, 0x1f9f, 0x1f87, 0x1f6f, 0x1f56, 0x1f3e, 0x1f26,
+ 0x1f0d, 0x1ef5, 0x1edd, 0x1ec4, 0x1eac, 0x1e93, 0x1e7b, 0x1e62,
+ 0x1e4a, 0x1e32, 0x1e19, 0x1e01, 0x1de8, 0x1dd0, 0x1db7, 0x1d9f,
+ 0x1d87, 0x1d6e, 0x1d56, 0x1d3d, 0x1d25, 0x1d0c, 0x1cf4, 0x1cdb,
+ 0x1cc3, 0x1caa, 0x1c92, 0x1c79, 0x1c61, 0x1c48, 0x1c30, 0x1c17,
+ 0x1bff, 0x1be6, 0x1bce, 0x1bb5, 0x1b9d, 0x1b84, 0x1b6c, 0x1b53,
+ 0x1b3a, 0x1b22, 0x1b09, 0x1af1, 0x1ad8, 0x1ac0, 0x1aa7, 0x1a8e,
+ 0x1a76, 0x1a5d, 0x1a45, 0x1a2c, 0x1a13, 0x19fb, 0x19e2, 0x19ca,
+ 0x19b1, 0x1998, 0x1980, 0x1967, 0x194e, 0x1936, 0x191d, 0x1905,
+ 0x18ec, 0x18d3, 0x18bb, 0x18a2, 0x1889, 0x1871, 0x1858, 0x183f,
+ 0x1827, 0x180e, 0x17f5, 0x17dd, 0x17c4, 0x17ab, 0x1792, 0x177a,
+ 0x1761, 0x1748, 0x1730, 0x1717, 0x16fe, 0x16e5, 0x16cd, 0x16b4,
+ 0x169b, 0x1682, 0x166a, 0x1651, 0x1638, 0x161f, 0x1607, 0x15ee,
+ 0x15d5, 0x15bc, 0x15a4, 0x158b, 0x1572, 0x1559, 0x1541, 0x1528,
+ 0x150f, 0x14f6, 0x14dd, 0x14c5, 0x14ac, 0x1493, 0x147a, 0x1461,
+ 0x1449, 0x1430, 0x1417, 0x13fe, 0x13e5, 0x13cc, 0x13b4, 0x139b,
+ 0x1382, 0x1369, 0x1350, 0x1337, 0x131f, 0x1306, 0x12ed, 0x12d4,
+ 0x12bb, 0x12a2, 0x1289, 0x1271, 0x1258, 0x123f, 0x1226, 0x120d,
+ 0x11f4, 0x11db, 0x11c2, 0x11a9, 0x1191, 0x1178, 0x115f, 0x1146,
+ 0x112d, 0x1114, 0x10fb, 0x10e2, 0x10c9, 0x10b0, 0x1098, 0x107f,
+ 0x1066, 0x104d, 0x1034, 0x101b, 0x1002, 0xfe9, 0xfd0, 0xfb7,
+ 0xf9e, 0xf85, 0xf6c, 0xf53, 0xf3a, 0xf21, 0xf08, 0xef0,
+ 0xed7, 0xebe, 0xea5, 0xe8c, 0xe73, 0xe5a, 0xe41, 0xe28,
+ 0xe0f, 0xdf6, 0xddd, 0xdc4, 0xdab, 0xd92, 0xd79, 0xd60,
+ 0xd47, 0xd2e, 0xd15, 0xcfc, 0xce3, 0xcca, 0xcb1, 0xc98,
+ 0xc7f, 0xc66, 0xc4d, 0xc34, 0xc1b, 0xc02, 0xbe9, 0xbd0,
+ 0xbb7, 0xb9e, 0xb85, 0xb6c, 0xb53, 0xb3a, 0xb20, 0xb07,
+ 0xaee, 0xad5, 0xabc, 0xaa3, 0xa8a, 0xa71, 0xa58, 0xa3f,
+ 0xa26, 0xa0d, 0x9f4, 0x9db, 0x9c2, 0x9a9, 0x990, 0x977,
+ 0x95e, 0x944, 0x92b, 0x912, 0x8f9, 0x8e0, 0x8c7, 0x8ae,
+ 0x895, 0x87c, 0x863, 0x84a, 0x831, 0x818, 0x7fe, 0x7e5,
+ 0x7cc, 0x7b3, 0x79a, 0x781, 0x768, 0x74f, 0x736, 0x71d,
+ 0x704, 0x6ea, 0x6d1, 0x6b8, 0x69f, 0x686, 0x66d, 0x654,
+ 0x63b, 0x622, 0x609, 0x5ef, 0x5d6, 0x5bd, 0x5a4, 0x58b,
+ 0x572, 0x559, 0x540, 0x527, 0x50d, 0x4f4, 0x4db, 0x4c2,
+ 0x4a9, 0x490, 0x477, 0x45e, 0x445, 0x42b, 0x412, 0x3f9,
+ 0x3e0, 0x3c7, 0x3ae, 0x395, 0x37c, 0x362, 0x349, 0x330,
+ 0x317, 0x2fe, 0x2e5, 0x2cc, 0x2b3, 0x299, 0x280, 0x267,
+ 0x24e, 0x235, 0x21c, 0x203, 0x1ea, 0x1d0, 0x1b7, 0x19e,
+ 0x185, 0x16c, 0x153, 0x13a, 0x121, 0x107, 0xee, 0xd5,
+ 0xbc, 0xa3, 0x8a, 0x71, 0x57, 0x3e, 0x25, 0xc,
+
+};
+
+static const q15_t ALIGN4 cos_factorsQ15_8192[8192] = {
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+ 0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,
+ 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe,
+ 0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd,
+ 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffd, 0x7ffc,
+ 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc, 0x7ffc,
+ 0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffb,
+ 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa,
+ 0x7ffa, 0x7ffa, 0x7ffa, 0x7ffa, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9,
+ 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff8,
+ 0x7ff8, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7, 0x7ff7,
+ 0x7ff7, 0x7ff7, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6, 0x7ff6,
+ 0x7ff6, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff5, 0x7ff4,
+ 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff3,
+ 0x7ff3, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2, 0x7ff2,
+ 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff1, 0x7ff0, 0x7ff0,
+ 0x7ff0, 0x7ff0, 0x7ff0, 0x7fef, 0x7fef, 0x7fef, 0x7fef, 0x7fef,
+ 0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fee, 0x7fed, 0x7fed, 0x7fed,
+ 0x7fed, 0x7fed, 0x7fec, 0x7fec, 0x7fec, 0x7fec, 0x7feb, 0x7feb,
+ 0x7feb, 0x7feb, 0x7feb, 0x7fea, 0x7fea, 0x7fea, 0x7fea, 0x7fe9,
+ 0x7fe9, 0x7fe9, 0x7fe9, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8, 0x7fe8,
+ 0x7fe7, 0x7fe7, 0x7fe7, 0x7fe7, 0x7fe6, 0x7fe6, 0x7fe6, 0x7fe6,
+ 0x7fe5, 0x7fe5, 0x7fe5, 0x7fe5, 0x7fe4, 0x7fe4, 0x7fe4, 0x7fe4,
+ 0x7fe3, 0x7fe3, 0x7fe3, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe2, 0x7fe1,
+ 0x7fe1, 0x7fe1, 0x7fe1, 0x7fe0, 0x7fe0, 0x7fe0, 0x7fdf, 0x7fdf,
+ 0x7fdf, 0x7fdf, 0x7fde, 0x7fde, 0x7fde, 0x7fde, 0x7fdd, 0x7fdd,
+ 0x7fdd, 0x7fdc, 0x7fdc, 0x7fdc, 0x7fdb, 0x7fdb, 0x7fdb, 0x7fdb,
+ 0x7fda, 0x7fda, 0x7fda, 0x7fd9, 0x7fd9, 0x7fd9, 0x7fd8, 0x7fd8,
+ 0x7fd8, 0x7fd8, 0x7fd7, 0x7fd7, 0x7fd7, 0x7fd6, 0x7fd6, 0x7fd6,
+ 0x7fd5, 0x7fd5, 0x7fd5, 0x7fd4, 0x7fd4, 0x7fd4, 0x7fd3, 0x7fd3,
+ 0x7fd3, 0x7fd2, 0x7fd2, 0x7fd2, 0x7fd1, 0x7fd1, 0x7fd1, 0x7fd0,
+ 0x7fd0, 0x7fd0, 0x7fcf, 0x7fcf, 0x7fcf, 0x7fce, 0x7fce, 0x7fce,
+ 0x7fcd, 0x7fcd, 0x7fcd, 0x7fcc, 0x7fcc, 0x7fcc, 0x7fcb, 0x7fcb,
+ 0x7fcb, 0x7fca, 0x7fca, 0x7fc9, 0x7fc9, 0x7fc9, 0x7fc8, 0x7fc8,
+ 0x7fc8, 0x7fc7, 0x7fc7, 0x7fc7, 0x7fc6, 0x7fc6, 0x7fc5, 0x7fc5,
+ 0x7fc5, 0x7fc4, 0x7fc4, 0x7fc4, 0x7fc3, 0x7fc3, 0x7fc2, 0x7fc2,
+ 0x7fc2, 0x7fc1, 0x7fc1, 0x7fc0, 0x7fc0, 0x7fc0, 0x7fbf, 0x7fbf,
+ 0x7fbf, 0x7fbe, 0x7fbe, 0x7fbd, 0x7fbd, 0x7fbd, 0x7fbc, 0x7fbc,
+ 0x7fbb, 0x7fbb, 0x7fbb, 0x7fba, 0x7fba, 0x7fb9, 0x7fb9, 0x7fb8,
+ 0x7fb8, 0x7fb8, 0x7fb7, 0x7fb7, 0x7fb6, 0x7fb6, 0x7fb6, 0x7fb5,
+ 0x7fb5, 0x7fb4, 0x7fb4, 0x7fb3, 0x7fb3, 0x7fb3, 0x7fb2, 0x7fb2,
+ 0x7fb1, 0x7fb1, 0x7fb0, 0x7fb0, 0x7faf, 0x7faf, 0x7faf, 0x7fae,
+ 0x7fae, 0x7fad, 0x7fad, 0x7fac, 0x7fac, 0x7fac, 0x7fab, 0x7fab,
+ 0x7faa, 0x7faa, 0x7fa9, 0x7fa9, 0x7fa8, 0x7fa8, 0x7fa7, 0x7fa7,
+ 0x7fa6, 0x7fa6, 0x7fa6, 0x7fa5, 0x7fa5, 0x7fa4, 0x7fa4, 0x7fa3,
+ 0x7fa3, 0x7fa2, 0x7fa2, 0x7fa1, 0x7fa1, 0x7fa0, 0x7fa0, 0x7f9f,
+ 0x7f9f, 0x7f9e, 0x7f9e, 0x7f9d, 0x7f9d, 0x7f9c, 0x7f9c, 0x7f9c,
+ 0x7f9b, 0x7f9b, 0x7f9a, 0x7f9a, 0x7f99, 0x7f99, 0x7f98, 0x7f98,
+ 0x7f97, 0x7f97, 0x7f96, 0x7f96, 0x7f95, 0x7f95, 0x7f94, 0x7f94,
+ 0x7f93, 0x7f92, 0x7f92, 0x7f91, 0x7f91, 0x7f90, 0x7f90, 0x7f8f,
+ 0x7f8f, 0x7f8e, 0x7f8e, 0x7f8d, 0x7f8d, 0x7f8c, 0x7f8c, 0x7f8b,
+ 0x7f8b, 0x7f8a, 0x7f8a, 0x7f89, 0x7f89, 0x7f88, 0x7f87, 0x7f87,
+ 0x7f86, 0x7f86, 0x7f85, 0x7f85, 0x7f84, 0x7f84, 0x7f83, 0x7f83,
+ 0x7f82, 0x7f81, 0x7f81, 0x7f80, 0x7f80, 0x7f7f, 0x7f7f, 0x7f7e,
+ 0x7f7e, 0x7f7d, 0x7f7c, 0x7f7c, 0x7f7b, 0x7f7b, 0x7f7a, 0x7f7a,
+ 0x7f79, 0x7f79, 0x7f78, 0x7f77, 0x7f77, 0x7f76, 0x7f76, 0x7f75,
+ 0x7f75, 0x7f74, 0x7f73, 0x7f73, 0x7f72, 0x7f72, 0x7f71, 0x7f70,
+ 0x7f70, 0x7f6f, 0x7f6f, 0x7f6e, 0x7f6d, 0x7f6d, 0x7f6c, 0x7f6c,
+ 0x7f6b, 0x7f6b, 0x7f6a, 0x7f69, 0x7f69, 0x7f68, 0x7f68, 0x7f67,
+ 0x7f66, 0x7f66, 0x7f65, 0x7f64, 0x7f64, 0x7f63, 0x7f63, 0x7f62,
+ 0x7f61, 0x7f61, 0x7f60, 0x7f60, 0x7f5f, 0x7f5e, 0x7f5e, 0x7f5d,
+ 0x7f5c, 0x7f5c, 0x7f5b, 0x7f5b, 0x7f5a, 0x7f59, 0x7f59, 0x7f58,
+ 0x7f57, 0x7f57, 0x7f56, 0x7f55, 0x7f55, 0x7f54, 0x7f54, 0x7f53,
+ 0x7f52, 0x7f52, 0x7f51, 0x7f50, 0x7f50, 0x7f4f, 0x7f4e, 0x7f4e,
+ 0x7f4d, 0x7f4c, 0x7f4c, 0x7f4b, 0x7f4a, 0x7f4a, 0x7f49, 0x7f48,
+ 0x7f48, 0x7f47, 0x7f46, 0x7f46, 0x7f45, 0x7f44, 0x7f44, 0x7f43,
+ 0x7f42, 0x7f42, 0x7f41, 0x7f40, 0x7f40, 0x7f3f, 0x7f3e, 0x7f3e,
+ 0x7f3d, 0x7f3c, 0x7f3c, 0x7f3b, 0x7f3a, 0x7f3a, 0x7f39, 0x7f38,
+ 0x7f37, 0x7f37, 0x7f36, 0x7f35, 0x7f35, 0x7f34, 0x7f33, 0x7f33,
+ 0x7f32, 0x7f31, 0x7f31, 0x7f30, 0x7f2f, 0x7f2e, 0x7f2e, 0x7f2d,
+ 0x7f2c, 0x7f2c, 0x7f2b, 0x7f2a, 0x7f29, 0x7f29, 0x7f28, 0x7f27,
+ 0x7f27, 0x7f26, 0x7f25, 0x7f24, 0x7f24, 0x7f23, 0x7f22, 0x7f21,
+ 0x7f21, 0x7f20, 0x7f1f, 0x7f1f, 0x7f1e, 0x7f1d, 0x7f1c, 0x7f1c,
+ 0x7f1b, 0x7f1a, 0x7f19, 0x7f19, 0x7f18, 0x7f17, 0x7f16, 0x7f16,
+ 0x7f15, 0x7f14, 0x7f13, 0x7f13, 0x7f12, 0x7f11, 0x7f10, 0x7f10,
+ 0x7f0f, 0x7f0e, 0x7f0d, 0x7f0d, 0x7f0c, 0x7f0b, 0x7f0a, 0x7f09,
+ 0x7f09, 0x7f08, 0x7f07, 0x7f06, 0x7f06, 0x7f05, 0x7f04, 0x7f03,
+ 0x7f02, 0x7f02, 0x7f01, 0x7f00, 0x7eff, 0x7eff, 0x7efe, 0x7efd,
+ 0x7efc, 0x7efb, 0x7efb, 0x7efa, 0x7ef9, 0x7ef8, 0x7ef7, 0x7ef7,
+ 0x7ef6, 0x7ef5, 0x7ef4, 0x7ef3, 0x7ef3, 0x7ef2, 0x7ef1, 0x7ef0,
+ 0x7eef, 0x7eef, 0x7eee, 0x7eed, 0x7eec, 0x7eeb, 0x7eeb, 0x7eea,
+ 0x7ee9, 0x7ee8, 0x7ee7, 0x7ee6, 0x7ee6, 0x7ee5, 0x7ee4, 0x7ee3,
+ 0x7ee2, 0x7ee2, 0x7ee1, 0x7ee0, 0x7edf, 0x7ede, 0x7edd, 0x7edd,
+ 0x7edc, 0x7edb, 0x7eda, 0x7ed9, 0x7ed8, 0x7ed8, 0x7ed7, 0x7ed6,
+ 0x7ed5, 0x7ed4, 0x7ed3, 0x7ed2, 0x7ed2, 0x7ed1, 0x7ed0, 0x7ecf,
+ 0x7ece, 0x7ecd, 0x7ecc, 0x7ecc, 0x7ecb, 0x7eca, 0x7ec9, 0x7ec8,
+ 0x7ec7, 0x7ec6, 0x7ec6, 0x7ec5, 0x7ec4, 0x7ec3, 0x7ec2, 0x7ec1,
+ 0x7ec0, 0x7ebf, 0x7ebf, 0x7ebe, 0x7ebd, 0x7ebc, 0x7ebb, 0x7eba,
+ 0x7eb9, 0x7eb8, 0x7eb8, 0x7eb7, 0x7eb6, 0x7eb5, 0x7eb4, 0x7eb3,
+ 0x7eb2, 0x7eb1, 0x7eb0, 0x7eaf, 0x7eaf, 0x7eae, 0x7ead, 0x7eac,
+ 0x7eab, 0x7eaa, 0x7ea9, 0x7ea8, 0x7ea7, 0x7ea6, 0x7ea6, 0x7ea5,
+ 0x7ea4, 0x7ea3, 0x7ea2, 0x7ea1, 0x7ea0, 0x7e9f, 0x7e9e, 0x7e9d,
+ 0x7e9c, 0x7e9b, 0x7e9b, 0x7e9a, 0x7e99, 0x7e98, 0x7e97, 0x7e96,
+ 0x7e95, 0x7e94, 0x7e93, 0x7e92, 0x7e91, 0x7e90, 0x7e8f, 0x7e8e,
+ 0x7e8d, 0x7e8d, 0x7e8c, 0x7e8b, 0x7e8a, 0x7e89, 0x7e88, 0x7e87,
+ 0x7e86, 0x7e85, 0x7e84, 0x7e83, 0x7e82, 0x7e81, 0x7e80, 0x7e7f,
+ 0x7e7e, 0x7e7d, 0x7e7c, 0x7e7b, 0x7e7a, 0x7e79, 0x7e78, 0x7e77,
+ 0x7e77, 0x7e76, 0x7e75, 0x7e74, 0x7e73, 0x7e72, 0x7e71, 0x7e70,
+ 0x7e6f, 0x7e6e, 0x7e6d, 0x7e6c, 0x7e6b, 0x7e6a, 0x7e69, 0x7e68,
+ 0x7e67, 0x7e66, 0x7e65, 0x7e64, 0x7e63, 0x7e62, 0x7e61, 0x7e60,
+ 0x7e5f, 0x7e5e, 0x7e5d, 0x7e5c, 0x7e5b, 0x7e5a, 0x7e59, 0x7e58,
+ 0x7e57, 0x7e56, 0x7e55, 0x7e54, 0x7e53, 0x7e52, 0x7e51, 0x7e50,
+ 0x7e4f, 0x7e4e, 0x7e4d, 0x7e4c, 0x7e4b, 0x7e4a, 0x7e49, 0x7e48,
+ 0x7e47, 0x7e46, 0x7e45, 0x7e43, 0x7e42, 0x7e41, 0x7e40, 0x7e3f,
+ 0x7e3e, 0x7e3d, 0x7e3c, 0x7e3b, 0x7e3a, 0x7e39, 0x7e38, 0x7e37,
+ 0x7e36, 0x7e35, 0x7e34, 0x7e33, 0x7e32, 0x7e31, 0x7e30, 0x7e2f,
+ 0x7e2e, 0x7e2d, 0x7e2b, 0x7e2a, 0x7e29, 0x7e28, 0x7e27, 0x7e26,
+ 0x7e25, 0x7e24, 0x7e23, 0x7e22, 0x7e21, 0x7e20, 0x7e1f, 0x7e1e,
+ 0x7e1d, 0x7e1b, 0x7e1a, 0x7e19, 0x7e18, 0x7e17, 0x7e16, 0x7e15,
+ 0x7e14, 0x7e13, 0x7e12, 0x7e11, 0x7e10, 0x7e0e, 0x7e0d, 0x7e0c,
+ 0x7e0b, 0x7e0a, 0x7e09, 0x7e08, 0x7e07, 0x7e06, 0x7e05, 0x7e04,
+ 0x7e02, 0x7e01, 0x7e00, 0x7dff, 0x7dfe, 0x7dfd, 0x7dfc, 0x7dfb,
+ 0x7dfa, 0x7df8, 0x7df7, 0x7df6, 0x7df5, 0x7df4, 0x7df3, 0x7df2,
+ 0x7df1, 0x7def, 0x7dee, 0x7ded, 0x7dec, 0x7deb, 0x7dea, 0x7de9,
+ 0x7de8, 0x7de6, 0x7de5, 0x7de4, 0x7de3, 0x7de2, 0x7de1, 0x7de0,
+ 0x7dde, 0x7ddd, 0x7ddc, 0x7ddb, 0x7dda, 0x7dd9, 0x7dd8, 0x7dd6,
+ 0x7dd5, 0x7dd4, 0x7dd3, 0x7dd2, 0x7dd1, 0x7dd0, 0x7dce, 0x7dcd,
+ 0x7dcc, 0x7dcb, 0x7dca, 0x7dc9, 0x7dc7, 0x7dc6, 0x7dc5, 0x7dc4,
+ 0x7dc3, 0x7dc2, 0x7dc0, 0x7dbf, 0x7dbe, 0x7dbd, 0x7dbc, 0x7dbb,
+ 0x7db9, 0x7db8, 0x7db7, 0x7db6, 0x7db5, 0x7db3, 0x7db2, 0x7db1,
+ 0x7db0, 0x7daf, 0x7dae, 0x7dac, 0x7dab, 0x7daa, 0x7da9, 0x7da8,
+ 0x7da6, 0x7da5, 0x7da4, 0x7da3, 0x7da2, 0x7da0, 0x7d9f, 0x7d9e,
+ 0x7d9d, 0x7d9c, 0x7d9a, 0x7d99, 0x7d98, 0x7d97, 0x7d95, 0x7d94,
+ 0x7d93, 0x7d92, 0x7d91, 0x7d8f, 0x7d8e, 0x7d8d, 0x7d8c, 0x7d8a,
+ 0x7d89, 0x7d88, 0x7d87, 0x7d86, 0x7d84, 0x7d83, 0x7d82, 0x7d81,
+ 0x7d7f, 0x7d7e, 0x7d7d, 0x7d7c, 0x7d7a, 0x7d79, 0x7d78, 0x7d77,
+ 0x7d75, 0x7d74, 0x7d73, 0x7d72, 0x7d70, 0x7d6f, 0x7d6e, 0x7d6d,
+ 0x7d6b, 0x7d6a, 0x7d69, 0x7d68, 0x7d66, 0x7d65, 0x7d64, 0x7d63,
+ 0x7d61, 0x7d60, 0x7d5f, 0x7d5e, 0x7d5c, 0x7d5b, 0x7d5a, 0x7d59,
+ 0x7d57, 0x7d56, 0x7d55, 0x7d53, 0x7d52, 0x7d51, 0x7d50, 0x7d4e,
+ 0x7d4d, 0x7d4c, 0x7d4a, 0x7d49, 0x7d48, 0x7d47, 0x7d45, 0x7d44,
+ 0x7d43, 0x7d41, 0x7d40, 0x7d3f, 0x7d3e, 0x7d3c, 0x7d3b, 0x7d3a,
+ 0x7d38, 0x7d37, 0x7d36, 0x7d34, 0x7d33, 0x7d32, 0x7d31, 0x7d2f,
+ 0x7d2e, 0x7d2d, 0x7d2b, 0x7d2a, 0x7d29, 0x7d27, 0x7d26, 0x7d25,
+ 0x7d23, 0x7d22, 0x7d21, 0x7d1f, 0x7d1e, 0x7d1d, 0x7d1b, 0x7d1a,
+ 0x7d19, 0x7d17, 0x7d16, 0x7d15, 0x7d13, 0x7d12, 0x7d11, 0x7d0f,
+ 0x7d0e, 0x7d0d, 0x7d0b, 0x7d0a, 0x7d09, 0x7d07, 0x7d06, 0x7d05,
+ 0x7d03, 0x7d02, 0x7d01, 0x7cff, 0x7cfe, 0x7cfd, 0x7cfb, 0x7cfa,
+ 0x7cf9, 0x7cf7, 0x7cf6, 0x7cf4, 0x7cf3, 0x7cf2, 0x7cf0, 0x7cef,
+ 0x7cee, 0x7cec, 0x7ceb, 0x7ce9, 0x7ce8, 0x7ce7, 0x7ce5, 0x7ce4,
+ 0x7ce3, 0x7ce1, 0x7ce0, 0x7cde, 0x7cdd, 0x7cdc, 0x7cda, 0x7cd9,
+ 0x7cd8, 0x7cd6, 0x7cd5, 0x7cd3, 0x7cd2, 0x7cd1, 0x7ccf, 0x7cce,
+ 0x7ccc, 0x7ccb, 0x7cca, 0x7cc8, 0x7cc7, 0x7cc5, 0x7cc4, 0x7cc3,
+ 0x7cc1, 0x7cc0, 0x7cbe, 0x7cbd, 0x7cbc, 0x7cba, 0x7cb9, 0x7cb7,
+ 0x7cb6, 0x7cb5, 0x7cb3, 0x7cb2, 0x7cb0, 0x7caf, 0x7cad, 0x7cac,
+ 0x7cab, 0x7ca9, 0x7ca8, 0x7ca6, 0x7ca5, 0x7ca3, 0x7ca2, 0x7ca1,
+ 0x7c9f, 0x7c9e, 0x7c9c, 0x7c9b, 0x7c99, 0x7c98, 0x7c97, 0x7c95,
+ 0x7c94, 0x7c92, 0x7c91, 0x7c8f, 0x7c8e, 0x7c8c, 0x7c8b, 0x7c8a,
+ 0x7c88, 0x7c87, 0x7c85, 0x7c84, 0x7c82, 0x7c81, 0x7c7f, 0x7c7e,
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+ 0x5d80, 0x5d7c, 0x5d78, 0x5d74, 0x5d6f, 0x5d6b, 0x5d67, 0x5d62,
+ 0x5d5e, 0x5d5a, 0x5d55, 0x5d51, 0x5d4d, 0x5d49, 0x5d44, 0x5d40,
+ 0x5d3c, 0x5d37, 0x5d33, 0x5d2f, 0x5d2a, 0x5d26, 0x5d22, 0x5d1e,
+ 0x5d19, 0x5d15, 0x5d11, 0x5d0c, 0x5d08, 0x5d04, 0x5cff, 0x5cfb,
+ 0x5cf7, 0x5cf2, 0x5cee, 0x5cea, 0x5ce5, 0x5ce1, 0x5cdd, 0x5cd8,
+ 0x5cd4, 0x5cd0, 0x5ccb, 0x5cc7, 0x5cc3, 0x5cbe, 0x5cba, 0x5cb6,
+ 0x5cb1, 0x5cad, 0x5ca9, 0x5ca4, 0x5ca0, 0x5c9c, 0x5c97, 0x5c93,
+ 0x5c8f, 0x5c8a, 0x5c86, 0x5c82, 0x5c7d, 0x5c79, 0x5c75, 0x5c70,
+ 0x5c6c, 0x5c68, 0x5c63, 0x5c5f, 0x5c5b, 0x5c56, 0x5c52, 0x5c4e,
+ 0x5c49, 0x5c45, 0x5c41, 0x5c3c, 0x5c38, 0x5c33, 0x5c2f, 0x5c2b,
+ 0x5c26, 0x5c22, 0x5c1e, 0x5c19, 0x5c15, 0x5c11, 0x5c0c, 0x5c08,
+ 0x5c03, 0x5bff, 0x5bfb, 0x5bf6, 0x5bf2, 0x5bee, 0x5be9, 0x5be5,
+ 0x5be0, 0x5bdc, 0x5bd8, 0x5bd3, 0x5bcf, 0x5bcb, 0x5bc6, 0x5bc2,
+ 0x5bbd, 0x5bb9, 0x5bb5, 0x5bb0, 0x5bac, 0x5ba8, 0x5ba3, 0x5b9f,
+ 0x5b9a, 0x5b96, 0x5b92, 0x5b8d, 0x5b89, 0x5b84, 0x5b80, 0x5b7c,
+ 0x5b77, 0x5b73, 0x5b6e, 0x5b6a, 0x5b66, 0x5b61, 0x5b5d, 0x5b58,
+ 0x5b54, 0x5b50, 0x5b4b, 0x5b47, 0x5b42, 0x5b3e, 0x5b3a, 0x5b35,
+ 0x5b31, 0x5b2c, 0x5b28, 0x5b24, 0x5b1f, 0x5b1b, 0x5b16, 0x5b12,
+ 0x5b0e, 0x5b09, 0x5b05, 0x5b00, 0x5afc, 0x5af7, 0x5af3, 0x5aef,
+ 0x5aea, 0x5ae6, 0x5ae1, 0x5add, 0x5ad8, 0x5ad4, 0x5ad0, 0x5acb,
+ 0x5ac7, 0x5ac2, 0x5abe, 0x5ab9, 0x5ab5, 0x5ab1, 0x5aac, 0x5aa8,
+ 0x5aa3, 0x5a9f, 0x5a9a, 0x5a96, 0x5a92, 0x5a8d, 0x5a89, 0x5a84,
+ 0x5a80, 0x5a7b, 0x5a77, 0x5a72, 0x5a6e, 0x5a6a, 0x5a65, 0x5a61,
+ 0x5a5c, 0x5a58, 0x5a53, 0x5a4f, 0x5a4a, 0x5a46, 0x5a41, 0x5a3d,
+ 0x5a39, 0x5a34, 0x5a30, 0x5a2b, 0x5a27, 0x5a22, 0x5a1e, 0x5a19,
+ 0x5a15, 0x5a10, 0x5a0c, 0x5a07, 0x5a03, 0x59ff, 0x59fa, 0x59f6,
+ 0x59f1, 0x59ed, 0x59e8, 0x59e4, 0x59df, 0x59db, 0x59d6, 0x59d2,
+ 0x59cd, 0x59c9, 0x59c4, 0x59c0, 0x59bb, 0x59b7, 0x59b2, 0x59ae,
+ 0x59a9, 0x59a5, 0x59a1, 0x599c, 0x5998, 0x5993, 0x598f, 0x598a,
+ 0x5986, 0x5981, 0x597d, 0x5978, 0x5974, 0x596f, 0x596b, 0x5966,
+ 0x5962, 0x595d, 0x5959, 0x5954, 0x5950, 0x594b, 0x5947, 0x5942,
+ 0x593e, 0x5939, 0x5935, 0x5930, 0x592c, 0x5927, 0x5923, 0x591e,
+ 0x591a, 0x5915, 0x5911, 0x590c, 0x5908, 0x5903, 0x58fe, 0x58fa,
+ 0x58f5, 0x58f1, 0x58ec, 0x58e8, 0x58e3, 0x58df, 0x58da, 0x58d6,
+ 0x58d1, 0x58cd, 0x58c8, 0x58c4, 0x58bf, 0x58bb, 0x58b6, 0x58b2,
+ 0x58ad, 0x58a9, 0x58a4, 0x589f, 0x589b, 0x5896, 0x5892, 0x588d,
+ 0x5889, 0x5884, 0x5880, 0x587b, 0x5877, 0x5872, 0x586e, 0x5869,
+ 0x5864, 0x5860, 0x585b, 0x5857, 0x5852, 0x584e, 0x5849, 0x5845,
+ 0x5840, 0x583c, 0x5837, 0x5832, 0x582e, 0x5829, 0x5825, 0x5820,
+ 0x581c, 0x5817, 0x5813, 0x580e, 0x5809, 0x5805, 0x5800, 0x57fc,
+ 0x57f7, 0x57f3, 0x57ee, 0x57e9, 0x57e5, 0x57e0, 0x57dc, 0x57d7,
+ 0x57d3, 0x57ce, 0x57c9, 0x57c5, 0x57c0, 0x57bc, 0x57b7, 0x57b3,
+ 0x57ae, 0x57a9, 0x57a5, 0x57a0, 0x579c, 0x5797, 0x5793, 0x578e,
+ 0x5789, 0x5785, 0x5780, 0x577c, 0x5777, 0x5772, 0x576e, 0x5769,
+ 0x5765, 0x5760, 0x575c, 0x5757, 0x5752, 0x574e, 0x5749, 0x5745,
+ 0x5740, 0x573b, 0x5737, 0x5732, 0x572e, 0x5729, 0x5724, 0x5720,
+ 0x571b, 0x5717, 0x5712, 0x570d, 0x5709, 0x5704, 0x56ff, 0x56fb,
+ 0x56f6, 0x56f2, 0x56ed, 0x56e8, 0x56e4, 0x56df, 0x56db, 0x56d6,
+ 0x56d1, 0x56cd, 0x56c8, 0x56c4, 0x56bf, 0x56ba, 0x56b6, 0x56b1,
+ 0x56ac, 0x56a8, 0x56a3, 0x569f, 0x569a, 0x5695, 0x5691, 0x568c,
+ 0x5687, 0x5683, 0x567e, 0x5679, 0x5675, 0x5670, 0x566c, 0x5667,
+ 0x5662, 0x565e, 0x5659, 0x5654, 0x5650, 0x564b, 0x5646, 0x5642,
+ 0x563d, 0x5639, 0x5634, 0x562f, 0x562b, 0x5626, 0x5621, 0x561d,
+ 0x5618, 0x5613, 0x560f, 0x560a, 0x5605, 0x5601, 0x55fc, 0x55f7,
+ 0x55f3, 0x55ee, 0x55ea, 0x55e5, 0x55e0, 0x55dc, 0x55d7, 0x55d2,
+ 0x55ce, 0x55c9, 0x55c4, 0x55c0, 0x55bb, 0x55b6, 0x55b2, 0x55ad,
+ 0x55a8, 0x55a4, 0x559f, 0x559a, 0x5596, 0x5591, 0x558c, 0x5588,
+ 0x5583, 0x557e, 0x5579, 0x5575, 0x5570, 0x556b, 0x5567, 0x5562,
+ 0x555d, 0x5559, 0x5554, 0x554f, 0x554b, 0x5546, 0x5541, 0x553d,
+ 0x5538, 0x5533, 0x552f, 0x552a, 0x5525, 0x5520, 0x551c, 0x5517,
+ 0x5512, 0x550e, 0x5509, 0x5504, 0x5500, 0x54fb, 0x54f6, 0x54f2,
+ 0x54ed, 0x54e8, 0x54e3, 0x54df, 0x54da, 0x54d5, 0x54d1, 0x54cc,
+ 0x54c7, 0x54c2, 0x54be, 0x54b9, 0x54b4, 0x54b0, 0x54ab, 0x54a6,
+ 0x54a2, 0x549d, 0x5498, 0x5493, 0x548f, 0x548a, 0x5485, 0x5480,
+ 0x547c, 0x5477, 0x5472, 0x546e, 0x5469, 0x5464, 0x545f, 0x545b,
+ 0x5456, 0x5451, 0x544d, 0x5448, 0x5443, 0x543e, 0x543a, 0x5435,
+ 0x5430, 0x542b, 0x5427, 0x5422, 0x541d, 0x5418, 0x5414, 0x540f,
+ 0x540a, 0x5406, 0x5401, 0x53fc, 0x53f7, 0x53f3, 0x53ee, 0x53e9,
+ 0x53e4, 0x53e0, 0x53db, 0x53d6, 0x53d1, 0x53cd, 0x53c8, 0x53c3,
+ 0x53be, 0x53ba, 0x53b5, 0x53b0, 0x53ab, 0x53a7, 0x53a2, 0x539d,
+ 0x5398, 0x5394, 0x538f, 0x538a, 0x5385, 0x5380, 0x537c, 0x5377,
+ 0x5372, 0x536d, 0x5369, 0x5364, 0x535f, 0x535a, 0x5356, 0x5351,
+ 0x534c, 0x5347, 0x5343, 0x533e, 0x5339, 0x5334, 0x532f, 0x532b,
+ 0x5326, 0x5321, 0x531c, 0x5318, 0x5313, 0x530e, 0x5309, 0x5304,
+ 0x5300, 0x52fb, 0x52f6, 0x52f1, 0x52ec, 0x52e8, 0x52e3, 0x52de,
+ 0x52d9, 0x52d5, 0x52d0, 0x52cb, 0x52c6, 0x52c1, 0x52bd, 0x52b8,
+ 0x52b3, 0x52ae, 0x52a9, 0x52a5, 0x52a0, 0x529b, 0x5296, 0x5291,
+ 0x528d, 0x5288, 0x5283, 0x527e, 0x5279, 0x5275, 0x5270, 0x526b,
+ 0x5266, 0x5261, 0x525d, 0x5258, 0x5253, 0x524e, 0x5249, 0x5244,
+ 0x5240, 0x523b, 0x5236, 0x5231, 0x522c, 0x5228, 0x5223, 0x521e,
+ 0x5219, 0x5214, 0x520f, 0x520b, 0x5206, 0x5201, 0x51fc, 0x51f7,
+ 0x51f3, 0x51ee, 0x51e9, 0x51e4, 0x51df, 0x51da, 0x51d6, 0x51d1,
+ 0x51cc, 0x51c7, 0x51c2, 0x51bd, 0x51b9, 0x51b4, 0x51af, 0x51aa,
+ 0x51a5, 0x51a0, 0x519c, 0x5197, 0x5192, 0x518d, 0x5188, 0x5183,
+ 0x517e, 0x517a, 0x5175, 0x5170, 0x516b, 0x5166, 0x5161, 0x515d,
+ 0x5158, 0x5153, 0x514e, 0x5149, 0x5144, 0x513f, 0x513b, 0x5136,
+ 0x5131, 0x512c, 0x5127, 0x5122, 0x511d, 0x5119, 0x5114, 0x510f,
+ 0x510a, 0x5105, 0x5100, 0x50fb, 0x50f7, 0x50f2, 0x50ed, 0x50e8,
+ 0x50e3, 0x50de, 0x50d9, 0x50d4, 0x50d0, 0x50cb, 0x50c6, 0x50c1,
+ 0x50bc, 0x50b7, 0x50b2, 0x50ad, 0x50a9, 0x50a4, 0x509f, 0x509a,
+ 0x5095, 0x5090, 0x508b, 0x5086, 0x5082, 0x507d, 0x5078, 0x5073,
+ 0x506e, 0x5069, 0x5064, 0x505f, 0x505a, 0x5056, 0x5051, 0x504c,
+ 0x5047, 0x5042, 0x503d, 0x5038, 0x5033, 0x502e, 0x5029, 0x5025,
+ 0x5020, 0x501b, 0x5016, 0x5011, 0x500c, 0x5007, 0x5002, 0x4ffd,
+ 0x4ff8, 0x4ff4, 0x4fef, 0x4fea, 0x4fe5, 0x4fe0, 0x4fdb, 0x4fd6,
+ 0x4fd1, 0x4fcc, 0x4fc7, 0x4fc2, 0x4fbe, 0x4fb9, 0x4fb4, 0x4faf,
+ 0x4faa, 0x4fa5, 0x4fa0, 0x4f9b, 0x4f96, 0x4f91, 0x4f8c, 0x4f87,
+ 0x4f82, 0x4f7e, 0x4f79, 0x4f74, 0x4f6f, 0x4f6a, 0x4f65, 0x4f60,
+ 0x4f5b, 0x4f56, 0x4f51, 0x4f4c, 0x4f47, 0x4f42, 0x4f3d, 0x4f39,
+ 0x4f34, 0x4f2f, 0x4f2a, 0x4f25, 0x4f20, 0x4f1b, 0x4f16, 0x4f11,
+ 0x4f0c, 0x4f07, 0x4f02, 0x4efd, 0x4ef8, 0x4ef3, 0x4eee, 0x4ee9,
+ 0x4ee5, 0x4ee0, 0x4edb, 0x4ed6, 0x4ed1, 0x4ecc, 0x4ec7, 0x4ec2,
+ 0x4ebd, 0x4eb8, 0x4eb3, 0x4eae, 0x4ea9, 0x4ea4, 0x4e9f, 0x4e9a,
+ 0x4e95, 0x4e90, 0x4e8b, 0x4e86, 0x4e81, 0x4e7c, 0x4e78, 0x4e73,
+ 0x4e6e, 0x4e69, 0x4e64, 0x4e5f, 0x4e5a, 0x4e55, 0x4e50, 0x4e4b,
+ 0x4e46, 0x4e41, 0x4e3c, 0x4e37, 0x4e32, 0x4e2d, 0x4e28, 0x4e23,
+ 0x4e1e, 0x4e19, 0x4e14, 0x4e0f, 0x4e0a, 0x4e05, 0x4e00, 0x4dfb,
+ 0x4df6, 0x4df1, 0x4dec, 0x4de7, 0x4de2, 0x4ddd, 0x4dd8, 0x4dd3,
+ 0x4dce, 0x4dc9, 0x4dc4, 0x4dbf, 0x4dba, 0x4db5, 0x4db0, 0x4dab,
+ 0x4da6, 0x4da1, 0x4d9c, 0x4d97, 0x4d92, 0x4d8d, 0x4d88, 0x4d83,
+ 0x4d7e, 0x4d79, 0x4d74, 0x4d6f, 0x4d6a, 0x4d65, 0x4d60, 0x4d5b,
+ 0x4d56, 0x4d51, 0x4d4c, 0x4d47, 0x4d42, 0x4d3d, 0x4d38, 0x4d33,
+ 0x4d2e, 0x4d29, 0x4d24, 0x4d1f, 0x4d1a, 0x4d15, 0x4d10, 0x4d0b,
+ 0x4d06, 0x4d01, 0x4cfc, 0x4cf7, 0x4cf2, 0x4ced, 0x4ce8, 0x4ce3,
+ 0x4cde, 0x4cd9, 0x4cd4, 0x4ccf, 0x4cca, 0x4cc5, 0x4cc0, 0x4cbb,
+ 0x4cb6, 0x4cb1, 0x4cac, 0x4ca7, 0x4ca2, 0x4c9d, 0x4c98, 0x4c93,
+ 0x4c8e, 0x4c88, 0x4c83, 0x4c7e, 0x4c79, 0x4c74, 0x4c6f, 0x4c6a,
+ 0x4c65, 0x4c60, 0x4c5b, 0x4c56, 0x4c51, 0x4c4c, 0x4c47, 0x4c42,
+ 0x4c3d, 0x4c38, 0x4c33, 0x4c2e, 0x4c29, 0x4c24, 0x4c1f, 0x4c1a,
+ 0x4c14, 0x4c0f, 0x4c0a, 0x4c05, 0x4c00, 0x4bfb, 0x4bf6, 0x4bf1,
+ 0x4bec, 0x4be7, 0x4be2, 0x4bdd, 0x4bd8, 0x4bd3, 0x4bce, 0x4bc9,
+ 0x4bc4, 0x4bbe, 0x4bb9, 0x4bb4, 0x4baf, 0x4baa, 0x4ba5, 0x4ba0,
+ 0x4b9b, 0x4b96, 0x4b91, 0x4b8c, 0x4b87, 0x4b82, 0x4b7d, 0x4b77,
+ 0x4b72, 0x4b6d, 0x4b68, 0x4b63, 0x4b5e, 0x4b59, 0x4b54, 0x4b4f,
+ 0x4b4a, 0x4b45, 0x4b40, 0x4b3b, 0x4b35, 0x4b30, 0x4b2b, 0x4b26,
+ 0x4b21, 0x4b1c, 0x4b17, 0x4b12, 0x4b0d, 0x4b08, 0x4b03, 0x4afd,
+ 0x4af8, 0x4af3, 0x4aee, 0x4ae9, 0x4ae4, 0x4adf, 0x4ada, 0x4ad5,
+ 0x4ad0, 0x4acb, 0x4ac5, 0x4ac0, 0x4abb, 0x4ab6, 0x4ab1, 0x4aac,
+ 0x4aa7, 0x4aa2, 0x4a9d, 0x4a97, 0x4a92, 0x4a8d, 0x4a88, 0x4a83,
+ 0x4a7e, 0x4a79, 0x4a74, 0x4a6f, 0x4a6a, 0x4a64, 0x4a5f, 0x4a5a,
+ 0x4a55, 0x4a50, 0x4a4b, 0x4a46, 0x4a41, 0x4a3b, 0x4a36, 0x4a31,
+ 0x4a2c, 0x4a27, 0x4a22, 0x4a1d, 0x4a18, 0x4a12, 0x4a0d, 0x4a08,
+ 0x4a03, 0x49fe, 0x49f9, 0x49f4, 0x49ef, 0x49e9, 0x49e4, 0x49df,
+ 0x49da, 0x49d5, 0x49d0, 0x49cb, 0x49c6, 0x49c0, 0x49bb, 0x49b6,
+ 0x49b1, 0x49ac, 0x49a7, 0x49a2, 0x499c, 0x4997, 0x4992, 0x498d,
+ 0x4988, 0x4983, 0x497e, 0x4978, 0x4973, 0x496e, 0x4969, 0x4964,
+ 0x495f, 0x495a, 0x4954, 0x494f, 0x494a, 0x4945, 0x4940, 0x493b,
+ 0x4936, 0x4930, 0x492b, 0x4926, 0x4921, 0x491c, 0x4917, 0x4911,
+ 0x490c, 0x4907, 0x4902, 0x48fd, 0x48f8, 0x48f2, 0x48ed, 0x48e8,
+ 0x48e3, 0x48de, 0x48d9, 0x48d3, 0x48ce, 0x48c9, 0x48c4, 0x48bf,
+ 0x48ba, 0x48b4, 0x48af, 0x48aa, 0x48a5, 0x48a0, 0x489b, 0x4895,
+ 0x4890, 0x488b, 0x4886, 0x4881, 0x487c, 0x4876, 0x4871, 0x486c,
+ 0x4867, 0x4862, 0x485c, 0x4857, 0x4852, 0x484d, 0x4848, 0x4843,
+ 0x483d, 0x4838, 0x4833, 0x482e, 0x4829, 0x4823, 0x481e, 0x4819,
+ 0x4814, 0x480f, 0x4809, 0x4804, 0x47ff, 0x47fa, 0x47f5, 0x47ef,
+ 0x47ea, 0x47e5, 0x47e0, 0x47db, 0x47d5, 0x47d0, 0x47cb, 0x47c6,
+ 0x47c1, 0x47bb, 0x47b6, 0x47b1, 0x47ac, 0x47a7, 0x47a1, 0x479c,
+ 0x4797, 0x4792, 0x478d, 0x4787, 0x4782, 0x477d, 0x4778, 0x4773,
+ 0x476d, 0x4768, 0x4763, 0x475e, 0x4758, 0x4753, 0x474e, 0x4749,
+ 0x4744, 0x473e, 0x4739, 0x4734, 0x472f, 0x4729, 0x4724, 0x471f,
+ 0x471a, 0x4715, 0x470f, 0x470a, 0x4705, 0x4700, 0x46fa, 0x46f5,
+ 0x46f0, 0x46eb, 0x46e6, 0x46e0, 0x46db, 0x46d6, 0x46d1, 0x46cb,
+ 0x46c6, 0x46c1, 0x46bc, 0x46b6, 0x46b1, 0x46ac, 0x46a7, 0x46a1,
+ 0x469c, 0x4697, 0x4692, 0x468d, 0x4687, 0x4682, 0x467d, 0x4678,
+ 0x4672, 0x466d, 0x4668, 0x4663, 0x465d, 0x4658, 0x4653, 0x464e,
+ 0x4648, 0x4643, 0x463e, 0x4639, 0x4633, 0x462e, 0x4629, 0x4624,
+ 0x461e, 0x4619, 0x4614, 0x460e, 0x4609, 0x4604, 0x45ff, 0x45f9,
+ 0x45f4, 0x45ef, 0x45ea, 0x45e4, 0x45df, 0x45da, 0x45d5, 0x45cf,
+ 0x45ca, 0x45c5, 0x45c0, 0x45ba, 0x45b5, 0x45b0, 0x45aa, 0x45a5,
+ 0x45a0, 0x459b, 0x4595, 0x4590, 0x458b, 0x4586, 0x4580, 0x457b,
+ 0x4576, 0x4570, 0x456b, 0x4566, 0x4561, 0x455b, 0x4556, 0x4551,
+ 0x454b, 0x4546, 0x4541, 0x453c, 0x4536, 0x4531, 0x452c, 0x4526,
+ 0x4521, 0x451c, 0x4517, 0x4511, 0x450c, 0x4507, 0x4501, 0x44fc,
+ 0x44f7, 0x44f2, 0x44ec, 0x44e7, 0x44e2, 0x44dc, 0x44d7, 0x44d2,
+ 0x44cd, 0x44c7, 0x44c2, 0x44bd, 0x44b7, 0x44b2, 0x44ad, 0x44a7,
+ 0x44a2, 0x449d, 0x4497, 0x4492, 0x448d, 0x4488, 0x4482, 0x447d,
+ 0x4478, 0x4472, 0x446d, 0x4468, 0x4462, 0x445d, 0x4458, 0x4452,
+ 0x444d, 0x4448, 0x4443, 0x443d, 0x4438, 0x4433, 0x442d, 0x4428,
+ 0x4423, 0x441d, 0x4418, 0x4413, 0x440d, 0x4408, 0x4403, 0x43fd,
+ 0x43f8, 0x43f3, 0x43ed, 0x43e8, 0x43e3, 0x43dd, 0x43d8, 0x43d3,
+ 0x43cd, 0x43c8, 0x43c3, 0x43bd, 0x43b8, 0x43b3, 0x43ad, 0x43a8,
+ 0x43a3, 0x439d, 0x4398, 0x4393, 0x438d, 0x4388, 0x4383, 0x437d,
+ 0x4378, 0x4373, 0x436d, 0x4368, 0x4363, 0x435d, 0x4358, 0x4353,
+ 0x434d, 0x4348, 0x4343, 0x433d, 0x4338, 0x4333, 0x432d, 0x4328,
+ 0x4323, 0x431d, 0x4318, 0x4313, 0x430d, 0x4308, 0x4302, 0x42fd,
+ 0x42f8, 0x42f2, 0x42ed, 0x42e8, 0x42e2, 0x42dd, 0x42d8, 0x42d2,
+ 0x42cd, 0x42c8, 0x42c2, 0x42bd, 0x42b7, 0x42b2, 0x42ad, 0x42a7,
+ 0x42a2, 0x429d, 0x4297, 0x4292, 0x428d, 0x4287, 0x4282, 0x427c,
+ 0x4277, 0x4272, 0x426c, 0x4267, 0x4262, 0x425c, 0x4257, 0x4251,
+ 0x424c, 0x4247, 0x4241, 0x423c, 0x4237, 0x4231, 0x422c, 0x4226,
+ 0x4221, 0x421c, 0x4216, 0x4211, 0x420c, 0x4206, 0x4201, 0x41fb,
+ 0x41f6, 0x41f1, 0x41eb, 0x41e6, 0x41e0, 0x41db, 0x41d6, 0x41d0,
+ 0x41cb, 0x41c6, 0x41c0, 0x41bb, 0x41b5, 0x41b0, 0x41ab, 0x41a5,
+ 0x41a0, 0x419a, 0x4195, 0x4190, 0x418a, 0x4185, 0x417f, 0x417a,
+ 0x4175, 0x416f, 0x416a, 0x4164, 0x415f, 0x415a, 0x4154, 0x414f,
+ 0x4149, 0x4144, 0x413f, 0x4139, 0x4134, 0x412e, 0x4129, 0x4124,
+ 0x411e, 0x4119, 0x4113, 0x410e, 0x4108, 0x4103, 0x40fe, 0x40f8,
+ 0x40f3, 0x40ed, 0x40e8, 0x40e3, 0x40dd, 0x40d8, 0x40d2, 0x40cd,
+ 0x40c8, 0x40c2, 0x40bd, 0x40b7, 0x40b2, 0x40ac, 0x40a7, 0x40a2,
+ 0x409c, 0x4097, 0x4091, 0x408c, 0x4086, 0x4081, 0x407c, 0x4076,
+ 0x4071, 0x406b, 0x4066, 0x4060, 0x405b, 0x4056, 0x4050, 0x404b,
+ 0x4045, 0x4040, 0x403a, 0x4035, 0x4030, 0x402a, 0x4025, 0x401f,
+ 0x401a, 0x4014, 0x400f, 0x4009, 0x4004, 0x3fff, 0x3ff9, 0x3ff4,
+ 0x3fee, 0x3fe9, 0x3fe3, 0x3fde, 0x3fd8, 0x3fd3, 0x3fce, 0x3fc8,
+ 0x3fc3, 0x3fbd, 0x3fb8, 0x3fb2, 0x3fad, 0x3fa7, 0x3fa2, 0x3f9d,
+ 0x3f97, 0x3f92, 0x3f8c, 0x3f87, 0x3f81, 0x3f7c, 0x3f76, 0x3f71,
+ 0x3f6b, 0x3f66, 0x3f61, 0x3f5b, 0x3f56, 0x3f50, 0x3f4b, 0x3f45,
+ 0x3f40, 0x3f3a, 0x3f35, 0x3f2f, 0x3f2a, 0x3f24, 0x3f1f, 0x3f1a,
+ 0x3f14, 0x3f0f, 0x3f09, 0x3f04, 0x3efe, 0x3ef9, 0x3ef3, 0x3eee,
+ 0x3ee8, 0x3ee3, 0x3edd, 0x3ed8, 0x3ed2, 0x3ecd, 0x3ec7, 0x3ec2,
+ 0x3ebd, 0x3eb7, 0x3eb2, 0x3eac, 0x3ea7, 0x3ea1, 0x3e9c, 0x3e96,
+ 0x3e91, 0x3e8b, 0x3e86, 0x3e80, 0x3e7b, 0x3e75, 0x3e70, 0x3e6a,
+ 0x3e65, 0x3e5f, 0x3e5a, 0x3e54, 0x3e4f, 0x3e49, 0x3e44, 0x3e3e,
+ 0x3e39, 0x3e33, 0x3e2e, 0x3e28, 0x3e23, 0x3e1d, 0x3e18, 0x3e12,
+ 0x3e0d, 0x3e07, 0x3e02, 0x3dfc, 0x3df7, 0x3df1, 0x3dec, 0x3de6,
+ 0x3de1, 0x3ddb, 0x3dd6, 0x3dd0, 0x3dcb, 0x3dc5, 0x3dc0, 0x3dba,
+ 0x3db5, 0x3daf, 0x3daa, 0x3da4, 0x3d9f, 0x3d99, 0x3d94, 0x3d8e,
+ 0x3d89, 0x3d83, 0x3d7e, 0x3d78, 0x3d73, 0x3d6d, 0x3d68, 0x3d62,
+ 0x3d5d, 0x3d57, 0x3d52, 0x3d4c, 0x3d47, 0x3d41, 0x3d3c, 0x3d36,
+ 0x3d31, 0x3d2b, 0x3d26, 0x3d20, 0x3d1b, 0x3d15, 0x3d10, 0x3d0a,
+ 0x3d04, 0x3cff, 0x3cf9, 0x3cf4, 0x3cee, 0x3ce9, 0x3ce3, 0x3cde,
+ 0x3cd8, 0x3cd3, 0x3ccd, 0x3cc8, 0x3cc2, 0x3cbd, 0x3cb7, 0x3cb2,
+ 0x3cac, 0x3ca7, 0x3ca1, 0x3c9b, 0x3c96, 0x3c90, 0x3c8b, 0x3c85,
+ 0x3c80, 0x3c7a, 0x3c75, 0x3c6f, 0x3c6a, 0x3c64, 0x3c5f, 0x3c59,
+ 0x3c53, 0x3c4e, 0x3c48, 0x3c43, 0x3c3d, 0x3c38, 0x3c32, 0x3c2d,
+ 0x3c27, 0x3c22, 0x3c1c, 0x3c16, 0x3c11, 0x3c0b, 0x3c06, 0x3c00,
+ 0x3bfb, 0x3bf5, 0x3bf0, 0x3bea, 0x3be5, 0x3bdf, 0x3bd9, 0x3bd4,
+ 0x3bce, 0x3bc9, 0x3bc3, 0x3bbe, 0x3bb8, 0x3bb3, 0x3bad, 0x3ba7,
+ 0x3ba2, 0x3b9c, 0x3b97, 0x3b91, 0x3b8c, 0x3b86, 0x3b80, 0x3b7b,
+ 0x3b75, 0x3b70, 0x3b6a, 0x3b65, 0x3b5f, 0x3b5a, 0x3b54, 0x3b4e,
+ 0x3b49, 0x3b43, 0x3b3e, 0x3b38, 0x3b33, 0x3b2d, 0x3b27, 0x3b22,
+ 0x3b1c, 0x3b17, 0x3b11, 0x3b0c, 0x3b06, 0x3b00, 0x3afb, 0x3af5,
+ 0x3af0, 0x3aea, 0x3ae4, 0x3adf, 0x3ad9, 0x3ad4, 0x3ace, 0x3ac9,
+ 0x3ac3, 0x3abd, 0x3ab8, 0x3ab2, 0x3aad, 0x3aa7, 0x3aa2, 0x3a9c,
+ 0x3a96, 0x3a91, 0x3a8b, 0x3a86, 0x3a80, 0x3a7a, 0x3a75, 0x3a6f,
+ 0x3a6a, 0x3a64, 0x3a5e, 0x3a59, 0x3a53, 0x3a4e, 0x3a48, 0x3a42,
+ 0x3a3d, 0x3a37, 0x3a32, 0x3a2c, 0x3a26, 0x3a21, 0x3a1b, 0x3a16,
+ 0x3a10, 0x3a0b, 0x3a05, 0x39ff, 0x39fa, 0x39f4, 0x39ee, 0x39e9,
+ 0x39e3, 0x39de, 0x39d8, 0x39d2, 0x39cd, 0x39c7, 0x39c2, 0x39bc,
+ 0x39b6, 0x39b1, 0x39ab, 0x39a6, 0x39a0, 0x399a, 0x3995, 0x398f,
+ 0x398a, 0x3984, 0x397e, 0x3979, 0x3973, 0x396d, 0x3968, 0x3962,
+ 0x395d, 0x3957, 0x3951, 0x394c, 0x3946, 0x3941, 0x393b, 0x3935,
+ 0x3930, 0x392a, 0x3924, 0x391f, 0x3919, 0x3914, 0x390e, 0x3908,
+ 0x3903, 0x38fd, 0x38f7, 0x38f2, 0x38ec, 0x38e7, 0x38e1, 0x38db,
+ 0x38d6, 0x38d0, 0x38ca, 0x38c5, 0x38bf, 0x38ba, 0x38b4, 0x38ae,
+ 0x38a9, 0x38a3, 0x389d, 0x3898, 0x3892, 0x388c, 0x3887, 0x3881,
+ 0x387c, 0x3876, 0x3870, 0x386b, 0x3865, 0x385f, 0x385a, 0x3854,
+ 0x384e, 0x3849, 0x3843, 0x383d, 0x3838, 0x3832, 0x382d, 0x3827,
+ 0x3821, 0x381c, 0x3816, 0x3810, 0x380b, 0x3805, 0x37ff, 0x37fa,
+ 0x37f4, 0x37ee, 0x37e9, 0x37e3, 0x37dd, 0x37d8, 0x37d2, 0x37cc,
+ 0x37c7, 0x37c1, 0x37bc, 0x37b6, 0x37b0, 0x37ab, 0x37a5, 0x379f,
+ 0x379a, 0x3794, 0x378e, 0x3789, 0x3783, 0x377d, 0x3778, 0x3772,
+ 0x376c, 0x3767, 0x3761, 0x375b, 0x3756, 0x3750, 0x374a, 0x3745,
+ 0x373f, 0x3739, 0x3734, 0x372e, 0x3728, 0x3723, 0x371d, 0x3717,
+ 0x3712, 0x370c, 0x3706, 0x3701, 0x36fb, 0x36f5, 0x36f0, 0x36ea,
+ 0x36e4, 0x36df, 0x36d9, 0x36d3, 0x36ce, 0x36c8, 0x36c2, 0x36bc,
+ 0x36b7, 0x36b1, 0x36ab, 0x36a6, 0x36a0, 0x369a, 0x3695, 0x368f,
+ 0x3689, 0x3684, 0x367e, 0x3678, 0x3673, 0x366d, 0x3667, 0x3662,
+ 0x365c, 0x3656, 0x3650, 0x364b, 0x3645, 0x363f, 0x363a, 0x3634,
+ 0x362e, 0x3629, 0x3623, 0x361d, 0x3618, 0x3612, 0x360c, 0x3606,
+ 0x3601, 0x35fb, 0x35f5, 0x35f0, 0x35ea, 0x35e4, 0x35df, 0x35d9,
+ 0x35d3, 0x35cd, 0x35c8, 0x35c2, 0x35bc, 0x35b7, 0x35b1, 0x35ab,
+ 0x35a6, 0x35a0, 0x359a, 0x3594, 0x358f, 0x3589, 0x3583, 0x357e,
+ 0x3578, 0x3572, 0x356c, 0x3567, 0x3561, 0x355b, 0x3556, 0x3550,
+ 0x354a, 0x3544, 0x353f, 0x3539, 0x3533, 0x352e, 0x3528, 0x3522,
+ 0x351c, 0x3517, 0x3511, 0x350b, 0x3506, 0x3500, 0x34fa, 0x34f4,
+ 0x34ef, 0x34e9, 0x34e3, 0x34de, 0x34d8, 0x34d2, 0x34cc, 0x34c7,
+ 0x34c1, 0x34bb, 0x34b6, 0x34b0, 0x34aa, 0x34a4, 0x349f, 0x3499,
+ 0x3493, 0x348d, 0x3488, 0x3482, 0x347c, 0x3476, 0x3471, 0x346b,
+ 0x3465, 0x3460, 0x345a, 0x3454, 0x344e, 0x3449, 0x3443, 0x343d,
+ 0x3437, 0x3432, 0x342c, 0x3426, 0x3420, 0x341b, 0x3415, 0x340f,
+ 0x340a, 0x3404, 0x33fe, 0x33f8, 0x33f3, 0x33ed, 0x33e7, 0x33e1,
+ 0x33dc, 0x33d6, 0x33d0, 0x33ca, 0x33c5, 0x33bf, 0x33b9, 0x33b3,
+ 0x33ae, 0x33a8, 0x33a2, 0x339c, 0x3397, 0x3391, 0x338b, 0x3385,
+ 0x3380, 0x337a, 0x3374, 0x336e, 0x3369, 0x3363, 0x335d, 0x3357,
+ 0x3352, 0x334c, 0x3346, 0x3340, 0x333b, 0x3335, 0x332f, 0x3329,
+ 0x3324, 0x331e, 0x3318, 0x3312, 0x330c, 0x3307, 0x3301, 0x32fb,
+ 0x32f5, 0x32f0, 0x32ea, 0x32e4, 0x32de, 0x32d9, 0x32d3, 0x32cd,
+ 0x32c7, 0x32c2, 0x32bc, 0x32b6, 0x32b0, 0x32aa, 0x32a5, 0x329f,
+ 0x3299, 0x3293, 0x328e, 0x3288, 0x3282, 0x327c, 0x3276, 0x3271,
+ 0x326b, 0x3265, 0x325f, 0x325a, 0x3254, 0x324e, 0x3248, 0x3243,
+ 0x323d, 0x3237, 0x3231, 0x322b, 0x3226, 0x3220, 0x321a, 0x3214,
+ 0x320e, 0x3209, 0x3203, 0x31fd, 0x31f7, 0x31f2, 0x31ec, 0x31e6,
+ 0x31e0, 0x31da, 0x31d5, 0x31cf, 0x31c9, 0x31c3, 0x31bd, 0x31b8,
+ 0x31b2, 0x31ac, 0x31a6, 0x31a1, 0x319b, 0x3195, 0x318f, 0x3189,
+ 0x3184, 0x317e, 0x3178, 0x3172, 0x316c, 0x3167, 0x3161, 0x315b,
+ 0x3155, 0x314f, 0x314a, 0x3144, 0x313e, 0x3138, 0x3132, 0x312d,
+ 0x3127, 0x3121, 0x311b, 0x3115, 0x3110, 0x310a, 0x3104, 0x30fe,
+ 0x30f8, 0x30f3, 0x30ed, 0x30e7, 0x30e1, 0x30db, 0x30d6, 0x30d0,
+ 0x30ca, 0x30c4, 0x30be, 0x30b8, 0x30b3, 0x30ad, 0x30a7, 0x30a1,
+ 0x309b, 0x3096, 0x3090, 0x308a, 0x3084, 0x307e, 0x3079, 0x3073,
+ 0x306d, 0x3067, 0x3061, 0x305b, 0x3056, 0x3050, 0x304a, 0x3044,
+ 0x303e, 0x3039, 0x3033, 0x302d, 0x3027, 0x3021, 0x301b, 0x3016,
+ 0x3010, 0x300a, 0x3004, 0x2ffe, 0x2ff8, 0x2ff3, 0x2fed, 0x2fe7,
+ 0x2fe1, 0x2fdb, 0x2fd6, 0x2fd0, 0x2fca, 0x2fc4, 0x2fbe, 0x2fb8,
+ 0x2fb3, 0x2fad, 0x2fa7, 0x2fa1, 0x2f9b, 0x2f95, 0x2f90, 0x2f8a,
+ 0x2f84, 0x2f7e, 0x2f78, 0x2f72, 0x2f6d, 0x2f67, 0x2f61, 0x2f5b,
+ 0x2f55, 0x2f4f, 0x2f4a, 0x2f44, 0x2f3e, 0x2f38, 0x2f32, 0x2f2c,
+ 0x2f27, 0x2f21, 0x2f1b, 0x2f15, 0x2f0f, 0x2f09, 0x2f03, 0x2efe,
+ 0x2ef8, 0x2ef2, 0x2eec, 0x2ee6, 0x2ee0, 0x2edb, 0x2ed5, 0x2ecf,
+ 0x2ec9, 0x2ec3, 0x2ebd, 0x2eb7, 0x2eb2, 0x2eac, 0x2ea6, 0x2ea0,
+ 0x2e9a, 0x2e94, 0x2e8e, 0x2e89, 0x2e83, 0x2e7d, 0x2e77, 0x2e71,
+ 0x2e6b, 0x2e65, 0x2e60, 0x2e5a, 0x2e54, 0x2e4e, 0x2e48, 0x2e42,
+ 0x2e3c, 0x2e37, 0x2e31, 0x2e2b, 0x2e25, 0x2e1f, 0x2e19, 0x2e13,
+ 0x2e0e, 0x2e08, 0x2e02, 0x2dfc, 0x2df6, 0x2df0, 0x2dea, 0x2de5,
+ 0x2ddf, 0x2dd9, 0x2dd3, 0x2dcd, 0x2dc7, 0x2dc1, 0x2dbb, 0x2db6,
+ 0x2db0, 0x2daa, 0x2da4, 0x2d9e, 0x2d98, 0x2d92, 0x2d8d, 0x2d87,
+ 0x2d81, 0x2d7b, 0x2d75, 0x2d6f, 0x2d69, 0x2d63, 0x2d5e, 0x2d58,
+ 0x2d52, 0x2d4c, 0x2d46, 0x2d40, 0x2d3a, 0x2d34, 0x2d2f, 0x2d29,
+ 0x2d23, 0x2d1d, 0x2d17, 0x2d11, 0x2d0b, 0x2d05, 0x2cff, 0x2cfa,
+ 0x2cf4, 0x2cee, 0x2ce8, 0x2ce2, 0x2cdc, 0x2cd6, 0x2cd0, 0x2ccb,
+ 0x2cc5, 0x2cbf, 0x2cb9, 0x2cb3, 0x2cad, 0x2ca7, 0x2ca1, 0x2c9b,
+ 0x2c96, 0x2c90, 0x2c8a, 0x2c84, 0x2c7e, 0x2c78, 0x2c72, 0x2c6c,
+ 0x2c66, 0x2c61, 0x2c5b, 0x2c55, 0x2c4f, 0x2c49, 0x2c43, 0x2c3d,
+ 0x2c37, 0x2c31, 0x2c2b, 0x2c26, 0x2c20, 0x2c1a, 0x2c14, 0x2c0e,
+ 0x2c08, 0x2c02, 0x2bfc, 0x2bf6, 0x2bf0, 0x2beb, 0x2be5, 0x2bdf,
+ 0x2bd9, 0x2bd3, 0x2bcd, 0x2bc7, 0x2bc1, 0x2bbb, 0x2bb5, 0x2bb0,
+ 0x2baa, 0x2ba4, 0x2b9e, 0x2b98, 0x2b92, 0x2b8c, 0x2b86, 0x2b80,
+ 0x2b7a, 0x2b74, 0x2b6f, 0x2b69, 0x2b63, 0x2b5d, 0x2b57, 0x2b51,
+ 0x2b4b, 0x2b45, 0x2b3f, 0x2b39, 0x2b33, 0x2b2d, 0x2b28, 0x2b22,
+ 0x2b1c, 0x2b16, 0x2b10, 0x2b0a, 0x2b04, 0x2afe, 0x2af8, 0x2af2,
+ 0x2aec, 0x2ae6, 0x2ae1, 0x2adb, 0x2ad5, 0x2acf, 0x2ac9, 0x2ac3,
+ 0x2abd, 0x2ab7, 0x2ab1, 0x2aab, 0x2aa5, 0x2a9f, 0x2a99, 0x2a94,
+ 0x2a8e, 0x2a88, 0x2a82, 0x2a7c, 0x2a76, 0x2a70, 0x2a6a, 0x2a64,
+ 0x2a5e, 0x2a58, 0x2a52, 0x2a4c, 0x2a47, 0x2a41, 0x2a3b, 0x2a35,
+ 0x2a2f, 0x2a29, 0x2a23, 0x2a1d, 0x2a17, 0x2a11, 0x2a0b, 0x2a05,
+ 0x29ff, 0x29f9, 0x29f3, 0x29ee, 0x29e8, 0x29e2, 0x29dc, 0x29d6,
+ 0x29d0, 0x29ca, 0x29c4, 0x29be, 0x29b8, 0x29b2, 0x29ac, 0x29a6,
+ 0x29a0, 0x299a, 0x2994, 0x298e, 0x2989, 0x2983, 0x297d, 0x2977,
+ 0x2971, 0x296b, 0x2965, 0x295f, 0x2959, 0x2953, 0x294d, 0x2947,
+ 0x2941, 0x293b, 0x2935, 0x292f, 0x2929, 0x2923, 0x291d, 0x2918,
+ 0x2912, 0x290c, 0x2906, 0x2900, 0x28fa, 0x28f4, 0x28ee, 0x28e8,
+ 0x28e2, 0x28dc, 0x28d6, 0x28d0, 0x28ca, 0x28c4, 0x28be, 0x28b8,
+ 0x28b2, 0x28ac, 0x28a6, 0x28a0, 0x289a, 0x2895, 0x288f, 0x2889,
+ 0x2883, 0x287d, 0x2877, 0x2871, 0x286b, 0x2865, 0x285f, 0x2859,
+ 0x2853, 0x284d, 0x2847, 0x2841, 0x283b, 0x2835, 0x282f, 0x2829,
+ 0x2823, 0x281d, 0x2817, 0x2811, 0x280b, 0x2805, 0x27ff, 0x27f9,
+ 0x27f3, 0x27ee, 0x27e8, 0x27e2, 0x27dc, 0x27d6, 0x27d0, 0x27ca,
+ 0x27c4, 0x27be, 0x27b8, 0x27b2, 0x27ac, 0x27a6, 0x27a0, 0x279a,
+ 0x2794, 0x278e, 0x2788, 0x2782, 0x277c, 0x2776, 0x2770, 0x276a,
+ 0x2764, 0x275e, 0x2758, 0x2752, 0x274c, 0x2746, 0x2740, 0x273a,
+ 0x2734, 0x272e, 0x2728, 0x2722, 0x271c, 0x2716, 0x2710, 0x270a,
+ 0x2704, 0x26fe, 0x26f8, 0x26f2, 0x26ec, 0x26e7, 0x26e1, 0x26db,
+ 0x26d5, 0x26cf, 0x26c9, 0x26c3, 0x26bd, 0x26b7, 0x26b1, 0x26ab,
+ 0x26a5, 0x269f, 0x2699, 0x2693, 0x268d, 0x2687, 0x2681, 0x267b,
+ 0x2675, 0x266f, 0x2669, 0x2663, 0x265d, 0x2657, 0x2651, 0x264b,
+ 0x2645, 0x263f, 0x2639, 0x2633, 0x262d, 0x2627, 0x2621, 0x261b,
+ 0x2615, 0x260f, 0x2609, 0x2603, 0x25fd, 0x25f7, 0x25f1, 0x25eb,
+ 0x25e5, 0x25df, 0x25d9, 0x25d3, 0x25cd, 0x25c7, 0x25c1, 0x25bb,
+ 0x25b5, 0x25af, 0x25a9, 0x25a3, 0x259d, 0x2597, 0x2591, 0x258b,
+ 0x2585, 0x257f, 0x2579, 0x2573, 0x256d, 0x2567, 0x2561, 0x255b,
+ 0x2555, 0x254f, 0x2549, 0x2543, 0x253d, 0x2537, 0x2531, 0x252b,
+ 0x2525, 0x251f, 0x2519, 0x2513, 0x250c, 0x2506, 0x2500, 0x24fa,
+ 0x24f4, 0x24ee, 0x24e8, 0x24e2, 0x24dc, 0x24d6, 0x24d0, 0x24ca,
+ 0x24c4, 0x24be, 0x24b8, 0x24b2, 0x24ac, 0x24a6, 0x24a0, 0x249a,
+ 0x2494, 0x248e, 0x2488, 0x2482, 0x247c, 0x2476, 0x2470, 0x246a,
+ 0x2464, 0x245e, 0x2458, 0x2452, 0x244c, 0x2446, 0x2440, 0x243a,
+ 0x2434, 0x242e, 0x2428, 0x2422, 0x241c, 0x2416, 0x2410, 0x240a,
+ 0x2404, 0x23fd, 0x23f7, 0x23f1, 0x23eb, 0x23e5, 0x23df, 0x23d9,
+ 0x23d3, 0x23cd, 0x23c7, 0x23c1, 0x23bb, 0x23b5, 0x23af, 0x23a9,
+ 0x23a3, 0x239d, 0x2397, 0x2391, 0x238b, 0x2385, 0x237f, 0x2379,
+ 0x2373, 0x236d, 0x2367, 0x2361, 0x235b, 0x2355, 0x234e, 0x2348,
+ 0x2342, 0x233c, 0x2336, 0x2330, 0x232a, 0x2324, 0x231e, 0x2318,
+ 0x2312, 0x230c, 0x2306, 0x2300, 0x22fa, 0x22f4, 0x22ee, 0x22e8,
+ 0x22e2, 0x22dc, 0x22d6, 0x22d0, 0x22ca, 0x22c4, 0x22bd, 0x22b7,
+ 0x22b1, 0x22ab, 0x22a5, 0x229f, 0x2299, 0x2293, 0x228d, 0x2287,
+ 0x2281, 0x227b, 0x2275, 0x226f, 0x2269, 0x2263, 0x225d, 0x2257,
+ 0x2251, 0x224a, 0x2244, 0x223e, 0x2238, 0x2232, 0x222c, 0x2226,
+ 0x2220, 0x221a, 0x2214, 0x220e, 0x2208, 0x2202, 0x21fc, 0x21f6,
+ 0x21f0, 0x21ea, 0x21e4, 0x21dd, 0x21d7, 0x21d1, 0x21cb, 0x21c5,
+ 0x21bf, 0x21b9, 0x21b3, 0x21ad, 0x21a7, 0x21a1, 0x219b, 0x2195,
+ 0x218f, 0x2189, 0x2183, 0x217c, 0x2176, 0x2170, 0x216a, 0x2164,
+ 0x215e, 0x2158, 0x2152, 0x214c, 0x2146, 0x2140, 0x213a, 0x2134,
+ 0x212e, 0x2128, 0x2121, 0x211b, 0x2115, 0x210f, 0x2109, 0x2103,
+ 0x20fd, 0x20f7, 0x20f1, 0x20eb, 0x20e5, 0x20df, 0x20d9, 0x20d3,
+ 0x20cc, 0x20c6, 0x20c0, 0x20ba, 0x20b4, 0x20ae, 0x20a8, 0x20a2,
+ 0x209c, 0x2096, 0x2090, 0x208a, 0x2084, 0x207e, 0x2077, 0x2071,
+ 0x206b, 0x2065, 0x205f, 0x2059, 0x2053, 0x204d, 0x2047, 0x2041,
+ 0x203b, 0x2035, 0x202e, 0x2028, 0x2022, 0x201c, 0x2016, 0x2010,
+ 0x200a, 0x2004, 0x1ffe, 0x1ff8, 0x1ff2, 0x1fec, 0x1fe5, 0x1fdf,
+ 0x1fd9, 0x1fd3, 0x1fcd, 0x1fc7, 0x1fc1, 0x1fbb, 0x1fb5, 0x1faf,
+ 0x1fa9, 0x1fa3, 0x1f9c, 0x1f96, 0x1f90, 0x1f8a, 0x1f84, 0x1f7e,
+ 0x1f78, 0x1f72, 0x1f6c, 0x1f66, 0x1f60, 0x1f59, 0x1f53, 0x1f4d,
+ 0x1f47, 0x1f41, 0x1f3b, 0x1f35, 0x1f2f, 0x1f29, 0x1f23, 0x1f1d,
+ 0x1f16, 0x1f10, 0x1f0a, 0x1f04, 0x1efe, 0x1ef8, 0x1ef2, 0x1eec,
+ 0x1ee6, 0x1ee0, 0x1ed9, 0x1ed3, 0x1ecd, 0x1ec7, 0x1ec1, 0x1ebb,
+ 0x1eb5, 0x1eaf, 0x1ea9, 0x1ea3, 0x1e9c, 0x1e96, 0x1e90, 0x1e8a,
+ 0x1e84, 0x1e7e, 0x1e78, 0x1e72, 0x1e6c, 0x1e66, 0x1e5f, 0x1e59,
+ 0x1e53, 0x1e4d, 0x1e47, 0x1e41, 0x1e3b, 0x1e35, 0x1e2f, 0x1e29,
+ 0x1e22, 0x1e1c, 0x1e16, 0x1e10, 0x1e0a, 0x1e04, 0x1dfe, 0x1df8,
+ 0x1df2, 0x1deb, 0x1de5, 0x1ddf, 0x1dd9, 0x1dd3, 0x1dcd, 0x1dc7,
+ 0x1dc1, 0x1dbb, 0x1db4, 0x1dae, 0x1da8, 0x1da2, 0x1d9c, 0x1d96,
+ 0x1d90, 0x1d8a, 0x1d84, 0x1d7d, 0x1d77, 0x1d71, 0x1d6b, 0x1d65,
+ 0x1d5f, 0x1d59, 0x1d53, 0x1d4c, 0x1d46, 0x1d40, 0x1d3a, 0x1d34,
+ 0x1d2e, 0x1d28, 0x1d22, 0x1d1c, 0x1d15, 0x1d0f, 0x1d09, 0x1d03,
+ 0x1cfd, 0x1cf7, 0x1cf1, 0x1ceb, 0x1ce4, 0x1cde, 0x1cd8, 0x1cd2,
+ 0x1ccc, 0x1cc6, 0x1cc0, 0x1cba, 0x1cb3, 0x1cad, 0x1ca7, 0x1ca1,
+ 0x1c9b, 0x1c95, 0x1c8f, 0x1c89, 0x1c83, 0x1c7c, 0x1c76, 0x1c70,
+ 0x1c6a, 0x1c64, 0x1c5e, 0x1c58, 0x1c51, 0x1c4b, 0x1c45, 0x1c3f,
+ 0x1c39, 0x1c33, 0x1c2d, 0x1c27, 0x1c20, 0x1c1a, 0x1c14, 0x1c0e,
+ 0x1c08, 0x1c02, 0x1bfc, 0x1bf6, 0x1bef, 0x1be9, 0x1be3, 0x1bdd,
+ 0x1bd7, 0x1bd1, 0x1bcb, 0x1bc4, 0x1bbe, 0x1bb8, 0x1bb2, 0x1bac,
+ 0x1ba6, 0x1ba0, 0x1b9a, 0x1b93, 0x1b8d, 0x1b87, 0x1b81, 0x1b7b,
+ 0x1b75, 0x1b6f, 0x1b68, 0x1b62, 0x1b5c, 0x1b56, 0x1b50, 0x1b4a,
+ 0x1b44, 0x1b3d, 0x1b37, 0x1b31, 0x1b2b, 0x1b25, 0x1b1f, 0x1b19,
+ 0x1b13, 0x1b0c, 0x1b06, 0x1b00, 0x1afa, 0x1af4, 0x1aee, 0x1ae8,
+ 0x1ae1, 0x1adb, 0x1ad5, 0x1acf, 0x1ac9, 0x1ac3, 0x1abd, 0x1ab6,
+ 0x1ab0, 0x1aaa, 0x1aa4, 0x1a9e, 0x1a98, 0x1a91, 0x1a8b, 0x1a85,
+ 0x1a7f, 0x1a79, 0x1a73, 0x1a6d, 0x1a66, 0x1a60, 0x1a5a, 0x1a54,
+ 0x1a4e, 0x1a48, 0x1a42, 0x1a3b, 0x1a35, 0x1a2f, 0x1a29, 0x1a23,
+ 0x1a1d, 0x1a17, 0x1a10, 0x1a0a, 0x1a04, 0x19fe, 0x19f8, 0x19f2,
+ 0x19eb, 0x19e5, 0x19df, 0x19d9, 0x19d3, 0x19cd, 0x19c7, 0x19c0,
+ 0x19ba, 0x19b4, 0x19ae, 0x19a8, 0x19a2, 0x199b, 0x1995, 0x198f,
+ 0x1989, 0x1983, 0x197d, 0x1977, 0x1970, 0x196a, 0x1964, 0x195e,
+ 0x1958, 0x1952, 0x194b, 0x1945, 0x193f, 0x1939, 0x1933, 0x192d,
+ 0x1926, 0x1920, 0x191a, 0x1914, 0x190e, 0x1908, 0x1901, 0x18fb,
+ 0x18f5, 0x18ef, 0x18e9, 0x18e3, 0x18dc, 0x18d6, 0x18d0, 0x18ca,
+ 0x18c4, 0x18be, 0x18b8, 0x18b1, 0x18ab, 0x18a5, 0x189f, 0x1899,
+ 0x1893, 0x188c, 0x1886, 0x1880, 0x187a, 0x1874, 0x186e, 0x1867,
+ 0x1861, 0x185b, 0x1855, 0x184f, 0x1848, 0x1842, 0x183c, 0x1836,
+ 0x1830, 0x182a, 0x1823, 0x181d, 0x1817, 0x1811, 0x180b, 0x1805,
+ 0x17fe, 0x17f8, 0x17f2, 0x17ec, 0x17e6, 0x17e0, 0x17d9, 0x17d3,
+ 0x17cd, 0x17c7, 0x17c1, 0x17bb, 0x17b4, 0x17ae, 0x17a8, 0x17a2,
+ 0x179c, 0x1795, 0x178f, 0x1789, 0x1783, 0x177d, 0x1777, 0x1770,
+ 0x176a, 0x1764, 0x175e, 0x1758, 0x1752, 0x174b, 0x1745, 0x173f,
+ 0x1739, 0x1733, 0x172c, 0x1726, 0x1720, 0x171a, 0x1714, 0x170e,
+ 0x1707, 0x1701, 0x16fb, 0x16f5, 0x16ef, 0x16e8, 0x16e2, 0x16dc,
+ 0x16d6, 0x16d0, 0x16ca, 0x16c3, 0x16bd, 0x16b7, 0x16b1, 0x16ab,
+ 0x16a4, 0x169e, 0x1698, 0x1692, 0x168c, 0x1686, 0x167f, 0x1679,
+ 0x1673, 0x166d, 0x1667, 0x1660, 0x165a, 0x1654, 0x164e, 0x1648,
+ 0x1642, 0x163b, 0x1635, 0x162f, 0x1629, 0x1623, 0x161c, 0x1616,
+ 0x1610, 0x160a, 0x1604, 0x15fd, 0x15f7, 0x15f1, 0x15eb, 0x15e5,
+ 0x15de, 0x15d8, 0x15d2, 0x15cc, 0x15c6, 0x15c0, 0x15b9, 0x15b3,
+ 0x15ad, 0x15a7, 0x15a1, 0x159a, 0x1594, 0x158e, 0x1588, 0x1582,
+ 0x157b, 0x1575, 0x156f, 0x1569, 0x1563, 0x155c, 0x1556, 0x1550,
+ 0x154a, 0x1544, 0x153d, 0x1537, 0x1531, 0x152b, 0x1525, 0x151e,
+ 0x1518, 0x1512, 0x150c, 0x1506, 0x14ff, 0x14f9, 0x14f3, 0x14ed,
+ 0x14e7, 0x14e0, 0x14da, 0x14d4, 0x14ce, 0x14c8, 0x14c1, 0x14bb,
+ 0x14b5, 0x14af, 0x14a9, 0x14a2, 0x149c, 0x1496, 0x1490, 0x148a,
+ 0x1483, 0x147d, 0x1477, 0x1471, 0x146b, 0x1464, 0x145e, 0x1458,
+ 0x1452, 0x144c, 0x1445, 0x143f, 0x1439, 0x1433, 0x142d, 0x1426,
+ 0x1420, 0x141a, 0x1414, 0x140e, 0x1407, 0x1401, 0x13fb, 0x13f5,
+ 0x13ef, 0x13e8, 0x13e2, 0x13dc, 0x13d6, 0x13d0, 0x13c9, 0x13c3,
+ 0x13bd, 0x13b7, 0x13b1, 0x13aa, 0x13a4, 0x139e, 0x1398, 0x1391,
+ 0x138b, 0x1385, 0x137f, 0x1379, 0x1372, 0x136c, 0x1366, 0x1360,
+ 0x135a, 0x1353, 0x134d, 0x1347, 0x1341, 0x133b, 0x1334, 0x132e,
+ 0x1328, 0x1322, 0x131b, 0x1315, 0x130f, 0x1309, 0x1303, 0x12fc,
+ 0x12f6, 0x12f0, 0x12ea, 0x12e4, 0x12dd, 0x12d7, 0x12d1, 0x12cb,
+ 0x12c4, 0x12be, 0x12b8, 0x12b2, 0x12ac, 0x12a5, 0x129f, 0x1299,
+ 0x1293, 0x128d, 0x1286, 0x1280, 0x127a, 0x1274, 0x126d, 0x1267,
+ 0x1261, 0x125b, 0x1255, 0x124e, 0x1248, 0x1242, 0x123c, 0x1235,
+ 0x122f, 0x1229, 0x1223, 0x121d, 0x1216, 0x1210, 0x120a, 0x1204,
+ 0x11fd, 0x11f7, 0x11f1, 0x11eb, 0x11e5, 0x11de, 0x11d8, 0x11d2,
+ 0x11cc, 0x11c5, 0x11bf, 0x11b9, 0x11b3, 0x11ad, 0x11a6, 0x11a0,
+ 0x119a, 0x1194, 0x118d, 0x1187, 0x1181, 0x117b, 0x1175, 0x116e,
+ 0x1168, 0x1162, 0x115c, 0x1155, 0x114f, 0x1149, 0x1143, 0x113d,
+ 0x1136, 0x1130, 0x112a, 0x1124, 0x111d, 0x1117, 0x1111, 0x110b,
+ 0x1105, 0x10fe, 0x10f8, 0x10f2, 0x10ec, 0x10e5, 0x10df, 0x10d9,
+ 0x10d3, 0x10cc, 0x10c6, 0x10c0, 0x10ba, 0x10b4, 0x10ad, 0x10a7,
+ 0x10a1, 0x109b, 0x1094, 0x108e, 0x1088, 0x1082, 0x107b, 0x1075,
+ 0x106f, 0x1069, 0x1063, 0x105c, 0x1056, 0x1050, 0x104a, 0x1043,
+ 0x103d, 0x1037, 0x1031, 0x102a, 0x1024, 0x101e, 0x1018, 0x1012,
+ 0x100b, 0x1005, 0xfff, 0xff9, 0xff2, 0xfec, 0xfe6, 0xfe0,
+ 0xfd9, 0xfd3, 0xfcd, 0xfc7, 0xfc0, 0xfba, 0xfb4, 0xfae,
+ 0xfa8, 0xfa1, 0xf9b, 0xf95, 0xf8f, 0xf88, 0xf82, 0xf7c,
+ 0xf76, 0xf6f, 0xf69, 0xf63, 0xf5d, 0xf56, 0xf50, 0xf4a,
+ 0xf44, 0xf3e, 0xf37, 0xf31, 0xf2b, 0xf25, 0xf1e, 0xf18,
+ 0xf12, 0xf0c, 0xf05, 0xeff, 0xef9, 0xef3, 0xeec, 0xee6,
+ 0xee0, 0xeda, 0xed3, 0xecd, 0xec7, 0xec1, 0xeba, 0xeb4,
+ 0xeae, 0xea8, 0xea1, 0xe9b, 0xe95, 0xe8f, 0xe89, 0xe82,
+ 0xe7c, 0xe76, 0xe70, 0xe69, 0xe63, 0xe5d, 0xe57, 0xe50,
+ 0xe4a, 0xe44, 0xe3e, 0xe37, 0xe31, 0xe2b, 0xe25, 0xe1e,
+ 0xe18, 0xe12, 0xe0c, 0xe05, 0xdff, 0xdf9, 0xdf3, 0xdec,
+ 0xde6, 0xde0, 0xdda, 0xdd3, 0xdcd, 0xdc7, 0xdc1, 0xdba,
+ 0xdb4, 0xdae, 0xda8, 0xda1, 0xd9b, 0xd95, 0xd8f, 0xd88,
+ 0xd82, 0xd7c, 0xd76, 0xd6f, 0xd69, 0xd63, 0xd5d, 0xd56,
+ 0xd50, 0xd4a, 0xd44, 0xd3d, 0xd37, 0xd31, 0xd2b, 0xd24,
+ 0xd1e, 0xd18, 0xd12, 0xd0b, 0xd05, 0xcff, 0xcf9, 0xcf2,
+ 0xcec, 0xce6, 0xce0, 0xcd9, 0xcd3, 0xccd, 0xcc7, 0xcc0,
+ 0xcba, 0xcb4, 0xcae, 0xca7, 0xca1, 0xc9b, 0xc95, 0xc8e,
+ 0xc88, 0xc82, 0xc7c, 0xc75, 0xc6f, 0xc69, 0xc63, 0xc5c,
+ 0xc56, 0xc50, 0xc4a, 0xc43, 0xc3d, 0xc37, 0xc31, 0xc2a,
+ 0xc24, 0xc1e, 0xc18, 0xc11, 0xc0b, 0xc05, 0xbff, 0xbf8,
+ 0xbf2, 0xbec, 0xbe6, 0xbdf, 0xbd9, 0xbd3, 0xbcd, 0xbc6,
+ 0xbc0, 0xbba, 0xbb4, 0xbad, 0xba7, 0xba1, 0xb9b, 0xb94,
+ 0xb8e, 0xb88, 0xb81, 0xb7b, 0xb75, 0xb6f, 0xb68, 0xb62,
+ 0xb5c, 0xb56, 0xb4f, 0xb49, 0xb43, 0xb3d, 0xb36, 0xb30,
+ 0xb2a, 0xb24, 0xb1d, 0xb17, 0xb11, 0xb0b, 0xb04, 0xafe,
+ 0xaf8, 0xaf2, 0xaeb, 0xae5, 0xadf, 0xad8, 0xad2, 0xacc,
+ 0xac6, 0xabf, 0xab9, 0xab3, 0xaad, 0xaa6, 0xaa0, 0xa9a,
+ 0xa94, 0xa8d, 0xa87, 0xa81, 0xa7b, 0xa74, 0xa6e, 0xa68,
+ 0xa62, 0xa5b, 0xa55, 0xa4f, 0xa48, 0xa42, 0xa3c, 0xa36,
+ 0xa2f, 0xa29, 0xa23, 0xa1d, 0xa16, 0xa10, 0xa0a, 0xa04,
+ 0x9fd, 0x9f7, 0x9f1, 0x9eb, 0x9e4, 0x9de, 0x9d8, 0x9d1,
+ 0x9cb, 0x9c5, 0x9bf, 0x9b8, 0x9b2, 0x9ac, 0x9a6, 0x99f,
+ 0x999, 0x993, 0x98d, 0x986, 0x980, 0x97a, 0x973, 0x96d,
+ 0x967, 0x961, 0x95a, 0x954, 0x94e, 0x948, 0x941, 0x93b,
+ 0x935, 0x92f, 0x928, 0x922, 0x91c, 0x915, 0x90f, 0x909,
+ 0x903, 0x8fc, 0x8f6, 0x8f0, 0x8ea, 0x8e3, 0x8dd, 0x8d7,
+ 0x8d1, 0x8ca, 0x8c4, 0x8be, 0x8b7, 0x8b1, 0x8ab, 0x8a5,
+ 0x89e, 0x898, 0x892, 0x88c, 0x885, 0x87f, 0x879, 0x872,
+ 0x86c, 0x866, 0x860, 0x859, 0x853, 0x84d, 0x847, 0x840,
+ 0x83a, 0x834, 0x82e, 0x827, 0x821, 0x81b, 0x814, 0x80e,
+ 0x808, 0x802, 0x7fb, 0x7f5, 0x7ef, 0x7e9, 0x7e2, 0x7dc,
+ 0x7d6, 0x7cf, 0x7c9, 0x7c3, 0x7bd, 0x7b6, 0x7b0, 0x7aa,
+ 0x7a4, 0x79d, 0x797, 0x791, 0x78a, 0x784, 0x77e, 0x778,
+ 0x771, 0x76b, 0x765, 0x75f, 0x758, 0x752, 0x74c, 0x745,
+ 0x73f, 0x739, 0x733, 0x72c, 0x726, 0x720, 0x71a, 0x713,
+ 0x70d, 0x707, 0x700, 0x6fa, 0x6f4, 0x6ee, 0x6e7, 0x6e1,
+ 0x6db, 0x6d5, 0x6ce, 0x6c8, 0x6c2, 0x6bb, 0x6b5, 0x6af,
+ 0x6a9, 0x6a2, 0x69c, 0x696, 0x690, 0x689, 0x683, 0x67d,
+ 0x676, 0x670, 0x66a, 0x664, 0x65d, 0x657, 0x651, 0x64a,
+ 0x644, 0x63e, 0x638, 0x631, 0x62b, 0x625, 0x61f, 0x618,
+ 0x612, 0x60c, 0x605, 0x5ff, 0x5f9, 0x5f3, 0x5ec, 0x5e6,
+ 0x5e0, 0x5da, 0x5d3, 0x5cd, 0x5c7, 0x5c0, 0x5ba, 0x5b4,
+ 0x5ae, 0x5a7, 0x5a1, 0x59b, 0x594, 0x58e, 0x588, 0x582,
+ 0x57b, 0x575, 0x56f, 0x569, 0x562, 0x55c, 0x556, 0x54f,
+ 0x549, 0x543, 0x53d, 0x536, 0x530, 0x52a, 0x523, 0x51d,
+ 0x517, 0x511, 0x50a, 0x504, 0x4fe, 0x4f8, 0x4f1, 0x4eb,
+ 0x4e5, 0x4de, 0x4d8, 0x4d2, 0x4cc, 0x4c5, 0x4bf, 0x4b9,
+ 0x4b2, 0x4ac, 0x4a6, 0x4a0, 0x499, 0x493, 0x48d, 0x487,
+ 0x480, 0x47a, 0x474, 0x46d, 0x467, 0x461, 0x45b, 0x454,
+ 0x44e, 0x448, 0x441, 0x43b, 0x435, 0x42f, 0x428, 0x422,
+ 0x41c, 0x415, 0x40f, 0x409, 0x403, 0x3fc, 0x3f6, 0x3f0,
+ 0x3ea, 0x3e3, 0x3dd, 0x3d7, 0x3d0, 0x3ca, 0x3c4, 0x3be,
+ 0x3b7, 0x3b1, 0x3ab, 0x3a4, 0x39e, 0x398, 0x392, 0x38b,
+ 0x385, 0x37f, 0x378, 0x372, 0x36c, 0x366, 0x35f, 0x359,
+ 0x353, 0x34c, 0x346, 0x340, 0x33a, 0x333, 0x32d, 0x327,
+ 0x321, 0x31a, 0x314, 0x30e, 0x307, 0x301, 0x2fb, 0x2f5,
+ 0x2ee, 0x2e8, 0x2e2, 0x2db, 0x2d5, 0x2cf, 0x2c9, 0x2c2,
+ 0x2bc, 0x2b6, 0x2af, 0x2a9, 0x2a3, 0x29d, 0x296, 0x290,
+ 0x28a, 0x283, 0x27d, 0x277, 0x271, 0x26a, 0x264, 0x25e,
+ 0x258, 0x251, 0x24b, 0x245, 0x23e, 0x238, 0x232, 0x22c,
+ 0x225, 0x21f, 0x219, 0x212, 0x20c, 0x206, 0x200, 0x1f9,
+ 0x1f3, 0x1ed, 0x1e6, 0x1e0, 0x1da, 0x1d4, 0x1cd, 0x1c7,
+ 0x1c1, 0x1ba, 0x1b4, 0x1ae, 0x1a8, 0x1a1, 0x19b, 0x195,
+ 0x18e, 0x188, 0x182, 0x17c, 0x175, 0x16f, 0x169, 0x162,
+ 0x15c, 0x156, 0x150, 0x149, 0x143, 0x13d, 0x137, 0x130,
+ 0x12a, 0x124, 0x11d, 0x117, 0x111, 0x10b, 0x104, 0xfe,
+ 0xf8, 0xf1, 0xeb, 0xe5, 0xdf, 0xd8, 0xd2, 0xcc,
+ 0xc5, 0xbf, 0xb9, 0xb3, 0xac, 0xa6, 0xa0, 0x99,
+ 0x93, 0x8d, 0x87, 0x80, 0x7a, 0x74, 0x6d, 0x67,
+ 0x61, 0x5b, 0x54, 0x4e, 0x48, 0x41, 0x3b, 0x35,
+ 0x2f, 0x28, 0x22, 0x1c, 0x15, 0xf, 0x9, 0x3,
+};
+
+/**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ * \par Normalizing factor:
+ * The normalizing factor is <code>sqrt(2/N)</code>, which depends on the size of transform <code>N</code>.
+ * Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes:
+ * \image html dct4NormalizingQ15Table.gif
+ */
+
+arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initializing the pointer array with the weight table base addresses of different lengths */
+ q15_t *twiddlePtr[4] = { (q15_t *) WeightsQ15_128, (q15_t *) WeightsQ15_512,
+ (q15_t *) WeightsQ15_2048, (q15_t *) WeightsQ15_8192
+ };
+
+ /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+ q15_t *pCosFactor[4] =
+ { (q15_t *) cos_factorsQ15_128, (q15_t *) cos_factorsQ15_512,
+ (q15_t *) cos_factorsQ15_2048, (q15_t *) cos_factorsQ15_8192
+ };
+
+ /* Initialize the DCT4 length */
+ S->N = N;
+
+ /* Initialize the half of DCT4 length */
+ S->Nby2 = Nby2;
+
+ /* Initialize the DCT4 Normalizing factor */
+ S->normalize = normalize;
+
+ /* Initialize Real FFT Instance */
+ S->pRfft = S_RFFT;
+
+ /* Initialize Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ switch (N)
+ {
+ /* Initialize the table modifier values */
+ case 8192u:
+ S->pTwiddle = twiddlePtr[3];
+ S->pCosFactor = pCosFactor[3];
+ break;
+ case 2048u:
+ S->pTwiddle = twiddlePtr[2];
+ S->pCosFactor = pCosFactor[2];
+ break;
+ case 512u:
+ S->pTwiddle = twiddlePtr[1];
+ S->pCosFactor = pCosFactor[1];
+ break;
+ case 128u:
+ S->pTwiddle = twiddlePtr[0];
+ S->pCosFactor = pCosFactor[0];
+ break;
+ default:
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+
+ /* Initialize the RFFT/RIFFT */
+ arm_rfft_init_q15(S->pRfft, S->pCfft, S->N, 0u, 1u);
+
+ /* return the status of DCT4 Init function */
+ return (status);
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_q31.c
new file mode 100644
index 000000000..673628db0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_init_q31.c
@@ -0,0 +1,8364 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_init_q31.c
+*
+* Description: Initialization function of DCT-4 & IDCT4 Q31
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/*
+* @brief Weights Table
+*/
+
+/**
+* \par
+* Weights tables are generated using the formula : <pre>weights[n] = e^(-j*n*pi/(2*N))</pre>
+* \par
+* C command to generate the table
+* <pre>
+* for(i = 0; i< N; i++)
+* {
+* weights[2*i]= cos(i*c);
+* weights[(2*i)+1]= -sin(i * c);
+* } </pre>
+* \par
+* where <code>N</code> is the Number of weights to be calculated and <code>c</code> is <code>pi/(2*N)</code>
+* \par
+* Convert the output to q31 format by multiplying with 2^31 and saturated if required.
+* \par
+* In the tables below the real and imaginary values are placed alternatively, hence the
+* array length is <code>2*N</code>.
+*/
+
+static const q31_t WeightsQ31_128[256] = {
+ 0x7fffffff, 0x0, 0x7ffd885a, 0xfe6de2e0, 0x7ff62182, 0xfcdbd541, 0x7fe9cbc0,
+ 0xfb49e6a3,
+ 0x7fd8878e, 0xf9b82684, 0x7fc25596, 0xf826a462, 0x7fa736b4, 0xf6956fb7,
+ 0x7f872bf3, 0xf50497fb,
+ 0x7f62368f, 0xf3742ca2, 0x7f3857f6, 0xf1e43d1c, 0x7f0991c4, 0xf054d8d5,
+ 0x7ed5e5c6, 0xeec60f31,
+ 0x7e9d55fc, 0xed37ef91, 0x7e5fe493, 0xebaa894f, 0x7e1d93ea, 0xea1debbb,
+ 0x7dd6668f, 0xe8922622,
+ 0x7d8a5f40, 0xe70747c4, 0x7d3980ec, 0xe57d5fda, 0x7ce3ceb2, 0xe3f47d96,
+ 0x7c894bde, 0xe26cb01b,
+ 0x7c29fbee, 0xe0e60685, 0x7bc5e290, 0xdf608fe4, 0x7b5d039e, 0xdddc5b3b,
+ 0x7aef6323, 0xdc597781,
+ 0x7a7d055b, 0xdad7f3a2, 0x7a05eead, 0xd957de7a, 0x798a23b1, 0xd7d946d8,
+ 0x7909a92d, 0xd65c3b7b,
+ 0x78848414, 0xd4e0cb15, 0x77fab989, 0xd3670446, 0x776c4edb, 0xd1eef59e,
+ 0x76d94989, 0xd078ad9e,
+ 0x7641af3d, 0xcf043ab3, 0x75a585cf, 0xcd91ab39, 0x7504d345, 0xcc210d79,
+ 0x745f9dd1, 0xcab26fa9,
+ 0x73b5ebd1, 0xc945dfec, 0x7307c3d0, 0xc7db6c50, 0x72552c85, 0xc67322ce,
+ 0x719e2cd2, 0xc50d1149,
+ 0x70e2cbc6, 0xc3a94590, 0x7023109a, 0xc247cd5a, 0x6f5f02b2, 0xc0e8b648,
+ 0x6e96a99d, 0xbf8c0de3,
+ 0x6dca0d14, 0xbe31e19b, 0x6cf934fc, 0xbcda3ecb, 0x6c242960, 0xbb8532b0,
+ 0x6b4af279, 0xba32ca71,
+ 0x6a6d98a4, 0xb8e31319, 0x698c246c, 0xb796199b, 0x68a69e81, 0xb64beacd,
+ 0x67bd0fbd, 0xb5049368,
+ 0x66cf8120, 0xb3c0200c, 0x65ddfbd3, 0xb27e9d3c, 0x64e88926, 0xb140175b,
+ 0x63ef3290, 0xb0049ab3,
+ 0x62f201ac, 0xaecc336c, 0x61f1003f, 0xad96ed92, 0x60ec3830, 0xac64d510,
+ 0x5fe3b38d, 0xab35f5b5,
+ 0x5ed77c8a, 0xaa0a5b2e, 0x5dc79d7c, 0xa8e21106, 0x5cb420e0, 0xa7bd22ac,
+ 0x5b9d1154, 0xa69b9b68,
+ 0x5a82799a, 0xa57d8666, 0x59646498, 0xa462eeac, 0x5842dd54, 0xa34bdf20,
+ 0x571deefa, 0xa2386284,
+ 0x55f5a4d2, 0xa1288376, 0x54ca0a4b, 0xa01c4c73, 0x539b2af0, 0x9f13c7d0,
+ 0x5269126e, 0x9e0effc1,
+ 0x5133cc94, 0x9d0dfe54, 0x4ffb654d, 0x9c10cd70, 0x4ebfe8a5, 0x9b1776da,
+ 0x4d8162c4, 0x9a22042d,
+ 0x4c3fdff4, 0x99307ee0, 0x4afb6c98, 0x9842f043, 0x49b41533, 0x9759617f,
+ 0x4869e665, 0x9673db94,
+ 0x471cece7, 0x9592675c, 0x45cd358f, 0x94b50d87, 0x447acd50, 0x93dbd6a0,
+ 0x4325c135, 0x9306cb04,
+ 0x41ce1e65, 0x9235f2ec, 0x4073f21d, 0x91695663, 0x3f1749b8, 0x90a0fd4e,
+ 0x3db832a6, 0x8fdcef66,
+ 0x3c56ba70, 0x8f1d343a, 0x3af2eeb7, 0x8e61d32e, 0x398cdd32, 0x8daad37b,
+ 0x382493b0, 0x8cf83c30,
+ 0x36ba2014, 0x8c4a142f, 0x354d9057, 0x8ba0622f, 0x33def287, 0x8afb2cbb,
+ 0x326e54c7, 0x8a5a7a31,
+ 0x30fbc54d, 0x89be50c3, 0x2f875262, 0x8926b677, 0x2e110a62, 0x8893b125,
+ 0x2c98fbba, 0x88054677,
+ 0x2b1f34eb, 0x877b7bec, 0x29a3c485, 0x86f656d3, 0x2826b928, 0x8675dc4f,
+ 0x26a82186, 0x85fa1153,
+ 0x25280c5e, 0x8582faa5, 0x23a6887f, 0x85109cdd, 0x2223a4c5, 0x84a2fc62,
+ 0x209f701c, 0x843a1d70,
+ 0x1f19f97b, 0x83d60412, 0x1d934fe5, 0x8376b422, 0x1c0b826a, 0x831c314e,
+ 0x1a82a026, 0x82c67f14,
+ 0x18f8b83c, 0x8275a0c0, 0x176dd9de, 0x82299971, 0x15e21445, 0x81e26c16,
+ 0x145576b1, 0x81a01b6d,
+ 0x12c8106f, 0x8162aa04, 0x1139f0cf, 0x812a1a3a, 0xfab272b, 0x80f66e3c,
+ 0xe1bc2e4, 0x80c7a80a,
+ 0xc8bd35e, 0x809dc971, 0xafb6805, 0x8078d40d, 0x96a9049, 0x8058c94c,
+ 0x7d95b9e, 0x803daa6a,
+ 0x647d97c, 0x80277872, 0x4b6195d, 0x80163440, 0x3242abf, 0x8009de7e,
+ 0x1921d20, 0x800277a6,
+};
+
+static const q31_t WeightsQ31_512[1024] = {
+ 0x7fffffff, 0x0, 0x7fffd886, 0xff9b781d, 0x7fff6216, 0xff36f078, 0x7ffe9cb2,
+ 0xfed2694f,
+ 0x7ffd885a, 0xfe6de2e0, 0x7ffc250f, 0xfe095d69, 0x7ffa72d1, 0xfda4d929,
+ 0x7ff871a2, 0xfd40565c,
+ 0x7ff62182, 0xfcdbd541, 0x7ff38274, 0xfc775616, 0x7ff09478, 0xfc12d91a,
+ 0x7fed5791, 0xfbae5e89,
+ 0x7fe9cbc0, 0xfb49e6a3, 0x7fe5f108, 0xfae571a4, 0x7fe1c76b, 0xfa80ffcb,
+ 0x7fdd4eec, 0xfa1c9157,
+ 0x7fd8878e, 0xf9b82684, 0x7fd37153, 0xf953bf91, 0x7fce0c3e, 0xf8ef5cbb,
+ 0x7fc85854, 0xf88afe42,
+ 0x7fc25596, 0xf826a462, 0x7fbc040a, 0xf7c24f59, 0x7fb563b3, 0xf75dff66,
+ 0x7fae7495, 0xf6f9b4c6,
+ 0x7fa736b4, 0xf6956fb7, 0x7f9faa15, 0xf6313077, 0x7f97cebd, 0xf5ccf743,
+ 0x7f8fa4b0, 0xf568c45b,
+ 0x7f872bf3, 0xf50497fb, 0x7f7e648c, 0xf4a07261, 0x7f754e80, 0xf43c53cb,
+ 0x7f6be9d4, 0xf3d83c77,
+ 0x7f62368f, 0xf3742ca2, 0x7f5834b7, 0xf310248a, 0x7f4de451, 0xf2ac246e,
+ 0x7f434563, 0xf2482c8a,
+ 0x7f3857f6, 0xf1e43d1c, 0x7f2d1c0e, 0xf1805662, 0x7f2191b4, 0xf11c789a,
+ 0x7f15b8ee, 0xf0b8a401,
+ 0x7f0991c4, 0xf054d8d5, 0x7efd1c3c, 0xeff11753, 0x7ef05860, 0xef8d5fb8,
+ 0x7ee34636, 0xef29b243,
+ 0x7ed5e5c6, 0xeec60f31, 0x7ec8371a, 0xee6276bf, 0x7eba3a39, 0xedfee92b,
+ 0x7eabef2c, 0xed9b66b2,
+ 0x7e9d55fc, 0xed37ef91, 0x7e8e6eb2, 0xecd48407, 0x7e7f3957, 0xec71244f,
+ 0x7e6fb5f4, 0xec0dd0a8,
+ 0x7e5fe493, 0xebaa894f, 0x7e4fc53e, 0xeb474e81, 0x7e3f57ff, 0xeae4207a,
+ 0x7e2e9cdf, 0xea80ff7a,
+ 0x7e1d93ea, 0xea1debbb, 0x7e0c3d29, 0xe9bae57d, 0x7dfa98a8, 0xe957ecfb,
+ 0x7de8a670, 0xe8f50273,
+ 0x7dd6668f, 0xe8922622, 0x7dc3d90d, 0xe82f5844, 0x7db0fdf8, 0xe7cc9917,
+ 0x7d9dd55a, 0xe769e8d8,
+ 0x7d8a5f40, 0xe70747c4, 0x7d769bb5, 0xe6a4b616, 0x7d628ac6, 0xe642340d,
+ 0x7d4e2c7f, 0xe5dfc1e5,
+ 0x7d3980ec, 0xe57d5fda, 0x7d24881b, 0xe51b0e2a, 0x7d0f4218, 0xe4b8cd11,
+ 0x7cf9aef0, 0xe4569ccb,
+ 0x7ce3ceb2, 0xe3f47d96, 0x7ccda169, 0xe3926fad, 0x7cb72724, 0xe330734d,
+ 0x7ca05ff1, 0xe2ce88b3,
+ 0x7c894bde, 0xe26cb01b, 0x7c71eaf9, 0xe20ae9c1, 0x7c5a3d50, 0xe1a935e2,
+ 0x7c4242f2, 0xe14794ba,
+ 0x7c29fbee, 0xe0e60685, 0x7c116853, 0xe0848b7f, 0x7bf88830, 0xe02323e5,
+ 0x7bdf5b94, 0xdfc1cff3,
+ 0x7bc5e290, 0xdf608fe4, 0x7bac1d31, 0xdeff63f4, 0x7b920b89, 0xde9e4c60,
+ 0x7b77ada8, 0xde3d4964,
+ 0x7b5d039e, 0xdddc5b3b, 0x7b420d7a, 0xdd7b8220, 0x7b26cb4f, 0xdd1abe51,
+ 0x7b0b3d2c, 0xdcba1008,
+ 0x7aef6323, 0xdc597781, 0x7ad33d45, 0xdbf8f4f8, 0x7ab6cba4, 0xdb9888a8,
+ 0x7a9a0e50, 0xdb3832cd,
+ 0x7a7d055b, 0xdad7f3a2, 0x7a5fb0d8, 0xda77cb63, 0x7a4210d8, 0xda17ba4a,
+ 0x7a24256f, 0xd9b7c094,
+ 0x7a05eead, 0xd957de7a, 0x79e76ca7, 0xd8f81439, 0x79c89f6e, 0xd898620c,
+ 0x79a98715, 0xd838c82d,
+ 0x798a23b1, 0xd7d946d8, 0x796a7554, 0xd779de47, 0x794a7c12, 0xd71a8eb5,
+ 0x792a37fe, 0xd6bb585e,
+ 0x7909a92d, 0xd65c3b7b, 0x78e8cfb2, 0xd5fd3848, 0x78c7aba2, 0xd59e4eff,
+ 0x78a63d11, 0xd53f7fda,
+ 0x78848414, 0xd4e0cb15, 0x786280bf, 0xd48230e9, 0x78403329, 0xd423b191,
+ 0x781d9b65, 0xd3c54d47,
+ 0x77fab989, 0xd3670446, 0x77d78daa, 0xd308d6c7, 0x77b417df, 0xd2aac504,
+ 0x7790583e, 0xd24ccf39,
+ 0x776c4edb, 0xd1eef59e, 0x7747fbce, 0xd191386e, 0x77235f2d, 0xd13397e2,
+ 0x76fe790e, 0xd0d61434,
+ 0x76d94989, 0xd078ad9e, 0x76b3d0b4, 0xd01b6459, 0x768e0ea6, 0xcfbe389f,
+ 0x76680376, 0xcf612aaa,
+ 0x7641af3d, 0xcf043ab3, 0x761b1211, 0xcea768f2, 0x75f42c0b, 0xce4ab5a2,
+ 0x75ccfd42, 0xcdee20fc,
+ 0x75a585cf, 0xcd91ab39, 0x757dc5ca, 0xcd355491, 0x7555bd4c, 0xccd91d3d,
+ 0x752d6c6c, 0xcc7d0578,
+ 0x7504d345, 0xcc210d79, 0x74dbf1ef, 0xcbc53579, 0x74b2c884, 0xcb697db0,
+ 0x7489571c, 0xcb0de658,
+ 0x745f9dd1, 0xcab26fa9, 0x74359cbd, 0xca5719db, 0x740b53fb, 0xc9fbe527,
+ 0x73e0c3a3, 0xc9a0d1c5,
+ 0x73b5ebd1, 0xc945dfec, 0x738acc9e, 0xc8eb0fd6, 0x735f6626, 0xc89061ba,
+ 0x7333b883, 0xc835d5d0,
+ 0x7307c3d0, 0xc7db6c50, 0x72db8828, 0xc7812572, 0x72af05a7, 0xc727016d,
+ 0x72823c67, 0xc6cd0079,
+ 0x72552c85, 0xc67322ce, 0x7227d61c, 0xc61968a2, 0x71fa3949, 0xc5bfd22e,
+ 0x71cc5626, 0xc5665fa9,
+ 0x719e2cd2, 0xc50d1149, 0x716fbd68, 0xc4b3e746, 0x71410805, 0xc45ae1d7,
+ 0x71120cc5, 0xc4020133,
+ 0x70e2cbc6, 0xc3a94590, 0x70b34525, 0xc350af26, 0x708378ff, 0xc2f83e2a,
+ 0x70536771, 0xc29ff2d4,
+ 0x7023109a, 0xc247cd5a, 0x6ff27497, 0xc1efcdf3, 0x6fc19385, 0xc197f4d4,
+ 0x6f906d84, 0xc1404233,
+ 0x6f5f02b2, 0xc0e8b648, 0x6f2d532c, 0xc0915148, 0x6efb5f12, 0xc03a1368,
+ 0x6ec92683, 0xbfe2fcdf,
+ 0x6e96a99d, 0xbf8c0de3, 0x6e63e87f, 0xbf3546a8, 0x6e30e34a, 0xbedea765,
+ 0x6dfd9a1c, 0xbe88304f,
+ 0x6dca0d14, 0xbe31e19b, 0x6d963c54, 0xbddbbb7f, 0x6d6227fa, 0xbd85be30,
+ 0x6d2dd027, 0xbd2fe9e2,
+ 0x6cf934fc, 0xbcda3ecb, 0x6cc45698, 0xbc84bd1f, 0x6c8f351c, 0xbc2f6513,
+ 0x6c59d0a9, 0xbbda36dd,
+ 0x6c242960, 0xbb8532b0, 0x6bee3f62, 0xbb3058c0, 0x6bb812d1, 0xbadba943,
+ 0x6b81a3cd, 0xba87246d,
+ 0x6b4af279, 0xba32ca71, 0x6b13fef5, 0xb9de9b83, 0x6adcc964, 0xb98a97d8,
+ 0x6aa551e9, 0xb936bfa4,
+ 0x6a6d98a4, 0xb8e31319, 0x6a359db9, 0xb88f926d, 0x69fd614a, 0xb83c3dd1,
+ 0x69c4e37a, 0xb7e9157a,
+ 0x698c246c, 0xb796199b, 0x69532442, 0xb7434a67, 0x6919e320, 0xb6f0a812,
+ 0x68e06129, 0xb69e32cd,
+ 0x68a69e81, 0xb64beacd, 0x686c9b4b, 0xb5f9d043, 0x683257ab, 0xb5a7e362,
+ 0x67f7d3c5, 0xb556245e,
+ 0x67bd0fbd, 0xb5049368, 0x67820bb7, 0xb4b330b3, 0x6746c7d8, 0xb461fc70,
+ 0x670b4444, 0xb410f6d3,
+ 0x66cf8120, 0xb3c0200c, 0x66937e91, 0xb36f784f, 0x66573cbb, 0xb31effcc,
+ 0x661abbc5, 0xb2ceb6b5,
+ 0x65ddfbd3, 0xb27e9d3c, 0x65a0fd0b, 0xb22eb392, 0x6563bf92, 0xb1def9e9,
+ 0x6526438f, 0xb18f7071,
+ 0x64e88926, 0xb140175b, 0x64aa907f, 0xb0f0eeda, 0x646c59bf, 0xb0a1f71d,
+ 0x642de50d, 0xb0533055,
+ 0x63ef3290, 0xb0049ab3, 0x63b0426d, 0xafb63667, 0x637114cc, 0xaf6803a2,
+ 0x6331a9d4, 0xaf1a0293,
+ 0x62f201ac, 0xaecc336c, 0x62b21c7b, 0xae7e965b, 0x6271fa69, 0xae312b92,
+ 0x62319b9d, 0xade3f33e,
+ 0x61f1003f, 0xad96ed92, 0x61b02876, 0xad4a1aba, 0x616f146c, 0xacfd7ae8,
+ 0x612dc447, 0xacb10e4b,
+ 0x60ec3830, 0xac64d510, 0x60aa7050, 0xac18cf69, 0x60686ccf, 0xabccfd83,
+ 0x60262dd6, 0xab815f8d,
+ 0x5fe3b38d, 0xab35f5b5, 0x5fa0fe1f, 0xaaeac02c, 0x5f5e0db3, 0xaa9fbf1e,
+ 0x5f1ae274, 0xaa54f2ba,
+ 0x5ed77c8a, 0xaa0a5b2e, 0x5e93dc1f, 0xa9bff8a8, 0x5e50015d, 0xa975cb57,
+ 0x5e0bec6e, 0xa92bd367,
+ 0x5dc79d7c, 0xa8e21106, 0x5d8314b1, 0xa8988463, 0x5d3e5237, 0xa84f2daa,
+ 0x5cf95638, 0xa8060d08,
+ 0x5cb420e0, 0xa7bd22ac, 0x5c6eb258, 0xa7746ec0, 0x5c290acc, 0xa72bf174,
+ 0x5be32a67, 0xa6e3aaf2,
+ 0x5b9d1154, 0xa69b9b68, 0x5b56bfbd, 0xa653c303, 0x5b1035cf, 0xa60c21ee,
+ 0x5ac973b5, 0xa5c4b855,
+ 0x5a82799a, 0xa57d8666, 0x5a3b47ab, 0xa5368c4b, 0x59f3de12, 0xa4efca31,
+ 0x59ac3cfd, 0xa4a94043,
+ 0x59646498, 0xa462eeac, 0x591c550e, 0xa41cd599, 0x58d40e8c, 0xa3d6f534,
+ 0x588b9140, 0xa3914da8,
+ 0x5842dd54, 0xa34bdf20, 0x57f9f2f8, 0xa306a9c8, 0x57b0d256, 0xa2c1adc9,
+ 0x57677b9d, 0xa27ceb4f,
+ 0x571deefa, 0xa2386284, 0x56d42c99, 0xa1f41392, 0x568a34a9, 0xa1affea3,
+ 0x56400758, 0xa16c23e1,
+ 0x55f5a4d2, 0xa1288376, 0x55ab0d46, 0xa0e51d8c, 0x556040e2, 0xa0a1f24d,
+ 0x55153fd4, 0xa05f01e1,
+ 0x54ca0a4b, 0xa01c4c73, 0x547ea073, 0x9fd9d22a, 0x5433027d, 0x9f979331,
+ 0x53e73097, 0x9f558fb0,
+ 0x539b2af0, 0x9f13c7d0, 0x534ef1b5, 0x9ed23bb9, 0x53028518, 0x9e90eb94,
+ 0x52b5e546, 0x9e4fd78a,
+ 0x5269126e, 0x9e0effc1, 0x521c0cc2, 0x9dce6463, 0x51ced46e, 0x9d8e0597,
+ 0x518169a5, 0x9d4de385,
+ 0x5133cc94, 0x9d0dfe54, 0x50e5fd6d, 0x9cce562c, 0x5097fc5e, 0x9c8eeb34,
+ 0x5049c999, 0x9c4fbd93,
+ 0x4ffb654d, 0x9c10cd70, 0x4faccfab, 0x9bd21af3, 0x4f5e08e3, 0x9b93a641,
+ 0x4f0f1126, 0x9b556f81,
+ 0x4ebfe8a5, 0x9b1776da, 0x4e708f8f, 0x9ad9bc71, 0x4e210617, 0x9a9c406e,
+ 0x4dd14c6e, 0x9a5f02f5,
+ 0x4d8162c4, 0x9a22042d, 0x4d31494b, 0x99e5443b, 0x4ce10034, 0x99a8c345,
+ 0x4c9087b1, 0x996c816f,
+ 0x4c3fdff4, 0x99307ee0, 0x4bef092d, 0x98f4bbbc, 0x4b9e0390, 0x98b93828,
+ 0x4b4ccf4d, 0x987df449,
+ 0x4afb6c98, 0x9842f043, 0x4aa9dba2, 0x98082c3b, 0x4a581c9e, 0x97cda855,
+ 0x4a062fbd, 0x979364b5,
+ 0x49b41533, 0x9759617f, 0x4961cd33, 0x971f9ed7, 0x490f57ee, 0x96e61ce0,
+ 0x48bcb599, 0x96acdbbe,
+ 0x4869e665, 0x9673db94, 0x4816ea86, 0x963b1c86, 0x47c3c22f, 0x96029eb6,
+ 0x47706d93, 0x95ca6247,
+ 0x471cece7, 0x9592675c, 0x46c9405c, 0x955aae17, 0x46756828, 0x9523369c,
+ 0x4621647d, 0x94ec010b,
+ 0x45cd358f, 0x94b50d87, 0x4578db93, 0x947e5c33, 0x452456bd, 0x9447ed2f,
+ 0x44cfa740, 0x9411c09e,
+ 0x447acd50, 0x93dbd6a0, 0x4425c923, 0x93a62f57, 0x43d09aed, 0x9370cae4,
+ 0x437b42e1, 0x933ba968,
+ 0x4325c135, 0x9306cb04, 0x42d0161e, 0x92d22fd9, 0x427a41d0, 0x929dd806,
+ 0x42244481, 0x9269c3ac,
+ 0x41ce1e65, 0x9235f2ec, 0x4177cfb1, 0x920265e4, 0x4121589b, 0x91cf1cb6,
+ 0x40cab958, 0x919c1781,
+ 0x4073f21d, 0x91695663, 0x401d0321, 0x9136d97d, 0x3fc5ec98, 0x9104a0ee,
+ 0x3f6eaeb8, 0x90d2acd4,
+ 0x3f1749b8, 0x90a0fd4e, 0x3ebfbdcd, 0x906f927c, 0x3e680b2c, 0x903e6c7b,
+ 0x3e10320d, 0x900d8b69,
+ 0x3db832a6, 0x8fdcef66, 0x3d600d2c, 0x8fac988f, 0x3d07c1d6, 0x8f7c8701,
+ 0x3caf50da, 0x8f4cbadb,
+ 0x3c56ba70, 0x8f1d343a, 0x3bfdfecd, 0x8eedf33b, 0x3ba51e29, 0x8ebef7fb,
+ 0x3b4c18ba, 0x8e904298,
+ 0x3af2eeb7, 0x8e61d32e, 0x3a99a057, 0x8e33a9da, 0x3a402dd2, 0x8e05c6b7,
+ 0x39e6975e, 0x8dd829e4,
+ 0x398cdd32, 0x8daad37b, 0x3932ff87, 0x8d7dc399, 0x38d8fe93, 0x8d50fa59,
+ 0x387eda8e, 0x8d2477d8,
+ 0x382493b0, 0x8cf83c30, 0x37ca2a30, 0x8ccc477d, 0x376f9e46, 0x8ca099da,
+ 0x3714f02a, 0x8c753362,
+ 0x36ba2014, 0x8c4a142f, 0x365f2e3b, 0x8c1f3c5d, 0x36041ad9, 0x8bf4ac05,
+ 0x35a8e625, 0x8bca6343,
+ 0x354d9057, 0x8ba0622f, 0x34f219a8, 0x8b76a8e4, 0x34968250, 0x8b4d377c,
+ 0x343aca87, 0x8b240e11,
+ 0x33def287, 0x8afb2cbb, 0x3382fa88, 0x8ad29394, 0x3326e2c3, 0x8aaa42b4,
+ 0x32caab6f, 0x8a823a36,
+ 0x326e54c7, 0x8a5a7a31, 0x3211df04, 0x8a3302be, 0x31b54a5e, 0x8a0bd3f5,
+ 0x3158970e, 0x89e4edef,
+ 0x30fbc54d, 0x89be50c3, 0x309ed556, 0x8997fc8a, 0x3041c761, 0x8971f15a,
+ 0x2fe49ba7, 0x894c2f4c,
+ 0x2f875262, 0x8926b677, 0x2f29ebcc, 0x890186f2, 0x2ecc681e, 0x88dca0d3,
+ 0x2e6ec792, 0x88b80432,
+ 0x2e110a62, 0x8893b125, 0x2db330c7, 0x886fa7c2, 0x2d553afc, 0x884be821,
+ 0x2cf72939, 0x88287256,
+ 0x2c98fbba, 0x88054677, 0x2c3ab2b9, 0x87e2649b, 0x2bdc4e6f, 0x87bfccd7,
+ 0x2b7dcf17, 0x879d7f41,
+ 0x2b1f34eb, 0x877b7bec, 0x2ac08026, 0x8759c2ef, 0x2a61b101, 0x8738545e,
+ 0x2a02c7b8, 0x8717304e,
+ 0x29a3c485, 0x86f656d3, 0x2944a7a2, 0x86d5c802, 0x28e5714b, 0x86b583ee,
+ 0x288621b9, 0x86958aac,
+ 0x2826b928, 0x8675dc4f, 0x27c737d3, 0x865678eb, 0x27679df4, 0x86376092,
+ 0x2707ebc7, 0x86189359,
+ 0x26a82186, 0x85fa1153, 0x26483f6c, 0x85dbda91, 0x25e845b6, 0x85bdef28,
+ 0x2588349d, 0x85a04f28,
+ 0x25280c5e, 0x8582faa5, 0x24c7cd33, 0x8565f1b0, 0x24677758, 0x8549345c,
+ 0x24070b08, 0x852cc2bb,
+ 0x23a6887f, 0x85109cdd, 0x2345eff8, 0x84f4c2d4, 0x22e541af, 0x84d934b1,
+ 0x22847de0, 0x84bdf286,
+ 0x2223a4c5, 0x84a2fc62, 0x21c2b69c, 0x84885258, 0x2161b3a0, 0x846df477,
+ 0x21009c0c, 0x8453e2cf,
+ 0x209f701c, 0x843a1d70, 0x203e300d, 0x8420a46c, 0x1fdcdc1b, 0x840777d0,
+ 0x1f7b7481, 0x83ee97ad,
+ 0x1f19f97b, 0x83d60412, 0x1eb86b46, 0x83bdbd0e, 0x1e56ca1e, 0x83a5c2b0,
+ 0x1df5163f, 0x838e1507,
+ 0x1d934fe5, 0x8376b422, 0x1d31774d, 0x835fa00f, 0x1ccf8cb3, 0x8348d8dc,
+ 0x1c6d9053, 0x83325e97,
+ 0x1c0b826a, 0x831c314e, 0x1ba96335, 0x83065110, 0x1b4732ef, 0x82f0bde8,
+ 0x1ae4f1d6, 0x82db77e5,
+ 0x1a82a026, 0x82c67f14, 0x1a203e1b, 0x82b1d381, 0x19bdcbf3, 0x829d753a,
+ 0x195b49ea, 0x8289644b,
+ 0x18f8b83c, 0x8275a0c0, 0x18961728, 0x82622aa6, 0x183366e9, 0x824f0208,
+ 0x17d0a7bc, 0x823c26f3,
+ 0x176dd9de, 0x82299971, 0x170afd8d, 0x82175990, 0x16a81305, 0x82056758,
+ 0x16451a83, 0x81f3c2d7,
+ 0x15e21445, 0x81e26c16, 0x157f0086, 0x81d16321, 0x151bdf86, 0x81c0a801,
+ 0x14b8b17f, 0x81b03ac2,
+ 0x145576b1, 0x81a01b6d, 0x13f22f58, 0x81904a0c, 0x138edbb1, 0x8180c6a9,
+ 0x132b7bf9, 0x8171914e,
+ 0x12c8106f, 0x8162aa04, 0x1264994e, 0x815410d4, 0x120116d5, 0x8145c5c7,
+ 0x119d8941, 0x8137c8e6,
+ 0x1139f0cf, 0x812a1a3a, 0x10d64dbd, 0x811cb9ca, 0x1072a048, 0x810fa7a0,
+ 0x100ee8ad, 0x8102e3c4,
+ 0xfab272b, 0x80f66e3c, 0xf475bff, 0x80ea4712, 0xee38766, 0x80de6e4c,
+ 0xe7fa99e, 0x80d2e3f2,
+ 0xe1bc2e4, 0x80c7a80a, 0xdb7d376, 0x80bcba9d, 0xd53db92, 0x80b21baf,
+ 0xcefdb76, 0x80a7cb49,
+ 0xc8bd35e, 0x809dc971, 0xc27c389, 0x8094162c, 0xbc3ac35, 0x808ab180,
+ 0xb5f8d9f, 0x80819b74,
+ 0xafb6805, 0x8078d40d, 0xa973ba5, 0x80705b50, 0xa3308bd, 0x80683143,
+ 0x9cecf89, 0x806055eb,
+ 0x96a9049, 0x8058c94c, 0x9064b3a, 0x80518b6b, 0x8a2009a, 0x804a9c4d,
+ 0x83db0a7, 0x8043fbf6,
+ 0x7d95b9e, 0x803daa6a, 0x77501be, 0x8037a7ac, 0x710a345, 0x8031f3c2,
+ 0x6ac406f, 0x802c8ead,
+ 0x647d97c, 0x80277872, 0x5e36ea9, 0x8022b114, 0x57f0035, 0x801e3895,
+ 0x51a8e5c, 0x801a0ef8,
+ 0x4b6195d, 0x80163440, 0x451a177, 0x8012a86f, 0x3ed26e6, 0x800f6b88,
+ 0x388a9ea, 0x800c7d8c,
+ 0x3242abf, 0x8009de7e, 0x2bfa9a4, 0x80078e5e, 0x25b26d7, 0x80058d2f,
+ 0x1f6a297, 0x8003daf1,
+ 0x1921d20, 0x800277a6, 0x12d96b1, 0x8001634e, 0xc90f88, 0x80009dea,
+ 0x6487e3, 0x8000277a,
+};
+
+static const q31_t WeightsQ31_2048[4096] = {
+ 0x7fffffff, 0x0, 0x7ffffd88, 0xffe6de05, 0x7ffff621, 0xffcdbc0b, 0x7fffe9cb,
+ 0xffb49a12,
+ 0x7fffd886, 0xff9b781d, 0x7fffc251, 0xff82562c, 0x7fffa72c, 0xff69343f,
+ 0x7fff8719, 0xff501258,
+ 0x7fff6216, 0xff36f078, 0x7fff3824, 0xff1dcea0, 0x7fff0943, 0xff04acd0,
+ 0x7ffed572, 0xfeeb8b0a,
+ 0x7ffe9cb2, 0xfed2694f, 0x7ffe5f03, 0xfeb947a0, 0x7ffe1c65, 0xfea025fd,
+ 0x7ffdd4d7, 0xfe870467,
+ 0x7ffd885a, 0xfe6de2e0, 0x7ffd36ee, 0xfe54c169, 0x7ffce093, 0xfe3ba002,
+ 0x7ffc8549, 0xfe227eac,
+ 0x7ffc250f, 0xfe095d69, 0x7ffbbfe6, 0xfdf03c3a, 0x7ffb55ce, 0xfdd71b1e,
+ 0x7ffae6c7, 0xfdbdfa18,
+ 0x7ffa72d1, 0xfda4d929, 0x7ff9f9ec, 0xfd8bb850, 0x7ff97c18, 0xfd729790,
+ 0x7ff8f954, 0xfd5976e9,
+ 0x7ff871a2, 0xfd40565c, 0x7ff7e500, 0xfd2735ea, 0x7ff75370, 0xfd0e1594,
+ 0x7ff6bcf0, 0xfcf4f55c,
+ 0x7ff62182, 0xfcdbd541, 0x7ff58125, 0xfcc2b545, 0x7ff4dbd9, 0xfca9956a,
+ 0x7ff4319d, 0xfc9075af,
+ 0x7ff38274, 0xfc775616, 0x7ff2ce5b, 0xfc5e36a0, 0x7ff21553, 0xfc45174e,
+ 0x7ff1575d, 0xfc2bf821,
+ 0x7ff09478, 0xfc12d91a, 0x7fefcca4, 0xfbf9ba39, 0x7feeffe1, 0xfbe09b80,
+ 0x7fee2e30, 0xfbc77cf0,
+ 0x7fed5791, 0xfbae5e89, 0x7fec7c02, 0xfb95404d, 0x7feb9b85, 0xfb7c223d,
+ 0x7feab61a, 0xfb630459,
+ 0x7fe9cbc0, 0xfb49e6a3, 0x7fe8dc78, 0xfb30c91b, 0x7fe7e841, 0xfb17abc2,
+ 0x7fe6ef1c, 0xfafe8e9b,
+ 0x7fe5f108, 0xfae571a4, 0x7fe4ee06, 0xfacc54e0, 0x7fe3e616, 0xfab3384f,
+ 0x7fe2d938, 0xfa9a1bf3,
+ 0x7fe1c76b, 0xfa80ffcb, 0x7fe0b0b1, 0xfa67e3da, 0x7fdf9508, 0xfa4ec821,
+ 0x7fde7471, 0xfa35ac9f,
+ 0x7fdd4eec, 0xfa1c9157, 0x7fdc247a, 0xfa037648, 0x7fdaf519, 0xf9ea5b75,
+ 0x7fd9c0ca, 0xf9d140de,
+ 0x7fd8878e, 0xf9b82684, 0x7fd74964, 0xf99f0c68, 0x7fd6064c, 0xf985f28a,
+ 0x7fd4be46, 0xf96cd8ed,
+ 0x7fd37153, 0xf953bf91, 0x7fd21f72, 0xf93aa676, 0x7fd0c8a3, 0xf9218d9e,
+ 0x7fcf6ce8, 0xf908750a,
+ 0x7fce0c3e, 0xf8ef5cbb, 0x7fcca6a7, 0xf8d644b2, 0x7fcb3c23, 0xf8bd2cef,
+ 0x7fc9ccb2, 0xf8a41574,
+ 0x7fc85854, 0xf88afe42, 0x7fc6df08, 0xf871e759, 0x7fc560cf, 0xf858d0bb,
+ 0x7fc3dda9, 0xf83fba68,
+ 0x7fc25596, 0xf826a462, 0x7fc0c896, 0xf80d8ea9, 0x7fbf36aa, 0xf7f4793e,
+ 0x7fbd9fd0, 0xf7db6423,
+ 0x7fbc040a, 0xf7c24f59, 0x7fba6357, 0xf7a93ae0, 0x7fb8bdb8, 0xf79026b9,
+ 0x7fb7132b, 0xf77712e5,
+ 0x7fb563b3, 0xf75dff66, 0x7fb3af4e, 0xf744ec3b, 0x7fb1f5fc, 0xf72bd967,
+ 0x7fb037bf, 0xf712c6ea,
+ 0x7fae7495, 0xf6f9b4c6, 0x7facac7f, 0xf6e0a2fa, 0x7faadf7c, 0xf6c79188,
+ 0x7fa90d8e, 0xf6ae8071,
+ 0x7fa736b4, 0xf6956fb7, 0x7fa55aee, 0xf67c5f59, 0x7fa37a3c, 0xf6634f59,
+ 0x7fa1949e, 0xf64a3fb8,
+ 0x7f9faa15, 0xf6313077, 0x7f9dbaa0, 0xf6182196, 0x7f9bc640, 0xf5ff1318,
+ 0x7f99ccf4, 0xf5e604fc,
+ 0x7f97cebd, 0xf5ccf743, 0x7f95cb9a, 0xf5b3e9f0, 0x7f93c38c, 0xf59add02,
+ 0x7f91b694, 0xf581d07b,
+ 0x7f8fa4b0, 0xf568c45b, 0x7f8d8de1, 0xf54fb8a4, 0x7f8b7227, 0xf536ad56,
+ 0x7f895182, 0xf51da273,
+ 0x7f872bf3, 0xf50497fb, 0x7f850179, 0xf4eb8def, 0x7f82d214, 0xf4d28451,
+ 0x7f809dc5, 0xf4b97b21,
+ 0x7f7e648c, 0xf4a07261, 0x7f7c2668, 0xf4876a10, 0x7f79e35a, 0xf46e6231,
+ 0x7f779b62, 0xf4555ac5,
+ 0x7f754e80, 0xf43c53cb, 0x7f72fcb4, 0xf4234d45, 0x7f70a5fe, 0xf40a4735,
+ 0x7f6e4a5e, 0xf3f1419a,
+ 0x7f6be9d4, 0xf3d83c77, 0x7f698461, 0xf3bf37cb, 0x7f671a05, 0xf3a63398,
+ 0x7f64aabf, 0xf38d2fe0,
+ 0x7f62368f, 0xf3742ca2, 0x7f5fbd77, 0xf35b29e0, 0x7f5d3f75, 0xf342279b,
+ 0x7f5abc8a, 0xf32925d3,
+ 0x7f5834b7, 0xf310248a, 0x7f55a7fa, 0xf2f723c1, 0x7f531655, 0xf2de2379,
+ 0x7f507fc7, 0xf2c523b2,
+ 0x7f4de451, 0xf2ac246e, 0x7f4b43f2, 0xf29325ad, 0x7f489eaa, 0xf27a2771,
+ 0x7f45f47b, 0xf26129ba,
+ 0x7f434563, 0xf2482c8a, 0x7f409164, 0xf22f2fe1, 0x7f3dd87c, 0xf21633c0,
+ 0x7f3b1aad, 0xf1fd3829,
+ 0x7f3857f6, 0xf1e43d1c, 0x7f359057, 0xf1cb429a, 0x7f32c3d1, 0xf1b248a5,
+ 0x7f2ff263, 0xf1994f3d,
+ 0x7f2d1c0e, 0xf1805662, 0x7f2a40d2, 0xf1675e17, 0x7f2760af, 0xf14e665c,
+ 0x7f247ba5, 0xf1356f32,
+ 0x7f2191b4, 0xf11c789a, 0x7f1ea2dc, 0xf1038295, 0x7f1baf1e, 0xf0ea8d24,
+ 0x7f18b679, 0xf0d19848,
+ 0x7f15b8ee, 0xf0b8a401, 0x7f12b67c, 0xf09fb051, 0x7f0faf25, 0xf086bd39,
+ 0x7f0ca2e7, 0xf06dcaba,
+ 0x7f0991c4, 0xf054d8d5, 0x7f067bba, 0xf03be78a, 0x7f0360cb, 0xf022f6da,
+ 0x7f0040f6, 0xf00a06c8,
+ 0x7efd1c3c, 0xeff11753, 0x7ef9f29d, 0xefd8287c, 0x7ef6c418, 0xefbf3a45,
+ 0x7ef390ae, 0xefa64cae,
+ 0x7ef05860, 0xef8d5fb8, 0x7eed1b2c, 0xef747365, 0x7ee9d914, 0xef5b87b5,
+ 0x7ee69217, 0xef429caa,
+ 0x7ee34636, 0xef29b243, 0x7edff570, 0xef10c883, 0x7edc9fc6, 0xeef7df6a,
+ 0x7ed94538, 0xeedef6f9,
+ 0x7ed5e5c6, 0xeec60f31, 0x7ed28171, 0xeead2813, 0x7ecf1837, 0xee9441a0,
+ 0x7ecbaa1a, 0xee7b5bd9,
+ 0x7ec8371a, 0xee6276bf, 0x7ec4bf36, 0xee499253, 0x7ec14270, 0xee30ae96,
+ 0x7ebdc0c6, 0xee17cb88,
+ 0x7eba3a39, 0xedfee92b, 0x7eb6aeca, 0xede60780, 0x7eb31e78, 0xedcd2687,
+ 0x7eaf8943, 0xedb44642,
+ 0x7eabef2c, 0xed9b66b2, 0x7ea85033, 0xed8287d7, 0x7ea4ac58, 0xed69a9b3,
+ 0x7ea1039b, 0xed50cc46,
+ 0x7e9d55fc, 0xed37ef91, 0x7e99a37c, 0xed1f1396, 0x7e95ec1a, 0xed063856,
+ 0x7e922fd6, 0xeced5dd0,
+ 0x7e8e6eb2, 0xecd48407, 0x7e8aa8ac, 0xecbbaafb, 0x7e86ddc6, 0xeca2d2ad,
+ 0x7e830dff, 0xec89fb1e,
+ 0x7e7f3957, 0xec71244f, 0x7e7b5fce, 0xec584e41, 0x7e778166, 0xec3f78f6,
+ 0x7e739e1d, 0xec26a46d,
+ 0x7e6fb5f4, 0xec0dd0a8, 0x7e6bc8eb, 0xebf4fda8, 0x7e67d703, 0xebdc2b6e,
+ 0x7e63e03b, 0xebc359fb,
+ 0x7e5fe493, 0xebaa894f, 0x7e5be40c, 0xeb91b96c, 0x7e57dea7, 0xeb78ea52,
+ 0x7e53d462, 0xeb601c04,
+ 0x7e4fc53e, 0xeb474e81, 0x7e4bb13c, 0xeb2e81ca, 0x7e47985b, 0xeb15b5e1,
+ 0x7e437a9c, 0xeafceac6,
+ 0x7e3f57ff, 0xeae4207a, 0x7e3b3083, 0xeacb56ff, 0x7e37042a, 0xeab28e56,
+ 0x7e32d2f4, 0xea99c67e,
+ 0x7e2e9cdf, 0xea80ff7a, 0x7e2a61ed, 0xea683949, 0x7e26221f, 0xea4f73ee,
+ 0x7e21dd73, 0xea36af69,
+ 0x7e1d93ea, 0xea1debbb, 0x7e194584, 0xea0528e5, 0x7e14f242, 0xe9ec66e8,
+ 0x7e109a24, 0xe9d3a5c5,
+ 0x7e0c3d29, 0xe9bae57d, 0x7e07db52, 0xe9a22610, 0x7e0374a0, 0xe9896781,
+ 0x7dff0911, 0xe970a9ce,
+ 0x7dfa98a8, 0xe957ecfb, 0x7df62362, 0xe93f3107, 0x7df1a942, 0xe92675f4,
+ 0x7ded2a47, 0xe90dbbc2,
+ 0x7de8a670, 0xe8f50273, 0x7de41dc0, 0xe8dc4a07, 0x7ddf9034, 0xe8c39280,
+ 0x7ddafdce, 0xe8aadbde,
+ 0x7dd6668f, 0xe8922622, 0x7dd1ca75, 0xe879714d, 0x7dcd2981, 0xe860bd61,
+ 0x7dc883b4, 0xe8480a5d,
+ 0x7dc3d90d, 0xe82f5844, 0x7dbf298d, 0xe816a716, 0x7dba7534, 0xe7fdf6d4,
+ 0x7db5bc02, 0xe7e5477f,
+ 0x7db0fdf8, 0xe7cc9917, 0x7dac3b15, 0xe7b3eb9f, 0x7da77359, 0xe79b3f16,
+ 0x7da2a6c6, 0xe782937e,
+ 0x7d9dd55a, 0xe769e8d8, 0x7d98ff17, 0xe7513f25, 0x7d9423fc, 0xe7389665,
+ 0x7d8f4409, 0xe71fee99,
+ 0x7d8a5f40, 0xe70747c4, 0x7d85759f, 0xe6eea1e4, 0x7d808728, 0xe6d5fcfc,
+ 0x7d7b93da, 0xe6bd590d,
+ 0x7d769bb5, 0xe6a4b616, 0x7d719eba, 0xe68c141a, 0x7d6c9ce9, 0xe6737319,
+ 0x7d679642, 0xe65ad315,
+ 0x7d628ac6, 0xe642340d, 0x7d5d7a74, 0xe6299604, 0x7d58654d, 0xe610f8f9,
+ 0x7d534b50, 0xe5f85cef,
+ 0x7d4e2c7f, 0xe5dfc1e5, 0x7d4908d9, 0xe5c727dd, 0x7d43e05e, 0xe5ae8ed8,
+ 0x7d3eb30f, 0xe595f6d7,
+ 0x7d3980ec, 0xe57d5fda, 0x7d3449f5, 0xe564c9e3, 0x7d2f0e2b, 0xe54c34f3,
+ 0x7d29cd8c, 0xe533a10a,
+ 0x7d24881b, 0xe51b0e2a, 0x7d1f3dd6, 0xe5027c53, 0x7d19eebf, 0xe4e9eb87,
+ 0x7d149ad5, 0xe4d15bc6,
+ 0x7d0f4218, 0xe4b8cd11, 0x7d09e489, 0xe4a03f69, 0x7d048228, 0xe487b2d0,
+ 0x7cff1af5, 0xe46f2745,
+ 0x7cf9aef0, 0xe4569ccb, 0x7cf43e1a, 0xe43e1362, 0x7ceec873, 0xe4258b0a,
+ 0x7ce94dfb, 0xe40d03c6,
+ 0x7ce3ceb2, 0xe3f47d96, 0x7cde4a98, 0xe3dbf87a, 0x7cd8c1ae, 0xe3c37474,
+ 0x7cd333f3, 0xe3aaf184,
+ 0x7ccda169, 0xe3926fad, 0x7cc80a0f, 0xe379eeed, 0x7cc26de5, 0xe3616f48,
+ 0x7cbcccec, 0xe348f0bd,
+ 0x7cb72724, 0xe330734d, 0x7cb17c8d, 0xe317f6fa, 0x7cabcd28, 0xe2ff7bc3,
+ 0x7ca618f3, 0xe2e701ac,
+ 0x7ca05ff1, 0xe2ce88b3, 0x7c9aa221, 0xe2b610da, 0x7c94df83, 0xe29d9a23,
+ 0x7c8f1817, 0xe285248d,
+ 0x7c894bde, 0xe26cb01b, 0x7c837ad8, 0xe2543ccc, 0x7c7da505, 0xe23bcaa2,
+ 0x7c77ca65, 0xe223599e,
+ 0x7c71eaf9, 0xe20ae9c1, 0x7c6c06c0, 0xe1f27b0b, 0x7c661dbc, 0xe1da0d7e,
+ 0x7c602fec, 0xe1c1a11b,
+ 0x7c5a3d50, 0xe1a935e2, 0x7c5445e9, 0xe190cbd4, 0x7c4e49b7, 0xe17862f3,
+ 0x7c4848ba, 0xe15ffb3f,
+ 0x7c4242f2, 0xe14794ba, 0x7c3c3860, 0xe12f2f63, 0x7c362904, 0xe116cb3d,
+ 0x7c3014de, 0xe0fe6848,
+ 0x7c29fbee, 0xe0e60685, 0x7c23de35, 0xe0cda5f5, 0x7c1dbbb3, 0xe0b54698,
+ 0x7c179467, 0xe09ce871,
+ 0x7c116853, 0xe0848b7f, 0x7c0b3777, 0xe06c2fc4, 0x7c0501d2, 0xe053d541,
+ 0x7bfec765, 0xe03b7bf6,
+ 0x7bf88830, 0xe02323e5, 0x7bf24434, 0xe00acd0e, 0x7bebfb70, 0xdff27773,
+ 0x7be5ade6, 0xdfda2314,
+ 0x7bdf5b94, 0xdfc1cff3, 0x7bd9047c, 0xdfa97e0f, 0x7bd2a89e, 0xdf912d6b,
+ 0x7bcc47fa, 0xdf78de07,
+ 0x7bc5e290, 0xdf608fe4, 0x7bbf7860, 0xdf484302, 0x7bb9096b, 0xdf2ff764,
+ 0x7bb295b0, 0xdf17ad0a,
+ 0x7bac1d31, 0xdeff63f4, 0x7ba59fee, 0xdee71c24, 0x7b9f1de6, 0xdeced59b,
+ 0x7b989719, 0xdeb69059,
+ 0x7b920b89, 0xde9e4c60, 0x7b8b7b36, 0xde8609b1, 0x7b84e61f, 0xde6dc84b,
+ 0x7b7e4c45, 0xde558831,
+ 0x7b77ada8, 0xde3d4964, 0x7b710a49, 0xde250be3, 0x7b6a6227, 0xde0ccfb1,
+ 0x7b63b543, 0xddf494ce,
+ 0x7b5d039e, 0xdddc5b3b, 0x7b564d36, 0xddc422f8, 0x7b4f920e, 0xddabec08,
+ 0x7b48d225, 0xdd93b66a,
+ 0x7b420d7a, 0xdd7b8220, 0x7b3b4410, 0xdd634f2b, 0x7b3475e5, 0xdd4b1d8c,
+ 0x7b2da2fa, 0xdd32ed43,
+ 0x7b26cb4f, 0xdd1abe51, 0x7b1feee5, 0xdd0290b8, 0x7b190dbc, 0xdcea6478,
+ 0x7b1227d3, 0xdcd23993,
+ 0x7b0b3d2c, 0xdcba1008, 0x7b044dc7, 0xdca1e7da, 0x7afd59a4, 0xdc89c109,
+ 0x7af660c2, 0xdc719b96,
+ 0x7aef6323, 0xdc597781, 0x7ae860c7, 0xdc4154cd, 0x7ae159ae, 0xdc293379,
+ 0x7ada4dd8, 0xdc111388,
+ 0x7ad33d45, 0xdbf8f4f8, 0x7acc27f7, 0xdbe0d7cd, 0x7ac50dec, 0xdbc8bc06,
+ 0x7abdef25, 0xdbb0a1a4,
+ 0x7ab6cba4, 0xdb9888a8, 0x7aafa367, 0xdb807114, 0x7aa8766f, 0xdb685ae9,
+ 0x7aa144bc, 0xdb504626,
+ 0x7a9a0e50, 0xdb3832cd, 0x7a92d329, 0xdb2020e0, 0x7a8b9348, 0xdb08105e,
+ 0x7a844eae, 0xdaf00149,
+ 0x7a7d055b, 0xdad7f3a2, 0x7a75b74f, 0xdabfe76a, 0x7a6e648a, 0xdaa7dca1,
+ 0x7a670d0d, 0xda8fd349,
+ 0x7a5fb0d8, 0xda77cb63, 0x7a584feb, 0xda5fc4ef, 0x7a50ea47, 0xda47bfee,
+ 0x7a497feb, 0xda2fbc61,
+ 0x7a4210d8, 0xda17ba4a, 0x7a3a9d0f, 0xd9ffb9a9, 0x7a332490, 0xd9e7ba7f,
+ 0x7a2ba75a, 0xd9cfbccd,
+ 0x7a24256f, 0xd9b7c094, 0x7a1c9ece, 0xd99fc5d4, 0x7a151378, 0xd987cc90,
+ 0x7a0d836d, 0xd96fd4c7,
+ 0x7a05eead, 0xd957de7a, 0x79fe5539, 0xd93fe9ab, 0x79f6b711, 0xd927f65b,
+ 0x79ef1436, 0xd910048a,
+ 0x79e76ca7, 0xd8f81439, 0x79dfc064, 0xd8e0256a, 0x79d80f6f, 0xd8c8381d,
+ 0x79d059c8, 0xd8b04c52,
+ 0x79c89f6e, 0xd898620c, 0x79c0e062, 0xd880794b, 0x79b91ca4, 0xd868920f,
+ 0x79b15435, 0xd850ac5a,
+ 0x79a98715, 0xd838c82d, 0x79a1b545, 0xd820e589, 0x7999dec4, 0xd809046e,
+ 0x79920392, 0xd7f124dd,
+ 0x798a23b1, 0xd7d946d8, 0x79823f20, 0xd7c16a5f, 0x797a55e0, 0xd7a98f73,
+ 0x797267f2, 0xd791b616,
+ 0x796a7554, 0xd779de47, 0x79627e08, 0xd7620808, 0x795a820e, 0xd74a335b,
+ 0x79528167, 0xd732603f,
+ 0x794a7c12, 0xd71a8eb5, 0x79427210, 0xd702bec0, 0x793a6361, 0xd6eaf05f,
+ 0x79325006, 0xd6d32393,
+ 0x792a37fe, 0xd6bb585e, 0x79221b4b, 0xd6a38ec0, 0x7919f9ec, 0xd68bc6ba,
+ 0x7911d3e2, 0xd674004e,
+ 0x7909a92d, 0xd65c3b7b, 0x790179cd, 0xd6447844, 0x78f945c3, 0xd62cb6a8,
+ 0x78f10d0f, 0xd614f6a9,
+ 0x78e8cfb2, 0xd5fd3848, 0x78e08dab, 0xd5e57b85, 0x78d846fb, 0xd5cdc062,
+ 0x78cffba3, 0xd5b606e0,
+ 0x78c7aba2, 0xd59e4eff, 0x78bf56f9, 0xd58698c0, 0x78b6fda8, 0xd56ee424,
+ 0x78ae9fb0, 0xd557312d,
+ 0x78a63d11, 0xd53f7fda, 0x789dd5cb, 0xd527d02e, 0x789569df, 0xd5102228,
+ 0x788cf94c, 0xd4f875ca,
+ 0x78848414, 0xd4e0cb15, 0x787c0a36, 0xd4c92209, 0x78738bb3, 0xd4b17aa8,
+ 0x786b088c, 0xd499d4f2,
+ 0x786280bf, 0xd48230e9, 0x7859f44f, 0xd46a8e8d, 0x7851633b, 0xd452eddf,
+ 0x7848cd83, 0xd43b4ee0,
+ 0x78403329, 0xd423b191, 0x7837942b, 0xd40c15f3, 0x782ef08b, 0xd3f47c06,
+ 0x78264849, 0xd3dce3cd,
+ 0x781d9b65, 0xd3c54d47, 0x7814e9df, 0xd3adb876, 0x780c33b8, 0xd396255a,
+ 0x780378f1, 0xd37e93f4,
+ 0x77fab989, 0xd3670446, 0x77f1f581, 0xd34f764f, 0x77e92cd9, 0xd337ea12,
+ 0x77e05f91, 0xd3205f8f,
+ 0x77d78daa, 0xd308d6c7, 0x77ceb725, 0xd2f14fba, 0x77c5dc01, 0xd2d9ca6a,
+ 0x77bcfc3f, 0xd2c246d8,
+ 0x77b417df, 0xd2aac504, 0x77ab2ee2, 0xd29344f0, 0x77a24148, 0xd27bc69c,
+ 0x77994f11, 0xd2644a0a,
+ 0x7790583e, 0xd24ccf39, 0x77875cce, 0xd235562b, 0x777e5cc3, 0xd21ddee2,
+ 0x7775581d, 0xd206695d,
+ 0x776c4edb, 0xd1eef59e, 0x776340ff, 0xd1d783a6, 0x775a2e89, 0xd1c01375,
+ 0x77511778, 0xd1a8a50d,
+ 0x7747fbce, 0xd191386e, 0x773edb8b, 0xd179cd99, 0x7735b6af, 0xd1626490,
+ 0x772c8d3a, 0xd14afd52,
+ 0x77235f2d, 0xd13397e2, 0x771a2c88, 0xd11c343f, 0x7710f54c, 0xd104d26b,
+ 0x7707b979, 0xd0ed7267,
+ 0x76fe790e, 0xd0d61434, 0x76f5340e, 0xd0beb7d2, 0x76ebea77, 0xd0a75d42,
+ 0x76e29c4b, 0xd0900486,
+ 0x76d94989, 0xd078ad9e, 0x76cff232, 0xd061588b, 0x76c69647, 0xd04a054e,
+ 0x76bd35c7, 0xd032b3e7,
+ 0x76b3d0b4, 0xd01b6459, 0x76aa670d, 0xd00416a3, 0x76a0f8d2, 0xcfeccac7,
+ 0x76978605, 0xcfd580c6,
+ 0x768e0ea6, 0xcfbe389f, 0x768492b4, 0xcfa6f255, 0x767b1231, 0xcf8fade9,
+ 0x76718d1c, 0xcf786b5a,
+ 0x76680376, 0xcf612aaa, 0x765e7540, 0xcf49ebda, 0x7654e279, 0xcf32aeeb,
+ 0x764b4b23, 0xcf1b73de,
+ 0x7641af3d, 0xcf043ab3, 0x76380ec8, 0xceed036b, 0x762e69c4, 0xced5ce08,
+ 0x7624c031, 0xcebe9a8a,
+ 0x761b1211, 0xcea768f2, 0x76115f63, 0xce903942, 0x7607a828, 0xce790b79,
+ 0x75fdec60, 0xce61df99,
+ 0x75f42c0b, 0xce4ab5a2, 0x75ea672a, 0xce338d97, 0x75e09dbd, 0xce1c6777,
+ 0x75d6cfc5, 0xce054343,
+ 0x75ccfd42, 0xcdee20fc, 0x75c32634, 0xcdd700a4, 0x75b94a9c, 0xcdbfe23a,
+ 0x75af6a7b, 0xcda8c5c1,
+ 0x75a585cf, 0xcd91ab39, 0x759b9c9b, 0xcd7a92a2, 0x7591aedd, 0xcd637bfe,
+ 0x7587bc98, 0xcd4c674d,
+ 0x757dc5ca, 0xcd355491, 0x7573ca75, 0xcd1e43ca, 0x7569ca99, 0xcd0734f9,
+ 0x755fc635, 0xccf0281f,
+ 0x7555bd4c, 0xccd91d3d, 0x754bafdc, 0xccc21455, 0x75419de7, 0xccab0d65,
+ 0x7537876c, 0xcc940871,
+ 0x752d6c6c, 0xcc7d0578, 0x75234ce8, 0xcc66047b, 0x751928e0, 0xcc4f057c,
+ 0x750f0054, 0xcc38087b,
+ 0x7504d345, 0xcc210d79, 0x74faa1b3, 0xcc0a1477, 0x74f06b9e, 0xcbf31d75,
+ 0x74e63108, 0xcbdc2876,
+ 0x74dbf1ef, 0xcbc53579, 0x74d1ae55, 0xcbae447f, 0x74c7663a, 0xcb97558a,
+ 0x74bd199f, 0xcb80689a,
+ 0x74b2c884, 0xcb697db0, 0x74a872e8, 0xcb5294ce, 0x749e18cd, 0xcb3badf3,
+ 0x7493ba34, 0xcb24c921,
+ 0x7489571c, 0xcb0de658, 0x747eef85, 0xcaf7059a, 0x74748371, 0xcae026e8,
+ 0x746a12df, 0xcac94a42,
+ 0x745f9dd1, 0xcab26fa9, 0x74552446, 0xca9b971e, 0x744aa63f, 0xca84c0a3,
+ 0x744023bc, 0xca6dec37,
+ 0x74359cbd, 0xca5719db, 0x742b1144, 0xca404992, 0x74208150, 0xca297b5a,
+ 0x7415ece2, 0xca12af37,
+ 0x740b53fb, 0xc9fbe527, 0x7400b69a, 0xc9e51d2d, 0x73f614c0, 0xc9ce5748,
+ 0x73eb6e6e, 0xc9b7937a,
+ 0x73e0c3a3, 0xc9a0d1c5, 0x73d61461, 0xc98a1227, 0x73cb60a8, 0xc97354a4,
+ 0x73c0a878, 0xc95c993a,
+ 0x73b5ebd1, 0xc945dfec, 0x73ab2ab4, 0xc92f28ba, 0x73a06522, 0xc91873a5,
+ 0x73959b1b, 0xc901c0ae,
+ 0x738acc9e, 0xc8eb0fd6, 0x737ff9ae, 0xc8d4611d, 0x73752249, 0xc8bdb485,
+ 0x736a4671, 0xc8a70a0e,
+ 0x735f6626, 0xc89061ba, 0x73548168, 0xc879bb89, 0x73499838, 0xc863177b,
+ 0x733eaa96, 0xc84c7593,
+ 0x7333b883, 0xc835d5d0, 0x7328c1ff, 0xc81f3834, 0x731dc70a, 0xc8089cbf,
+ 0x7312c7a5, 0xc7f20373,
+ 0x7307c3d0, 0xc7db6c50, 0x72fcbb8c, 0xc7c4d757, 0x72f1aed9, 0xc7ae4489,
+ 0x72e69db7, 0xc797b3e7,
+ 0x72db8828, 0xc7812572, 0x72d06e2b, 0xc76a992a, 0x72c54fc1, 0xc7540f11,
+ 0x72ba2cea, 0xc73d8727,
+ 0x72af05a7, 0xc727016d, 0x72a3d9f7, 0xc7107de4, 0x7298a9dd, 0xc6f9fc8d,
+ 0x728d7557, 0xc6e37d69,
+ 0x72823c67, 0xc6cd0079, 0x7276ff0d, 0xc6b685bd, 0x726bbd48, 0xc6a00d37,
+ 0x7260771b, 0xc68996e7,
+ 0x72552c85, 0xc67322ce, 0x7249dd86, 0xc65cb0ed, 0x723e8a20, 0xc6464144,
+ 0x72333251, 0xc62fd3d6,
+ 0x7227d61c, 0xc61968a2, 0x721c7580, 0xc602ffaa, 0x7211107e, 0xc5ec98ee,
+ 0x7205a716, 0xc5d6346f,
+ 0x71fa3949, 0xc5bfd22e, 0x71eec716, 0xc5a9722c, 0x71e35080, 0xc593146a,
+ 0x71d7d585, 0xc57cb8e9,
+ 0x71cc5626, 0xc5665fa9, 0x71c0d265, 0xc55008ab, 0x71b54a41, 0xc539b3f1,
+ 0x71a9bdba, 0xc523617a,
+ 0x719e2cd2, 0xc50d1149, 0x71929789, 0xc4f6c35d, 0x7186fdde, 0xc4e077b8,
+ 0x717b5fd3, 0xc4ca2e5b,
+ 0x716fbd68, 0xc4b3e746, 0x7164169d, 0xc49da27a, 0x71586b74, 0xc4875ff9,
+ 0x714cbbeb, 0xc4711fc2,
+ 0x71410805, 0xc45ae1d7, 0x71354fc0, 0xc444a639, 0x7129931f, 0xc42e6ce8,
+ 0x711dd220, 0xc41835e6,
+ 0x71120cc5, 0xc4020133, 0x7106430e, 0xc3ebced0, 0x70fa74fc, 0xc3d59ebe,
+ 0x70eea28e, 0xc3bf70fd,
+ 0x70e2cbc6, 0xc3a94590, 0x70d6f0a4, 0xc3931c76, 0x70cb1128, 0xc37cf5b0,
+ 0x70bf2d53, 0xc366d140,
+ 0x70b34525, 0xc350af26, 0x70a7589f, 0xc33a8f62, 0x709b67c0, 0xc32471f7,
+ 0x708f728b, 0xc30e56e4,
+ 0x708378ff, 0xc2f83e2a, 0x70777b1c, 0xc2e227cb, 0x706b78e3, 0xc2cc13c7,
+ 0x705f7255, 0xc2b6021f,
+ 0x70536771, 0xc29ff2d4, 0x70475839, 0xc289e5e7, 0x703b44ad, 0xc273db58,
+ 0x702f2ccd, 0xc25dd329,
+ 0x7023109a, 0xc247cd5a, 0x7016f014, 0xc231c9ec, 0x700acb3c, 0xc21bc8e1,
+ 0x6ffea212, 0xc205ca38,
+ 0x6ff27497, 0xc1efcdf3, 0x6fe642ca, 0xc1d9d412, 0x6fda0cae, 0xc1c3dc97,
+ 0x6fcdd241, 0xc1ade781,
+ 0x6fc19385, 0xc197f4d4, 0x6fb5507a, 0xc182048d, 0x6fa90921, 0xc16c16b0,
+ 0x6f9cbd79, 0xc1562b3d,
+ 0x6f906d84, 0xc1404233, 0x6f841942, 0xc12a5b95, 0x6f77c0b3, 0xc1147764,
+ 0x6f6b63d8, 0xc0fe959f,
+ 0x6f5f02b2, 0xc0e8b648, 0x6f529d40, 0xc0d2d960, 0x6f463383, 0xc0bcfee7,
+ 0x6f39c57d, 0xc0a726df,
+ 0x6f2d532c, 0xc0915148, 0x6f20dc92, 0xc07b7e23, 0x6f1461b0, 0xc065ad70,
+ 0x6f07e285, 0xc04fdf32,
+ 0x6efb5f12, 0xc03a1368, 0x6eeed758, 0xc0244a14, 0x6ee24b57, 0xc00e8336,
+ 0x6ed5bb10, 0xbff8bece,
+ 0x6ec92683, 0xbfe2fcdf, 0x6ebc8db0, 0xbfcd3d69, 0x6eaff099, 0xbfb7806c,
+ 0x6ea34f3d, 0xbfa1c5ea,
+ 0x6e96a99d, 0xbf8c0de3, 0x6e89ffb9, 0xbf765858, 0x6e7d5193, 0xbf60a54a,
+ 0x6e709f2a, 0xbf4af4ba,
+ 0x6e63e87f, 0xbf3546a8, 0x6e572d93, 0xbf1f9b16, 0x6e4a6e66, 0xbf09f205,
+ 0x6e3daaf8, 0xbef44b74,
+ 0x6e30e34a, 0xbedea765, 0x6e24175c, 0xbec905d9, 0x6e174730, 0xbeb366d1,
+ 0x6e0a72c5, 0xbe9dca4e,
+ 0x6dfd9a1c, 0xbe88304f, 0x6df0bd35, 0xbe7298d7, 0x6de3dc11, 0xbe5d03e6,
+ 0x6dd6f6b1, 0xbe47717c,
+ 0x6dca0d14, 0xbe31e19b, 0x6dbd1f3c, 0xbe1c5444, 0x6db02d29, 0xbe06c977,
+ 0x6da336dc, 0xbdf14135,
+ 0x6d963c54, 0xbddbbb7f, 0x6d893d93, 0xbdc63856, 0x6d7c3a98, 0xbdb0b7bb,
+ 0x6d6f3365, 0xbd9b39ad,
+ 0x6d6227fa, 0xbd85be30, 0x6d551858, 0xbd704542, 0x6d48047e, 0xbd5acee5,
+ 0x6d3aec6e, 0xbd455b1a,
+ 0x6d2dd027, 0xbd2fe9e2, 0x6d20afac, 0xbd1a7b3d, 0x6d138afb, 0xbd050f2c,
+ 0x6d066215, 0xbcefa5b0,
+ 0x6cf934fc, 0xbcda3ecb, 0x6cec03af, 0xbcc4da7b, 0x6cdece2f, 0xbcaf78c4,
+ 0x6cd1947c, 0xbc9a19a5,
+ 0x6cc45698, 0xbc84bd1f, 0x6cb71482, 0xbc6f6333, 0x6ca9ce3b, 0xbc5a0be2,
+ 0x6c9c83c3, 0xbc44b72c,
+ 0x6c8f351c, 0xbc2f6513, 0x6c81e245, 0xbc1a1598, 0x6c748b3f, 0xbc04c8ba,
+ 0x6c67300b, 0xbbef7e7c,
+ 0x6c59d0a9, 0xbbda36dd, 0x6c4c6d1a, 0xbbc4f1df, 0x6c3f055d, 0xbbafaf82,
+ 0x6c319975, 0xbb9a6fc7,
+ 0x6c242960, 0xbb8532b0, 0x6c16b521, 0xbb6ff83c, 0x6c093cb6, 0xbb5ac06d,
+ 0x6bfbc021, 0xbb458b43,
+ 0x6bee3f62, 0xbb3058c0, 0x6be0ba7b, 0xbb1b28e4, 0x6bd3316a, 0xbb05fbb0,
+ 0x6bc5a431, 0xbaf0d125,
+ 0x6bb812d1, 0xbadba943, 0x6baa7d49, 0xbac6840c, 0x6b9ce39b, 0xbab16180,
+ 0x6b8f45c7, 0xba9c41a0,
+ 0x6b81a3cd, 0xba87246d, 0x6b73fdae, 0xba7209e7, 0x6b66536b, 0xba5cf210,
+ 0x6b58a503, 0xba47dce8,
+ 0x6b4af279, 0xba32ca71, 0x6b3d3bcb, 0xba1dbaaa, 0x6b2f80fb, 0xba08ad95,
+ 0x6b21c208, 0xb9f3a332,
+ 0x6b13fef5, 0xb9de9b83, 0x6b0637c1, 0xb9c99688, 0x6af86c6c, 0xb9b49442,
+ 0x6aea9cf8, 0xb99f94b2,
+ 0x6adcc964, 0xb98a97d8, 0x6acef1b2, 0xb9759db6, 0x6ac115e2, 0xb960a64c,
+ 0x6ab335f4, 0xb94bb19b,
+ 0x6aa551e9, 0xb936bfa4, 0x6a9769c1, 0xb921d067, 0x6a897d7d, 0xb90ce3e6,
+ 0x6a7b8d1e, 0xb8f7fa21,
+ 0x6a6d98a4, 0xb8e31319, 0x6a5fa010, 0xb8ce2ecf, 0x6a51a361, 0xb8b94d44,
+ 0x6a43a29a, 0xb8a46e78,
+ 0x6a359db9, 0xb88f926d, 0x6a2794c1, 0xb87ab922, 0x6a1987b0, 0xb865e299,
+ 0x6a0b7689, 0xb8510ed4,
+ 0x69fd614a, 0xb83c3dd1, 0x69ef47f6, 0xb8276f93, 0x69e12a8c, 0xb812a41a,
+ 0x69d3090e, 0xb7fddb67,
+ 0x69c4e37a, 0xb7e9157a, 0x69b6b9d3, 0xb7d45255, 0x69a88c19, 0xb7bf91f8,
+ 0x699a5a4c, 0xb7aad465,
+ 0x698c246c, 0xb796199b, 0x697dea7b, 0xb781619c, 0x696fac78, 0xb76cac69,
+ 0x69616a65, 0xb757fa01,
+ 0x69532442, 0xb7434a67, 0x6944da10, 0xb72e9d9b, 0x69368bce, 0xb719f39e,
+ 0x6928397e, 0xb7054c6f,
+ 0x6919e320, 0xb6f0a812, 0x690b88b5, 0xb6dc0685, 0x68fd2a3d, 0xb6c767ca,
+ 0x68eec7b9, 0xb6b2cbe2,
+ 0x68e06129, 0xb69e32cd, 0x68d1f68f, 0xb6899c8d, 0x68c387e9, 0xb6750921,
+ 0x68b5153a, 0xb660788c,
+ 0x68a69e81, 0xb64beacd, 0x689823bf, 0xb6375fe5, 0x6889a4f6, 0xb622d7d6,
+ 0x687b2224, 0xb60e529f,
+ 0x686c9b4b, 0xb5f9d043, 0x685e106c, 0xb5e550c1, 0x684f8186, 0xb5d0d41a,
+ 0x6840ee9b, 0xb5bc5a50,
+ 0x683257ab, 0xb5a7e362, 0x6823bcb7, 0xb5936f53, 0x68151dbe, 0xb57efe22,
+ 0x68067ac3, 0xb56a8fd0,
+ 0x67f7d3c5, 0xb556245e, 0x67e928c5, 0xb541bbcd, 0x67da79c3, 0xb52d561e,
+ 0x67cbc6c0, 0xb518f351,
+ 0x67bd0fbd, 0xb5049368, 0x67ae54ba, 0xb4f03663, 0x679f95b7, 0xb4dbdc42,
+ 0x6790d2b6, 0xb4c78507,
+ 0x67820bb7, 0xb4b330b3, 0x677340ba, 0xb49edf45, 0x676471c0, 0xb48a90c0,
+ 0x67559eca, 0xb4764523,
+ 0x6746c7d8, 0xb461fc70, 0x6737ecea, 0xb44db6a8, 0x67290e02, 0xb43973ca,
+ 0x671a2b20, 0xb42533d8,
+ 0x670b4444, 0xb410f6d3, 0x66fc596f, 0xb3fcbcbb, 0x66ed6aa1, 0xb3e88592,
+ 0x66de77dc, 0xb3d45157,
+ 0x66cf8120, 0xb3c0200c, 0x66c0866d, 0xb3abf1b2, 0x66b187c3, 0xb397c649,
+ 0x66a28524, 0xb3839dd3,
+ 0x66937e91, 0xb36f784f, 0x66847408, 0xb35b55bf, 0x6675658c, 0xb3473623,
+ 0x6666531d, 0xb333197c,
+ 0x66573cbb, 0xb31effcc, 0x66482267, 0xb30ae912, 0x66390422, 0xb2f6d550,
+ 0x6629e1ec, 0xb2e2c486,
+ 0x661abbc5, 0xb2ceb6b5, 0x660b91af, 0xb2baabde, 0x65fc63a9, 0xb2a6a402,
+ 0x65ed31b5, 0xb2929f21,
+ 0x65ddfbd3, 0xb27e9d3c, 0x65cec204, 0xb26a9e54, 0x65bf8447, 0xb256a26a,
+ 0x65b0429f, 0xb242a97e,
+ 0x65a0fd0b, 0xb22eb392, 0x6591b38c, 0xb21ac0a6, 0x65826622, 0xb206d0ba,
+ 0x657314cf, 0xb1f2e3d0,
+ 0x6563bf92, 0xb1def9e9, 0x6554666d, 0xb1cb1304, 0x6545095f, 0xb1b72f23,
+ 0x6535a86b, 0xb1a34e47,
+ 0x6526438f, 0xb18f7071, 0x6516dacd, 0xb17b95a0, 0x65076e25, 0xb167bdd7,
+ 0x64f7fd98, 0xb153e915,
+ 0x64e88926, 0xb140175b, 0x64d910d1, 0xb12c48ab, 0x64c99498, 0xb1187d05,
+ 0x64ba147d, 0xb104b46a,
+ 0x64aa907f, 0xb0f0eeda, 0x649b08a0, 0xb0dd2c56, 0x648b7ce0, 0xb0c96ce0,
+ 0x647bed3f, 0xb0b5b077,
+ 0x646c59bf, 0xb0a1f71d, 0x645cc260, 0xb08e40d2, 0x644d2722, 0xb07a8d97,
+ 0x643d8806, 0xb066dd6d,
+ 0x642de50d, 0xb0533055, 0x641e3e38, 0xb03f864f, 0x640e9386, 0xb02bdf5c,
+ 0x63fee4f8, 0xb0183b7d,
+ 0x63ef3290, 0xb0049ab3, 0x63df7c4d, 0xaff0fcfe, 0x63cfc231, 0xafdd625f,
+ 0x63c0043b, 0xafc9cad7,
+ 0x63b0426d, 0xafb63667, 0x63a07cc7, 0xafa2a50f, 0x6390b34a, 0xaf8f16d1,
+ 0x6380e5f6, 0xaf7b8bac,
+ 0x637114cc, 0xaf6803a2, 0x63613fcd, 0xaf547eb3, 0x635166f9, 0xaf40fce1,
+ 0x63418a50, 0xaf2d7e2b,
+ 0x6331a9d4, 0xaf1a0293, 0x6321c585, 0xaf068a1a, 0x6311dd64, 0xaef314c0,
+ 0x6301f171, 0xaedfa285,
+ 0x62f201ac, 0xaecc336c, 0x62e20e17, 0xaeb8c774, 0x62d216b3, 0xaea55e9e,
+ 0x62c21b7e, 0xae91f8eb,
+ 0x62b21c7b, 0xae7e965b, 0x62a219aa, 0xae6b36f0, 0x6292130c, 0xae57daab,
+ 0x628208a1, 0xae44818b,
+ 0x6271fa69, 0xae312b92, 0x6261e866, 0xae1dd8c0, 0x6251d298, 0xae0a8916,
+ 0x6241b8ff, 0xadf73c96,
+ 0x62319b9d, 0xade3f33e, 0x62217a72, 0xadd0ad12, 0x6211557e, 0xadbd6a10,
+ 0x62012cc2, 0xadaa2a3b,
+ 0x61f1003f, 0xad96ed92, 0x61e0cff5, 0xad83b416, 0x61d09be5, 0xad707dc8,
+ 0x61c06410, 0xad5d4aaa,
+ 0x61b02876, 0xad4a1aba, 0x619fe918, 0xad36edfc, 0x618fa5f7, 0xad23c46e,
+ 0x617f5f12, 0xad109e12,
+ 0x616f146c, 0xacfd7ae8, 0x615ec603, 0xacea5af2, 0x614e73da, 0xacd73e30,
+ 0x613e1df0, 0xacc424a3,
+ 0x612dc447, 0xacb10e4b, 0x611d66de, 0xac9dfb29, 0x610d05b7, 0xac8aeb3e,
+ 0x60fca0d2, 0xac77de8b,
+ 0x60ec3830, 0xac64d510, 0x60dbcbd1, 0xac51cecf, 0x60cb5bb7, 0xac3ecbc7,
+ 0x60bae7e1, 0xac2bcbfa,
+ 0x60aa7050, 0xac18cf69, 0x6099f505, 0xac05d613, 0x60897601, 0xabf2dffb,
+ 0x6078f344, 0xabdfed1f,
+ 0x60686ccf, 0xabccfd83, 0x6057e2a2, 0xabba1125, 0x604754bf, 0xaba72807,
+ 0x6036c325, 0xab944229,
+ 0x60262dd6, 0xab815f8d, 0x601594d1, 0xab6e8032, 0x6004f819, 0xab5ba41a,
+ 0x5ff457ad, 0xab48cb46,
+ 0x5fe3b38d, 0xab35f5b5, 0x5fd30bbc, 0xab23236a, 0x5fc26038, 0xab105464,
+ 0x5fb1b104, 0xaafd88a4,
+ 0x5fa0fe1f, 0xaaeac02c, 0x5f90478a, 0xaad7fafb, 0x5f7f8d46, 0xaac53912,
+ 0x5f6ecf53, 0xaab27a73,
+ 0x5f5e0db3, 0xaa9fbf1e, 0x5f4d4865, 0xaa8d0713, 0x5f3c7f6b, 0xaa7a5253,
+ 0x5f2bb2c5, 0xaa67a0e0,
+ 0x5f1ae274, 0xaa54f2ba, 0x5f0a0e77, 0xaa4247e1, 0x5ef936d1, 0xaa2fa056,
+ 0x5ee85b82, 0xaa1cfc1a,
+ 0x5ed77c8a, 0xaa0a5b2e, 0x5ec699e9, 0xa9f7bd92, 0x5eb5b3a2, 0xa9e52347,
+ 0x5ea4c9b3, 0xa9d28c4e,
+ 0x5e93dc1f, 0xa9bff8a8, 0x5e82eae5, 0xa9ad6855, 0x5e71f606, 0xa99adb56,
+ 0x5e60fd84, 0xa98851ac,
+ 0x5e50015d, 0xa975cb57, 0x5e3f0194, 0xa9634858, 0x5e2dfe29, 0xa950c8b0,
+ 0x5e1cf71c, 0xa93e4c5f,
+ 0x5e0bec6e, 0xa92bd367, 0x5dfade20, 0xa9195dc7, 0x5de9cc33, 0xa906eb82,
+ 0x5dd8b6a7, 0xa8f47c97,
+ 0x5dc79d7c, 0xa8e21106, 0x5db680b4, 0xa8cfa8d2, 0x5da5604f, 0xa8bd43fa,
+ 0x5d943c4e, 0xa8aae280,
+ 0x5d8314b1, 0xa8988463, 0x5d71e979, 0xa88629a5, 0x5d60baa7, 0xa873d246,
+ 0x5d4f883b, 0xa8617e48,
+ 0x5d3e5237, 0xa84f2daa, 0x5d2d189a, 0xa83ce06e, 0x5d1bdb65, 0xa82a9693,
+ 0x5d0a9a9a, 0xa818501c,
+ 0x5cf95638, 0xa8060d08, 0x5ce80e41, 0xa7f3cd59, 0x5cd6c2b5, 0xa7e1910f,
+ 0x5cc57394, 0xa7cf582a,
+ 0x5cb420e0, 0xa7bd22ac, 0x5ca2ca99, 0xa7aaf094, 0x5c9170bf, 0xa798c1e5,
+ 0x5c801354, 0xa786969e,
+ 0x5c6eb258, 0xa7746ec0, 0x5c5d4dcc, 0xa7624a4d, 0x5c4be5b0, 0xa7502943,
+ 0x5c3a7a05, 0xa73e0ba5,
+ 0x5c290acc, 0xa72bf174, 0x5c179806, 0xa719daae, 0x5c0621b2, 0xa707c757,
+ 0x5bf4a7d2, 0xa6f5b76d,
+ 0x5be32a67, 0xa6e3aaf2, 0x5bd1a971, 0xa6d1a1e7, 0x5bc024f0, 0xa6bf9c4b,
+ 0x5bae9ce7, 0xa6ad9a21,
+ 0x5b9d1154, 0xa69b9b68, 0x5b8b8239, 0xa689a022, 0x5b79ef96, 0xa677a84e,
+ 0x5b68596d, 0xa665b3ee,
+ 0x5b56bfbd, 0xa653c303, 0x5b452288, 0xa641d58c, 0x5b3381ce, 0xa62feb8b,
+ 0x5b21dd90, 0xa61e0501,
+ 0x5b1035cf, 0xa60c21ee, 0x5afe8a8b, 0xa5fa4252, 0x5aecdbc5, 0xa5e8662f,
+ 0x5adb297d, 0xa5d68d85,
+ 0x5ac973b5, 0xa5c4b855, 0x5ab7ba6c, 0xa5b2e6a0, 0x5aa5fda5, 0xa5a11866,
+ 0x5a943d5e, 0xa58f4da8,
+ 0x5a82799a, 0xa57d8666, 0x5a70b258, 0xa56bc2a2, 0x5a5ee79a, 0xa55a025b,
+ 0x5a4d1960, 0xa5484594,
+ 0x5a3b47ab, 0xa5368c4b, 0x5a29727b, 0xa524d683, 0x5a1799d1, 0xa513243b,
+ 0x5a05bdae, 0xa5017575,
+ 0x59f3de12, 0xa4efca31, 0x59e1faff, 0xa4de2270, 0x59d01475, 0xa4cc7e32,
+ 0x59be2a74, 0xa4badd78,
+ 0x59ac3cfd, 0xa4a94043, 0x599a4c12, 0xa497a693, 0x598857b2, 0xa486106a,
+ 0x59765fde, 0xa4747dc7,
+ 0x59646498, 0xa462eeac, 0x595265df, 0xa4516319, 0x594063b5, 0xa43fdb10,
+ 0x592e5e19, 0xa42e568f,
+ 0x591c550e, 0xa41cd599, 0x590a4893, 0xa40b582e, 0x58f838a9, 0xa3f9de4e,
+ 0x58e62552, 0xa3e867fa,
+ 0x58d40e8c, 0xa3d6f534, 0x58c1f45b, 0xa3c585fb, 0x58afd6bd, 0xa3b41a50,
+ 0x589db5b3, 0xa3a2b234,
+ 0x588b9140, 0xa3914da8, 0x58796962, 0xa37fecac, 0x58673e1b, 0xa36e8f41,
+ 0x58550f6c, 0xa35d3567,
+ 0x5842dd54, 0xa34bdf20, 0x5830a7d6, 0xa33a8c6c, 0x581e6ef1, 0xa3293d4b,
+ 0x580c32a7, 0xa317f1bf,
+ 0x57f9f2f8, 0xa306a9c8, 0x57e7afe4, 0xa2f56566, 0x57d5696d, 0xa2e4249b,
+ 0x57c31f92, 0xa2d2e766,
+ 0x57b0d256, 0xa2c1adc9, 0x579e81b8, 0xa2b077c5, 0x578c2dba, 0xa29f4559,
+ 0x5779d65b, 0xa28e1687,
+ 0x57677b9d, 0xa27ceb4f, 0x57551d80, 0xa26bc3b2, 0x5742bc06, 0xa25a9fb1,
+ 0x5730572e, 0xa2497f4c,
+ 0x571deefa, 0xa2386284, 0x570b8369, 0xa2274959, 0x56f9147e, 0xa21633cd,
+ 0x56e6a239, 0xa20521e0,
+ 0x56d42c99, 0xa1f41392, 0x56c1b3a1, 0xa1e308e4, 0x56af3750, 0xa1d201d7,
+ 0x569cb7a8, 0xa1c0fe6c,
+ 0x568a34a9, 0xa1affea3, 0x5677ae54, 0xa19f027c, 0x566524aa, 0xa18e09fa,
+ 0x565297ab, 0xa17d151b,
+ 0x56400758, 0xa16c23e1, 0x562d73b2, 0xa15b364d, 0x561adcb9, 0xa14a4c5e,
+ 0x5608426e, 0xa1396617,
+ 0x55f5a4d2, 0xa1288376, 0x55e303e6, 0xa117a47e, 0x55d05faa, 0xa106c92f,
+ 0x55bdb81f, 0xa0f5f189,
+ 0x55ab0d46, 0xa0e51d8c, 0x55985f20, 0xa0d44d3b, 0x5585adad, 0xa0c38095,
+ 0x5572f8ed, 0xa0b2b79b,
+ 0x556040e2, 0xa0a1f24d, 0x554d858d, 0xa09130ad, 0x553ac6ee, 0xa08072ba,
+ 0x55280505, 0xa06fb876,
+ 0x55153fd4, 0xa05f01e1, 0x5502775c, 0xa04e4efc, 0x54efab9c, 0xa03d9fc8,
+ 0x54dcdc96, 0xa02cf444,
+ 0x54ca0a4b, 0xa01c4c73, 0x54b734ba, 0xa00ba853, 0x54a45be6, 0x9ffb07e7,
+ 0x54917fce, 0x9fea6b2f,
+ 0x547ea073, 0x9fd9d22a, 0x546bbdd7, 0x9fc93cdb, 0x5458d7f9, 0x9fb8ab41,
+ 0x5445eedb, 0x9fa81d5e,
+ 0x5433027d, 0x9f979331, 0x542012e1, 0x9f870cbc, 0x540d2005, 0x9f7689ff,
+ 0x53fa29ed, 0x9f660afb,
+ 0x53e73097, 0x9f558fb0, 0x53d43406, 0x9f45181f, 0x53c13439, 0x9f34a449,
+ 0x53ae3131, 0x9f24342f,
+ 0x539b2af0, 0x9f13c7d0, 0x53882175, 0x9f035f2e, 0x537514c2, 0x9ef2fa49,
+ 0x536204d7, 0x9ee29922,
+ 0x534ef1b5, 0x9ed23bb9, 0x533bdb5d, 0x9ec1e210, 0x5328c1d0, 0x9eb18c26,
+ 0x5315a50e, 0x9ea139fd,
+ 0x53028518, 0x9e90eb94, 0x52ef61ee, 0x9e80a0ee, 0x52dc3b92, 0x9e705a09,
+ 0x52c91204, 0x9e6016e8,
+ 0x52b5e546, 0x9e4fd78a, 0x52a2b556, 0x9e3f9bf0, 0x528f8238, 0x9e2f641b,
+ 0x527c4bea, 0x9e1f300b,
+ 0x5269126e, 0x9e0effc1, 0x5255d5c5, 0x9dfed33e, 0x524295f0, 0x9deeaa82,
+ 0x522f52ee, 0x9dde858e,
+ 0x521c0cc2, 0x9dce6463, 0x5208c36a, 0x9dbe4701, 0x51f576ea, 0x9dae2d68,
+ 0x51e22740, 0x9d9e179a,
+ 0x51ced46e, 0x9d8e0597, 0x51bb7e75, 0x9d7df75f, 0x51a82555, 0x9d6decf4,
+ 0x5194c910, 0x9d5de656,
+ 0x518169a5, 0x9d4de385, 0x516e0715, 0x9d3de482, 0x515aa162, 0x9d2de94d,
+ 0x5147388c, 0x9d1df1e9,
+ 0x5133cc94, 0x9d0dfe54, 0x51205d7b, 0x9cfe0e8f, 0x510ceb40, 0x9cee229c,
+ 0x50f975e6, 0x9cde3a7b,
+ 0x50e5fd6d, 0x9cce562c, 0x50d281d5, 0x9cbe75b0, 0x50bf031f, 0x9cae9907,
+ 0x50ab814d, 0x9c9ec033,
+ 0x5097fc5e, 0x9c8eeb34, 0x50847454, 0x9c7f1a0a, 0x5070e92f, 0x9c6f4cb6,
+ 0x505d5af1, 0x9c5f8339,
+ 0x5049c999, 0x9c4fbd93, 0x50363529, 0x9c3ffbc5, 0x50229da1, 0x9c303dcf,
+ 0x500f0302, 0x9c2083b3,
+ 0x4ffb654d, 0x9c10cd70, 0x4fe7c483, 0x9c011b08, 0x4fd420a4, 0x9bf16c7a,
+ 0x4fc079b1, 0x9be1c1c8,
+ 0x4faccfab, 0x9bd21af3, 0x4f992293, 0x9bc277fa, 0x4f857269, 0x9bb2d8de,
+ 0x4f71bf2e, 0x9ba33da0,
+ 0x4f5e08e3, 0x9b93a641, 0x4f4a4f89, 0x9b8412c1, 0x4f369320, 0x9b748320,
+ 0x4f22d3aa, 0x9b64f760,
+ 0x4f0f1126, 0x9b556f81, 0x4efb4b96, 0x9b45eb83, 0x4ee782fb, 0x9b366b68,
+ 0x4ed3b755, 0x9b26ef2f,
+ 0x4ebfe8a5, 0x9b1776da, 0x4eac16eb, 0x9b080268, 0x4e984229, 0x9af891db,
+ 0x4e846a60, 0x9ae92533,
+ 0x4e708f8f, 0x9ad9bc71, 0x4e5cb1b9, 0x9aca5795, 0x4e48d0dd, 0x9abaf6a1,
+ 0x4e34ecfc, 0x9aab9993,
+ 0x4e210617, 0x9a9c406e, 0x4e0d1c30, 0x9a8ceb31, 0x4df92f46, 0x9a7d99de,
+ 0x4de53f5a, 0x9a6e4c74,
+ 0x4dd14c6e, 0x9a5f02f5, 0x4dbd5682, 0x9a4fbd61, 0x4da95d96, 0x9a407bb9,
+ 0x4d9561ac, 0x9a313dfc,
+ 0x4d8162c4, 0x9a22042d, 0x4d6d60df, 0x9a12ce4b, 0x4d595bfe, 0x9a039c57,
+ 0x4d455422, 0x99f46e51,
+ 0x4d31494b, 0x99e5443b, 0x4d1d3b7a, 0x99d61e14, 0x4d092ab0, 0x99c6fbde,
+ 0x4cf516ee, 0x99b7dd99,
+ 0x4ce10034, 0x99a8c345, 0x4ccce684, 0x9999ace3, 0x4cb8c9dd, 0x998a9a74,
+ 0x4ca4aa41, 0x997b8bf8,
+ 0x4c9087b1, 0x996c816f, 0x4c7c622d, 0x995d7adc, 0x4c6839b7, 0x994e783d,
+ 0x4c540e4e, 0x993f7993,
+ 0x4c3fdff4, 0x99307ee0, 0x4c2baea9, 0x99218824, 0x4c177a6e, 0x9912955f,
+ 0x4c034345, 0x9903a691,
+ 0x4bef092d, 0x98f4bbbc, 0x4bdacc28, 0x98e5d4e0, 0x4bc68c36, 0x98d6f1fe,
+ 0x4bb24958, 0x98c81316,
+ 0x4b9e0390, 0x98b93828, 0x4b89badd, 0x98aa6136, 0x4b756f40, 0x989b8e40,
+ 0x4b6120bb, 0x988cbf46,
+ 0x4b4ccf4d, 0x987df449, 0x4b387af9, 0x986f2d4a, 0x4b2423be, 0x98606a49,
+ 0x4b0fc99d, 0x9851ab46,
+ 0x4afb6c98, 0x9842f043, 0x4ae70caf, 0x98343940, 0x4ad2a9e2, 0x9825863d,
+ 0x4abe4433, 0x9816d73b,
+ 0x4aa9dba2, 0x98082c3b, 0x4a957030, 0x97f9853d, 0x4a8101de, 0x97eae242,
+ 0x4a6c90ad, 0x97dc4349,
+ 0x4a581c9e, 0x97cda855, 0x4a43a5b0, 0x97bf1165, 0x4a2f2be6, 0x97b07e7a,
+ 0x4a1aaf3f, 0x97a1ef94,
+ 0x4a062fbd, 0x979364b5, 0x49f1ad61, 0x9784dddc, 0x49dd282a, 0x97765b0a,
+ 0x49c8a01b, 0x9767dc41,
+ 0x49b41533, 0x9759617f, 0x499f8774, 0x974aeac6, 0x498af6df, 0x973c7817,
+ 0x49766373, 0x972e0971,
+ 0x4961cd33, 0x971f9ed7, 0x494d341e, 0x97113847, 0x49389836, 0x9702d5c3,
+ 0x4923f97b, 0x96f4774b,
+ 0x490f57ee, 0x96e61ce0, 0x48fab391, 0x96d7c682, 0x48e60c62, 0x96c97432,
+ 0x48d16265, 0x96bb25f0,
+ 0x48bcb599, 0x96acdbbe, 0x48a805ff, 0x969e959b, 0x48935397, 0x96905388,
+ 0x487e9e64, 0x96821585,
+ 0x4869e665, 0x9673db94, 0x48552b9b, 0x9665a5b4, 0x48406e08, 0x965773e7,
+ 0x482badab, 0x9649462d,
+ 0x4816ea86, 0x963b1c86, 0x48022499, 0x962cf6f2, 0x47ed5be6, 0x961ed574,
+ 0x47d8906d, 0x9610b80a,
+ 0x47c3c22f, 0x96029eb6, 0x47aef12c, 0x95f48977, 0x479a1d67, 0x95e67850,
+ 0x478546de, 0x95d86b3f,
+ 0x47706d93, 0x95ca6247, 0x475b9188, 0x95bc5d66, 0x4746b2bc, 0x95ae5c9f,
+ 0x4731d131, 0x95a05ff0,
+ 0x471cece7, 0x9592675c, 0x470805df, 0x958472e2, 0x46f31c1a, 0x95768283,
+ 0x46de2f99, 0x9568963f,
+ 0x46c9405c, 0x955aae17, 0x46b44e65, 0x954cca0c, 0x469f59b4, 0x953eea1e,
+ 0x468a624a, 0x95310e4e,
+ 0x46756828, 0x9523369c, 0x46606b4e, 0x95156308, 0x464b6bbe, 0x95079394,
+ 0x46366978, 0x94f9c83f,
+ 0x4621647d, 0x94ec010b, 0x460c5cce, 0x94de3df8, 0x45f7526b, 0x94d07f05,
+ 0x45e24556, 0x94c2c435,
+ 0x45cd358f, 0x94b50d87, 0x45b82318, 0x94a75afd, 0x45a30df0, 0x9499ac95,
+ 0x458df619, 0x948c0252,
+ 0x4578db93, 0x947e5c33, 0x4563be60, 0x9470ba39, 0x454e9e80, 0x94631c65,
+ 0x45397bf4, 0x945582b7,
+ 0x452456bd, 0x9447ed2f, 0x450f2edb, 0x943a5bcf, 0x44fa0450, 0x942cce96,
+ 0x44e4d71c, 0x941f4585,
+ 0x44cfa740, 0x9411c09e, 0x44ba74bd, 0x94043fdf, 0x44a53f93, 0x93f6c34a,
+ 0x449007c4, 0x93e94adf,
+ 0x447acd50, 0x93dbd6a0, 0x44659039, 0x93ce668b, 0x4450507e, 0x93c0faa3,
+ 0x443b0e21, 0x93b392e6,
+ 0x4425c923, 0x93a62f57, 0x44108184, 0x9398cff5, 0x43fb3746, 0x938b74c1,
+ 0x43e5ea68, 0x937e1dbb,
+ 0x43d09aed, 0x9370cae4, 0x43bb48d4, 0x93637c3d, 0x43a5f41e, 0x935631c5,
+ 0x43909ccd, 0x9348eb7e,
+ 0x437b42e1, 0x933ba968, 0x4365e65b, 0x932e6b84, 0x4350873c, 0x932131d1,
+ 0x433b2585, 0x9313fc51,
+ 0x4325c135, 0x9306cb04, 0x43105a50, 0x92f99deb, 0x42faf0d4, 0x92ec7505,
+ 0x42e584c3, 0x92df5054,
+ 0x42d0161e, 0x92d22fd9, 0x42baa4e6, 0x92c51392, 0x42a5311b, 0x92b7fb82,
+ 0x428fbabe, 0x92aae7a8,
+ 0x427a41d0, 0x929dd806, 0x4264c653, 0x9290cc9b, 0x424f4845, 0x9283c568,
+ 0x4239c7aa, 0x9276c26d,
+ 0x42244481, 0x9269c3ac, 0x420ebecb, 0x925cc924, 0x41f93689, 0x924fd2d7,
+ 0x41e3abbc, 0x9242e0c4,
+ 0x41ce1e65, 0x9235f2ec, 0x41b88e84, 0x9229094f, 0x41a2fc1a, 0x921c23ef,
+ 0x418d6729, 0x920f42cb,
+ 0x4177cfb1, 0x920265e4, 0x416235b2, 0x91f58d3b, 0x414c992f, 0x91e8b8d0,
+ 0x4136fa27, 0x91dbe8a4,
+ 0x4121589b, 0x91cf1cb6, 0x410bb48c, 0x91c25508, 0x40f60dfb, 0x91b5919a,
+ 0x40e064ea, 0x91a8d26d,
+ 0x40cab958, 0x919c1781, 0x40b50b46, 0x918f60d6, 0x409f5ab6, 0x9182ae6d,
+ 0x4089a7a8, 0x91760047,
+ 0x4073f21d, 0x91695663, 0x405e3a16, 0x915cb0c3, 0x40487f94, 0x91500f67,
+ 0x4032c297, 0x91437250,
+ 0x401d0321, 0x9136d97d, 0x40074132, 0x912a44f0, 0x3ff17cca, 0x911db4a9,
+ 0x3fdbb5ec, 0x911128a8,
+ 0x3fc5ec98, 0x9104a0ee, 0x3fb020ce, 0x90f81d7b, 0x3f9a5290, 0x90eb9e50,
+ 0x3f8481dd, 0x90df236e,
+ 0x3f6eaeb8, 0x90d2acd4, 0x3f58d921, 0x90c63a83, 0x3f430119, 0x90b9cc7d,
+ 0x3f2d26a0, 0x90ad62c0,
+ 0x3f1749b8, 0x90a0fd4e, 0x3f016a61, 0x90949c28, 0x3eeb889c, 0x90883f4d,
+ 0x3ed5a46b, 0x907be6be,
+ 0x3ebfbdcd, 0x906f927c, 0x3ea9d4c3, 0x90634287, 0x3e93e950, 0x9056f6df,
+ 0x3e7dfb73, 0x904aaf86,
+ 0x3e680b2c, 0x903e6c7b, 0x3e52187f, 0x90322dbf, 0x3e3c2369, 0x9025f352,
+ 0x3e262bee, 0x9019bd36,
+ 0x3e10320d, 0x900d8b69, 0x3dfa35c8, 0x90015dee, 0x3de4371f, 0x8ff534c4,
+ 0x3dce3614, 0x8fe90fec,
+ 0x3db832a6, 0x8fdcef66, 0x3da22cd7, 0x8fd0d333, 0x3d8c24a8, 0x8fc4bb53,
+ 0x3d761a19, 0x8fb8a7c7,
+ 0x3d600d2c, 0x8fac988f, 0x3d49fde1, 0x8fa08dab, 0x3d33ec39, 0x8f94871d,
+ 0x3d1dd835, 0x8f8884e4,
+ 0x3d07c1d6, 0x8f7c8701, 0x3cf1a91c, 0x8f708d75, 0x3cdb8e09, 0x8f649840,
+ 0x3cc5709e, 0x8f58a761,
+ 0x3caf50da, 0x8f4cbadb, 0x3c992ec0, 0x8f40d2ad, 0x3c830a50, 0x8f34eed8,
+ 0x3c6ce38a, 0x8f290f5c,
+ 0x3c56ba70, 0x8f1d343a, 0x3c408f03, 0x8f115d72, 0x3c2a6142, 0x8f058b04,
+ 0x3c143130, 0x8ef9bcf2,
+ 0x3bfdfecd, 0x8eedf33b, 0x3be7ca1a, 0x8ee22de0, 0x3bd19318, 0x8ed66ce1,
+ 0x3bbb59c7, 0x8ecab040,
+ 0x3ba51e29, 0x8ebef7fb, 0x3b8ee03e, 0x8eb34415, 0x3b78a007, 0x8ea7948c,
+ 0x3b625d86, 0x8e9be963,
+ 0x3b4c18ba, 0x8e904298, 0x3b35d1a5, 0x8e84a02d, 0x3b1f8848, 0x8e790222,
+ 0x3b093ca3, 0x8e6d6877,
+ 0x3af2eeb7, 0x8e61d32e, 0x3adc9e86, 0x8e564246, 0x3ac64c0f, 0x8e4ab5bf,
+ 0x3aaff755, 0x8e3f2d9b,
+ 0x3a99a057, 0x8e33a9da, 0x3a834717, 0x8e282a7b, 0x3a6ceb96, 0x8e1caf80,
+ 0x3a568dd4, 0x8e1138ea,
+ 0x3a402dd2, 0x8e05c6b7, 0x3a29cb91, 0x8dfa58ea, 0x3a136712, 0x8deeef82,
+ 0x39fd0056, 0x8de38a80,
+ 0x39e6975e, 0x8dd829e4, 0x39d02c2a, 0x8dcccdaf, 0x39b9bebc, 0x8dc175e0,
+ 0x39a34f13, 0x8db6227a,
+ 0x398cdd32, 0x8daad37b, 0x39766919, 0x8d9f88e5, 0x395ff2c9, 0x8d9442b8,
+ 0x39497a43, 0x8d8900f3,
+ 0x3932ff87, 0x8d7dc399, 0x391c8297, 0x8d728aa9, 0x39060373, 0x8d675623,
+ 0x38ef821c, 0x8d5c2609,
+ 0x38d8fe93, 0x8d50fa59, 0x38c278d9, 0x8d45d316, 0x38abf0ef, 0x8d3ab03f,
+ 0x389566d6, 0x8d2f91d5,
+ 0x387eda8e, 0x8d2477d8, 0x38684c19, 0x8d196249, 0x3851bb77, 0x8d0e5127,
+ 0x383b28a9, 0x8d034474,
+ 0x382493b0, 0x8cf83c30, 0x380dfc8d, 0x8ced385b, 0x37f76341, 0x8ce238f6,
+ 0x37e0c7cc, 0x8cd73e01,
+ 0x37ca2a30, 0x8ccc477d, 0x37b38a6d, 0x8cc1556a, 0x379ce885, 0x8cb667c8,
+ 0x37864477, 0x8cab7e98,
+ 0x376f9e46, 0x8ca099da, 0x3758f5f2, 0x8c95b98f, 0x37424b7b, 0x8c8addb7,
+ 0x372b9ee3, 0x8c800652,
+ 0x3714f02a, 0x8c753362, 0x36fe3f52, 0x8c6a64e5, 0x36e78c5b, 0x8c5f9ade,
+ 0x36d0d746, 0x8c54d54c,
+ 0x36ba2014, 0x8c4a142f, 0x36a366c6, 0x8c3f5788, 0x368cab5c, 0x8c349f58,
+ 0x3675edd9, 0x8c29eb9f,
+ 0x365f2e3b, 0x8c1f3c5d, 0x36486c86, 0x8c149192, 0x3631a8b8, 0x8c09eb40,
+ 0x361ae2d3, 0x8bff4966,
+ 0x36041ad9, 0x8bf4ac05, 0x35ed50c9, 0x8bea131e, 0x35d684a6, 0x8bdf7eb0,
+ 0x35bfb66e, 0x8bd4eebc,
+ 0x35a8e625, 0x8bca6343, 0x359213c9, 0x8bbfdc44, 0x357b3f5d, 0x8bb559c1,
+ 0x356468e2, 0x8baadbba,
+ 0x354d9057, 0x8ba0622f, 0x3536b5be, 0x8b95ed21, 0x351fd918, 0x8b8b7c8f,
+ 0x3508fa66, 0x8b81107b,
+ 0x34f219a8, 0x8b76a8e4, 0x34db36df, 0x8b6c45cc, 0x34c4520d, 0x8b61e733,
+ 0x34ad6b32, 0x8b578d18,
+ 0x34968250, 0x8b4d377c, 0x347f9766, 0x8b42e661, 0x3468aa76, 0x8b3899c6,
+ 0x3451bb81, 0x8b2e51ab,
+ 0x343aca87, 0x8b240e11, 0x3423d78a, 0x8b19cef8, 0x340ce28b, 0x8b0f9462,
+ 0x33f5eb89, 0x8b055e4d,
+ 0x33def287, 0x8afb2cbb, 0x33c7f785, 0x8af0ffac, 0x33b0fa84, 0x8ae6d720,
+ 0x3399fb85, 0x8adcb318,
+ 0x3382fa88, 0x8ad29394, 0x336bf78f, 0x8ac87894, 0x3354f29b, 0x8abe6219,
+ 0x333debab, 0x8ab45024,
+ 0x3326e2c3, 0x8aaa42b4, 0x330fd7e1, 0x8aa039cb, 0x32f8cb07, 0x8a963567,
+ 0x32e1bc36, 0x8a8c358b,
+ 0x32caab6f, 0x8a823a36, 0x32b398b3, 0x8a784368, 0x329c8402, 0x8a6e5123,
+ 0x32856d5e, 0x8a646365,
+ 0x326e54c7, 0x8a5a7a31, 0x32573a3f, 0x8a509585, 0x32401dc6, 0x8a46b564,
+ 0x3228ff5c, 0x8a3cd9cc,
+ 0x3211df04, 0x8a3302be, 0x31fabcbd, 0x8a29303b, 0x31e39889, 0x8a1f6243,
+ 0x31cc7269, 0x8a1598d6,
+ 0x31b54a5e, 0x8a0bd3f5, 0x319e2067, 0x8a0213a0, 0x3186f487, 0x89f857d8,
+ 0x316fc6be, 0x89eea09d,
+ 0x3158970e, 0x89e4edef, 0x31416576, 0x89db3fcf, 0x312a31f8, 0x89d1963c,
+ 0x3112fc95, 0x89c7f138,
+ 0x30fbc54d, 0x89be50c3, 0x30e48c22, 0x89b4b4dd, 0x30cd5115, 0x89ab1d87,
+ 0x30b61426, 0x89a18ac0,
+ 0x309ed556, 0x8997fc8a, 0x308794a6, 0x898e72e4, 0x30705217, 0x8984edcf,
+ 0x30590dab, 0x897b6d4c,
+ 0x3041c761, 0x8971f15a, 0x302a7f3a, 0x896879fb, 0x30133539, 0x895f072e,
+ 0x2ffbe95d, 0x895598f3,
+ 0x2fe49ba7, 0x894c2f4c, 0x2fcd4c19, 0x8942ca39, 0x2fb5fab2, 0x893969b9,
+ 0x2f9ea775, 0x89300dce,
+ 0x2f875262, 0x8926b677, 0x2f6ffb7a, 0x891d63b5, 0x2f58a2be, 0x89141589,
+ 0x2f41482e, 0x890acbf2,
+ 0x2f29ebcc, 0x890186f2, 0x2f128d99, 0x88f84687, 0x2efb2d95, 0x88ef0ab4,
+ 0x2ee3cbc1, 0x88e5d378,
+ 0x2ecc681e, 0x88dca0d3, 0x2eb502ae, 0x88d372c6, 0x2e9d9b70, 0x88ca4951,
+ 0x2e863267, 0x88c12475,
+ 0x2e6ec792, 0x88b80432, 0x2e575af3, 0x88aee888, 0x2e3fec8b, 0x88a5d177,
+ 0x2e287c5a, 0x889cbf01,
+ 0x2e110a62, 0x8893b125, 0x2df996a3, 0x888aa7e3, 0x2de2211e, 0x8881a33d,
+ 0x2dcaa9d5, 0x8878a332,
+ 0x2db330c7, 0x886fa7c2, 0x2d9bb5f6, 0x8866b0ef, 0x2d843964, 0x885dbeb8,
+ 0x2d6cbb10, 0x8854d11e,
+ 0x2d553afc, 0x884be821, 0x2d3db928, 0x884303c1, 0x2d263596, 0x883a23ff,
+ 0x2d0eb046, 0x883148db,
+ 0x2cf72939, 0x88287256, 0x2cdfa071, 0x881fa06f, 0x2cc815ee, 0x8816d327,
+ 0x2cb089b1, 0x880e0a7f,
+ 0x2c98fbba, 0x88054677, 0x2c816c0c, 0x87fc870f, 0x2c69daa6, 0x87f3cc48,
+ 0x2c52478a, 0x87eb1621,
+ 0x2c3ab2b9, 0x87e2649b, 0x2c231c33, 0x87d9b7b7, 0x2c0b83fa, 0x87d10f75,
+ 0x2bf3ea0d, 0x87c86bd5,
+ 0x2bdc4e6f, 0x87bfccd7, 0x2bc4b120, 0x87b7327d, 0x2bad1221, 0x87ae9cc5,
+ 0x2b957173, 0x87a60bb1,
+ 0x2b7dcf17, 0x879d7f41, 0x2b662b0e, 0x8794f774, 0x2b4e8558, 0x878c744d,
+ 0x2b36ddf7, 0x8783f5ca,
+ 0x2b1f34eb, 0x877b7bec, 0x2b078a36, 0x877306b4, 0x2aefddd8, 0x876a9621,
+ 0x2ad82fd2, 0x87622a35,
+ 0x2ac08026, 0x8759c2ef, 0x2aa8ced3, 0x87516050, 0x2a911bdc, 0x87490258,
+ 0x2a796740, 0x8740a907,
+ 0x2a61b101, 0x8738545e, 0x2a49f920, 0x8730045d, 0x2a323f9e, 0x8727b905,
+ 0x2a1a847b, 0x871f7255,
+ 0x2a02c7b8, 0x8717304e, 0x29eb0957, 0x870ef2f1, 0x29d34958, 0x8706ba3d,
+ 0x29bb87bc, 0x86fe8633,
+ 0x29a3c485, 0x86f656d3, 0x298bffb2, 0x86ee2c1e, 0x29743946, 0x86e60614,
+ 0x295c7140, 0x86dde4b5,
+ 0x2944a7a2, 0x86d5c802, 0x292cdc6d, 0x86cdaffa, 0x29150fa1, 0x86c59c9f,
+ 0x28fd4140, 0x86bd8df0,
+ 0x28e5714b, 0x86b583ee, 0x28cd9fc1, 0x86ad7e99, 0x28b5cca5, 0x86a57df2,
+ 0x289df7f8, 0x869d81f8,
+ 0x288621b9, 0x86958aac, 0x286e49ea, 0x868d980e, 0x2856708d, 0x8685aa20,
+ 0x283e95a1, 0x867dc0e0,
+ 0x2826b928, 0x8675dc4f, 0x280edb23, 0x866dfc6e, 0x27f6fb92, 0x8666213c,
+ 0x27df1a77, 0x865e4abb,
+ 0x27c737d3, 0x865678eb, 0x27af53a6, 0x864eabcb, 0x27976df1, 0x8646e35c,
+ 0x277f86b5, 0x863f1f9e,
+ 0x27679df4, 0x86376092, 0x274fb3ae, 0x862fa638, 0x2737c7e3, 0x8627f091,
+ 0x271fda96, 0x86203f9c,
+ 0x2707ebc7, 0x86189359, 0x26effb76, 0x8610ebca, 0x26d809a5, 0x860948ef,
+ 0x26c01655, 0x8601aac7,
+ 0x26a82186, 0x85fa1153, 0x26902b39, 0x85f27c93, 0x26783370, 0x85eaec88,
+ 0x26603a2c, 0x85e36132,
+ 0x26483f6c, 0x85dbda91, 0x26304333, 0x85d458a6, 0x26184581, 0x85ccdb70,
+ 0x26004657, 0x85c562f1,
+ 0x25e845b6, 0x85bdef28, 0x25d0439f, 0x85b68015, 0x25b84012, 0x85af15b9,
+ 0x25a03b11, 0x85a7b015,
+ 0x2588349d, 0x85a04f28, 0x25702cb7, 0x8598f2f3, 0x2558235f, 0x85919b76,
+ 0x25401896, 0x858a48b1,
+ 0x25280c5e, 0x8582faa5, 0x250ffeb7, 0x857bb152, 0x24f7efa2, 0x85746cb8,
+ 0x24dfdf20, 0x856d2cd7,
+ 0x24c7cd33, 0x8565f1b0, 0x24afb9da, 0x855ebb44, 0x2497a517, 0x85578991,
+ 0x247f8eec, 0x85505c99,
+ 0x24677758, 0x8549345c, 0x244f5e5c, 0x854210db, 0x243743fa, 0x853af214,
+ 0x241f2833, 0x8533d809,
+ 0x24070b08, 0x852cc2bb, 0x23eeec78, 0x8525b228, 0x23d6cc87, 0x851ea652,
+ 0x23beab33, 0x85179f39,
+ 0x23a6887f, 0x85109cdd, 0x238e646a, 0x85099f3e, 0x23763ef7, 0x8502a65c,
+ 0x235e1826, 0x84fbb239,
+ 0x2345eff8, 0x84f4c2d4, 0x232dc66d, 0x84edd82d, 0x23159b88, 0x84e6f244,
+ 0x22fd6f48, 0x84e0111b,
+ 0x22e541af, 0x84d934b1, 0x22cd12bd, 0x84d25d06, 0x22b4e274, 0x84cb8a1b,
+ 0x229cb0d5, 0x84c4bbf0,
+ 0x22847de0, 0x84bdf286, 0x226c4996, 0x84b72ddb, 0x225413f8, 0x84b06df2,
+ 0x223bdd08, 0x84a9b2ca,
+ 0x2223a4c5, 0x84a2fc62, 0x220b6b32, 0x849c4abd, 0x21f3304f, 0x84959dd9,
+ 0x21daf41d, 0x848ef5b7,
+ 0x21c2b69c, 0x84885258, 0x21aa77cf, 0x8481b3bb, 0x219237b5, 0x847b19e1,
+ 0x2179f64f, 0x847484ca,
+ 0x2161b3a0, 0x846df477, 0x21496fa7, 0x846768e7, 0x21312a65, 0x8460e21a,
+ 0x2118e3dc, 0x845a6012,
+ 0x21009c0c, 0x8453e2cf, 0x20e852f6, 0x844d6a50, 0x20d0089c, 0x8446f695,
+ 0x20b7bcfe, 0x844087a0,
+ 0x209f701c, 0x843a1d70, 0x208721f9, 0x8433b806, 0x206ed295, 0x842d5762,
+ 0x205681f1, 0x8426fb84,
+ 0x203e300d, 0x8420a46c, 0x2025dcec, 0x841a521a, 0x200d888d, 0x84140490,
+ 0x1ff532f2, 0x840dbbcc,
+ 0x1fdcdc1b, 0x840777d0, 0x1fc4840a, 0x8401389b, 0x1fac2abf, 0x83fafe2e,
+ 0x1f93d03c, 0x83f4c889,
+ 0x1f7b7481, 0x83ee97ad, 0x1f63178f, 0x83e86b99, 0x1f4ab968, 0x83e2444d,
+ 0x1f325a0b, 0x83dc21cb,
+ 0x1f19f97b, 0x83d60412, 0x1f0197b8, 0x83cfeb22, 0x1ee934c3, 0x83c9d6fc,
+ 0x1ed0d09d, 0x83c3c7a0,
+ 0x1eb86b46, 0x83bdbd0e, 0x1ea004c1, 0x83b7b746, 0x1e879d0d, 0x83b1b649,
+ 0x1e6f342c, 0x83abba17,
+ 0x1e56ca1e, 0x83a5c2b0, 0x1e3e5ee5, 0x839fd014, 0x1e25f282, 0x8399e244,
+ 0x1e0d84f5, 0x8393f940,
+ 0x1df5163f, 0x838e1507, 0x1ddca662, 0x8388359b, 0x1dc4355e, 0x83825afb,
+ 0x1dabc334, 0x837c8528,
+ 0x1d934fe5, 0x8376b422, 0x1d7adb73, 0x8370e7e9, 0x1d6265dd, 0x836b207d,
+ 0x1d49ef26, 0x83655ddf,
+ 0x1d31774d, 0x835fa00f, 0x1d18fe54, 0x8359e70d, 0x1d00843d, 0x835432d8,
+ 0x1ce80906, 0x834e8373,
+ 0x1ccf8cb3, 0x8348d8dc, 0x1cb70f43, 0x83433314, 0x1c9e90b8, 0x833d921b,
+ 0x1c861113, 0x8337f5f1,
+ 0x1c6d9053, 0x83325e97, 0x1c550e7c, 0x832ccc0d, 0x1c3c8b8c, 0x83273e52,
+ 0x1c240786, 0x8321b568,
+ 0x1c0b826a, 0x831c314e, 0x1bf2fc3a, 0x8316b205, 0x1bda74f6, 0x8311378d,
+ 0x1bc1ec9e, 0x830bc1e6,
+ 0x1ba96335, 0x83065110, 0x1b90d8bb, 0x8300e50b, 0x1b784d30, 0x82fb7dd8,
+ 0x1b5fc097, 0x82f61b77,
+ 0x1b4732ef, 0x82f0bde8, 0x1b2ea43a, 0x82eb652b, 0x1b161479, 0x82e61141,
+ 0x1afd83ad, 0x82e0c22a,
+ 0x1ae4f1d6, 0x82db77e5, 0x1acc5ef6, 0x82d63274, 0x1ab3cb0d, 0x82d0f1d5,
+ 0x1a9b361d, 0x82cbb60b,
+ 0x1a82a026, 0x82c67f14, 0x1a6a0929, 0x82c14cf1, 0x1a517128, 0x82bc1fa2,
+ 0x1a38d823, 0x82b6f727,
+ 0x1a203e1b, 0x82b1d381, 0x1a07a311, 0x82acb4b0, 0x19ef0707, 0x82a79ab3,
+ 0x19d669fc, 0x82a2858c,
+ 0x19bdcbf3, 0x829d753a, 0x19a52ceb, 0x829869be, 0x198c8ce7, 0x82936317,
+ 0x1973ebe6, 0x828e6146,
+ 0x195b49ea, 0x8289644b, 0x1942a6f3, 0x82846c26, 0x192a0304, 0x827f78d8,
+ 0x19115e1c, 0x827a8a61,
+ 0x18f8b83c, 0x8275a0c0, 0x18e01167, 0x8270bbf7, 0x18c7699b, 0x826bdc04,
+ 0x18aec0db, 0x826700e9,
+ 0x18961728, 0x82622aa6, 0x187d6c82, 0x825d593a, 0x1864c0ea, 0x82588ca7,
+ 0x184c1461, 0x8253c4eb,
+ 0x183366e9, 0x824f0208, 0x181ab881, 0x824a43fe, 0x1802092c, 0x82458acc,
+ 0x17e958ea, 0x8240d673,
+ 0x17d0a7bc, 0x823c26f3, 0x17b7f5a3, 0x82377c4c, 0x179f429f, 0x8232d67f,
+ 0x17868eb3, 0x822e358b,
+ 0x176dd9de, 0x82299971, 0x17552422, 0x82250232, 0x173c6d80, 0x82206fcc,
+ 0x1723b5f9, 0x821be240,
+ 0x170afd8d, 0x82175990, 0x16f2443e, 0x8212d5b9, 0x16d98a0c, 0x820e56be,
+ 0x16c0cef9, 0x8209dc9e,
+ 0x16a81305, 0x82056758, 0x168f5632, 0x8200f6ef, 0x1676987f, 0x81fc8b60,
+ 0x165dd9f0, 0x81f824ae,
+ 0x16451a83, 0x81f3c2d7, 0x162c5a3b, 0x81ef65dc, 0x16139918, 0x81eb0dbe,
+ 0x15fad71b, 0x81e6ba7c,
+ 0x15e21445, 0x81e26c16, 0x15c95097, 0x81de228d, 0x15b08c12, 0x81d9dde1,
+ 0x1597c6b7, 0x81d59e13,
+ 0x157f0086, 0x81d16321, 0x15663982, 0x81cd2d0c, 0x154d71aa, 0x81c8fbd6,
+ 0x1534a901, 0x81c4cf7d,
+ 0x151bdf86, 0x81c0a801, 0x1503153a, 0x81bc8564, 0x14ea4a1f, 0x81b867a5,
+ 0x14d17e36, 0x81b44ec4,
+ 0x14b8b17f, 0x81b03ac2, 0x149fe3fc, 0x81ac2b9e, 0x148715ae, 0x81a82159,
+ 0x146e4694, 0x81a41bf4,
+ 0x145576b1, 0x81a01b6d, 0x143ca605, 0x819c1fc5, 0x1423d492, 0x819828fd,
+ 0x140b0258, 0x81943715,
+ 0x13f22f58, 0x81904a0c, 0x13d95b93, 0x818c61e3, 0x13c0870a, 0x81887e9a,
+ 0x13a7b1bf, 0x8184a032,
+ 0x138edbb1, 0x8180c6a9, 0x137604e2, 0x817cf201, 0x135d2d53, 0x8179223a,
+ 0x13445505, 0x81755754,
+ 0x132b7bf9, 0x8171914e, 0x1312a230, 0x816dd02a, 0x12f9c7aa, 0x816a13e6,
+ 0x12e0ec6a, 0x81665c84,
+ 0x12c8106f, 0x8162aa04, 0x12af33ba, 0x815efc65, 0x1296564d, 0x815b53a8,
+ 0x127d7829, 0x8157afcd,
+ 0x1264994e, 0x815410d4, 0x124bb9be, 0x815076bd, 0x1232d979, 0x814ce188,
+ 0x1219f880, 0x81495136,
+ 0x120116d5, 0x8145c5c7, 0x11e83478, 0x81423f3a, 0x11cf516a, 0x813ebd90,
+ 0x11b66dad, 0x813b40ca,
+ 0x119d8941, 0x8137c8e6, 0x1184a427, 0x813455e6, 0x116bbe60, 0x8130e7c9,
+ 0x1152d7ed, 0x812d7e8f,
+ 0x1139f0cf, 0x812a1a3a, 0x11210907, 0x8126bac8, 0x11082096, 0x8123603a,
+ 0x10ef377d, 0x81200a90,
+ 0x10d64dbd, 0x811cb9ca, 0x10bd6356, 0x81196de9, 0x10a4784b, 0x811626ec,
+ 0x108b8c9b, 0x8112e4d4,
+ 0x1072a048, 0x810fa7a0, 0x1059b352, 0x810c6f52, 0x1040c5bb, 0x81093be8,
+ 0x1027d784, 0x81060d63,
+ 0x100ee8ad, 0x8102e3c4, 0xff5f938, 0x80ffbf0a, 0xfdd0926, 0x80fc9f35,
+ 0xfc41876, 0x80f98446,
+ 0xfab272b, 0x80f66e3c, 0xf923546, 0x80f35d19, 0xf7942c7, 0x80f050db,
+ 0xf604faf, 0x80ed4984,
+ 0xf475bff, 0x80ea4712, 0xf2e67b8, 0x80e74987, 0xf1572dc, 0x80e450e2,
+ 0xefc7d6b, 0x80e15d24,
+ 0xee38766, 0x80de6e4c, 0xeca90ce, 0x80db845b, 0xeb199a4, 0x80d89f51,
+ 0xe98a1e9, 0x80d5bf2e,
+ 0xe7fa99e, 0x80d2e3f2, 0xe66b0c3, 0x80d00d9d, 0xe4db75b, 0x80cd3c2f,
+ 0xe34bd66, 0x80ca6fa9,
+ 0xe1bc2e4, 0x80c7a80a, 0xe02c7d7, 0x80c4e553, 0xde9cc40, 0x80c22784,
+ 0xdd0d01f, 0x80bf6e9c,
+ 0xdb7d376, 0x80bcba9d, 0xd9ed646, 0x80ba0b85, 0xd85d88f, 0x80b76156,
+ 0xd6cda53, 0x80b4bc0e,
+ 0xd53db92, 0x80b21baf, 0xd3adc4e, 0x80af8039, 0xd21dc87, 0x80ace9ab,
+ 0xd08dc3f, 0x80aa5806,
+ 0xcefdb76, 0x80a7cb49, 0xcd6da2d, 0x80a54376, 0xcbdd865, 0x80a2c08b,
+ 0xca4d620, 0x80a04289,
+ 0xc8bd35e, 0x809dc971, 0xc72d020, 0x809b5541, 0xc59cc68, 0x8098e5fb,
+ 0xc40c835, 0x80967b9f,
+ 0xc27c389, 0x8094162c, 0xc0ebe66, 0x8091b5a2, 0xbf5b8cb, 0x808f5a02,
+ 0xbdcb2bb, 0x808d034c,
+ 0xbc3ac35, 0x808ab180, 0xbaaa53b, 0x8088649e, 0xb919dcf, 0x80861ca6,
+ 0xb7895f0, 0x8083d998,
+ 0xb5f8d9f, 0x80819b74, 0xb4684df, 0x807f623b, 0xb2d7baf, 0x807d2dec,
+ 0xb147211, 0x807afe87,
+ 0xafb6805, 0x8078d40d, 0xae25d8d, 0x8076ae7e, 0xac952aa, 0x80748dd9,
+ 0xab0475c, 0x8072721f,
+ 0xa973ba5, 0x80705b50, 0xa7e2f85, 0x806e496c, 0xa6522fe, 0x806c3c74,
+ 0xa4c1610, 0x806a3466,
+ 0xa3308bd, 0x80683143, 0xa19fb04, 0x8066330c, 0xa00ece8, 0x806439c0,
+ 0x9e7de6a, 0x80624560,
+ 0x9cecf89, 0x806055eb, 0x9b5c048, 0x805e6b62, 0x99cb0a7, 0x805c85c4,
+ 0x983a0a7, 0x805aa512,
+ 0x96a9049, 0x8058c94c, 0x9517f8f, 0x8056f272, 0x9386e78, 0x80552084,
+ 0x91f5d06, 0x80535381,
+ 0x9064b3a, 0x80518b6b, 0x8ed3916, 0x804fc841, 0x8d42699, 0x804e0a04,
+ 0x8bb13c5, 0x804c50b2,
+ 0x8a2009a, 0x804a9c4d, 0x888ed1b, 0x8048ecd5, 0x86fd947, 0x80474248,
+ 0x856c520, 0x80459ca9,
+ 0x83db0a7, 0x8043fbf6, 0x8249bdd, 0x80426030, 0x80b86c2, 0x8040c956,
+ 0x7f27157, 0x803f376a,
+ 0x7d95b9e, 0x803daa6a, 0x7c04598, 0x803c2257, 0x7a72f45, 0x803a9f31,
+ 0x78e18a7, 0x803920f8,
+ 0x77501be, 0x8037a7ac, 0x75bea8c, 0x8036334e, 0x742d311, 0x8034c3dd,
+ 0x729bb4e, 0x80335959,
+ 0x710a345, 0x8031f3c2, 0x6f78af6, 0x80309318, 0x6de7262, 0x802f375d,
+ 0x6c5598a, 0x802de08e,
+ 0x6ac406f, 0x802c8ead, 0x6932713, 0x802b41ba, 0x67a0d76, 0x8029f9b4,
+ 0x660f398, 0x8028b69c,
+ 0x647d97c, 0x80277872, 0x62ebf22, 0x80263f36, 0x615a48b, 0x80250ae7,
+ 0x5fc89b8, 0x8023db86,
+ 0x5e36ea9, 0x8022b114, 0x5ca5361, 0x80218b8f, 0x5b137df, 0x80206af8,
+ 0x5981c26, 0x801f4f4f,
+ 0x57f0035, 0x801e3895, 0x565e40d, 0x801d26c8, 0x54cc7b1, 0x801c19ea,
+ 0x533ab20, 0x801b11fa,
+ 0x51a8e5c, 0x801a0ef8, 0x5017165, 0x801910e4, 0x4e8543e, 0x801817bf,
+ 0x4cf36e5, 0x80172388,
+ 0x4b6195d, 0x80163440, 0x49cfba7, 0x801549e6, 0x483ddc3, 0x8014647b,
+ 0x46abfb3, 0x801383fe,
+ 0x451a177, 0x8012a86f, 0x4388310, 0x8011d1d0, 0x41f6480, 0x8011001f,
+ 0x40645c7, 0x8010335c,
+ 0x3ed26e6, 0x800f6b88, 0x3d407df, 0x800ea8a3, 0x3bae8b2, 0x800deaad,
+ 0x3a1c960, 0x800d31a5,
+ 0x388a9ea, 0x800c7d8c, 0x36f8a51, 0x800bce63, 0x3566a96, 0x800b2427,
+ 0x33d4abb, 0x800a7edb,
+ 0x3242abf, 0x8009de7e, 0x30b0aa4, 0x80094310, 0x2f1ea6c, 0x8008ac90,
+ 0x2d8ca16, 0x80081b00,
+ 0x2bfa9a4, 0x80078e5e, 0x2a68917, 0x800706ac, 0x28d6870, 0x800683e8,
+ 0x27447b0, 0x80060614,
+ 0x25b26d7, 0x80058d2f, 0x24205e8, 0x80051939, 0x228e4e2, 0x8004aa32,
+ 0x20fc3c6, 0x8004401a,
+ 0x1f6a297, 0x8003daf1, 0x1dd8154, 0x80037ab7, 0x1c45ffe, 0x80031f6d,
+ 0x1ab3e97, 0x8002c912,
+ 0x1921d20, 0x800277a6, 0x178fb99, 0x80022b29, 0x15fda03, 0x8001e39b,
+ 0x146b860, 0x8001a0fd,
+ 0x12d96b1, 0x8001634e, 0x11474f6, 0x80012a8e, 0xfb5330, 0x8000f6bd,
+ 0xe23160, 0x8000c7dc,
+ 0xc90f88, 0x80009dea, 0xafeda8, 0x800078e7, 0x96cbc1, 0x800058d4, 0x7da9d4,
+ 0x80003daf,
+ 0x6487e3, 0x8000277a, 0x4b65ee, 0x80001635, 0x3243f5, 0x800009df, 0x1921fb,
+ 0x80000278,
+};
+
+static const q31_t WeightsQ31_8192[16384] = {
+ 0x7fffffff, 0x0, 0x7fffffd9, 0xfff9b781, 0x7fffff62, 0xfff36f02, 0x7ffffe9d,
+ 0xffed2684,
+ 0x7ffffd88, 0xffe6de05, 0x7ffffc25, 0xffe09586, 0x7ffffa73, 0xffda4d08,
+ 0x7ffff872, 0xffd40489,
+ 0x7ffff621, 0xffcdbc0b, 0x7ffff382, 0xffc7738c, 0x7ffff094, 0xffc12b0e,
+ 0x7fffed57, 0xffbae290,
+ 0x7fffe9cb, 0xffb49a12, 0x7fffe5f0, 0xffae5195, 0x7fffe1c6, 0xffa80917,
+ 0x7fffdd4d, 0xffa1c09a,
+ 0x7fffd886, 0xff9b781d, 0x7fffd36f, 0xff952fa0, 0x7fffce09, 0xff8ee724,
+ 0x7fffc854, 0xff889ea7,
+ 0x7fffc251, 0xff82562c, 0x7fffbbfe, 0xff7c0db0, 0x7fffb55c, 0xff75c535,
+ 0x7fffae6c, 0xff6f7cba,
+ 0x7fffa72c, 0xff69343f, 0x7fff9f9e, 0xff62ebc5, 0x7fff97c1, 0xff5ca34b,
+ 0x7fff8f94, 0xff565ad1,
+ 0x7fff8719, 0xff501258, 0x7fff7e4f, 0xff49c9df, 0x7fff7536, 0xff438167,
+ 0x7fff6bcd, 0xff3d38ef,
+ 0x7fff6216, 0xff36f078, 0x7fff5810, 0xff30a801, 0x7fff4dbb, 0xff2a5f8b,
+ 0x7fff4317, 0xff241715,
+ 0x7fff3824, 0xff1dcea0, 0x7fff2ce2, 0xff17862b, 0x7fff2151, 0xff113db7,
+ 0x7fff1572, 0xff0af543,
+ 0x7fff0943, 0xff04acd0, 0x7ffefcc5, 0xfefe645e, 0x7ffeeff8, 0xfef81bec,
+ 0x7ffee2dd, 0xfef1d37b,
+ 0x7ffed572, 0xfeeb8b0a, 0x7ffec7b9, 0xfee5429a, 0x7ffeb9b0, 0xfedefa2b,
+ 0x7ffeab59, 0xfed8b1bd,
+ 0x7ffe9cb2, 0xfed2694f, 0x7ffe8dbd, 0xfecc20e2, 0x7ffe7e79, 0xfec5d876,
+ 0x7ffe6ee5, 0xfebf900a,
+ 0x7ffe5f03, 0xfeb947a0, 0x7ffe4ed2, 0xfeb2ff36, 0x7ffe3e52, 0xfeacb6cc,
+ 0x7ffe2d83, 0xfea66e64,
+ 0x7ffe1c65, 0xfea025fd, 0x7ffe0af8, 0xfe99dd96, 0x7ffdf93c, 0xfe939530,
+ 0x7ffde731, 0xfe8d4ccb,
+ 0x7ffdd4d7, 0xfe870467, 0x7ffdc22e, 0xfe80bc04, 0x7ffdaf37, 0xfe7a73a2,
+ 0x7ffd9bf0, 0xfe742b41,
+ 0x7ffd885a, 0xfe6de2e0, 0x7ffd7476, 0xfe679a81, 0x7ffd6042, 0xfe615223,
+ 0x7ffd4bc0, 0xfe5b09c5,
+ 0x7ffd36ee, 0xfe54c169, 0x7ffd21ce, 0xfe4e790d, 0x7ffd0c5f, 0xfe4830b3,
+ 0x7ffcf6a0, 0xfe41e85a,
+ 0x7ffce093, 0xfe3ba002, 0x7ffcca37, 0xfe3557ab, 0x7ffcb38c, 0xfe2f0f55,
+ 0x7ffc9c92, 0xfe28c700,
+ 0x7ffc8549, 0xfe227eac, 0x7ffc6db1, 0xfe1c365a, 0x7ffc55ca, 0xfe15ee09,
+ 0x7ffc3d94, 0xfe0fa5b8,
+ 0x7ffc250f, 0xfe095d69, 0x7ffc0c3b, 0xfe03151c, 0x7ffbf319, 0xfdfccccf,
+ 0x7ffbd9a7, 0xfdf68484,
+ 0x7ffbbfe6, 0xfdf03c3a, 0x7ffba5d7, 0xfde9f3f1, 0x7ffb8b78, 0xfde3aba9,
+ 0x7ffb70cb, 0xfddd6363,
+ 0x7ffb55ce, 0xfdd71b1e, 0x7ffb3a83, 0xfdd0d2db, 0x7ffb1ee9, 0xfdca8a99,
+ 0x7ffb0300, 0xfdc44258,
+ 0x7ffae6c7, 0xfdbdfa18, 0x7ffaca40, 0xfdb7b1da, 0x7ffaad6a, 0xfdb1699e,
+ 0x7ffa9045, 0xfdab2162,
+ 0x7ffa72d1, 0xfda4d929, 0x7ffa550e, 0xfd9e90f0, 0x7ffa36fc, 0xfd9848b9,
+ 0x7ffa189c, 0xfd920084,
+ 0x7ff9f9ec, 0xfd8bb850, 0x7ff9daed, 0xfd85701e, 0x7ff9bba0, 0xfd7f27ed,
+ 0x7ff99c03, 0xfd78dfbd,
+ 0x7ff97c18, 0xfd729790, 0x7ff95bdd, 0xfd6c4f64, 0x7ff93b54, 0xfd660739,
+ 0x7ff91a7b, 0xfd5fbf10,
+ 0x7ff8f954, 0xfd5976e9, 0x7ff8d7de, 0xfd532ec3, 0x7ff8b619, 0xfd4ce69f,
+ 0x7ff89405, 0xfd469e7c,
+ 0x7ff871a2, 0xfd40565c, 0x7ff84ef0, 0xfd3a0e3d, 0x7ff82bef, 0xfd33c61f,
+ 0x7ff8089f, 0xfd2d7e04,
+ 0x7ff7e500, 0xfd2735ea, 0x7ff7c113, 0xfd20edd2, 0x7ff79cd6, 0xfd1aa5bc,
+ 0x7ff7784a, 0xfd145da7,
+ 0x7ff75370, 0xfd0e1594, 0x7ff72e46, 0xfd07cd83, 0x7ff708ce, 0xfd018574,
+ 0x7ff6e307, 0xfcfb3d67,
+ 0x7ff6bcf0, 0xfcf4f55c, 0x7ff6968b, 0xfceead52, 0x7ff66fd7, 0xfce8654b,
+ 0x7ff648d4, 0xfce21d45,
+ 0x7ff62182, 0xfcdbd541, 0x7ff5f9e1, 0xfcd58d3f, 0x7ff5d1f1, 0xfccf453f,
+ 0x7ff5a9b2, 0xfcc8fd41,
+ 0x7ff58125, 0xfcc2b545, 0x7ff55848, 0xfcbc6d4c, 0x7ff52f1d, 0xfcb62554,
+ 0x7ff505a2, 0xfcafdd5e,
+ 0x7ff4dbd9, 0xfca9956a, 0x7ff4b1c0, 0xfca34d78, 0x7ff48759, 0xfc9d0588,
+ 0x7ff45ca3, 0xfc96bd9b,
+ 0x7ff4319d, 0xfc9075af, 0x7ff40649, 0xfc8a2dc6, 0x7ff3daa6, 0xfc83e5de,
+ 0x7ff3aeb4, 0xfc7d9df9,
+ 0x7ff38274, 0xfc775616, 0x7ff355e4, 0xfc710e36, 0x7ff32905, 0xfc6ac657,
+ 0x7ff2fbd7, 0xfc647e7b,
+ 0x7ff2ce5b, 0xfc5e36a0, 0x7ff2a08f, 0xfc57eec9, 0x7ff27275, 0xfc51a6f3,
+ 0x7ff2440b, 0xfc4b5f20,
+ 0x7ff21553, 0xfc45174e, 0x7ff1e64c, 0xfc3ecf80, 0x7ff1b6f6, 0xfc3887b3,
+ 0x7ff18751, 0xfc323fe9,
+ 0x7ff1575d, 0xfc2bf821, 0x7ff1271a, 0xfc25b05c, 0x7ff0f688, 0xfc1f6899,
+ 0x7ff0c5a7, 0xfc1920d8,
+ 0x7ff09478, 0xfc12d91a, 0x7ff062f9, 0xfc0c915e, 0x7ff0312c, 0xfc0649a5,
+ 0x7fefff0f, 0xfc0001ee,
+ 0x7fefcca4, 0xfbf9ba39, 0x7fef99ea, 0xfbf37287, 0x7fef66e1, 0xfbed2ad8,
+ 0x7fef3388, 0xfbe6e32b,
+ 0x7feeffe1, 0xfbe09b80, 0x7feecbec, 0xfbda53d8, 0x7fee97a7, 0xfbd40c33,
+ 0x7fee6313, 0xfbcdc490,
+ 0x7fee2e30, 0xfbc77cf0, 0x7fedf8ff, 0xfbc13552, 0x7fedc37e, 0xfbbaedb7,
+ 0x7fed8daf, 0xfbb4a61f,
+ 0x7fed5791, 0xfbae5e89, 0x7fed2123, 0xfba816f6, 0x7fecea67, 0xfba1cf66,
+ 0x7fecb35c, 0xfb9b87d8,
+ 0x7fec7c02, 0xfb95404d, 0x7fec4459, 0xfb8ef8c5, 0x7fec0c62, 0xfb88b13f,
+ 0x7febd41b, 0xfb8269bd,
+ 0x7feb9b85, 0xfb7c223d, 0x7feb62a1, 0xfb75dac0, 0x7feb296d, 0xfb6f9345,
+ 0x7feaefeb, 0xfb694bce,
+ 0x7feab61a, 0xfb630459, 0x7fea7bfa, 0xfb5cbce7, 0x7fea418b, 0xfb567578,
+ 0x7fea06cd, 0xfb502e0c,
+ 0x7fe9cbc0, 0xfb49e6a3, 0x7fe99064, 0xfb439f3c, 0x7fe954ba, 0xfb3d57d9,
+ 0x7fe918c0, 0xfb371078,
+ 0x7fe8dc78, 0xfb30c91b, 0x7fe89fe0, 0xfb2a81c0, 0x7fe862fa, 0xfb243a69,
+ 0x7fe825c5, 0xfb1df314,
+ 0x7fe7e841, 0xfb17abc2, 0x7fe7aa6e, 0xfb116474, 0x7fe76c4c, 0xfb0b1d28,
+ 0x7fe72ddb, 0xfb04d5e0,
+ 0x7fe6ef1c, 0xfafe8e9b, 0x7fe6b00d, 0xfaf84758, 0x7fe670b0, 0xfaf20019,
+ 0x7fe63103, 0xfaebb8dd,
+ 0x7fe5f108, 0xfae571a4, 0x7fe5b0be, 0xfadf2a6e, 0x7fe57025, 0xfad8e33c,
+ 0x7fe52f3d, 0xfad29c0c,
+ 0x7fe4ee06, 0xfacc54e0, 0x7fe4ac81, 0xfac60db7, 0x7fe46aac, 0xfabfc691,
+ 0x7fe42889, 0xfab97f6e,
+ 0x7fe3e616, 0xfab3384f, 0x7fe3a355, 0xfaacf133, 0x7fe36045, 0xfaa6aa1a,
+ 0x7fe31ce6, 0xfaa06305,
+ 0x7fe2d938, 0xfa9a1bf3, 0x7fe2953b, 0xfa93d4e4, 0x7fe250ef, 0xfa8d8dd8,
+ 0x7fe20c55, 0xfa8746d0,
+ 0x7fe1c76b, 0xfa80ffcb, 0x7fe18233, 0xfa7ab8ca, 0x7fe13cac, 0xfa7471cc,
+ 0x7fe0f6d6, 0xfa6e2ad1,
+ 0x7fe0b0b1, 0xfa67e3da, 0x7fe06a3d, 0xfa619ce7, 0x7fe0237a, 0xfa5b55f7,
+ 0x7fdfdc69, 0xfa550f0a,
+ 0x7fdf9508, 0xfa4ec821, 0x7fdf4d59, 0xfa48813b, 0x7fdf055a, 0xfa423a59,
+ 0x7fdebd0d, 0xfa3bf37a,
+ 0x7fde7471, 0xfa35ac9f, 0x7fde2b86, 0xfa2f65c8, 0x7fdde24d, 0xfa291ef4,
+ 0x7fdd98c4, 0xfa22d823,
+ 0x7fdd4eec, 0xfa1c9157, 0x7fdd04c6, 0xfa164a8e, 0x7fdcba51, 0xfa1003c8,
+ 0x7fdc6f8d, 0xfa09bd06,
+ 0x7fdc247a, 0xfa037648, 0x7fdbd918, 0xf9fd2f8e, 0x7fdb8d67, 0xf9f6e8d7,
+ 0x7fdb4167, 0xf9f0a224,
+ 0x7fdaf519, 0xf9ea5b75, 0x7fdaa87c, 0xf9e414ca, 0x7fda5b8f, 0xf9ddce22,
+ 0x7fda0e54, 0xf9d7877e,
+ 0x7fd9c0ca, 0xf9d140de, 0x7fd972f2, 0xf9cafa42, 0x7fd924ca, 0xf9c4b3a9,
+ 0x7fd8d653, 0xf9be6d15,
+ 0x7fd8878e, 0xf9b82684, 0x7fd8387a, 0xf9b1dff7, 0x7fd7e917, 0xf9ab996e,
+ 0x7fd79965, 0xf9a552e9,
+ 0x7fd74964, 0xf99f0c68, 0x7fd6f914, 0xf998c5ea, 0x7fd6a875, 0xf9927f71,
+ 0x7fd65788, 0xf98c38fc,
+ 0x7fd6064c, 0xf985f28a, 0x7fd5b4c1, 0xf97fac1d, 0x7fd562e7, 0xf97965b4,
+ 0x7fd510be, 0xf9731f4e,
+ 0x7fd4be46, 0xf96cd8ed, 0x7fd46b80, 0xf9669290, 0x7fd4186a, 0xf9604c37,
+ 0x7fd3c506, 0xf95a05e2,
+ 0x7fd37153, 0xf953bf91, 0x7fd31d51, 0xf94d7944, 0x7fd2c900, 0xf94732fb,
+ 0x7fd27460, 0xf940ecb7,
+ 0x7fd21f72, 0xf93aa676, 0x7fd1ca35, 0xf934603a, 0x7fd174a8, 0xf92e1a02,
+ 0x7fd11ecd, 0xf927d3ce,
+ 0x7fd0c8a3, 0xf9218d9e, 0x7fd0722b, 0xf91b4773, 0x7fd01b63, 0xf915014c,
+ 0x7fcfc44d, 0xf90ebb29,
+ 0x7fcf6ce8, 0xf908750a, 0x7fcf1533, 0xf9022ef0, 0x7fcebd31, 0xf8fbe8da,
+ 0x7fce64df, 0xf8f5a2c9,
+ 0x7fce0c3e, 0xf8ef5cbb, 0x7fcdb34f, 0xf8e916b2, 0x7fcd5a11, 0xf8e2d0ae,
+ 0x7fcd0083, 0xf8dc8aae,
+ 0x7fcca6a7, 0xf8d644b2, 0x7fcc4c7d, 0xf8cffebb, 0x7fcbf203, 0xf8c9b8c8,
+ 0x7fcb973b, 0xf8c372d9,
+ 0x7fcb3c23, 0xf8bd2cef, 0x7fcae0bd, 0xf8b6e70a, 0x7fca8508, 0xf8b0a129,
+ 0x7fca2905, 0xf8aa5b4c,
+ 0x7fc9ccb2, 0xf8a41574, 0x7fc97011, 0xf89dcfa1, 0x7fc91320, 0xf89789d2,
+ 0x7fc8b5e1, 0xf8914407,
+ 0x7fc85854, 0xf88afe42, 0x7fc7fa77, 0xf884b880, 0x7fc79c4b, 0xf87e72c4,
+ 0x7fc73dd1, 0xf8782d0c,
+ 0x7fc6df08, 0xf871e759, 0x7fc67ff0, 0xf86ba1aa, 0x7fc62089, 0xf8655c00,
+ 0x7fc5c0d3, 0xf85f165b,
+ 0x7fc560cf, 0xf858d0bb, 0x7fc5007c, 0xf8528b1f, 0x7fc49fda, 0xf84c4588,
+ 0x7fc43ee9, 0xf845fff5,
+ 0x7fc3dda9, 0xf83fba68, 0x7fc37c1b, 0xf83974df, 0x7fc31a3d, 0xf8332f5b,
+ 0x7fc2b811, 0xf82ce9dc,
+ 0x7fc25596, 0xf826a462, 0x7fc1f2cc, 0xf8205eec, 0x7fc18fb4, 0xf81a197b,
+ 0x7fc12c4d, 0xf813d410,
+ 0x7fc0c896, 0xf80d8ea9, 0x7fc06491, 0xf8074947, 0x7fc0003e, 0xf80103ea,
+ 0x7fbf9b9b, 0xf7fabe92,
+ 0x7fbf36aa, 0xf7f4793e, 0x7fbed16a, 0xf7ee33f0, 0x7fbe6bdb, 0xf7e7eea7,
+ 0x7fbe05fd, 0xf7e1a963,
+ 0x7fbd9fd0, 0xf7db6423, 0x7fbd3955, 0xf7d51ee9, 0x7fbcd28b, 0xf7ced9b4,
+ 0x7fbc6b72, 0xf7c89484,
+ 0x7fbc040a, 0xf7c24f59, 0x7fbb9c53, 0xf7bc0a33, 0x7fbb344e, 0xf7b5c512,
+ 0x7fbacbfa, 0xf7af7ff6,
+ 0x7fba6357, 0xf7a93ae0, 0x7fb9fa65, 0xf7a2f5ce, 0x7fb99125, 0xf79cb0c2,
+ 0x7fb92796, 0xf7966bbb,
+ 0x7fb8bdb8, 0xf79026b9, 0x7fb8538b, 0xf789e1bc, 0x7fb7e90f, 0xf7839cc4,
+ 0x7fb77e45, 0xf77d57d2,
+ 0x7fb7132b, 0xf77712e5, 0x7fb6a7c3, 0xf770cdfd, 0x7fb63c0d, 0xf76a891b,
+ 0x7fb5d007, 0xf764443d,
+ 0x7fb563b3, 0xf75dff66, 0x7fb4f710, 0xf757ba93, 0x7fb48a1e, 0xf75175c6,
+ 0x7fb41cdd, 0xf74b30fe,
+ 0x7fb3af4e, 0xf744ec3b, 0x7fb34170, 0xf73ea77e, 0x7fb2d343, 0xf73862c6,
+ 0x7fb264c7, 0xf7321e14,
+ 0x7fb1f5fc, 0xf72bd967, 0x7fb186e3, 0xf72594c0, 0x7fb1177b, 0xf71f501e,
+ 0x7fb0a7c4, 0xf7190b81,
+ 0x7fb037bf, 0xf712c6ea, 0x7fafc76a, 0xf70c8259, 0x7faf56c7, 0xf7063dcd,
+ 0x7faee5d5, 0xf6fff946,
+ 0x7fae7495, 0xf6f9b4c6, 0x7fae0305, 0xf6f3704a, 0x7fad9127, 0xf6ed2bd4,
+ 0x7fad1efa, 0xf6e6e764,
+ 0x7facac7f, 0xf6e0a2fa, 0x7fac39b4, 0xf6da5e95, 0x7fabc69b, 0xf6d41a36,
+ 0x7fab5333, 0xf6cdd5dc,
+ 0x7faadf7c, 0xf6c79188, 0x7faa6b77, 0xf6c14d3a, 0x7fa9f723, 0xf6bb08f1,
+ 0x7fa98280, 0xf6b4c4ae,
+ 0x7fa90d8e, 0xf6ae8071, 0x7fa8984e, 0xf6a83c3a, 0x7fa822bf, 0xf6a1f808,
+ 0x7fa7ace1, 0xf69bb3dd,
+ 0x7fa736b4, 0xf6956fb7, 0x7fa6c039, 0xf68f2b96, 0x7fa6496e, 0xf688e77c,
+ 0x7fa5d256, 0xf682a367,
+ 0x7fa55aee, 0xf67c5f59, 0x7fa4e338, 0xf6761b50, 0x7fa46b32, 0xf66fd74d,
+ 0x7fa3f2df, 0xf6699350,
+ 0x7fa37a3c, 0xf6634f59, 0x7fa3014b, 0xf65d0b68, 0x7fa2880b, 0xf656c77c,
+ 0x7fa20e7c, 0xf6508397,
+ 0x7fa1949e, 0xf64a3fb8, 0x7fa11a72, 0xf643fbdf, 0x7fa09ff7, 0xf63db80b,
+ 0x7fa0252e, 0xf637743e,
+ 0x7f9faa15, 0xf6313077, 0x7f9f2eae, 0xf62aecb5, 0x7f9eb2f8, 0xf624a8fa,
+ 0x7f9e36f4, 0xf61e6545,
+ 0x7f9dbaa0, 0xf6182196, 0x7f9d3dfe, 0xf611dded, 0x7f9cc10d, 0xf60b9a4b,
+ 0x7f9c43ce, 0xf60556ae,
+ 0x7f9bc640, 0xf5ff1318, 0x7f9b4863, 0xf5f8cf87, 0x7f9aca37, 0xf5f28bfd,
+ 0x7f9a4bbd, 0xf5ec4879,
+ 0x7f99ccf4, 0xf5e604fc, 0x7f994ddc, 0xf5dfc184, 0x7f98ce76, 0xf5d97e13,
+ 0x7f984ec1, 0xf5d33aa8,
+ 0x7f97cebd, 0xf5ccf743, 0x7f974e6a, 0xf5c6b3e5, 0x7f96cdc9, 0xf5c0708d,
+ 0x7f964cd9, 0xf5ba2d3b,
+ 0x7f95cb9a, 0xf5b3e9f0, 0x7f954a0d, 0xf5ada6ab, 0x7f94c831, 0xf5a7636c,
+ 0x7f944606, 0xf5a12034,
+ 0x7f93c38c, 0xf59add02, 0x7f9340c4, 0xf59499d6, 0x7f92bdad, 0xf58e56b1,
+ 0x7f923a48, 0xf5881393,
+ 0x7f91b694, 0xf581d07b, 0x7f913291, 0xf57b8d69, 0x7f90ae3f, 0xf5754a5e,
+ 0x7f90299f, 0xf56f0759,
+ 0x7f8fa4b0, 0xf568c45b, 0x7f8f1f72, 0xf5628163, 0x7f8e99e6, 0xf55c3e72,
+ 0x7f8e140a, 0xf555fb88,
+ 0x7f8d8de1, 0xf54fb8a4, 0x7f8d0768, 0xf54975c6, 0x7f8c80a1, 0xf54332ef,
+ 0x7f8bf98b, 0xf53cf01f,
+ 0x7f8b7227, 0xf536ad56, 0x7f8aea74, 0xf5306a93, 0x7f8a6272, 0xf52a27d7,
+ 0x7f89da21, 0xf523e521,
+ 0x7f895182, 0xf51da273, 0x7f88c894, 0xf5175fca, 0x7f883f58, 0xf5111d29,
+ 0x7f87b5cd, 0xf50ada8f,
+ 0x7f872bf3, 0xf50497fb, 0x7f86a1ca, 0xf4fe556e, 0x7f861753, 0xf4f812e7,
+ 0x7f858c8d, 0xf4f1d068,
+ 0x7f850179, 0xf4eb8def, 0x7f847616, 0xf4e54b7d, 0x7f83ea64, 0xf4df0912,
+ 0x7f835e64, 0xf4d8c6ae,
+ 0x7f82d214, 0xf4d28451, 0x7f824577, 0xf4cc41fb, 0x7f81b88a, 0xf4c5ffab,
+ 0x7f812b4f, 0xf4bfbd63,
+ 0x7f809dc5, 0xf4b97b21, 0x7f800fed, 0xf4b338e7, 0x7f7f81c6, 0xf4acf6b3,
+ 0x7f7ef350, 0xf4a6b486,
+ 0x7f7e648c, 0xf4a07261, 0x7f7dd579, 0xf49a3042, 0x7f7d4617, 0xf493ee2b,
+ 0x7f7cb667, 0xf48dac1a,
+ 0x7f7c2668, 0xf4876a10, 0x7f7b961b, 0xf481280e, 0x7f7b057e, 0xf47ae613,
+ 0x7f7a7494, 0xf474a41f,
+ 0x7f79e35a, 0xf46e6231, 0x7f7951d2, 0xf468204b, 0x7f78bffb, 0xf461de6d,
+ 0x7f782dd6, 0xf45b9c95,
+ 0x7f779b62, 0xf4555ac5, 0x7f77089f, 0xf44f18fb, 0x7f76758e, 0xf448d739,
+ 0x7f75e22e, 0xf442957e,
+ 0x7f754e80, 0xf43c53cb, 0x7f74ba83, 0xf436121e, 0x7f742637, 0xf42fd079,
+ 0x7f73919d, 0xf4298edc,
+ 0x7f72fcb4, 0xf4234d45, 0x7f72677c, 0xf41d0bb6, 0x7f71d1f6, 0xf416ca2e,
+ 0x7f713c21, 0xf41088ae,
+ 0x7f70a5fe, 0xf40a4735, 0x7f700f8c, 0xf40405c3, 0x7f6f78cb, 0xf3fdc459,
+ 0x7f6ee1bc, 0xf3f782f6,
+ 0x7f6e4a5e, 0xf3f1419a, 0x7f6db2b1, 0xf3eb0046, 0x7f6d1ab6, 0xf3e4bef9,
+ 0x7f6c826d, 0xf3de7db4,
+ 0x7f6be9d4, 0xf3d83c77, 0x7f6b50ed, 0xf3d1fb40, 0x7f6ab7b8, 0xf3cbba12,
+ 0x7f6a1e34, 0xf3c578eb,
+ 0x7f698461, 0xf3bf37cb, 0x7f68ea40, 0xf3b8f6b3, 0x7f684fd0, 0xf3b2b5a3,
+ 0x7f67b512, 0xf3ac749a,
+ 0x7f671a05, 0xf3a63398, 0x7f667ea9, 0xf39ff29f, 0x7f65e2ff, 0xf399b1ad,
+ 0x7f654706, 0xf39370c2,
+ 0x7f64aabf, 0xf38d2fe0, 0x7f640e29, 0xf386ef05, 0x7f637144, 0xf380ae31,
+ 0x7f62d411, 0xf37a6d66,
+ 0x7f62368f, 0xf3742ca2, 0x7f6198bf, 0xf36debe6, 0x7f60faa0, 0xf367ab31,
+ 0x7f605c33, 0xf3616a85,
+ 0x7f5fbd77, 0xf35b29e0, 0x7f5f1e6c, 0xf354e943, 0x7f5e7f13, 0xf34ea8ae,
+ 0x7f5ddf6b, 0xf3486820,
+ 0x7f5d3f75, 0xf342279b, 0x7f5c9f30, 0xf33be71d, 0x7f5bfe9d, 0xf335a6a7,
+ 0x7f5b5dbb, 0xf32f6639,
+ 0x7f5abc8a, 0xf32925d3, 0x7f5a1b0b, 0xf322e575, 0x7f59793e, 0xf31ca51f,
+ 0x7f58d721, 0xf31664d1,
+ 0x7f5834b7, 0xf310248a, 0x7f5791fd, 0xf309e44c, 0x7f56eef5, 0xf303a416,
+ 0x7f564b9f, 0xf2fd63e8,
+ 0x7f55a7fa, 0xf2f723c1, 0x7f550407, 0xf2f0e3a3, 0x7f545fc5, 0xf2eaa38d,
+ 0x7f53bb34, 0xf2e4637f,
+ 0x7f531655, 0xf2de2379, 0x7f527127, 0xf2d7e37b, 0x7f51cbab, 0xf2d1a385,
+ 0x7f5125e0, 0xf2cb6398,
+ 0x7f507fc7, 0xf2c523b2, 0x7f4fd95f, 0xf2bee3d5, 0x7f4f32a9, 0xf2b8a400,
+ 0x7f4e8ba4, 0xf2b26433,
+ 0x7f4de451, 0xf2ac246e, 0x7f4d3caf, 0xf2a5e4b1, 0x7f4c94be, 0xf29fa4fd,
+ 0x7f4bec7f, 0xf2996551,
+ 0x7f4b43f2, 0xf29325ad, 0x7f4a9b16, 0xf28ce612, 0x7f49f1eb, 0xf286a67e,
+ 0x7f494872, 0xf28066f4,
+ 0x7f489eaa, 0xf27a2771, 0x7f47f494, 0xf273e7f7, 0x7f474a30, 0xf26da885,
+ 0x7f469f7d, 0xf267691b,
+ 0x7f45f47b, 0xf26129ba, 0x7f45492b, 0xf25aea61, 0x7f449d8c, 0xf254ab11,
+ 0x7f43f19f, 0xf24e6bc9,
+ 0x7f434563, 0xf2482c8a, 0x7f4298d9, 0xf241ed53, 0x7f41ec01, 0xf23bae24,
+ 0x7f413ed9, 0xf2356efe,
+ 0x7f409164, 0xf22f2fe1, 0x7f3fe3a0, 0xf228f0cc, 0x7f3f358d, 0xf222b1c0,
+ 0x7f3e872c, 0xf21c72bc,
+ 0x7f3dd87c, 0xf21633c0, 0x7f3d297e, 0xf20ff4ce, 0x7f3c7a31, 0xf209b5e4,
+ 0x7f3bca96, 0xf2037702,
+ 0x7f3b1aad, 0xf1fd3829, 0x7f3a6a75, 0xf1f6f959, 0x7f39b9ee, 0xf1f0ba91,
+ 0x7f390919, 0xf1ea7bd2,
+ 0x7f3857f6, 0xf1e43d1c, 0x7f37a684, 0xf1ddfe6f, 0x7f36f4c3, 0xf1d7bfca,
+ 0x7f3642b4, 0xf1d1812e,
+ 0x7f359057, 0xf1cb429a, 0x7f34ddab, 0xf1c50410, 0x7f342ab1, 0xf1bec58e,
+ 0x7f337768, 0xf1b88715,
+ 0x7f32c3d1, 0xf1b248a5, 0x7f320feb, 0xf1ac0a3e, 0x7f315bb7, 0xf1a5cbdf,
+ 0x7f30a734, 0xf19f8d89,
+ 0x7f2ff263, 0xf1994f3d, 0x7f2f3d44, 0xf19310f9, 0x7f2e87d6, 0xf18cd2be,
+ 0x7f2dd219, 0xf186948c,
+ 0x7f2d1c0e, 0xf1805662, 0x7f2c65b5, 0xf17a1842, 0x7f2baf0d, 0xf173da2b,
+ 0x7f2af817, 0xf16d9c1d,
+ 0x7f2a40d2, 0xf1675e17, 0x7f29893f, 0xf161201b, 0x7f28d15d, 0xf15ae228,
+ 0x7f28192d, 0xf154a43d,
+ 0x7f2760af, 0xf14e665c, 0x7f26a7e2, 0xf1482884, 0x7f25eec7, 0xf141eab5,
+ 0x7f25355d, 0xf13bacef,
+ 0x7f247ba5, 0xf1356f32, 0x7f23c19e, 0xf12f317e, 0x7f230749, 0xf128f3d4,
+ 0x7f224ca6, 0xf122b632,
+ 0x7f2191b4, 0xf11c789a, 0x7f20d674, 0xf1163b0b, 0x7f201ae5, 0xf10ffd85,
+ 0x7f1f5f08, 0xf109c009,
+ 0x7f1ea2dc, 0xf1038295, 0x7f1de662, 0xf0fd452b, 0x7f1d299a, 0xf0f707ca,
+ 0x7f1c6c83, 0xf0f0ca72,
+ 0x7f1baf1e, 0xf0ea8d24, 0x7f1af16a, 0xf0e44fdf, 0x7f1a3368, 0xf0de12a3,
+ 0x7f197518, 0xf0d7d571,
+ 0x7f18b679, 0xf0d19848, 0x7f17f78c, 0xf0cb5b28, 0x7f173850, 0xf0c51e12,
+ 0x7f1678c6, 0xf0bee105,
+ 0x7f15b8ee, 0xf0b8a401, 0x7f14f8c7, 0xf0b26707, 0x7f143852, 0xf0ac2a16,
+ 0x7f13778e, 0xf0a5ed2f,
+ 0x7f12b67c, 0xf09fb051, 0x7f11f51c, 0xf099737d, 0x7f11336d, 0xf09336b2,
+ 0x7f107170, 0xf08cf9f1,
+ 0x7f0faf25, 0xf086bd39, 0x7f0eec8b, 0xf080808b, 0x7f0e29a3, 0xf07a43e7,
+ 0x7f0d666c, 0xf074074c,
+ 0x7f0ca2e7, 0xf06dcaba, 0x7f0bdf14, 0xf0678e32, 0x7f0b1af2, 0xf06151b4,
+ 0x7f0a5682, 0xf05b1540,
+ 0x7f0991c4, 0xf054d8d5, 0x7f08ccb7, 0xf04e9c73, 0x7f08075c, 0xf048601c,
+ 0x7f0741b2, 0xf04223ce,
+ 0x7f067bba, 0xf03be78a, 0x7f05b574, 0xf035ab4f, 0x7f04eedf, 0xf02f6f1f,
+ 0x7f0427fc, 0xf02932f8,
+ 0x7f0360cb, 0xf022f6da, 0x7f02994b, 0xf01cbac7, 0x7f01d17d, 0xf0167ebd,
+ 0x7f010961, 0xf01042be,
+ 0x7f0040f6, 0xf00a06c8, 0x7eff783d, 0xf003cadc, 0x7efeaf36, 0xeffd8ef9,
+ 0x7efde5e0, 0xeff75321,
+ 0x7efd1c3c, 0xeff11753, 0x7efc524a, 0xefeadb8e, 0x7efb8809, 0xefe49fd3,
+ 0x7efabd7a, 0xefde6423,
+ 0x7ef9f29d, 0xefd8287c, 0x7ef92771, 0xefd1ecdf, 0x7ef85bf7, 0xefcbb14c,
+ 0x7ef7902f, 0xefc575c3,
+ 0x7ef6c418, 0xefbf3a45, 0x7ef5f7b3, 0xefb8fed0, 0x7ef52b00, 0xefb2c365,
+ 0x7ef45dfe, 0xefac8804,
+ 0x7ef390ae, 0xefa64cae, 0x7ef2c310, 0xefa01161, 0x7ef1f524, 0xef99d61f,
+ 0x7ef126e9, 0xef939ae6,
+ 0x7ef05860, 0xef8d5fb8, 0x7eef8988, 0xef872494, 0x7eeeba62, 0xef80e97a,
+ 0x7eedeaee, 0xef7aae6b,
+ 0x7eed1b2c, 0xef747365, 0x7eec4b1b, 0xef6e386a, 0x7eeb7abc, 0xef67fd79,
+ 0x7eeaaa0f, 0xef61c292,
+ 0x7ee9d914, 0xef5b87b5, 0x7ee907ca, 0xef554ce3, 0x7ee83632, 0xef4f121b,
+ 0x7ee7644c, 0xef48d75d,
+ 0x7ee69217, 0xef429caa, 0x7ee5bf94, 0xef3c6201, 0x7ee4ecc3, 0xef362762,
+ 0x7ee419a3, 0xef2feccd,
+ 0x7ee34636, 0xef29b243, 0x7ee2727a, 0xef2377c4, 0x7ee19e6f, 0xef1d3d4e,
+ 0x7ee0ca17, 0xef1702e4,
+ 0x7edff570, 0xef10c883, 0x7edf207b, 0xef0a8e2d, 0x7ede4b38, 0xef0453e2,
+ 0x7edd75a6, 0xeefe19a1,
+ 0x7edc9fc6, 0xeef7df6a, 0x7edbc998, 0xeef1a53e, 0x7edaf31c, 0xeeeb6b1c,
+ 0x7eda1c51, 0xeee53105,
+ 0x7ed94538, 0xeedef6f9, 0x7ed86dd1, 0xeed8bcf7, 0x7ed7961c, 0xeed28300,
+ 0x7ed6be18, 0xeecc4913,
+ 0x7ed5e5c6, 0xeec60f31, 0x7ed50d26, 0xeebfd55a, 0x7ed43438, 0xeeb99b8d,
+ 0x7ed35afb, 0xeeb361cb,
+ 0x7ed28171, 0xeead2813, 0x7ed1a798, 0xeea6ee66, 0x7ed0cd70, 0xeea0b4c4,
+ 0x7ecff2fb, 0xee9a7b2d,
+ 0x7ecf1837, 0xee9441a0, 0x7ece3d25, 0xee8e081e, 0x7ecd61c5, 0xee87cea7,
+ 0x7ecc8617, 0xee81953b,
+ 0x7ecbaa1a, 0xee7b5bd9, 0x7ecacdd0, 0xee752283, 0x7ec9f137, 0xee6ee937,
+ 0x7ec9144f, 0xee68aff6,
+ 0x7ec8371a, 0xee6276bf, 0x7ec75996, 0xee5c3d94, 0x7ec67bc5, 0xee560473,
+ 0x7ec59da5, 0xee4fcb5e,
+ 0x7ec4bf36, 0xee499253, 0x7ec3e07a, 0xee435953, 0x7ec3016f, 0xee3d205e,
+ 0x7ec22217, 0xee36e775,
+ 0x7ec14270, 0xee30ae96, 0x7ec0627a, 0xee2a75c2, 0x7ebf8237, 0xee243cf9,
+ 0x7ebea1a6, 0xee1e043b,
+ 0x7ebdc0c6, 0xee17cb88, 0x7ebcdf98, 0xee1192e0, 0x7ebbfe1c, 0xee0b5a43,
+ 0x7ebb1c52, 0xee0521b2,
+ 0x7eba3a39, 0xedfee92b, 0x7eb957d2, 0xedf8b0b0, 0x7eb8751e, 0xedf2783f,
+ 0x7eb7921b, 0xedec3fda,
+ 0x7eb6aeca, 0xede60780, 0x7eb5cb2a, 0xeddfcf31, 0x7eb4e73d, 0xedd996ed,
+ 0x7eb40301, 0xedd35eb5,
+ 0x7eb31e78, 0xedcd2687, 0x7eb239a0, 0xedc6ee65, 0x7eb1547a, 0xedc0b64e,
+ 0x7eb06f05, 0xedba7e43,
+ 0x7eaf8943, 0xedb44642, 0x7eaea333, 0xedae0e4d, 0x7eadbcd4, 0xeda7d664,
+ 0x7eacd627, 0xeda19e85,
+ 0x7eabef2c, 0xed9b66b2, 0x7eab07e3, 0xed952eea, 0x7eaa204c, 0xed8ef72e,
+ 0x7ea93867, 0xed88bf7d,
+ 0x7ea85033, 0xed8287d7, 0x7ea767b2, 0xed7c503d, 0x7ea67ee2, 0xed7618ae,
+ 0x7ea595c4, 0xed6fe12b,
+ 0x7ea4ac58, 0xed69a9b3, 0x7ea3c29e, 0xed637246, 0x7ea2d896, 0xed5d3ae5,
+ 0x7ea1ee3f, 0xed570390,
+ 0x7ea1039b, 0xed50cc46, 0x7ea018a8, 0xed4a9507, 0x7e9f2d68, 0xed445dd5,
+ 0x7e9e41d9, 0xed3e26ad,
+ 0x7e9d55fc, 0xed37ef91, 0x7e9c69d1, 0xed31b881, 0x7e9b7d58, 0xed2b817d,
+ 0x7e9a9091, 0xed254a84,
+ 0x7e99a37c, 0xed1f1396, 0x7e98b618, 0xed18dcb5, 0x7e97c867, 0xed12a5df,
+ 0x7e96da67, 0xed0c6f14,
+ 0x7e95ec1a, 0xed063856, 0x7e94fd7e, 0xed0001a3, 0x7e940e94, 0xecf9cafb,
+ 0x7e931f5c, 0xecf39460,
+ 0x7e922fd6, 0xeced5dd0, 0x7e914002, 0xece7274c, 0x7e904fe0, 0xece0f0d4,
+ 0x7e8f5f70, 0xecdaba67,
+ 0x7e8e6eb2, 0xecd48407, 0x7e8d7da6, 0xecce4db2, 0x7e8c8c4b, 0xecc81769,
+ 0x7e8b9aa3, 0xecc1e12c,
+ 0x7e8aa8ac, 0xecbbaafb, 0x7e89b668, 0xecb574d5, 0x7e88c3d5, 0xecaf3ebc,
+ 0x7e87d0f5, 0xeca908ae,
+ 0x7e86ddc6, 0xeca2d2ad, 0x7e85ea49, 0xec9c9cb7, 0x7e84f67e, 0xec9666cd,
+ 0x7e840265, 0xec9030f0,
+ 0x7e830dff, 0xec89fb1e, 0x7e82194a, 0xec83c558, 0x7e812447, 0xec7d8f9e,
+ 0x7e802ef6, 0xec7759f1,
+ 0x7e7f3957, 0xec71244f, 0x7e7e436a, 0xec6aeeba, 0x7e7d4d2f, 0xec64b930,
+ 0x7e7c56a5, 0xec5e83b3,
+ 0x7e7b5fce, 0xec584e41, 0x7e7a68a9, 0xec5218dc, 0x7e797136, 0xec4be383,
+ 0x7e787975, 0xec45ae36,
+ 0x7e778166, 0xec3f78f6, 0x7e768908, 0xec3943c1, 0x7e75905d, 0xec330e99,
+ 0x7e749764, 0xec2cd97d,
+ 0x7e739e1d, 0xec26a46d, 0x7e72a488, 0xec206f69, 0x7e71aaa4, 0xec1a3a72,
+ 0x7e70b073, 0xec140587,
+ 0x7e6fb5f4, 0xec0dd0a8, 0x7e6ebb27, 0xec079bd6, 0x7e6dc00c, 0xec01670f,
+ 0x7e6cc4a2, 0xebfb3256,
+ 0x7e6bc8eb, 0xebf4fda8, 0x7e6acce6, 0xebeec907, 0x7e69d093, 0xebe89472,
+ 0x7e68d3f2, 0xebe25fea,
+ 0x7e67d703, 0xebdc2b6e, 0x7e66d9c6, 0xebd5f6fe, 0x7e65dc3b, 0xebcfc29b,
+ 0x7e64de62, 0xebc98e45,
+ 0x7e63e03b, 0xebc359fb, 0x7e62e1c6, 0xebbd25bd, 0x7e61e303, 0xebb6f18c,
+ 0x7e60e3f2, 0xebb0bd67,
+ 0x7e5fe493, 0xebaa894f, 0x7e5ee4e6, 0xeba45543, 0x7e5de4ec, 0xeb9e2144,
+ 0x7e5ce4a3, 0xeb97ed52,
+ 0x7e5be40c, 0xeb91b96c, 0x7e5ae328, 0xeb8b8593, 0x7e59e1f5, 0xeb8551c6,
+ 0x7e58e075, 0xeb7f1e06,
+ 0x7e57dea7, 0xeb78ea52, 0x7e56dc8a, 0xeb72b6ac, 0x7e55da20, 0xeb6c8312,
+ 0x7e54d768, 0xeb664f84,
+ 0x7e53d462, 0xeb601c04, 0x7e52d10e, 0xeb59e890, 0x7e51cd6c, 0xeb53b529,
+ 0x7e50c97c, 0xeb4d81ce,
+ 0x7e4fc53e, 0xeb474e81, 0x7e4ec0b2, 0xeb411b40, 0x7e4dbbd9, 0xeb3ae80c,
+ 0x7e4cb6b1, 0xeb34b4e4,
+ 0x7e4bb13c, 0xeb2e81ca, 0x7e4aab78, 0xeb284ebc, 0x7e49a567, 0xeb221bbb,
+ 0x7e489f08, 0xeb1be8c8,
+ 0x7e47985b, 0xeb15b5e1, 0x7e469160, 0xeb0f8307, 0x7e458a17, 0xeb095039,
+ 0x7e448281, 0xeb031d79,
+ 0x7e437a9c, 0xeafceac6, 0x7e427269, 0xeaf6b81f, 0x7e4169e9, 0xeaf08586,
+ 0x7e40611b, 0xeaea52fa,
+ 0x7e3f57ff, 0xeae4207a, 0x7e3e4e95, 0xeaddee08, 0x7e3d44dd, 0xead7bba3,
+ 0x7e3c3ad7, 0xead1894b,
+ 0x7e3b3083, 0xeacb56ff, 0x7e3a25e2, 0xeac524c1, 0x7e391af3, 0xeabef290,
+ 0x7e380fb5, 0xeab8c06c,
+ 0x7e37042a, 0xeab28e56, 0x7e35f851, 0xeaac5c4c, 0x7e34ec2b, 0xeaa62a4f,
+ 0x7e33dfb6, 0xea9ff860,
+ 0x7e32d2f4, 0xea99c67e, 0x7e31c5e3, 0xea9394a9, 0x7e30b885, 0xea8d62e1,
+ 0x7e2faad9, 0xea873127,
+ 0x7e2e9cdf, 0xea80ff7a, 0x7e2d8e97, 0xea7acdda, 0x7e2c8002, 0xea749c47,
+ 0x7e2b711f, 0xea6e6ac2,
+ 0x7e2a61ed, 0xea683949, 0x7e29526e, 0xea6207df, 0x7e2842a2, 0xea5bd681,
+ 0x7e273287, 0xea55a531,
+ 0x7e26221f, 0xea4f73ee, 0x7e251168, 0xea4942b9, 0x7e240064, 0xea431191,
+ 0x7e22ef12, 0xea3ce077,
+ 0x7e21dd73, 0xea36af69, 0x7e20cb85, 0xea307e6a, 0x7e1fb94a, 0xea2a4d78,
+ 0x7e1ea6c1, 0xea241c93,
+ 0x7e1d93ea, 0xea1debbb, 0x7e1c80c5, 0xea17baf2, 0x7e1b6d53, 0xea118a35,
+ 0x7e1a5992, 0xea0b5987,
+ 0x7e194584, 0xea0528e5, 0x7e183128, 0xe9fef852, 0x7e171c7f, 0xe9f8c7cc,
+ 0x7e160787, 0xe9f29753,
+ 0x7e14f242, 0xe9ec66e8, 0x7e13dcaf, 0xe9e6368b, 0x7e12c6ce, 0xe9e0063c,
+ 0x7e11b0a0, 0xe9d9d5fa,
+ 0x7e109a24, 0xe9d3a5c5, 0x7e0f835a, 0xe9cd759f, 0x7e0e6c42, 0xe9c74586,
+ 0x7e0d54dc, 0xe9c1157a,
+ 0x7e0c3d29, 0xe9bae57d, 0x7e0b2528, 0xe9b4b58d, 0x7e0a0cd9, 0xe9ae85ab,
+ 0x7e08f43d, 0xe9a855d7,
+ 0x7e07db52, 0xe9a22610, 0x7e06c21a, 0xe99bf658, 0x7e05a894, 0xe995c6ad,
+ 0x7e048ec1, 0xe98f9710,
+ 0x7e0374a0, 0xe9896781, 0x7e025a31, 0xe98337ff, 0x7e013f74, 0xe97d088c,
+ 0x7e00246a, 0xe976d926,
+ 0x7dff0911, 0xe970a9ce, 0x7dfded6c, 0xe96a7a85, 0x7dfcd178, 0xe9644b49,
+ 0x7dfbb537, 0xe95e1c1b,
+ 0x7dfa98a8, 0xe957ecfb, 0x7df97bcb, 0xe951bde9, 0x7df85ea0, 0xe94b8ee5,
+ 0x7df74128, 0xe9455fef,
+ 0x7df62362, 0xe93f3107, 0x7df5054f, 0xe939022d, 0x7df3e6ee, 0xe932d361,
+ 0x7df2c83f, 0xe92ca4a4,
+ 0x7df1a942, 0xe92675f4, 0x7df089f8, 0xe9204752, 0x7def6a60, 0xe91a18bf,
+ 0x7dee4a7a, 0xe913ea39,
+ 0x7ded2a47, 0xe90dbbc2, 0x7dec09c6, 0xe9078d59, 0x7deae8f7, 0xe9015efe,
+ 0x7de9c7da, 0xe8fb30b1,
+ 0x7de8a670, 0xe8f50273, 0x7de784b9, 0xe8eed443, 0x7de662b3, 0xe8e8a621,
+ 0x7de54060, 0xe8e2780d,
+ 0x7de41dc0, 0xe8dc4a07, 0x7de2fad1, 0xe8d61c10, 0x7de1d795, 0xe8cfee27,
+ 0x7de0b40b, 0xe8c9c04c,
+ 0x7ddf9034, 0xe8c39280, 0x7dde6c0f, 0xe8bd64c2, 0x7ddd479d, 0xe8b73712,
+ 0x7ddc22dc, 0xe8b10971,
+ 0x7ddafdce, 0xe8aadbde, 0x7dd9d873, 0xe8a4ae59, 0x7dd8b2ca, 0xe89e80e3,
+ 0x7dd78cd3, 0xe898537b,
+ 0x7dd6668f, 0xe8922622, 0x7dd53ffc, 0xe88bf8d7, 0x7dd4191d, 0xe885cb9a,
+ 0x7dd2f1f0, 0xe87f9e6c,
+ 0x7dd1ca75, 0xe879714d, 0x7dd0a2ac, 0xe873443c, 0x7dcf7a96, 0xe86d173a,
+ 0x7dce5232, 0xe866ea46,
+ 0x7dcd2981, 0xe860bd61, 0x7dcc0082, 0xe85a908a, 0x7dcad736, 0xe85463c2,
+ 0x7dc9ad9c, 0xe84e3708,
+ 0x7dc883b4, 0xe8480a5d, 0x7dc7597f, 0xe841ddc1, 0x7dc62efc, 0xe83bb133,
+ 0x7dc5042b, 0xe83584b4,
+ 0x7dc3d90d, 0xe82f5844, 0x7dc2ada2, 0xe8292be3, 0x7dc181e8, 0xe822ff90,
+ 0x7dc055e2, 0xe81cd34b,
+ 0x7dbf298d, 0xe816a716, 0x7dbdfceb, 0xe8107aef, 0x7dbccffc, 0xe80a4ed7,
+ 0x7dbba2bf, 0xe80422ce,
+ 0x7dba7534, 0xe7fdf6d4, 0x7db9475c, 0xe7f7cae8, 0x7db81936, 0xe7f19f0c,
+ 0x7db6eac3, 0xe7eb733e,
+ 0x7db5bc02, 0xe7e5477f, 0x7db48cf4, 0xe7df1bcf, 0x7db35d98, 0xe7d8f02d,
+ 0x7db22def, 0xe7d2c49b,
+ 0x7db0fdf8, 0xe7cc9917, 0x7dafcdb3, 0xe7c66da3, 0x7dae9d21, 0xe7c0423d,
+ 0x7dad6c42, 0xe7ba16e7,
+ 0x7dac3b15, 0xe7b3eb9f, 0x7dab099a, 0xe7adc066, 0x7da9d7d2, 0xe7a7953d,
+ 0x7da8a5bc, 0xe7a16a22,
+ 0x7da77359, 0xe79b3f16, 0x7da640a9, 0xe795141a, 0x7da50dab, 0xe78ee92c,
+ 0x7da3da5f, 0xe788be4e,
+ 0x7da2a6c6, 0xe782937e, 0x7da172df, 0xe77c68be, 0x7da03eab, 0xe7763e0d,
+ 0x7d9f0a29, 0xe770136b,
+ 0x7d9dd55a, 0xe769e8d8, 0x7d9ca03e, 0xe763be55, 0x7d9b6ad3, 0xe75d93e0,
+ 0x7d9a351c, 0xe757697b,
+ 0x7d98ff17, 0xe7513f25, 0x7d97c8c4, 0xe74b14de, 0x7d969224, 0xe744eaa6,
+ 0x7d955b37, 0xe73ec07e,
+ 0x7d9423fc, 0xe7389665, 0x7d92ec73, 0xe7326c5b, 0x7d91b49e, 0xe72c4260,
+ 0x7d907c7a, 0xe7261875,
+ 0x7d8f4409, 0xe71fee99, 0x7d8e0b4b, 0xe719c4cd, 0x7d8cd240, 0xe7139b10,
+ 0x7d8b98e6, 0xe70d7162,
+ 0x7d8a5f40, 0xe70747c4, 0x7d89254c, 0xe7011e35, 0x7d87eb0a, 0xe6faf4b5,
+ 0x7d86b07c, 0xe6f4cb45,
+ 0x7d85759f, 0xe6eea1e4, 0x7d843a76, 0xe6e87893, 0x7d82fefe, 0xe6e24f51,
+ 0x7d81c33a, 0xe6dc261f,
+ 0x7d808728, 0xe6d5fcfc, 0x7d7f4ac8, 0xe6cfd3e9, 0x7d7e0e1c, 0xe6c9aae5,
+ 0x7d7cd121, 0xe6c381f1,
+ 0x7d7b93da, 0xe6bd590d, 0x7d7a5645, 0xe6b73038, 0x7d791862, 0xe6b10772,
+ 0x7d77da32, 0xe6aadebc,
+ 0x7d769bb5, 0xe6a4b616, 0x7d755cea, 0xe69e8d80, 0x7d741dd2, 0xe69864f9,
+ 0x7d72de6d, 0xe6923c82,
+ 0x7d719eba, 0xe68c141a, 0x7d705eba, 0xe685ebc2, 0x7d6f1e6c, 0xe67fc37a,
+ 0x7d6dddd2, 0xe6799b42,
+ 0x7d6c9ce9, 0xe6737319, 0x7d6b5bb4, 0xe66d4b01, 0x7d6a1a31, 0xe66722f7,
+ 0x7d68d860, 0xe660fafe,
+ 0x7d679642, 0xe65ad315, 0x7d6653d7, 0xe654ab3b, 0x7d65111f, 0xe64e8371,
+ 0x7d63ce19, 0xe6485bb7,
+ 0x7d628ac6, 0xe642340d, 0x7d614725, 0xe63c0c73, 0x7d600338, 0xe635e4e9,
+ 0x7d5ebefc, 0xe62fbd6e,
+ 0x7d5d7a74, 0xe6299604, 0x7d5c359e, 0xe6236ea9, 0x7d5af07b, 0xe61d475e,
+ 0x7d59ab0a, 0xe6172024,
+ 0x7d58654d, 0xe610f8f9, 0x7d571f41, 0xe60ad1de, 0x7d55d8e9, 0xe604aad4,
+ 0x7d549243, 0xe5fe83d9,
+ 0x7d534b50, 0xe5f85cef, 0x7d520410, 0xe5f23614, 0x7d50bc82, 0xe5ec0f4a,
+ 0x7d4f74a7, 0xe5e5e88f,
+ 0x7d4e2c7f, 0xe5dfc1e5, 0x7d4ce409, 0xe5d99b4b, 0x7d4b9b46, 0xe5d374c1,
+ 0x7d4a5236, 0xe5cd4e47,
+ 0x7d4908d9, 0xe5c727dd, 0x7d47bf2e, 0xe5c10184, 0x7d467536, 0xe5badb3a,
+ 0x7d452af1, 0xe5b4b501,
+ 0x7d43e05e, 0xe5ae8ed8, 0x7d42957e, 0xe5a868bf, 0x7d414a51, 0xe5a242b7,
+ 0x7d3ffed7, 0xe59c1cbf,
+ 0x7d3eb30f, 0xe595f6d7, 0x7d3d66fa, 0xe58fd0ff, 0x7d3c1a98, 0xe589ab38,
+ 0x7d3acde9, 0xe5838581,
+ 0x7d3980ec, 0xe57d5fda, 0x7d3833a2, 0xe5773a44, 0x7d36e60b, 0xe57114be,
+ 0x7d359827, 0xe56aef49,
+ 0x7d3449f5, 0xe564c9e3, 0x7d32fb76, 0xe55ea48f, 0x7d31acaa, 0xe5587f4a,
+ 0x7d305d91, 0xe5525a17,
+ 0x7d2f0e2b, 0xe54c34f3, 0x7d2dbe77, 0xe5460fe0, 0x7d2c6e76, 0xe53feade,
+ 0x7d2b1e28, 0xe539c5ec,
+ 0x7d29cd8c, 0xe533a10a, 0x7d287ca4, 0xe52d7c39, 0x7d272b6e, 0xe5275779,
+ 0x7d25d9eb, 0xe52132c9,
+ 0x7d24881b, 0xe51b0e2a, 0x7d2335fe, 0xe514e99b, 0x7d21e393, 0xe50ec51d,
+ 0x7d2090db, 0xe508a0b0,
+ 0x7d1f3dd6, 0xe5027c53, 0x7d1dea84, 0xe4fc5807, 0x7d1c96e5, 0xe4f633cc,
+ 0x7d1b42f9, 0xe4f00fa1,
+ 0x7d19eebf, 0xe4e9eb87, 0x7d189a38, 0xe4e3c77d, 0x7d174564, 0xe4dda385,
+ 0x7d15f043, 0xe4d77f9d,
+ 0x7d149ad5, 0xe4d15bc6, 0x7d134519, 0xe4cb37ff, 0x7d11ef11, 0xe4c5144a,
+ 0x7d1098bb, 0xe4bef0a5,
+ 0x7d0f4218, 0xe4b8cd11, 0x7d0deb28, 0xe4b2a98e, 0x7d0c93eb, 0xe4ac861b,
+ 0x7d0b3c60, 0xe4a662ba,
+ 0x7d09e489, 0xe4a03f69, 0x7d088c64, 0xe49a1c29, 0x7d0733f3, 0xe493f8fb,
+ 0x7d05db34, 0xe48dd5dd,
+ 0x7d048228, 0xe487b2d0, 0x7d0328cf, 0xe4818fd4, 0x7d01cf29, 0xe47b6ce9,
+ 0x7d007535, 0xe4754a0e,
+ 0x7cff1af5, 0xe46f2745, 0x7cfdc068, 0xe469048d, 0x7cfc658d, 0xe462e1e6,
+ 0x7cfb0a65, 0xe45cbf50,
+ 0x7cf9aef0, 0xe4569ccb, 0x7cf8532f, 0xe4507a57, 0x7cf6f720, 0xe44a57f4,
+ 0x7cf59ac4, 0xe44435a2,
+ 0x7cf43e1a, 0xe43e1362, 0x7cf2e124, 0xe437f132, 0x7cf183e1, 0xe431cf14,
+ 0x7cf02651, 0xe42bad07,
+ 0x7ceec873, 0xe4258b0a, 0x7ced6a49, 0xe41f6920, 0x7cec0bd1, 0xe4194746,
+ 0x7ceaad0c, 0xe413257d,
+ 0x7ce94dfb, 0xe40d03c6, 0x7ce7ee9c, 0xe406e220, 0x7ce68ef0, 0xe400c08b,
+ 0x7ce52ef7, 0xe3fa9f08,
+ 0x7ce3ceb2, 0xe3f47d96, 0x7ce26e1f, 0xe3ee5c35, 0x7ce10d3f, 0xe3e83ae5,
+ 0x7cdfac12, 0xe3e219a7,
+ 0x7cde4a98, 0xe3dbf87a, 0x7cdce8d1, 0xe3d5d75e, 0x7cdb86bd, 0xe3cfb654,
+ 0x7cda245c, 0xe3c9955b,
+ 0x7cd8c1ae, 0xe3c37474, 0x7cd75eb3, 0xe3bd539e, 0x7cd5fb6a, 0xe3b732d9,
+ 0x7cd497d5, 0xe3b11226,
+ 0x7cd333f3, 0xe3aaf184, 0x7cd1cfc4, 0xe3a4d0f4, 0x7cd06b48, 0xe39eb075,
+ 0x7ccf067f, 0xe3989008,
+ 0x7ccda169, 0xe3926fad, 0x7ccc3c06, 0xe38c4f63, 0x7ccad656, 0xe3862f2a,
+ 0x7cc97059, 0xe3800f03,
+ 0x7cc80a0f, 0xe379eeed, 0x7cc6a378, 0xe373ceea, 0x7cc53c94, 0xe36daef7,
+ 0x7cc3d563, 0xe3678f17,
+ 0x7cc26de5, 0xe3616f48, 0x7cc1061a, 0xe35b4f8b, 0x7cbf9e03, 0xe3552fdf,
+ 0x7cbe359e, 0xe34f1045,
+ 0x7cbcccec, 0xe348f0bd, 0x7cbb63ee, 0xe342d146, 0x7cb9faa2, 0xe33cb1e1,
+ 0x7cb8910a, 0xe336928e,
+ 0x7cb72724, 0xe330734d, 0x7cb5bcf2, 0xe32a541d, 0x7cb45272, 0xe3243500,
+ 0x7cb2e7a6, 0xe31e15f4,
+ 0x7cb17c8d, 0xe317f6fa, 0x7cb01127, 0xe311d811, 0x7caea574, 0xe30bb93b,
+ 0x7cad3974, 0xe3059a76,
+ 0x7cabcd28, 0xe2ff7bc3, 0x7caa608e, 0xe2f95d23, 0x7ca8f3a7, 0xe2f33e94,
+ 0x7ca78674, 0xe2ed2017,
+ 0x7ca618f3, 0xe2e701ac, 0x7ca4ab26, 0xe2e0e352, 0x7ca33d0c, 0xe2dac50b,
+ 0x7ca1cea5, 0xe2d4a6d6,
+ 0x7ca05ff1, 0xe2ce88b3, 0x7c9ef0f0, 0xe2c86aa2, 0x7c9d81a3, 0xe2c24ca2,
+ 0x7c9c1208, 0xe2bc2eb5,
+ 0x7c9aa221, 0xe2b610da, 0x7c9931ec, 0xe2aff311, 0x7c97c16b, 0xe2a9d55a,
+ 0x7c96509d, 0xe2a3b7b5,
+ 0x7c94df83, 0xe29d9a23, 0x7c936e1b, 0xe2977ca2, 0x7c91fc66, 0xe2915f34,
+ 0x7c908a65, 0xe28b41d7,
+ 0x7c8f1817, 0xe285248d, 0x7c8da57c, 0xe27f0755, 0x7c8c3294, 0xe278ea30,
+ 0x7c8abf5f, 0xe272cd1c,
+ 0x7c894bde, 0xe26cb01b, 0x7c87d810, 0xe266932c, 0x7c8663f4, 0xe260764f,
+ 0x7c84ef8c, 0xe25a5984,
+ 0x7c837ad8, 0xe2543ccc, 0x7c8205d6, 0xe24e2026, 0x7c809088, 0xe2480393,
+ 0x7c7f1aed, 0xe241e711,
+ 0x7c7da505, 0xe23bcaa2, 0x7c7c2ed0, 0xe235ae46, 0x7c7ab84e, 0xe22f91fc,
+ 0x7c794180, 0xe22975c4,
+ 0x7c77ca65, 0xe223599e, 0x7c7652fd, 0xe21d3d8b, 0x7c74db48, 0xe217218b,
+ 0x7c736347, 0xe211059d,
+ 0x7c71eaf9, 0xe20ae9c1, 0x7c70725e, 0xe204cdf8, 0x7c6ef976, 0xe1feb241,
+ 0x7c6d8041, 0xe1f8969d,
+ 0x7c6c06c0, 0xe1f27b0b, 0x7c6a8cf2, 0xe1ec5f8c, 0x7c6912d7, 0xe1e64420,
+ 0x7c679870, 0xe1e028c6,
+ 0x7c661dbc, 0xe1da0d7e, 0x7c64a2bb, 0xe1d3f24a, 0x7c63276d, 0xe1cdd727,
+ 0x7c61abd3, 0xe1c7bc18,
+ 0x7c602fec, 0xe1c1a11b, 0x7c5eb3b8, 0xe1bb8631, 0x7c5d3737, 0xe1b56b59,
+ 0x7c5bba6a, 0xe1af5094,
+ 0x7c5a3d50, 0xe1a935e2, 0x7c58bfe9, 0xe1a31b42, 0x7c574236, 0xe19d00b6,
+ 0x7c55c436, 0xe196e63c,
+ 0x7c5445e9, 0xe190cbd4, 0x7c52c74f, 0xe18ab180, 0x7c514869, 0xe184973e,
+ 0x7c4fc936, 0xe17e7d0f,
+ 0x7c4e49b7, 0xe17862f3, 0x7c4cc9ea, 0xe17248ea, 0x7c4b49d2, 0xe16c2ef4,
+ 0x7c49c96c, 0xe1661510,
+ 0x7c4848ba, 0xe15ffb3f, 0x7c46c7bb, 0xe159e182, 0x7c45466f, 0xe153c7d7,
+ 0x7c43c4d7, 0xe14dae3f,
+ 0x7c4242f2, 0xe14794ba, 0x7c40c0c1, 0xe1417b48, 0x7c3f3e42, 0xe13b61e9,
+ 0x7c3dbb78, 0xe135489d,
+ 0x7c3c3860, 0xe12f2f63, 0x7c3ab4fc, 0xe129163d, 0x7c39314b, 0xe122fd2a,
+ 0x7c37ad4e, 0xe11ce42a,
+ 0x7c362904, 0xe116cb3d, 0x7c34a46d, 0xe110b263, 0x7c331f8a, 0xe10a999c,
+ 0x7c319a5a, 0xe10480e9,
+ 0x7c3014de, 0xe0fe6848, 0x7c2e8f15, 0xe0f84fbb, 0x7c2d08ff, 0xe0f23740,
+ 0x7c2b829d, 0xe0ec1ed9,
+ 0x7c29fbee, 0xe0e60685, 0x7c2874f3, 0xe0dfee44, 0x7c26edab, 0xe0d9d616,
+ 0x7c256616, 0xe0d3bdfc,
+ 0x7c23de35, 0xe0cda5f5, 0x7c225607, 0xe0c78e01, 0x7c20cd8d, 0xe0c17620,
+ 0x7c1f44c6, 0xe0bb5e53,
+ 0x7c1dbbb3, 0xe0b54698, 0x7c1c3253, 0xe0af2ef2, 0x7c1aa8a6, 0xe0a9175e,
+ 0x7c191ead, 0xe0a2ffde,
+ 0x7c179467, 0xe09ce871, 0x7c1609d5, 0xe096d117, 0x7c147ef6, 0xe090b9d1,
+ 0x7c12f3cb, 0xe08aa29f,
+ 0x7c116853, 0xe0848b7f, 0x7c0fdc8f, 0xe07e7473, 0x7c0e507e, 0xe0785d7b,
+ 0x7c0cc421, 0xe0724696,
+ 0x7c0b3777, 0xe06c2fc4, 0x7c09aa80, 0xe0661906, 0x7c081d3d, 0xe060025c,
+ 0x7c068fae, 0xe059ebc5,
+ 0x7c0501d2, 0xe053d541, 0x7c0373a9, 0xe04dbed1, 0x7c01e534, 0xe047a875,
+ 0x7c005673, 0xe041922c,
+ 0x7bfec765, 0xe03b7bf6, 0x7bfd380a, 0xe03565d5, 0x7bfba863, 0xe02f4fc6,
+ 0x7bfa1870, 0xe02939cc,
+ 0x7bf88830, 0xe02323e5, 0x7bf6f7a4, 0xe01d0e12, 0x7bf566cb, 0xe016f852,
+ 0x7bf3d5a6, 0xe010e2a7,
+ 0x7bf24434, 0xe00acd0e, 0x7bf0b276, 0xe004b78a, 0x7bef206b, 0xdffea219,
+ 0x7bed8e14, 0xdff88cbc,
+ 0x7bebfb70, 0xdff27773, 0x7bea6880, 0xdfec623e, 0x7be8d544, 0xdfe64d1c,
+ 0x7be741bb, 0xdfe0380e,
+ 0x7be5ade6, 0xdfda2314, 0x7be419c4, 0xdfd40e2e, 0x7be28556, 0xdfcdf95c,
+ 0x7be0f09b, 0xdfc7e49d,
+ 0x7bdf5b94, 0xdfc1cff3, 0x7bddc641, 0xdfbbbb5c, 0x7bdc30a1, 0xdfb5a6d9,
+ 0x7bda9ab5, 0xdfaf926a,
+ 0x7bd9047c, 0xdfa97e0f, 0x7bd76df7, 0xdfa369c8, 0x7bd5d726, 0xdf9d5595,
+ 0x7bd44008, 0xdf974176,
+ 0x7bd2a89e, 0xdf912d6b, 0x7bd110e8, 0xdf8b1974, 0x7bcf78e5, 0xdf850591,
+ 0x7bcde095, 0xdf7ef1c2,
+ 0x7bcc47fa, 0xdf78de07, 0x7bcaaf12, 0xdf72ca60, 0x7bc915dd, 0xdf6cb6cd,
+ 0x7bc77c5d, 0xdf66a34e,
+ 0x7bc5e290, 0xdf608fe4, 0x7bc44876, 0xdf5a7c8d, 0x7bc2ae10, 0xdf54694b,
+ 0x7bc1135e, 0xdf4e561c,
+ 0x7bbf7860, 0xdf484302, 0x7bbddd15, 0xdf422ffd, 0x7bbc417e, 0xdf3c1d0b,
+ 0x7bbaa59a, 0xdf360a2d,
+ 0x7bb9096b, 0xdf2ff764, 0x7bb76cef, 0xdf29e4af, 0x7bb5d026, 0xdf23d20e,
+ 0x7bb43311, 0xdf1dbf82,
+ 0x7bb295b0, 0xdf17ad0a, 0x7bb0f803, 0xdf119aa6, 0x7baf5a09, 0xdf0b8856,
+ 0x7badbbc3, 0xdf05761b,
+ 0x7bac1d31, 0xdeff63f4, 0x7baa7e53, 0xdef951e2, 0x7ba8df28, 0xdef33fe3,
+ 0x7ba73fb1, 0xdeed2dfa,
+ 0x7ba59fee, 0xdee71c24, 0x7ba3ffde, 0xdee10a63, 0x7ba25f82, 0xdedaf8b7,
+ 0x7ba0beda, 0xded4e71f,
+ 0x7b9f1de6, 0xdeced59b, 0x7b9d7ca5, 0xdec8c42c, 0x7b9bdb18, 0xdec2b2d1,
+ 0x7b9a393f, 0xdebca18b,
+ 0x7b989719, 0xdeb69059, 0x7b96f4a8, 0xdeb07f3c, 0x7b9551ea, 0xdeaa6e34,
+ 0x7b93aee0, 0xdea45d40,
+ 0x7b920b89, 0xde9e4c60, 0x7b9067e7, 0xde983b95, 0x7b8ec3f8, 0xde922adf,
+ 0x7b8d1fbd, 0xde8c1a3e,
+ 0x7b8b7b36, 0xde8609b1, 0x7b89d662, 0xde7ff938, 0x7b883143, 0xde79e8d5,
+ 0x7b868bd7, 0xde73d886,
+ 0x7b84e61f, 0xde6dc84b, 0x7b83401b, 0xde67b826, 0x7b8199ca, 0xde61a815,
+ 0x7b7ff32e, 0xde5b9819,
+ 0x7b7e4c45, 0xde558831, 0x7b7ca510, 0xde4f785f, 0x7b7afd8f, 0xde4968a1,
+ 0x7b7955c2, 0xde4358f8,
+ 0x7b77ada8, 0xde3d4964, 0x7b760542, 0xde3739e4, 0x7b745c91, 0xde312a7a,
+ 0x7b72b393, 0xde2b1b24,
+ 0x7b710a49, 0xde250be3, 0x7b6f60b2, 0xde1efcb7, 0x7b6db6d0, 0xde18eda0,
+ 0x7b6c0ca2, 0xde12de9e,
+ 0x7b6a6227, 0xde0ccfb1, 0x7b68b760, 0xde06c0d9, 0x7b670c4d, 0xde00b216,
+ 0x7b6560ee, 0xddfaa367,
+ 0x7b63b543, 0xddf494ce, 0x7b62094c, 0xddee8649, 0x7b605d09, 0xdde877da,
+ 0x7b5eb079, 0xdde26980,
+ 0x7b5d039e, 0xdddc5b3b, 0x7b5b5676, 0xddd64d0a, 0x7b59a902, 0xddd03eef,
+ 0x7b57fb42, 0xddca30e9,
+ 0x7b564d36, 0xddc422f8, 0x7b549ede, 0xddbe151d, 0x7b52f03a, 0xddb80756,
+ 0x7b51414a, 0xddb1f9a4,
+ 0x7b4f920e, 0xddabec08, 0x7b4de286, 0xdda5de81, 0x7b4c32b1, 0xdd9fd10f,
+ 0x7b4a8291, 0xdd99c3b2,
+ 0x7b48d225, 0xdd93b66a, 0x7b47216c, 0xdd8da938, 0x7b457068, 0xdd879c1b,
+ 0x7b43bf17, 0xdd818f13,
+ 0x7b420d7a, 0xdd7b8220, 0x7b405b92, 0xdd757543, 0x7b3ea95d, 0xdd6f687b,
+ 0x7b3cf6dc, 0xdd695bc9,
+ 0x7b3b4410, 0xdd634f2b, 0x7b3990f7, 0xdd5d42a3, 0x7b37dd92, 0xdd573631,
+ 0x7b3629e1, 0xdd5129d4,
+ 0x7b3475e5, 0xdd4b1d8c, 0x7b32c19c, 0xdd451159, 0x7b310d07, 0xdd3f053c,
+ 0x7b2f5826, 0xdd38f935,
+ 0x7b2da2fa, 0xdd32ed43, 0x7b2bed81, 0xdd2ce166, 0x7b2a37bc, 0xdd26d59f,
+ 0x7b2881ac, 0xdd20c9ed,
+ 0x7b26cb4f, 0xdd1abe51, 0x7b2514a6, 0xdd14b2ca, 0x7b235db2, 0xdd0ea759,
+ 0x7b21a671, 0xdd089bfe,
+ 0x7b1feee5, 0xdd0290b8, 0x7b1e370d, 0xdcfc8588, 0x7b1c7ee8, 0xdcf67a6d,
+ 0x7b1ac678, 0xdcf06f68,
+ 0x7b190dbc, 0xdcea6478, 0x7b1754b3, 0xdce4599e, 0x7b159b5f, 0xdcde4eda,
+ 0x7b13e1bf, 0xdcd8442b,
+ 0x7b1227d3, 0xdcd23993, 0x7b106d9b, 0xdccc2f0f, 0x7b0eb318, 0xdcc624a2,
+ 0x7b0cf848, 0xdcc01a4a,
+ 0x7b0b3d2c, 0xdcba1008, 0x7b0981c5, 0xdcb405dc, 0x7b07c612, 0xdcadfbc5,
+ 0x7b060a12, 0xdca7f1c5,
+ 0x7b044dc7, 0xdca1e7da, 0x7b029130, 0xdc9bde05, 0x7b00d44d, 0xdc95d446,
+ 0x7aff171e, 0xdc8fca9c,
+ 0x7afd59a4, 0xdc89c109, 0x7afb9bdd, 0xdc83b78b, 0x7af9ddcb, 0xdc7dae23,
+ 0x7af81f6c, 0xdc77a4d2,
+ 0x7af660c2, 0xdc719b96, 0x7af4a1cc, 0xdc6b9270, 0x7af2e28b, 0xdc658960,
+ 0x7af122fd, 0xdc5f8066,
+ 0x7aef6323, 0xdc597781, 0x7aeda2fe, 0xdc536eb3, 0x7aebe28d, 0xdc4d65fb,
+ 0x7aea21d0, 0xdc475d59,
+ 0x7ae860c7, 0xdc4154cd, 0x7ae69f73, 0xdc3b4c57, 0x7ae4ddd2, 0xdc3543f7,
+ 0x7ae31be6, 0xdc2f3bad,
+ 0x7ae159ae, 0xdc293379, 0x7adf972a, 0xdc232b5c, 0x7addd45b, 0xdc1d2354,
+ 0x7adc113f, 0xdc171b63,
+ 0x7ada4dd8, 0xdc111388, 0x7ad88a25, 0xdc0b0bc2, 0x7ad6c626, 0xdc050414,
+ 0x7ad501dc, 0xdbfefc7b,
+ 0x7ad33d45, 0xdbf8f4f8, 0x7ad17863, 0xdbf2ed8c, 0x7acfb336, 0xdbece636,
+ 0x7acdedbc, 0xdbe6def6,
+ 0x7acc27f7, 0xdbe0d7cd, 0x7aca61e6, 0xdbdad0b9, 0x7ac89b89, 0xdbd4c9bc,
+ 0x7ac6d4e0, 0xdbcec2d6,
+ 0x7ac50dec, 0xdbc8bc06, 0x7ac346ac, 0xdbc2b54c, 0x7ac17f20, 0xdbbcaea8,
+ 0x7abfb749, 0xdbb6a81b,
+ 0x7abdef25, 0xdbb0a1a4, 0x7abc26b7, 0xdbaa9b43, 0x7aba5dfc, 0xdba494f9,
+ 0x7ab894f6, 0xdb9e8ec6,
+ 0x7ab6cba4, 0xdb9888a8, 0x7ab50206, 0xdb9282a2, 0x7ab3381d, 0xdb8c7cb1,
+ 0x7ab16de7, 0xdb8676d8,
+ 0x7aafa367, 0xdb807114, 0x7aadd89a, 0xdb7a6b68, 0x7aac0d82, 0xdb7465d1,
+ 0x7aaa421e, 0xdb6e6052,
+ 0x7aa8766f, 0xdb685ae9, 0x7aa6aa74, 0xdb625596, 0x7aa4de2d, 0xdb5c505a,
+ 0x7aa3119a, 0xdb564b35,
+ 0x7aa144bc, 0xdb504626, 0x7a9f7793, 0xdb4a412e, 0x7a9daa1d, 0xdb443c4c,
+ 0x7a9bdc5c, 0xdb3e3781,
+ 0x7a9a0e50, 0xdb3832cd, 0x7a983ff7, 0xdb322e30, 0x7a967153, 0xdb2c29a9,
+ 0x7a94a264, 0xdb262539,
+ 0x7a92d329, 0xdb2020e0, 0x7a9103a2, 0xdb1a1c9d, 0x7a8f33d0, 0xdb141871,
+ 0x7a8d63b2, 0xdb0e145c,
+ 0x7a8b9348, 0xdb08105e, 0x7a89c293, 0xdb020c77, 0x7a87f192, 0xdafc08a6,
+ 0x7a862046, 0xdaf604ec,
+ 0x7a844eae, 0xdaf00149, 0x7a827ccb, 0xdae9fdbd, 0x7a80aa9c, 0xdae3fa48,
+ 0x7a7ed821, 0xdaddf6ea,
+ 0x7a7d055b, 0xdad7f3a2, 0x7a7b3249, 0xdad1f072, 0x7a795eec, 0xdacbed58,
+ 0x7a778b43, 0xdac5ea56,
+ 0x7a75b74f, 0xdabfe76a, 0x7a73e30f, 0xdab9e495, 0x7a720e84, 0xdab3e1d8,
+ 0x7a7039ad, 0xdaaddf31,
+ 0x7a6e648a, 0xdaa7dca1, 0x7a6c8f1c, 0xdaa1da29, 0x7a6ab963, 0xda9bd7c7,
+ 0x7a68e35e, 0xda95d57d,
+ 0x7a670d0d, 0xda8fd349, 0x7a653671, 0xda89d12d, 0x7a635f8a, 0xda83cf28,
+ 0x7a618857, 0xda7dcd3a,
+ 0x7a5fb0d8, 0xda77cb63, 0x7a5dd90e, 0xda71c9a3, 0x7a5c00f9, 0xda6bc7fa,
+ 0x7a5a2898, 0xda65c669,
+ 0x7a584feb, 0xda5fc4ef, 0x7a5676f3, 0xda59c38c, 0x7a549db0, 0xda53c240,
+ 0x7a52c421, 0xda4dc10b,
+ 0x7a50ea47, 0xda47bfee, 0x7a4f1021, 0xda41bee8, 0x7a4d35b0, 0xda3bbdf9,
+ 0x7a4b5af3, 0xda35bd22,
+ 0x7a497feb, 0xda2fbc61, 0x7a47a498, 0xda29bbb9, 0x7a45c8f9, 0xda23bb27,
+ 0x7a43ed0e, 0xda1dbaad,
+ 0x7a4210d8, 0xda17ba4a, 0x7a403457, 0xda11b9ff, 0x7a3e578b, 0xda0bb9cb,
+ 0x7a3c7a73, 0xda05b9ae,
+ 0x7a3a9d0f, 0xd9ffb9a9, 0x7a38bf60, 0xd9f9b9bb, 0x7a36e166, 0xd9f3b9e5,
+ 0x7a350321, 0xd9edba26,
+ 0x7a332490, 0xd9e7ba7f, 0x7a3145b3, 0xd9e1baef, 0x7a2f668c, 0xd9dbbb77,
+ 0x7a2d8719, 0xd9d5bc16,
+ 0x7a2ba75a, 0xd9cfbccd, 0x7a29c750, 0xd9c9bd9b, 0x7a27e6fb, 0xd9c3be81,
+ 0x7a26065b, 0xd9bdbf7e,
+ 0x7a24256f, 0xd9b7c094, 0x7a224437, 0xd9b1c1c0, 0x7a2062b5, 0xd9abc305,
+ 0x7a1e80e7, 0xd9a5c461,
+ 0x7a1c9ece, 0xd99fc5d4, 0x7a1abc69, 0xd999c75f, 0x7a18d9b9, 0xd993c902,
+ 0x7a16f6be, 0xd98dcabd,
+ 0x7a151378, 0xd987cc90, 0x7a132fe6, 0xd981ce7a, 0x7a114c09, 0xd97bd07c,
+ 0x7a0f67e0, 0xd975d295,
+ 0x7a0d836d, 0xd96fd4c7, 0x7a0b9eae, 0xd969d710, 0x7a09b9a4, 0xd963d971,
+ 0x7a07d44e, 0xd95ddbea,
+ 0x7a05eead, 0xd957de7a, 0x7a0408c1, 0xd951e123, 0x7a02228a, 0xd94be3e3,
+ 0x7a003c07, 0xd945e6bb,
+ 0x79fe5539, 0xd93fe9ab, 0x79fc6e20, 0xd939ecb3, 0x79fa86bc, 0xd933efd3,
+ 0x79f89f0c, 0xd92df30b,
+ 0x79f6b711, 0xd927f65b, 0x79f4cecb, 0xd921f9c3, 0x79f2e63a, 0xd91bfd43,
+ 0x79f0fd5d, 0xd91600da,
+ 0x79ef1436, 0xd910048a, 0x79ed2ac3, 0xd90a0852, 0x79eb4105, 0xd9040c32,
+ 0x79e956fb, 0xd8fe1029,
+ 0x79e76ca7, 0xd8f81439, 0x79e58207, 0xd8f21861, 0x79e3971c, 0xd8ec1ca1,
+ 0x79e1abe6, 0xd8e620fa,
+ 0x79dfc064, 0xd8e0256a, 0x79ddd498, 0xd8da29f2, 0x79dbe880, 0xd8d42e93,
+ 0x79d9fc1d, 0xd8ce334c,
+ 0x79d80f6f, 0xd8c8381d, 0x79d62276, 0xd8c23d06, 0x79d43532, 0xd8bc4207,
+ 0x79d247a2, 0xd8b64720,
+ 0x79d059c8, 0xd8b04c52, 0x79ce6ba2, 0xd8aa519c, 0x79cc7d31, 0xd8a456ff,
+ 0x79ca8e75, 0xd89e5c79,
+ 0x79c89f6e, 0xd898620c, 0x79c6b01b, 0xd89267b7, 0x79c4c07e, 0xd88c6d7b,
+ 0x79c2d095, 0xd8867356,
+ 0x79c0e062, 0xd880794b, 0x79beefe3, 0xd87a7f57, 0x79bcff19, 0xd874857c,
+ 0x79bb0e04, 0xd86e8bb9,
+ 0x79b91ca4, 0xd868920f, 0x79b72af9, 0xd862987d, 0x79b53903, 0xd85c9f04,
+ 0x79b346c2, 0xd856a5a3,
+ 0x79b15435, 0xd850ac5a, 0x79af615e, 0xd84ab32a, 0x79ad6e3c, 0xd844ba13,
+ 0x79ab7ace, 0xd83ec114,
+ 0x79a98715, 0xd838c82d, 0x79a79312, 0xd832cf5f, 0x79a59ec3, 0xd82cd6aa,
+ 0x79a3aa29, 0xd826de0d,
+ 0x79a1b545, 0xd820e589, 0x799fc015, 0xd81aed1d, 0x799dca9a, 0xd814f4ca,
+ 0x799bd4d4, 0xd80efc8f,
+ 0x7999dec4, 0xd809046e, 0x7997e868, 0xd8030c64, 0x7995f1c1, 0xd7fd1474,
+ 0x7993facf, 0xd7f71c9c,
+ 0x79920392, 0xd7f124dd, 0x79900c0a, 0xd7eb2d37, 0x798e1438, 0xd7e535a9,
+ 0x798c1c1a, 0xd7df3e34,
+ 0x798a23b1, 0xd7d946d8, 0x79882afd, 0xd7d34f94, 0x798631ff, 0xd7cd586a,
+ 0x798438b5, 0xd7c76158,
+ 0x79823f20, 0xd7c16a5f, 0x79804541, 0xd7bb737f, 0x797e4b16, 0xd7b57cb7,
+ 0x797c50a1, 0xd7af8609,
+ 0x797a55e0, 0xd7a98f73, 0x79785ad5, 0xd7a398f6, 0x79765f7f, 0xd79da293,
+ 0x797463de, 0xd797ac48,
+ 0x797267f2, 0xd791b616, 0x79706bbb, 0xd78bbffc, 0x796e6f39, 0xd785c9fc,
+ 0x796c726c, 0xd77fd415,
+ 0x796a7554, 0xd779de47, 0x796877f1, 0xd773e892, 0x79667a44, 0xd76df2f6,
+ 0x79647c4c, 0xd767fd72,
+ 0x79627e08, 0xd7620808, 0x79607f7a, 0xd75c12b7, 0x795e80a1, 0xd7561d7f,
+ 0x795c817d, 0xd7502860,
+ 0x795a820e, 0xd74a335b, 0x79588255, 0xd7443e6e, 0x79568250, 0xd73e499a,
+ 0x79548201, 0xd73854e0,
+ 0x79528167, 0xd732603f, 0x79508082, 0xd72c6bb6, 0x794e7f52, 0xd7267748,
+ 0x794c7dd7, 0xd72082f2,
+ 0x794a7c12, 0xd71a8eb5, 0x79487a01, 0xd7149a92, 0x794677a6, 0xd70ea688,
+ 0x79447500, 0xd708b297,
+ 0x79427210, 0xd702bec0, 0x79406ed4, 0xd6fccb01, 0x793e6b4e, 0xd6f6d75d,
+ 0x793c677d, 0xd6f0e3d1,
+ 0x793a6361, 0xd6eaf05f, 0x79385efa, 0xd6e4fd06, 0x79365a49, 0xd6df09c6,
+ 0x7934554d, 0xd6d916a0,
+ 0x79325006, 0xd6d32393, 0x79304a74, 0xd6cd30a0, 0x792e4497, 0xd6c73dc6,
+ 0x792c3e70, 0xd6c14b05,
+ 0x792a37fe, 0xd6bb585e, 0x79283141, 0xd6b565d0, 0x79262a3a, 0xd6af735c,
+ 0x792422e8, 0xd6a98101,
+ 0x79221b4b, 0xd6a38ec0, 0x79201363, 0xd69d9c98, 0x791e0b31, 0xd697aa8a,
+ 0x791c02b4, 0xd691b895,
+ 0x7919f9ec, 0xd68bc6ba, 0x7917f0d9, 0xd685d4f9, 0x7915e77c, 0xd67fe351,
+ 0x7913ddd4, 0xd679f1c2,
+ 0x7911d3e2, 0xd674004e, 0x790fc9a4, 0xd66e0ef2, 0x790dbf1d, 0xd6681db1,
+ 0x790bb44a, 0xd6622c89,
+ 0x7909a92d, 0xd65c3b7b, 0x79079dc5, 0xd6564a87, 0x79059212, 0xd65059ac,
+ 0x79038615, 0xd64a68eb,
+ 0x790179cd, 0xd6447844, 0x78ff6d3b, 0xd63e87b6, 0x78fd605d, 0xd6389742,
+ 0x78fb5336, 0xd632a6e8,
+ 0x78f945c3, 0xd62cb6a8, 0x78f73806, 0xd626c681, 0x78f529fe, 0xd620d675,
+ 0x78f31bac, 0xd61ae682,
+ 0x78f10d0f, 0xd614f6a9, 0x78eefe28, 0xd60f06ea, 0x78eceef6, 0xd6091745,
+ 0x78eadf79, 0xd60327b9,
+ 0x78e8cfb2, 0xd5fd3848, 0x78e6bfa0, 0xd5f748f0, 0x78e4af44, 0xd5f159b3,
+ 0x78e29e9d, 0xd5eb6a8f,
+ 0x78e08dab, 0xd5e57b85, 0x78de7c6f, 0xd5df8c96, 0x78dc6ae8, 0xd5d99dc0,
+ 0x78da5917, 0xd5d3af04,
+ 0x78d846fb, 0xd5cdc062, 0x78d63495, 0xd5c7d1db, 0x78d421e4, 0xd5c1e36d,
+ 0x78d20ee9, 0xd5bbf519,
+ 0x78cffba3, 0xd5b606e0, 0x78cde812, 0xd5b018c0, 0x78cbd437, 0xd5aa2abb,
+ 0x78c9c012, 0xd5a43cd0,
+ 0x78c7aba2, 0xd59e4eff, 0x78c596e7, 0xd5986148, 0x78c381e2, 0xd59273ab,
+ 0x78c16c93, 0xd58c8628,
+ 0x78bf56f9, 0xd58698c0, 0x78bd4114, 0xd580ab72, 0x78bb2ae5, 0xd57abe3d,
+ 0x78b9146c, 0xd574d124,
+ 0x78b6fda8, 0xd56ee424, 0x78b4e69a, 0xd568f73f, 0x78b2cf41, 0xd5630a74,
+ 0x78b0b79e, 0xd55d1dc3,
+ 0x78ae9fb0, 0xd557312d, 0x78ac8778, 0xd55144b0, 0x78aa6ef5, 0xd54b584f,
+ 0x78a85628, 0xd5456c07,
+ 0x78a63d11, 0xd53f7fda, 0x78a423af, 0xd53993c7, 0x78a20a03, 0xd533a7cf,
+ 0x789ff00c, 0xd52dbbf1,
+ 0x789dd5cb, 0xd527d02e, 0x789bbb3f, 0xd521e484, 0x7899a06a, 0xd51bf8f6,
+ 0x78978549, 0xd5160d82,
+ 0x789569df, 0xd5102228, 0x78934e2a, 0xd50a36e9, 0x7891322a, 0xd5044bc4,
+ 0x788f15e0, 0xd4fe60ba,
+ 0x788cf94c, 0xd4f875ca, 0x788adc6e, 0xd4f28af5, 0x7888bf45, 0xd4eca03a,
+ 0x7886a1d1, 0xd4e6b59a,
+ 0x78848414, 0xd4e0cb15, 0x7882660c, 0xd4dae0aa, 0x788047ba, 0xd4d4f65a,
+ 0x787e291d, 0xd4cf0c24,
+ 0x787c0a36, 0xd4c92209, 0x7879eb05, 0xd4c33809, 0x7877cb89, 0xd4bd4e23,
+ 0x7875abc3, 0xd4b76458,
+ 0x78738bb3, 0xd4b17aa8, 0x78716b59, 0xd4ab9112, 0x786f4ab4, 0xd4a5a798,
+ 0x786d29c5, 0xd49fbe37,
+ 0x786b088c, 0xd499d4f2, 0x7868e708, 0xd493ebc8, 0x7866c53a, 0xd48e02b8,
+ 0x7864a322, 0xd48819c3,
+ 0x786280bf, 0xd48230e9, 0x78605e13, 0xd47c4829, 0x785e3b1c, 0xd4765f85,
+ 0x785c17db, 0xd47076fb,
+ 0x7859f44f, 0xd46a8e8d, 0x7857d079, 0xd464a639, 0x7855ac5a, 0xd45ebe00,
+ 0x785387ef, 0xd458d5e2,
+ 0x7851633b, 0xd452eddf, 0x784f3e3c, 0xd44d05f6, 0x784d18f4, 0xd4471e29,
+ 0x784af361, 0xd4413677,
+ 0x7848cd83, 0xd43b4ee0, 0x7846a75c, 0xd4356763, 0x784480ea, 0xd42f8002,
+ 0x78425a2f, 0xd42998bc,
+ 0x78403329, 0xd423b191, 0x783e0bd9, 0xd41dca81, 0x783be43e, 0xd417e38c,
+ 0x7839bc5a, 0xd411fcb2,
+ 0x7837942b, 0xd40c15f3, 0x78356bb2, 0xd4062f4f, 0x783342ef, 0xd40048c6,
+ 0x783119e2, 0xd3fa6259,
+ 0x782ef08b, 0xd3f47c06, 0x782cc6ea, 0xd3ee95cf, 0x782a9cfe, 0xd3e8afb3,
+ 0x782872c8, 0xd3e2c9b2,
+ 0x78264849, 0xd3dce3cd, 0x78241d7f, 0xd3d6fe03, 0x7821f26b, 0xd3d11853,
+ 0x781fc70d, 0xd3cb32c0,
+ 0x781d9b65, 0xd3c54d47, 0x781b6f72, 0xd3bf67ea, 0x78194336, 0xd3b982a8,
+ 0x781716b0, 0xd3b39d81,
+ 0x7814e9df, 0xd3adb876, 0x7812bcc4, 0xd3a7d385, 0x78108f60, 0xd3a1eeb1,
+ 0x780e61b1, 0xd39c09f7,
+ 0x780c33b8, 0xd396255a, 0x780a0575, 0xd39040d7, 0x7807d6e9, 0xd38a5c70,
+ 0x7805a812, 0xd3847824,
+ 0x780378f1, 0xd37e93f4, 0x78014986, 0xd378afdf, 0x77ff19d1, 0xd372cbe6,
+ 0x77fce9d2, 0xd36ce808,
+ 0x77fab989, 0xd3670446, 0x77f888f6, 0xd361209f, 0x77f65819, 0xd35b3d13,
+ 0x77f426f2, 0xd35559a4,
+ 0x77f1f581, 0xd34f764f, 0x77efc3c5, 0xd3499317, 0x77ed91c0, 0xd343affa,
+ 0x77eb5f71, 0xd33dccf8,
+ 0x77e92cd9, 0xd337ea12, 0x77e6f9f6, 0xd3320748, 0x77e4c6c9, 0xd32c2499,
+ 0x77e29352, 0xd3264206,
+ 0x77e05f91, 0xd3205f8f, 0x77de2b86, 0xd31a7d33, 0x77dbf732, 0xd3149af3,
+ 0x77d9c293, 0xd30eb8cf,
+ 0x77d78daa, 0xd308d6c7, 0x77d55878, 0xd302f4da, 0x77d322fc, 0xd2fd1309,
+ 0x77d0ed35, 0xd2f73154,
+ 0x77ceb725, 0xd2f14fba, 0x77cc80cb, 0xd2eb6e3c, 0x77ca4a27, 0xd2e58cdb,
+ 0x77c81339, 0xd2dfab95,
+ 0x77c5dc01, 0xd2d9ca6a, 0x77c3a47f, 0xd2d3e95c, 0x77c16cb4, 0xd2ce0869,
+ 0x77bf349f, 0xd2c82793,
+ 0x77bcfc3f, 0xd2c246d8, 0x77bac396, 0xd2bc6639, 0x77b88aa3, 0xd2b685b6,
+ 0x77b65166, 0xd2b0a54f,
+ 0x77b417df, 0xd2aac504, 0x77b1de0f, 0xd2a4e4d5, 0x77afa3f5, 0xd29f04c2,
+ 0x77ad6990, 0xd29924cb,
+ 0x77ab2ee2, 0xd29344f0, 0x77a8f3ea, 0xd28d6531, 0x77a6b8a9, 0xd287858e,
+ 0x77a47d1d, 0xd281a607,
+ 0x77a24148, 0xd27bc69c, 0x77a00529, 0xd275e74d, 0x779dc8c0, 0xd270081b,
+ 0x779b8c0e, 0xd26a2904,
+ 0x77994f11, 0xd2644a0a, 0x779711cb, 0xd25e6b2b, 0x7794d43b, 0xd2588c69,
+ 0x77929661, 0xd252adc3,
+ 0x7790583e, 0xd24ccf39, 0x778e19d0, 0xd246f0cb, 0x778bdb19, 0xd241127a,
+ 0x77899c19, 0xd23b3444,
+ 0x77875cce, 0xd235562b, 0x77851d3a, 0xd22f782f, 0x7782dd5c, 0xd2299a4e,
+ 0x77809d35, 0xd223bc8a,
+ 0x777e5cc3, 0xd21ddee2, 0x777c1c08, 0xd2180156, 0x7779db03, 0xd21223e7,
+ 0x777799b5, 0xd20c4694,
+ 0x7775581d, 0xd206695d, 0x7773163b, 0xd2008c43, 0x7770d40f, 0xd1faaf45,
+ 0x776e919a, 0xd1f4d263,
+ 0x776c4edb, 0xd1eef59e, 0x776a0bd3, 0xd1e918f5, 0x7767c880, 0xd1e33c69,
+ 0x776584e5, 0xd1dd5ff9,
+ 0x776340ff, 0xd1d783a6, 0x7760fcd0, 0xd1d1a76f, 0x775eb857, 0xd1cbcb54,
+ 0x775c7395, 0xd1c5ef56,
+ 0x775a2e89, 0xd1c01375, 0x7757e933, 0xd1ba37b0, 0x7755a394, 0xd1b45c08,
+ 0x77535dab, 0xd1ae807c,
+ 0x77511778, 0xd1a8a50d, 0x774ed0fc, 0xd1a2c9ba, 0x774c8a36, 0xd19cee84,
+ 0x774a4327, 0xd197136b,
+ 0x7747fbce, 0xd191386e, 0x7745b42c, 0xd18b5d8e, 0x77436c40, 0xd18582ca,
+ 0x7741240a, 0xd17fa823,
+ 0x773edb8b, 0xd179cd99, 0x773c92c2, 0xd173f32c, 0x773a49b0, 0xd16e18db,
+ 0x77380054, 0xd1683ea7,
+ 0x7735b6af, 0xd1626490, 0x77336cc0, 0xd15c8a95, 0x77312287, 0xd156b0b7,
+ 0x772ed805, 0xd150d6f6,
+ 0x772c8d3a, 0xd14afd52, 0x772a4225, 0xd14523cb, 0x7727f6c6, 0xd13f4a60,
+ 0x7725ab1f, 0xd1397113,
+ 0x77235f2d, 0xd13397e2, 0x772112f2, 0xd12dbece, 0x771ec66e, 0xd127e5d7,
+ 0x771c79a0, 0xd1220cfc,
+ 0x771a2c88, 0xd11c343f, 0x7717df27, 0xd1165b9f, 0x7715917d, 0xd110831b,
+ 0x77134389, 0xd10aaab5,
+ 0x7710f54c, 0xd104d26b, 0x770ea6c5, 0xd0fefa3f, 0x770c57f5, 0xd0f9222f,
+ 0x770a08dc, 0xd0f34a3d,
+ 0x7707b979, 0xd0ed7267, 0x770569cc, 0xd0e79aaf, 0x770319d6, 0xd0e1c313,
+ 0x7700c997, 0xd0dbeb95,
+ 0x76fe790e, 0xd0d61434, 0x76fc283c, 0xd0d03cf0, 0x76f9d721, 0xd0ca65c9,
+ 0x76f785bc, 0xd0c48ebf,
+ 0x76f5340e, 0xd0beb7d2, 0x76f2e216, 0xd0b8e102, 0x76f08fd5, 0xd0b30a50,
+ 0x76ee3d4b, 0xd0ad33ba,
+ 0x76ebea77, 0xd0a75d42, 0x76e9975a, 0xd0a186e7, 0x76e743f4, 0xd09bb0aa,
+ 0x76e4f044, 0xd095da89,
+ 0x76e29c4b, 0xd0900486, 0x76e04808, 0xd08a2ea0, 0x76ddf37c, 0xd08458d7,
+ 0x76db9ea7, 0xd07e832c,
+ 0x76d94989, 0xd078ad9e, 0x76d6f421, 0xd072d82d, 0x76d49e70, 0xd06d02da,
+ 0x76d24876, 0xd0672da3,
+ 0x76cff232, 0xd061588b, 0x76cd9ba5, 0xd05b838f, 0x76cb44cf, 0xd055aeb1,
+ 0x76c8edb0, 0xd04fd9f1,
+ 0x76c69647, 0xd04a054e, 0x76c43e95, 0xd04430c8, 0x76c1e699, 0xd03e5c60,
+ 0x76bf8e55, 0xd0388815,
+ 0x76bd35c7, 0xd032b3e7, 0x76badcf0, 0xd02cdfd8, 0x76b883d0, 0xd0270be5,
+ 0x76b62a66, 0xd0213810,
+ 0x76b3d0b4, 0xd01b6459, 0x76b176b8, 0xd01590bf, 0x76af1c72, 0xd00fbd43,
+ 0x76acc1e4, 0xd009e9e4,
+ 0x76aa670d, 0xd00416a3, 0x76a80bec, 0xcffe4380, 0x76a5b082, 0xcff8707a,
+ 0x76a354cf, 0xcff29d92,
+ 0x76a0f8d2, 0xcfeccac7, 0x769e9c8d, 0xcfe6f81a, 0x769c3ffe, 0xcfe1258b,
+ 0x7699e326, 0xcfdb531a,
+ 0x76978605, 0xcfd580c6, 0x7695289b, 0xcfcfae8f, 0x7692cae8, 0xcfc9dc77,
+ 0x76906ceb, 0xcfc40a7c,
+ 0x768e0ea6, 0xcfbe389f, 0x768bb017, 0xcfb866e0, 0x7689513f, 0xcfb2953f,
+ 0x7686f21e, 0xcfacc3bb,
+ 0x768492b4, 0xcfa6f255, 0x76823301, 0xcfa1210d, 0x767fd304, 0xcf9b4fe3,
+ 0x767d72bf, 0xcf957ed7,
+ 0x767b1231, 0xcf8fade9, 0x7678b159, 0xcf89dd18, 0x76765038, 0xcf840c65,
+ 0x7673eecf, 0xcf7e3bd1,
+ 0x76718d1c, 0xcf786b5a, 0x766f2b20, 0xcf729b01, 0x766cc8db, 0xcf6ccac6,
+ 0x766a664d, 0xcf66faa9,
+ 0x76680376, 0xcf612aaa, 0x7665a056, 0xcf5b5ac9, 0x76633ced, 0xcf558b06,
+ 0x7660d93b, 0xcf4fbb61,
+ 0x765e7540, 0xcf49ebda, 0x765c10fc, 0xcf441c71, 0x7659ac6f, 0xcf3e4d26,
+ 0x76574798, 0xcf387dfa,
+ 0x7654e279, 0xcf32aeeb, 0x76527d11, 0xcf2cdffa, 0x76501760, 0xcf271128,
+ 0x764db166, 0xcf214274,
+ 0x764b4b23, 0xcf1b73de, 0x7648e497, 0xcf15a566, 0x76467dc2, 0xcf0fd70c,
+ 0x764416a4, 0xcf0a08d0,
+ 0x7641af3d, 0xcf043ab3, 0x763f478d, 0xcefe6cb3, 0x763cdf94, 0xcef89ed2,
+ 0x763a7752, 0xcef2d110,
+ 0x76380ec8, 0xceed036b, 0x7635a5f4, 0xcee735e5, 0x76333cd8, 0xcee1687d,
+ 0x7630d372, 0xcedb9b33,
+ 0x762e69c4, 0xced5ce08, 0x762bffcd, 0xced000fb, 0x7629958c, 0xceca340c,
+ 0x76272b03, 0xcec4673c,
+ 0x7624c031, 0xcebe9a8a, 0x76225517, 0xceb8cdf7, 0x761fe9b3, 0xceb30181,
+ 0x761d7e06, 0xcead352b,
+ 0x761b1211, 0xcea768f2, 0x7618a5d3, 0xcea19cd8, 0x7616394c, 0xce9bd0dd,
+ 0x7613cc7c, 0xce960500,
+ 0x76115f63, 0xce903942, 0x760ef201, 0xce8a6da2, 0x760c8457, 0xce84a220,
+ 0x760a1664, 0xce7ed6bd,
+ 0x7607a828, 0xce790b79, 0x760539a3, 0xce734053, 0x7602cad5, 0xce6d754c,
+ 0x76005bbf, 0xce67aa63,
+ 0x75fdec60, 0xce61df99, 0x75fb7cb8, 0xce5c14ed, 0x75f90cc7, 0xce564a60,
+ 0x75f69c8d, 0xce507ff2,
+ 0x75f42c0b, 0xce4ab5a2, 0x75f1bb40, 0xce44eb71, 0x75ef4a2c, 0xce3f215f,
+ 0x75ecd8cf, 0xce39576c,
+ 0x75ea672a, 0xce338d97, 0x75e7f53c, 0xce2dc3e1, 0x75e58305, 0xce27fa49,
+ 0x75e31086, 0xce2230d0,
+ 0x75e09dbd, 0xce1c6777, 0x75de2aac, 0xce169e3b, 0x75dbb753, 0xce10d51f,
+ 0x75d943b0, 0xce0b0c21,
+ 0x75d6cfc5, 0xce054343, 0x75d45b92, 0xcdff7a83, 0x75d1e715, 0xcdf9b1e2,
+ 0x75cf7250, 0xcdf3e95f,
+ 0x75ccfd42, 0xcdee20fc, 0x75ca87ec, 0xcde858b8, 0x75c8124d, 0xcde29092,
+ 0x75c59c65, 0xcddcc88b,
+ 0x75c32634, 0xcdd700a4, 0x75c0afbb, 0xcdd138db, 0x75be38fa, 0xcdcb7131,
+ 0x75bbc1ef, 0xcdc5a9a6,
+ 0x75b94a9c, 0xcdbfe23a, 0x75b6d301, 0xcdba1aee, 0x75b45b1d, 0xcdb453c0,
+ 0x75b1e2f0, 0xcdae8cb1,
+ 0x75af6a7b, 0xcda8c5c1, 0x75acf1bd, 0xcda2fef0, 0x75aa78b6, 0xcd9d383f,
+ 0x75a7ff67, 0xcd9771ac,
+ 0x75a585cf, 0xcd91ab39, 0x75a30bef, 0xcd8be4e4, 0x75a091c6, 0xcd861eaf,
+ 0x759e1755, 0xcd805899,
+ 0x759b9c9b, 0xcd7a92a2, 0x75992198, 0xcd74ccca, 0x7596a64d, 0xcd6f0711,
+ 0x75942ab9, 0xcd694178,
+ 0x7591aedd, 0xcd637bfe, 0x758f32b9, 0xcd5db6a3, 0x758cb64c, 0xcd57f167,
+ 0x758a3996, 0xcd522c4a,
+ 0x7587bc98, 0xcd4c674d, 0x75853f51, 0xcd46a26f, 0x7582c1c2, 0xcd40ddb0,
+ 0x758043ea, 0xcd3b1911,
+ 0x757dc5ca, 0xcd355491, 0x757b4762, 0xcd2f9030, 0x7578c8b0, 0xcd29cbee,
+ 0x757649b7, 0xcd2407cc,
+ 0x7573ca75, 0xcd1e43ca, 0x75714aea, 0xcd187fe6, 0x756ecb18, 0xcd12bc22,
+ 0x756c4afc, 0xcd0cf87e,
+ 0x7569ca99, 0xcd0734f9, 0x756749ec, 0xcd017193, 0x7564c8f8, 0xccfbae4d,
+ 0x756247bb, 0xccf5eb26,
+ 0x755fc635, 0xccf0281f, 0x755d4467, 0xccea6538, 0x755ac251, 0xcce4a26f,
+ 0x75583ff3, 0xccdedfc7,
+ 0x7555bd4c, 0xccd91d3d, 0x75533a5c, 0xccd35ad4, 0x7550b725, 0xcccd988a,
+ 0x754e33a4, 0xccc7d65f,
+ 0x754bafdc, 0xccc21455, 0x75492bcb, 0xccbc5269, 0x7546a772, 0xccb6909e,
+ 0x754422d0, 0xccb0cef2,
+ 0x75419de7, 0xccab0d65, 0x753f18b4, 0xcca54bf9, 0x753c933a, 0xcc9f8aac,
+ 0x753a0d77, 0xcc99c97e,
+ 0x7537876c, 0xcc940871, 0x75350118, 0xcc8e4783, 0x75327a7d, 0xcc8886b5,
+ 0x752ff399, 0xcc82c607,
+ 0x752d6c6c, 0xcc7d0578, 0x752ae4f8, 0xcc774509, 0x75285d3b, 0xcc7184ba,
+ 0x7525d536, 0xcc6bc48b,
+ 0x75234ce8, 0xcc66047b, 0x7520c453, 0xcc60448c, 0x751e3b75, 0xcc5a84bc,
+ 0x751bb24f, 0xcc54c50c,
+ 0x751928e0, 0xcc4f057c, 0x75169f2a, 0xcc49460c, 0x7514152b, 0xcc4386bc,
+ 0x75118ae4, 0xcc3dc78b,
+ 0x750f0054, 0xcc38087b, 0x750c757d, 0xcc32498a, 0x7509ea5d, 0xcc2c8aba,
+ 0x75075ef5, 0xcc26cc09,
+ 0x7504d345, 0xcc210d79, 0x7502474d, 0xcc1b4f08, 0x74ffbb0d, 0xcc1590b8,
+ 0x74fd2e84, 0xcc0fd287,
+ 0x74faa1b3, 0xcc0a1477, 0x74f8149a, 0xcc045686, 0x74f58739, 0xcbfe98b6,
+ 0x74f2f990, 0xcbf8db05,
+ 0x74f06b9e, 0xcbf31d75, 0x74eddd65, 0xcbed6005, 0x74eb4ee3, 0xcbe7a2b5,
+ 0x74e8c01a, 0xcbe1e585,
+ 0x74e63108, 0xcbdc2876, 0x74e3a1ae, 0xcbd66b86, 0x74e1120c, 0xcbd0aeb7,
+ 0x74de8221, 0xcbcaf208,
+ 0x74dbf1ef, 0xcbc53579, 0x74d96175, 0xcbbf790a, 0x74d6d0b2, 0xcbb9bcbb,
+ 0x74d43fa8, 0xcbb4008d,
+ 0x74d1ae55, 0xcbae447f, 0x74cf1cbb, 0xcba88891, 0x74cc8ad8, 0xcba2ccc4,
+ 0x74c9f8ad, 0xcb9d1117,
+ 0x74c7663a, 0xcb97558a, 0x74c4d380, 0xcb919a1d, 0x74c2407d, 0xcb8bded1,
+ 0x74bfad32, 0xcb8623a5,
+ 0x74bd199f, 0xcb80689a, 0x74ba85c4, 0xcb7aadaf, 0x74b7f1a1, 0xcb74f2e4,
+ 0x74b55d36, 0xcb6f383a,
+ 0x74b2c884, 0xcb697db0, 0x74b03389, 0xcb63c347, 0x74ad9e46, 0xcb5e08fe,
+ 0x74ab08bb, 0xcb584ed6,
+ 0x74a872e8, 0xcb5294ce, 0x74a5dccd, 0xcb4cdae6, 0x74a3466b, 0xcb47211f,
+ 0x74a0afc0, 0xcb416779,
+ 0x749e18cd, 0xcb3badf3, 0x749b8193, 0xcb35f48d, 0x7498ea11, 0xcb303b49,
+ 0x74965246, 0xcb2a8224,
+ 0x7493ba34, 0xcb24c921, 0x749121da, 0xcb1f103e, 0x748e8938, 0xcb19577b,
+ 0x748bf04d, 0xcb139ed9,
+ 0x7489571c, 0xcb0de658, 0x7486bda2, 0xcb082df8, 0x748423e0, 0xcb0275b8,
+ 0x748189d7, 0xcafcbd99,
+ 0x747eef85, 0xcaf7059a, 0x747c54ec, 0xcaf14dbd, 0x7479ba0b, 0xcaeb9600,
+ 0x74771ee2, 0xcae5de64,
+ 0x74748371, 0xcae026e8, 0x7471e7b8, 0xcada6f8d, 0x746f4bb8, 0xcad4b853,
+ 0x746caf70, 0xcacf013a,
+ 0x746a12df, 0xcac94a42, 0x74677608, 0xcac3936b, 0x7464d8e8, 0xcabddcb4,
+ 0x74623b80, 0xcab8261e,
+ 0x745f9dd1, 0xcab26fa9, 0x745cffda, 0xcaacb955, 0x745a619b, 0xcaa70322,
+ 0x7457c314, 0xcaa14d10,
+ 0x74552446, 0xca9b971e, 0x74528530, 0xca95e14e, 0x744fe5d2, 0xca902b9f,
+ 0x744d462c, 0xca8a7610,
+ 0x744aa63f, 0xca84c0a3, 0x7448060a, 0xca7f0b56, 0x7445658d, 0xca79562b,
+ 0x7442c4c8, 0xca73a120,
+ 0x744023bc, 0xca6dec37, 0x743d8268, 0xca68376e, 0x743ae0cc, 0xca6282c7,
+ 0x74383ee9, 0xca5cce40,
+ 0x74359cbd, 0xca5719db, 0x7432fa4b, 0xca516597, 0x74305790, 0xca4bb174,
+ 0x742db48e, 0xca45fd72,
+ 0x742b1144, 0xca404992, 0x74286db3, 0xca3a95d2, 0x7425c9da, 0xca34e234,
+ 0x742325b9, 0xca2f2eb6,
+ 0x74208150, 0xca297b5a, 0x741ddca0, 0xca23c820, 0x741b37a9, 0xca1e1506,
+ 0x74189269, 0xca18620e,
+ 0x7415ece2, 0xca12af37, 0x74134714, 0xca0cfc81, 0x7410a0fe, 0xca0749ec,
+ 0x740dfaa0, 0xca019779,
+ 0x740b53fb, 0xc9fbe527, 0x7408ad0e, 0xc9f632f6, 0x740605d9, 0xc9f080e7,
+ 0x74035e5d, 0xc9eacef9,
+ 0x7400b69a, 0xc9e51d2d, 0x73fe0e8f, 0xc9df6b81, 0x73fb663c, 0xc9d9b9f7,
+ 0x73f8bda2, 0xc9d4088f,
+ 0x73f614c0, 0xc9ce5748, 0x73f36b97, 0xc9c8a622, 0x73f0c226, 0xc9c2f51e,
+ 0x73ee186e, 0xc9bd443c,
+ 0x73eb6e6e, 0xc9b7937a, 0x73e8c426, 0xc9b1e2db, 0x73e61997, 0xc9ac325d,
+ 0x73e36ec1, 0xc9a68200,
+ 0x73e0c3a3, 0xc9a0d1c5, 0x73de183e, 0xc99b21ab, 0x73db6c91, 0xc99571b3,
+ 0x73d8c09d, 0xc98fc1dc,
+ 0x73d61461, 0xc98a1227, 0x73d367de, 0xc9846294, 0x73d0bb13, 0xc97eb322,
+ 0x73ce0e01, 0xc97903d2,
+ 0x73cb60a8, 0xc97354a4, 0x73c8b307, 0xc96da597, 0x73c6051f, 0xc967f6ac,
+ 0x73c356ef, 0xc96247e2,
+ 0x73c0a878, 0xc95c993a, 0x73bdf9b9, 0xc956eab4, 0x73bb4ab3, 0xc9513c50,
+ 0x73b89b66, 0xc94b8e0d,
+ 0x73b5ebd1, 0xc945dfec, 0x73b33bf5, 0xc94031ed, 0x73b08bd1, 0xc93a8410,
+ 0x73addb67, 0xc934d654,
+ 0x73ab2ab4, 0xc92f28ba, 0x73a879bb, 0xc9297b42, 0x73a5c87a, 0xc923cdec,
+ 0x73a316f2, 0xc91e20b8,
+ 0x73a06522, 0xc91873a5, 0x739db30b, 0xc912c6b5, 0x739b00ad, 0xc90d19e6,
+ 0x73984e07, 0xc9076d39,
+ 0x73959b1b, 0xc901c0ae, 0x7392e7e6, 0xc8fc1445, 0x7390346b, 0xc8f667fe,
+ 0x738d80a8, 0xc8f0bbd9,
+ 0x738acc9e, 0xc8eb0fd6, 0x7388184d, 0xc8e563f5, 0x738563b5, 0xc8dfb836,
+ 0x7382aed5, 0xc8da0c99,
+ 0x737ff9ae, 0xc8d4611d, 0x737d4440, 0xc8ceb5c4, 0x737a8e8a, 0xc8c90a8d,
+ 0x7377d88d, 0xc8c35f78,
+ 0x73752249, 0xc8bdb485, 0x73726bbe, 0xc8b809b4, 0x736fb4ec, 0xc8b25f06,
+ 0x736cfdd2, 0xc8acb479,
+ 0x736a4671, 0xc8a70a0e, 0x73678ec9, 0xc8a15fc6, 0x7364d6da, 0xc89bb5a0,
+ 0x73621ea4, 0xc8960b9c,
+ 0x735f6626, 0xc89061ba, 0x735cad61, 0xc88ab7fa, 0x7359f456, 0xc8850e5d,
+ 0x73573b03, 0xc87f64e2,
+ 0x73548168, 0xc879bb89, 0x7351c787, 0xc8741252, 0x734f0d5f, 0xc86e693d,
+ 0x734c52ef, 0xc868c04b,
+ 0x73499838, 0xc863177b, 0x7346dd3a, 0xc85d6ece, 0x734421f6, 0xc857c642,
+ 0x7341666a, 0xc8521dd9,
+ 0x733eaa96, 0xc84c7593, 0x733bee7c, 0xc846cd6e, 0x7339321b, 0xc841256d,
+ 0x73367572, 0xc83b7d8d,
+ 0x7333b883, 0xc835d5d0, 0x7330fb4d, 0xc8302e35, 0x732e3dcf, 0xc82a86bd,
+ 0x732b800a, 0xc824df67,
+ 0x7328c1ff, 0xc81f3834, 0x732603ac, 0xc8199123, 0x73234512, 0xc813ea35,
+ 0x73208632, 0xc80e4369,
+ 0x731dc70a, 0xc8089cbf, 0x731b079b, 0xc802f638, 0x731847e5, 0xc7fd4fd4,
+ 0x731587e8, 0xc7f7a992,
+ 0x7312c7a5, 0xc7f20373, 0x7310071a, 0xc7ec5d76, 0x730d4648, 0xc7e6b79c,
+ 0x730a8530, 0xc7e111e5,
+ 0x7307c3d0, 0xc7db6c50, 0x73050229, 0xc7d5c6de, 0x7302403c, 0xc7d0218e,
+ 0x72ff7e07, 0xc7ca7c61,
+ 0x72fcbb8c, 0xc7c4d757, 0x72f9f8c9, 0xc7bf3270, 0x72f735c0, 0xc7b98dab,
+ 0x72f47270, 0xc7b3e909,
+ 0x72f1aed9, 0xc7ae4489, 0x72eeeafb, 0xc7a8a02c, 0x72ec26d6, 0xc7a2fbf3,
+ 0x72e9626a, 0xc79d57db,
+ 0x72e69db7, 0xc797b3e7, 0x72e3d8be, 0xc7921015, 0x72e1137d, 0xc78c6c67,
+ 0x72de4df6, 0xc786c8db,
+ 0x72db8828, 0xc7812572, 0x72d8c213, 0xc77b822b, 0x72d5fbb7, 0xc775df08,
+ 0x72d33514, 0xc7703c08,
+ 0x72d06e2b, 0xc76a992a, 0x72cda6fb, 0xc764f66f, 0x72cadf83, 0xc75f53d7,
+ 0x72c817c6, 0xc759b163,
+ 0x72c54fc1, 0xc7540f11, 0x72c28775, 0xc74e6ce2, 0x72bfbee3, 0xc748cad6,
+ 0x72bcf60a, 0xc74328ed,
+ 0x72ba2cea, 0xc73d8727, 0x72b76383, 0xc737e584, 0x72b499d6, 0xc7324404,
+ 0x72b1cfe1, 0xc72ca2a7,
+ 0x72af05a7, 0xc727016d, 0x72ac3b25, 0xc7216056, 0x72a9705c, 0xc71bbf62,
+ 0x72a6a54d, 0xc7161e92,
+ 0x72a3d9f7, 0xc7107de4, 0x72a10e5b, 0xc70add5a, 0x729e4277, 0xc7053cf2,
+ 0x729b764d, 0xc6ff9cae,
+ 0x7298a9dd, 0xc6f9fc8d, 0x7295dd25, 0xc6f45c8f, 0x72931027, 0xc6eebcb5,
+ 0x729042e3, 0xc6e91cfd,
+ 0x728d7557, 0xc6e37d69, 0x728aa785, 0xc6ddddf8, 0x7287d96c, 0xc6d83eab,
+ 0x72850b0d, 0xc6d29f80,
+ 0x72823c67, 0xc6cd0079, 0x727f6d7a, 0xc6c76195, 0x727c9e47, 0xc6c1c2d4,
+ 0x7279cecd, 0xc6bc2437,
+ 0x7276ff0d, 0xc6b685bd, 0x72742f05, 0xc6b0e767, 0x72715eb8, 0xc6ab4933,
+ 0x726e8e23, 0xc6a5ab23,
+ 0x726bbd48, 0xc6a00d37, 0x7268ec27, 0xc69a6f6e, 0x72661abf, 0xc694d1c8,
+ 0x72634910, 0xc68f3446,
+ 0x7260771b, 0xc68996e7, 0x725da4df, 0xc683f9ab, 0x725ad25d, 0xc67e5c93,
+ 0x7257ff94, 0xc678bf9f,
+ 0x72552c85, 0xc67322ce, 0x7252592f, 0xc66d8620, 0x724f8593, 0xc667e996,
+ 0x724cb1b0, 0xc6624d30,
+ 0x7249dd86, 0xc65cb0ed, 0x72470916, 0xc65714cd, 0x72443460, 0xc65178d1,
+ 0x72415f63, 0xc64bdcf9,
+ 0x723e8a20, 0xc6464144, 0x723bb496, 0xc640a5b3, 0x7238dec5, 0xc63b0a46,
+ 0x723608af, 0xc6356efc,
+ 0x72333251, 0xc62fd3d6, 0x72305bae, 0xc62a38d4, 0x722d84c4, 0xc6249df5,
+ 0x722aad93, 0xc61f033a,
+ 0x7227d61c, 0xc61968a2, 0x7224fe5f, 0xc613ce2f, 0x7222265b, 0xc60e33df,
+ 0x721f4e11, 0xc60899b2,
+ 0x721c7580, 0xc602ffaa, 0x72199ca9, 0xc5fd65c5, 0x7216c38c, 0xc5f7cc04,
+ 0x7213ea28, 0xc5f23267,
+ 0x7211107e, 0xc5ec98ee, 0x720e368d, 0xc5e6ff98, 0x720b5c57, 0xc5e16667,
+ 0x720881d9, 0xc5dbcd59,
+ 0x7205a716, 0xc5d6346f, 0x7202cc0c, 0xc5d09ba9, 0x71fff0bc, 0xc5cb0307,
+ 0x71fd1525, 0xc5c56a89,
+ 0x71fa3949, 0xc5bfd22e, 0x71f75d25, 0xc5ba39f8, 0x71f480bc, 0xc5b4a1e5,
+ 0x71f1a40c, 0xc5af09f7,
+ 0x71eec716, 0xc5a9722c, 0x71ebe9da, 0xc5a3da86, 0x71e90c57, 0xc59e4303,
+ 0x71e62e8f, 0xc598aba5,
+ 0x71e35080, 0xc593146a, 0x71e0722a, 0xc58d7d54, 0x71dd938f, 0xc587e661,
+ 0x71dab4ad, 0xc5824f93,
+ 0x71d7d585, 0xc57cb8e9, 0x71d4f617, 0xc5772263, 0x71d21662, 0xc5718c00,
+ 0x71cf3667, 0xc56bf5c2,
+ 0x71cc5626, 0xc5665fa9, 0x71c9759f, 0xc560c9b3, 0x71c694d2, 0xc55b33e2,
+ 0x71c3b3bf, 0xc5559e34,
+ 0x71c0d265, 0xc55008ab, 0x71bdf0c5, 0xc54a7346, 0x71bb0edf, 0xc544de05,
+ 0x71b82cb3, 0xc53f48e9,
+ 0x71b54a41, 0xc539b3f1, 0x71b26788, 0xc5341f1d, 0x71af848a, 0xc52e8a6d,
+ 0x71aca145, 0xc528f5e1,
+ 0x71a9bdba, 0xc523617a, 0x71a6d9e9, 0xc51dcd37, 0x71a3f5d2, 0xc5183919,
+ 0x71a11175, 0xc512a51f,
+ 0x719e2cd2, 0xc50d1149, 0x719b47e9, 0xc5077d97, 0x719862b9, 0xc501ea0a,
+ 0x71957d44, 0xc4fc56a2,
+ 0x71929789, 0xc4f6c35d, 0x718fb187, 0xc4f1303d, 0x718ccb3f, 0xc4eb9d42,
+ 0x7189e4b2, 0xc4e60a6b,
+ 0x7186fdde, 0xc4e077b8, 0x718416c4, 0xc4dae52a, 0x71812f65, 0xc4d552c1,
+ 0x717e47bf, 0xc4cfc07c,
+ 0x717b5fd3, 0xc4ca2e5b, 0x717877a1, 0xc4c49c5f, 0x71758f29, 0xc4bf0a87,
+ 0x7172a66c, 0xc4b978d4,
+ 0x716fbd68, 0xc4b3e746, 0x716cd41e, 0xc4ae55dc, 0x7169ea8f, 0xc4a8c497,
+ 0x716700b9, 0xc4a33376,
+ 0x7164169d, 0xc49da27a, 0x71612c3c, 0xc49811a3, 0x715e4194, 0xc49280f0,
+ 0x715b56a7, 0xc48cf062,
+ 0x71586b74, 0xc4875ff9, 0x71557ffa, 0xc481cfb4, 0x7152943b, 0xc47c3f94,
+ 0x714fa836, 0xc476af98,
+ 0x714cbbeb, 0xc4711fc2, 0x7149cf5a, 0xc46b9010, 0x7146e284, 0xc4660083,
+ 0x7143f567, 0xc460711b,
+ 0x71410805, 0xc45ae1d7, 0x713e1a5c, 0xc45552b8, 0x713b2c6e, 0xc44fc3be,
+ 0x71383e3a, 0xc44a34e9,
+ 0x71354fc0, 0xc444a639, 0x71326101, 0xc43f17ad, 0x712f71fb, 0xc4398947,
+ 0x712c82b0, 0xc433fb05,
+ 0x7129931f, 0xc42e6ce8, 0x7126a348, 0xc428def0, 0x7123b32b, 0xc423511d,
+ 0x7120c2c8, 0xc41dc36f,
+ 0x711dd220, 0xc41835e6, 0x711ae132, 0xc412a882, 0x7117effe, 0xc40d1b42,
+ 0x7114fe84, 0xc4078e28,
+ 0x71120cc5, 0xc4020133, 0x710f1ac0, 0xc3fc7462, 0x710c2875, 0xc3f6e7b7,
+ 0x710935e4, 0xc3f15b31,
+ 0x7106430e, 0xc3ebced0, 0x71034ff2, 0xc3e64294, 0x71005c90, 0xc3e0b67d,
+ 0x70fd68e9, 0xc3db2a8b,
+ 0x70fa74fc, 0xc3d59ebe, 0x70f780c9, 0xc3d01316, 0x70f48c50, 0xc3ca8793,
+ 0x70f19792, 0xc3c4fc36,
+ 0x70eea28e, 0xc3bf70fd, 0x70ebad45, 0xc3b9e5ea, 0x70e8b7b5, 0xc3b45afc,
+ 0x70e5c1e1, 0xc3aed034,
+ 0x70e2cbc6, 0xc3a94590, 0x70dfd566, 0xc3a3bb12, 0x70dcdec0, 0xc39e30b8,
+ 0x70d9e7d5, 0xc398a685,
+ 0x70d6f0a4, 0xc3931c76, 0x70d3f92d, 0xc38d928d, 0x70d10171, 0xc38808c9,
+ 0x70ce096f, 0xc3827f2a,
+ 0x70cb1128, 0xc37cf5b0, 0x70c8189b, 0xc3776c5c, 0x70c51fc8, 0xc371e32d,
+ 0x70c226b0, 0xc36c5a24,
+ 0x70bf2d53, 0xc366d140, 0x70bc33b0, 0xc3614881, 0x70b939c7, 0xc35bbfe8,
+ 0x70b63f99, 0xc3563774,
+ 0x70b34525, 0xc350af26, 0x70b04a6b, 0xc34b26fc, 0x70ad4f6d, 0xc3459ef9,
+ 0x70aa5428, 0xc340171b,
+ 0x70a7589f, 0xc33a8f62, 0x70a45ccf, 0xc33507cf, 0x70a160ba, 0xc32f8061,
+ 0x709e6460, 0xc329f919,
+ 0x709b67c0, 0xc32471f7, 0x70986adb, 0xc31eeaf9, 0x70956db1, 0xc3196422,
+ 0x70927041, 0xc313dd70,
+ 0x708f728b, 0xc30e56e4, 0x708c7490, 0xc308d07d, 0x70897650, 0xc3034a3c,
+ 0x708677ca, 0xc2fdc420,
+ 0x708378ff, 0xc2f83e2a, 0x708079ee, 0xc2f2b85a, 0x707d7a98, 0xc2ed32af,
+ 0x707a7afd, 0xc2e7ad2a,
+ 0x70777b1c, 0xc2e227cb, 0x70747af6, 0xc2dca291, 0x70717a8a, 0xc2d71d7e,
+ 0x706e79d9, 0xc2d1988f,
+ 0x706b78e3, 0xc2cc13c7, 0x706877a7, 0xc2c68f24, 0x70657626, 0xc2c10aa7,
+ 0x70627460, 0xc2bb8650,
+ 0x705f7255, 0xc2b6021f, 0x705c7004, 0xc2b07e14, 0x70596d6d, 0xc2aafa2e,
+ 0x70566a92, 0xc2a5766e,
+ 0x70536771, 0xc29ff2d4, 0x7050640b, 0xc29a6f60, 0x704d6060, 0xc294ec12,
+ 0x704a5c6f, 0xc28f68e9,
+ 0x70475839, 0xc289e5e7, 0x704453be, 0xc284630a, 0x70414efd, 0xc27ee054,
+ 0x703e49f8, 0xc2795dc3,
+ 0x703b44ad, 0xc273db58, 0x70383f1d, 0xc26e5913, 0x70353947, 0xc268d6f5,
+ 0x7032332d, 0xc26354fc,
+ 0x702f2ccd, 0xc25dd329, 0x702c2628, 0xc258517c, 0x70291f3e, 0xc252cff5,
+ 0x7026180e, 0xc24d4e95,
+ 0x7023109a, 0xc247cd5a, 0x702008e0, 0xc2424c46, 0x701d00e1, 0xc23ccb57,
+ 0x7019f89d, 0xc2374a8f,
+ 0x7016f014, 0xc231c9ec, 0x7013e746, 0xc22c4970, 0x7010de32, 0xc226c91a,
+ 0x700dd4da, 0xc22148ea,
+ 0x700acb3c, 0xc21bc8e1, 0x7007c159, 0xc21648fd, 0x7004b731, 0xc210c940,
+ 0x7001acc4, 0xc20b49a9,
+ 0x6ffea212, 0xc205ca38, 0x6ffb971b, 0xc2004aed, 0x6ff88bde, 0xc1facbc9,
+ 0x6ff5805d, 0xc1f54cca,
+ 0x6ff27497, 0xc1efcdf3, 0x6fef688b, 0xc1ea4f41, 0x6fec5c3b, 0xc1e4d0b6,
+ 0x6fe94fa5, 0xc1df5251,
+ 0x6fe642ca, 0xc1d9d412, 0x6fe335ab, 0xc1d455f9, 0x6fe02846, 0xc1ced807,
+ 0x6fdd1a9c, 0xc1c95a3c,
+ 0x6fda0cae, 0xc1c3dc97, 0x6fd6fe7a, 0xc1be5f18, 0x6fd3f001, 0xc1b8e1bf,
+ 0x6fd0e144, 0xc1b3648d,
+ 0x6fcdd241, 0xc1ade781, 0x6fcac2fa, 0xc1a86a9c, 0x6fc7b36d, 0xc1a2edde,
+ 0x6fc4a39c, 0xc19d7145,
+ 0x6fc19385, 0xc197f4d4, 0x6fbe832a, 0xc1927888, 0x6fbb728a, 0xc18cfc63,
+ 0x6fb861a4, 0xc1878065,
+ 0x6fb5507a, 0xc182048d, 0x6fb23f0b, 0xc17c88dc, 0x6faf2d57, 0xc1770d52,
+ 0x6fac1b5f, 0xc17191ee,
+ 0x6fa90921, 0xc16c16b0, 0x6fa5f69e, 0xc1669b99, 0x6fa2e3d7, 0xc16120a9,
+ 0x6f9fd0cb, 0xc15ba5df,
+ 0x6f9cbd79, 0xc1562b3d, 0x6f99a9e3, 0xc150b0c0, 0x6f969608, 0xc14b366b,
+ 0x6f9381e9, 0xc145bc3c,
+ 0x6f906d84, 0xc1404233, 0x6f8d58db, 0xc13ac852, 0x6f8a43ed, 0xc1354e97,
+ 0x6f872eba, 0xc12fd503,
+ 0x6f841942, 0xc12a5b95, 0x6f810386, 0xc124e24f, 0x6f7ded84, 0xc11f692f,
+ 0x6f7ad73e, 0xc119f036,
+ 0x6f77c0b3, 0xc1147764, 0x6f74a9e4, 0xc10efeb8, 0x6f7192cf, 0xc1098634,
+ 0x6f6e7b76, 0xc1040dd6,
+ 0x6f6b63d8, 0xc0fe959f, 0x6f684bf6, 0xc0f91d8f, 0x6f6533ce, 0xc0f3a5a6,
+ 0x6f621b62, 0xc0ee2de3,
+ 0x6f5f02b2, 0xc0e8b648, 0x6f5be9bc, 0xc0e33ed4, 0x6f58d082, 0xc0ddc786,
+ 0x6f55b703, 0xc0d8505f,
+ 0x6f529d40, 0xc0d2d960, 0x6f4f8338, 0xc0cd6287, 0x6f4c68eb, 0xc0c7ebd6,
+ 0x6f494e5a, 0xc0c2754b,
+ 0x6f463383, 0xc0bcfee7, 0x6f431869, 0xc0b788ab, 0x6f3ffd09, 0xc0b21295,
+ 0x6f3ce165, 0xc0ac9ca6,
+ 0x6f39c57d, 0xc0a726df, 0x6f36a94f, 0xc0a1b13e, 0x6f338cde, 0xc09c3bc5,
+ 0x6f307027, 0xc096c673,
+ 0x6f2d532c, 0xc0915148, 0x6f2a35ed, 0xc08bdc44, 0x6f271868, 0xc0866767,
+ 0x6f23faa0, 0xc080f2b1,
+ 0x6f20dc92, 0xc07b7e23, 0x6f1dbe41, 0xc07609bb, 0x6f1a9faa, 0xc070957b,
+ 0x6f1780cf, 0xc06b2162,
+ 0x6f1461b0, 0xc065ad70, 0x6f11424c, 0xc06039a6, 0x6f0e22a3, 0xc05ac603,
+ 0x6f0b02b6, 0xc0555287,
+ 0x6f07e285, 0xc04fdf32, 0x6f04c20f, 0xc04a6c05, 0x6f01a155, 0xc044f8fe,
+ 0x6efe8056, 0xc03f8620,
+ 0x6efb5f12, 0xc03a1368, 0x6ef83d8a, 0xc034a0d8, 0x6ef51bbe, 0xc02f2e6f,
+ 0x6ef1f9ad, 0xc029bc2e,
+ 0x6eeed758, 0xc0244a14, 0x6eebb4bf, 0xc01ed821, 0x6ee891e1, 0xc0196656,
+ 0x6ee56ebe, 0xc013f4b2,
+ 0x6ee24b57, 0xc00e8336, 0x6edf27ac, 0xc00911e1, 0x6edc03bc, 0xc003a0b3,
+ 0x6ed8df88, 0xbffe2fad,
+ 0x6ed5bb10, 0xbff8bece, 0x6ed29653, 0xbff34e17, 0x6ecf7152, 0xbfeddd88,
+ 0x6ecc4c0d, 0xbfe86d20,
+ 0x6ec92683, 0xbfe2fcdf, 0x6ec600b5, 0xbfdd8cc6, 0x6ec2daa2, 0xbfd81cd5,
+ 0x6ebfb44b, 0xbfd2ad0b,
+ 0x6ebc8db0, 0xbfcd3d69, 0x6eb966d1, 0xbfc7cdee, 0x6eb63fad, 0xbfc25e9b,
+ 0x6eb31845, 0xbfbcef70,
+ 0x6eaff099, 0xbfb7806c, 0x6eacc8a8, 0xbfb21190, 0x6ea9a073, 0xbfaca2dc,
+ 0x6ea677fa, 0xbfa7344f,
+ 0x6ea34f3d, 0xbfa1c5ea, 0x6ea0263b, 0xbf9c57ac, 0x6e9cfcf5, 0xbf96e997,
+ 0x6e99d36b, 0xbf917ba9,
+ 0x6e96a99d, 0xbf8c0de3, 0x6e937f8a, 0xbf86a044, 0x6e905534, 0xbf8132ce,
+ 0x6e8d2a99, 0xbf7bc57f,
+ 0x6e89ffb9, 0xbf765858, 0x6e86d496, 0xbf70eb59, 0x6e83a92f, 0xbf6b7e81,
+ 0x6e807d83, 0xbf6611d2,
+ 0x6e7d5193, 0xbf60a54a, 0x6e7a255f, 0xbf5b38ea, 0x6e76f8e7, 0xbf55ccb2,
+ 0x6e73cc2b, 0xbf5060a2,
+ 0x6e709f2a, 0xbf4af4ba, 0x6e6d71e6, 0xbf4588fa, 0x6e6a445d, 0xbf401d61,
+ 0x6e671690, 0xbf3ab1f1,
+ 0x6e63e87f, 0xbf3546a8, 0x6e60ba2a, 0xbf2fdb88, 0x6e5d8b91, 0xbf2a708f,
+ 0x6e5a5cb4, 0xbf2505bf,
+ 0x6e572d93, 0xbf1f9b16, 0x6e53fe2e, 0xbf1a3096, 0x6e50ce84, 0xbf14c63d,
+ 0x6e4d9e97, 0xbf0f5c0d,
+ 0x6e4a6e66, 0xbf09f205, 0x6e473df0, 0xbf048824, 0x6e440d37, 0xbeff1e6c,
+ 0x6e40dc39, 0xbef9b4dc,
+ 0x6e3daaf8, 0xbef44b74, 0x6e3a7972, 0xbeeee234, 0x6e3747a9, 0xbee9791c,
+ 0x6e34159b, 0xbee4102d,
+ 0x6e30e34a, 0xbedea765, 0x6e2db0b4, 0xbed93ec6, 0x6e2a7ddb, 0xbed3d64f,
+ 0x6e274abe, 0xbece6e00,
+ 0x6e24175c, 0xbec905d9, 0x6e20e3b7, 0xbec39ddb, 0x6e1dafce, 0xbebe3605,
+ 0x6e1a7ba1, 0xbeb8ce57,
+ 0x6e174730, 0xbeb366d1, 0x6e14127b, 0xbeadff74, 0x6e10dd82, 0xbea8983f,
+ 0x6e0da845, 0xbea33132,
+ 0x6e0a72c5, 0xbe9dca4e, 0x6e073d00, 0xbe986391, 0x6e0406f8, 0xbe92fcfe,
+ 0x6e00d0ac, 0xbe8d9692,
+ 0x6dfd9a1c, 0xbe88304f, 0x6dfa6348, 0xbe82ca35, 0x6df72c30, 0xbe7d6442,
+ 0x6df3f4d4, 0xbe77fe78,
+ 0x6df0bd35, 0xbe7298d7, 0x6ded8552, 0xbe6d335e, 0x6dea4d2b, 0xbe67ce0d,
+ 0x6de714c0, 0xbe6268e5,
+ 0x6de3dc11, 0xbe5d03e6, 0x6de0a31f, 0xbe579f0f, 0x6ddd69e9, 0xbe523a60,
+ 0x6dda306f, 0xbe4cd5da,
+ 0x6dd6f6b1, 0xbe47717c, 0x6dd3bcaf, 0xbe420d47, 0x6dd0826a, 0xbe3ca93b,
+ 0x6dcd47e1, 0xbe374557,
+ 0x6dca0d14, 0xbe31e19b, 0x6dc6d204, 0xbe2c7e09, 0x6dc396b0, 0xbe271a9f,
+ 0x6dc05b18, 0xbe21b75d,
+ 0x6dbd1f3c, 0xbe1c5444, 0x6db9e31d, 0xbe16f154, 0x6db6a6ba, 0xbe118e8c,
+ 0x6db36a14, 0xbe0c2bed,
+ 0x6db02d29, 0xbe06c977, 0x6daceffb, 0xbe01672a, 0x6da9b28a, 0xbdfc0505,
+ 0x6da674d5, 0xbdf6a309,
+ 0x6da336dc, 0xbdf14135, 0x6d9ff89f, 0xbdebdf8b, 0x6d9cba1f, 0xbde67e09,
+ 0x6d997b5b, 0xbde11cb0,
+ 0x6d963c54, 0xbddbbb7f, 0x6d92fd09, 0xbdd65a78, 0x6d8fbd7a, 0xbdd0f999,
+ 0x6d8c7da8, 0xbdcb98e3,
+ 0x6d893d93, 0xbdc63856, 0x6d85fd39, 0xbdc0d7f2, 0x6d82bc9d, 0xbdbb77b7,
+ 0x6d7f7bbc, 0xbdb617a4,
+ 0x6d7c3a98, 0xbdb0b7bb, 0x6d78f931, 0xbdab57fa, 0x6d75b786, 0xbda5f862,
+ 0x6d727597, 0xbda098f3,
+ 0x6d6f3365, 0xbd9b39ad, 0x6d6bf0f0, 0xbd95da91, 0x6d68ae37, 0xbd907b9d,
+ 0x6d656b3a, 0xbd8b1cd2,
+ 0x6d6227fa, 0xbd85be30, 0x6d5ee477, 0xbd805fb7, 0x6d5ba0b0, 0xbd7b0167,
+ 0x6d585ca6, 0xbd75a340,
+ 0x6d551858, 0xbd704542, 0x6d51d3c6, 0xbd6ae76d, 0x6d4e8ef2, 0xbd6589c1,
+ 0x6d4b49da, 0xbd602c3f,
+ 0x6d48047e, 0xbd5acee5, 0x6d44bedf, 0xbd5571b5, 0x6d4178fd, 0xbd5014ad,
+ 0x6d3e32d7, 0xbd4ab7cf,
+ 0x6d3aec6e, 0xbd455b1a, 0x6d37a5c1, 0xbd3ffe8e, 0x6d345ed1, 0xbd3aa22c,
+ 0x6d31179e, 0xbd3545f2,
+ 0x6d2dd027, 0xbd2fe9e2, 0x6d2a886e, 0xbd2a8dfb, 0x6d274070, 0xbd25323d,
+ 0x6d23f830, 0xbd1fd6a8,
+ 0x6d20afac, 0xbd1a7b3d, 0x6d1d66e4, 0xbd151ffb, 0x6d1a1dda, 0xbd0fc4e2,
+ 0x6d16d48c, 0xbd0a69f2,
+ 0x6d138afb, 0xbd050f2c, 0x6d104126, 0xbcffb48f, 0x6d0cf70f, 0xbcfa5a1b,
+ 0x6d09acb4, 0xbcf4ffd1,
+ 0x6d066215, 0xbcefa5b0, 0x6d031734, 0xbcea4bb9, 0x6cffcc0f, 0xbce4f1eb,
+ 0x6cfc80a7, 0xbcdf9846,
+ 0x6cf934fc, 0xbcda3ecb, 0x6cf5e90d, 0xbcd4e579, 0x6cf29cdc, 0xbccf8c50,
+ 0x6cef5067, 0xbcca3351,
+ 0x6cec03af, 0xbcc4da7b, 0x6ce8b6b4, 0xbcbf81cf, 0x6ce56975, 0xbcba294d,
+ 0x6ce21bf4, 0xbcb4d0f4,
+ 0x6cdece2f, 0xbcaf78c4, 0x6cdb8027, 0xbcaa20be, 0x6cd831dc, 0xbca4c8e1,
+ 0x6cd4e34e, 0xbc9f712e,
+ 0x6cd1947c, 0xbc9a19a5, 0x6cce4568, 0xbc94c245, 0x6ccaf610, 0xbc8f6b0f,
+ 0x6cc7a676, 0xbc8a1402,
+ 0x6cc45698, 0xbc84bd1f, 0x6cc10677, 0xbc7f6665, 0x6cbdb613, 0xbc7a0fd6,
+ 0x6cba656c, 0xbc74b96f,
+ 0x6cb71482, 0xbc6f6333, 0x6cb3c355, 0xbc6a0d20, 0x6cb071e4, 0xbc64b737,
+ 0x6cad2031, 0xbc5f6177,
+ 0x6ca9ce3b, 0xbc5a0be2, 0x6ca67c01, 0xbc54b676, 0x6ca32985, 0xbc4f6134,
+ 0x6c9fd6c6, 0xbc4a0c1b,
+ 0x6c9c83c3, 0xbc44b72c, 0x6c99307e, 0xbc3f6267, 0x6c95dcf6, 0xbc3a0dcc,
+ 0x6c92892a, 0xbc34b95b,
+ 0x6c8f351c, 0xbc2f6513, 0x6c8be0cb, 0xbc2a10f6, 0x6c888c36, 0xbc24bd02,
+ 0x6c85375f, 0xbc1f6938,
+ 0x6c81e245, 0xbc1a1598, 0x6c7e8ce8, 0xbc14c221, 0x6c7b3748, 0xbc0f6ed5,
+ 0x6c77e165, 0xbc0a1bb3,
+ 0x6c748b3f, 0xbc04c8ba, 0x6c7134d7, 0xbbff75ec, 0x6c6dde2b, 0xbbfa2347,
+ 0x6c6a873d, 0xbbf4d0cc,
+ 0x6c67300b, 0xbbef7e7c, 0x6c63d897, 0xbbea2c55, 0x6c6080e0, 0xbbe4da58,
+ 0x6c5d28e6, 0xbbdf8885,
+ 0x6c59d0a9, 0xbbda36dd, 0x6c56782a, 0xbbd4e55e, 0x6c531f67, 0xbbcf940a,
+ 0x6c4fc662, 0xbbca42df,
+ 0x6c4c6d1a, 0xbbc4f1df, 0x6c49138f, 0xbbbfa108, 0x6c45b9c1, 0xbbba505c,
+ 0x6c425fb1, 0xbbb4ffda,
+ 0x6c3f055d, 0xbbafaf82, 0x6c3baac7, 0xbbaa5f54, 0x6c384fef, 0xbba50f50,
+ 0x6c34f4d3, 0xbb9fbf77,
+ 0x6c319975, 0xbb9a6fc7, 0x6c2e3dd4, 0xbb952042, 0x6c2ae1f0, 0xbb8fd0e7,
+ 0x6c2785ca, 0xbb8a81b6,
+ 0x6c242960, 0xbb8532b0, 0x6c20ccb4, 0xbb7fe3d3, 0x6c1d6fc6, 0xbb7a9521,
+ 0x6c1a1295, 0xbb754699,
+ 0x6c16b521, 0xbb6ff83c, 0x6c13576a, 0xbb6aaa09, 0x6c0ff971, 0xbb655c00,
+ 0x6c0c9b35, 0xbb600e21,
+ 0x6c093cb6, 0xbb5ac06d, 0x6c05ddf5, 0xbb5572e3, 0x6c027ef1, 0xbb502583,
+ 0x6bff1faa, 0xbb4ad84e,
+ 0x6bfbc021, 0xbb458b43, 0x6bf86055, 0xbb403e63, 0x6bf50047, 0xbb3af1ad,
+ 0x6bf19ff6, 0xbb35a521,
+ 0x6bee3f62, 0xbb3058c0, 0x6beade8c, 0xbb2b0c8a, 0x6be77d74, 0xbb25c07d,
+ 0x6be41c18, 0xbb20749c,
+ 0x6be0ba7b, 0xbb1b28e4, 0x6bdd589a, 0xbb15dd57, 0x6bd9f677, 0xbb1091f5,
+ 0x6bd69412, 0xbb0b46bd,
+ 0x6bd3316a, 0xbb05fbb0, 0x6bcfce80, 0xbb00b0ce, 0x6bcc6b53, 0xbafb6615,
+ 0x6bc907e3, 0xbaf61b88,
+ 0x6bc5a431, 0xbaf0d125, 0x6bc2403d, 0xbaeb86ed, 0x6bbedc06, 0xbae63cdf,
+ 0x6bbb778d, 0xbae0f2fc,
+ 0x6bb812d1, 0xbadba943, 0x6bb4add3, 0xbad65fb5, 0x6bb14892, 0xbad11652,
+ 0x6bade30f, 0xbacbcd1a,
+ 0x6baa7d49, 0xbac6840c, 0x6ba71741, 0xbac13b29, 0x6ba3b0f7, 0xbabbf270,
+ 0x6ba04a6a, 0xbab6a9e3,
+ 0x6b9ce39b, 0xbab16180, 0x6b997c8a, 0xbaac1948, 0x6b961536, 0xbaa6d13a,
+ 0x6b92ada0, 0xbaa18958,
+ 0x6b8f45c7, 0xba9c41a0, 0x6b8bddac, 0xba96fa13, 0x6b88754f, 0xba91b2b1,
+ 0x6b850caf, 0xba8c6b79,
+ 0x6b81a3cd, 0xba87246d, 0x6b7e3aa9, 0xba81dd8b, 0x6b7ad142, 0xba7c96d4,
+ 0x6b776799, 0xba775048,
+ 0x6b73fdae, 0xba7209e7, 0x6b709381, 0xba6cc3b1, 0x6b6d2911, 0xba677da6,
+ 0x6b69be5f, 0xba6237c5,
+ 0x6b66536b, 0xba5cf210, 0x6b62e834, 0xba57ac86, 0x6b5f7cbc, 0xba526726,
+ 0x6b5c1101, 0xba4d21f2,
+ 0x6b58a503, 0xba47dce8, 0x6b5538c4, 0xba42980a, 0x6b51cc42, 0xba3d5356,
+ 0x6b4e5f7f, 0xba380ece,
+ 0x6b4af279, 0xba32ca71, 0x6b478530, 0xba2d863e, 0x6b4417a6, 0xba284237,
+ 0x6b40a9d9, 0xba22fe5b,
+ 0x6b3d3bcb, 0xba1dbaaa, 0x6b39cd7a, 0xba187724, 0x6b365ee7, 0xba1333c9,
+ 0x6b32f012, 0xba0df099,
+ 0x6b2f80fb, 0xba08ad95, 0x6b2c11a1, 0xba036abb, 0x6b28a206, 0xb9fe280d,
+ 0x6b253228, 0xb9f8e58a,
+ 0x6b21c208, 0xb9f3a332, 0x6b1e51a7, 0xb9ee6106, 0x6b1ae103, 0xb9e91f04,
+ 0x6b17701d, 0xb9e3dd2e,
+ 0x6b13fef5, 0xb9de9b83, 0x6b108d8b, 0xb9d95a03, 0x6b0d1bdf, 0xb9d418af,
+ 0x6b09a9f1, 0xb9ced786,
+ 0x6b0637c1, 0xb9c99688, 0x6b02c54f, 0xb9c455b6, 0x6aff529a, 0xb9bf150e,
+ 0x6afbdfa4, 0xb9b9d493,
+ 0x6af86c6c, 0xb9b49442, 0x6af4f8f2, 0xb9af541d, 0x6af18536, 0xb9aa1423,
+ 0x6aee1138, 0xb9a4d455,
+ 0x6aea9cf8, 0xb99f94b2, 0x6ae72876, 0xb99a553a, 0x6ae3b3b2, 0xb99515ee,
+ 0x6ae03eac, 0xb98fd6cd,
+ 0x6adcc964, 0xb98a97d8, 0x6ad953db, 0xb985590e, 0x6ad5de0f, 0xb9801a70,
+ 0x6ad26802, 0xb97adbfd,
+ 0x6acef1b2, 0xb9759db6, 0x6acb7b21, 0xb9705f9a, 0x6ac8044e, 0xb96b21aa,
+ 0x6ac48d39, 0xb965e3e5,
+ 0x6ac115e2, 0xb960a64c, 0x6abd9e49, 0xb95b68de, 0x6aba266e, 0xb9562b9c,
+ 0x6ab6ae52, 0xb950ee86,
+ 0x6ab335f4, 0xb94bb19b, 0x6aafbd54, 0xb94674dc, 0x6aac4472, 0xb9413848,
+ 0x6aa8cb4e, 0xb93bfbe0,
+ 0x6aa551e9, 0xb936bfa4, 0x6aa1d841, 0xb9318393, 0x6a9e5e58, 0xb92c47ae,
+ 0x6a9ae42e, 0xb9270bf5,
+ 0x6a9769c1, 0xb921d067, 0x6a93ef13, 0xb91c9505, 0x6a907423, 0xb91759cf,
+ 0x6a8cf8f1, 0xb9121ec5,
+ 0x6a897d7d, 0xb90ce3e6, 0x6a8601c8, 0xb907a933, 0x6a8285d1, 0xb9026eac,
+ 0x6a7f0999, 0xb8fd3451,
+ 0x6a7b8d1e, 0xb8f7fa21, 0x6a781062, 0xb8f2c01d, 0x6a749365, 0xb8ed8646,
+ 0x6a711625, 0xb8e84c99,
+ 0x6a6d98a4, 0xb8e31319, 0x6a6a1ae2, 0xb8ddd9c5, 0x6a669cdd, 0xb8d8a09d,
+ 0x6a631e97, 0xb8d367a0,
+ 0x6a5fa010, 0xb8ce2ecf, 0x6a5c2147, 0xb8c8f62b, 0x6a58a23c, 0xb8c3bdb2,
+ 0x6a5522ef, 0xb8be8565,
+ 0x6a51a361, 0xb8b94d44, 0x6a4e2392, 0xb8b4154f, 0x6a4aa381, 0xb8aedd86,
+ 0x6a47232e, 0xb8a9a5e9,
+ 0x6a43a29a, 0xb8a46e78, 0x6a4021c4, 0xb89f3733, 0x6a3ca0ad, 0xb89a001a,
+ 0x6a391f54, 0xb894c92d,
+ 0x6a359db9, 0xb88f926d, 0x6a321bdd, 0xb88a5bd8, 0x6a2e99c0, 0xb885256f,
+ 0x6a2b1761, 0xb87fef33,
+ 0x6a2794c1, 0xb87ab922, 0x6a2411df, 0xb875833e, 0x6a208ebb, 0xb8704d85,
+ 0x6a1d0b57, 0xb86b17f9,
+ 0x6a1987b0, 0xb865e299, 0x6a1603c8, 0xb860ad66, 0x6a127f9f, 0xb85b785e,
+ 0x6a0efb35, 0xb8564383,
+ 0x6a0b7689, 0xb8510ed4, 0x6a07f19b, 0xb84bda51, 0x6a046c6c, 0xb846a5fa,
+ 0x6a00e6fc, 0xb84171cf,
+ 0x69fd614a, 0xb83c3dd1, 0x69f9db57, 0xb83709ff, 0x69f65523, 0xb831d659,
+ 0x69f2cead, 0xb82ca2e0,
+ 0x69ef47f6, 0xb8276f93, 0x69ebc0fe, 0xb8223c72, 0x69e839c4, 0xb81d097e,
+ 0x69e4b249, 0xb817d6b6,
+ 0x69e12a8c, 0xb812a41a, 0x69dda28f, 0xb80d71aa, 0x69da1a50, 0xb8083f67,
+ 0x69d691cf, 0xb8030d51,
+ 0x69d3090e, 0xb7fddb67, 0x69cf800b, 0xb7f8a9a9, 0x69cbf6c7, 0xb7f37818,
+ 0x69c86d41, 0xb7ee46b3,
+ 0x69c4e37a, 0xb7e9157a, 0x69c15973, 0xb7e3e46e, 0x69bdcf29, 0xb7deb38f,
+ 0x69ba449f, 0xb7d982dc,
+ 0x69b6b9d3, 0xb7d45255, 0x69b32ec7, 0xb7cf21fb, 0x69afa378, 0xb7c9f1ce,
+ 0x69ac17e9, 0xb7c4c1cd,
+ 0x69a88c19, 0xb7bf91f8, 0x69a50007, 0xb7ba6251, 0x69a173b5, 0xb7b532d6,
+ 0x699de721, 0xb7b00387,
+ 0x699a5a4c, 0xb7aad465, 0x6996cd35, 0xb7a5a570, 0x69933fde, 0xb7a076a7,
+ 0x698fb246, 0xb79b480b,
+ 0x698c246c, 0xb796199b, 0x69889651, 0xb790eb58, 0x698507f6, 0xb78bbd42,
+ 0x69817959, 0xb7868f59,
+ 0x697dea7b, 0xb781619c, 0x697a5b5c, 0xb77c340c, 0x6976cbfc, 0xb77706a9,
+ 0x69733c5b, 0xb771d972,
+ 0x696fac78, 0xb76cac69, 0x696c1c55, 0xb7677f8c, 0x69688bf1, 0xb76252db,
+ 0x6964fb4c, 0xb75d2658,
+ 0x69616a65, 0xb757fa01, 0x695dd93e, 0xb752cdd8, 0x695a47d6, 0xb74da1db,
+ 0x6956b62d, 0xb748760b,
+ 0x69532442, 0xb7434a67, 0x694f9217, 0xb73e1ef1, 0x694bffab, 0xb738f3a7,
+ 0x69486cfe, 0xb733c88b,
+ 0x6944da10, 0xb72e9d9b, 0x694146e1, 0xb72972d8, 0x693db371, 0xb7244842,
+ 0x693a1fc0, 0xb71f1dd9,
+ 0x69368bce, 0xb719f39e, 0x6932f79b, 0xb714c98e, 0x692f6328, 0xb70f9fac,
+ 0x692bce73, 0xb70a75f7,
+ 0x6928397e, 0xb7054c6f, 0x6924a448, 0xb7002314, 0x69210ed1, 0xb6faf9e6,
+ 0x691d7919, 0xb6f5d0e5,
+ 0x6919e320, 0xb6f0a812, 0x69164ce7, 0xb6eb7f6b, 0x6912b66c, 0xb6e656f1,
+ 0x690f1fb1, 0xb6e12ea4,
+ 0x690b88b5, 0xb6dc0685, 0x6907f178, 0xb6d6de92, 0x690459fb, 0xb6d1b6cd,
+ 0x6900c23c, 0xb6cc8f35,
+ 0x68fd2a3d, 0xb6c767ca, 0x68f991fd, 0xb6c2408c, 0x68f5f97d, 0xb6bd197c,
+ 0x68f260bb, 0xb6b7f298,
+ 0x68eec7b9, 0xb6b2cbe2, 0x68eb2e76, 0xb6ada559, 0x68e794f3, 0xb6a87efd,
+ 0x68e3fb2e, 0xb6a358ce,
+ 0x68e06129, 0xb69e32cd, 0x68dcc6e4, 0xb6990cf9, 0x68d92c5d, 0xb693e752,
+ 0x68d59196, 0xb68ec1d9,
+ 0x68d1f68f, 0xb6899c8d, 0x68ce5b46, 0xb684776e, 0x68cabfbd, 0xb67f527c,
+ 0x68c723f3, 0xb67a2db8,
+ 0x68c387e9, 0xb6750921, 0x68bfeb9e, 0xb66fe4b8, 0x68bc4f13, 0xb66ac07c,
+ 0x68b8b247, 0xb6659c6d,
+ 0x68b5153a, 0xb660788c, 0x68b177ed, 0xb65b54d8, 0x68adda5f, 0xb6563151,
+ 0x68aa3c90, 0xb6510df8,
+ 0x68a69e81, 0xb64beacd, 0x68a30031, 0xb646c7ce, 0x689f61a1, 0xb641a4fe,
+ 0x689bc2d1, 0xb63c825b,
+ 0x689823bf, 0xb6375fe5, 0x6894846e, 0xb6323d9d, 0x6890e4dc, 0xb62d1b82,
+ 0x688d4509, 0xb627f995,
+ 0x6889a4f6, 0xb622d7d6, 0x688604a2, 0xb61db644, 0x6882640e, 0xb61894df,
+ 0x687ec339, 0xb61373a9,
+ 0x687b2224, 0xb60e529f, 0x687780ce, 0xb60931c4, 0x6873df38, 0xb6041116,
+ 0x68703d62, 0xb5fef095,
+ 0x686c9b4b, 0xb5f9d043, 0x6868f8f4, 0xb5f4b01e, 0x6865565c, 0xb5ef9026,
+ 0x6861b384, 0xb5ea705d,
+ 0x685e106c, 0xb5e550c1, 0x685a6d13, 0xb5e03153, 0x6856c979, 0xb5db1212,
+ 0x685325a0, 0xb5d5f2ff,
+ 0x684f8186, 0xb5d0d41a, 0x684bdd2c, 0xb5cbb563, 0x68483891, 0xb5c696da,
+ 0x684493b6, 0xb5c1787e,
+ 0x6840ee9b, 0xb5bc5a50, 0x683d493f, 0xb5b73c50, 0x6839a3a4, 0xb5b21e7e,
+ 0x6835fdc7, 0xb5ad00d9,
+ 0x683257ab, 0xb5a7e362, 0x682eb14e, 0xb5a2c61a, 0x682b0ab1, 0xb59da8ff,
+ 0x682763d4, 0xb5988c12,
+ 0x6823bcb7, 0xb5936f53, 0x68201559, 0xb58e52c2, 0x681c6dbb, 0xb589365e,
+ 0x6818c5dd, 0xb5841a29,
+ 0x68151dbe, 0xb57efe22, 0x68117560, 0xb579e248, 0x680dccc1, 0xb574c69d,
+ 0x680a23e2, 0xb56fab1f,
+ 0x68067ac3, 0xb56a8fd0, 0x6802d164, 0xb56574ae, 0x67ff27c4, 0xb56059bb,
+ 0x67fb7de5, 0xb55b3ef5,
+ 0x67f7d3c5, 0xb556245e, 0x67f42965, 0xb55109f5, 0x67f07ec5, 0xb54befba,
+ 0x67ecd3e5, 0xb546d5ac,
+ 0x67e928c5, 0xb541bbcd, 0x67e57d64, 0xb53ca21c, 0x67e1d1c4, 0xb5378899,
+ 0x67de25e3, 0xb5326f45,
+ 0x67da79c3, 0xb52d561e, 0x67d6cd62, 0xb5283d26, 0x67d320c1, 0xb523245b,
+ 0x67cf73e1, 0xb51e0bbf,
+ 0x67cbc6c0, 0xb518f351, 0x67c8195f, 0xb513db12, 0x67c46bbe, 0xb50ec300,
+ 0x67c0bddd, 0xb509ab1d,
+ 0x67bd0fbd, 0xb5049368, 0x67b9615c, 0xb4ff7be1, 0x67b5b2bb, 0xb4fa6489,
+ 0x67b203da, 0xb4f54d5f,
+ 0x67ae54ba, 0xb4f03663, 0x67aaa559, 0xb4eb1f95, 0x67a6f5b8, 0xb4e608f6,
+ 0x67a345d8, 0xb4e0f285,
+ 0x679f95b7, 0xb4dbdc42, 0x679be557, 0xb4d6c62e, 0x679834b6, 0xb4d1b048,
+ 0x679483d6, 0xb4cc9a90,
+ 0x6790d2b6, 0xb4c78507, 0x678d2156, 0xb4c26fad, 0x67896fb6, 0xb4bd5a80,
+ 0x6785bdd6, 0xb4b84582,
+ 0x67820bb7, 0xb4b330b3, 0x677e5957, 0xb4ae1c12, 0x677aa6b8, 0xb4a9079f,
+ 0x6776f3d9, 0xb4a3f35b,
+ 0x677340ba, 0xb49edf45, 0x676f8d5b, 0xb499cb5e, 0x676bd9bd, 0xb494b7a6,
+ 0x676825de, 0xb48fa41c,
+ 0x676471c0, 0xb48a90c0, 0x6760bd62, 0xb4857d93, 0x675d08c4, 0xb4806a95,
+ 0x675953e7, 0xb47b57c5,
+ 0x67559eca, 0xb4764523, 0x6751e96d, 0xb47132b1, 0x674e33d0, 0xb46c206d,
+ 0x674a7df4, 0xb4670e57,
+ 0x6746c7d8, 0xb461fc70, 0x6743117c, 0xb45ceab8, 0x673f5ae0, 0xb457d92f,
+ 0x673ba405, 0xb452c7d4,
+ 0x6737ecea, 0xb44db6a8, 0x67343590, 0xb448a5aa, 0x67307df5, 0xb44394db,
+ 0x672cc61c, 0xb43e843b,
+ 0x67290e02, 0xb43973ca, 0x672555a9, 0xb4346387, 0x67219d10, 0xb42f5373,
+ 0x671de438, 0xb42a438e,
+ 0x671a2b20, 0xb42533d8, 0x671671c8, 0xb4202451, 0x6712b831, 0xb41b14f8,
+ 0x670efe5a, 0xb41605ce,
+ 0x670b4444, 0xb410f6d3, 0x670789ee, 0xb40be807, 0x6703cf58, 0xb406d969,
+ 0x67001483, 0xb401cafb,
+ 0x66fc596f, 0xb3fcbcbb, 0x66f89e1b, 0xb3f7aeaa, 0x66f4e287, 0xb3f2a0c9,
+ 0x66f126b4, 0xb3ed9316,
+ 0x66ed6aa1, 0xb3e88592, 0x66e9ae4f, 0xb3e3783d, 0x66e5f1be, 0xb3de6b17,
+ 0x66e234ed, 0xb3d95e1f,
+ 0x66de77dc, 0xb3d45157, 0x66daba8c, 0xb3cf44be, 0x66d6fcfd, 0xb3ca3854,
+ 0x66d33f2e, 0xb3c52c19,
+ 0x66cf8120, 0xb3c0200c, 0x66cbc2d2, 0xb3bb142f, 0x66c80445, 0xb3b60881,
+ 0x66c44579, 0xb3b0fd02,
+ 0x66c0866d, 0xb3abf1b2, 0x66bcc721, 0xb3a6e691, 0x66b90797, 0xb3a1dba0,
+ 0x66b547cd, 0xb39cd0dd,
+ 0x66b187c3, 0xb397c649, 0x66adc77b, 0xb392bbe5, 0x66aa06f3, 0xb38db1b0,
+ 0x66a6462b, 0xb388a7aa,
+ 0x66a28524, 0xb3839dd3, 0x669ec3de, 0xb37e942b, 0x669b0259, 0xb3798ab2,
+ 0x66974095, 0xb3748169,
+ 0x66937e91, 0xb36f784f, 0x668fbc4e, 0xb36a6f64, 0x668bf9cb, 0xb36566a8,
+ 0x66883709, 0xb3605e1c,
+ 0x66847408, 0xb35b55bf, 0x6680b0c8, 0xb3564d91, 0x667ced49, 0xb3514592,
+ 0x6679298a, 0xb34c3dc3,
+ 0x6675658c, 0xb3473623, 0x6671a14f, 0xb3422eb2, 0x666ddcd3, 0xb33d2771,
+ 0x666a1818, 0xb338205f,
+ 0x6666531d, 0xb333197c, 0x66628de4, 0xb32e12c9, 0x665ec86b, 0xb3290c45,
+ 0x665b02b3, 0xb32405f1,
+ 0x66573cbb, 0xb31effcc, 0x66537685, 0xb319f9d6, 0x664fb010, 0xb314f410,
+ 0x664be95b, 0xb30fee79,
+ 0x66482267, 0xb30ae912, 0x66445b35, 0xb305e3da, 0x664093c3, 0xb300ded2,
+ 0x663ccc12, 0xb2fbd9f9,
+ 0x66390422, 0xb2f6d550, 0x66353bf3, 0xb2f1d0d6, 0x66317385, 0xb2eccc8c,
+ 0x662daad8, 0xb2e7c871,
+ 0x6629e1ec, 0xb2e2c486, 0x662618c1, 0xb2ddc0ca, 0x66224f56, 0xb2d8bd3e,
+ 0x661e85ad, 0xb2d3b9e2,
+ 0x661abbc5, 0xb2ceb6b5, 0x6616f19e, 0xb2c9b3b8, 0x66132738, 0xb2c4b0ea,
+ 0x660f5c93, 0xb2bfae4c,
+ 0x660b91af, 0xb2baabde, 0x6607c68c, 0xb2b5a99f, 0x6603fb2a, 0xb2b0a790,
+ 0x66002f89, 0xb2aba5b1,
+ 0x65fc63a9, 0xb2a6a402, 0x65f8978b, 0xb2a1a282, 0x65f4cb2d, 0xb29ca132,
+ 0x65f0fe91, 0xb297a011,
+ 0x65ed31b5, 0xb2929f21, 0x65e9649b, 0xb28d9e60, 0x65e59742, 0xb2889dcf,
+ 0x65e1c9aa, 0xb2839d6d,
+ 0x65ddfbd3, 0xb27e9d3c, 0x65da2dbd, 0xb2799d3a, 0x65d65f69, 0xb2749d68,
+ 0x65d290d6, 0xb26f9dc6,
+ 0x65cec204, 0xb26a9e54, 0x65caf2f3, 0xb2659f12, 0x65c723a3, 0xb2609fff,
+ 0x65c35415, 0xb25ba11d,
+ 0x65bf8447, 0xb256a26a, 0x65bbb43b, 0xb251a3e7, 0x65b7e3f1, 0xb24ca594,
+ 0x65b41367, 0xb247a771,
+ 0x65b0429f, 0xb242a97e, 0x65ac7198, 0xb23dabbb, 0x65a8a052, 0xb238ae28,
+ 0x65a4cece, 0xb233b0c5,
+ 0x65a0fd0b, 0xb22eb392, 0x659d2b09, 0xb229b68f, 0x659958c9, 0xb224b9bc,
+ 0x6595864a, 0xb21fbd19,
+ 0x6591b38c, 0xb21ac0a6, 0x658de08f, 0xb215c463, 0x658a0d54, 0xb210c850,
+ 0x658639db, 0xb20bcc6d,
+ 0x65826622, 0xb206d0ba, 0x657e922b, 0xb201d537, 0x657abdf6, 0xb1fcd9e5,
+ 0x6576e982, 0xb1f7dec2,
+ 0x657314cf, 0xb1f2e3d0, 0x656f3fde, 0xb1ede90e, 0x656b6aae, 0xb1e8ee7c,
+ 0x6567953f, 0xb1e3f41a,
+ 0x6563bf92, 0xb1def9e9, 0x655fe9a7, 0xb1d9ffe7, 0x655c137d, 0xb1d50616,
+ 0x65583d14, 0xb1d00c75,
+ 0x6554666d, 0xb1cb1304, 0x65508f87, 0xb1c619c3, 0x654cb863, 0xb1c120b3,
+ 0x6548e101, 0xb1bc27d3,
+ 0x6545095f, 0xb1b72f23, 0x65413180, 0xb1b236a4, 0x653d5962, 0xb1ad3e55,
+ 0x65398105, 0xb1a84636,
+ 0x6535a86b, 0xb1a34e47, 0x6531cf91, 0xb19e5689, 0x652df679, 0xb1995efb,
+ 0x652a1d23, 0xb194679e,
+ 0x6526438f, 0xb18f7071, 0x652269bc, 0xb18a7974, 0x651e8faa, 0xb18582a8,
+ 0x651ab55b, 0xb1808c0c,
+ 0x6516dacd, 0xb17b95a0, 0x65130000, 0xb1769f65, 0x650f24f5, 0xb171a95b,
+ 0x650b49ac, 0xb16cb380,
+ 0x65076e25, 0xb167bdd7, 0x6503925f, 0xb162c85d, 0x64ffb65b, 0xb15dd315,
+ 0x64fbda18, 0xb158ddfd,
+ 0x64f7fd98, 0xb153e915, 0x64f420d9, 0xb14ef45e, 0x64f043dc, 0xb149ffd7,
+ 0x64ec66a0, 0xb1450b81,
+ 0x64e88926, 0xb140175b, 0x64e4ab6e, 0xb13b2367, 0x64e0cd78, 0xb1362fa2,
+ 0x64dcef44, 0xb1313c0e,
+ 0x64d910d1, 0xb12c48ab, 0x64d53220, 0xb1275579, 0x64d15331, 0xb1226277,
+ 0x64cd7404, 0xb11d6fa6,
+ 0x64c99498, 0xb1187d05, 0x64c5b4ef, 0xb1138a95, 0x64c1d507, 0xb10e9856,
+ 0x64bdf4e1, 0xb109a648,
+ 0x64ba147d, 0xb104b46a, 0x64b633da, 0xb0ffc2bd, 0x64b252fa, 0xb0fad140,
+ 0x64ae71dc, 0xb0f5dff5,
+ 0x64aa907f, 0xb0f0eeda, 0x64a6aee4, 0xb0ebfdf0, 0x64a2cd0c, 0xb0e70d37,
+ 0x649eeaf5, 0xb0e21cae,
+ 0x649b08a0, 0xb0dd2c56, 0x6497260d, 0xb0d83c2f, 0x6493433c, 0xb0d34c39,
+ 0x648f602d, 0xb0ce5c74,
+ 0x648b7ce0, 0xb0c96ce0, 0x64879955, 0xb0c47d7c, 0x6483b58c, 0xb0bf8e4a,
+ 0x647fd185, 0xb0ba9f48,
+ 0x647bed3f, 0xb0b5b077, 0x647808bc, 0xb0b0c1d7, 0x647423fb, 0xb0abd368,
+ 0x64703efc, 0xb0a6e52a,
+ 0x646c59bf, 0xb0a1f71d, 0x64687444, 0xb09d0941, 0x64648e8c, 0xb0981b96,
+ 0x6460a895, 0xb0932e1b,
+ 0x645cc260, 0xb08e40d2, 0x6458dbed, 0xb08953ba, 0x6454f53d, 0xb08466d3,
+ 0x64510e4e, 0xb07f7a1c,
+ 0x644d2722, 0xb07a8d97, 0x64493fb8, 0xb075a143, 0x64455810, 0xb070b520,
+ 0x6441702a, 0xb06bc92e,
+ 0x643d8806, 0xb066dd6d, 0x64399fa5, 0xb061f1de, 0x6435b706, 0xb05d067f,
+ 0x6431ce28, 0xb0581b51,
+ 0x642de50d, 0xb0533055, 0x6429fbb5, 0xb04e458a, 0x6426121e, 0xb0495af0,
+ 0x6422284a, 0xb0447087,
+ 0x641e3e38, 0xb03f864f, 0x641a53e8, 0xb03a9c49, 0x6416695a, 0xb035b273,
+ 0x64127e8f, 0xb030c8cf,
+ 0x640e9386, 0xb02bdf5c, 0x640aa83f, 0xb026f61b, 0x6406bcba, 0xb0220d0a,
+ 0x6402d0f8, 0xb01d242b,
+ 0x63fee4f8, 0xb0183b7d, 0x63faf8bb, 0xb0135301, 0x63f70c3f, 0xb00e6ab5,
+ 0x63f31f86, 0xb009829c,
+ 0x63ef3290, 0xb0049ab3, 0x63eb455c, 0xafffb2fc, 0x63e757ea, 0xaffacb76,
+ 0x63e36a3a, 0xaff5e421,
+ 0x63df7c4d, 0xaff0fcfe, 0x63db8e22, 0xafec160c, 0x63d79fba, 0xafe72f4c,
+ 0x63d3b114, 0xafe248bd,
+ 0x63cfc231, 0xafdd625f, 0x63cbd310, 0xafd87c33, 0x63c7e3b1, 0xafd39638,
+ 0x63c3f415, 0xafceb06f,
+ 0x63c0043b, 0xafc9cad7, 0x63bc1424, 0xafc4e571, 0x63b823cf, 0xafc0003c,
+ 0x63b4333d, 0xafbb1b39,
+ 0x63b0426d, 0xafb63667, 0x63ac5160, 0xafb151c7, 0x63a86015, 0xafac6d58,
+ 0x63a46e8d, 0xafa7891b,
+ 0x63a07cc7, 0xafa2a50f, 0x639c8ac4, 0xaf9dc135, 0x63989884, 0xaf98dd8d,
+ 0x6394a606, 0xaf93fa16,
+ 0x6390b34a, 0xaf8f16d1, 0x638cc051, 0xaf8a33bd, 0x6388cd1b, 0xaf8550db,
+ 0x6384d9a7, 0xaf806e2b,
+ 0x6380e5f6, 0xaf7b8bac, 0x637cf208, 0xaf76a95f, 0x6378fddc, 0xaf71c743,
+ 0x63750973, 0xaf6ce55a,
+ 0x637114cc, 0xaf6803a2, 0x636d1fe9, 0xaf63221c, 0x63692ac7, 0xaf5e40c7,
+ 0x63653569, 0xaf595fa4,
+ 0x63613fcd, 0xaf547eb3, 0x635d49f4, 0xaf4f9df4, 0x635953dd, 0xaf4abd66,
+ 0x63555d8a, 0xaf45dd0b,
+ 0x635166f9, 0xaf40fce1, 0x634d702b, 0xaf3c1ce9, 0x6349791f, 0xaf373d22,
+ 0x634581d6, 0xaf325d8e,
+ 0x63418a50, 0xaf2d7e2b, 0x633d928d, 0xaf289efa, 0x63399a8d, 0xaf23bffb,
+ 0x6335a24f, 0xaf1ee12e,
+ 0x6331a9d4, 0xaf1a0293, 0x632db11c, 0xaf15242a, 0x6329b827, 0xaf1045f3,
+ 0x6325bef5, 0xaf0b67ed,
+ 0x6321c585, 0xaf068a1a, 0x631dcbd9, 0xaf01ac78, 0x6319d1ef, 0xaefccf09,
+ 0x6315d7c8, 0xaef7f1cb,
+ 0x6311dd64, 0xaef314c0, 0x630de2c3, 0xaeee37e6, 0x6309e7e4, 0xaee95b3f,
+ 0x6305ecc9, 0xaee47ec9,
+ 0x6301f171, 0xaedfa285, 0x62fdf5db, 0xaedac674, 0x62f9fa09, 0xaed5ea95,
+ 0x62f5fdf9, 0xaed10ee7,
+ 0x62f201ac, 0xaecc336c, 0x62ee0523, 0xaec75823, 0x62ea085c, 0xaec27d0c,
+ 0x62e60b58, 0xaebda227,
+ 0x62e20e17, 0xaeb8c774, 0x62de109a, 0xaeb3ecf3, 0x62da12df, 0xaeaf12a4,
+ 0x62d614e7, 0xaeaa3888,
+ 0x62d216b3, 0xaea55e9e, 0x62ce1841, 0xaea084e6, 0x62ca1992, 0xae9bab60,
+ 0x62c61aa7, 0xae96d20c,
+ 0x62c21b7e, 0xae91f8eb, 0x62be1c19, 0xae8d1ffb, 0x62ba1c77, 0xae88473e,
+ 0x62b61c98, 0xae836eb4,
+ 0x62b21c7b, 0xae7e965b, 0x62ae1c23, 0xae79be35, 0x62aa1b8d, 0xae74e641,
+ 0x62a61aba, 0xae700e80,
+ 0x62a219aa, 0xae6b36f0, 0x629e185e, 0xae665f93, 0x629a16d5, 0xae618869,
+ 0x6296150f, 0xae5cb171,
+ 0x6292130c, 0xae57daab, 0x628e10cc, 0xae530417, 0x628a0e50, 0xae4e2db6,
+ 0x62860b97, 0xae495787,
+ 0x628208a1, 0xae44818b, 0x627e056e, 0xae3fabc1, 0x627a01fe, 0xae3ad629,
+ 0x6275fe52, 0xae3600c4,
+ 0x6271fa69, 0xae312b92, 0x626df643, 0xae2c5691, 0x6269f1e1, 0xae2781c4,
+ 0x6265ed42, 0xae22ad29,
+ 0x6261e866, 0xae1dd8c0, 0x625de34e, 0xae19048a, 0x6259ddf8, 0xae143086,
+ 0x6255d866, 0xae0f5cb5,
+ 0x6251d298, 0xae0a8916, 0x624dcc8d, 0xae05b5aa, 0x6249c645, 0xae00e271,
+ 0x6245bfc0, 0xadfc0f6a,
+ 0x6241b8ff, 0xadf73c96, 0x623db202, 0xadf269f4, 0x6239aac7, 0xaded9785,
+ 0x6235a351, 0xade8c548,
+ 0x62319b9d, 0xade3f33e, 0x622d93ad, 0xaddf2167, 0x62298b81, 0xadda4fc3,
+ 0x62258317, 0xadd57e51,
+ 0x62217a72, 0xadd0ad12, 0x621d7190, 0xadcbdc05, 0x62196871, 0xadc70b2c,
+ 0x62155f16, 0xadc23a85,
+ 0x6211557e, 0xadbd6a10, 0x620d4baa, 0xadb899cf, 0x62094199, 0xadb3c9c0,
+ 0x6205374c, 0xadaef9e4,
+ 0x62012cc2, 0xadaa2a3b, 0x61fd21fc, 0xada55ac4, 0x61f916f9, 0xada08b80,
+ 0x61f50bba, 0xad9bbc70,
+ 0x61f1003f, 0xad96ed92, 0x61ecf487, 0xad921ee6, 0x61e8e893, 0xad8d506e,
+ 0x61e4dc62, 0xad888229,
+ 0x61e0cff5, 0xad83b416, 0x61dcc34c, 0xad7ee636, 0x61d8b666, 0xad7a1889,
+ 0x61d4a944, 0xad754b0f,
+ 0x61d09be5, 0xad707dc8, 0x61cc8e4b, 0xad6bb0b4, 0x61c88074, 0xad66e3d3,
+ 0x61c47260, 0xad621725,
+ 0x61c06410, 0xad5d4aaa, 0x61bc5584, 0xad587e61, 0x61b846bc, 0xad53b24c,
+ 0x61b437b7, 0xad4ee66a,
+ 0x61b02876, 0xad4a1aba, 0x61ac18f9, 0xad454f3e, 0x61a80940, 0xad4083f5,
+ 0x61a3f94a, 0xad3bb8df,
+ 0x619fe918, 0xad36edfc, 0x619bd8aa, 0xad32234b, 0x6197c800, 0xad2d58ce,
+ 0x6193b719, 0xad288e85,
+ 0x618fa5f7, 0xad23c46e, 0x618b9498, 0xad1efa8a, 0x618782fd, 0xad1a30d9,
+ 0x61837126, 0xad15675c,
+ 0x617f5f12, 0xad109e12, 0x617b4cc3, 0xad0bd4fb, 0x61773a37, 0xad070c17,
+ 0x61732770, 0xad024366,
+ 0x616f146c, 0xacfd7ae8, 0x616b012c, 0xacf8b29e, 0x6166edb0, 0xacf3ea87,
+ 0x6162d9f8, 0xacef22a3,
+ 0x615ec603, 0xacea5af2, 0x615ab1d3, 0xace59375, 0x61569d67, 0xace0cc2b,
+ 0x615288be, 0xacdc0514,
+ 0x614e73da, 0xacd73e30, 0x614a5eba, 0xacd27780, 0x6146495d, 0xaccdb103,
+ 0x614233c5, 0xacc8eab9,
+ 0x613e1df0, 0xacc424a3, 0x613a07e0, 0xacbf5ec0, 0x6135f193, 0xacba9910,
+ 0x6131db0b, 0xacb5d394,
+ 0x612dc447, 0xacb10e4b, 0x6129ad46, 0xacac4935, 0x6125960a, 0xaca78453,
+ 0x61217e92, 0xaca2bfa4,
+ 0x611d66de, 0xac9dfb29, 0x61194eee, 0xac9936e1, 0x611536c2, 0xac9472cd,
+ 0x61111e5b, 0xac8faeec,
+ 0x610d05b7, 0xac8aeb3e, 0x6108ecd8, 0xac8627c4, 0x6104d3bc, 0xac81647e,
+ 0x6100ba65, 0xac7ca16b,
+ 0x60fca0d2, 0xac77de8b, 0x60f88703, 0xac731bdf, 0x60f46cf9, 0xac6e5967,
+ 0x60f052b2, 0xac699722,
+ 0x60ec3830, 0xac64d510, 0x60e81d72, 0xac601333, 0x60e40278, 0xac5b5189,
+ 0x60dfe743, 0xac569012,
+ 0x60dbcbd1, 0xac51cecf, 0x60d7b024, 0xac4d0dc0, 0x60d3943b, 0xac484ce4,
+ 0x60cf7817, 0xac438c3c,
+ 0x60cb5bb7, 0xac3ecbc7, 0x60c73f1b, 0xac3a0b87, 0x60c32243, 0xac354b7a,
+ 0x60bf0530, 0xac308ba0,
+ 0x60bae7e1, 0xac2bcbfa, 0x60b6ca56, 0xac270c88, 0x60b2ac8f, 0xac224d4a,
+ 0x60ae8e8d, 0xac1d8e40,
+ 0x60aa7050, 0xac18cf69, 0x60a651d7, 0xac1410c6, 0x60a23322, 0xac0f5256,
+ 0x609e1431, 0xac0a941b,
+ 0x6099f505, 0xac05d613, 0x6095d59d, 0xac01183f, 0x6091b5fa, 0xabfc5a9f,
+ 0x608d961b, 0xabf79d33,
+ 0x60897601, 0xabf2dffb, 0x608555ab, 0xabee22f6, 0x60813519, 0xabe96625,
+ 0x607d144c, 0xabe4a988,
+ 0x6078f344, 0xabdfed1f, 0x6074d200, 0xabdb30ea, 0x6070b080, 0xabd674e9,
+ 0x606c8ec5, 0xabd1b91c,
+ 0x60686ccf, 0xabccfd83, 0x60644a9d, 0xabc8421d, 0x6060282f, 0xabc386ec,
+ 0x605c0587, 0xabbecbee,
+ 0x6057e2a2, 0xabba1125, 0x6053bf82, 0xabb5568f, 0x604f9c27, 0xabb09c2e,
+ 0x604b7891, 0xababe200,
+ 0x604754bf, 0xaba72807, 0x604330b1, 0xaba26e41, 0x603f0c69, 0xab9db4b0,
+ 0x603ae7e5, 0xab98fb52,
+ 0x6036c325, 0xab944229, 0x60329e2a, 0xab8f8934, 0x602e78f4, 0xab8ad073,
+ 0x602a5383, 0xab8617e6,
+ 0x60262dd6, 0xab815f8d, 0x602207ee, 0xab7ca768, 0x601de1ca, 0xab77ef77,
+ 0x6019bb6b, 0xab7337bb,
+ 0x601594d1, 0xab6e8032, 0x60116dfc, 0xab69c8de, 0x600d46ec, 0xab6511be,
+ 0x60091fa0, 0xab605ad2,
+ 0x6004f819, 0xab5ba41a, 0x6000d057, 0xab56ed97, 0x5ffca859, 0xab523748,
+ 0x5ff88021, 0xab4d812d,
+ 0x5ff457ad, 0xab48cb46, 0x5ff02efe, 0xab441593, 0x5fec0613, 0xab3f6015,
+ 0x5fe7dcee, 0xab3aaacb,
+ 0x5fe3b38d, 0xab35f5b5, 0x5fdf89f2, 0xab3140d4, 0x5fdb601b, 0xab2c8c27,
+ 0x5fd73609, 0xab27d7ae,
+ 0x5fd30bbc, 0xab23236a, 0x5fcee133, 0xab1e6f5a, 0x5fcab670, 0xab19bb7e,
+ 0x5fc68b72, 0xab1507d7,
+ 0x5fc26038, 0xab105464, 0x5fbe34c4, 0xab0ba125, 0x5fba0914, 0xab06ee1b,
+ 0x5fb5dd29, 0xab023b46,
+ 0x5fb1b104, 0xaafd88a4, 0x5fad84a3, 0xaaf8d637, 0x5fa95807, 0xaaf423ff,
+ 0x5fa52b31, 0xaaef71fb,
+ 0x5fa0fe1f, 0xaaeac02c, 0x5f9cd0d2, 0xaae60e91, 0x5f98a34a, 0xaae15d2a,
+ 0x5f947588, 0xaadcabf8,
+ 0x5f90478a, 0xaad7fafb, 0x5f8c1951, 0xaad34a32, 0x5f87eade, 0xaace999d,
+ 0x5f83bc2f, 0xaac9e93e,
+ 0x5f7f8d46, 0xaac53912, 0x5f7b5e22, 0xaac0891c, 0x5f772ec2, 0xaabbd959,
+ 0x5f72ff28, 0xaab729cc,
+ 0x5f6ecf53, 0xaab27a73, 0x5f6a9f44, 0xaaadcb4f, 0x5f666ef9, 0xaaa91c5f,
+ 0x5f623e73, 0xaaa46da4,
+ 0x5f5e0db3, 0xaa9fbf1e, 0x5f59dcb8, 0xaa9b10cc, 0x5f55ab82, 0xaa9662af,
+ 0x5f517a11, 0xaa91b4c7,
+ 0x5f4d4865, 0xaa8d0713, 0x5f49167f, 0xaa885994, 0x5f44e45e, 0xaa83ac4a,
+ 0x5f40b202, 0xaa7eff34,
+ 0x5f3c7f6b, 0xaa7a5253, 0x5f384c9a, 0xaa75a5a8, 0x5f34198e, 0xaa70f930,
+ 0x5f2fe647, 0xaa6c4cee,
+ 0x5f2bb2c5, 0xaa67a0e0, 0x5f277f09, 0xaa62f507, 0x5f234b12, 0xaa5e4963,
+ 0x5f1f16e0, 0xaa599df4,
+ 0x5f1ae274, 0xaa54f2ba, 0x5f16adcc, 0xaa5047b4, 0x5f1278eb, 0xaa4b9ce3,
+ 0x5f0e43ce, 0xaa46f248,
+ 0x5f0a0e77, 0xaa4247e1, 0x5f05d8e6, 0xaa3d9daf, 0x5f01a31a, 0xaa38f3b1,
+ 0x5efd6d13, 0xaa3449e9,
+ 0x5ef936d1, 0xaa2fa056, 0x5ef50055, 0xaa2af6f7, 0x5ef0c99f, 0xaa264dce,
+ 0x5eec92ae, 0xaa21a4d9,
+ 0x5ee85b82, 0xaa1cfc1a, 0x5ee4241c, 0xaa18538f, 0x5edfec7b, 0xaa13ab3a,
+ 0x5edbb49f, 0xaa0f0319,
+ 0x5ed77c8a, 0xaa0a5b2e, 0x5ed34439, 0xaa05b377, 0x5ecf0baf, 0xaa010bf6,
+ 0x5ecad2e9, 0xa9fc64a9,
+ 0x5ec699e9, 0xa9f7bd92, 0x5ec260af, 0xa9f316b0, 0x5ebe273b, 0xa9ee7002,
+ 0x5eb9ed8b, 0xa9e9c98a,
+ 0x5eb5b3a2, 0xa9e52347, 0x5eb1797e, 0xa9e07d39, 0x5ead3f1f, 0xa9dbd761,
+ 0x5ea90487, 0xa9d731bd,
+ 0x5ea4c9b3, 0xa9d28c4e, 0x5ea08ea6, 0xa9cde715, 0x5e9c535e, 0xa9c94211,
+ 0x5e9817dc, 0xa9c49d42,
+ 0x5e93dc1f, 0xa9bff8a8, 0x5e8fa028, 0xa9bb5444, 0x5e8b63f7, 0xa9b6b014,
+ 0x5e87278b, 0xa9b20c1a,
+ 0x5e82eae5, 0xa9ad6855, 0x5e7eae05, 0xa9a8c4c5, 0x5e7a70ea, 0xa9a4216b,
+ 0x5e763395, 0xa99f7e46,
+ 0x5e71f606, 0xa99adb56, 0x5e6db83d, 0xa996389b, 0x5e697a39, 0xa9919616,
+ 0x5e653bfc, 0xa98cf3c6,
+ 0x5e60fd84, 0xa98851ac, 0x5e5cbed1, 0xa983afc6, 0x5e587fe5, 0xa97f0e16,
+ 0x5e5440be, 0xa97a6c9c,
+ 0x5e50015d, 0xa975cb57, 0x5e4bc1c2, 0xa9712a47, 0x5e4781ed, 0xa96c896c,
+ 0x5e4341de, 0xa967e8c7,
+ 0x5e3f0194, 0xa9634858, 0x5e3ac110, 0xa95ea81d, 0x5e368053, 0xa95a0819,
+ 0x5e323f5b, 0xa9556849,
+ 0x5e2dfe29, 0xa950c8b0, 0x5e29bcbd, 0xa94c294b, 0x5e257b17, 0xa9478a1c,
+ 0x5e213936, 0xa942eb23,
+ 0x5e1cf71c, 0xa93e4c5f, 0x5e18b4c8, 0xa939add1, 0x5e147239, 0xa9350f78,
+ 0x5e102f71, 0xa9307155,
+ 0x5e0bec6e, 0xa92bd367, 0x5e07a932, 0xa92735af, 0x5e0365bb, 0xa922982c,
+ 0x5dff220b, 0xa91dfadf,
+ 0x5dfade20, 0xa9195dc7, 0x5df699fc, 0xa914c0e6, 0x5df2559e, 0xa9102439,
+ 0x5dee1105, 0xa90b87c3,
+ 0x5de9cc33, 0xa906eb82, 0x5de58727, 0xa9024f76, 0x5de141e1, 0xa8fdb3a1,
+ 0x5ddcfc61, 0xa8f91801,
+ 0x5dd8b6a7, 0xa8f47c97, 0x5dd470b3, 0xa8efe162, 0x5dd02a85, 0xa8eb4663,
+ 0x5dcbe41d, 0xa8e6ab9a,
+ 0x5dc79d7c, 0xa8e21106, 0x5dc356a1, 0xa8dd76a9, 0x5dbf0f8c, 0xa8d8dc81,
+ 0x5dbac83d, 0xa8d4428f,
+ 0x5db680b4, 0xa8cfa8d2, 0x5db238f1, 0xa8cb0f4b, 0x5dadf0f5, 0xa8c675fb,
+ 0x5da9a8bf, 0xa8c1dce0,
+ 0x5da5604f, 0xa8bd43fa, 0x5da117a5, 0xa8b8ab4b, 0x5d9ccec2, 0xa8b412d1,
+ 0x5d9885a5, 0xa8af7a8e,
+ 0x5d943c4e, 0xa8aae280, 0x5d8ff2bd, 0xa8a64aa8, 0x5d8ba8f3, 0xa8a1b306,
+ 0x5d875eef, 0xa89d1b99,
+ 0x5d8314b1, 0xa8988463, 0x5d7eca39, 0xa893ed63, 0x5d7a7f88, 0xa88f5698,
+ 0x5d76349d, 0xa88ac004,
+ 0x5d71e979, 0xa88629a5, 0x5d6d9e1b, 0xa881937c, 0x5d695283, 0xa87cfd8a,
+ 0x5d6506b2, 0xa87867cd,
+ 0x5d60baa7, 0xa873d246, 0x5d5c6e62, 0xa86f3cf6, 0x5d5821e4, 0xa86aa7db,
+ 0x5d53d52d, 0xa86612f6,
+ 0x5d4f883b, 0xa8617e48, 0x5d4b3b10, 0xa85ce9cf, 0x5d46edac, 0xa858558d,
+ 0x5d42a00e, 0xa853c180,
+ 0x5d3e5237, 0xa84f2daa, 0x5d3a0426, 0xa84a9a0a, 0x5d35b5db, 0xa84606a0,
+ 0x5d316757, 0xa841736c,
+ 0x5d2d189a, 0xa83ce06e, 0x5d28c9a3, 0xa8384da6, 0x5d247a72, 0xa833bb14,
+ 0x5d202b09, 0xa82f28b9,
+ 0x5d1bdb65, 0xa82a9693, 0x5d178b89, 0xa82604a4, 0x5d133b72, 0xa82172eb,
+ 0x5d0eeb23, 0xa81ce169,
+ 0x5d0a9a9a, 0xa818501c, 0x5d0649d7, 0xa813bf06, 0x5d01f8dc, 0xa80f2e26,
+ 0x5cfda7a7, 0xa80a9d7c,
+ 0x5cf95638, 0xa8060d08, 0x5cf50490, 0xa8017ccb, 0x5cf0b2af, 0xa7fcecc4,
+ 0x5cec6095, 0xa7f85cf3,
+ 0x5ce80e41, 0xa7f3cd59, 0x5ce3bbb4, 0xa7ef3df5, 0x5cdf68ed, 0xa7eaaec7,
+ 0x5cdb15ed, 0xa7e61fd0,
+ 0x5cd6c2b5, 0xa7e1910f, 0x5cd26f42, 0xa7dd0284, 0x5cce1b97, 0xa7d8742f,
+ 0x5cc9c7b2, 0xa7d3e611,
+ 0x5cc57394, 0xa7cf582a, 0x5cc11f3d, 0xa7caca79, 0x5cbccaac, 0xa7c63cfe,
+ 0x5cb875e3, 0xa7c1afb9,
+ 0x5cb420e0, 0xa7bd22ac, 0x5cafcba4, 0xa7b895d4, 0x5cab762f, 0xa7b40933,
+ 0x5ca72080, 0xa7af7cc8,
+ 0x5ca2ca99, 0xa7aaf094, 0x5c9e7478, 0xa7a66497, 0x5c9a1e1e, 0xa7a1d8d0,
+ 0x5c95c78b, 0xa79d4d3f,
+ 0x5c9170bf, 0xa798c1e5, 0x5c8d19ba, 0xa79436c1, 0x5c88c27c, 0xa78fabd4,
+ 0x5c846b05, 0xa78b211e,
+ 0x5c801354, 0xa786969e, 0x5c7bbb6b, 0xa7820c55, 0x5c776348, 0xa77d8242,
+ 0x5c730aed, 0xa778f866,
+ 0x5c6eb258, 0xa7746ec0, 0x5c6a598b, 0xa76fe551, 0x5c660084, 0xa76b5c19,
+ 0x5c61a745, 0xa766d317,
+ 0x5c5d4dcc, 0xa7624a4d, 0x5c58f41a, 0xa75dc1b8, 0x5c549a30, 0xa759395b,
+ 0x5c50400d, 0xa754b134,
+ 0x5c4be5b0, 0xa7502943, 0x5c478b1b, 0xa74ba18a, 0x5c43304d, 0xa7471a07,
+ 0x5c3ed545, 0xa74292bb,
+ 0x5c3a7a05, 0xa73e0ba5, 0x5c361e8c, 0xa73984c7, 0x5c31c2db, 0xa734fe1f,
+ 0x5c2d66f0, 0xa73077ae,
+ 0x5c290acc, 0xa72bf174, 0x5c24ae70, 0xa7276b70, 0x5c2051db, 0xa722e5a3,
+ 0x5c1bf50d, 0xa71e600d,
+ 0x5c179806, 0xa719daae, 0x5c133ac6, 0xa7155586, 0x5c0edd4e, 0xa710d095,
+ 0x5c0a7f9c, 0xa70c4bda,
+ 0x5c0621b2, 0xa707c757, 0x5c01c38f, 0xa703430a, 0x5bfd6534, 0xa6febef4,
+ 0x5bf906a0, 0xa6fa3b15,
+ 0x5bf4a7d2, 0xa6f5b76d, 0x5bf048cd, 0xa6f133fc, 0x5bebe98e, 0xa6ecb0c2,
+ 0x5be78a17, 0xa6e82dbe,
+ 0x5be32a67, 0xa6e3aaf2, 0x5bdeca7f, 0xa6df285d, 0x5bda6a5d, 0xa6daa5fe,
+ 0x5bd60a03, 0xa6d623d7,
+ 0x5bd1a971, 0xa6d1a1e7, 0x5bcd48a6, 0xa6cd202d, 0x5bc8e7a2, 0xa6c89eab,
+ 0x5bc48666, 0xa6c41d60,
+ 0x5bc024f0, 0xa6bf9c4b, 0x5bbbc343, 0xa6bb1b6e, 0x5bb7615d, 0xa6b69ac8,
+ 0x5bb2ff3e, 0xa6b21a59,
+ 0x5bae9ce7, 0xa6ad9a21, 0x5baa3a57, 0xa6a91a20, 0x5ba5d78e, 0xa6a49a56,
+ 0x5ba1748d, 0xa6a01ac4,
+ 0x5b9d1154, 0xa69b9b68, 0x5b98ade2, 0xa6971c44, 0x5b944a37, 0xa6929d57,
+ 0x5b8fe654, 0xa68e1ea1,
+ 0x5b8b8239, 0xa689a022, 0x5b871de5, 0xa68521da, 0x5b82b958, 0xa680a3ca,
+ 0x5b7e5493, 0xa67c25f0,
+ 0x5b79ef96, 0xa677a84e, 0x5b758a60, 0xa6732ae3, 0x5b7124f2, 0xa66eadb0,
+ 0x5b6cbf4c, 0xa66a30b3,
+ 0x5b68596d, 0xa665b3ee, 0x5b63f355, 0xa6613760, 0x5b5f8d06, 0xa65cbb0a,
+ 0x5b5b267e, 0xa6583eeb,
+ 0x5b56bfbd, 0xa653c303, 0x5b5258c4, 0xa64f4752, 0x5b4df193, 0xa64acbd9,
+ 0x5b498a2a, 0xa6465097,
+ 0x5b452288, 0xa641d58c, 0x5b40baae, 0xa63d5ab9, 0x5b3c529c, 0xa638e01d,
+ 0x5b37ea51, 0xa63465b9,
+ 0x5b3381ce, 0xa62feb8b, 0x5b2f1913, 0xa62b7196, 0x5b2ab020, 0xa626f7d7,
+ 0x5b2646f4, 0xa6227e50,
+ 0x5b21dd90, 0xa61e0501, 0x5b1d73f4, 0xa6198be9, 0x5b190a20, 0xa6151308,
+ 0x5b14a014, 0xa6109a5f,
+ 0x5b1035cf, 0xa60c21ee, 0x5b0bcb52, 0xa607a9b4, 0x5b07609d, 0xa60331b1,
+ 0x5b02f5b0, 0xa5feb9e6,
+ 0x5afe8a8b, 0xa5fa4252, 0x5afa1f2e, 0xa5f5caf6, 0x5af5b398, 0xa5f153d2,
+ 0x5af147ca, 0xa5ecdce5,
+ 0x5aecdbc5, 0xa5e8662f, 0x5ae86f87, 0xa5e3efb1, 0x5ae40311, 0xa5df796b,
+ 0x5adf9663, 0xa5db035c,
+ 0x5adb297d, 0xa5d68d85, 0x5ad6bc5f, 0xa5d217e6, 0x5ad24f09, 0xa5cda27e,
+ 0x5acde17b, 0xa5c92d4e,
+ 0x5ac973b5, 0xa5c4b855, 0x5ac505b7, 0xa5c04395, 0x5ac09781, 0xa5bbcf0b,
+ 0x5abc2912, 0xa5b75aba,
+ 0x5ab7ba6c, 0xa5b2e6a0, 0x5ab34b8e, 0xa5ae72be, 0x5aaedc78, 0xa5a9ff14,
+ 0x5aaa6d2b, 0xa5a58ba1,
+ 0x5aa5fda5, 0xa5a11866, 0x5aa18de7, 0xa59ca563, 0x5a9d1df1, 0xa5983297,
+ 0x5a98adc4, 0xa593c004,
+ 0x5a943d5e, 0xa58f4da8, 0x5a8fccc1, 0xa58adb84, 0x5a8b5bec, 0xa5866997,
+ 0x5a86eadf, 0xa581f7e3,
+ 0x5a82799a, 0xa57d8666, 0x5a7e081d, 0xa5791521, 0x5a799669, 0xa574a414,
+ 0x5a75247c, 0xa570333f,
+ 0x5a70b258, 0xa56bc2a2, 0x5a6c3ffc, 0xa567523c, 0x5a67cd69, 0xa562e20f,
+ 0x5a635a9d, 0xa55e7219,
+ 0x5a5ee79a, 0xa55a025b, 0x5a5a745f, 0xa55592d5, 0x5a5600ec, 0xa5512388,
+ 0x5a518d42, 0xa54cb472,
+ 0x5a4d1960, 0xa5484594, 0x5a48a546, 0xa543d6ee, 0x5a4430f5, 0xa53f687f,
+ 0x5a3fbc6b, 0xa53afa49,
+ 0x5a3b47ab, 0xa5368c4b, 0x5a36d2b2, 0xa5321e85, 0x5a325d82, 0xa52db0f7,
+ 0x5a2de81a, 0xa52943a1,
+ 0x5a29727b, 0xa524d683, 0x5a24fca4, 0xa520699d, 0x5a208695, 0xa51bfcef,
+ 0x5a1c104f, 0xa5179079,
+ 0x5a1799d1, 0xa513243b, 0x5a13231b, 0xa50eb836, 0x5a0eac2e, 0xa50a4c68,
+ 0x5a0a350a, 0xa505e0d2,
+ 0x5a05bdae, 0xa5017575, 0x5a01461a, 0xa4fd0a50, 0x59fcce4f, 0xa4f89f63,
+ 0x59f8564c, 0xa4f434ae,
+ 0x59f3de12, 0xa4efca31, 0x59ef65a1, 0xa4eb5fec, 0x59eaecf8, 0xa4e6f5e0,
+ 0x59e67417, 0xa4e28c0c,
+ 0x59e1faff, 0xa4de2270, 0x59dd81b0, 0xa4d9b90c, 0x59d90829, 0xa4d54fe0,
+ 0x59d48e6a, 0xa4d0e6ed,
+ 0x59d01475, 0xa4cc7e32, 0x59cb9a47, 0xa4c815af, 0x59c71fe3, 0xa4c3ad64,
+ 0x59c2a547, 0xa4bf4552,
+ 0x59be2a74, 0xa4badd78, 0x59b9af69, 0xa4b675d6, 0x59b53427, 0xa4b20e6d,
+ 0x59b0b8ae, 0xa4ada73c,
+ 0x59ac3cfd, 0xa4a94043, 0x59a7c115, 0xa4a4d982, 0x59a344f6, 0xa4a072fa,
+ 0x599ec8a0, 0xa49c0cab,
+ 0x599a4c12, 0xa497a693, 0x5995cf4d, 0xa49340b4, 0x59915250, 0xa48edb0e,
+ 0x598cd51d, 0xa48a75a0,
+ 0x598857b2, 0xa486106a, 0x5983da10, 0xa481ab6d, 0x597f5c36, 0xa47d46a8,
+ 0x597ade26, 0xa478e21b,
+ 0x59765fde, 0xa4747dc7, 0x5971e15f, 0xa47019ac, 0x596d62a9, 0xa46bb5c9,
+ 0x5968e3bc, 0xa467521e,
+ 0x59646498, 0xa462eeac, 0x595fe53c, 0xa45e8b73, 0x595b65aa, 0xa45a2872,
+ 0x5956e5e0, 0xa455c5a9,
+ 0x595265df, 0xa4516319, 0x594de5a7, 0xa44d00c2, 0x59496538, 0xa4489ea3,
+ 0x5944e492, 0xa4443cbd,
+ 0x594063b5, 0xa43fdb10, 0x593be2a0, 0xa43b799a, 0x59376155, 0xa437185e,
+ 0x5932dfd3, 0xa432b75a,
+ 0x592e5e19, 0xa42e568f, 0x5929dc29, 0xa429f5fd, 0x59255a02, 0xa42595a3,
+ 0x5920d7a3, 0xa4213581,
+ 0x591c550e, 0xa41cd599, 0x5917d242, 0xa41875e9, 0x59134f3e, 0xa4141672,
+ 0x590ecc04, 0xa40fb733,
+ 0x590a4893, 0xa40b582e, 0x5905c4eb, 0xa406f960, 0x5901410c, 0xa4029acc,
+ 0x58fcbcf6, 0xa3fe3c71,
+ 0x58f838a9, 0xa3f9de4e, 0x58f3b426, 0xa3f58064, 0x58ef2f6b, 0xa3f122b2,
+ 0x58eaaa7a, 0xa3ecc53a,
+ 0x58e62552, 0xa3e867fa, 0x58e19ff3, 0xa3e40af3, 0x58dd1a5d, 0xa3dfae25,
+ 0x58d89490, 0xa3db5190,
+ 0x58d40e8c, 0xa3d6f534, 0x58cf8852, 0xa3d29910, 0x58cb01e1, 0xa3ce3d25,
+ 0x58c67b39, 0xa3c9e174,
+ 0x58c1f45b, 0xa3c585fb, 0x58bd6d45, 0xa3c12abb, 0x58b8e5f9, 0xa3bccfb3,
+ 0x58b45e76, 0xa3b874e5,
+ 0x58afd6bd, 0xa3b41a50, 0x58ab4ecc, 0xa3afbff3, 0x58a6c6a5, 0xa3ab65d0,
+ 0x58a23e48, 0xa3a70be6,
+ 0x589db5b3, 0xa3a2b234, 0x58992ce9, 0xa39e58bb, 0x5894a3e7, 0xa399ff7c,
+ 0x58901aaf, 0xa395a675,
+ 0x588b9140, 0xa3914da8, 0x5887079a, 0xa38cf513, 0x58827dbe, 0xa3889cb8,
+ 0x587df3ab, 0xa3844495,
+ 0x58796962, 0xa37fecac, 0x5874dee2, 0xa37b94fb, 0x5870542c, 0xa3773d84,
+ 0x586bc93f, 0xa372e646,
+ 0x58673e1b, 0xa36e8f41, 0x5862b2c1, 0xa36a3875, 0x585e2730, 0xa365e1e2,
+ 0x58599b69, 0xa3618b88,
+ 0x58550f6c, 0xa35d3567, 0x58508338, 0xa358df80, 0x584bf6cd, 0xa35489d1,
+ 0x58476a2c, 0xa350345c,
+ 0x5842dd54, 0xa34bdf20, 0x583e5047, 0xa3478a1d, 0x5839c302, 0xa3433554,
+ 0x58353587, 0xa33ee0c3,
+ 0x5830a7d6, 0xa33a8c6c, 0x582c19ef, 0xa336384e, 0x58278bd1, 0xa331e469,
+ 0x5822fd7c, 0xa32d90be,
+ 0x581e6ef1, 0xa3293d4b, 0x5819e030, 0xa324ea13, 0x58155139, 0xa3209713,
+ 0x5810c20b, 0xa31c444c,
+ 0x580c32a7, 0xa317f1bf, 0x5807a30d, 0xa3139f6b, 0x5803133c, 0xa30f4d51,
+ 0x57fe8335, 0xa30afb70,
+ 0x57f9f2f8, 0xa306a9c8, 0x57f56284, 0xa3025859, 0x57f0d1da, 0xa2fe0724,
+ 0x57ec40fa, 0xa2f9b629,
+ 0x57e7afe4, 0xa2f56566, 0x57e31e97, 0xa2f114dd, 0x57de8d15, 0xa2ecc48e,
+ 0x57d9fb5c, 0xa2e87477,
+ 0x57d5696d, 0xa2e4249b, 0x57d0d747, 0xa2dfd4f7, 0x57cc44ec, 0xa2db858e,
+ 0x57c7b25a, 0xa2d7365d,
+ 0x57c31f92, 0xa2d2e766, 0x57be8c94, 0xa2ce98a9, 0x57b9f960, 0xa2ca4a25,
+ 0x57b565f6, 0xa2c5fbda,
+ 0x57b0d256, 0xa2c1adc9, 0x57ac3e80, 0xa2bd5ff2, 0x57a7aa73, 0xa2b91254,
+ 0x57a31631, 0xa2b4c4f0,
+ 0x579e81b8, 0xa2b077c5, 0x5799ed0a, 0xa2ac2ad3, 0x57955825, 0xa2a7de1c,
+ 0x5790c30a, 0xa2a3919e,
+ 0x578c2dba, 0xa29f4559, 0x57879833, 0xa29af94e, 0x57830276, 0xa296ad7d,
+ 0x577e6c84, 0xa29261e5,
+ 0x5779d65b, 0xa28e1687, 0x57753ffc, 0xa289cb63, 0x5770a968, 0xa2858078,
+ 0x576c129d, 0xa28135c7,
+ 0x57677b9d, 0xa27ceb4f, 0x5762e467, 0xa278a111, 0x575e4cfa, 0xa274570d,
+ 0x5759b558, 0xa2700d43,
+ 0x57551d80, 0xa26bc3b2, 0x57508572, 0xa2677a5b, 0x574bed2f, 0xa263313e,
+ 0x574754b5, 0xa25ee85b,
+ 0x5742bc06, 0xa25a9fb1, 0x573e2320, 0xa2565741, 0x57398a05, 0xa2520f0b,
+ 0x5734f0b5, 0xa24dc70f,
+ 0x5730572e, 0xa2497f4c, 0x572bbd71, 0xa24537c3, 0x5727237f, 0xa240f074,
+ 0x57228957, 0xa23ca95f,
+ 0x571deefa, 0xa2386284, 0x57195466, 0xa2341be3, 0x5714b99d, 0xa22fd57b,
+ 0x57101e9e, 0xa22b8f4d,
+ 0x570b8369, 0xa2274959, 0x5706e7ff, 0xa223039f, 0x57024c5f, 0xa21ebe1f,
+ 0x56fdb08a, 0xa21a78d9,
+ 0x56f9147e, 0xa21633cd, 0x56f4783d, 0xa211eefb, 0x56efdbc7, 0xa20daa62,
+ 0x56eb3f1a, 0xa2096604,
+ 0x56e6a239, 0xa20521e0, 0x56e20521, 0xa200ddf5, 0x56dd67d4, 0xa1fc9a45,
+ 0x56d8ca51, 0xa1f856ce,
+ 0x56d42c99, 0xa1f41392, 0x56cf8eab, 0xa1efd08f, 0x56caf088, 0xa1eb8dc7,
+ 0x56c6522f, 0xa1e74b38,
+ 0x56c1b3a1, 0xa1e308e4, 0x56bd14dd, 0xa1dec6ca, 0x56b875e4, 0xa1da84e9,
+ 0x56b3d6b5, 0xa1d64343,
+ 0x56af3750, 0xa1d201d7, 0x56aa97b7, 0xa1cdc0a5, 0x56a5f7e7, 0xa1c97fad,
+ 0x56a157e3, 0xa1c53ef0,
+ 0x569cb7a8, 0xa1c0fe6c, 0x56981739, 0xa1bcbe22, 0x56937694, 0xa1b87e13,
+ 0x568ed5b9, 0xa1b43e3e,
+ 0x568a34a9, 0xa1affea3, 0x56859364, 0xa1abbf42, 0x5680f1ea, 0xa1a7801b,
+ 0x567c503a, 0xa1a3412f,
+ 0x5677ae54, 0xa19f027c, 0x56730c3a, 0xa19ac404, 0x566e69ea, 0xa19685c7,
+ 0x5669c765, 0xa19247c3,
+ 0x566524aa, 0xa18e09fa, 0x566081ba, 0xa189cc6b, 0x565bde95, 0xa1858f16,
+ 0x56573b3b, 0xa18151fb,
+ 0x565297ab, 0xa17d151b, 0x564df3e6, 0xa178d875, 0x56494fec, 0xa1749c09,
+ 0x5644abbc, 0xa1705fd8,
+ 0x56400758, 0xa16c23e1, 0x563b62be, 0xa167e824, 0x5636bdef, 0xa163aca2,
+ 0x563218eb, 0xa15f715a,
+ 0x562d73b2, 0xa15b364d, 0x5628ce43, 0xa156fb79, 0x5624289f, 0xa152c0e1,
+ 0x561f82c7, 0xa14e8682,
+ 0x561adcb9, 0xa14a4c5e, 0x56163676, 0xa1461275, 0x56118ffe, 0xa141d8c5,
+ 0x560ce950, 0xa13d9f51,
+ 0x5608426e, 0xa1396617, 0x56039b57, 0xa1352d17, 0x55fef40a, 0xa130f451,
+ 0x55fa4c89, 0xa12cbbc7,
+ 0x55f5a4d2, 0xa1288376, 0x55f0fce7, 0xa1244b61, 0x55ec54c6, 0xa1201385,
+ 0x55e7ac71, 0xa11bdbe4,
+ 0x55e303e6, 0xa117a47e, 0x55de5b27, 0xa1136d52, 0x55d9b232, 0xa10f3661,
+ 0x55d50909, 0xa10affab,
+ 0x55d05faa, 0xa106c92f, 0x55cbb617, 0xa10292ed, 0x55c70c4f, 0xa0fe5ce6,
+ 0x55c26251, 0xa0fa271a,
+ 0x55bdb81f, 0xa0f5f189, 0x55b90db8, 0xa0f1bc32, 0x55b4631d, 0xa0ed8715,
+ 0x55afb84c, 0xa0e95234,
+ 0x55ab0d46, 0xa0e51d8c, 0x55a6620c, 0xa0e0e920, 0x55a1b69d, 0xa0dcb4ee,
+ 0x559d0af9, 0xa0d880f7,
+ 0x55985f20, 0xa0d44d3b, 0x5593b312, 0xa0d019b9, 0x558f06d0, 0xa0cbe672,
+ 0x558a5a58, 0xa0c7b366,
+ 0x5585adad, 0xa0c38095, 0x558100cc, 0xa0bf4dfe, 0x557c53b6, 0xa0bb1ba2,
+ 0x5577a66c, 0xa0b6e981,
+ 0x5572f8ed, 0xa0b2b79b, 0x556e4b39, 0xa0ae85ef, 0x55699d51, 0xa0aa547e,
+ 0x5564ef34, 0xa0a62348,
+ 0x556040e2, 0xa0a1f24d, 0x555b925c, 0xa09dc18d, 0x5556e3a1, 0xa0999107,
+ 0x555234b1, 0xa09560bc,
+ 0x554d858d, 0xa09130ad, 0x5548d634, 0xa08d00d8, 0x554426a7, 0xa088d13e,
+ 0x553f76e4, 0xa084a1de,
+ 0x553ac6ee, 0xa08072ba, 0x553616c2, 0xa07c43d1, 0x55316663, 0xa0781522,
+ 0x552cb5ce, 0xa073e6af,
+ 0x55280505, 0xa06fb876, 0x55235408, 0xa06b8a78, 0x551ea2d6, 0xa0675cb6,
+ 0x5519f16f, 0xa0632f2e,
+ 0x55153fd4, 0xa05f01e1, 0x55108e05, 0xa05ad4cf, 0x550bdc01, 0xa056a7f9,
+ 0x550729c9, 0xa0527b5d,
+ 0x5502775c, 0xa04e4efc, 0x54fdc4ba, 0xa04a22d7, 0x54f911e5, 0xa045f6ec,
+ 0x54f45edb, 0xa041cb3c,
+ 0x54efab9c, 0xa03d9fc8, 0x54eaf829, 0xa039748e, 0x54e64482, 0xa0354990,
+ 0x54e190a6, 0xa0311ecd,
+ 0x54dcdc96, 0xa02cf444, 0x54d82852, 0xa028c9f7, 0x54d373d9, 0xa0249fe5,
+ 0x54cebf2c, 0xa020760e,
+ 0x54ca0a4b, 0xa01c4c73, 0x54c55535, 0xa0182312, 0x54c09feb, 0xa013f9ed,
+ 0x54bbea6d, 0xa00fd102,
+ 0x54b734ba, 0xa00ba853, 0x54b27ed3, 0xa0077fdf, 0x54adc8b8, 0xa00357a7,
+ 0x54a91269, 0x9fff2fa9,
+ 0x54a45be6, 0x9ffb07e7, 0x549fa52e, 0x9ff6e060, 0x549aee42, 0x9ff2b914,
+ 0x54963722, 0x9fee9204,
+ 0x54917fce, 0x9fea6b2f, 0x548cc845, 0x9fe64495, 0x54881089, 0x9fe21e36,
+ 0x54835898, 0x9fddf812,
+ 0x547ea073, 0x9fd9d22a, 0x5479e81a, 0x9fd5ac7d, 0x54752f8d, 0x9fd1870c,
+ 0x547076cc, 0x9fcd61d6,
+ 0x546bbdd7, 0x9fc93cdb, 0x546704ae, 0x9fc5181b, 0x54624b50, 0x9fc0f397,
+ 0x545d91bf, 0x9fbccf4f,
+ 0x5458d7f9, 0x9fb8ab41, 0x54541e00, 0x9fb4876f, 0x544f63d2, 0x9fb063d9,
+ 0x544aa971, 0x9fac407e,
+ 0x5445eedb, 0x9fa81d5e, 0x54413412, 0x9fa3fa79, 0x543c7914, 0x9f9fd7d1,
+ 0x5437bde3, 0x9f9bb563,
+ 0x5433027d, 0x9f979331, 0x542e46e4, 0x9f93713b, 0x54298b17, 0x9f8f4f80,
+ 0x5424cf16, 0x9f8b2e00,
+ 0x542012e1, 0x9f870cbc, 0x541b5678, 0x9f82ebb4, 0x541699db, 0x9f7ecae7,
+ 0x5411dd0a, 0x9f7aaa55,
+ 0x540d2005, 0x9f7689ff, 0x540862cd, 0x9f7269e5, 0x5403a561, 0x9f6e4a06,
+ 0x53fee7c1, 0x9f6a2a63,
+ 0x53fa29ed, 0x9f660afb, 0x53f56be5, 0x9f61ebcf, 0x53f0adaa, 0x9f5dccde,
+ 0x53ebef3a, 0x9f59ae29,
+ 0x53e73097, 0x9f558fb0, 0x53e271c0, 0x9f517173, 0x53ddb2b6, 0x9f4d5371,
+ 0x53d8f378, 0x9f4935aa,
+ 0x53d43406, 0x9f45181f, 0x53cf7460, 0x9f40fad0, 0x53cab486, 0x9f3cddbd,
+ 0x53c5f479, 0x9f38c0e5,
+ 0x53c13439, 0x9f34a449, 0x53bc73c4, 0x9f3087e9, 0x53b7b31c, 0x9f2c6bc5,
+ 0x53b2f240, 0x9f284fdc,
+ 0x53ae3131, 0x9f24342f, 0x53a96fee, 0x9f2018bd, 0x53a4ae77, 0x9f1bfd88,
+ 0x539feccd, 0x9f17e28e,
+ 0x539b2af0, 0x9f13c7d0, 0x539668de, 0x9f0fad4e, 0x5391a699, 0x9f0b9307,
+ 0x538ce421, 0x9f0778fd,
+ 0x53882175, 0x9f035f2e, 0x53835e95, 0x9eff459b, 0x537e9b82, 0x9efb2c44,
+ 0x5379d83c, 0x9ef71328,
+ 0x537514c2, 0x9ef2fa49, 0x53705114, 0x9eeee1a5, 0x536b8d33, 0x9eeac93e,
+ 0x5366c91f, 0x9ee6b112,
+ 0x536204d7, 0x9ee29922, 0x535d405c, 0x9ede816e, 0x53587bad, 0x9eda69f6,
+ 0x5353b6cb, 0x9ed652ba,
+ 0x534ef1b5, 0x9ed23bb9, 0x534a2c6c, 0x9ece24f5, 0x534566f0, 0x9eca0e6d,
+ 0x5340a140, 0x9ec5f820,
+ 0x533bdb5d, 0x9ec1e210, 0x53371547, 0x9ebdcc3b, 0x53324efd, 0x9eb9b6a3,
+ 0x532d8880, 0x9eb5a146,
+ 0x5328c1d0, 0x9eb18c26, 0x5323faec, 0x9ead7742, 0x531f33d5, 0x9ea96299,
+ 0x531a6c8b, 0x9ea54e2d,
+ 0x5315a50e, 0x9ea139fd, 0x5310dd5d, 0x9e9d2608, 0x530c1579, 0x9e991250,
+ 0x53074d62, 0x9e94fed4,
+ 0x53028518, 0x9e90eb94, 0x52fdbc9a, 0x9e8cd890, 0x52f8f3e9, 0x9e88c5c9,
+ 0x52f42b05, 0x9e84b33d,
+ 0x52ef61ee, 0x9e80a0ee, 0x52ea98a4, 0x9e7c8eda, 0x52e5cf27, 0x9e787d03,
+ 0x52e10576, 0x9e746b68,
+ 0x52dc3b92, 0x9e705a09, 0x52d7717b, 0x9e6c48e7, 0x52d2a732, 0x9e683800,
+ 0x52cddcb5, 0x9e642756,
+ 0x52c91204, 0x9e6016e8, 0x52c44721, 0x9e5c06b6, 0x52bf7c0b, 0x9e57f6c0,
+ 0x52bab0c2, 0x9e53e707,
+ 0x52b5e546, 0x9e4fd78a, 0x52b11996, 0x9e4bc849, 0x52ac4db4, 0x9e47b944,
+ 0x52a7819f, 0x9e43aa7c,
+ 0x52a2b556, 0x9e3f9bf0, 0x529de8db, 0x9e3b8da0, 0x52991c2d, 0x9e377f8c,
+ 0x52944f4c, 0x9e3371b5,
+ 0x528f8238, 0x9e2f641b, 0x528ab4f1, 0x9e2b56bc, 0x5285e777, 0x9e27499a,
+ 0x528119ca, 0x9e233cb4,
+ 0x527c4bea, 0x9e1f300b, 0x52777dd7, 0x9e1b239e, 0x5272af92, 0x9e17176d,
+ 0x526de11a, 0x9e130b79,
+ 0x5269126e, 0x9e0effc1, 0x52644390, 0x9e0af446, 0x525f7480, 0x9e06e907,
+ 0x525aa53c, 0x9e02de04,
+ 0x5255d5c5, 0x9dfed33e, 0x5251061c, 0x9dfac8b4, 0x524c3640, 0x9df6be67,
+ 0x52476631, 0x9df2b456,
+ 0x524295f0, 0x9deeaa82, 0x523dc57b, 0x9deaa0ea, 0x5238f4d4, 0x9de6978f,
+ 0x523423fb, 0x9de28e70,
+ 0x522f52ee, 0x9dde858e, 0x522a81af, 0x9dda7ce9, 0x5225b03d, 0x9dd6747f,
+ 0x5220de99, 0x9dd26c53,
+ 0x521c0cc2, 0x9dce6463, 0x52173ab8, 0x9dca5caf, 0x5212687b, 0x9dc65539,
+ 0x520d960c, 0x9dc24dfe,
+ 0x5208c36a, 0x9dbe4701, 0x5203f096, 0x9dba4040, 0x51ff1d8f, 0x9db639bb,
+ 0x51fa4a56, 0x9db23373,
+ 0x51f576ea, 0x9dae2d68, 0x51f0a34b, 0x9daa279a, 0x51ebcf7a, 0x9da62208,
+ 0x51e6fb76, 0x9da21cb2,
+ 0x51e22740, 0x9d9e179a, 0x51dd52d7, 0x9d9a12be, 0x51d87e3c, 0x9d960e1f,
+ 0x51d3a96f, 0x9d9209bd,
+ 0x51ced46e, 0x9d8e0597, 0x51c9ff3c, 0x9d8a01ae, 0x51c529d7, 0x9d85fe02,
+ 0x51c0543f, 0x9d81fa92,
+ 0x51bb7e75, 0x9d7df75f, 0x51b6a879, 0x9d79f469, 0x51b1d24a, 0x9d75f1b0,
+ 0x51acfbe9, 0x9d71ef34,
+ 0x51a82555, 0x9d6decf4, 0x51a34e8f, 0x9d69eaf1, 0x519e7797, 0x9d65e92b,
+ 0x5199a06d, 0x9d61e7a2,
+ 0x5194c910, 0x9d5de656, 0x518ff180, 0x9d59e546, 0x518b19bf, 0x9d55e473,
+ 0x518641cb, 0x9d51e3dd,
+ 0x518169a5, 0x9d4de385, 0x517c914c, 0x9d49e368, 0x5177b8c2, 0x9d45e389,
+ 0x5172e005, 0x9d41e3e7,
+ 0x516e0715, 0x9d3de482, 0x51692df4, 0x9d39e559, 0x516454a0, 0x9d35e66e,
+ 0x515f7b1a, 0x9d31e7bf,
+ 0x515aa162, 0x9d2de94d, 0x5155c778, 0x9d29eb19, 0x5150ed5c, 0x9d25ed21,
+ 0x514c130d, 0x9d21ef66,
+ 0x5147388c, 0x9d1df1e9, 0x51425dd9, 0x9d19f4a8, 0x513d82f4, 0x9d15f7a4,
+ 0x5138a7dd, 0x9d11fadd,
+ 0x5133cc94, 0x9d0dfe54, 0x512ef119, 0x9d0a0207, 0x512a156b, 0x9d0605f7,
+ 0x5125398c, 0x9d020a25,
+ 0x51205d7b, 0x9cfe0e8f, 0x511b8137, 0x9cfa1337, 0x5116a4c1, 0x9cf6181c,
+ 0x5111c81a, 0x9cf21d3d,
+ 0x510ceb40, 0x9cee229c, 0x51080e35, 0x9cea2838, 0x510330f7, 0x9ce62e11,
+ 0x50fe5388, 0x9ce23427,
+ 0x50f975e6, 0x9cde3a7b, 0x50f49813, 0x9cda410b, 0x50efba0d, 0x9cd647d9,
+ 0x50eadbd6, 0x9cd24ee4,
+ 0x50e5fd6d, 0x9cce562c, 0x50e11ed2, 0x9cca5db1, 0x50dc4005, 0x9cc66573,
+ 0x50d76106, 0x9cc26d73,
+ 0x50d281d5, 0x9cbe75b0, 0x50cda272, 0x9cba7e2a, 0x50c8c2de, 0x9cb686e1,
+ 0x50c3e317, 0x9cb28fd5,
+ 0x50bf031f, 0x9cae9907, 0x50ba22f5, 0x9caaa276, 0x50b5429a, 0x9ca6ac23,
+ 0x50b0620c, 0x9ca2b60c,
+ 0x50ab814d, 0x9c9ec033, 0x50a6a05c, 0x9c9aca97, 0x50a1bf39, 0x9c96d539,
+ 0x509cdde4, 0x9c92e017,
+ 0x5097fc5e, 0x9c8eeb34, 0x50931aa6, 0x9c8af68d, 0x508e38bd, 0x9c870224,
+ 0x508956a1, 0x9c830df8,
+ 0x50847454, 0x9c7f1a0a, 0x507f91d5, 0x9c7b2659, 0x507aaf25, 0x9c7732e5,
+ 0x5075cc43, 0x9c733faf,
+ 0x5070e92f, 0x9c6f4cb6, 0x506c05ea, 0x9c6b59fa, 0x50672273, 0x9c67677c,
+ 0x50623ecb, 0x9c63753c,
+ 0x505d5af1, 0x9c5f8339, 0x505876e5, 0x9c5b9173, 0x505392a8, 0x9c579feb,
+ 0x504eae39, 0x9c53aea0,
+ 0x5049c999, 0x9c4fbd93, 0x5044e4c7, 0x9c4bccc3, 0x503fffc4, 0x9c47dc31,
+ 0x503b1a8f, 0x9c43ebdc,
+ 0x50363529, 0x9c3ffbc5, 0x50314f91, 0x9c3c0beb, 0x502c69c8, 0x9c381c4f,
+ 0x502783cd, 0x9c342cf0,
+ 0x50229da1, 0x9c303dcf, 0x501db743, 0x9c2c4eec, 0x5018d0b4, 0x9c286046,
+ 0x5013e9f4, 0x9c2471de,
+ 0x500f0302, 0x9c2083b3, 0x500a1bdf, 0x9c1c95c6, 0x5005348a, 0x9c18a816,
+ 0x50004d04, 0x9c14baa4,
+ 0x4ffb654d, 0x9c10cd70, 0x4ff67d64, 0x9c0ce07a, 0x4ff1954b, 0x9c08f3c1,
+ 0x4fecacff, 0x9c050745,
+ 0x4fe7c483, 0x9c011b08, 0x4fe2dbd5, 0x9bfd2f08, 0x4fddf2f6, 0x9bf94346,
+ 0x4fd909e5, 0x9bf557c1,
+ 0x4fd420a4, 0x9bf16c7a, 0x4fcf3731, 0x9bed8171, 0x4fca4d8d, 0x9be996a6,
+ 0x4fc563b7, 0x9be5ac18,
+ 0x4fc079b1, 0x9be1c1c8, 0x4fbb8f79, 0x9bddd7b6, 0x4fb6a510, 0x9bd9ede2,
+ 0x4fb1ba76, 0x9bd6044b,
+ 0x4faccfab, 0x9bd21af3, 0x4fa7e4af, 0x9bce31d8, 0x4fa2f981, 0x9bca48fa,
+ 0x4f9e0e22, 0x9bc6605b,
+ 0x4f992293, 0x9bc277fa, 0x4f9436d2, 0x9bbe8fd6, 0x4f8f4ae0, 0x9bbaa7f0,
+ 0x4f8a5ebd, 0x9bb6c048,
+ 0x4f857269, 0x9bb2d8de, 0x4f8085e4, 0x9baef1b2, 0x4f7b992d, 0x9bab0ac3,
+ 0x4f76ac46, 0x9ba72413,
+ 0x4f71bf2e, 0x9ba33da0, 0x4f6cd1e5, 0x9b9f576b, 0x4f67e46a, 0x9b9b7174,
+ 0x4f62f6bf, 0x9b978bbc,
+ 0x4f5e08e3, 0x9b93a641, 0x4f591ad6, 0x9b8fc104, 0x4f542c98, 0x9b8bdc05,
+ 0x4f4f3e29, 0x9b87f744,
+ 0x4f4a4f89, 0x9b8412c1, 0x4f4560b8, 0x9b802e7b, 0x4f4071b6, 0x9b7c4a74,
+ 0x4f3b8284, 0x9b7866ab,
+ 0x4f369320, 0x9b748320, 0x4f31a38c, 0x9b709fd3, 0x4f2cb3c7, 0x9b6cbcc4,
+ 0x4f27c3d1, 0x9b68d9f3,
+ 0x4f22d3aa, 0x9b64f760, 0x4f1de352, 0x9b61150b, 0x4f18f2c9, 0x9b5d32f4,
+ 0x4f140210, 0x9b59511c,
+ 0x4f0f1126, 0x9b556f81, 0x4f0a200b, 0x9b518e24, 0x4f052ec0, 0x9b4dad06,
+ 0x4f003d43, 0x9b49cc26,
+ 0x4efb4b96, 0x9b45eb83, 0x4ef659b8, 0x9b420b1f, 0x4ef167aa, 0x9b3e2af9,
+ 0x4eec756b, 0x9b3a4b11,
+ 0x4ee782fb, 0x9b366b68, 0x4ee2905a, 0x9b328bfc, 0x4edd9d89, 0x9b2eaccf,
+ 0x4ed8aa87, 0x9b2acde0,
+ 0x4ed3b755, 0x9b26ef2f, 0x4ecec3f2, 0x9b2310bc, 0x4ec9d05e, 0x9b1f3288,
+ 0x4ec4dc99, 0x9b1b5492,
+ 0x4ebfe8a5, 0x9b1776da, 0x4ebaf47f, 0x9b139960, 0x4eb60029, 0x9b0fbc24,
+ 0x4eb10ba2, 0x9b0bdf27,
+ 0x4eac16eb, 0x9b080268, 0x4ea72203, 0x9b0425e8, 0x4ea22ceb, 0x9b0049a5,
+ 0x4e9d37a3, 0x9afc6da1,
+ 0x4e984229, 0x9af891db, 0x4e934c80, 0x9af4b654, 0x4e8e56a5, 0x9af0db0b,
+ 0x4e89609b, 0x9aed0000,
+ 0x4e846a60, 0x9ae92533, 0x4e7f73f4, 0x9ae54aa5, 0x4e7a7d58, 0x9ae17056,
+ 0x4e75868c, 0x9add9644,
+ 0x4e708f8f, 0x9ad9bc71, 0x4e6b9862, 0x9ad5e2dd, 0x4e66a105, 0x9ad20987,
+ 0x4e61a977, 0x9ace306f,
+ 0x4e5cb1b9, 0x9aca5795, 0x4e57b9ca, 0x9ac67efb, 0x4e52c1ab, 0x9ac2a69e,
+ 0x4e4dc95c, 0x9abece80,
+ 0x4e48d0dd, 0x9abaf6a1, 0x4e43d82d, 0x9ab71eff, 0x4e3edf4d, 0x9ab3479d,
+ 0x4e39e63d, 0x9aaf7079,
+ 0x4e34ecfc, 0x9aab9993, 0x4e2ff38b, 0x9aa7c2ec, 0x4e2af9ea, 0x9aa3ec83,
+ 0x4e260019, 0x9aa01659,
+ 0x4e210617, 0x9a9c406e, 0x4e1c0be6, 0x9a986ac1, 0x4e171184, 0x9a949552,
+ 0x4e1216f2, 0x9a90c022,
+ 0x4e0d1c30, 0x9a8ceb31, 0x4e08213e, 0x9a89167e, 0x4e03261b, 0x9a85420a,
+ 0x4dfe2ac9, 0x9a816dd5,
+ 0x4df92f46, 0x9a7d99de, 0x4df43393, 0x9a79c625, 0x4def37b0, 0x9a75f2ac,
+ 0x4dea3b9d, 0x9a721f71,
+ 0x4de53f5a, 0x9a6e4c74, 0x4de042e7, 0x9a6a79b6, 0x4ddb4644, 0x9a66a737,
+ 0x4dd64971, 0x9a62d4f7,
+ 0x4dd14c6e, 0x9a5f02f5, 0x4dcc4f3b, 0x9a5b3132, 0x4dc751d8, 0x9a575fae,
+ 0x4dc25445, 0x9a538e68,
+ 0x4dbd5682, 0x9a4fbd61, 0x4db8588f, 0x9a4bec99, 0x4db35a6c, 0x9a481c0f,
+ 0x4dae5c19, 0x9a444bc5,
+ 0x4da95d96, 0x9a407bb9, 0x4da45ee3, 0x9a3cabeb, 0x4d9f6001, 0x9a38dc5d,
+ 0x4d9a60ee, 0x9a350d0d,
+ 0x4d9561ac, 0x9a313dfc, 0x4d90623a, 0x9a2d6f2a, 0x4d8b6298, 0x9a29a097,
+ 0x4d8662c6, 0x9a25d243,
+ 0x4d8162c4, 0x9a22042d, 0x4d7c6293, 0x9a1e3656, 0x4d776231, 0x9a1a68be,
+ 0x4d7261a0, 0x9a169b65,
+ 0x4d6d60df, 0x9a12ce4b, 0x4d685fef, 0x9a0f016f, 0x4d635ece, 0x9a0b34d3,
+ 0x4d5e5d7e, 0x9a076875,
+ 0x4d595bfe, 0x9a039c57, 0x4d545a4f, 0x99ffd077, 0x4d4f5870, 0x99fc04d6,
+ 0x4d4a5661, 0x99f83974,
+ 0x4d455422, 0x99f46e51, 0x4d4051b4, 0x99f0a36d, 0x4d3b4f16, 0x99ecd8c8,
+ 0x4d364c48, 0x99e90e62,
+ 0x4d31494b, 0x99e5443b, 0x4d2c461e, 0x99e17a53, 0x4d2742c2, 0x99ddb0aa,
+ 0x4d223f36, 0x99d9e73f,
+ 0x4d1d3b7a, 0x99d61e14, 0x4d18378f, 0x99d25528, 0x4d133374, 0x99ce8c7b,
+ 0x4d0e2f2a, 0x99cac40d,
+ 0x4d092ab0, 0x99c6fbde, 0x4d042607, 0x99c333ee, 0x4cff212e, 0x99bf6c3d,
+ 0x4cfa1c26, 0x99bba4cb,
+ 0x4cf516ee, 0x99b7dd99, 0x4cf01187, 0x99b416a5, 0x4ceb0bf0, 0x99b04ff0,
+ 0x4ce6062a, 0x99ac897b,
+ 0x4ce10034, 0x99a8c345, 0x4cdbfa0f, 0x99a4fd4d, 0x4cd6f3bb, 0x99a13795,
+ 0x4cd1ed37, 0x999d721c,
+ 0x4ccce684, 0x9999ace3, 0x4cc7dfa1, 0x9995e7e8, 0x4cc2d88f, 0x9992232d,
+ 0x4cbdd14e, 0x998e5eb1,
+ 0x4cb8c9dd, 0x998a9a74, 0x4cb3c23d, 0x9986d676, 0x4caeba6e, 0x998312b7,
+ 0x4ca9b26f, 0x997f4f38,
+ 0x4ca4aa41, 0x997b8bf8, 0x4c9fa1e4, 0x9977c8f7, 0x4c9a9958, 0x99740635,
+ 0x4c95909c, 0x997043b2,
+ 0x4c9087b1, 0x996c816f, 0x4c8b7e97, 0x9968bf6b, 0x4c86754e, 0x9964fda7,
+ 0x4c816bd5, 0x99613c22,
+ 0x4c7c622d, 0x995d7adc, 0x4c775856, 0x9959b9d5, 0x4c724e50, 0x9955f90d,
+ 0x4c6d441b, 0x99523885,
+ 0x4c6839b7, 0x994e783d, 0x4c632f23, 0x994ab833, 0x4c5e2460, 0x9946f869,
+ 0x4c59196f, 0x994338df,
+ 0x4c540e4e, 0x993f7993, 0x4c4f02fe, 0x993bba87, 0x4c49f77f, 0x9937fbbb,
+ 0x4c44ebd1, 0x99343d2e,
+ 0x4c3fdff4, 0x99307ee0, 0x4c3ad3e7, 0x992cc0d2, 0x4c35c7ac, 0x99290303,
+ 0x4c30bb42, 0x99254574,
+ 0x4c2baea9, 0x99218824, 0x4c26a1e1, 0x991dcb13, 0x4c2194e9, 0x991a0e42,
+ 0x4c1c87c3, 0x991651b1,
+ 0x4c177a6e, 0x9912955f, 0x4c126cea, 0x990ed94c, 0x4c0d5f37, 0x990b1d79,
+ 0x4c085156, 0x990761e5,
+ 0x4c034345, 0x9903a691, 0x4bfe3505, 0x98ffeb7d, 0x4bf92697, 0x98fc30a8,
+ 0x4bf417f9, 0x98f87612,
+ 0x4bef092d, 0x98f4bbbc, 0x4be9fa32, 0x98f101a6, 0x4be4eb08, 0x98ed47cf,
+ 0x4bdfdbaf, 0x98e98e38,
+ 0x4bdacc28, 0x98e5d4e0, 0x4bd5bc72, 0x98e21bc8, 0x4bd0ac8d, 0x98de62f0,
+ 0x4bcb9c79, 0x98daaa57,
+ 0x4bc68c36, 0x98d6f1fe, 0x4bc17bc5, 0x98d339e4, 0x4bbc6b25, 0x98cf820b,
+ 0x4bb75a56, 0x98cbca70,
+ 0x4bb24958, 0x98c81316, 0x4bad382c, 0x98c45bfb, 0x4ba826d1, 0x98c0a520,
+ 0x4ba31548, 0x98bcee84,
+ 0x4b9e0390, 0x98b93828, 0x4b98f1a9, 0x98b5820c, 0x4b93df93, 0x98b1cc30,
+ 0x4b8ecd4f, 0x98ae1693,
+ 0x4b89badd, 0x98aa6136, 0x4b84a83b, 0x98a6ac19, 0x4b7f956b, 0x98a2f73c,
+ 0x4b7a826d, 0x989f429e,
+ 0x4b756f40, 0x989b8e40, 0x4b705be4, 0x9897da22, 0x4b6b485a, 0x98942643,
+ 0x4b6634a2, 0x989072a5,
+ 0x4b6120bb, 0x988cbf46, 0x4b5c0ca5, 0x98890c27, 0x4b56f861, 0x98855948,
+ 0x4b51e3ee, 0x9881a6a9,
+ 0x4b4ccf4d, 0x987df449, 0x4b47ba7e, 0x987a422a, 0x4b42a580, 0x9876904a,
+ 0x4b3d9053, 0x9872deaa,
+ 0x4b387af9, 0x986f2d4a, 0x4b336570, 0x986b7c2a, 0x4b2e4fb8, 0x9867cb4a,
+ 0x4b2939d2, 0x98641aa9,
+ 0x4b2423be, 0x98606a49, 0x4b1f0d7b, 0x985cba28, 0x4b19f70a, 0x98590a48,
+ 0x4b14e06b, 0x98555aa7,
+ 0x4b0fc99d, 0x9851ab46, 0x4b0ab2a1, 0x984dfc26, 0x4b059b77, 0x984a4d45,
+ 0x4b00841f, 0x98469ea4,
+ 0x4afb6c98, 0x9842f043, 0x4af654e3, 0x983f4223, 0x4af13d00, 0x983b9442,
+ 0x4aec24ee, 0x9837e6a1,
+ 0x4ae70caf, 0x98343940, 0x4ae1f441, 0x98308c1f, 0x4adcdba5, 0x982cdf3f,
+ 0x4ad7c2da, 0x9829329e,
+ 0x4ad2a9e2, 0x9825863d, 0x4acd90bb, 0x9821da1d, 0x4ac87767, 0x981e2e3c,
+ 0x4ac35de4, 0x981a829c,
+ 0x4abe4433, 0x9816d73b, 0x4ab92a54, 0x98132c1b, 0x4ab41046, 0x980f813b,
+ 0x4aaef60b, 0x980bd69b,
+ 0x4aa9dba2, 0x98082c3b, 0x4aa4c10b, 0x9804821b, 0x4a9fa645, 0x9800d83c,
+ 0x4a9a8b52, 0x97fd2e9c,
+ 0x4a957030, 0x97f9853d, 0x4a9054e1, 0x97f5dc1e, 0x4a8b3963, 0x97f2333f,
+ 0x4a861db8, 0x97ee8aa0,
+ 0x4a8101de, 0x97eae242, 0x4a7be5d7, 0x97e73a23, 0x4a76c9a2, 0x97e39245,
+ 0x4a71ad3e, 0x97dfeaa7,
+ 0x4a6c90ad, 0x97dc4349, 0x4a6773ee, 0x97d89c2c, 0x4a625701, 0x97d4f54f,
+ 0x4a5d39e6, 0x97d14eb2,
+ 0x4a581c9e, 0x97cda855, 0x4a52ff27, 0x97ca0239, 0x4a4de182, 0x97c65c5c,
+ 0x4a48c3b0, 0x97c2b6c1,
+ 0x4a43a5b0, 0x97bf1165, 0x4a3e8782, 0x97bb6c4a, 0x4a396926, 0x97b7c76f,
+ 0x4a344a9d, 0x97b422d4,
+ 0x4a2f2be6, 0x97b07e7a, 0x4a2a0d01, 0x97acda60, 0x4a24edee, 0x97a93687,
+ 0x4a1fcead, 0x97a592ed,
+ 0x4a1aaf3f, 0x97a1ef94, 0x4a158fa3, 0x979e4c7c, 0x4a106fda, 0x979aa9a4,
+ 0x4a0b4fe2, 0x9797070c,
+ 0x4a062fbd, 0x979364b5, 0x4a010f6b, 0x978fc29e, 0x49fbeeea, 0x978c20c8,
+ 0x49f6ce3c, 0x97887f32,
+ 0x49f1ad61, 0x9784dddc, 0x49ec8c57, 0x97813cc7, 0x49e76b21, 0x977d9bf2,
+ 0x49e249bc, 0x9779fb5e,
+ 0x49dd282a, 0x97765b0a, 0x49d8066b, 0x9772baf7, 0x49d2e47e, 0x976f1b24,
+ 0x49cdc263, 0x976b7b92,
+ 0x49c8a01b, 0x9767dc41, 0x49c37da5, 0x97643d2f, 0x49be5b02, 0x97609e5f,
+ 0x49b93832, 0x975cffcf,
+ 0x49b41533, 0x9759617f, 0x49aef208, 0x9755c370, 0x49a9ceaf, 0x975225a1,
+ 0x49a4ab28, 0x974e8813,
+ 0x499f8774, 0x974aeac6, 0x499a6393, 0x97474db9, 0x49953f84, 0x9743b0ed,
+ 0x49901b48, 0x97401462,
+ 0x498af6df, 0x973c7817, 0x4985d248, 0x9738dc0d, 0x4980ad84, 0x97354043,
+ 0x497b8892, 0x9731a4ba,
+ 0x49766373, 0x972e0971, 0x49713e27, 0x972a6e6a, 0x496c18ae, 0x9726d3a3,
+ 0x4966f307, 0x9723391c,
+ 0x4961cd33, 0x971f9ed7, 0x495ca732, 0x971c04d2, 0x49578103, 0x97186b0d,
+ 0x49525aa7, 0x9714d18a,
+ 0x494d341e, 0x97113847, 0x49480d68, 0x970d9f45, 0x4942e684, 0x970a0683,
+ 0x493dbf74, 0x97066e03,
+ 0x49389836, 0x9702d5c3, 0x493370cb, 0x96ff3dc4, 0x492e4933, 0x96fba605,
+ 0x4929216e, 0x96f80e88,
+ 0x4923f97b, 0x96f4774b, 0x491ed15c, 0x96f0e04f, 0x4919a90f, 0x96ed4994,
+ 0x49148095, 0x96e9b319,
+ 0x490f57ee, 0x96e61ce0, 0x490a2f1b, 0x96e286e7, 0x4905061a, 0x96def12f,
+ 0x48ffdcec, 0x96db5bb8,
+ 0x48fab391, 0x96d7c682, 0x48f58a09, 0x96d4318d, 0x48f06054, 0x96d09cd8,
+ 0x48eb3672, 0x96cd0865,
+ 0x48e60c62, 0x96c97432, 0x48e0e227, 0x96c5e040, 0x48dbb7be, 0x96c24c8f,
+ 0x48d68d28, 0x96beb91f,
+ 0x48d16265, 0x96bb25f0, 0x48cc3775, 0x96b79302, 0x48c70c59, 0x96b40055,
+ 0x48c1e10f, 0x96b06de9,
+ 0x48bcb599, 0x96acdbbe, 0x48b789f5, 0x96a949d3, 0x48b25e25, 0x96a5b82a,
+ 0x48ad3228, 0x96a226c2,
+ 0x48a805ff, 0x969e959b, 0x48a2d9a8, 0x969b04b4, 0x489dad25, 0x9697740f,
+ 0x48988074, 0x9693e3ab,
+ 0x48935397, 0x96905388, 0x488e268e, 0x968cc3a5, 0x4888f957, 0x96893404,
+ 0x4883cbf4, 0x9685a4a4,
+ 0x487e9e64, 0x96821585, 0x487970a7, 0x967e86a7, 0x487442be, 0x967af80a,
+ 0x486f14a8, 0x967769af,
+ 0x4869e665, 0x9673db94, 0x4864b7f5, 0x96704dba, 0x485f8959, 0x966cc022,
+ 0x485a5a90, 0x966932cb,
+ 0x48552b9b, 0x9665a5b4, 0x484ffc79, 0x966218df, 0x484acd2a, 0x965e8c4b,
+ 0x48459daf, 0x965afff9,
+ 0x48406e08, 0x965773e7, 0x483b3e33, 0x9653e817, 0x48360e32, 0x96505c88,
+ 0x4830de05, 0x964cd139,
+ 0x482badab, 0x9649462d, 0x48267d24, 0x9645bb61, 0x48214c71, 0x964230d7,
+ 0x481c1b92, 0x963ea68d,
+ 0x4816ea86, 0x963b1c86, 0x4811b94d, 0x963792bf, 0x480c87e8, 0x96340939,
+ 0x48075657, 0x96307ff5,
+ 0x48022499, 0x962cf6f2, 0x47fcf2af, 0x96296e31, 0x47f7c099, 0x9625e5b0,
+ 0x47f28e56, 0x96225d71,
+ 0x47ed5be6, 0x961ed574, 0x47e8294a, 0x961b4db7, 0x47e2f682, 0x9617c63c,
+ 0x47ddc38e, 0x96143f02,
+ 0x47d8906d, 0x9610b80a, 0x47d35d20, 0x960d3153, 0x47ce29a7, 0x9609aadd,
+ 0x47c8f601, 0x960624a9,
+ 0x47c3c22f, 0x96029eb6, 0x47be8e31, 0x95ff1904, 0x47b95a06, 0x95fb9394,
+ 0x47b425af, 0x95f80e65,
+ 0x47aef12c, 0x95f48977, 0x47a9bc7d, 0x95f104cb, 0x47a487a2, 0x95ed8061,
+ 0x479f529a, 0x95e9fc38,
+ 0x479a1d67, 0x95e67850, 0x4794e807, 0x95e2f4a9, 0x478fb27b, 0x95df7145,
+ 0x478a7cc2, 0x95dbee21,
+ 0x478546de, 0x95d86b3f, 0x478010cd, 0x95d4e89f, 0x477ada91, 0x95d16640,
+ 0x4775a428, 0x95cde423,
+ 0x47706d93, 0x95ca6247, 0x476b36d3, 0x95c6e0ac, 0x4765ffe6, 0x95c35f53,
+ 0x4760c8cd, 0x95bfde3c,
+ 0x475b9188, 0x95bc5d66, 0x47565a17, 0x95b8dcd2, 0x4751227a, 0x95b55c7f,
+ 0x474beab1, 0x95b1dc6e,
+ 0x4746b2bc, 0x95ae5c9f, 0x47417a9b, 0x95aadd11, 0x473c424e, 0x95a75dc4,
+ 0x473709d5, 0x95a3deb9,
+ 0x4731d131, 0x95a05ff0, 0x472c9860, 0x959ce169, 0x47275f63, 0x95996323,
+ 0x4722263b, 0x9595e51e,
+ 0x471cece7, 0x9592675c, 0x4717b367, 0x958ee9db, 0x471279ba, 0x958b6c9b,
+ 0x470d3fe3, 0x9587ef9e,
+ 0x470805df, 0x958472e2, 0x4702cbaf, 0x9580f667, 0x46fd9154, 0x957d7a2f,
+ 0x46f856cd, 0x9579fe38,
+ 0x46f31c1a, 0x95768283, 0x46ede13b, 0x9573070f, 0x46e8a631, 0x956f8bdd,
+ 0x46e36afb, 0x956c10ed,
+ 0x46de2f99, 0x9568963f, 0x46d8f40b, 0x95651bd2, 0x46d3b852, 0x9561a1a8,
+ 0x46ce7c6d, 0x955e27bf,
+ 0x46c9405c, 0x955aae17, 0x46c40420, 0x955734b2, 0x46bec7b8, 0x9553bb8e,
+ 0x46b98b24, 0x955042ac,
+ 0x46b44e65, 0x954cca0c, 0x46af117a, 0x954951ae, 0x46a9d464, 0x9545d992,
+ 0x46a49722, 0x954261b7,
+ 0x469f59b4, 0x953eea1e, 0x469a1c1b, 0x953b72c7, 0x4694de56, 0x9537fbb2,
+ 0x468fa066, 0x953484df,
+ 0x468a624a, 0x95310e4e, 0x46852403, 0x952d97fe, 0x467fe590, 0x952a21f1,
+ 0x467aa6f2, 0x9526ac25,
+ 0x46756828, 0x9523369c, 0x46702933, 0x951fc154, 0x466aea12, 0x951c4c4e,
+ 0x4665aac6, 0x9518d78a,
+ 0x46606b4e, 0x95156308, 0x465b2bab, 0x9511eec8, 0x4655ebdd, 0x950e7aca,
+ 0x4650abe3, 0x950b070e,
+ 0x464b6bbe, 0x95079394, 0x46462b6d, 0x9504205c, 0x4640eaf2, 0x9500ad66,
+ 0x463baa4a, 0x94fd3ab1,
+ 0x46366978, 0x94f9c83f, 0x4631287a, 0x94f6560f, 0x462be751, 0x94f2e421,
+ 0x4626a5fd, 0x94ef7275,
+ 0x4621647d, 0x94ec010b, 0x461c22d2, 0x94e88fe3, 0x4616e0fc, 0x94e51efd,
+ 0x46119efa, 0x94e1ae59,
+ 0x460c5cce, 0x94de3df8, 0x46071a76, 0x94dacdd8, 0x4601d7f3, 0x94d75dfa,
+ 0x45fc9545, 0x94d3ee5f,
+ 0x45f7526b, 0x94d07f05, 0x45f20f67, 0x94cd0fee, 0x45eccc37, 0x94c9a119,
+ 0x45e788dc, 0x94c63286,
+ 0x45e24556, 0x94c2c435, 0x45dd01a5, 0x94bf5627, 0x45d7bdc9, 0x94bbe85a,
+ 0x45d279c2, 0x94b87ad0,
+ 0x45cd358f, 0x94b50d87, 0x45c7f132, 0x94b1a081, 0x45c2acaa, 0x94ae33be,
+ 0x45bd67f6, 0x94aac73c,
+ 0x45b82318, 0x94a75afd, 0x45b2de0e, 0x94a3eeff, 0x45ad98da, 0x94a08344,
+ 0x45a8537a, 0x949d17cc,
+ 0x45a30df0, 0x9499ac95, 0x459dc83b, 0x949641a1, 0x4598825a, 0x9492d6ef,
+ 0x45933c4f, 0x948f6c7f,
+ 0x458df619, 0x948c0252, 0x4588afb8, 0x94889867, 0x4583692c, 0x94852ebe,
+ 0x457e2275, 0x9481c557,
+ 0x4578db93, 0x947e5c33, 0x45739487, 0x947af351, 0x456e4d4f, 0x94778ab1,
+ 0x456905ed, 0x94742254,
+ 0x4563be60, 0x9470ba39, 0x455e76a8, 0x946d5260, 0x45592ec6, 0x9469eaca,
+ 0x4553e6b8, 0x94668376,
+ 0x454e9e80, 0x94631c65, 0x4549561d, 0x945fb596, 0x45440d90, 0x945c4f09,
+ 0x453ec4d7, 0x9458e8bf,
+ 0x45397bf4, 0x945582b7, 0x453432e6, 0x94521cf1, 0x452ee9ae, 0x944eb76e,
+ 0x4529a04b, 0x944b522d,
+ 0x452456bd, 0x9447ed2f, 0x451f0d04, 0x94448873, 0x4519c321, 0x944123fa,
+ 0x45147913, 0x943dbfc3,
+ 0x450f2edb, 0x943a5bcf, 0x4509e478, 0x9436f81d, 0x450499eb, 0x943394ad,
+ 0x44ff4f32, 0x94303180,
+ 0x44fa0450, 0x942cce96, 0x44f4b943, 0x94296bee, 0x44ef6e0b, 0x94260989,
+ 0x44ea22a9, 0x9422a766,
+ 0x44e4d71c, 0x941f4585, 0x44df8b64, 0x941be3e8, 0x44da3f83, 0x9418828c,
+ 0x44d4f376, 0x94152174,
+ 0x44cfa740, 0x9411c09e, 0x44ca5adf, 0x940e600a, 0x44c50e53, 0x940affb9,
+ 0x44bfc19d, 0x94079fab,
+ 0x44ba74bd, 0x94043fdf, 0x44b527b2, 0x9400e056, 0x44afda7d, 0x93fd810f,
+ 0x44aa8d1d, 0x93fa220b,
+ 0x44a53f93, 0x93f6c34a, 0x449ff1df, 0x93f364cb, 0x449aa400, 0x93f0068f,
+ 0x449555f7, 0x93eca896,
+ 0x449007c4, 0x93e94adf, 0x448ab967, 0x93e5ed6b, 0x44856adf, 0x93e2903a,
+ 0x44801c2d, 0x93df334c,
+ 0x447acd50, 0x93dbd6a0, 0x44757e4a, 0x93d87a36, 0x44702f19, 0x93d51e10,
+ 0x446adfbe, 0x93d1c22c,
+ 0x44659039, 0x93ce668b, 0x44604089, 0x93cb0b2d, 0x445af0b0, 0x93c7b011,
+ 0x4455a0ac, 0x93c45539,
+ 0x4450507e, 0x93c0faa3, 0x444b0026, 0x93bda04f, 0x4445afa4, 0x93ba463f,
+ 0x44405ef8, 0x93b6ec71,
+ 0x443b0e21, 0x93b392e6, 0x4435bd21, 0x93b0399e, 0x44306bf6, 0x93ace099,
+ 0x442b1aa2, 0x93a987d6,
+ 0x4425c923, 0x93a62f57, 0x4420777b, 0x93a2d71a, 0x441b25a8, 0x939f7f20,
+ 0x4415d3ab, 0x939c2769,
+ 0x44108184, 0x9398cff5, 0x440b2f34, 0x939578c3, 0x4405dcb9, 0x939221d5,
+ 0x44008a14, 0x938ecb29,
+ 0x43fb3746, 0x938b74c1, 0x43f5e44d, 0x93881e9b, 0x43f0912b, 0x9384c8b8,
+ 0x43eb3ddf, 0x93817318,
+ 0x43e5ea68, 0x937e1dbb, 0x43e096c8, 0x937ac8a1, 0x43db42fe, 0x937773ca,
+ 0x43d5ef0a, 0x93741f35,
+ 0x43d09aed, 0x9370cae4, 0x43cb46a5, 0x936d76d6, 0x43c5f234, 0x936a230a,
+ 0x43c09d99, 0x9366cf82,
+ 0x43bb48d4, 0x93637c3d, 0x43b5f3e5, 0x9360293a, 0x43b09ecc, 0x935cd67b,
+ 0x43ab498a, 0x935983ff,
+ 0x43a5f41e, 0x935631c5, 0x43a09e89, 0x9352dfcf, 0x439b48c9, 0x934f8e1c,
+ 0x4395f2e0, 0x934c3cab,
+ 0x43909ccd, 0x9348eb7e, 0x438b4691, 0x93459a94, 0x4385f02a, 0x934249ed,
+ 0x4380999b, 0x933ef989,
+ 0x437b42e1, 0x933ba968, 0x4375ebfe, 0x9338598a, 0x437094f1, 0x933509f0,
+ 0x436b3dbb, 0x9331ba98,
+ 0x4365e65b, 0x932e6b84, 0x43608ed2, 0x932b1cb2, 0x435b371f, 0x9327ce24,
+ 0x4355df42, 0x93247fd9,
+ 0x4350873c, 0x932131d1, 0x434b2f0c, 0x931de40c, 0x4345d6b3, 0x931a968b,
+ 0x43407e31, 0x9317494c,
+ 0x433b2585, 0x9313fc51, 0x4335ccaf, 0x9310af99, 0x433073b0, 0x930d6324,
+ 0x432b1a87, 0x930a16f3,
+ 0x4325c135, 0x9306cb04, 0x432067ba, 0x93037f59, 0x431b0e15, 0x930033f1,
+ 0x4315b447, 0x92fce8cc,
+ 0x43105a50, 0x92f99deb, 0x430b002f, 0x92f6534c, 0x4305a5e5, 0x92f308f1,
+ 0x43004b71, 0x92efbeda,
+ 0x42faf0d4, 0x92ec7505, 0x42f5960e, 0x92e92b74, 0x42f03b1e, 0x92e5e226,
+ 0x42eae005, 0x92e2991c,
+ 0x42e584c3, 0x92df5054, 0x42e02958, 0x92dc07d0, 0x42dacdc3, 0x92d8bf90,
+ 0x42d57205, 0x92d57792,
+ 0x42d0161e, 0x92d22fd9, 0x42caba0e, 0x92cee862, 0x42c55dd4, 0x92cba12f,
+ 0x42c00172, 0x92c85a3f,
+ 0x42baa4e6, 0x92c51392, 0x42b54831, 0x92c1cd29, 0x42afeb53, 0x92be8703,
+ 0x42aa8e4b, 0x92bb4121,
+ 0x42a5311b, 0x92b7fb82, 0x429fd3c1, 0x92b4b626, 0x429a763f, 0x92b1710e,
+ 0x42951893, 0x92ae2c3a,
+ 0x428fbabe, 0x92aae7a8, 0x428a5cc0, 0x92a7a35a, 0x4284fe99, 0x92a45f50,
+ 0x427fa049, 0x92a11b89,
+ 0x427a41d0, 0x929dd806, 0x4274e32e, 0x929a94c6, 0x426f8463, 0x929751c9,
+ 0x426a256f, 0x92940f10,
+ 0x4264c653, 0x9290cc9b, 0x425f670d, 0x928d8a69, 0x425a079e, 0x928a487a,
+ 0x4254a806, 0x928706cf,
+ 0x424f4845, 0x9283c568, 0x4249e85c, 0x92808444, 0x42448849, 0x927d4363,
+ 0x423f280e, 0x927a02c7,
+ 0x4239c7aa, 0x9276c26d, 0x4234671d, 0x92738258, 0x422f0667, 0x92704286,
+ 0x4229a588, 0x926d02f7,
+ 0x42244481, 0x9269c3ac, 0x421ee350, 0x926684a5, 0x421981f7, 0x926345e1,
+ 0x42142075, 0x92600761,
+ 0x420ebecb, 0x925cc924, 0x42095cf7, 0x92598b2b, 0x4203fafb, 0x92564d76,
+ 0x41fe98d6, 0x92531005,
+ 0x41f93689, 0x924fd2d7, 0x41f3d413, 0x924c95ec, 0x41ee7174, 0x92495946,
+ 0x41e90eac, 0x92461ce3,
+ 0x41e3abbc, 0x9242e0c4, 0x41de48a3, 0x923fa4e8, 0x41d8e561, 0x923c6950,
+ 0x41d381f7, 0x92392dfc,
+ 0x41ce1e65, 0x9235f2ec, 0x41c8baa9, 0x9232b81f, 0x41c356c5, 0x922f7d96,
+ 0x41bdf2b9, 0x922c4351,
+ 0x41b88e84, 0x9229094f, 0x41b32a26, 0x9225cf91, 0x41adc5a0, 0x92229617,
+ 0x41a860f1, 0x921f5ce1,
+ 0x41a2fc1a, 0x921c23ef, 0x419d971b, 0x9218eb40, 0x419831f3, 0x9215b2d5,
+ 0x4192cca2, 0x92127aae,
+ 0x418d6729, 0x920f42cb, 0x41880188, 0x920c0b2c, 0x41829bbe, 0x9208d3d0,
+ 0x417d35cb, 0x92059cb8,
+ 0x4177cfb1, 0x920265e4, 0x4172696e, 0x91ff2f54, 0x416d0302, 0x91fbf908,
+ 0x41679c6f, 0x91f8c300,
+ 0x416235b2, 0x91f58d3b, 0x415ccece, 0x91f257bb, 0x415767c1, 0x91ef227e,
+ 0x4152008c, 0x91ebed85,
+ 0x414c992f, 0x91e8b8d0, 0x414731a9, 0x91e5845f, 0x4141c9fb, 0x91e25032,
+ 0x413c6225, 0x91df1c49,
+ 0x4136fa27, 0x91dbe8a4, 0x41319200, 0x91d8b542, 0x412c29b1, 0x91d58225,
+ 0x4126c13a, 0x91d24f4c,
+ 0x4121589b, 0x91cf1cb6, 0x411befd3, 0x91cbea65, 0x411686e4, 0x91c8b857,
+ 0x41111dcc, 0x91c5868e,
+ 0x410bb48c, 0x91c25508, 0x41064b24, 0x91bf23c7, 0x4100e194, 0x91bbf2c9,
+ 0x40fb77dc, 0x91b8c210,
+ 0x40f60dfb, 0x91b5919a, 0x40f0a3f3, 0x91b26169, 0x40eb39c3, 0x91af317c,
+ 0x40e5cf6a, 0x91ac01d2,
+ 0x40e064ea, 0x91a8d26d, 0x40dafa41, 0x91a5a34c, 0x40d58f71, 0x91a2746f,
+ 0x40d02478, 0x919f45d6,
+ 0x40cab958, 0x919c1781, 0x40c54e0f, 0x9198e970, 0x40bfe29f, 0x9195bba3,
+ 0x40ba7706, 0x91928e1a,
+ 0x40b50b46, 0x918f60d6, 0x40af9f5e, 0x918c33d5, 0x40aa334e, 0x91890719,
+ 0x40a4c716, 0x9185daa1,
+ 0x409f5ab6, 0x9182ae6d, 0x4099ee2e, 0x917f827d, 0x4094817f, 0x917c56d1,
+ 0x408f14a7, 0x91792b6a,
+ 0x4089a7a8, 0x91760047, 0x40843a81, 0x9172d567, 0x407ecd32, 0x916faacc,
+ 0x40795fbc, 0x916c8076,
+ 0x4073f21d, 0x91695663, 0x406e8457, 0x91662c95, 0x40691669, 0x9163030b,
+ 0x4063a854, 0x915fd9c5,
+ 0x405e3a16, 0x915cb0c3, 0x4058cbb1, 0x91598806, 0x40535d24, 0x91565f8d,
+ 0x404dee70, 0x91533758,
+ 0x40487f94, 0x91500f67, 0x40431090, 0x914ce7bb, 0x403da165, 0x9149c053,
+ 0x40383212, 0x9146992f,
+ 0x4032c297, 0x91437250, 0x402d52f5, 0x91404bb5, 0x4027e32b, 0x913d255e,
+ 0x4022733a, 0x9139ff4b,
+ 0x401d0321, 0x9136d97d, 0x401792e0, 0x9133b3f3, 0x40122278, 0x91308eae,
+ 0x400cb1e9, 0x912d69ad,
+ 0x40074132, 0x912a44f0, 0x4001d053, 0x91272078, 0x3ffc5f4d, 0x9123fc44,
+ 0x3ff6ee1f, 0x9120d854,
+ 0x3ff17cca, 0x911db4a9, 0x3fec0b4e, 0x911a9142, 0x3fe699aa, 0x91176e1f,
+ 0x3fe127df, 0x91144b41,
+ 0x3fdbb5ec, 0x911128a8, 0x3fd643d2, 0x910e0653, 0x3fd0d191, 0x910ae442,
+ 0x3fcb5f28, 0x9107c276,
+ 0x3fc5ec98, 0x9104a0ee, 0x3fc079e0, 0x91017faa, 0x3fbb0702, 0x90fe5eab,
+ 0x3fb593fb, 0x90fb3df1,
+ 0x3fb020ce, 0x90f81d7b, 0x3faaad79, 0x90f4fd4a, 0x3fa539fd, 0x90f1dd5d,
+ 0x3f9fc65a, 0x90eebdb4,
+ 0x3f9a5290, 0x90eb9e50, 0x3f94de9e, 0x90e87f31, 0x3f8f6a85, 0x90e56056,
+ 0x3f89f645, 0x90e241bf,
+ 0x3f8481dd, 0x90df236e, 0x3f7f0d4f, 0x90dc0560, 0x3f799899, 0x90d8e798,
+ 0x3f7423bc, 0x90d5ca13,
+ 0x3f6eaeb8, 0x90d2acd4, 0x3f69398d, 0x90cf8fd9, 0x3f63c43b, 0x90cc7322,
+ 0x3f5e4ec2, 0x90c956b1,
+ 0x3f58d921, 0x90c63a83, 0x3f53635a, 0x90c31e9b, 0x3f4ded6b, 0x90c002f7,
+ 0x3f487755, 0x90bce797,
+ 0x3f430119, 0x90b9cc7d, 0x3f3d8ab5, 0x90b6b1a6, 0x3f38142a, 0x90b39715,
+ 0x3f329d79, 0x90b07cc8,
+ 0x3f2d26a0, 0x90ad62c0, 0x3f27afa1, 0x90aa48fd, 0x3f22387a, 0x90a72f7e,
+ 0x3f1cc12c, 0x90a41644,
+ 0x3f1749b8, 0x90a0fd4e, 0x3f11d21d, 0x909de49e, 0x3f0c5a5a, 0x909acc32,
+ 0x3f06e271, 0x9097b40a,
+ 0x3f016a61, 0x90949c28, 0x3efbf22a, 0x9091848a, 0x3ef679cc, 0x908e6d31,
+ 0x3ef10148, 0x908b561c,
+ 0x3eeb889c, 0x90883f4d, 0x3ee60fca, 0x908528c2, 0x3ee096d1, 0x9082127c,
+ 0x3edb1db1, 0x907efc7a,
+ 0x3ed5a46b, 0x907be6be, 0x3ed02afd, 0x9078d146, 0x3ecab169, 0x9075bc13,
+ 0x3ec537ae, 0x9072a725,
+ 0x3ebfbdcd, 0x906f927c, 0x3eba43c4, 0x906c7e17, 0x3eb4c995, 0x906969f8,
+ 0x3eaf4f40, 0x9066561d,
+ 0x3ea9d4c3, 0x90634287, 0x3ea45a21, 0x90602f35, 0x3e9edf57, 0x905d1c29,
+ 0x3e996467, 0x905a0962,
+ 0x3e93e950, 0x9056f6df, 0x3e8e6e12, 0x9053e4a1, 0x3e88f2ae, 0x9050d2a9,
+ 0x3e837724, 0x904dc0f5,
+ 0x3e7dfb73, 0x904aaf86, 0x3e787f9b, 0x90479e5c, 0x3e73039d, 0x90448d76,
+ 0x3e6d8778, 0x90417cd6,
+ 0x3e680b2c, 0x903e6c7b, 0x3e628ebb, 0x903b5c64, 0x3e5d1222, 0x90384c93,
+ 0x3e579564, 0x90353d06,
+ 0x3e52187f, 0x90322dbf, 0x3e4c9b73, 0x902f1ebc, 0x3e471e41, 0x902c0fff,
+ 0x3e41a0e8, 0x90290186,
+ 0x3e3c2369, 0x9025f352, 0x3e36a5c4, 0x9022e564, 0x3e3127f9, 0x901fd7ba,
+ 0x3e2baa07, 0x901cca55,
+ 0x3e262bee, 0x9019bd36, 0x3e20adaf, 0x9016b05b, 0x3e1b2f4a, 0x9013a3c5,
+ 0x3e15b0bf, 0x90109775,
+ 0x3e10320d, 0x900d8b69, 0x3e0ab336, 0x900a7fa3, 0x3e053437, 0x90077422,
+ 0x3dffb513, 0x900468e5,
+ 0x3dfa35c8, 0x90015dee, 0x3df4b657, 0x8ffe533c, 0x3def36c0, 0x8ffb48cf,
+ 0x3de9b703, 0x8ff83ea7,
+ 0x3de4371f, 0x8ff534c4, 0x3ddeb716, 0x8ff22b26, 0x3dd936e6, 0x8fef21ce,
+ 0x3dd3b690, 0x8fec18ba,
+ 0x3dce3614, 0x8fe90fec, 0x3dc8b571, 0x8fe60763, 0x3dc334a9, 0x8fe2ff1f,
+ 0x3dbdb3ba, 0x8fdff720,
+ 0x3db832a6, 0x8fdcef66, 0x3db2b16b, 0x8fd9e7f2, 0x3dad300b, 0x8fd6e0c2,
+ 0x3da7ae84, 0x8fd3d9d8,
+ 0x3da22cd7, 0x8fd0d333, 0x3d9cab04, 0x8fcdccd3, 0x3d97290b, 0x8fcac6b9,
+ 0x3d91a6ed, 0x8fc7c0e3,
+ 0x3d8c24a8, 0x8fc4bb53, 0x3d86a23d, 0x8fc1b608, 0x3d811fac, 0x8fbeb103,
+ 0x3d7b9cf6, 0x8fbbac42,
+ 0x3d761a19, 0x8fb8a7c7, 0x3d709717, 0x8fb5a391, 0x3d6b13ee, 0x8fb29fa0,
+ 0x3d6590a0, 0x8faf9bf5,
+ 0x3d600d2c, 0x8fac988f, 0x3d5a8992, 0x8fa9956e, 0x3d5505d2, 0x8fa69293,
+ 0x3d4f81ec, 0x8fa38ffc,
+ 0x3d49fde1, 0x8fa08dab, 0x3d4479b0, 0x8f9d8ba0, 0x3d3ef559, 0x8f9a89da,
+ 0x3d3970dc, 0x8f978859,
+ 0x3d33ec39, 0x8f94871d, 0x3d2e6771, 0x8f918627, 0x3d28e282, 0x8f8e8576,
+ 0x3d235d6f, 0x8f8b850a,
+ 0x3d1dd835, 0x8f8884e4, 0x3d1852d6, 0x8f858503, 0x3d12cd51, 0x8f828568,
+ 0x3d0d47a6, 0x8f7f8612,
+ 0x3d07c1d6, 0x8f7c8701, 0x3d023be0, 0x8f798836, 0x3cfcb5c4, 0x8f7689b0,
+ 0x3cf72f83, 0x8f738b70,
+ 0x3cf1a91c, 0x8f708d75, 0x3cec2290, 0x8f6d8fbf, 0x3ce69bde, 0x8f6a924f,
+ 0x3ce11507, 0x8f679525,
+ 0x3cdb8e09, 0x8f649840, 0x3cd606e7, 0x8f619ba0, 0x3cd07f9f, 0x8f5e9f46,
+ 0x3ccaf831, 0x8f5ba331,
+ 0x3cc5709e, 0x8f58a761, 0x3cbfe8e5, 0x8f55abd8, 0x3cba6107, 0x8f52b093,
+ 0x3cb4d904, 0x8f4fb595,
+ 0x3caf50da, 0x8f4cbadb, 0x3ca9c88c, 0x8f49c067, 0x3ca44018, 0x8f46c639,
+ 0x3c9eb77f, 0x8f43cc50,
+ 0x3c992ec0, 0x8f40d2ad, 0x3c93a5dc, 0x8f3dd950, 0x3c8e1cd3, 0x8f3ae038,
+ 0x3c8893a4, 0x8f37e765,
+ 0x3c830a50, 0x8f34eed8, 0x3c7d80d6, 0x8f31f691, 0x3c77f737, 0x8f2efe8f,
+ 0x3c726d73, 0x8f2c06d3,
+ 0x3c6ce38a, 0x8f290f5c, 0x3c67597b, 0x8f26182b, 0x3c61cf48, 0x8f232140,
+ 0x3c5c44ee, 0x8f202a9a,
+ 0x3c56ba70, 0x8f1d343a, 0x3c512fcc, 0x8f1a3e1f, 0x3c4ba504, 0x8f17484b,
+ 0x3c461a16, 0x8f1452bb,
+ 0x3c408f03, 0x8f115d72, 0x3c3b03ca, 0x8f0e686e, 0x3c35786d, 0x8f0b73b0,
+ 0x3c2fecea, 0x8f087f37,
+ 0x3c2a6142, 0x8f058b04, 0x3c24d575, 0x8f029717, 0x3c1f4983, 0x8effa370,
+ 0x3c19bd6c, 0x8efcb00e,
+ 0x3c143130, 0x8ef9bcf2, 0x3c0ea4cf, 0x8ef6ca1c, 0x3c091849, 0x8ef3d78b,
+ 0x3c038b9e, 0x8ef0e540,
+ 0x3bfdfecd, 0x8eedf33b, 0x3bf871d8, 0x8eeb017c, 0x3bf2e4be, 0x8ee81002,
+ 0x3bed577e, 0x8ee51ece,
+ 0x3be7ca1a, 0x8ee22de0, 0x3be23c91, 0x8edf3d38, 0x3bdcaee3, 0x8edc4cd5,
+ 0x3bd72110, 0x8ed95cb8,
+ 0x3bd19318, 0x8ed66ce1, 0x3bcc04fb, 0x8ed37d50, 0x3bc676b9, 0x8ed08e05,
+ 0x3bc0e853, 0x8ecd9eff,
+ 0x3bbb59c7, 0x8ecab040, 0x3bb5cb17, 0x8ec7c1c6, 0x3bb03c42, 0x8ec4d392,
+ 0x3baaad48, 0x8ec1e5a4,
+ 0x3ba51e29, 0x8ebef7fb, 0x3b9f8ee5, 0x8ebc0a99, 0x3b99ff7d, 0x8eb91d7c,
+ 0x3b946ff0, 0x8eb630a6,
+ 0x3b8ee03e, 0x8eb34415, 0x3b895068, 0x8eb057ca, 0x3b83c06c, 0x8ead6bc5,
+ 0x3b7e304c, 0x8eaa8006,
+ 0x3b78a007, 0x8ea7948c, 0x3b730f9e, 0x8ea4a959, 0x3b6d7f10, 0x8ea1be6c,
+ 0x3b67ee5d, 0x8e9ed3c4,
+ 0x3b625d86, 0x8e9be963, 0x3b5ccc8a, 0x8e98ff47, 0x3b573b69, 0x8e961571,
+ 0x3b51aa24, 0x8e932be2,
+ 0x3b4c18ba, 0x8e904298, 0x3b46872c, 0x8e8d5994, 0x3b40f579, 0x8e8a70d7,
+ 0x3b3b63a1, 0x8e87885f,
+ 0x3b35d1a5, 0x8e84a02d, 0x3b303f84, 0x8e81b841, 0x3b2aad3f, 0x8e7ed09b,
+ 0x3b251ad6, 0x8e7be93c,
+ 0x3b1f8848, 0x8e790222, 0x3b19f595, 0x8e761b4e, 0x3b1462be, 0x8e7334c1,
+ 0x3b0ecfc3, 0x8e704e79,
+ 0x3b093ca3, 0x8e6d6877, 0x3b03a95e, 0x8e6a82bc, 0x3afe15f6, 0x8e679d47,
+ 0x3af88269, 0x8e64b817,
+ 0x3af2eeb7, 0x8e61d32e, 0x3aed5ae1, 0x8e5eee8b, 0x3ae7c6e7, 0x8e5c0a2e,
+ 0x3ae232c9, 0x8e592617,
+ 0x3adc9e86, 0x8e564246, 0x3ad70a1f, 0x8e535ebb, 0x3ad17593, 0x8e507b76,
+ 0x3acbe0e3, 0x8e4d9878,
+ 0x3ac64c0f, 0x8e4ab5bf, 0x3ac0b717, 0x8e47d34d, 0x3abb21fb, 0x8e44f121,
+ 0x3ab58cba, 0x8e420f3b,
+ 0x3aaff755, 0x8e3f2d9b, 0x3aaa61cc, 0x8e3c4c41, 0x3aa4cc1e, 0x8e396b2e,
+ 0x3a9f364d, 0x8e368a61,
+ 0x3a99a057, 0x8e33a9da, 0x3a940a3e, 0x8e30c999, 0x3a8e7400, 0x8e2de99e,
+ 0x3a88dd9d, 0x8e2b09e9,
+ 0x3a834717, 0x8e282a7b, 0x3a7db06d, 0x8e254b53, 0x3a78199f, 0x8e226c71,
+ 0x3a7282ac, 0x8e1f8dd6,
+ 0x3a6ceb96, 0x8e1caf80, 0x3a67545b, 0x8e19d171, 0x3a61bcfd, 0x8e16f3a9,
+ 0x3a5c257a, 0x8e141626,
+ 0x3a568dd4, 0x8e1138ea, 0x3a50f609, 0x8e0e5bf4, 0x3a4b5e1b, 0x8e0b7f44,
+ 0x3a45c608, 0x8e08a2db,
+ 0x3a402dd2, 0x8e05c6b7, 0x3a3a9577, 0x8e02eadb, 0x3a34fcf9, 0x8e000f44,
+ 0x3a2f6457, 0x8dfd33f4,
+ 0x3a29cb91, 0x8dfa58ea, 0x3a2432a7, 0x8df77e27, 0x3a1e9999, 0x8df4a3a9,
+ 0x3a190068, 0x8df1c973,
+ 0x3a136712, 0x8deeef82, 0x3a0dcd99, 0x8dec15d8, 0x3a0833fc, 0x8de93c74,
+ 0x3a029a3b, 0x8de66357,
+ 0x39fd0056, 0x8de38a80, 0x39f7664e, 0x8de0b1ef, 0x39f1cc21, 0x8dddd9a5,
+ 0x39ec31d1, 0x8ddb01a1,
+ 0x39e6975e, 0x8dd829e4, 0x39e0fcc6, 0x8dd5526d, 0x39db620b, 0x8dd27b3c,
+ 0x39d5c72c, 0x8dcfa452,
+ 0x39d02c2a, 0x8dcccdaf, 0x39ca9104, 0x8dc9f751, 0x39c4f5ba, 0x8dc7213b,
+ 0x39bf5a4d, 0x8dc44b6a,
+ 0x39b9bebc, 0x8dc175e0, 0x39b42307, 0x8dbea09d, 0x39ae872f, 0x8dbbcba0,
+ 0x39a8eb33, 0x8db8f6ea,
+ 0x39a34f13, 0x8db6227a, 0x399db2d0, 0x8db34e50, 0x3998166a, 0x8db07a6d,
+ 0x399279e0, 0x8dada6d1,
+ 0x398cdd32, 0x8daad37b, 0x39874061, 0x8da8006c, 0x3981a36d, 0x8da52da3,
+ 0x397c0655, 0x8da25b21,
+ 0x39766919, 0x8d9f88e5, 0x3970cbba, 0x8d9cb6f0, 0x396b2e38, 0x8d99e541,
+ 0x39659092, 0x8d9713d9,
+ 0x395ff2c9, 0x8d9442b8, 0x395a54dd, 0x8d9171dd, 0x3954b6cd, 0x8d8ea148,
+ 0x394f1899, 0x8d8bd0fb,
+ 0x39497a43, 0x8d8900f3, 0x3943dbc9, 0x8d863133, 0x393e3d2c, 0x8d8361b9,
+ 0x39389e6b, 0x8d809286,
+ 0x3932ff87, 0x8d7dc399, 0x392d6080, 0x8d7af4f3, 0x3927c155, 0x8d782694,
+ 0x39222208, 0x8d75587b,
+ 0x391c8297, 0x8d728aa9, 0x3916e303, 0x8d6fbd1d, 0x3911434b, 0x8d6cefd9,
+ 0x390ba371, 0x8d6a22db,
+ 0x39060373, 0x8d675623, 0x39006352, 0x8d6489b3, 0x38fac30e, 0x8d61bd89,
+ 0x38f522a6, 0x8d5ef1a5,
+ 0x38ef821c, 0x8d5c2609, 0x38e9e16e, 0x8d595ab3, 0x38e4409e, 0x8d568fa4,
+ 0x38de9faa, 0x8d53c4db,
+ 0x38d8fe93, 0x8d50fa59, 0x38d35d59, 0x8d4e301f, 0x38cdbbfc, 0x8d4b662a,
+ 0x38c81a7c, 0x8d489c7d,
+ 0x38c278d9, 0x8d45d316, 0x38bcd713, 0x8d4309f6, 0x38b7352a, 0x8d40411d,
+ 0x38b1931e, 0x8d3d788b,
+ 0x38abf0ef, 0x8d3ab03f, 0x38a64e9d, 0x8d37e83a, 0x38a0ac29, 0x8d35207d,
+ 0x389b0991, 0x8d325905,
+ 0x389566d6, 0x8d2f91d5, 0x388fc3f8, 0x8d2ccaec, 0x388a20f8, 0x8d2a0449,
+ 0x38847dd5, 0x8d273ded,
+ 0x387eda8e, 0x8d2477d8, 0x38793725, 0x8d21b20a, 0x38739399, 0x8d1eec83,
+ 0x386defeb, 0x8d1c2742,
+ 0x38684c19, 0x8d196249, 0x3862a825, 0x8d169d96, 0x385d040d, 0x8d13d92a,
+ 0x38575fd4, 0x8d111505,
+ 0x3851bb77, 0x8d0e5127, 0x384c16f7, 0x8d0b8d90, 0x38467255, 0x8d08ca40,
+ 0x3840cd90, 0x8d060737,
+ 0x383b28a9, 0x8d034474, 0x3835839f, 0x8d0081f9, 0x382fde72, 0x8cfdbfc4,
+ 0x382a3922, 0x8cfafdd7,
+ 0x382493b0, 0x8cf83c30, 0x381eee1b, 0x8cf57ad0, 0x38194864, 0x8cf2b9b8,
+ 0x3813a28a, 0x8ceff8e6,
+ 0x380dfc8d, 0x8ced385b, 0x3808566e, 0x8cea7818, 0x3802b02c, 0x8ce7b81b,
+ 0x37fd09c8, 0x8ce4f865,
+ 0x37f76341, 0x8ce238f6, 0x37f1bc97, 0x8cdf79ce, 0x37ec15cb, 0x8cdcbaee,
+ 0x37e66edd, 0x8cd9fc54,
+ 0x37e0c7cc, 0x8cd73e01, 0x37db2099, 0x8cd47ff6, 0x37d57943, 0x8cd1c231,
+ 0x37cfd1cb, 0x8ccf04b3,
+ 0x37ca2a30, 0x8ccc477d, 0x37c48273, 0x8cc98a8e, 0x37beda93, 0x8cc6cde5,
+ 0x37b93292, 0x8cc41184,
+ 0x37b38a6d, 0x8cc1556a, 0x37ade227, 0x8cbe9996, 0x37a839be, 0x8cbbde0a,
+ 0x37a29132, 0x8cb922c6,
+ 0x379ce885, 0x8cb667c8, 0x37973fb5, 0x8cb3ad11, 0x379196c3, 0x8cb0f2a1,
+ 0x378bedae, 0x8cae3879,
+ 0x37864477, 0x8cab7e98, 0x37809b1e, 0x8ca8c4fd, 0x377af1a3, 0x8ca60baa,
+ 0x37754806, 0x8ca3529f,
+ 0x376f9e46, 0x8ca099da, 0x3769f464, 0x8c9de15c, 0x37644a60, 0x8c9b2926,
+ 0x375ea03a, 0x8c987137,
+ 0x3758f5f2, 0x8c95b98f, 0x37534b87, 0x8c93022e, 0x374da0fa, 0x8c904b14,
+ 0x3747f64c, 0x8c8d9442,
+ 0x37424b7b, 0x8c8addb7, 0x373ca088, 0x8c882773, 0x3736f573, 0x8c857176,
+ 0x37314a3c, 0x8c82bbc0,
+ 0x372b9ee3, 0x8c800652, 0x3725f367, 0x8c7d512b, 0x372047ca, 0x8c7a9c4b,
+ 0x371a9c0b, 0x8c77e7b3,
+ 0x3714f02a, 0x8c753362, 0x370f4427, 0x8c727f58, 0x37099802, 0x8c6fcb95,
+ 0x3703ebbb, 0x8c6d181a,
+ 0x36fe3f52, 0x8c6a64e5, 0x36f892c7, 0x8c67b1f9, 0x36f2e61a, 0x8c64ff53,
+ 0x36ed394b, 0x8c624cf5,
+ 0x36e78c5b, 0x8c5f9ade, 0x36e1df48, 0x8c5ce90e, 0x36dc3214, 0x8c5a3786,
+ 0x36d684be, 0x8c578645,
+ 0x36d0d746, 0x8c54d54c, 0x36cb29ac, 0x8c522499, 0x36c57bf0, 0x8c4f742f,
+ 0x36bfce13, 0x8c4cc40b,
+ 0x36ba2014, 0x8c4a142f, 0x36b471f3, 0x8c47649a, 0x36aec3b0, 0x8c44b54d,
+ 0x36a9154c, 0x8c420647,
+ 0x36a366c6, 0x8c3f5788, 0x369db81e, 0x8c3ca911, 0x36980954, 0x8c39fae1,
+ 0x36925a69, 0x8c374cf9,
+ 0x368cab5c, 0x8c349f58, 0x3686fc2e, 0x8c31f1ff, 0x36814cde, 0x8c2f44ed,
+ 0x367b9d6c, 0x8c2c9822,
+ 0x3675edd9, 0x8c29eb9f, 0x36703e24, 0x8c273f63, 0x366a8e4d, 0x8c24936f,
+ 0x3664de55, 0x8c21e7c2,
+ 0x365f2e3b, 0x8c1f3c5d, 0x36597e00, 0x8c1c913f, 0x3653cda3, 0x8c19e669,
+ 0x364e1d25, 0x8c173bda,
+ 0x36486c86, 0x8c149192, 0x3642bbc4, 0x8c11e792, 0x363d0ae2, 0x8c0f3dda,
+ 0x363759de, 0x8c0c9469,
+ 0x3631a8b8, 0x8c09eb40, 0x362bf771, 0x8c07425e, 0x36264609, 0x8c0499c4,
+ 0x3620947f, 0x8c01f171,
+ 0x361ae2d3, 0x8bff4966, 0x36153107, 0x8bfca1a3, 0x360f7f19, 0x8bf9fa27,
+ 0x3609cd0a, 0x8bf752f2,
+ 0x36041ad9, 0x8bf4ac05, 0x35fe6887, 0x8bf20560, 0x35f8b614, 0x8bef5f02,
+ 0x35f3037f, 0x8becb8ec,
+ 0x35ed50c9, 0x8bea131e, 0x35e79df2, 0x8be76d97, 0x35e1eafa, 0x8be4c857,
+ 0x35dc37e0, 0x8be22360,
+ 0x35d684a6, 0x8bdf7eb0, 0x35d0d14a, 0x8bdcda47, 0x35cb1dcc, 0x8bda3626,
+ 0x35c56a2e, 0x8bd7924d,
+ 0x35bfb66e, 0x8bd4eebc, 0x35ba028e, 0x8bd24b72, 0x35b44e8c, 0x8bcfa870,
+ 0x35ae9a69, 0x8bcd05b5,
+ 0x35a8e625, 0x8bca6343, 0x35a331c0, 0x8bc7c117, 0x359d7d39, 0x8bc51f34,
+ 0x3597c892, 0x8bc27d98,
+ 0x359213c9, 0x8bbfdc44, 0x358c5ee0, 0x8bbd3b38, 0x3586a9d5, 0x8bba9a73,
+ 0x3580f4aa, 0x8bb7f9f6,
+ 0x357b3f5d, 0x8bb559c1, 0x357589f0, 0x8bb2b9d4, 0x356fd461, 0x8bb01a2e,
+ 0x356a1eb2, 0x8bad7ad0,
+ 0x356468e2, 0x8baadbba, 0x355eb2f0, 0x8ba83cec, 0x3558fcde, 0x8ba59e65,
+ 0x355346ab, 0x8ba30026,
+ 0x354d9057, 0x8ba0622f, 0x3547d9e2, 0x8b9dc480, 0x3542234c, 0x8b9b2718,
+ 0x353c6c95, 0x8b9889f8,
+ 0x3536b5be, 0x8b95ed21, 0x3530fec6, 0x8b935090, 0x352b47ad, 0x8b90b448,
+ 0x35259073, 0x8b8e1848,
+ 0x351fd918, 0x8b8b7c8f, 0x351a219c, 0x8b88e11e, 0x35146a00, 0x8b8645f5,
+ 0x350eb243, 0x8b83ab14,
+ 0x3508fa66, 0x8b81107b, 0x35034267, 0x8b7e7629, 0x34fd8a48, 0x8b7bdc20,
+ 0x34f7d208, 0x8b79425e,
+ 0x34f219a8, 0x8b76a8e4, 0x34ec6127, 0x8b740fb3, 0x34e6a885, 0x8b7176c8,
+ 0x34e0efc2, 0x8b6ede26,
+ 0x34db36df, 0x8b6c45cc, 0x34d57ddc, 0x8b69adba, 0x34cfc4b7, 0x8b6715ef,
+ 0x34ca0b73, 0x8b647e6d,
+ 0x34c4520d, 0x8b61e733, 0x34be9887, 0x8b5f5040, 0x34b8dee1, 0x8b5cb995,
+ 0x34b3251a, 0x8b5a2333,
+ 0x34ad6b32, 0x8b578d18, 0x34a7b12a, 0x8b54f745, 0x34a1f702, 0x8b5261ba,
+ 0x349c3cb9, 0x8b4fcc77,
+ 0x34968250, 0x8b4d377c, 0x3490c7c6, 0x8b4aa2ca, 0x348b0d1c, 0x8b480e5f,
+ 0x34855251, 0x8b457a3c,
+ 0x347f9766, 0x8b42e661, 0x3479dc5b, 0x8b4052ce, 0x3474212f, 0x8b3dbf83,
+ 0x346e65e3, 0x8b3b2c80,
+ 0x3468aa76, 0x8b3899c6, 0x3462eee9, 0x8b360753, 0x345d333c, 0x8b337528,
+ 0x3457776f, 0x8b30e345,
+ 0x3451bb81, 0x8b2e51ab, 0x344bff73, 0x8b2bc058, 0x34464345, 0x8b292f4e,
+ 0x344086f6, 0x8b269e8b,
+ 0x343aca87, 0x8b240e11, 0x34350df8, 0x8b217ddf, 0x342f5149, 0x8b1eedf4,
+ 0x3429947a, 0x8b1c5e52,
+ 0x3423d78a, 0x8b19cef8, 0x341e1a7b, 0x8b173fe6, 0x34185d4b, 0x8b14b11d,
+ 0x34129ffb, 0x8b12229b,
+ 0x340ce28b, 0x8b0f9462, 0x340724fb, 0x8b0d0670, 0x3401674a, 0x8b0a78c7,
+ 0x33fba97a, 0x8b07eb66,
+ 0x33f5eb89, 0x8b055e4d, 0x33f02d79, 0x8b02d17c, 0x33ea6f48, 0x8b0044f3,
+ 0x33e4b0f8, 0x8afdb8b3,
+ 0x33def287, 0x8afb2cbb, 0x33d933f7, 0x8af8a10b, 0x33d37546, 0x8af615a3,
+ 0x33cdb676, 0x8af38a83,
+ 0x33c7f785, 0x8af0ffac, 0x33c23875, 0x8aee751c, 0x33bc7944, 0x8aebead5,
+ 0x33b6b9f4, 0x8ae960d6,
+ 0x33b0fa84, 0x8ae6d720, 0x33ab3af4, 0x8ae44db1, 0x33a57b44, 0x8ae1c48b,
+ 0x339fbb74, 0x8adf3bad,
+ 0x3399fb85, 0x8adcb318, 0x33943b75, 0x8ada2aca, 0x338e7b46, 0x8ad7a2c5,
+ 0x3388baf7, 0x8ad51b08,
+ 0x3382fa88, 0x8ad29394, 0x337d39f9, 0x8ad00c67, 0x3377794b, 0x8acd8583,
+ 0x3371b87d, 0x8acafee8,
+ 0x336bf78f, 0x8ac87894, 0x33663682, 0x8ac5f289, 0x33607554, 0x8ac36cc6,
+ 0x335ab407, 0x8ac0e74c,
+ 0x3354f29b, 0x8abe6219, 0x334f310e, 0x8abbdd30, 0x33496f62, 0x8ab9588e,
+ 0x3343ad97, 0x8ab6d435,
+ 0x333debab, 0x8ab45024, 0x333829a1, 0x8ab1cc5c, 0x33326776, 0x8aaf48db,
+ 0x332ca52c, 0x8aacc5a4,
+ 0x3326e2c3, 0x8aaa42b4, 0x33212039, 0x8aa7c00d, 0x331b5d91, 0x8aa53daf,
+ 0x33159ac8, 0x8aa2bb99,
+ 0x330fd7e1, 0x8aa039cb, 0x330a14da, 0x8a9db845, 0x330451b3, 0x8a9b3708,
+ 0x32fe8e6d, 0x8a98b614,
+ 0x32f8cb07, 0x8a963567, 0x32f30782, 0x8a93b504, 0x32ed43de, 0x8a9134e8,
+ 0x32e7801a, 0x8a8eb516,
+ 0x32e1bc36, 0x8a8c358b, 0x32dbf834, 0x8a89b649, 0x32d63412, 0x8a873750,
+ 0x32d06fd0, 0x8a84b89e,
+ 0x32caab6f, 0x8a823a36, 0x32c4e6ef, 0x8a7fbc16, 0x32bf2250, 0x8a7d3e3e,
+ 0x32b95d91, 0x8a7ac0af,
+ 0x32b398b3, 0x8a784368, 0x32add3b6, 0x8a75c66a, 0x32a80e99, 0x8a7349b4,
+ 0x32a2495d, 0x8a70cd47,
+ 0x329c8402, 0x8a6e5123, 0x3296be88, 0x8a6bd547, 0x3290f8ef, 0x8a6959b3,
+ 0x328b3336, 0x8a66de68,
+ 0x32856d5e, 0x8a646365, 0x327fa767, 0x8a61e8ab, 0x3279e151, 0x8a5f6e3a,
+ 0x32741b1c, 0x8a5cf411,
+ 0x326e54c7, 0x8a5a7a31, 0x32688e54, 0x8a580099, 0x3262c7c1, 0x8a55874a,
+ 0x325d0110, 0x8a530e43,
+ 0x32573a3f, 0x8a509585, 0x3251734f, 0x8a4e1d10, 0x324bac40, 0x8a4ba4e3,
+ 0x3245e512, 0x8a492cff,
+ 0x32401dc6, 0x8a46b564, 0x323a565a, 0x8a443e11, 0x32348ecf, 0x8a41c706,
+ 0x322ec725, 0x8a3f5045,
+ 0x3228ff5c, 0x8a3cd9cc, 0x32233775, 0x8a3a639b, 0x321d6f6e, 0x8a37edb3,
+ 0x3217a748, 0x8a357814,
+ 0x3211df04, 0x8a3302be, 0x320c16a1, 0x8a308db0, 0x32064e1e, 0x8a2e18eb,
+ 0x3200857d, 0x8a2ba46e,
+ 0x31fabcbd, 0x8a29303b, 0x31f4f3df, 0x8a26bc50, 0x31ef2ae1, 0x8a2448ad,
+ 0x31e961c5, 0x8a21d554,
+ 0x31e39889, 0x8a1f6243, 0x31ddcf30, 0x8a1cef7a, 0x31d805b7, 0x8a1a7cfb,
+ 0x31d23c1f, 0x8a180ac4,
+ 0x31cc7269, 0x8a1598d6, 0x31c6a894, 0x8a132731, 0x31c0dea1, 0x8a10b5d4,
+ 0x31bb148f, 0x8a0e44c0,
+ 0x31b54a5e, 0x8a0bd3f5, 0x31af800e, 0x8a096373, 0x31a9b5a0, 0x8a06f339,
+ 0x31a3eb13, 0x8a048348,
+ 0x319e2067, 0x8a0213a0, 0x3198559d, 0x89ffa441, 0x31928ab4, 0x89fd352b,
+ 0x318cbfad, 0x89fac65d,
+ 0x3186f487, 0x89f857d8, 0x31812943, 0x89f5e99c, 0x317b5de0, 0x89f37ba9,
+ 0x3175925e, 0x89f10dff,
+ 0x316fc6be, 0x89eea09d, 0x3169fb00, 0x89ec3384, 0x31642f23, 0x89e9c6b4,
+ 0x315e6328, 0x89e75a2d,
+ 0x3158970e, 0x89e4edef, 0x3152cad5, 0x89e281fa, 0x314cfe7f, 0x89e0164d,
+ 0x31473209, 0x89ddaae9,
+ 0x31416576, 0x89db3fcf, 0x313b98c4, 0x89d8d4fd, 0x3135cbf4, 0x89d66a74,
+ 0x312fff05, 0x89d40033,
+ 0x312a31f8, 0x89d1963c, 0x312464cd, 0x89cf2c8e, 0x311e9783, 0x89ccc328,
+ 0x3118ca1b, 0x89ca5a0c,
+ 0x3112fc95, 0x89c7f138, 0x310d2ef0, 0x89c588ae, 0x3107612e, 0x89c3206c,
+ 0x3101934d, 0x89c0b873,
+ 0x30fbc54d, 0x89be50c3, 0x30f5f730, 0x89bbe95c, 0x30f028f4, 0x89b9823e,
+ 0x30ea5a9a, 0x89b71b69,
+ 0x30e48c22, 0x89b4b4dd, 0x30debd8c, 0x89b24e9a, 0x30d8eed8, 0x89afe8a0,
+ 0x30d32006, 0x89ad82ef,
+ 0x30cd5115, 0x89ab1d87, 0x30c78206, 0x89a8b868, 0x30c1b2da, 0x89a65391,
+ 0x30bbe38f, 0x89a3ef04,
+ 0x30b61426, 0x89a18ac0, 0x30b0449f, 0x899f26c5, 0x30aa74fa, 0x899cc313,
+ 0x30a4a537, 0x899a5faa,
+ 0x309ed556, 0x8997fc8a, 0x30990557, 0x899599b3, 0x3093353a, 0x89933725,
+ 0x308d64ff, 0x8990d4e0,
+ 0x308794a6, 0x898e72e4, 0x3081c42f, 0x898c1131, 0x307bf39b, 0x8989afc8,
+ 0x307622e8, 0x89874ea7,
+ 0x30705217, 0x8984edcf, 0x306a8129, 0x89828d41, 0x3064b01d, 0x89802cfc,
+ 0x305edef3, 0x897dccff,
+ 0x30590dab, 0x897b6d4c, 0x30533c45, 0x89790de2, 0x304d6ac1, 0x8976aec1,
+ 0x30479920, 0x89744fe9,
+ 0x3041c761, 0x8971f15a, 0x303bf584, 0x896f9315, 0x30362389, 0x896d3518,
+ 0x30305171, 0x896ad765,
+ 0x302a7f3a, 0x896879fb, 0x3024ace6, 0x89661cda, 0x301eda75, 0x8963c002,
+ 0x301907e6, 0x89616373,
+ 0x30133539, 0x895f072e, 0x300d626e, 0x895cab31, 0x30078f86, 0x895a4f7e,
+ 0x3001bc80, 0x8957f414,
+ 0x2ffbe95d, 0x895598f3, 0x2ff6161c, 0x89533e1c, 0x2ff042bd, 0x8950e38e,
+ 0x2fea6f41, 0x894e8948,
+ 0x2fe49ba7, 0x894c2f4c, 0x2fdec7f0, 0x8949d59a, 0x2fd8f41b, 0x89477c30,
+ 0x2fd32028, 0x89452310,
+ 0x2fcd4c19, 0x8942ca39, 0x2fc777eb, 0x894071ab, 0x2fc1a3a0, 0x893e1967,
+ 0x2fbbcf38, 0x893bc16b,
+ 0x2fb5fab2, 0x893969b9, 0x2fb0260f, 0x89371250, 0x2faa514f, 0x8934bb31,
+ 0x2fa47c71, 0x8932645b,
+ 0x2f9ea775, 0x89300dce, 0x2f98d25d, 0x892db78a, 0x2f92fd26, 0x892b6190,
+ 0x2f8d27d3, 0x89290bdf,
+ 0x2f875262, 0x8926b677, 0x2f817cd4, 0x89246159, 0x2f7ba729, 0x89220c84,
+ 0x2f75d160, 0x891fb7f8,
+ 0x2f6ffb7a, 0x891d63b5, 0x2f6a2577, 0x891b0fbc, 0x2f644f56, 0x8918bc0c,
+ 0x2f5e7919, 0x891668a6,
+ 0x2f58a2be, 0x89141589, 0x2f52cc46, 0x8911c2b5, 0x2f4cf5b0, 0x890f702b,
+ 0x2f471efe, 0x890d1dea,
+ 0x2f41482e, 0x890acbf2, 0x2f3b7141, 0x89087a44, 0x2f359a37, 0x890628df,
+ 0x2f2fc310, 0x8903d7c4,
+ 0x2f29ebcc, 0x890186f2, 0x2f24146b, 0x88ff3669, 0x2f1e3ced, 0x88fce62a,
+ 0x2f186551, 0x88fa9634,
+ 0x2f128d99, 0x88f84687, 0x2f0cb5c3, 0x88f5f724, 0x2f06ddd1, 0x88f3a80b,
+ 0x2f0105c1, 0x88f1593b,
+ 0x2efb2d95, 0x88ef0ab4, 0x2ef5554b, 0x88ecbc77, 0x2eef7ce5, 0x88ea6e83,
+ 0x2ee9a461, 0x88e820d9,
+ 0x2ee3cbc1, 0x88e5d378, 0x2eddf304, 0x88e38660, 0x2ed81a29, 0x88e13992,
+ 0x2ed24132, 0x88deed0e,
+ 0x2ecc681e, 0x88dca0d3, 0x2ec68eed, 0x88da54e1, 0x2ec0b5a0, 0x88d8093a,
+ 0x2ebadc35, 0x88d5bddb,
+ 0x2eb502ae, 0x88d372c6, 0x2eaf290a, 0x88d127fb, 0x2ea94f49, 0x88cedd79,
+ 0x2ea3756b, 0x88cc9340,
+ 0x2e9d9b70, 0x88ca4951, 0x2e97c159, 0x88c7ffac, 0x2e91e725, 0x88c5b650,
+ 0x2e8c0cd4, 0x88c36d3e,
+ 0x2e863267, 0x88c12475, 0x2e8057dd, 0x88bedbf6, 0x2e7a7d36, 0x88bc93c0,
+ 0x2e74a272, 0x88ba4bd4,
+ 0x2e6ec792, 0x88b80432, 0x2e68ec95, 0x88b5bcd9, 0x2e63117c, 0x88b375ca,
+ 0x2e5d3646, 0x88b12f04,
+ 0x2e575af3, 0x88aee888, 0x2e517f84, 0x88aca255, 0x2e4ba3f8, 0x88aa5c6c,
+ 0x2e45c850, 0x88a816cd,
+ 0x2e3fec8b, 0x88a5d177, 0x2e3a10aa, 0x88a38c6b, 0x2e3434ac, 0x88a147a9,
+ 0x2e2e5891, 0x889f0330,
+ 0x2e287c5a, 0x889cbf01, 0x2e22a007, 0x889a7b1b, 0x2e1cc397, 0x88983780,
+ 0x2e16e70b, 0x8895f42d,
+ 0x2e110a62, 0x8893b125, 0x2e0b2d9d, 0x88916e66, 0x2e0550bb, 0x888f2bf1,
+ 0x2dff73bd, 0x888ce9c5,
+ 0x2df996a3, 0x888aa7e3, 0x2df3b96c, 0x8888664b, 0x2deddc19, 0x888624fd,
+ 0x2de7feaa, 0x8883e3f8,
+ 0x2de2211e, 0x8881a33d, 0x2ddc4376, 0x887f62cb, 0x2dd665b2, 0x887d22a4,
+ 0x2dd087d1, 0x887ae2c6,
+ 0x2dcaa9d5, 0x8878a332, 0x2dc4cbbc, 0x887663e7, 0x2dbeed86, 0x887424e7,
+ 0x2db90f35, 0x8871e630,
+ 0x2db330c7, 0x886fa7c2, 0x2dad523d, 0x886d699f, 0x2da77397, 0x886b2bc5,
+ 0x2da194d5, 0x8868ee35,
+ 0x2d9bb5f6, 0x8866b0ef, 0x2d95d6fc, 0x886473f2, 0x2d8ff7e5, 0x88623740,
+ 0x2d8a18b3, 0x885ffad7,
+ 0x2d843964, 0x885dbeb8, 0x2d7e59f9, 0x885b82e3, 0x2d787a72, 0x88594757,
+ 0x2d729acf, 0x88570c16,
+ 0x2d6cbb10, 0x8854d11e, 0x2d66db35, 0x88529670, 0x2d60fb3e, 0x88505c0b,
+ 0x2d5b1b2b, 0x884e21f1,
+ 0x2d553afc, 0x884be821, 0x2d4f5ab1, 0x8849ae9a, 0x2d497a4a, 0x8847755d,
+ 0x2d4399c7, 0x88453c6a,
+ 0x2d3db928, 0x884303c1, 0x2d37d86d, 0x8840cb61, 0x2d31f797, 0x883e934c,
+ 0x2d2c16a4, 0x883c5b81,
+ 0x2d263596, 0x883a23ff, 0x2d20546b, 0x8837ecc7, 0x2d1a7325, 0x8835b5d9,
+ 0x2d1491c4, 0x88337f35,
+ 0x2d0eb046, 0x883148db, 0x2d08ceac, 0x882f12cb, 0x2d02ecf7, 0x882cdd04,
+ 0x2cfd0b26, 0x882aa788,
+ 0x2cf72939, 0x88287256, 0x2cf14731, 0x88263d6d, 0x2ceb650d, 0x882408ce,
+ 0x2ce582cd, 0x8821d47a,
+ 0x2cdfa071, 0x881fa06f, 0x2cd9bdfa, 0x881d6cae, 0x2cd3db67, 0x881b3937,
+ 0x2ccdf8b8, 0x8819060a,
+ 0x2cc815ee, 0x8816d327, 0x2cc23308, 0x8814a08f, 0x2cbc5006, 0x88126e40,
+ 0x2cb66ce9, 0x88103c3b,
+ 0x2cb089b1, 0x880e0a7f, 0x2caaa65c, 0x880bd90e, 0x2ca4c2ed, 0x8809a7e7,
+ 0x2c9edf61, 0x8807770a,
+ 0x2c98fbba, 0x88054677, 0x2c9317f8, 0x8803162e, 0x2c8d341a, 0x8800e62f,
+ 0x2c875021, 0x87feb67a,
+ 0x2c816c0c, 0x87fc870f, 0x2c7b87dc, 0x87fa57ee, 0x2c75a390, 0x87f82917,
+ 0x2c6fbf29, 0x87f5fa8b,
+ 0x2c69daa6, 0x87f3cc48, 0x2c63f609, 0x87f19e4f, 0x2c5e114f, 0x87ef70a0,
+ 0x2c582c7b, 0x87ed433c,
+ 0x2c52478a, 0x87eb1621, 0x2c4c627f, 0x87e8e950, 0x2c467d58, 0x87e6bcca,
+ 0x2c409816, 0x87e4908e,
+ 0x2c3ab2b9, 0x87e2649b, 0x2c34cd40, 0x87e038f3, 0x2c2ee7ad, 0x87de0d95,
+ 0x2c2901fd, 0x87dbe281,
+ 0x2c231c33, 0x87d9b7b7, 0x2c1d364e, 0x87d78d38, 0x2c17504d, 0x87d56302,
+ 0x2c116a31, 0x87d33916,
+ 0x2c0b83fa, 0x87d10f75, 0x2c059da7, 0x87cee61e, 0x2bffb73a, 0x87ccbd11,
+ 0x2bf9d0b1, 0x87ca944e,
+ 0x2bf3ea0d, 0x87c86bd5, 0x2bee034e, 0x87c643a6, 0x2be81c74, 0x87c41bc2,
+ 0x2be2357f, 0x87c1f427,
+ 0x2bdc4e6f, 0x87bfccd7, 0x2bd66744, 0x87bda5d1, 0x2bd07ffe, 0x87bb7f16,
+ 0x2bca989d, 0x87b958a4,
+ 0x2bc4b120, 0x87b7327d, 0x2bbec989, 0x87b50c9f, 0x2bb8e1d7, 0x87b2e70c,
+ 0x2bb2fa0a, 0x87b0c1c4,
+ 0x2bad1221, 0x87ae9cc5, 0x2ba72a1e, 0x87ac7811, 0x2ba14200, 0x87aa53a6,
+ 0x2b9b59c7, 0x87a82f87,
+ 0x2b957173, 0x87a60bb1, 0x2b8f8905, 0x87a3e825, 0x2b89a07b, 0x87a1c4e4,
+ 0x2b83b7d7, 0x879fa1ed,
+ 0x2b7dcf17, 0x879d7f41, 0x2b77e63d, 0x879b5cde, 0x2b71fd48, 0x87993ac6,
+ 0x2b6c1438, 0x879718f8,
+ 0x2b662b0e, 0x8794f774, 0x2b6041c9, 0x8792d63b, 0x2b5a5868, 0x8790b54c,
+ 0x2b546eee, 0x878e94a7,
+ 0x2b4e8558, 0x878c744d, 0x2b489ba8, 0x878a543d, 0x2b42b1dd, 0x87883477,
+ 0x2b3cc7f7, 0x878614fb,
+ 0x2b36ddf7, 0x8783f5ca, 0x2b30f3dc, 0x8781d6e3, 0x2b2b09a6, 0x877fb846,
+ 0x2b251f56, 0x877d99f4,
+ 0x2b1f34eb, 0x877b7bec, 0x2b194a66, 0x87795e2f, 0x2b135fc6, 0x877740bb,
+ 0x2b0d750b, 0x87752392,
+ 0x2b078a36, 0x877306b4, 0x2b019f46, 0x8770ea20, 0x2afbb43c, 0x876ecdd6,
+ 0x2af5c917, 0x876cb1d6,
+ 0x2aefddd8, 0x876a9621, 0x2ae9f27e, 0x87687ab7, 0x2ae4070a, 0x87665f96,
+ 0x2ade1b7c, 0x876444c1,
+ 0x2ad82fd2, 0x87622a35, 0x2ad2440f, 0x87600ff4, 0x2acc5831, 0x875df5fd,
+ 0x2ac66c39, 0x875bdc51,
+ 0x2ac08026, 0x8759c2ef, 0x2aba93f9, 0x8757a9d8, 0x2ab4a7b1, 0x8755910b,
+ 0x2aaebb50, 0x87537888,
+ 0x2aa8ced3, 0x87516050, 0x2aa2e23d, 0x874f4862, 0x2a9cf58c, 0x874d30bf,
+ 0x2a9708c1, 0x874b1966,
+ 0x2a911bdc, 0x87490258, 0x2a8b2edc, 0x8746eb94, 0x2a8541c3, 0x8744d51b,
+ 0x2a7f548e, 0x8742beec,
+ 0x2a796740, 0x8740a907, 0x2a7379d8, 0x873e936d, 0x2a6d8c55, 0x873c7e1e,
+ 0x2a679eb8, 0x873a6919,
+ 0x2a61b101, 0x8738545e, 0x2a5bc330, 0x87363fee, 0x2a55d545, 0x87342bc9,
+ 0x2a4fe740, 0x873217ee,
+ 0x2a49f920, 0x8730045d, 0x2a440ae7, 0x872df117, 0x2a3e1c93, 0x872bde1c,
+ 0x2a382e25, 0x8729cb6b,
+ 0x2a323f9e, 0x8727b905, 0x2a2c50fc, 0x8725a6e9, 0x2a266240, 0x87239518,
+ 0x2a20736a, 0x87218391,
+ 0x2a1a847b, 0x871f7255, 0x2a149571, 0x871d6163, 0x2a0ea64d, 0x871b50bc,
+ 0x2a08b710, 0x87194060,
+ 0x2a02c7b8, 0x8717304e, 0x29fcd847, 0x87152087, 0x29f6e8bb, 0x8713110a,
+ 0x29f0f916, 0x871101d8,
+ 0x29eb0957, 0x870ef2f1, 0x29e5197e, 0x870ce454, 0x29df298b, 0x870ad602,
+ 0x29d9397f, 0x8708c7fa,
+ 0x29d34958, 0x8706ba3d, 0x29cd5918, 0x8704acca, 0x29c768be, 0x87029fa3,
+ 0x29c1784a, 0x870092c5,
+ 0x29bb87bc, 0x86fe8633, 0x29b59715, 0x86fc79eb, 0x29afa654, 0x86fa6dee,
+ 0x29a9b579, 0x86f8623b,
+ 0x29a3c485, 0x86f656d3, 0x299dd377, 0x86f44bb6, 0x2997e24f, 0x86f240e3,
+ 0x2991f10e, 0x86f0365c,
+ 0x298bffb2, 0x86ee2c1e, 0x29860e3e, 0x86ec222c, 0x29801caf, 0x86ea1884,
+ 0x297a2b07, 0x86e80f27,
+ 0x29743946, 0x86e60614, 0x296e476b, 0x86e3fd4c, 0x29685576, 0x86e1f4cf,
+ 0x29626368, 0x86dfec9d,
+ 0x295c7140, 0x86dde4b5, 0x29567eff, 0x86dbdd18, 0x29508ca4, 0x86d9d5c6,
+ 0x294a9a30, 0x86d7cebf,
+ 0x2944a7a2, 0x86d5c802, 0x293eb4fb, 0x86d3c190, 0x2938c23a, 0x86d1bb69,
+ 0x2932cf60, 0x86cfb58c,
+ 0x292cdc6d, 0x86cdaffa, 0x2926e960, 0x86cbaab3, 0x2920f63a, 0x86c9a5b7,
+ 0x291b02fa, 0x86c7a106,
+ 0x29150fa1, 0x86c59c9f, 0x290f1c2f, 0x86c39883, 0x290928a3, 0x86c194b2,
+ 0x290334ff, 0x86bf912c,
+ 0x28fd4140, 0x86bd8df0, 0x28f74d69, 0x86bb8b00, 0x28f15978, 0x86b9885a,
+ 0x28eb656e, 0x86b785ff,
+ 0x28e5714b, 0x86b583ee, 0x28df7d0e, 0x86b38229, 0x28d988b8, 0x86b180ae,
+ 0x28d3944a, 0x86af7f7e,
+ 0x28cd9fc1, 0x86ad7e99, 0x28c7ab20, 0x86ab7dff, 0x28c1b666, 0x86a97db0,
+ 0x28bbc192, 0x86a77dab,
+ 0x28b5cca5, 0x86a57df2, 0x28afd7a0, 0x86a37e83, 0x28a9e281, 0x86a17f5f,
+ 0x28a3ed49, 0x869f8086,
+ 0x289df7f8, 0x869d81f8, 0x2898028e, 0x869b83b4, 0x28920d0a, 0x869985bc,
+ 0x288c176e, 0x8697880f,
+ 0x288621b9, 0x86958aac, 0x28802beb, 0x86938d94, 0x287a3604, 0x869190c7,
+ 0x28744004, 0x868f9445,
+ 0x286e49ea, 0x868d980e, 0x286853b8, 0x868b9c22, 0x28625d6d, 0x8689a081,
+ 0x285c670a, 0x8687a52b,
+ 0x2856708d, 0x8685aa20, 0x285079f7, 0x8683af5f, 0x284a8349, 0x8681b4ea,
+ 0x28448c81, 0x867fbabf,
+ 0x283e95a1, 0x867dc0e0, 0x28389ea8, 0x867bc74b, 0x2832a796, 0x8679ce01,
+ 0x282cb06c, 0x8677d503,
+ 0x2826b928, 0x8675dc4f, 0x2820c1cc, 0x8673e3e6, 0x281aca57, 0x8671ebc8,
+ 0x2814d2c9, 0x866ff3f6,
+ 0x280edb23, 0x866dfc6e, 0x2808e364, 0x866c0531, 0x2802eb8c, 0x866a0e3f,
+ 0x27fcf39c, 0x86681798,
+ 0x27f6fb92, 0x8666213c, 0x27f10371, 0x86642b2c, 0x27eb0b36, 0x86623566,
+ 0x27e512e3, 0x86603feb,
+ 0x27df1a77, 0x865e4abb, 0x27d921f3, 0x865c55d7, 0x27d32956, 0x865a613d,
+ 0x27cd30a1, 0x86586cee,
+ 0x27c737d3, 0x865678eb, 0x27c13eec, 0x86548532, 0x27bb45ed, 0x865291c4,
+ 0x27b54cd6, 0x86509ea2,
+ 0x27af53a6, 0x864eabcb, 0x27a95a5d, 0x864cb93e, 0x27a360fc, 0x864ac6fd,
+ 0x279d6783, 0x8648d507,
+ 0x27976df1, 0x8646e35c, 0x27917447, 0x8644f1fc, 0x278b7a84, 0x864300e7,
+ 0x278580a9, 0x8641101d,
+ 0x277f86b5, 0x863f1f9e, 0x27798caa, 0x863d2f6b, 0x27739285, 0x863b3f82,
+ 0x276d9849, 0x86394fe5,
+ 0x27679df4, 0x86376092, 0x2761a387, 0x8635718b, 0x275ba901, 0x863382cf,
+ 0x2755ae64, 0x8631945e,
+ 0x274fb3ae, 0x862fa638, 0x2749b8e0, 0x862db85e, 0x2743bdf9, 0x862bcace,
+ 0x273dc2fa, 0x8629dd8a,
+ 0x2737c7e3, 0x8627f091, 0x2731ccb4, 0x862603e3, 0x272bd16d, 0x86241780,
+ 0x2725d60e, 0x86222b68,
+ 0x271fda96, 0x86203f9c, 0x2719df06, 0x861e541a, 0x2713e35f, 0x861c68e4,
+ 0x270de79f, 0x861a7df9,
+ 0x2707ebc7, 0x86189359, 0x2701efd7, 0x8616a905, 0x26fbf3ce, 0x8614befb,
+ 0x26f5f7ae, 0x8612d53d,
+ 0x26effb76, 0x8610ebca, 0x26e9ff26, 0x860f02a3, 0x26e402bd, 0x860d19c6,
+ 0x26de063d, 0x860b3135,
+ 0x26d809a5, 0x860948ef, 0x26d20cf5, 0x860760f4, 0x26cc102d, 0x86057944,
+ 0x26c6134d, 0x860391e0,
+ 0x26c01655, 0x8601aac7, 0x26ba1945, 0x85ffc3f9, 0x26b41c1d, 0x85fddd76,
+ 0x26ae1edd, 0x85fbf73f,
+ 0x26a82186, 0x85fa1153, 0x26a22416, 0x85f82bb2, 0x269c268f, 0x85f6465c,
+ 0x269628f0, 0x85f46152,
+ 0x26902b39, 0x85f27c93, 0x268a2d6b, 0x85f09820, 0x26842f84, 0x85eeb3f7,
+ 0x267e3186, 0x85ecd01a,
+ 0x26783370, 0x85eaec88, 0x26723543, 0x85e90942, 0x266c36fe, 0x85e72647,
+ 0x266638a1, 0x85e54397,
+ 0x26603a2c, 0x85e36132, 0x265a3b9f, 0x85e17f19, 0x26543cfb, 0x85df9d4b,
+ 0x264e3e40, 0x85ddbbc9,
+ 0x26483f6c, 0x85dbda91, 0x26424082, 0x85d9f9a5, 0x263c417f, 0x85d81905,
+ 0x26364265, 0x85d638b0,
+ 0x26304333, 0x85d458a6, 0x262a43ea, 0x85d278e7, 0x26244489, 0x85d09974,
+ 0x261e4511, 0x85ceba4d,
+ 0x26184581, 0x85ccdb70, 0x261245da, 0x85cafcdf, 0x260c461b, 0x85c91e9a,
+ 0x26064645, 0x85c740a0,
+ 0x26004657, 0x85c562f1, 0x25fa4652, 0x85c3858d, 0x25f44635, 0x85c1a875,
+ 0x25ee4601, 0x85bfcba9,
+ 0x25e845b6, 0x85bdef28, 0x25e24553, 0x85bc12f2, 0x25dc44d9, 0x85ba3707,
+ 0x25d64447, 0x85b85b68,
+ 0x25d0439f, 0x85b68015, 0x25ca42de, 0x85b4a50d, 0x25c44207, 0x85b2ca50,
+ 0x25be4118, 0x85b0efdf,
+ 0x25b84012, 0x85af15b9, 0x25b23ef5, 0x85ad3bdf, 0x25ac3dc0, 0x85ab6250,
+ 0x25a63c74, 0x85a9890d,
+ 0x25a03b11, 0x85a7b015, 0x259a3997, 0x85a5d768, 0x25943806, 0x85a3ff07,
+ 0x258e365d, 0x85a226f2,
+ 0x2588349d, 0x85a04f28, 0x258232c6, 0x859e77a9, 0x257c30d8, 0x859ca076,
+ 0x25762ed3, 0x859ac98f,
+ 0x25702cb7, 0x8598f2f3, 0x256a2a83, 0x85971ca2, 0x25642839, 0x8595469d,
+ 0x255e25d7, 0x859370e4,
+ 0x2558235f, 0x85919b76, 0x255220cf, 0x858fc653, 0x254c1e28, 0x858df17c,
+ 0x25461b6b, 0x858c1cf1,
+ 0x25401896, 0x858a48b1, 0x253a15aa, 0x858874bd, 0x253412a8, 0x8586a114,
+ 0x252e0f8e, 0x8584cdb7,
+ 0x25280c5e, 0x8582faa5, 0x25220916, 0x858127df, 0x251c05b8, 0x857f5564,
+ 0x25160243, 0x857d8335,
+ 0x250ffeb7, 0x857bb152, 0x2509fb14, 0x8579dfba, 0x2503f75a, 0x85780e6e,
+ 0x24fdf389, 0x85763d6d,
+ 0x24f7efa2, 0x85746cb8, 0x24f1eba4, 0x85729c4e, 0x24ebe78f, 0x8570cc30,
+ 0x24e5e363, 0x856efc5e,
+ 0x24dfdf20, 0x856d2cd7, 0x24d9dac7, 0x856b5d9c, 0x24d3d657, 0x85698ead,
+ 0x24cdd1d0, 0x8567c009,
+ 0x24c7cd33, 0x8565f1b0, 0x24c1c87f, 0x856423a4, 0x24bbc3b4, 0x856255e3,
+ 0x24b5bed2, 0x8560886d,
+ 0x24afb9da, 0x855ebb44, 0x24a9b4cb, 0x855cee66, 0x24a3afa6, 0x855b21d3,
+ 0x249daa6a, 0x8559558c,
+ 0x2497a517, 0x85578991, 0x24919fae, 0x8555bde2, 0x248b9a2f, 0x8553f27e,
+ 0x24859498, 0x85522766,
+ 0x247f8eec, 0x85505c99, 0x24798928, 0x854e9219, 0x2473834f, 0x854cc7e3,
+ 0x246d7d5e, 0x854afdfa,
+ 0x24677758, 0x8549345c, 0x2461713a, 0x85476b0a, 0x245b6b07, 0x8545a204,
+ 0x245564bd, 0x8543d949,
+ 0x244f5e5c, 0x854210db, 0x244957e5, 0x854048b7, 0x24435158, 0x853e80e0,
+ 0x243d4ab4, 0x853cb954,
+ 0x243743fa, 0x853af214, 0x24313d2a, 0x85392b20, 0x242b3644, 0x85376477,
+ 0x24252f47, 0x85359e1a,
+ 0x241f2833, 0x8533d809, 0x2419210a, 0x85321244, 0x241319ca, 0x85304cca,
+ 0x240d1274, 0x852e879d,
+ 0x24070b08, 0x852cc2bb, 0x24010385, 0x852afe24, 0x23fafbec, 0x852939da,
+ 0x23f4f43e, 0x852775db,
+ 0x23eeec78, 0x8525b228, 0x23e8e49d, 0x8523eec1, 0x23e2dcac, 0x85222ba5,
+ 0x23dcd4a4, 0x852068d6,
+ 0x23d6cc87, 0x851ea652, 0x23d0c453, 0x851ce41a, 0x23cabc09, 0x851b222e,
+ 0x23c4b3a9, 0x8519608d,
+ 0x23beab33, 0x85179f39, 0x23b8a2a7, 0x8515de30, 0x23b29a05, 0x85141d73,
+ 0x23ac914d, 0x85125d02,
+ 0x23a6887f, 0x85109cdd, 0x23a07f9a, 0x850edd03, 0x239a76a0, 0x850d1d75,
+ 0x23946d90, 0x850b5e34,
+ 0x238e646a, 0x85099f3e, 0x23885b2e, 0x8507e094, 0x238251dd, 0x85062235,
+ 0x237c4875, 0x85046423,
+ 0x23763ef7, 0x8502a65c, 0x23703564, 0x8500e8e2, 0x236a2bba, 0x84ff2bb3,
+ 0x236421fb, 0x84fd6ed0,
+ 0x235e1826, 0x84fbb239, 0x23580e3b, 0x84f9f5ee, 0x2352043b, 0x84f839ee,
+ 0x234bfa24, 0x84f67e3b,
+ 0x2345eff8, 0x84f4c2d4, 0x233fe5b6, 0x84f307b8, 0x2339db5e, 0x84f14ce8,
+ 0x2333d0f1, 0x84ef9265,
+ 0x232dc66d, 0x84edd82d, 0x2327bbd5, 0x84ec1e41, 0x2321b126, 0x84ea64a1,
+ 0x231ba662, 0x84e8ab4d,
+ 0x23159b88, 0x84e6f244, 0x230f9098, 0x84e53988, 0x23098593, 0x84e38118,
+ 0x23037a78, 0x84e1c8f3,
+ 0x22fd6f48, 0x84e0111b, 0x22f76402, 0x84de598f, 0x22f158a7, 0x84dca24e,
+ 0x22eb4d36, 0x84daeb5a,
+ 0x22e541af, 0x84d934b1, 0x22df3613, 0x84d77e54, 0x22d92a61, 0x84d5c844,
+ 0x22d31e9a, 0x84d4127f,
+ 0x22cd12bd, 0x84d25d06, 0x22c706cb, 0x84d0a7da, 0x22c0fac4, 0x84cef2f9,
+ 0x22baeea7, 0x84cd3e64,
+ 0x22b4e274, 0x84cb8a1b, 0x22aed62c, 0x84c9d61f, 0x22a8c9cf, 0x84c8226e,
+ 0x22a2bd5d, 0x84c66f09,
+ 0x229cb0d5, 0x84c4bbf0, 0x2296a437, 0x84c30924, 0x22909785, 0x84c156a3,
+ 0x228a8abd, 0x84bfa46e,
+ 0x22847de0, 0x84bdf286, 0x227e70ed, 0x84bc40e9, 0x227863e5, 0x84ba8f98,
+ 0x227256c8, 0x84b8de94,
+ 0x226c4996, 0x84b72ddb, 0x22663c4e, 0x84b57d6f, 0x22602ef1, 0x84b3cd4f,
+ 0x225a217f, 0x84b21d7a,
+ 0x225413f8, 0x84b06df2, 0x224e065c, 0x84aebeb6, 0x2247f8aa, 0x84ad0fc6,
+ 0x2241eae3, 0x84ab6122,
+ 0x223bdd08, 0x84a9b2ca, 0x2235cf17, 0x84a804be, 0x222fc111, 0x84a656fe,
+ 0x2229b2f6, 0x84a4a98a,
+ 0x2223a4c5, 0x84a2fc62, 0x221d9680, 0x84a14f87, 0x22178826, 0x849fa2f7,
+ 0x221179b7, 0x849df6b4,
+ 0x220b6b32, 0x849c4abd, 0x22055c99, 0x849a9f12, 0x21ff4dea, 0x8498f3b3,
+ 0x21f93f27, 0x849748a0,
+ 0x21f3304f, 0x84959dd9, 0x21ed2162, 0x8493f35e, 0x21e71260, 0x84924930,
+ 0x21e10349, 0x84909f4e,
+ 0x21daf41d, 0x848ef5b7, 0x21d4e4dc, 0x848d4c6d, 0x21ced586, 0x848ba36f,
+ 0x21c8c61c, 0x8489fabe,
+ 0x21c2b69c, 0x84885258, 0x21bca708, 0x8486aa3e, 0x21b6975f, 0x84850271,
+ 0x21b087a1, 0x84835af0,
+ 0x21aa77cf, 0x8481b3bb, 0x21a467e7, 0x84800cd2, 0x219e57eb, 0x847e6636,
+ 0x219847da, 0x847cbfe5,
+ 0x219237b5, 0x847b19e1, 0x218c277a, 0x84797429, 0x2186172b, 0x8477cebd,
+ 0x218006c8, 0x8476299e,
+ 0x2179f64f, 0x847484ca, 0x2173e5c2, 0x8472e043, 0x216dd521, 0x84713c08,
+ 0x2167c46b, 0x846f9819,
+ 0x2161b3a0, 0x846df477, 0x215ba2c0, 0x846c5120, 0x215591cc, 0x846aae16,
+ 0x214f80c4, 0x84690b58,
+ 0x21496fa7, 0x846768e7, 0x21435e75, 0x8465c6c1, 0x213d4d2f, 0x846424e8,
+ 0x21373bd4, 0x8462835b,
+ 0x21312a65, 0x8460e21a, 0x212b18e1, 0x845f4126, 0x21250749, 0x845da07e,
+ 0x211ef59d, 0x845c0022,
+ 0x2118e3dc, 0x845a6012, 0x2112d206, 0x8458c04f, 0x210cc01d, 0x845720d8,
+ 0x2106ae1e, 0x845581ad,
+ 0x21009c0c, 0x8453e2cf, 0x20fa89e5, 0x8452443d, 0x20f477aa, 0x8450a5f7,
+ 0x20ee655a, 0x844f07fd,
+ 0x20e852f6, 0x844d6a50, 0x20e2407e, 0x844bccef, 0x20dc2df2, 0x844a2fda,
+ 0x20d61b51, 0x84489311,
+ 0x20d0089c, 0x8446f695, 0x20c9f5d3, 0x84455a66, 0x20c3e2f5, 0x8443be82,
+ 0x20bdd003, 0x844222eb,
+ 0x20b7bcfe, 0x844087a0, 0x20b1a9e4, 0x843eeca2, 0x20ab96b5, 0x843d51f0,
+ 0x20a58373, 0x843bb78a,
+ 0x209f701c, 0x843a1d70, 0x20995cb2, 0x843883a3, 0x20934933, 0x8436ea23,
+ 0x208d35a0, 0x843550ee,
+ 0x208721f9, 0x8433b806, 0x20810e3e, 0x84321f6b, 0x207afa6f, 0x8430871b,
+ 0x2074e68c, 0x842eef18,
+ 0x206ed295, 0x842d5762, 0x2068be8a, 0x842bbff8, 0x2062aa6b, 0x842a28da,
+ 0x205c9638, 0x84289209,
+ 0x205681f1, 0x8426fb84, 0x20506d96, 0x8425654b, 0x204a5927, 0x8423cf5f,
+ 0x204444a4, 0x842239bf,
+ 0x203e300d, 0x8420a46c, 0x20381b63, 0x841f0f65, 0x203206a4, 0x841d7aaa,
+ 0x202bf1d2, 0x841be63c,
+ 0x2025dcec, 0x841a521a, 0x201fc7f2, 0x8418be45, 0x2019b2e4, 0x84172abc,
+ 0x20139dc2, 0x84159780,
+ 0x200d888d, 0x84140490, 0x20077344, 0x841271ec, 0x20015de7, 0x8410df95,
+ 0x1ffb4876, 0x840f4d8a,
+ 0x1ff532f2, 0x840dbbcc, 0x1fef1d59, 0x840c2a5a, 0x1fe907ae, 0x840a9935,
+ 0x1fe2f1ee, 0x8409085c,
+ 0x1fdcdc1b, 0x840777d0, 0x1fd6c634, 0x8405e790, 0x1fd0b03a, 0x8404579d,
+ 0x1fca9a2b, 0x8402c7f6,
+ 0x1fc4840a, 0x8401389b, 0x1fbe6dd4, 0x83ffa98d, 0x1fb8578b, 0x83fe1acc,
+ 0x1fb2412f, 0x83fc8c57,
+ 0x1fac2abf, 0x83fafe2e, 0x1fa6143b, 0x83f97052, 0x1f9ffda4, 0x83f7e2c3,
+ 0x1f99e6fa, 0x83f65580,
+ 0x1f93d03c, 0x83f4c889, 0x1f8db96a, 0x83f33bdf, 0x1f87a285, 0x83f1af82,
+ 0x1f818b8d, 0x83f02371,
+ 0x1f7b7481, 0x83ee97ad, 0x1f755d61, 0x83ed0c35, 0x1f6f462f, 0x83eb810a,
+ 0x1f692ee9, 0x83e9f62b,
+ 0x1f63178f, 0x83e86b99, 0x1f5d0022, 0x83e6e153, 0x1f56e8a2, 0x83e5575a,
+ 0x1f50d10e, 0x83e3cdad,
+ 0x1f4ab968, 0x83e2444d, 0x1f44a1ad, 0x83e0bb3a, 0x1f3e89e0, 0x83df3273,
+ 0x1f3871ff, 0x83dda9f9,
+ 0x1f325a0b, 0x83dc21cb, 0x1f2c4204, 0x83da99ea, 0x1f2629ea, 0x83d91255,
+ 0x1f2011bc, 0x83d78b0d,
+ 0x1f19f97b, 0x83d60412, 0x1f13e127, 0x83d47d63, 0x1f0dc8c0, 0x83d2f701,
+ 0x1f07b045, 0x83d170eb,
+ 0x1f0197b8, 0x83cfeb22, 0x1efb7f17, 0x83ce65a6, 0x1ef56664, 0x83cce076,
+ 0x1eef4d9d, 0x83cb5b93,
+ 0x1ee934c3, 0x83c9d6fc, 0x1ee31bd6, 0x83c852b2, 0x1edd02d6, 0x83c6ceb5,
+ 0x1ed6e9c3, 0x83c54b04,
+ 0x1ed0d09d, 0x83c3c7a0, 0x1ecab763, 0x83c24488, 0x1ec49e17, 0x83c0c1be,
+ 0x1ebe84b8, 0x83bf3f3f,
+ 0x1eb86b46, 0x83bdbd0e, 0x1eb251c1, 0x83bc3b29, 0x1eac3829, 0x83bab991,
+ 0x1ea61e7e, 0x83b93845,
+ 0x1ea004c1, 0x83b7b746, 0x1e99eaf0, 0x83b63694, 0x1e93d10c, 0x83b4b62e,
+ 0x1e8db716, 0x83b33616,
+ 0x1e879d0d, 0x83b1b649, 0x1e8182f1, 0x83b036ca, 0x1e7b68c2, 0x83aeb797,
+ 0x1e754e80, 0x83ad38b1,
+ 0x1e6f342c, 0x83abba17, 0x1e6919c4, 0x83aa3bca, 0x1e62ff4a, 0x83a8bdca,
+ 0x1e5ce4be, 0x83a74017,
+ 0x1e56ca1e, 0x83a5c2b0, 0x1e50af6c, 0x83a44596, 0x1e4a94a7, 0x83a2c8c9,
+ 0x1e4479cf, 0x83a14c48,
+ 0x1e3e5ee5, 0x839fd014, 0x1e3843e8, 0x839e542d, 0x1e3228d9, 0x839cd893,
+ 0x1e2c0db6, 0x839b5d45,
+ 0x1e25f282, 0x8399e244, 0x1e1fd73a, 0x83986790, 0x1e19bbe0, 0x8396ed29,
+ 0x1e13a074, 0x8395730e,
+ 0x1e0d84f5, 0x8393f940, 0x1e076963, 0x83927fbf, 0x1e014dbf, 0x8391068a,
+ 0x1dfb3208, 0x838f8da2,
+ 0x1df5163f, 0x838e1507, 0x1deefa63, 0x838c9cb9, 0x1de8de75, 0x838b24b8,
+ 0x1de2c275, 0x8389ad03,
+ 0x1ddca662, 0x8388359b, 0x1dd68a3c, 0x8386be80, 0x1dd06e04, 0x838547b2,
+ 0x1dca51ba, 0x8383d130,
+ 0x1dc4355e, 0x83825afb, 0x1dbe18ef, 0x8380e513, 0x1db7fc6d, 0x837f6f78,
+ 0x1db1dfda, 0x837dfa2a,
+ 0x1dabc334, 0x837c8528, 0x1da5a67c, 0x837b1074, 0x1d9f89b1, 0x83799c0c,
+ 0x1d996cd4, 0x837827f0,
+ 0x1d934fe5, 0x8376b422, 0x1d8d32e4, 0x837540a1, 0x1d8715d0, 0x8373cd6c,
+ 0x1d80f8ab, 0x83725a84,
+ 0x1d7adb73, 0x8370e7e9, 0x1d74be29, 0x836f759b, 0x1d6ea0cc, 0x836e039a,
+ 0x1d68835e, 0x836c91e5,
+ 0x1d6265dd, 0x836b207d, 0x1d5c484b, 0x8369af63, 0x1d562aa6, 0x83683e95,
+ 0x1d500cef, 0x8366ce14,
+ 0x1d49ef26, 0x83655ddf, 0x1d43d14b, 0x8363edf8, 0x1d3db35e, 0x83627e5d,
+ 0x1d37955e, 0x83610f10,
+ 0x1d31774d, 0x835fa00f, 0x1d2b592a, 0x835e315b, 0x1d253af5, 0x835cc2f4,
+ 0x1d1f1cae, 0x835b54da,
+ 0x1d18fe54, 0x8359e70d, 0x1d12dfe9, 0x8358798c, 0x1d0cc16c, 0x83570c59,
+ 0x1d06a2dd, 0x83559f72,
+ 0x1d00843d, 0x835432d8, 0x1cfa658a, 0x8352c68c, 0x1cf446c5, 0x83515a8c,
+ 0x1cee27ef, 0x834feed9,
+ 0x1ce80906, 0x834e8373, 0x1ce1ea0c, 0x834d185a, 0x1cdbcb00, 0x834bad8e,
+ 0x1cd5abe3, 0x834a430e,
+ 0x1ccf8cb3, 0x8348d8dc, 0x1cc96d72, 0x83476ef6, 0x1cc34e1f, 0x8346055e,
+ 0x1cbd2eba, 0x83449c12,
+ 0x1cb70f43, 0x83433314, 0x1cb0efbb, 0x8341ca62, 0x1caad021, 0x834061fd,
+ 0x1ca4b075, 0x833ef9e6,
+ 0x1c9e90b8, 0x833d921b, 0x1c9870e9, 0x833c2a9d, 0x1c925109, 0x833ac36c,
+ 0x1c8c3116, 0x83395c88,
+ 0x1c861113, 0x8337f5f1, 0x1c7ff0fd, 0x83368fa7, 0x1c79d0d6, 0x833529aa,
+ 0x1c73b09d, 0x8333c3fa,
+ 0x1c6d9053, 0x83325e97, 0x1c676ff8, 0x8330f981, 0x1c614f8b, 0x832f94b8,
+ 0x1c5b2f0c, 0x832e303c,
+ 0x1c550e7c, 0x832ccc0d, 0x1c4eedda, 0x832b682b, 0x1c48cd27, 0x832a0496,
+ 0x1c42ac62, 0x8328a14d,
+ 0x1c3c8b8c, 0x83273e52, 0x1c366aa5, 0x8325dba4, 0x1c3049ac, 0x83247943,
+ 0x1c2a28a2, 0x8323172f,
+ 0x1c240786, 0x8321b568, 0x1c1de659, 0x832053ee, 0x1c17c51b, 0x831ef2c1,
+ 0x1c11a3cb, 0x831d91e1,
+ 0x1c0b826a, 0x831c314e, 0x1c0560f8, 0x831ad109, 0x1bff3f75, 0x83197110,
+ 0x1bf91de0, 0x83181164,
+ 0x1bf2fc3a, 0x8316b205, 0x1becda83, 0x831552f4, 0x1be6b8ba, 0x8313f42f,
+ 0x1be096e0, 0x831295b7,
+ 0x1bda74f6, 0x8311378d, 0x1bd452f9, 0x830fd9af, 0x1bce30ec, 0x830e7c1f,
+ 0x1bc80ece, 0x830d1edc,
+ 0x1bc1ec9e, 0x830bc1e6, 0x1bbbca5e, 0x830a653c, 0x1bb5a80c, 0x830908e0,
+ 0x1baf85a9, 0x8307acd1,
+ 0x1ba96335, 0x83065110, 0x1ba340b0, 0x8304f59b, 0x1b9d1e1a, 0x83039a73,
+ 0x1b96fb73, 0x83023f98,
+ 0x1b90d8bb, 0x8300e50b, 0x1b8ab5f2, 0x82ff8acb, 0x1b849317, 0x82fe30d7,
+ 0x1b7e702c, 0x82fcd731,
+ 0x1b784d30, 0x82fb7dd8, 0x1b722a23, 0x82fa24cc, 0x1b6c0705, 0x82f8cc0d,
+ 0x1b65e3d7, 0x82f7739c,
+ 0x1b5fc097, 0x82f61b77, 0x1b599d46, 0x82f4c3a0, 0x1b5379e5, 0x82f36c15,
+ 0x1b4d5672, 0x82f214d8,
+ 0x1b4732ef, 0x82f0bde8, 0x1b410f5b, 0x82ef6745, 0x1b3aebb6, 0x82ee10ef,
+ 0x1b34c801, 0x82ecbae7,
+ 0x1b2ea43a, 0x82eb652b, 0x1b288063, 0x82ea0fbd, 0x1b225c7b, 0x82e8ba9c,
+ 0x1b1c3883, 0x82e765c8,
+ 0x1b161479, 0x82e61141, 0x1b0ff05f, 0x82e4bd07, 0x1b09cc34, 0x82e3691b,
+ 0x1b03a7f9, 0x82e2157c,
+ 0x1afd83ad, 0x82e0c22a, 0x1af75f50, 0x82df6f25, 0x1af13ae3, 0x82de1c6d,
+ 0x1aeb1665, 0x82dcca02,
+ 0x1ae4f1d6, 0x82db77e5, 0x1adecd37, 0x82da2615, 0x1ad8a887, 0x82d8d492,
+ 0x1ad283c7, 0x82d7835c,
+ 0x1acc5ef6, 0x82d63274, 0x1ac63a14, 0x82d4e1d8, 0x1ac01522, 0x82d3918a,
+ 0x1ab9f020, 0x82d24189,
+ 0x1ab3cb0d, 0x82d0f1d5, 0x1aada5e9, 0x82cfa26f, 0x1aa780b6, 0x82ce5356,
+ 0x1aa15b71, 0x82cd048a,
+ 0x1a9b361d, 0x82cbb60b, 0x1a9510b7, 0x82ca67d9, 0x1a8eeb42, 0x82c919f5,
+ 0x1a88c5bc, 0x82c7cc5e,
+ 0x1a82a026, 0x82c67f14, 0x1a7c7a7f, 0x82c53217, 0x1a7654c8, 0x82c3e568,
+ 0x1a702f01, 0x82c29906,
+ 0x1a6a0929, 0x82c14cf1, 0x1a63e341, 0x82c00129, 0x1a5dbd49, 0x82beb5af,
+ 0x1a579741, 0x82bd6a82,
+ 0x1a517128, 0x82bc1fa2, 0x1a4b4aff, 0x82bad50f, 0x1a4524c6, 0x82b98aca,
+ 0x1a3efe7c, 0x82b840d2,
+ 0x1a38d823, 0x82b6f727, 0x1a32b1b9, 0x82b5adca, 0x1a2c8b3f, 0x82b464ba,
+ 0x1a2664b5, 0x82b31bf7,
+ 0x1a203e1b, 0x82b1d381, 0x1a1a1771, 0x82b08b59, 0x1a13f0b6, 0x82af437e,
+ 0x1a0dc9ec, 0x82adfbf0,
+ 0x1a07a311, 0x82acb4b0, 0x1a017c27, 0x82ab6dbd, 0x19fb552c, 0x82aa2717,
+ 0x19f52e22, 0x82a8e0bf,
+ 0x19ef0707, 0x82a79ab3, 0x19e8dfdc, 0x82a654f6, 0x19e2b8a2, 0x82a50f85,
+ 0x19dc9157, 0x82a3ca62,
+ 0x19d669fc, 0x82a2858c, 0x19d04292, 0x82a14104, 0x19ca1b17, 0x829ffcc8,
+ 0x19c3f38d, 0x829eb8db,
+ 0x19bdcbf3, 0x829d753a, 0x19b7a449, 0x829c31e7, 0x19b17c8f, 0x829aeee1,
+ 0x19ab54c5, 0x8299ac29,
+ 0x19a52ceb, 0x829869be, 0x199f0502, 0x829727a0, 0x1998dd09, 0x8295e5cf,
+ 0x1992b4ff, 0x8294a44c,
+ 0x198c8ce7, 0x82936317, 0x198664be, 0x8292222e, 0x19803c86, 0x8290e194,
+ 0x197a143e, 0x828fa146,
+ 0x1973ebe6, 0x828e6146, 0x196dc37e, 0x828d2193, 0x19679b07, 0x828be22e,
+ 0x19617280, 0x828aa316,
+ 0x195b49ea, 0x8289644b, 0x19552144, 0x828825ce, 0x194ef88e, 0x8286e79e,
+ 0x1948cfc8, 0x8285a9bb,
+ 0x1942a6f3, 0x82846c26, 0x193c7e0f, 0x82832edf, 0x1936551b, 0x8281f1e4,
+ 0x19302c17, 0x8280b538,
+ 0x192a0304, 0x827f78d8, 0x1923d9e1, 0x827e3cc6, 0x191db0af, 0x827d0102,
+ 0x1917876d, 0x827bc58a,
+ 0x19115e1c, 0x827a8a61, 0x190b34bb, 0x82794f84, 0x19050b4b, 0x827814f6,
+ 0x18fee1cb, 0x8276dab4,
+ 0x18f8b83c, 0x8275a0c0, 0x18f28e9e, 0x8274671a, 0x18ec64f0, 0x82732dc0,
+ 0x18e63b33, 0x8271f4b5,
+ 0x18e01167, 0x8270bbf7, 0x18d9e78b, 0x826f8386, 0x18d3bda0, 0x826e4b62,
+ 0x18cd93a5, 0x826d138d,
+ 0x18c7699b, 0x826bdc04, 0x18c13f82, 0x826aa4c9, 0x18bb155a, 0x82696ddc,
+ 0x18b4eb22, 0x8268373c,
+ 0x18aec0db, 0x826700e9, 0x18a89685, 0x8265cae4, 0x18a26c20, 0x8264952d,
+ 0x189c41ab, 0x82635fc2,
+ 0x18961728, 0x82622aa6, 0x188fec95, 0x8260f5d7, 0x1889c1f3, 0x825fc155,
+ 0x18839742, 0x825e8d21,
+ 0x187d6c82, 0x825d593a, 0x187741b2, 0x825c25a1, 0x187116d4, 0x825af255,
+ 0x186aebe6, 0x8259bf57,
+ 0x1864c0ea, 0x82588ca7, 0x185e95de, 0x82575a44, 0x18586ac3, 0x8256282e,
+ 0x18523f9a, 0x8254f666,
+ 0x184c1461, 0x8253c4eb, 0x1845e919, 0x825293be, 0x183fbdc3, 0x825162df,
+ 0x1839925d, 0x8250324d,
+ 0x183366e9, 0x824f0208, 0x182d3b65, 0x824dd211, 0x18270fd3, 0x824ca268,
+ 0x1820e431, 0x824b730c,
+ 0x181ab881, 0x824a43fe, 0x18148cc2, 0x8249153d, 0x180e60f4, 0x8247e6ca,
+ 0x18083518, 0x8246b8a4,
+ 0x1802092c, 0x82458acc, 0x17fbdd32, 0x82445d41, 0x17f5b129, 0x82433004,
+ 0x17ef8511, 0x82420315,
+ 0x17e958ea, 0x8240d673, 0x17e32cb5, 0x823faa1e, 0x17dd0070, 0x823e7e18,
+ 0x17d6d41d, 0x823d525e,
+ 0x17d0a7bc, 0x823c26f3, 0x17ca7b4c, 0x823afbd5, 0x17c44ecd, 0x8239d104,
+ 0x17be223f, 0x8238a681,
+ 0x17b7f5a3, 0x82377c4c, 0x17b1c8f8, 0x82365264, 0x17ab9c3e, 0x823528ca,
+ 0x17a56f76, 0x8233ff7e,
+ 0x179f429f, 0x8232d67f, 0x179915ba, 0x8231adce, 0x1792e8c6, 0x8230856a,
+ 0x178cbbc4, 0x822f5d54,
+ 0x17868eb3, 0x822e358b, 0x17806194, 0x822d0e10, 0x177a3466, 0x822be6e3,
+ 0x17740729, 0x822ac004,
+ 0x176dd9de, 0x82299971, 0x1767ac85, 0x8228732d, 0x17617f1d, 0x82274d36,
+ 0x175b51a7, 0x8226278d,
+ 0x17552422, 0x82250232, 0x174ef68f, 0x8223dd24, 0x1748c8ee, 0x8222b863,
+ 0x17429b3e, 0x822193f1,
+ 0x173c6d80, 0x82206fcc, 0x17363fb4, 0x821f4bf5, 0x173011d9, 0x821e286b,
+ 0x1729e3f0, 0x821d052f,
+ 0x1723b5f9, 0x821be240, 0x171d87f3, 0x821abfa0, 0x171759df, 0x82199d4d,
+ 0x17112bbd, 0x82187b47,
+ 0x170afd8d, 0x82175990, 0x1704cf4f, 0x82163826, 0x16fea102, 0x82151709,
+ 0x16f872a7, 0x8213f63a,
+ 0x16f2443e, 0x8212d5b9, 0x16ec15c7, 0x8211b586, 0x16e5e741, 0x821095a0,
+ 0x16dfb8ae, 0x820f7608,
+ 0x16d98a0c, 0x820e56be, 0x16d35b5c, 0x820d37c1, 0x16cd2c9f, 0x820c1912,
+ 0x16c6fdd3, 0x820afab1,
+ 0x16c0cef9, 0x8209dc9e, 0x16baa011, 0x8208bed8, 0x16b4711b, 0x8207a160,
+ 0x16ae4217, 0x82068435,
+ 0x16a81305, 0x82056758, 0x16a1e3e5, 0x82044ac9, 0x169bb4b7, 0x82032e88,
+ 0x1695857b, 0x82021294,
+ 0x168f5632, 0x8200f6ef, 0x168926da, 0x81ffdb96, 0x1682f774, 0x81fec08c,
+ 0x167cc801, 0x81fda5cf,
+ 0x1676987f, 0x81fc8b60, 0x167068f0, 0x81fb713f, 0x166a3953, 0x81fa576c,
+ 0x166409a8, 0x81f93de6,
+ 0x165dd9f0, 0x81f824ae, 0x1657aa29, 0x81f70bc3, 0x16517a55, 0x81f5f327,
+ 0x164b4a73, 0x81f4dad8,
+ 0x16451a83, 0x81f3c2d7, 0x163eea86, 0x81f2ab24, 0x1638ba7a, 0x81f193be,
+ 0x16328a61, 0x81f07ca6,
+ 0x162c5a3b, 0x81ef65dc, 0x16262a06, 0x81ee4f60, 0x161ff9c4, 0x81ed3932,
+ 0x1619c975, 0x81ec2351,
+ 0x16139918, 0x81eb0dbe, 0x160d68ad, 0x81e9f879, 0x16073834, 0x81e8e381,
+ 0x160107ae, 0x81e7ced8,
+ 0x15fad71b, 0x81e6ba7c, 0x15f4a679, 0x81e5a66e, 0x15ee75cb, 0x81e492ad,
+ 0x15e8450e, 0x81e37f3b,
+ 0x15e21445, 0x81e26c16, 0x15dbe36d, 0x81e1593f, 0x15d5b288, 0x81e046b6,
+ 0x15cf8196, 0x81df347b,
+ 0x15c95097, 0x81de228d, 0x15c31f89, 0x81dd10ee, 0x15bcee6f, 0x81dbff9c,
+ 0x15b6bd47, 0x81daee98,
+ 0x15b08c12, 0x81d9dde1, 0x15aa5acf, 0x81d8cd79, 0x15a4297f, 0x81d7bd5e,
+ 0x159df821, 0x81d6ad92,
+ 0x1597c6b7, 0x81d59e13, 0x1591953e, 0x81d48ee1, 0x158b63b9, 0x81d37ffe,
+ 0x15853226, 0x81d27169,
+ 0x157f0086, 0x81d16321, 0x1578ced9, 0x81d05527, 0x15729d1f, 0x81cf477b,
+ 0x156c6b57, 0x81ce3a1d,
+ 0x15663982, 0x81cd2d0c, 0x156007a0, 0x81cc204a, 0x1559d5b1, 0x81cb13d5,
+ 0x1553a3b4, 0x81ca07af,
+ 0x154d71aa, 0x81c8fbd6, 0x15473f94, 0x81c7f04b, 0x15410d70, 0x81c6e50d,
+ 0x153adb3f, 0x81c5da1e,
+ 0x1534a901, 0x81c4cf7d, 0x152e76b5, 0x81c3c529, 0x1528445d, 0x81c2bb23,
+ 0x152211f8, 0x81c1b16b,
+ 0x151bdf86, 0x81c0a801, 0x1515ad06, 0x81bf9ee5, 0x150f7a7a, 0x81be9617,
+ 0x150947e1, 0x81bd8d97,
+ 0x1503153a, 0x81bc8564, 0x14fce287, 0x81bb7d7f, 0x14f6afc7, 0x81ba75e9,
+ 0x14f07cf9, 0x81b96ea0,
+ 0x14ea4a1f, 0x81b867a5, 0x14e41738, 0x81b760f8, 0x14dde445, 0x81b65a99,
+ 0x14d7b144, 0x81b55488,
+ 0x14d17e36, 0x81b44ec4, 0x14cb4b1c, 0x81b3494f, 0x14c517f4, 0x81b24427,
+ 0x14bee4c0, 0x81b13f4e,
+ 0x14b8b17f, 0x81b03ac2, 0x14b27e32, 0x81af3684, 0x14ac4ad7, 0x81ae3294,
+ 0x14a61770, 0x81ad2ef2,
+ 0x149fe3fc, 0x81ac2b9e, 0x1499b07c, 0x81ab2898, 0x14937cee, 0x81aa25e0,
+ 0x148d4954, 0x81a92376,
+ 0x148715ae, 0x81a82159, 0x1480e1fa, 0x81a71f8b, 0x147aae3a, 0x81a61e0b,
+ 0x14747a6d, 0x81a51cd8,
+ 0x146e4694, 0x81a41bf4, 0x146812ae, 0x81a31b5d, 0x1461debc, 0x81a21b14,
+ 0x145baabd, 0x81a11b1a,
+ 0x145576b1, 0x81a01b6d, 0x144f4299, 0x819f1c0e, 0x14490e74, 0x819e1cfd,
+ 0x1442da43, 0x819d1e3a,
+ 0x143ca605, 0x819c1fc5, 0x143671bb, 0x819b219e, 0x14303d65, 0x819a23c5,
+ 0x142a0902, 0x8199263a,
+ 0x1423d492, 0x819828fd, 0x141da016, 0x81972c0e, 0x14176b8e, 0x81962f6d,
+ 0x141136f9, 0x8195331a,
+ 0x140b0258, 0x81943715, 0x1404cdaa, 0x81933b5e, 0x13fe98f1, 0x81923ff4,
+ 0x13f8642a, 0x819144d9,
+ 0x13f22f58, 0x81904a0c, 0x13ebfa79, 0x818f4f8d, 0x13e5c58e, 0x818e555c,
+ 0x13df9097, 0x818d5b78,
+ 0x13d95b93, 0x818c61e3, 0x13d32683, 0x818b689c, 0x13ccf167, 0x818a6fa3,
+ 0x13c6bc3f, 0x818976f8,
+ 0x13c0870a, 0x81887e9a, 0x13ba51ca, 0x8187868b, 0x13b41c7d, 0x81868eca,
+ 0x13ade724, 0x81859757,
+ 0x13a7b1bf, 0x8184a032, 0x13a17c4d, 0x8183a95b, 0x139b46d0, 0x8182b2d1,
+ 0x13951146, 0x8181bc96,
+ 0x138edbb1, 0x8180c6a9, 0x1388a60f, 0x817fd10a, 0x13827062, 0x817edbb9,
+ 0x137c3aa8, 0x817de6b6,
+ 0x137604e2, 0x817cf201, 0x136fcf10, 0x817bfd9b, 0x13699933, 0x817b0982,
+ 0x13636349, 0x817a15b7,
+ 0x135d2d53, 0x8179223a, 0x1356f752, 0x81782f0b, 0x1350c144, 0x81773c2b,
+ 0x134a8b2b, 0x81764998,
+ 0x13445505, 0x81755754, 0x133e1ed4, 0x8174655d, 0x1337e897, 0x817373b5,
+ 0x1331b24e, 0x8172825a,
+ 0x132b7bf9, 0x8171914e, 0x13254599, 0x8170a090, 0x131f0f2c, 0x816fb020,
+ 0x1318d8b4, 0x816ebffe,
+ 0x1312a230, 0x816dd02a, 0x130c6ba0, 0x816ce0a4, 0x13063505, 0x816bf16c,
+ 0x12fffe5d, 0x816b0282,
+ 0x12f9c7aa, 0x816a13e6, 0x12f390ec, 0x81692599, 0x12ed5a21, 0x81683799,
+ 0x12e7234b, 0x816749e8,
+ 0x12e0ec6a, 0x81665c84, 0x12dab57c, 0x81656f6f, 0x12d47e83, 0x816482a8,
+ 0x12ce477f, 0x8163962f,
+ 0x12c8106f, 0x8162aa04, 0x12c1d953, 0x8161be27, 0x12bba22b, 0x8160d298,
+ 0x12b56af9, 0x815fe758,
+ 0x12af33ba, 0x815efc65, 0x12a8fc70, 0x815e11c1, 0x12a2c51b, 0x815d276a,
+ 0x129c8dba, 0x815c3d62,
+ 0x1296564d, 0x815b53a8, 0x12901ed5, 0x815a6a3c, 0x1289e752, 0x8159811e,
+ 0x1283afc3, 0x8158984e,
+ 0x127d7829, 0x8157afcd, 0x12774083, 0x8156c799, 0x127108d2, 0x8155dfb4,
+ 0x126ad116, 0x8154f81d,
+ 0x1264994e, 0x815410d4, 0x125e617b, 0x815329d9, 0x1258299c, 0x8152432c,
+ 0x1251f1b3, 0x81515ccd,
+ 0x124bb9be, 0x815076bd, 0x124581bd, 0x814f90fb, 0x123f49b2, 0x814eab86,
+ 0x1239119b, 0x814dc660,
+ 0x1232d979, 0x814ce188, 0x122ca14b, 0x814bfcff, 0x12266913, 0x814b18c3,
+ 0x122030cf, 0x814a34d6,
+ 0x1219f880, 0x81495136, 0x1213c026, 0x81486de5, 0x120d87c1, 0x81478ae2,
+ 0x12074f50, 0x8146a82e,
+ 0x120116d5, 0x8145c5c7, 0x11fade4e, 0x8144e3ae, 0x11f4a5bd, 0x814401e4,
+ 0x11ee6d20, 0x81432068,
+ 0x11e83478, 0x81423f3a, 0x11e1fbc5, 0x81415e5a, 0x11dbc307, 0x81407dc9,
+ 0x11d58a3e, 0x813f9d86,
+ 0x11cf516a, 0x813ebd90, 0x11c9188b, 0x813ddde9, 0x11c2dfa2, 0x813cfe91,
+ 0x11bca6ad, 0x813c1f86,
+ 0x11b66dad, 0x813b40ca, 0x11b034a2, 0x813a625b, 0x11a9fb8d, 0x8139843b,
+ 0x11a3c26c, 0x8138a66a,
+ 0x119d8941, 0x8137c8e6, 0x1197500a, 0x8136ebb1, 0x119116c9, 0x81360ec9,
+ 0x118add7d, 0x81353230,
+ 0x1184a427, 0x813455e6, 0x117e6ac5, 0x813379e9, 0x11783159, 0x81329e3b,
+ 0x1171f7e2, 0x8131c2db,
+ 0x116bbe60, 0x8130e7c9, 0x116584d3, 0x81300d05, 0x115f4b3c, 0x812f3290,
+ 0x1159119a, 0x812e5868,
+ 0x1152d7ed, 0x812d7e8f, 0x114c9e35, 0x812ca505, 0x11466473, 0x812bcbc8,
+ 0x11402aa6, 0x812af2da,
+ 0x1139f0cf, 0x812a1a3a, 0x1133b6ed, 0x812941e8, 0x112d7d00, 0x812869e4,
+ 0x11274309, 0x8127922f,
+ 0x11210907, 0x8126bac8, 0x111acefb, 0x8125e3af, 0x111494e4, 0x81250ce4,
+ 0x110e5ac2, 0x81243668,
+ 0x11082096, 0x8123603a, 0x1101e65f, 0x81228a5a, 0x10fbac1e, 0x8121b4c8,
+ 0x10f571d3, 0x8120df85,
+ 0x10ef377d, 0x81200a90, 0x10e8fd1c, 0x811f35e9, 0x10e2c2b2, 0x811e6191,
+ 0x10dc883c, 0x811d8d86,
+ 0x10d64dbd, 0x811cb9ca, 0x10d01333, 0x811be65d, 0x10c9d89e, 0x811b133d,
+ 0x10c39dff, 0x811a406c,
+ 0x10bd6356, 0x81196de9, 0x10b728a3, 0x81189bb4, 0x10b0ede5, 0x8117c9ce,
+ 0x10aab31d, 0x8116f836,
+ 0x10a4784b, 0x811626ec, 0x109e3d6e, 0x811555f1, 0x10980287, 0x81148544,
+ 0x1091c796, 0x8113b4e5,
+ 0x108b8c9b, 0x8112e4d4, 0x10855195, 0x81121512, 0x107f1686, 0x8111459e,
+ 0x1078db6c, 0x81107678,
+ 0x1072a048, 0x810fa7a0, 0x106c651a, 0x810ed917, 0x106629e1, 0x810e0adc,
+ 0x105fee9f, 0x810d3cf0,
+ 0x1059b352, 0x810c6f52, 0x105377fc, 0x810ba202, 0x104d3c9b, 0x810ad500,
+ 0x10470130, 0x810a084d,
+ 0x1040c5bb, 0x81093be8, 0x103a8a3d, 0x81086fd1, 0x10344eb4, 0x8107a409,
+ 0x102e1321, 0x8106d88f,
+ 0x1027d784, 0x81060d63, 0x10219bdd, 0x81054286, 0x101b602d, 0x810477f7,
+ 0x10152472, 0x8103adb6,
+ 0x100ee8ad, 0x8102e3c4, 0x1008acdf, 0x81021a20, 0x10027107, 0x810150ca,
+ 0xffc3524, 0x810087c3,
+ 0xff5f938, 0x80ffbf0a, 0xfefbd42, 0x80fef69f, 0xfe98143, 0x80fe2e83,
+ 0xfe34539, 0x80fd66b5,
+ 0xfdd0926, 0x80fc9f35, 0xfd6cd08, 0x80fbd804, 0xfd090e1, 0x80fb1121,
+ 0xfca54b1, 0x80fa4a8c,
+ 0xfc41876, 0x80f98446, 0xfbddc32, 0x80f8be4e, 0xfb79fe4, 0x80f7f8a4,
+ 0xfb1638d, 0x80f73349,
+ 0xfab272b, 0x80f66e3c, 0xfa4eac0, 0x80f5a97e, 0xf9eae4c, 0x80f4e50e,
+ 0xf9871ce, 0x80f420ec,
+ 0xf923546, 0x80f35d19, 0xf8bf8b4, 0x80f29994, 0xf85bc19, 0x80f1d65d,
+ 0xf7f7f75, 0x80f11375,
+ 0xf7942c7, 0x80f050db, 0xf73060f, 0x80ef8e90, 0xf6cc94e, 0x80eecc93,
+ 0xf668c83, 0x80ee0ae4,
+ 0xf604faf, 0x80ed4984, 0xf5a12d1, 0x80ec8872, 0xf53d5ea, 0x80ebc7ae,
+ 0xf4d98f9, 0x80eb0739,
+ 0xf475bff, 0x80ea4712, 0xf411efb, 0x80e9873a, 0xf3ae1ee, 0x80e8c7b0,
+ 0xf34a4d8, 0x80e80874,
+ 0xf2e67b8, 0x80e74987, 0xf282a8f, 0x80e68ae8, 0xf21ed5d, 0x80e5cc98,
+ 0xf1bb021, 0x80e50e96,
+ 0xf1572dc, 0x80e450e2, 0xf0f358e, 0x80e3937d, 0xf08f836, 0x80e2d666,
+ 0xf02bad5, 0x80e2199e,
+ 0xefc7d6b, 0x80e15d24, 0xef63ff7, 0x80e0a0f8, 0xef0027b, 0x80dfe51b,
+ 0xee9c4f5, 0x80df298c,
+ 0xee38766, 0x80de6e4c, 0xedd49ce, 0x80ddb35a, 0xed70c2c, 0x80dcf8b7,
+ 0xed0ce82, 0x80dc3e62,
+ 0xeca90ce, 0x80db845b, 0xec45311, 0x80dacaa3, 0xebe154b, 0x80da1139,
+ 0xeb7d77c, 0x80d9581e,
+ 0xeb199a4, 0x80d89f51, 0xeab5bc3, 0x80d7e6d3, 0xea51dd8, 0x80d72ea3,
+ 0xe9edfe5, 0x80d676c1,
+ 0xe98a1e9, 0x80d5bf2e, 0xe9263e3, 0x80d507e9, 0xe8c25d5, 0x80d450f3,
+ 0xe85e7be, 0x80d39a4b,
+ 0xe7fa99e, 0x80d2e3f2, 0xe796b74, 0x80d22de7, 0xe732d42, 0x80d1782a,
+ 0xe6cef07, 0x80d0c2bc,
+ 0xe66b0c3, 0x80d00d9d, 0xe607277, 0x80cf58cc, 0xe5a3421, 0x80cea449,
+ 0xe53f5c2, 0x80cdf015,
+ 0xe4db75b, 0x80cd3c2f, 0xe4778eb, 0x80cc8898, 0xe413a72, 0x80cbd54f,
+ 0xe3afbf0, 0x80cb2255,
+ 0xe34bd66, 0x80ca6fa9, 0xe2e7ed2, 0x80c9bd4c, 0xe284036, 0x80c90b3d,
+ 0xe220191, 0x80c8597c,
+ 0xe1bc2e4, 0x80c7a80a, 0xe15842e, 0x80c6f6e7, 0xe0f456f, 0x80c64612,
+ 0xe0906a7, 0x80c5958b,
+ 0xe02c7d7, 0x80c4e553, 0xdfc88fe, 0x80c4356a, 0xdf64a1c, 0x80c385cf,
+ 0xdf00b32, 0x80c2d682,
+ 0xde9cc40, 0x80c22784, 0xde38d44, 0x80c178d4, 0xddd4e40, 0x80c0ca73,
+ 0xdd70f34, 0x80c01c60,
+ 0xdd0d01f, 0x80bf6e9c, 0xdca9102, 0x80bec127, 0xdc451dc, 0x80be13ff,
+ 0xdbe12ad, 0x80bd6727,
+ 0xdb7d376, 0x80bcba9d, 0xdb19437, 0x80bc0e61, 0xdab54ef, 0x80bb6274,
+ 0xda5159f, 0x80bab6d5,
+ 0xd9ed646, 0x80ba0b85, 0xd9896e5, 0x80b96083, 0xd92577b, 0x80b8b5d0,
+ 0xd8c1809, 0x80b80b6c,
+ 0xd85d88f, 0x80b76156, 0xd7f990c, 0x80b6b78e, 0xd795982, 0x80b60e15,
+ 0xd7319ee, 0x80b564ea,
+ 0xd6cda53, 0x80b4bc0e, 0xd669aaf, 0x80b41381, 0xd605b03, 0x80b36b42,
+ 0xd5a1b4f, 0x80b2c351,
+ 0xd53db92, 0x80b21baf, 0xd4d9bcd, 0x80b1745c, 0xd475c00, 0x80b0cd57,
+ 0xd411c2b, 0x80b026a1,
+ 0xd3adc4e, 0x80af8039, 0xd349c68, 0x80aeda20, 0xd2e5c7b, 0x80ae3455,
+ 0xd281c85, 0x80ad8ed9,
+ 0xd21dc87, 0x80ace9ab, 0xd1b9c81, 0x80ac44cc, 0xd155c73, 0x80aba03b,
+ 0xd0f1c5d, 0x80aafbf9,
+ 0xd08dc3f, 0x80aa5806, 0xd029c18, 0x80a9b461, 0xcfc5bea, 0x80a9110b,
+ 0xcf61bb4, 0x80a86e03,
+ 0xcefdb76, 0x80a7cb49, 0xce99b2f, 0x80a728df, 0xce35ae1, 0x80a686c2,
+ 0xcdd1a8b, 0x80a5e4f5,
+ 0xcd6da2d, 0x80a54376, 0xcd099c7, 0x80a4a245, 0xcca5959, 0x80a40163,
+ 0xcc418e3, 0x80a360d0,
+ 0xcbdd865, 0x80a2c08b, 0xcb797e0, 0x80a22095, 0xcb15752, 0x80a180ed,
+ 0xcab16bd, 0x80a0e194,
+ 0xca4d620, 0x80a04289, 0xc9e957b, 0x809fa3cd, 0xc9854cf, 0x809f0560,
+ 0xc92141a, 0x809e6741,
+ 0xc8bd35e, 0x809dc971, 0xc85929a, 0x809d2bef, 0xc7f51cf, 0x809c8ebc,
+ 0xc7910fb, 0x809bf1d7,
+ 0xc72d020, 0x809b5541, 0xc6c8f3e, 0x809ab8fa, 0xc664e53, 0x809a1d01,
+ 0xc600d61, 0x80998157,
+ 0xc59cc68, 0x8098e5fb, 0xc538b66, 0x80984aee, 0xc4d4a5d, 0x8097b030,
+ 0xc47094d, 0x809715c0,
+ 0xc40c835, 0x80967b9f, 0xc3a8715, 0x8095e1cc, 0xc3445ee, 0x80954848,
+ 0xc2e04c0, 0x8094af13,
+ 0xc27c389, 0x8094162c, 0xc21824c, 0x80937d93, 0xc1b4107, 0x8092e54a,
+ 0xc14ffba, 0x80924d4f,
+ 0xc0ebe66, 0x8091b5a2, 0xc087d0a, 0x80911e44, 0xc023ba7, 0x80908735,
+ 0xbfbfa3d, 0x808ff074,
+ 0xbf5b8cb, 0x808f5a02, 0xbef7752, 0x808ec3df, 0xbe935d2, 0x808e2e0a,
+ 0xbe2f44a, 0x808d9884,
+ 0xbdcb2bb, 0x808d034c, 0xbd67124, 0x808c6e63, 0xbd02f87, 0x808bd9c9,
+ 0xbc9ede2, 0x808b457d,
+ 0xbc3ac35, 0x808ab180, 0xbbd6a82, 0x808a1dd2, 0xbb728c7, 0x80898a72,
+ 0xbb0e705, 0x8088f761,
+ 0xbaaa53b, 0x8088649e, 0xba4636b, 0x8087d22a, 0xb9e2193, 0x80874005,
+ 0xb97dfb5, 0x8086ae2e,
+ 0xb919dcf, 0x80861ca6, 0xb8b5be1, 0x80858b6c, 0xb8519ed, 0x8084fa82,
+ 0xb7ed7f2, 0x808469e5,
+ 0xb7895f0, 0x8083d998, 0xb7253e6, 0x80834999, 0xb6c11d5, 0x8082b9e9,
+ 0xb65cfbe, 0x80822a87,
+ 0xb5f8d9f, 0x80819b74, 0xb594b7a, 0x80810cb0, 0xb53094d, 0x80807e3a,
+ 0xb4cc719, 0x807ff013,
+ 0xb4684df, 0x807f623b, 0xb40429d, 0x807ed4b1, 0xb3a0055, 0x807e4776,
+ 0xb33be05, 0x807dba89,
+ 0xb2d7baf, 0x807d2dec, 0xb273952, 0x807ca19c, 0xb20f6ee, 0x807c159c,
+ 0xb1ab483, 0x807b89ea,
+ 0xb147211, 0x807afe87, 0xb0e2f98, 0x807a7373, 0xb07ed19, 0x8079e8ad,
+ 0xb01aa92, 0x80795e36,
+ 0xafb6805, 0x8078d40d, 0xaf52571, 0x80784a33, 0xaeee2d7, 0x8077c0a8,
+ 0xae8a036, 0x8077376c,
+ 0xae25d8d, 0x8076ae7e, 0xadc1adf, 0x807625df, 0xad5d829, 0x80759d8e,
+ 0xacf956d, 0x8075158c,
+ 0xac952aa, 0x80748dd9, 0xac30fe1, 0x80740675, 0xabccd11, 0x80737f5f,
+ 0xab68a3a, 0x8072f898,
+ 0xab0475c, 0x8072721f, 0xaaa0478, 0x8071ebf6, 0xaa3c18e, 0x8071661a,
+ 0xa9d7e9d, 0x8070e08e,
+ 0xa973ba5, 0x80705b50, 0xa90f8a7, 0x806fd661, 0xa8ab5a2, 0x806f51c1,
+ 0xa847297, 0x806ecd6f,
+ 0xa7e2f85, 0x806e496c, 0xa77ec6d, 0x806dc5b8, 0xa71a94f, 0x806d4253,
+ 0xa6b662a, 0x806cbf3c,
+ 0xa6522fe, 0x806c3c74, 0xa5edfcc, 0x806bb9fa, 0xa589c94, 0x806b37cf,
+ 0xa525955, 0x806ab5f3,
+ 0xa4c1610, 0x806a3466, 0xa45d2c5, 0x8069b327, 0xa3f8f73, 0x80693237,
+ 0xa394c1b, 0x8068b196,
+ 0xa3308bd, 0x80683143, 0xa2cc558, 0x8067b13f, 0xa2681ed, 0x8067318a,
+ 0xa203e7c, 0x8066b224,
+ 0xa19fb04, 0x8066330c, 0xa13b787, 0x8065b443, 0xa0d7403, 0x806535c9,
+ 0xa073079, 0x8064b79d,
+ 0xa00ece8, 0x806439c0, 0x9faa952, 0x8063bc32, 0x9f465b5, 0x80633ef3,
+ 0x9ee2213, 0x8062c202,
+ 0x9e7de6a, 0x80624560, 0x9e19abb, 0x8061c90c, 0x9db5706, 0x80614d08,
+ 0x9d5134b, 0x8060d152,
+ 0x9cecf89, 0x806055eb, 0x9c88bc2, 0x805fdad2, 0x9c247f5, 0x805f6009,
+ 0x9bc0421, 0x805ee58e,
+ 0x9b5c048, 0x805e6b62, 0x9af7c69, 0x805df184, 0x9a93884, 0x805d77f5,
+ 0x9a2f498, 0x805cfeb5,
+ 0x99cb0a7, 0x805c85c4, 0x9966cb0, 0x805c0d21, 0x99028b3, 0x805b94ce,
+ 0x989e4b0, 0x805b1cc8,
+ 0x983a0a7, 0x805aa512, 0x97d5c99, 0x805a2daa, 0x9771884, 0x8059b692,
+ 0x970d46a, 0x80593fc7,
+ 0x96a9049, 0x8058c94c, 0x9644c23, 0x8058531f, 0x95e07f8, 0x8057dd41,
+ 0x957c3c6, 0x805767b2,
+ 0x9517f8f, 0x8056f272, 0x94b3b52, 0x80567d80, 0x944f70f, 0x805608dd,
+ 0x93eb2c6, 0x80559489,
+ 0x9386e78, 0x80552084, 0x9322a24, 0x8054accd, 0x92be5ca, 0x80543965,
+ 0x925a16b, 0x8053c64c,
+ 0x91f5d06, 0x80535381, 0x919189c, 0x8052e106, 0x912d42c, 0x80526ed9,
+ 0x90c8fb6, 0x8051fcfb,
+ 0x9064b3a, 0x80518b6b, 0x90006ba, 0x80511a2b, 0x8f9c233, 0x8050a939,
+ 0x8f37da7, 0x80503896,
+ 0x8ed3916, 0x804fc841, 0x8e6f47f, 0x804f583c, 0x8e0afe2, 0x804ee885,
+ 0x8da6b40, 0x804e791d,
+ 0x8d42699, 0x804e0a04, 0x8cde1ec, 0x804d9b39, 0x8c79d3a, 0x804d2cbd,
+ 0x8c15882, 0x804cbe90,
+ 0x8bb13c5, 0x804c50b2, 0x8b4cf02, 0x804be323, 0x8ae8a3a, 0x804b75e2,
+ 0x8a8456d, 0x804b08f0,
+ 0x8a2009a, 0x804a9c4d, 0x89bbbc3, 0x804a2ff9, 0x89576e5, 0x8049c3f3,
+ 0x88f3203, 0x8049583d,
+ 0x888ed1b, 0x8048ecd5, 0x882a82e, 0x804881bb, 0x87c633c, 0x804816f1,
+ 0x8761e44, 0x8047ac75,
+ 0x86fd947, 0x80474248, 0x8699445, 0x8046d86a, 0x8634f3e, 0x80466edb,
+ 0x85d0a32, 0x8046059b,
+ 0x856c520, 0x80459ca9, 0x850800a, 0x80453406, 0x84a3aee, 0x8044cbb2,
+ 0x843f5cd, 0x804463ad,
+ 0x83db0a7, 0x8043fbf6, 0x8376b7c, 0x8043948e, 0x831264c, 0x80432d75,
+ 0x82ae117, 0x8042c6ab,
+ 0x8249bdd, 0x80426030, 0x81e569d, 0x8041fa03, 0x8181159, 0x80419425,
+ 0x811cc10, 0x80412e96,
+ 0x80b86c2, 0x8040c956, 0x805416e, 0x80406465, 0x7fefc16, 0x803fffc2,
+ 0x7f8b6b9, 0x803f9b6f,
+ 0x7f27157, 0x803f376a, 0x7ec2bf0, 0x803ed3b3, 0x7e5e685, 0x803e704c,
+ 0x7dfa114, 0x803e0d34,
+ 0x7d95b9e, 0x803daa6a, 0x7d31624, 0x803d47ef, 0x7ccd0a5, 0x803ce5c3,
+ 0x7c68b21, 0x803c83e5,
+ 0x7c04598, 0x803c2257, 0x7ba000b, 0x803bc117, 0x7b3ba78, 0x803b6026,
+ 0x7ad74e1, 0x803aff84,
+ 0x7a72f45, 0x803a9f31, 0x7a0e9a5, 0x803a3f2d, 0x79aa400, 0x8039df77,
+ 0x7945e56, 0x80398010,
+ 0x78e18a7, 0x803920f8, 0x787d2f4, 0x8038c22f, 0x7818d3c, 0x803863b5,
+ 0x77b4780, 0x80380589,
+ 0x77501be, 0x8037a7ac, 0x76ebbf9, 0x80374a1f, 0x768762e, 0x8036ece0,
+ 0x762305f, 0x80368fef,
+ 0x75bea8c, 0x8036334e, 0x755a4b4, 0x8035d6fb, 0x74f5ed7, 0x80357af8,
+ 0x74918f6, 0x80351f43,
+ 0x742d311, 0x8034c3dd, 0x73c8d27, 0x803468c5, 0x7364738, 0x80340dfd,
+ 0x7300145, 0x8033b383,
+ 0x729bb4e, 0x80335959, 0x7237552, 0x8032ff7d, 0x71d2f52, 0x8032a5ef,
+ 0x716e94e, 0x80324cb1,
+ 0x710a345, 0x8031f3c2, 0x70a5d37, 0x80319b21, 0x7041726, 0x803142cf,
+ 0x6fdd110, 0x8030eacd,
+ 0x6f78af6, 0x80309318, 0x6f144d7, 0x80303bb3, 0x6eafeb4, 0x802fe49d,
+ 0x6e4b88d, 0x802f8dd5,
+ 0x6de7262, 0x802f375d, 0x6d82c32, 0x802ee133, 0x6d1e5fe, 0x802e8b58,
+ 0x6cb9fc6, 0x802e35cb,
+ 0x6c5598a, 0x802de08e, 0x6bf1349, 0x802d8ba0, 0x6b8cd05, 0x802d3700,
+ 0x6b286bc, 0x802ce2af,
+ 0x6ac406f, 0x802c8ead, 0x6a5fa1e, 0x802c3afa, 0x69fb3c9, 0x802be796,
+ 0x6996d70, 0x802b9480,
+ 0x6932713, 0x802b41ba, 0x68ce0b2, 0x802aef42, 0x6869a4c, 0x802a9d19,
+ 0x68053e3, 0x802a4b3f,
+ 0x67a0d76, 0x8029f9b4, 0x673c704, 0x8029a878, 0x66d808f, 0x8029578b,
+ 0x6673a16, 0x802906ec,
+ 0x660f398, 0x8028b69c, 0x65aad17, 0x8028669b, 0x6546692, 0x802816e9,
+ 0x64e2009, 0x8027c786,
+ 0x647d97c, 0x80277872, 0x64192eb, 0x802729ad, 0x63b4c57, 0x8026db36,
+ 0x63505be, 0x80268d0e,
+ 0x62ebf22, 0x80263f36, 0x6287882, 0x8025f1ac, 0x62231de, 0x8025a471,
+ 0x61beb36, 0x80255784,
+ 0x615a48b, 0x80250ae7, 0x60f5ddc, 0x8024be99, 0x6091729, 0x80247299,
+ 0x602d072, 0x802426e8,
+ 0x5fc89b8, 0x8023db86, 0x5f642fa, 0x80239073, 0x5effc38, 0x802345af,
+ 0x5e9b572, 0x8022fb3a,
+ 0x5e36ea9, 0x8022b114, 0x5dd27dd, 0x8022673c, 0x5d6e10c, 0x80221db3,
+ 0x5d09a38, 0x8021d47a,
+ 0x5ca5361, 0x80218b8f, 0x5c40c86, 0x802142f3, 0x5bdc5a7, 0x8020faa6,
+ 0x5b77ec5, 0x8020b2a7,
+ 0x5b137df, 0x80206af8, 0x5aaf0f6, 0x80202397, 0x5a4aa09, 0x801fdc86,
+ 0x59e6319, 0x801f95c3,
+ 0x5981c26, 0x801f4f4f, 0x591d52f, 0x801f092a, 0x58b8e34, 0x801ec354,
+ 0x5854736, 0x801e7dcd,
+ 0x57f0035, 0x801e3895, 0x578b930, 0x801df3ab, 0x5727228, 0x801daf11,
+ 0x56c2b1c, 0x801d6ac5,
+ 0x565e40d, 0x801d26c8, 0x55f9cfb, 0x801ce31a, 0x55955e6, 0x801c9fbb,
+ 0x5530ecd, 0x801c5cab,
+ 0x54cc7b1, 0x801c19ea, 0x5468092, 0x801bd777, 0x540396f, 0x801b9554,
+ 0x539f249, 0x801b537f,
+ 0x533ab20, 0x801b11fa, 0x52d63f4, 0x801ad0c3, 0x5271cc4, 0x801a8fdb,
+ 0x520d592, 0x801a4f42,
+ 0x51a8e5c, 0x801a0ef8, 0x5144723, 0x8019cefd, 0x50dffe7, 0x80198f50,
+ 0x507b8a8, 0x80194ff3,
+ 0x5017165, 0x801910e4, 0x4fb2a20, 0x8018d225, 0x4f4e2d8, 0x801893b4,
+ 0x4ee9b8c, 0x80185592,
+ 0x4e8543e, 0x801817bf, 0x4e20cec, 0x8017da3b, 0x4dbc597, 0x80179d06,
+ 0x4d57e40, 0x80176020,
+ 0x4cf36e5, 0x80172388, 0x4c8ef88, 0x8016e740, 0x4c2a827, 0x8016ab46,
+ 0x4bc60c4, 0x80166f9c,
+ 0x4b6195d, 0x80163440, 0x4afd1f4, 0x8015f933, 0x4a98a88, 0x8015be75,
+ 0x4a34319, 0x80158406,
+ 0x49cfba7, 0x801549e6, 0x496b432, 0x80151015, 0x4906cbb, 0x8014d693,
+ 0x48a2540, 0x80149d5f,
+ 0x483ddc3, 0x8014647b, 0x47d9643, 0x80142be5, 0x4774ec1, 0x8013f39e,
+ 0x471073b, 0x8013bba7,
+ 0x46abfb3, 0x801383fe, 0x4647828, 0x80134ca4, 0x45e309a, 0x80131599,
+ 0x457e90a, 0x8012dedd,
+ 0x451a177, 0x8012a86f, 0x44b59e1, 0x80127251, 0x4451249, 0x80123c82,
+ 0x43ecaae, 0x80120701,
+ 0x4388310, 0x8011d1d0, 0x4323b70, 0x80119ced, 0x42bf3cd, 0x80116859,
+ 0x425ac28, 0x80113414,
+ 0x41f6480, 0x8011001f, 0x4191cd5, 0x8010cc78, 0x412d528, 0x8010991f,
+ 0x40c8d79, 0x80106616,
+ 0x40645c7, 0x8010335c, 0x3fffe12, 0x801000f1, 0x3f9b65b, 0x800fced4,
+ 0x3f36ea2, 0x800f9d07,
+ 0x3ed26e6, 0x800f6b88, 0x3e6df28, 0x800f3a59, 0x3e09767, 0x800f0978,
+ 0x3da4fa4, 0x800ed8e6,
+ 0x3d407df, 0x800ea8a3, 0x3cdc017, 0x800e78af, 0x3c7784d, 0x800e490a,
+ 0x3c13080, 0x800e19b4,
+ 0x3bae8b2, 0x800deaad, 0x3b4a0e0, 0x800dbbf5, 0x3ae590d, 0x800d8d8b,
+ 0x3a81137, 0x800d5f71,
+ 0x3a1c960, 0x800d31a5, 0x39b8185, 0x800d0429, 0x39539a9, 0x800cd6fb,
+ 0x38ef1ca, 0x800caa1c,
+ 0x388a9ea, 0x800c7d8c, 0x3826207, 0x800c514c, 0x37c1a22, 0x800c255a,
+ 0x375d23a, 0x800bf9b7,
+ 0x36f8a51, 0x800bce63, 0x3694265, 0x800ba35d, 0x362fa78, 0x800b78a7,
+ 0x35cb288, 0x800b4e40,
+ 0x3566a96, 0x800b2427, 0x35022a2, 0x800afa5e, 0x349daac, 0x800ad0e3,
+ 0x34392b4, 0x800aa7b8,
+ 0x33d4abb, 0x800a7edb, 0x33702bf, 0x800a564e, 0x330bac1, 0x800a2e0f,
+ 0x32a72c1, 0x800a061f,
+ 0x3242abf, 0x8009de7e, 0x31de2bb, 0x8009b72c, 0x3179ab5, 0x80099029,
+ 0x31152ae, 0x80096975,
+ 0x30b0aa4, 0x80094310, 0x304c299, 0x80091cf9, 0x2fe7a8c, 0x8008f732,
+ 0x2f8327d, 0x8008d1ba,
+ 0x2f1ea6c, 0x8008ac90, 0x2eba259, 0x800887b6, 0x2e55a44, 0x8008632a,
+ 0x2df122e, 0x80083eed,
+ 0x2d8ca16, 0x80081b00, 0x2d281fc, 0x8007f761, 0x2cc39e1, 0x8007d411,
+ 0x2c5f1c3, 0x8007b110,
+ 0x2bfa9a4, 0x80078e5e, 0x2b96184, 0x80076bfb, 0x2b31961, 0x800749e7,
+ 0x2acd13d, 0x80072822,
+ 0x2a68917, 0x800706ac, 0x2a040f0, 0x8006e585, 0x299f8c7, 0x8006c4ac,
+ 0x293b09c, 0x8006a423,
+ 0x28d6870, 0x800683e8, 0x2872043, 0x800663fd, 0x280d813, 0x80064460,
+ 0x27a8fe2, 0x80062513,
+ 0x27447b0, 0x80060614, 0x26dff7c, 0x8005e764, 0x267b747, 0x8005c904,
+ 0x2616f10, 0x8005aaf2,
+ 0x25b26d7, 0x80058d2f, 0x254de9e, 0x80056fbb, 0x24e9662, 0x80055296,
+ 0x2484e26, 0x800535c0,
+ 0x24205e8, 0x80051939, 0x23bbda8, 0x8004fd00, 0x2357567, 0x8004e117,
+ 0x22f2d25, 0x8004c57d,
+ 0x228e4e2, 0x8004aa32, 0x2229c9d, 0x80048f35, 0x21c5457, 0x80047488,
+ 0x2160c0f, 0x80045a29,
+ 0x20fc3c6, 0x8004401a, 0x2097b7c, 0x80042659, 0x2033331, 0x80040ce7,
+ 0x1fceae4, 0x8003f3c5,
+ 0x1f6a297, 0x8003daf1, 0x1f05a48, 0x8003c26c, 0x1ea11f7, 0x8003aa36,
+ 0x1e3c9a6, 0x8003924f,
+ 0x1dd8154, 0x80037ab7, 0x1d73900, 0x8003636e, 0x1d0f0ab, 0x80034c74,
+ 0x1caa855, 0x800335c9,
+ 0x1c45ffe, 0x80031f6d, 0x1be17a6, 0x80030960, 0x1b7cf4d, 0x8002f3a1,
+ 0x1b186f3, 0x8002de32,
+ 0x1ab3e97, 0x8002c912, 0x1a4f63b, 0x8002b440, 0x19eaddd, 0x80029fbe,
+ 0x198657f, 0x80028b8a,
+ 0x1921d20, 0x800277a6, 0x18bd4bf, 0x80026410, 0x1858c5e, 0x800250c9,
+ 0x17f43fc, 0x80023dd2,
+ 0x178fb99, 0x80022b29, 0x172b335, 0x800218cf, 0x16c6ad0, 0x800206c4,
+ 0x166226a, 0x8001f508,
+ 0x15fda03, 0x8001e39b, 0x159919c, 0x8001d27d, 0x1534934, 0x8001c1ae,
+ 0x14d00ca, 0x8001b12e,
+ 0x146b860, 0x8001a0fd, 0x1406ff6, 0x8001911b, 0x13a278a, 0x80018187,
+ 0x133df1e, 0x80017243,
+ 0x12d96b1, 0x8001634e, 0x1274e43, 0x800154a7, 0x12105d5, 0x80014650,
+ 0x11abd66, 0x80013847,
+ 0x11474f6, 0x80012a8e, 0x10e2c85, 0x80011d23, 0x107e414, 0x80011008,
+ 0x1019ba2, 0x8001033b,
+ 0xfb5330, 0x8000f6bd, 0xf50abd, 0x8000ea8e, 0xeec249, 0x8000deaf, 0xe879d5,
+ 0x8000d31e,
+ 0xe23160, 0x8000c7dc, 0xdbe8eb, 0x8000bce9, 0xd5a075, 0x8000b245, 0xcf57ff,
+ 0x8000a7f0,
+ 0xc90f88, 0x80009dea, 0xc2c711, 0x80009433, 0xbc7e99, 0x80008aca, 0xb63621,
+ 0x800081b1,
+ 0xafeda8, 0x800078e7, 0xa9a52f, 0x8000706c, 0xa35cb5, 0x8000683f, 0x9d143b,
+ 0x80006062,
+ 0x96cbc1, 0x800058d4, 0x908346, 0x80005194, 0x8a3acb, 0x80004aa4, 0x83f250,
+ 0x80004402,
+ 0x7da9d4, 0x80003daf, 0x776159, 0x800037ac, 0x7118dc, 0x800031f7, 0x6ad060,
+ 0x80002c91,
+ 0x6487e3, 0x8000277a, 0x5e3f66, 0x800022b3, 0x57f6e9, 0x80001e3a, 0x51ae6b,
+ 0x80001a10,
+ 0x4b65ee, 0x80001635, 0x451d70, 0x800012a9, 0x3ed4f2, 0x80000f6c, 0x388c74,
+ 0x80000c7e,
+ 0x3243f5, 0x800009df, 0x2bfb77, 0x8000078e, 0x25b2f8, 0x8000058d, 0x1f6a7a,
+ 0x800003db,
+ 0x1921fb, 0x80000278, 0x12d97c, 0x80000163, 0xc90fe, 0x8000009e, 0x6487f,
+ 0x80000027,
+
+};
+
+/**
+* \par
+* cosFactor tables are generated using the formula : <pre>cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))</pre>
+* \par
+* C command to generate the table
+* <pre>
+* for(i = 0; i< N; i++)
+* {
+* cos_factors[i]= 2 * cos((2*i+1)*c/2);
+* } </pre>
+* \par
+* where <code>N</code> is the number of factors to generate and <code>c</code> is <code>pi/(2*N)</code>
+* \par
+* Then converted to q31 format by multiplying with 2^31 and saturated if required.
+*/
+
+
+static const q31_t cos_factorsQ31_128[128] = {
+ 0x7fff6216, 0x7ffa72d1, 0x7ff09478, 0x7fe1c76b, 0x7fce0c3e, 0x7fb563b3,
+ 0x7f97cebd, 0x7f754e80,
+ 0x7f4de451, 0x7f2191b4, 0x7ef05860, 0x7eba3a39, 0x7e7f3957, 0x7e3f57ff,
+ 0x7dfa98a8, 0x7db0fdf8,
+ 0x7d628ac6, 0x7d0f4218, 0x7cb72724, 0x7c5a3d50, 0x7bf88830, 0x7b920b89,
+ 0x7b26cb4f, 0x7ab6cba4,
+ 0x7a4210d8, 0x79c89f6e, 0x794a7c12, 0x78c7aba2, 0x78403329, 0x77b417df,
+ 0x77235f2d, 0x768e0ea6,
+ 0x75f42c0b, 0x7555bd4c, 0x74b2c884, 0x740b53fb, 0x735f6626, 0x72af05a7,
+ 0x71fa3949, 0x71410805,
+ 0x708378ff, 0x6fc19385, 0x6efb5f12, 0x6e30e34a, 0x6d6227fa, 0x6c8f351c,
+ 0x6bb812d1, 0x6adcc964,
+ 0x69fd614a, 0x6919e320, 0x683257ab, 0x6746c7d8, 0x66573cbb, 0x6563bf92,
+ 0x646c59bf, 0x637114cc,
+ 0x6271fa69, 0x616f146c, 0x60686ccf, 0x5f5e0db3, 0x5e50015d, 0x5d3e5237,
+ 0x5c290acc, 0x5b1035cf,
+ 0x59f3de12, 0x58d40e8c, 0x57b0d256, 0x568a34a9, 0x556040e2, 0x5433027d,
+ 0x53028518, 0x51ced46e,
+ 0x5097fc5e, 0x4f5e08e3, 0x4e210617, 0x4ce10034, 0x4b9e0390, 0x4a581c9e,
+ 0x490f57ee, 0x47c3c22f,
+ 0x46756828, 0x452456bd, 0x43d09aed, 0x427a41d0, 0x4121589b, 0x3fc5ec98,
+ 0x3e680b2c, 0x3d07c1d6,
+ 0x3ba51e29, 0x3a402dd2, 0x38d8fe93, 0x376f9e46, 0x36041ad9, 0x34968250,
+ 0x3326e2c3, 0x31b54a5e,
+ 0x3041c761, 0x2ecc681e, 0x2d553afc, 0x2bdc4e6f, 0x2a61b101, 0x28e5714b,
+ 0x27679df4, 0x25e845b6,
+ 0x24677758, 0x22e541af, 0x2161b3a0, 0x1fdcdc1b, 0x1e56ca1e, 0x1ccf8cb3,
+ 0x1b4732ef, 0x19bdcbf3,
+ 0x183366e9, 0x16a81305, 0x151bdf86, 0x138edbb1, 0x120116d5, 0x1072a048,
+ 0xee38766, 0xd53db92,
+ 0xbc3ac35, 0xa3308bd, 0x8a2009a, 0x710a345, 0x57f0035, 0x3ed26e6, 0x25b26d7,
+ 0xc90f88,
+};
+
+static const q31_t cos_factorsQ31_512[512] = {
+ 0x7ffff621, 0x7fffa72c, 0x7fff0943, 0x7ffe1c65, 0x7ffce093, 0x7ffb55ce,
+ 0x7ff97c18, 0x7ff75370,
+ 0x7ff4dbd9, 0x7ff21553, 0x7feeffe1, 0x7feb9b85, 0x7fe7e841, 0x7fe3e616,
+ 0x7fdf9508, 0x7fdaf519,
+ 0x7fd6064c, 0x7fd0c8a3, 0x7fcb3c23, 0x7fc560cf, 0x7fbf36aa, 0x7fb8bdb8,
+ 0x7fb1f5fc, 0x7faadf7c,
+ 0x7fa37a3c, 0x7f9bc640, 0x7f93c38c, 0x7f8b7227, 0x7f82d214, 0x7f79e35a,
+ 0x7f70a5fe, 0x7f671a05,
+ 0x7f5d3f75, 0x7f531655, 0x7f489eaa, 0x7f3dd87c, 0x7f32c3d1, 0x7f2760af,
+ 0x7f1baf1e, 0x7f0faf25,
+ 0x7f0360cb, 0x7ef6c418, 0x7ee9d914, 0x7edc9fc6, 0x7ecf1837, 0x7ec14270,
+ 0x7eb31e78, 0x7ea4ac58,
+ 0x7e95ec1a, 0x7e86ddc6, 0x7e778166, 0x7e67d703, 0x7e57dea7, 0x7e47985b,
+ 0x7e37042a, 0x7e26221f,
+ 0x7e14f242, 0x7e0374a0, 0x7df1a942, 0x7ddf9034, 0x7dcd2981, 0x7dba7534,
+ 0x7da77359, 0x7d9423fc,
+ 0x7d808728, 0x7d6c9ce9, 0x7d58654d, 0x7d43e05e, 0x7d2f0e2b, 0x7d19eebf,
+ 0x7d048228, 0x7ceec873,
+ 0x7cd8c1ae, 0x7cc26de5, 0x7cabcd28, 0x7c94df83, 0x7c7da505, 0x7c661dbc,
+ 0x7c4e49b7, 0x7c362904,
+ 0x7c1dbbb3, 0x7c0501d2, 0x7bebfb70, 0x7bd2a89e, 0x7bb9096b, 0x7b9f1de6,
+ 0x7b84e61f, 0x7b6a6227,
+ 0x7b4f920e, 0x7b3475e5, 0x7b190dbc, 0x7afd59a4, 0x7ae159ae, 0x7ac50dec,
+ 0x7aa8766f, 0x7a8b9348,
+ 0x7a6e648a, 0x7a50ea47, 0x7a332490, 0x7a151378, 0x79f6b711, 0x79d80f6f,
+ 0x79b91ca4, 0x7999dec4,
+ 0x797a55e0, 0x795a820e, 0x793a6361, 0x7919f9ec, 0x78f945c3, 0x78d846fb,
+ 0x78b6fda8, 0x789569df,
+ 0x78738bb3, 0x7851633b, 0x782ef08b, 0x780c33b8, 0x77e92cd9, 0x77c5dc01,
+ 0x77a24148, 0x777e5cc3,
+ 0x775a2e89, 0x7735b6af, 0x7710f54c, 0x76ebea77, 0x76c69647, 0x76a0f8d2,
+ 0x767b1231, 0x7654e279,
+ 0x762e69c4, 0x7607a828, 0x75e09dbd, 0x75b94a9c, 0x7591aedd, 0x7569ca99,
+ 0x75419de7, 0x751928e0,
+ 0x74f06b9e, 0x74c7663a, 0x749e18cd, 0x74748371, 0x744aa63f, 0x74208150,
+ 0x73f614c0, 0x73cb60a8,
+ 0x73a06522, 0x73752249, 0x73499838, 0x731dc70a, 0x72f1aed9, 0x72c54fc1,
+ 0x7298a9dd, 0x726bbd48,
+ 0x723e8a20, 0x7211107e, 0x71e35080, 0x71b54a41, 0x7186fdde, 0x71586b74,
+ 0x7129931f, 0x70fa74fc,
+ 0x70cb1128, 0x709b67c0, 0x706b78e3, 0x703b44ad, 0x700acb3c, 0x6fda0cae,
+ 0x6fa90921, 0x6f77c0b3,
+ 0x6f463383, 0x6f1461b0, 0x6ee24b57, 0x6eaff099, 0x6e7d5193, 0x6e4a6e66,
+ 0x6e174730, 0x6de3dc11,
+ 0x6db02d29, 0x6d7c3a98, 0x6d48047e, 0x6d138afb, 0x6cdece2f, 0x6ca9ce3b,
+ 0x6c748b3f, 0x6c3f055d,
+ 0x6c093cb6, 0x6bd3316a, 0x6b9ce39b, 0x6b66536b, 0x6b2f80fb, 0x6af86c6c,
+ 0x6ac115e2, 0x6a897d7d,
+ 0x6a51a361, 0x6a1987b0, 0x69e12a8c, 0x69a88c19, 0x696fac78, 0x69368bce,
+ 0x68fd2a3d, 0x68c387e9,
+ 0x6889a4f6, 0x684f8186, 0x68151dbe, 0x67da79c3, 0x679f95b7, 0x676471c0,
+ 0x67290e02, 0x66ed6aa1,
+ 0x66b187c3, 0x6675658c, 0x66390422, 0x65fc63a9, 0x65bf8447, 0x65826622,
+ 0x6545095f, 0x65076e25,
+ 0x64c99498, 0x648b7ce0, 0x644d2722, 0x640e9386, 0x63cfc231, 0x6390b34a,
+ 0x635166f9, 0x6311dd64,
+ 0x62d216b3, 0x6292130c, 0x6251d298, 0x6211557e, 0x61d09be5, 0x618fa5f7,
+ 0x614e73da, 0x610d05b7,
+ 0x60cb5bb7, 0x60897601, 0x604754bf, 0x6004f819, 0x5fc26038, 0x5f7f8d46,
+ 0x5f3c7f6b, 0x5ef936d1,
+ 0x5eb5b3a2, 0x5e71f606, 0x5e2dfe29, 0x5de9cc33, 0x5da5604f, 0x5d60baa7,
+ 0x5d1bdb65, 0x5cd6c2b5,
+ 0x5c9170bf, 0x5c4be5b0, 0x5c0621b2, 0x5bc024f0, 0x5b79ef96, 0x5b3381ce,
+ 0x5aecdbc5, 0x5aa5fda5,
+ 0x5a5ee79a, 0x5a1799d1, 0x59d01475, 0x598857b2, 0x594063b5, 0x58f838a9,
+ 0x58afd6bd, 0x58673e1b,
+ 0x581e6ef1, 0x57d5696d, 0x578c2dba, 0x5742bc06, 0x56f9147e, 0x56af3750,
+ 0x566524aa, 0x561adcb9,
+ 0x55d05faa, 0x5585adad, 0x553ac6ee, 0x54efab9c, 0x54a45be6, 0x5458d7f9,
+ 0x540d2005, 0x53c13439,
+ 0x537514c2, 0x5328c1d0, 0x52dc3b92, 0x528f8238, 0x524295f0, 0x51f576ea,
+ 0x51a82555, 0x515aa162,
+ 0x510ceb40, 0x50bf031f, 0x5070e92f, 0x50229da1, 0x4fd420a4, 0x4f857269,
+ 0x4f369320, 0x4ee782fb,
+ 0x4e984229, 0x4e48d0dd, 0x4df92f46, 0x4da95d96, 0x4d595bfe, 0x4d092ab0,
+ 0x4cb8c9dd, 0x4c6839b7,
+ 0x4c177a6e, 0x4bc68c36, 0x4b756f40, 0x4b2423be, 0x4ad2a9e2, 0x4a8101de,
+ 0x4a2f2be6, 0x49dd282a,
+ 0x498af6df, 0x49389836, 0x48e60c62, 0x48935397, 0x48406e08, 0x47ed5be6,
+ 0x479a1d67, 0x4746b2bc,
+ 0x46f31c1a, 0x469f59b4, 0x464b6bbe, 0x45f7526b, 0x45a30df0, 0x454e9e80,
+ 0x44fa0450, 0x44a53f93,
+ 0x4450507e, 0x43fb3746, 0x43a5f41e, 0x4350873c, 0x42faf0d4, 0x42a5311b,
+ 0x424f4845, 0x41f93689,
+ 0x41a2fc1a, 0x414c992f, 0x40f60dfb, 0x409f5ab6, 0x40487f94, 0x3ff17cca,
+ 0x3f9a5290, 0x3f430119,
+ 0x3eeb889c, 0x3e93e950, 0x3e3c2369, 0x3de4371f, 0x3d8c24a8, 0x3d33ec39,
+ 0x3cdb8e09, 0x3c830a50,
+ 0x3c2a6142, 0x3bd19318, 0x3b78a007, 0x3b1f8848, 0x3ac64c0f, 0x3a6ceb96,
+ 0x3a136712, 0x39b9bebc,
+ 0x395ff2c9, 0x39060373, 0x38abf0ef, 0x3851bb77, 0x37f76341, 0x379ce885,
+ 0x37424b7b, 0x36e78c5b,
+ 0x368cab5c, 0x3631a8b8, 0x35d684a6, 0x357b3f5d, 0x351fd918, 0x34c4520d,
+ 0x3468aa76, 0x340ce28b,
+ 0x33b0fa84, 0x3354f29b, 0x32f8cb07, 0x329c8402, 0x32401dc6, 0x31e39889,
+ 0x3186f487, 0x312a31f8,
+ 0x30cd5115, 0x30705217, 0x30133539, 0x2fb5fab2, 0x2f58a2be, 0x2efb2d95,
+ 0x2e9d9b70, 0x2e3fec8b,
+ 0x2de2211e, 0x2d843964, 0x2d263596, 0x2cc815ee, 0x2c69daa6, 0x2c0b83fa,
+ 0x2bad1221, 0x2b4e8558,
+ 0x2aefddd8, 0x2a911bdc, 0x2a323f9e, 0x29d34958, 0x29743946, 0x29150fa1,
+ 0x28b5cca5, 0x2856708d,
+ 0x27f6fb92, 0x27976df1, 0x2737c7e3, 0x26d809a5, 0x26783370, 0x26184581,
+ 0x25b84012, 0x2558235f,
+ 0x24f7efa2, 0x2497a517, 0x243743fa, 0x23d6cc87, 0x23763ef7, 0x23159b88,
+ 0x22b4e274, 0x225413f8,
+ 0x21f3304f, 0x219237b5, 0x21312a65, 0x20d0089c, 0x206ed295, 0x200d888d,
+ 0x1fac2abf, 0x1f4ab968,
+ 0x1ee934c3, 0x1e879d0d, 0x1e25f282, 0x1dc4355e, 0x1d6265dd, 0x1d00843d,
+ 0x1c9e90b8, 0x1c3c8b8c,
+ 0x1bda74f6, 0x1b784d30, 0x1b161479, 0x1ab3cb0d, 0x1a517128, 0x19ef0707,
+ 0x198c8ce7, 0x192a0304,
+ 0x18c7699b, 0x1864c0ea, 0x1802092c, 0x179f429f, 0x173c6d80, 0x16d98a0c,
+ 0x1676987f, 0x16139918,
+ 0x15b08c12, 0x154d71aa, 0x14ea4a1f, 0x148715ae, 0x1423d492, 0x13c0870a,
+ 0x135d2d53, 0x12f9c7aa,
+ 0x1296564d, 0x1232d979, 0x11cf516a, 0x116bbe60, 0x11082096, 0x10a4784b,
+ 0x1040c5bb, 0xfdd0926,
+ 0xf7942c7, 0xf1572dc, 0xeb199a4, 0xe4db75b, 0xde9cc40, 0xd85d88f, 0xd21dc87,
+ 0xcbdd865,
+ 0xc59cc68, 0xbf5b8cb, 0xb919dcf, 0xb2d7baf, 0xac952aa, 0xa6522fe, 0xa00ece8,
+ 0x99cb0a7,
+ 0x9386e78, 0x8d42699, 0x86fd947, 0x80b86c2, 0x7a72f45, 0x742d311, 0x6de7262,
+ 0x67a0d76,
+ 0x615a48b, 0x5b137df, 0x54cc7b1, 0x4e8543e, 0x483ddc3, 0x41f6480, 0x3bae8b2,
+ 0x3566a96,
+ 0x2f1ea6c, 0x28d6870, 0x228e4e2, 0x1c45ffe, 0x15fda03, 0xfb5330, 0x96cbc1,
+ 0x3243f5,
+};
+
+static const q31_t cos_factorsQ31_2048[2048] = {
+ 0x7fffff62, 0x7ffffa73, 0x7ffff094, 0x7fffe1c6, 0x7fffce09, 0x7fffb55c,
+ 0x7fff97c1, 0x7fff7536,
+ 0x7fff4dbb, 0x7fff2151, 0x7ffeeff8, 0x7ffeb9b0, 0x7ffe7e79, 0x7ffe3e52,
+ 0x7ffdf93c, 0x7ffdaf37,
+ 0x7ffd6042, 0x7ffd0c5f, 0x7ffcb38c, 0x7ffc55ca, 0x7ffbf319, 0x7ffb8b78,
+ 0x7ffb1ee9, 0x7ffaad6a,
+ 0x7ffa36fc, 0x7ff9bba0, 0x7ff93b54, 0x7ff8b619, 0x7ff82bef, 0x7ff79cd6,
+ 0x7ff708ce, 0x7ff66fd7,
+ 0x7ff5d1f1, 0x7ff52f1d, 0x7ff48759, 0x7ff3daa6, 0x7ff32905, 0x7ff27275,
+ 0x7ff1b6f6, 0x7ff0f688,
+ 0x7ff0312c, 0x7fef66e1, 0x7fee97a7, 0x7fedc37e, 0x7fecea67, 0x7fec0c62,
+ 0x7feb296d, 0x7fea418b,
+ 0x7fe954ba, 0x7fe862fa, 0x7fe76c4c, 0x7fe670b0, 0x7fe57025, 0x7fe46aac,
+ 0x7fe36045, 0x7fe250ef,
+ 0x7fe13cac, 0x7fe0237a, 0x7fdf055a, 0x7fdde24d, 0x7fdcba51, 0x7fdb8d67,
+ 0x7fda5b8f, 0x7fd924ca,
+ 0x7fd7e917, 0x7fd6a875, 0x7fd562e7, 0x7fd4186a, 0x7fd2c900, 0x7fd174a8,
+ 0x7fd01b63, 0x7fcebd31,
+ 0x7fcd5a11, 0x7fcbf203, 0x7fca8508, 0x7fc91320, 0x7fc79c4b, 0x7fc62089,
+ 0x7fc49fda, 0x7fc31a3d,
+ 0x7fc18fb4, 0x7fc0003e, 0x7fbe6bdb, 0x7fbcd28b, 0x7fbb344e, 0x7fb99125,
+ 0x7fb7e90f, 0x7fb63c0d,
+ 0x7fb48a1e, 0x7fb2d343, 0x7fb1177b, 0x7faf56c7, 0x7fad9127, 0x7fabc69b,
+ 0x7fa9f723, 0x7fa822bf,
+ 0x7fa6496e, 0x7fa46b32, 0x7fa2880b, 0x7fa09ff7, 0x7f9eb2f8, 0x7f9cc10d,
+ 0x7f9aca37, 0x7f98ce76,
+ 0x7f96cdc9, 0x7f94c831, 0x7f92bdad, 0x7f90ae3f, 0x7f8e99e6, 0x7f8c80a1,
+ 0x7f8a6272, 0x7f883f58,
+ 0x7f861753, 0x7f83ea64, 0x7f81b88a, 0x7f7f81c6, 0x7f7d4617, 0x7f7b057e,
+ 0x7f78bffb, 0x7f76758e,
+ 0x7f742637, 0x7f71d1f6, 0x7f6f78cb, 0x7f6d1ab6, 0x7f6ab7b8, 0x7f684fd0,
+ 0x7f65e2ff, 0x7f637144,
+ 0x7f60faa0, 0x7f5e7f13, 0x7f5bfe9d, 0x7f59793e, 0x7f56eef5, 0x7f545fc5,
+ 0x7f51cbab, 0x7f4f32a9,
+ 0x7f4c94be, 0x7f49f1eb, 0x7f474a30, 0x7f449d8c, 0x7f41ec01, 0x7f3f358d,
+ 0x7f3c7a31, 0x7f39b9ee,
+ 0x7f36f4c3, 0x7f342ab1, 0x7f315bb7, 0x7f2e87d6, 0x7f2baf0d, 0x7f28d15d,
+ 0x7f25eec7, 0x7f230749,
+ 0x7f201ae5, 0x7f1d299a, 0x7f1a3368, 0x7f173850, 0x7f143852, 0x7f11336d,
+ 0x7f0e29a3, 0x7f0b1af2,
+ 0x7f08075c, 0x7f04eedf, 0x7f01d17d, 0x7efeaf36, 0x7efb8809, 0x7ef85bf7,
+ 0x7ef52b00, 0x7ef1f524,
+ 0x7eeeba62, 0x7eeb7abc, 0x7ee83632, 0x7ee4ecc3, 0x7ee19e6f, 0x7ede4b38,
+ 0x7edaf31c, 0x7ed7961c,
+ 0x7ed43438, 0x7ed0cd70, 0x7ecd61c5, 0x7ec9f137, 0x7ec67bc5, 0x7ec3016f,
+ 0x7ebf8237, 0x7ebbfe1c,
+ 0x7eb8751e, 0x7eb4e73d, 0x7eb1547a, 0x7eadbcd4, 0x7eaa204c, 0x7ea67ee2,
+ 0x7ea2d896, 0x7e9f2d68,
+ 0x7e9b7d58, 0x7e97c867, 0x7e940e94, 0x7e904fe0, 0x7e8c8c4b, 0x7e88c3d5,
+ 0x7e84f67e, 0x7e812447,
+ 0x7e7d4d2f, 0x7e797136, 0x7e75905d, 0x7e71aaa4, 0x7e6dc00c, 0x7e69d093,
+ 0x7e65dc3b, 0x7e61e303,
+ 0x7e5de4ec, 0x7e59e1f5, 0x7e55da20, 0x7e51cd6c, 0x7e4dbbd9, 0x7e49a567,
+ 0x7e458a17, 0x7e4169e9,
+ 0x7e3d44dd, 0x7e391af3, 0x7e34ec2b, 0x7e30b885, 0x7e2c8002, 0x7e2842a2,
+ 0x7e240064, 0x7e1fb94a,
+ 0x7e1b6d53, 0x7e171c7f, 0x7e12c6ce, 0x7e0e6c42, 0x7e0a0cd9, 0x7e05a894,
+ 0x7e013f74, 0x7dfcd178,
+ 0x7df85ea0, 0x7df3e6ee, 0x7def6a60, 0x7deae8f7, 0x7de662b3, 0x7de1d795,
+ 0x7ddd479d, 0x7dd8b2ca,
+ 0x7dd4191d, 0x7dcf7a96, 0x7dcad736, 0x7dc62efc, 0x7dc181e8, 0x7dbccffc,
+ 0x7db81936, 0x7db35d98,
+ 0x7dae9d21, 0x7da9d7d2, 0x7da50dab, 0x7da03eab, 0x7d9b6ad3, 0x7d969224,
+ 0x7d91b49e, 0x7d8cd240,
+ 0x7d87eb0a, 0x7d82fefe, 0x7d7e0e1c, 0x7d791862, 0x7d741dd2, 0x7d6f1e6c,
+ 0x7d6a1a31, 0x7d65111f,
+ 0x7d600338, 0x7d5af07b, 0x7d55d8e9, 0x7d50bc82, 0x7d4b9b46, 0x7d467536,
+ 0x7d414a51, 0x7d3c1a98,
+ 0x7d36e60b, 0x7d31acaa, 0x7d2c6e76, 0x7d272b6e, 0x7d21e393, 0x7d1c96e5,
+ 0x7d174564, 0x7d11ef11,
+ 0x7d0c93eb, 0x7d0733f3, 0x7d01cf29, 0x7cfc658d, 0x7cf6f720, 0x7cf183e1,
+ 0x7cec0bd1, 0x7ce68ef0,
+ 0x7ce10d3f, 0x7cdb86bd, 0x7cd5fb6a, 0x7cd06b48, 0x7ccad656, 0x7cc53c94,
+ 0x7cbf9e03, 0x7cb9faa2,
+ 0x7cb45272, 0x7caea574, 0x7ca8f3a7, 0x7ca33d0c, 0x7c9d81a3, 0x7c97c16b,
+ 0x7c91fc66, 0x7c8c3294,
+ 0x7c8663f4, 0x7c809088, 0x7c7ab84e, 0x7c74db48, 0x7c6ef976, 0x7c6912d7,
+ 0x7c63276d, 0x7c5d3737,
+ 0x7c574236, 0x7c514869, 0x7c4b49d2, 0x7c45466f, 0x7c3f3e42, 0x7c39314b,
+ 0x7c331f8a, 0x7c2d08ff,
+ 0x7c26edab, 0x7c20cd8d, 0x7c1aa8a6, 0x7c147ef6, 0x7c0e507e, 0x7c081d3d,
+ 0x7c01e534, 0x7bfba863,
+ 0x7bf566cb, 0x7bef206b, 0x7be8d544, 0x7be28556, 0x7bdc30a1, 0x7bd5d726,
+ 0x7bcf78e5, 0x7bc915dd,
+ 0x7bc2ae10, 0x7bbc417e, 0x7bb5d026, 0x7baf5a09, 0x7ba8df28, 0x7ba25f82,
+ 0x7b9bdb18, 0x7b9551ea,
+ 0x7b8ec3f8, 0x7b883143, 0x7b8199ca, 0x7b7afd8f, 0x7b745c91, 0x7b6db6d0,
+ 0x7b670c4d, 0x7b605d09,
+ 0x7b59a902, 0x7b52f03a, 0x7b4c32b1, 0x7b457068, 0x7b3ea95d, 0x7b37dd92,
+ 0x7b310d07, 0x7b2a37bc,
+ 0x7b235db2, 0x7b1c7ee8, 0x7b159b5f, 0x7b0eb318, 0x7b07c612, 0x7b00d44d,
+ 0x7af9ddcb, 0x7af2e28b,
+ 0x7aebe28d, 0x7ae4ddd2, 0x7addd45b, 0x7ad6c626, 0x7acfb336, 0x7ac89b89,
+ 0x7ac17f20, 0x7aba5dfc,
+ 0x7ab3381d, 0x7aac0d82, 0x7aa4de2d, 0x7a9daa1d, 0x7a967153, 0x7a8f33d0,
+ 0x7a87f192, 0x7a80aa9c,
+ 0x7a795eec, 0x7a720e84, 0x7a6ab963, 0x7a635f8a, 0x7a5c00f9, 0x7a549db0,
+ 0x7a4d35b0, 0x7a45c8f9,
+ 0x7a3e578b, 0x7a36e166, 0x7a2f668c, 0x7a27e6fb, 0x7a2062b5, 0x7a18d9b9,
+ 0x7a114c09, 0x7a09b9a4,
+ 0x7a02228a, 0x79fa86bc, 0x79f2e63a, 0x79eb4105, 0x79e3971c, 0x79dbe880,
+ 0x79d43532, 0x79cc7d31,
+ 0x79c4c07e, 0x79bcff19, 0x79b53903, 0x79ad6e3c, 0x79a59ec3, 0x799dca9a,
+ 0x7995f1c1, 0x798e1438,
+ 0x798631ff, 0x797e4b16, 0x79765f7f, 0x796e6f39, 0x79667a44, 0x795e80a1,
+ 0x79568250, 0x794e7f52,
+ 0x794677a6, 0x793e6b4e, 0x79365a49, 0x792e4497, 0x79262a3a, 0x791e0b31,
+ 0x7915e77c, 0x790dbf1d,
+ 0x79059212, 0x78fd605d, 0x78f529fe, 0x78eceef6, 0x78e4af44, 0x78dc6ae8,
+ 0x78d421e4, 0x78cbd437,
+ 0x78c381e2, 0x78bb2ae5, 0x78b2cf41, 0x78aa6ef5, 0x78a20a03, 0x7899a06a,
+ 0x7891322a, 0x7888bf45,
+ 0x788047ba, 0x7877cb89, 0x786f4ab4, 0x7866c53a, 0x785e3b1c, 0x7855ac5a,
+ 0x784d18f4, 0x784480ea,
+ 0x783be43e, 0x783342ef, 0x782a9cfe, 0x7821f26b, 0x78194336, 0x78108f60,
+ 0x7807d6e9, 0x77ff19d1,
+ 0x77f65819, 0x77ed91c0, 0x77e4c6c9, 0x77dbf732, 0x77d322fc, 0x77ca4a27,
+ 0x77c16cb4, 0x77b88aa3,
+ 0x77afa3f5, 0x77a6b8a9, 0x779dc8c0, 0x7794d43b, 0x778bdb19, 0x7782dd5c,
+ 0x7779db03, 0x7770d40f,
+ 0x7767c880, 0x775eb857, 0x7755a394, 0x774c8a36, 0x77436c40, 0x773a49b0,
+ 0x77312287, 0x7727f6c6,
+ 0x771ec66e, 0x7715917d, 0x770c57f5, 0x770319d6, 0x76f9d721, 0x76f08fd5,
+ 0x76e743f4, 0x76ddf37c,
+ 0x76d49e70, 0x76cb44cf, 0x76c1e699, 0x76b883d0, 0x76af1c72, 0x76a5b082,
+ 0x769c3ffe, 0x7692cae8,
+ 0x7689513f, 0x767fd304, 0x76765038, 0x766cc8db, 0x76633ced, 0x7659ac6f,
+ 0x76501760, 0x76467dc2,
+ 0x763cdf94, 0x76333cd8, 0x7629958c, 0x761fe9b3, 0x7616394c, 0x760c8457,
+ 0x7602cad5, 0x75f90cc7,
+ 0x75ef4a2c, 0x75e58305, 0x75dbb753, 0x75d1e715, 0x75c8124d, 0x75be38fa,
+ 0x75b45b1d, 0x75aa78b6,
+ 0x75a091c6, 0x7596a64d, 0x758cb64c, 0x7582c1c2, 0x7578c8b0, 0x756ecb18,
+ 0x7564c8f8, 0x755ac251,
+ 0x7550b725, 0x7546a772, 0x753c933a, 0x75327a7d, 0x75285d3b, 0x751e3b75,
+ 0x7514152b, 0x7509ea5d,
+ 0x74ffbb0d, 0x74f58739, 0x74eb4ee3, 0x74e1120c, 0x74d6d0b2, 0x74cc8ad8,
+ 0x74c2407d, 0x74b7f1a1,
+ 0x74ad9e46, 0x74a3466b, 0x7498ea11, 0x748e8938, 0x748423e0, 0x7479ba0b,
+ 0x746f4bb8, 0x7464d8e8,
+ 0x745a619b, 0x744fe5d2, 0x7445658d, 0x743ae0cc, 0x74305790, 0x7425c9da,
+ 0x741b37a9, 0x7410a0fe,
+ 0x740605d9, 0x73fb663c, 0x73f0c226, 0x73e61997, 0x73db6c91, 0x73d0bb13,
+ 0x73c6051f, 0x73bb4ab3,
+ 0x73b08bd1, 0x73a5c87a, 0x739b00ad, 0x7390346b, 0x738563b5, 0x737a8e8a,
+ 0x736fb4ec, 0x7364d6da,
+ 0x7359f456, 0x734f0d5f, 0x734421f6, 0x7339321b, 0x732e3dcf, 0x73234512,
+ 0x731847e5, 0x730d4648,
+ 0x7302403c, 0x72f735c0, 0x72ec26d6, 0x72e1137d, 0x72d5fbb7, 0x72cadf83,
+ 0x72bfbee3, 0x72b499d6,
+ 0x72a9705c, 0x729e4277, 0x72931027, 0x7287d96c, 0x727c9e47, 0x72715eb8,
+ 0x72661abf, 0x725ad25d,
+ 0x724f8593, 0x72443460, 0x7238dec5, 0x722d84c4, 0x7222265b, 0x7216c38c,
+ 0x720b5c57, 0x71fff0bc,
+ 0x71f480bc, 0x71e90c57, 0x71dd938f, 0x71d21662, 0x71c694d2, 0x71bb0edf,
+ 0x71af848a, 0x71a3f5d2,
+ 0x719862b9, 0x718ccb3f, 0x71812f65, 0x71758f29, 0x7169ea8f, 0x715e4194,
+ 0x7152943b, 0x7146e284,
+ 0x713b2c6e, 0x712f71fb, 0x7123b32b, 0x7117effe, 0x710c2875, 0x71005c90,
+ 0x70f48c50, 0x70e8b7b5,
+ 0x70dcdec0, 0x70d10171, 0x70c51fc8, 0x70b939c7, 0x70ad4f6d, 0x70a160ba,
+ 0x70956db1, 0x70897650,
+ 0x707d7a98, 0x70717a8a, 0x70657626, 0x70596d6d, 0x704d6060, 0x70414efd,
+ 0x70353947, 0x70291f3e,
+ 0x701d00e1, 0x7010de32, 0x7004b731, 0x6ff88bde, 0x6fec5c3b, 0x6fe02846,
+ 0x6fd3f001, 0x6fc7b36d,
+ 0x6fbb728a, 0x6faf2d57, 0x6fa2e3d7, 0x6f969608, 0x6f8a43ed, 0x6f7ded84,
+ 0x6f7192cf, 0x6f6533ce,
+ 0x6f58d082, 0x6f4c68eb, 0x6f3ffd09, 0x6f338cde, 0x6f271868, 0x6f1a9faa,
+ 0x6f0e22a3, 0x6f01a155,
+ 0x6ef51bbe, 0x6ee891e1, 0x6edc03bc, 0x6ecf7152, 0x6ec2daa2, 0x6eb63fad,
+ 0x6ea9a073, 0x6e9cfcf5,
+ 0x6e905534, 0x6e83a92f, 0x6e76f8e7, 0x6e6a445d, 0x6e5d8b91, 0x6e50ce84,
+ 0x6e440d37, 0x6e3747a9,
+ 0x6e2a7ddb, 0x6e1dafce, 0x6e10dd82, 0x6e0406f8, 0x6df72c30, 0x6dea4d2b,
+ 0x6ddd69e9, 0x6dd0826a,
+ 0x6dc396b0, 0x6db6a6ba, 0x6da9b28a, 0x6d9cba1f, 0x6d8fbd7a, 0x6d82bc9d,
+ 0x6d75b786, 0x6d68ae37,
+ 0x6d5ba0b0, 0x6d4e8ef2, 0x6d4178fd, 0x6d345ed1, 0x6d274070, 0x6d1a1dda,
+ 0x6d0cf70f, 0x6cffcc0f,
+ 0x6cf29cdc, 0x6ce56975, 0x6cd831dc, 0x6ccaf610, 0x6cbdb613, 0x6cb071e4,
+ 0x6ca32985, 0x6c95dcf6,
+ 0x6c888c36, 0x6c7b3748, 0x6c6dde2b, 0x6c6080e0, 0x6c531f67, 0x6c45b9c1,
+ 0x6c384fef, 0x6c2ae1f0,
+ 0x6c1d6fc6, 0x6c0ff971, 0x6c027ef1, 0x6bf50047, 0x6be77d74, 0x6bd9f677,
+ 0x6bcc6b53, 0x6bbedc06,
+ 0x6bb14892, 0x6ba3b0f7, 0x6b961536, 0x6b88754f, 0x6b7ad142, 0x6b6d2911,
+ 0x6b5f7cbc, 0x6b51cc42,
+ 0x6b4417a6, 0x6b365ee7, 0x6b28a206, 0x6b1ae103, 0x6b0d1bdf, 0x6aff529a,
+ 0x6af18536, 0x6ae3b3b2,
+ 0x6ad5de0f, 0x6ac8044e, 0x6aba266e, 0x6aac4472, 0x6a9e5e58, 0x6a907423,
+ 0x6a8285d1, 0x6a749365,
+ 0x6a669cdd, 0x6a58a23c, 0x6a4aa381, 0x6a3ca0ad, 0x6a2e99c0, 0x6a208ebb,
+ 0x6a127f9f, 0x6a046c6c,
+ 0x69f65523, 0x69e839c4, 0x69da1a50, 0x69cbf6c7, 0x69bdcf29, 0x69afa378,
+ 0x69a173b5, 0x69933fde,
+ 0x698507f6, 0x6976cbfc, 0x69688bf1, 0x695a47d6, 0x694bffab, 0x693db371,
+ 0x692f6328, 0x69210ed1,
+ 0x6912b66c, 0x690459fb, 0x68f5f97d, 0x68e794f3, 0x68d92c5d, 0x68cabfbd,
+ 0x68bc4f13, 0x68adda5f,
+ 0x689f61a1, 0x6890e4dc, 0x6882640e, 0x6873df38, 0x6865565c, 0x6856c979,
+ 0x68483891, 0x6839a3a4,
+ 0x682b0ab1, 0x681c6dbb, 0x680dccc1, 0x67ff27c4, 0x67f07ec5, 0x67e1d1c4,
+ 0x67d320c1, 0x67c46bbe,
+ 0x67b5b2bb, 0x67a6f5b8, 0x679834b6, 0x67896fb6, 0x677aa6b8, 0x676bd9bd,
+ 0x675d08c4, 0x674e33d0,
+ 0x673f5ae0, 0x67307df5, 0x67219d10, 0x6712b831, 0x6703cf58, 0x66f4e287,
+ 0x66e5f1be, 0x66d6fcfd,
+ 0x66c80445, 0x66b90797, 0x66aa06f3, 0x669b0259, 0x668bf9cb, 0x667ced49,
+ 0x666ddcd3, 0x665ec86b,
+ 0x664fb010, 0x664093c3, 0x66317385, 0x66224f56, 0x66132738, 0x6603fb2a,
+ 0x65f4cb2d, 0x65e59742,
+ 0x65d65f69, 0x65c723a3, 0x65b7e3f1, 0x65a8a052, 0x659958c9, 0x658a0d54,
+ 0x657abdf6, 0x656b6aae,
+ 0x655c137d, 0x654cb863, 0x653d5962, 0x652df679, 0x651e8faa, 0x650f24f5,
+ 0x64ffb65b, 0x64f043dc,
+ 0x64e0cd78, 0x64d15331, 0x64c1d507, 0x64b252fa, 0x64a2cd0c, 0x6493433c,
+ 0x6483b58c, 0x647423fb,
+ 0x64648e8c, 0x6454f53d, 0x64455810, 0x6435b706, 0x6426121e, 0x6416695a,
+ 0x6406bcba, 0x63f70c3f,
+ 0x63e757ea, 0x63d79fba, 0x63c7e3b1, 0x63b823cf, 0x63a86015, 0x63989884,
+ 0x6388cd1b, 0x6378fddc,
+ 0x63692ac7, 0x635953dd, 0x6349791f, 0x63399a8d, 0x6329b827, 0x6319d1ef,
+ 0x6309e7e4, 0x62f9fa09,
+ 0x62ea085c, 0x62da12df, 0x62ca1992, 0x62ba1c77, 0x62aa1b8d, 0x629a16d5,
+ 0x628a0e50, 0x627a01fe,
+ 0x6269f1e1, 0x6259ddf8, 0x6249c645, 0x6239aac7, 0x62298b81, 0x62196871,
+ 0x62094199, 0x61f916f9,
+ 0x61e8e893, 0x61d8b666, 0x61c88074, 0x61b846bc, 0x61a80940, 0x6197c800,
+ 0x618782fd, 0x61773a37,
+ 0x6166edb0, 0x61569d67, 0x6146495d, 0x6135f193, 0x6125960a, 0x611536c2,
+ 0x6104d3bc, 0x60f46cf9,
+ 0x60e40278, 0x60d3943b, 0x60c32243, 0x60b2ac8f, 0x60a23322, 0x6091b5fa,
+ 0x60813519, 0x6070b080,
+ 0x6060282f, 0x604f9c27, 0x603f0c69, 0x602e78f4, 0x601de1ca, 0x600d46ec,
+ 0x5ffca859, 0x5fec0613,
+ 0x5fdb601b, 0x5fcab670, 0x5fba0914, 0x5fa95807, 0x5f98a34a, 0x5f87eade,
+ 0x5f772ec2, 0x5f666ef9,
+ 0x5f55ab82, 0x5f44e45e, 0x5f34198e, 0x5f234b12, 0x5f1278eb, 0x5f01a31a,
+ 0x5ef0c99f, 0x5edfec7b,
+ 0x5ecf0baf, 0x5ebe273b, 0x5ead3f1f, 0x5e9c535e, 0x5e8b63f7, 0x5e7a70ea,
+ 0x5e697a39, 0x5e587fe5,
+ 0x5e4781ed, 0x5e368053, 0x5e257b17, 0x5e147239, 0x5e0365bb, 0x5df2559e,
+ 0x5de141e1, 0x5dd02a85,
+ 0x5dbf0f8c, 0x5dadf0f5, 0x5d9ccec2, 0x5d8ba8f3, 0x5d7a7f88, 0x5d695283,
+ 0x5d5821e4, 0x5d46edac,
+ 0x5d35b5db, 0x5d247a72, 0x5d133b72, 0x5d01f8dc, 0x5cf0b2af, 0x5cdf68ed,
+ 0x5cce1b97, 0x5cbccaac,
+ 0x5cab762f, 0x5c9a1e1e, 0x5c88c27c, 0x5c776348, 0x5c660084, 0x5c549a30,
+ 0x5c43304d, 0x5c31c2db,
+ 0x5c2051db, 0x5c0edd4e, 0x5bfd6534, 0x5bebe98e, 0x5bda6a5d, 0x5bc8e7a2,
+ 0x5bb7615d, 0x5ba5d78e,
+ 0x5b944a37, 0x5b82b958, 0x5b7124f2, 0x5b5f8d06, 0x5b4df193, 0x5b3c529c,
+ 0x5b2ab020, 0x5b190a20,
+ 0x5b07609d, 0x5af5b398, 0x5ae40311, 0x5ad24f09, 0x5ac09781, 0x5aaedc78,
+ 0x5a9d1df1, 0x5a8b5bec,
+ 0x5a799669, 0x5a67cd69, 0x5a5600ec, 0x5a4430f5, 0x5a325d82, 0x5a208695,
+ 0x5a0eac2e, 0x59fcce4f,
+ 0x59eaecf8, 0x59d90829, 0x59c71fe3, 0x59b53427, 0x59a344f6, 0x59915250,
+ 0x597f5c36, 0x596d62a9,
+ 0x595b65aa, 0x59496538, 0x59376155, 0x59255a02, 0x59134f3e, 0x5901410c,
+ 0x58ef2f6b, 0x58dd1a5d,
+ 0x58cb01e1, 0x58b8e5f9, 0x58a6c6a5, 0x5894a3e7, 0x58827dbe, 0x5870542c,
+ 0x585e2730, 0x584bf6cd,
+ 0x5839c302, 0x58278bd1, 0x58155139, 0x5803133c, 0x57f0d1da, 0x57de8d15,
+ 0x57cc44ec, 0x57b9f960,
+ 0x57a7aa73, 0x57955825, 0x57830276, 0x5770a968, 0x575e4cfa, 0x574bed2f,
+ 0x57398a05, 0x5727237f,
+ 0x5714b99d, 0x57024c5f, 0x56efdbc7, 0x56dd67d4, 0x56caf088, 0x56b875e4,
+ 0x56a5f7e7, 0x56937694,
+ 0x5680f1ea, 0x566e69ea, 0x565bde95, 0x56494fec, 0x5636bdef, 0x5624289f,
+ 0x56118ffe, 0x55fef40a,
+ 0x55ec54c6, 0x55d9b232, 0x55c70c4f, 0x55b4631d, 0x55a1b69d, 0x558f06d0,
+ 0x557c53b6, 0x55699d51,
+ 0x5556e3a1, 0x554426a7, 0x55316663, 0x551ea2d6, 0x550bdc01, 0x54f911e5,
+ 0x54e64482, 0x54d373d9,
+ 0x54c09feb, 0x54adc8b8, 0x549aee42, 0x54881089, 0x54752f8d, 0x54624b50,
+ 0x544f63d2, 0x543c7914,
+ 0x54298b17, 0x541699db, 0x5403a561, 0x53f0adaa, 0x53ddb2b6, 0x53cab486,
+ 0x53b7b31c, 0x53a4ae77,
+ 0x5391a699, 0x537e9b82, 0x536b8d33, 0x53587bad, 0x534566f0, 0x53324efd,
+ 0x531f33d5, 0x530c1579,
+ 0x52f8f3e9, 0x52e5cf27, 0x52d2a732, 0x52bf7c0b, 0x52ac4db4, 0x52991c2d,
+ 0x5285e777, 0x5272af92,
+ 0x525f7480, 0x524c3640, 0x5238f4d4, 0x5225b03d, 0x5212687b, 0x51ff1d8f,
+ 0x51ebcf7a, 0x51d87e3c,
+ 0x51c529d7, 0x51b1d24a, 0x519e7797, 0x518b19bf, 0x5177b8c2, 0x516454a0,
+ 0x5150ed5c, 0x513d82f4,
+ 0x512a156b, 0x5116a4c1, 0x510330f7, 0x50efba0d, 0x50dc4005, 0x50c8c2de,
+ 0x50b5429a, 0x50a1bf39,
+ 0x508e38bd, 0x507aaf25, 0x50672273, 0x505392a8, 0x503fffc4, 0x502c69c8,
+ 0x5018d0b4, 0x5005348a,
+ 0x4ff1954b, 0x4fddf2f6, 0x4fca4d8d, 0x4fb6a510, 0x4fa2f981, 0x4f8f4ae0,
+ 0x4f7b992d, 0x4f67e46a,
+ 0x4f542c98, 0x4f4071b6, 0x4f2cb3c7, 0x4f18f2c9, 0x4f052ec0, 0x4ef167aa,
+ 0x4edd9d89, 0x4ec9d05e,
+ 0x4eb60029, 0x4ea22ceb, 0x4e8e56a5, 0x4e7a7d58, 0x4e66a105, 0x4e52c1ab,
+ 0x4e3edf4d, 0x4e2af9ea,
+ 0x4e171184, 0x4e03261b, 0x4def37b0, 0x4ddb4644, 0x4dc751d8, 0x4db35a6c,
+ 0x4d9f6001, 0x4d8b6298,
+ 0x4d776231, 0x4d635ece, 0x4d4f5870, 0x4d3b4f16, 0x4d2742c2, 0x4d133374,
+ 0x4cff212e, 0x4ceb0bf0,
+ 0x4cd6f3bb, 0x4cc2d88f, 0x4caeba6e, 0x4c9a9958, 0x4c86754e, 0x4c724e50,
+ 0x4c5e2460, 0x4c49f77f,
+ 0x4c35c7ac, 0x4c2194e9, 0x4c0d5f37, 0x4bf92697, 0x4be4eb08, 0x4bd0ac8d,
+ 0x4bbc6b25, 0x4ba826d1,
+ 0x4b93df93, 0x4b7f956b, 0x4b6b485a, 0x4b56f861, 0x4b42a580, 0x4b2e4fb8,
+ 0x4b19f70a, 0x4b059b77,
+ 0x4af13d00, 0x4adcdba5, 0x4ac87767, 0x4ab41046, 0x4a9fa645, 0x4a8b3963,
+ 0x4a76c9a2, 0x4a625701,
+ 0x4a4de182, 0x4a396926, 0x4a24edee, 0x4a106fda, 0x49fbeeea, 0x49e76b21,
+ 0x49d2e47e, 0x49be5b02,
+ 0x49a9ceaf, 0x49953f84, 0x4980ad84, 0x496c18ae, 0x49578103, 0x4942e684,
+ 0x492e4933, 0x4919a90f,
+ 0x4905061a, 0x48f06054, 0x48dbb7be, 0x48c70c59, 0x48b25e25, 0x489dad25,
+ 0x4888f957, 0x487442be,
+ 0x485f8959, 0x484acd2a, 0x48360e32, 0x48214c71, 0x480c87e8, 0x47f7c099,
+ 0x47e2f682, 0x47ce29a7,
+ 0x47b95a06, 0x47a487a2, 0x478fb27b, 0x477ada91, 0x4765ffe6, 0x4751227a,
+ 0x473c424e, 0x47275f63,
+ 0x471279ba, 0x46fd9154, 0x46e8a631, 0x46d3b852, 0x46bec7b8, 0x46a9d464,
+ 0x4694de56, 0x467fe590,
+ 0x466aea12, 0x4655ebdd, 0x4640eaf2, 0x462be751, 0x4616e0fc, 0x4601d7f3,
+ 0x45eccc37, 0x45d7bdc9,
+ 0x45c2acaa, 0x45ad98da, 0x4598825a, 0x4583692c, 0x456e4d4f, 0x45592ec6,
+ 0x45440d90, 0x452ee9ae,
+ 0x4519c321, 0x450499eb, 0x44ef6e0b, 0x44da3f83, 0x44c50e53, 0x44afda7d,
+ 0x449aa400, 0x44856adf,
+ 0x44702f19, 0x445af0b0, 0x4445afa4, 0x44306bf6, 0x441b25a8, 0x4405dcb9,
+ 0x43f0912b, 0x43db42fe,
+ 0x43c5f234, 0x43b09ecc, 0x439b48c9, 0x4385f02a, 0x437094f1, 0x435b371f,
+ 0x4345d6b3, 0x433073b0,
+ 0x431b0e15, 0x4305a5e5, 0x42f03b1e, 0x42dacdc3, 0x42c55dd4, 0x42afeb53,
+ 0x429a763f, 0x4284fe99,
+ 0x426f8463, 0x425a079e, 0x42448849, 0x422f0667, 0x421981f7, 0x4203fafb,
+ 0x41ee7174, 0x41d8e561,
+ 0x41c356c5, 0x41adc5a0, 0x419831f3, 0x41829bbe, 0x416d0302, 0x415767c1,
+ 0x4141c9fb, 0x412c29b1,
+ 0x411686e4, 0x4100e194, 0x40eb39c3, 0x40d58f71, 0x40bfe29f, 0x40aa334e,
+ 0x4094817f, 0x407ecd32,
+ 0x40691669, 0x40535d24, 0x403da165, 0x4027e32b, 0x40122278, 0x3ffc5f4d,
+ 0x3fe699aa, 0x3fd0d191,
+ 0x3fbb0702, 0x3fa539fd, 0x3f8f6a85, 0x3f799899, 0x3f63c43b, 0x3f4ded6b,
+ 0x3f38142a, 0x3f22387a,
+ 0x3f0c5a5a, 0x3ef679cc, 0x3ee096d1, 0x3ecab169, 0x3eb4c995, 0x3e9edf57,
+ 0x3e88f2ae, 0x3e73039d,
+ 0x3e5d1222, 0x3e471e41, 0x3e3127f9, 0x3e1b2f4a, 0x3e053437, 0x3def36c0,
+ 0x3dd936e6, 0x3dc334a9,
+ 0x3dad300b, 0x3d97290b, 0x3d811fac, 0x3d6b13ee, 0x3d5505d2, 0x3d3ef559,
+ 0x3d28e282, 0x3d12cd51,
+ 0x3cfcb5c4, 0x3ce69bde, 0x3cd07f9f, 0x3cba6107, 0x3ca44018, 0x3c8e1cd3,
+ 0x3c77f737, 0x3c61cf48,
+ 0x3c4ba504, 0x3c35786d, 0x3c1f4983, 0x3c091849, 0x3bf2e4be, 0x3bdcaee3,
+ 0x3bc676b9, 0x3bb03c42,
+ 0x3b99ff7d, 0x3b83c06c, 0x3b6d7f10, 0x3b573b69, 0x3b40f579, 0x3b2aad3f,
+ 0x3b1462be, 0x3afe15f6,
+ 0x3ae7c6e7, 0x3ad17593, 0x3abb21fb, 0x3aa4cc1e, 0x3a8e7400, 0x3a78199f,
+ 0x3a61bcfd, 0x3a4b5e1b,
+ 0x3a34fcf9, 0x3a1e9999, 0x3a0833fc, 0x39f1cc21, 0x39db620b, 0x39c4f5ba,
+ 0x39ae872f, 0x3998166a,
+ 0x3981a36d, 0x396b2e38, 0x3954b6cd, 0x393e3d2c, 0x3927c155, 0x3911434b,
+ 0x38fac30e, 0x38e4409e,
+ 0x38cdbbfc, 0x38b7352a, 0x38a0ac29, 0x388a20f8, 0x38739399, 0x385d040d,
+ 0x38467255, 0x382fde72,
+ 0x38194864, 0x3802b02c, 0x37ec15cb, 0x37d57943, 0x37beda93, 0x37a839be,
+ 0x379196c3, 0x377af1a3,
+ 0x37644a60, 0x374da0fa, 0x3736f573, 0x372047ca, 0x37099802, 0x36f2e61a,
+ 0x36dc3214, 0x36c57bf0,
+ 0x36aec3b0, 0x36980954, 0x36814cde, 0x366a8e4d, 0x3653cda3, 0x363d0ae2,
+ 0x36264609, 0x360f7f19,
+ 0x35f8b614, 0x35e1eafa, 0x35cb1dcc, 0x35b44e8c, 0x359d7d39, 0x3586a9d5,
+ 0x356fd461, 0x3558fcde,
+ 0x3542234c, 0x352b47ad, 0x35146a00, 0x34fd8a48, 0x34e6a885, 0x34cfc4b7,
+ 0x34b8dee1, 0x34a1f702,
+ 0x348b0d1c, 0x3474212f, 0x345d333c, 0x34464345, 0x342f5149, 0x34185d4b,
+ 0x3401674a, 0x33ea6f48,
+ 0x33d37546, 0x33bc7944, 0x33a57b44, 0x338e7b46, 0x3377794b, 0x33607554,
+ 0x33496f62, 0x33326776,
+ 0x331b5d91, 0x330451b3, 0x32ed43de, 0x32d63412, 0x32bf2250, 0x32a80e99,
+ 0x3290f8ef, 0x3279e151,
+ 0x3262c7c1, 0x324bac40, 0x32348ecf, 0x321d6f6e, 0x32064e1e, 0x31ef2ae1,
+ 0x31d805b7, 0x31c0dea1,
+ 0x31a9b5a0, 0x31928ab4, 0x317b5de0, 0x31642f23, 0x314cfe7f, 0x3135cbf4,
+ 0x311e9783, 0x3107612e,
+ 0x30f028f4, 0x30d8eed8, 0x30c1b2da, 0x30aa74fa, 0x3093353a, 0x307bf39b,
+ 0x3064b01d, 0x304d6ac1,
+ 0x30362389, 0x301eda75, 0x30078f86, 0x2ff042bd, 0x2fd8f41b, 0x2fc1a3a0,
+ 0x2faa514f, 0x2f92fd26,
+ 0x2f7ba729, 0x2f644f56, 0x2f4cf5b0, 0x2f359a37, 0x2f1e3ced, 0x2f06ddd1,
+ 0x2eef7ce5, 0x2ed81a29,
+ 0x2ec0b5a0, 0x2ea94f49, 0x2e91e725, 0x2e7a7d36, 0x2e63117c, 0x2e4ba3f8,
+ 0x2e3434ac, 0x2e1cc397,
+ 0x2e0550bb, 0x2deddc19, 0x2dd665b2, 0x2dbeed86, 0x2da77397, 0x2d8ff7e5,
+ 0x2d787a72, 0x2d60fb3e,
+ 0x2d497a4a, 0x2d31f797, 0x2d1a7325, 0x2d02ecf7, 0x2ceb650d, 0x2cd3db67,
+ 0x2cbc5006, 0x2ca4c2ed,
+ 0x2c8d341a, 0x2c75a390, 0x2c5e114f, 0x2c467d58, 0x2c2ee7ad, 0x2c17504d,
+ 0x2bffb73a, 0x2be81c74,
+ 0x2bd07ffe, 0x2bb8e1d7, 0x2ba14200, 0x2b89a07b, 0x2b71fd48, 0x2b5a5868,
+ 0x2b42b1dd, 0x2b2b09a6,
+ 0x2b135fc6, 0x2afbb43c, 0x2ae4070a, 0x2acc5831, 0x2ab4a7b1, 0x2a9cf58c,
+ 0x2a8541c3, 0x2a6d8c55,
+ 0x2a55d545, 0x2a3e1c93, 0x2a266240, 0x2a0ea64d, 0x29f6e8bb, 0x29df298b,
+ 0x29c768be, 0x29afa654,
+ 0x2997e24f, 0x29801caf, 0x29685576, 0x29508ca4, 0x2938c23a, 0x2920f63a,
+ 0x290928a3, 0x28f15978,
+ 0x28d988b8, 0x28c1b666, 0x28a9e281, 0x28920d0a, 0x287a3604, 0x28625d6d,
+ 0x284a8349, 0x2832a796,
+ 0x281aca57, 0x2802eb8c, 0x27eb0b36, 0x27d32956, 0x27bb45ed, 0x27a360fc,
+ 0x278b7a84, 0x27739285,
+ 0x275ba901, 0x2743bdf9, 0x272bd16d, 0x2713e35f, 0x26fbf3ce, 0x26e402bd,
+ 0x26cc102d, 0x26b41c1d,
+ 0x269c268f, 0x26842f84, 0x266c36fe, 0x26543cfb, 0x263c417f, 0x26244489,
+ 0x260c461b, 0x25f44635,
+ 0x25dc44d9, 0x25c44207, 0x25ac3dc0, 0x25943806, 0x257c30d8, 0x25642839,
+ 0x254c1e28, 0x253412a8,
+ 0x251c05b8, 0x2503f75a, 0x24ebe78f, 0x24d3d657, 0x24bbc3b4, 0x24a3afa6,
+ 0x248b9a2f, 0x2473834f,
+ 0x245b6b07, 0x24435158, 0x242b3644, 0x241319ca, 0x23fafbec, 0x23e2dcac,
+ 0x23cabc09, 0x23b29a05,
+ 0x239a76a0, 0x238251dd, 0x236a2bba, 0x2352043b, 0x2339db5e, 0x2321b126,
+ 0x23098593, 0x22f158a7,
+ 0x22d92a61, 0x22c0fac4, 0x22a8c9cf, 0x22909785, 0x227863e5, 0x22602ef1,
+ 0x2247f8aa, 0x222fc111,
+ 0x22178826, 0x21ff4dea, 0x21e71260, 0x21ced586, 0x21b6975f, 0x219e57eb,
+ 0x2186172b, 0x216dd521,
+ 0x215591cc, 0x213d4d2f, 0x21250749, 0x210cc01d, 0x20f477aa, 0x20dc2df2,
+ 0x20c3e2f5, 0x20ab96b5,
+ 0x20934933, 0x207afa6f, 0x2062aa6b, 0x204a5927, 0x203206a4, 0x2019b2e4,
+ 0x20015de7, 0x1fe907ae,
+ 0x1fd0b03a, 0x1fb8578b, 0x1f9ffda4, 0x1f87a285, 0x1f6f462f, 0x1f56e8a2,
+ 0x1f3e89e0, 0x1f2629ea,
+ 0x1f0dc8c0, 0x1ef56664, 0x1edd02d6, 0x1ec49e17, 0x1eac3829, 0x1e93d10c,
+ 0x1e7b68c2, 0x1e62ff4a,
+ 0x1e4a94a7, 0x1e3228d9, 0x1e19bbe0, 0x1e014dbf, 0x1de8de75, 0x1dd06e04,
+ 0x1db7fc6d, 0x1d9f89b1,
+ 0x1d8715d0, 0x1d6ea0cc, 0x1d562aa6, 0x1d3db35e, 0x1d253af5, 0x1d0cc16c,
+ 0x1cf446c5, 0x1cdbcb00,
+ 0x1cc34e1f, 0x1caad021, 0x1c925109, 0x1c79d0d6, 0x1c614f8b, 0x1c48cd27,
+ 0x1c3049ac, 0x1c17c51b,
+ 0x1bff3f75, 0x1be6b8ba, 0x1bce30ec, 0x1bb5a80c, 0x1b9d1e1a, 0x1b849317,
+ 0x1b6c0705, 0x1b5379e5,
+ 0x1b3aebb6, 0x1b225c7b, 0x1b09cc34, 0x1af13ae3, 0x1ad8a887, 0x1ac01522,
+ 0x1aa780b6, 0x1a8eeb42,
+ 0x1a7654c8, 0x1a5dbd49, 0x1a4524c6, 0x1a2c8b3f, 0x1a13f0b6, 0x19fb552c,
+ 0x19e2b8a2, 0x19ca1b17,
+ 0x19b17c8f, 0x1998dd09, 0x19803c86, 0x19679b07, 0x194ef88e, 0x1936551b,
+ 0x191db0af, 0x19050b4b,
+ 0x18ec64f0, 0x18d3bda0, 0x18bb155a, 0x18a26c20, 0x1889c1f3, 0x187116d4,
+ 0x18586ac3, 0x183fbdc3,
+ 0x18270fd3, 0x180e60f4, 0x17f5b129, 0x17dd0070, 0x17c44ecd, 0x17ab9c3e,
+ 0x1792e8c6, 0x177a3466,
+ 0x17617f1d, 0x1748c8ee, 0x173011d9, 0x171759df, 0x16fea102, 0x16e5e741,
+ 0x16cd2c9f, 0x16b4711b,
+ 0x169bb4b7, 0x1682f774, 0x166a3953, 0x16517a55, 0x1638ba7a, 0x161ff9c4,
+ 0x16073834, 0x15ee75cb,
+ 0x15d5b288, 0x15bcee6f, 0x15a4297f, 0x158b63b9, 0x15729d1f, 0x1559d5b1,
+ 0x15410d70, 0x1528445d,
+ 0x150f7a7a, 0x14f6afc7, 0x14dde445, 0x14c517f4, 0x14ac4ad7, 0x14937cee,
+ 0x147aae3a, 0x1461debc,
+ 0x14490e74, 0x14303d65, 0x14176b8e, 0x13fe98f1, 0x13e5c58e, 0x13ccf167,
+ 0x13b41c7d, 0x139b46d0,
+ 0x13827062, 0x13699933, 0x1350c144, 0x1337e897, 0x131f0f2c, 0x13063505,
+ 0x12ed5a21, 0x12d47e83,
+ 0x12bba22b, 0x12a2c51b, 0x1289e752, 0x127108d2, 0x1258299c, 0x123f49b2,
+ 0x12266913, 0x120d87c1,
+ 0x11f4a5bd, 0x11dbc307, 0x11c2dfa2, 0x11a9fb8d, 0x119116c9, 0x11783159,
+ 0x115f4b3c, 0x11466473,
+ 0x112d7d00, 0x111494e4, 0x10fbac1e, 0x10e2c2b2, 0x10c9d89e, 0x10b0ede5,
+ 0x10980287, 0x107f1686,
+ 0x106629e1, 0x104d3c9b, 0x10344eb4, 0x101b602d, 0x10027107, 0xfe98143,
+ 0xfd090e1, 0xfb79fe4,
+ 0xf9eae4c, 0xf85bc19, 0xf6cc94e, 0xf53d5ea, 0xf3ae1ee, 0xf21ed5d, 0xf08f836,
+ 0xef0027b,
+ 0xed70c2c, 0xebe154b, 0xea51dd8, 0xe8c25d5, 0xe732d42, 0xe5a3421, 0xe413a72,
+ 0xe284036,
+ 0xe0f456f, 0xdf64a1c, 0xddd4e40, 0xdc451dc, 0xdab54ef, 0xd92577b, 0xd795982,
+ 0xd605b03,
+ 0xd475c00, 0xd2e5c7b, 0xd155c73, 0xcfc5bea, 0xce35ae1, 0xcca5959, 0xcb15752,
+ 0xc9854cf,
+ 0xc7f51cf, 0xc664e53, 0xc4d4a5d, 0xc3445ee, 0xc1b4107, 0xc023ba7, 0xbe935d2,
+ 0xbd02f87,
+ 0xbb728c7, 0xb9e2193, 0xb8519ed, 0xb6c11d5, 0xb53094d, 0xb3a0055, 0xb20f6ee,
+ 0xb07ed19,
+ 0xaeee2d7, 0xad5d829, 0xabccd11, 0xaa3c18e, 0xa8ab5a2, 0xa71a94f, 0xa589c94,
+ 0xa3f8f73,
+ 0xa2681ed, 0xa0d7403, 0x9f465b5, 0x9db5706, 0x9c247f5, 0x9a93884, 0x99028b3,
+ 0x9771884,
+ 0x95e07f8, 0x944f70f, 0x92be5ca, 0x912d42c, 0x8f9c233, 0x8e0afe2, 0x8c79d3a,
+ 0x8ae8a3a,
+ 0x89576e5, 0x87c633c, 0x8634f3e, 0x84a3aee, 0x831264c, 0x8181159, 0x7fefc16,
+ 0x7e5e685,
+ 0x7ccd0a5, 0x7b3ba78, 0x79aa400, 0x7818d3c, 0x768762e, 0x74f5ed7, 0x7364738,
+ 0x71d2f52,
+ 0x7041726, 0x6eafeb4, 0x6d1e5fe, 0x6b8cd05, 0x69fb3c9, 0x6869a4c, 0x66d808f,
+ 0x6546692,
+ 0x63b4c57, 0x62231de, 0x6091729, 0x5effc38, 0x5d6e10c, 0x5bdc5a7, 0x5a4aa09,
+ 0x58b8e34,
+ 0x5727228, 0x55955e6, 0x540396f, 0x5271cc4, 0x50dffe7, 0x4f4e2d8, 0x4dbc597,
+ 0x4c2a827,
+ 0x4a98a88, 0x4906cbb, 0x4774ec1, 0x45e309a, 0x4451249, 0x42bf3cd, 0x412d528,
+ 0x3f9b65b,
+ 0x3e09767, 0x3c7784d, 0x3ae590d, 0x39539a9, 0x37c1a22, 0x362fa78, 0x349daac,
+ 0x330bac1,
+ 0x3179ab5, 0x2fe7a8c, 0x2e55a44, 0x2cc39e1, 0x2b31961, 0x299f8c7, 0x280d813,
+ 0x267b747,
+ 0x24e9662, 0x2357567, 0x21c5457, 0x2033331, 0x1ea11f7, 0x1d0f0ab, 0x1b7cf4d,
+ 0x19eaddd,
+ 0x1858c5e, 0x16c6ad0, 0x1534934, 0x13a278a, 0x12105d5, 0x107e414, 0xeec249,
+ 0xd5a075,
+ 0xbc7e99, 0xa35cb5, 0x8a3acb, 0x7118dc, 0x57f6e9, 0x3ed4f2, 0x25b2f8,
+ 0xc90fe,
+
+};
+
+static const q31_t cos_factorsQ31_8192[8192] = {
+ 0x7ffffff6, 0x7fffffa7, 0x7fffff09, 0x7ffffe1c, 0x7ffffce1, 0x7ffffb56,
+ 0x7ffff97c, 0x7ffff753,
+ 0x7ffff4dc, 0x7ffff215, 0x7fffef00, 0x7fffeb9b, 0x7fffe7e8, 0x7fffe3e5,
+ 0x7fffdf94, 0x7fffdaf3,
+ 0x7fffd604, 0x7fffd0c6, 0x7fffcb39, 0x7fffc55c, 0x7fffbf31, 0x7fffb8b7,
+ 0x7fffb1ee, 0x7fffaad6,
+ 0x7fffa36f, 0x7fff9bb9, 0x7fff93b4, 0x7fff8b61, 0x7fff82be, 0x7fff79cc,
+ 0x7fff708b, 0x7fff66fc,
+ 0x7fff5d1d, 0x7fff52ef, 0x7fff4873, 0x7fff3da8, 0x7fff328d, 0x7fff2724,
+ 0x7fff1b6b, 0x7fff0f64,
+ 0x7fff030e, 0x7ffef669, 0x7ffee975, 0x7ffedc31, 0x7ffece9f, 0x7ffec0be,
+ 0x7ffeb28e, 0x7ffea40f,
+ 0x7ffe9542, 0x7ffe8625, 0x7ffe76b9, 0x7ffe66fe, 0x7ffe56f5, 0x7ffe469c,
+ 0x7ffe35f4, 0x7ffe24fe,
+ 0x7ffe13b8, 0x7ffe0224, 0x7ffdf040, 0x7ffdde0e, 0x7ffdcb8d, 0x7ffdb8bc,
+ 0x7ffda59d, 0x7ffd922f,
+ 0x7ffd7e72, 0x7ffd6a66, 0x7ffd560b, 0x7ffd4161, 0x7ffd2c68, 0x7ffd1720,
+ 0x7ffd0189, 0x7ffceba4,
+ 0x7ffcd56f, 0x7ffcbeeb, 0x7ffca819, 0x7ffc90f7, 0x7ffc7987, 0x7ffc61c7,
+ 0x7ffc49b9, 0x7ffc315b,
+ 0x7ffc18af, 0x7ffbffb4, 0x7ffbe66a, 0x7ffbccd0, 0x7ffbb2e8, 0x7ffb98b1,
+ 0x7ffb7e2b, 0x7ffb6356,
+ 0x7ffb4833, 0x7ffb2cc0, 0x7ffb10fe, 0x7ffaf4ed, 0x7ffad88e, 0x7ffabbdf,
+ 0x7ffa9ee2, 0x7ffa8195,
+ 0x7ffa63fa, 0x7ffa460f, 0x7ffa27d6, 0x7ffa094e, 0x7ff9ea76, 0x7ff9cb50,
+ 0x7ff9abdb, 0x7ff98c17,
+ 0x7ff96c04, 0x7ff94ba2, 0x7ff92af1, 0x7ff909f2, 0x7ff8e8a3, 0x7ff8c705,
+ 0x7ff8a519, 0x7ff882dd,
+ 0x7ff86053, 0x7ff83d79, 0x7ff81a51, 0x7ff7f6da, 0x7ff7d313, 0x7ff7aefe,
+ 0x7ff78a9a, 0x7ff765e7,
+ 0x7ff740e5, 0x7ff71b94, 0x7ff6f5f4, 0x7ff6d005, 0x7ff6a9c8, 0x7ff6833b,
+ 0x7ff65c5f, 0x7ff63535,
+ 0x7ff60dbb, 0x7ff5e5f3, 0x7ff5bddc, 0x7ff59576, 0x7ff56cc0, 0x7ff543bc,
+ 0x7ff51a69, 0x7ff4f0c7,
+ 0x7ff4c6d6, 0x7ff49c96, 0x7ff47208, 0x7ff4472a, 0x7ff41bfd, 0x7ff3f082,
+ 0x7ff3c4b7, 0x7ff3989e,
+ 0x7ff36c36, 0x7ff33f7e, 0x7ff31278, 0x7ff2e523, 0x7ff2b77f, 0x7ff2898c,
+ 0x7ff25b4a, 0x7ff22cb9,
+ 0x7ff1fdd9, 0x7ff1ceab, 0x7ff19f2d, 0x7ff16f61, 0x7ff13f45, 0x7ff10edb,
+ 0x7ff0de22, 0x7ff0ad19,
+ 0x7ff07bc2, 0x7ff04a1c, 0x7ff01827, 0x7fefe5e4, 0x7fefb351, 0x7fef806f,
+ 0x7fef4d3e, 0x7fef19bf,
+ 0x7feee5f0, 0x7feeb1d3, 0x7fee7d67, 0x7fee48ac, 0x7fee13a1, 0x7fedde48,
+ 0x7feda8a0, 0x7fed72aa,
+ 0x7fed3c64, 0x7fed05cf, 0x7fecceec, 0x7fec97b9, 0x7fec6038, 0x7fec2867,
+ 0x7febf048, 0x7febb7da,
+ 0x7feb7f1d, 0x7feb4611, 0x7feb0cb6, 0x7fead30c, 0x7fea9914, 0x7fea5ecc,
+ 0x7fea2436, 0x7fe9e950,
+ 0x7fe9ae1c, 0x7fe97299, 0x7fe936c7, 0x7fe8faa6, 0x7fe8be36, 0x7fe88177,
+ 0x7fe84469, 0x7fe8070d,
+ 0x7fe7c961, 0x7fe78b67, 0x7fe74d1e, 0x7fe70e85, 0x7fe6cf9e, 0x7fe69068,
+ 0x7fe650e3, 0x7fe61110,
+ 0x7fe5d0ed, 0x7fe5907b, 0x7fe54fbb, 0x7fe50eac, 0x7fe4cd4d, 0x7fe48ba0,
+ 0x7fe449a4, 0x7fe40759,
+ 0x7fe3c4bf, 0x7fe381d7, 0x7fe33e9f, 0x7fe2fb19, 0x7fe2b743, 0x7fe2731f,
+ 0x7fe22eac, 0x7fe1e9ea,
+ 0x7fe1a4d9, 0x7fe15f79, 0x7fe119cb, 0x7fe0d3cd, 0x7fe08d81, 0x7fe046e5,
+ 0x7fdffffb, 0x7fdfb8c2,
+ 0x7fdf713a, 0x7fdf2963, 0x7fdee13e, 0x7fde98c9, 0x7fde5006, 0x7fde06f3,
+ 0x7fddbd92, 0x7fdd73e2,
+ 0x7fdd29e3, 0x7fdcdf95, 0x7fdc94f9, 0x7fdc4a0d, 0x7fdbfed3, 0x7fdbb349,
+ 0x7fdb6771, 0x7fdb1b4a,
+ 0x7fdaced4, 0x7fda820f, 0x7fda34fc, 0x7fd9e799, 0x7fd999e8, 0x7fd94be8,
+ 0x7fd8fd98, 0x7fd8aefa,
+ 0x7fd8600e, 0x7fd810d2, 0x7fd7c147, 0x7fd7716e, 0x7fd72146, 0x7fd6d0cf,
+ 0x7fd68009, 0x7fd62ef4,
+ 0x7fd5dd90, 0x7fd58bdd, 0x7fd539dc, 0x7fd4e78c, 0x7fd494ed, 0x7fd441ff,
+ 0x7fd3eec2, 0x7fd39b36,
+ 0x7fd3475c, 0x7fd2f332, 0x7fd29eba, 0x7fd249f3, 0x7fd1f4dd, 0x7fd19f78,
+ 0x7fd149c5, 0x7fd0f3c2,
+ 0x7fd09d71, 0x7fd046d1, 0x7fcfefe2, 0x7fcf98a4, 0x7fcf4117, 0x7fcee93c,
+ 0x7fce9112, 0x7fce3898,
+ 0x7fcddfd0, 0x7fcd86b9, 0x7fcd2d54, 0x7fccd39f, 0x7fcc799c, 0x7fcc1f4a,
+ 0x7fcbc4a9, 0x7fcb69b9,
+ 0x7fcb0e7a, 0x7fcab2ed, 0x7fca5710, 0x7fc9fae5, 0x7fc99e6b, 0x7fc941a2,
+ 0x7fc8e48b, 0x7fc88724,
+ 0x7fc8296f, 0x7fc7cb6b, 0x7fc76d18, 0x7fc70e76, 0x7fc6af86, 0x7fc65046,
+ 0x7fc5f0b8, 0x7fc590db,
+ 0x7fc530af, 0x7fc4d035, 0x7fc46f6b, 0x7fc40e53, 0x7fc3acec, 0x7fc34b36,
+ 0x7fc2e931, 0x7fc286de,
+ 0x7fc2243b, 0x7fc1c14a, 0x7fc15e0a, 0x7fc0fa7b, 0x7fc0969e, 0x7fc03271,
+ 0x7fbfcdf6, 0x7fbf692c,
+ 0x7fbf0414, 0x7fbe9eac, 0x7fbe38f6, 0x7fbdd2f0, 0x7fbd6c9c, 0x7fbd05fa,
+ 0x7fbc9f08, 0x7fbc37c8,
+ 0x7fbbd039, 0x7fbb685b, 0x7fbb002e, 0x7fba97b2, 0x7fba2ee8, 0x7fb9c5cf,
+ 0x7fb95c67, 0x7fb8f2b0,
+ 0x7fb888ab, 0x7fb81e57, 0x7fb7b3b4, 0x7fb748c2, 0x7fb6dd81, 0x7fb671f2,
+ 0x7fb60614, 0x7fb599e7,
+ 0x7fb52d6b, 0x7fb4c0a1, 0x7fb45387, 0x7fb3e61f, 0x7fb37869, 0x7fb30a63,
+ 0x7fb29c0f, 0x7fb22d6c,
+ 0x7fb1be7a, 0x7fb14f39, 0x7fb0dfaa, 0x7fb06fcb, 0x7fafff9e, 0x7faf8f23,
+ 0x7faf1e58, 0x7faead3f,
+ 0x7fae3bd7, 0x7fadca20, 0x7fad581b, 0x7face5c6, 0x7fac7323, 0x7fac0031,
+ 0x7fab8cf1, 0x7fab1962,
+ 0x7faaa584, 0x7faa3157, 0x7fa9bcdb, 0x7fa94811, 0x7fa8d2f8, 0x7fa85d90,
+ 0x7fa7e7d9, 0x7fa771d4,
+ 0x7fa6fb80, 0x7fa684dd, 0x7fa60dec, 0x7fa596ac, 0x7fa51f1d, 0x7fa4a73f,
+ 0x7fa42f12, 0x7fa3b697,
+ 0x7fa33dcd, 0x7fa2c4b5, 0x7fa24b4d, 0x7fa1d197, 0x7fa15792, 0x7fa0dd3f,
+ 0x7fa0629c, 0x7f9fe7ab,
+ 0x7f9f6c6b, 0x7f9ef0dd, 0x7f9e7500, 0x7f9df8d4, 0x7f9d7c59, 0x7f9cff90,
+ 0x7f9c8278, 0x7f9c0511,
+ 0x7f9b875b, 0x7f9b0957, 0x7f9a8b04, 0x7f9a0c62, 0x7f998d72, 0x7f990e33,
+ 0x7f988ea5, 0x7f980ec8,
+ 0x7f978e9d, 0x7f970e23, 0x7f968d5b, 0x7f960c43, 0x7f958add, 0x7f950929,
+ 0x7f948725, 0x7f9404d3,
+ 0x7f938232, 0x7f92ff43, 0x7f927c04, 0x7f91f878, 0x7f91749c, 0x7f90f072,
+ 0x7f906bf9, 0x7f8fe731,
+ 0x7f8f621b, 0x7f8edcb6, 0x7f8e5702, 0x7f8dd0ff, 0x7f8d4aae, 0x7f8cc40f,
+ 0x7f8c3d20, 0x7f8bb5e3,
+ 0x7f8b2e57, 0x7f8aa67d, 0x7f8a1e54, 0x7f8995dc, 0x7f890d15, 0x7f888400,
+ 0x7f87fa9c, 0x7f8770ea,
+ 0x7f86e6e9, 0x7f865c99, 0x7f85d1fa, 0x7f85470d, 0x7f84bbd1, 0x7f843047,
+ 0x7f83a46e, 0x7f831846,
+ 0x7f828bcf, 0x7f81ff0a, 0x7f8171f6, 0x7f80e494, 0x7f8056e3, 0x7f7fc8e3,
+ 0x7f7f3a95, 0x7f7eabf8,
+ 0x7f7e1d0c, 0x7f7d8dd2, 0x7f7cfe49, 0x7f7c6e71, 0x7f7bde4b, 0x7f7b4dd6,
+ 0x7f7abd13, 0x7f7a2c01,
+ 0x7f799aa0, 0x7f7908f0, 0x7f7876f2, 0x7f77e4a6, 0x7f77520a, 0x7f76bf21,
+ 0x7f762be8, 0x7f759861,
+ 0x7f75048b, 0x7f747067, 0x7f73dbf4, 0x7f734732, 0x7f72b222, 0x7f721cc3,
+ 0x7f718715, 0x7f70f119,
+ 0x7f705ace, 0x7f6fc435, 0x7f6f2d4d, 0x7f6e9617, 0x7f6dfe91, 0x7f6d66be,
+ 0x7f6cce9b, 0x7f6c362a,
+ 0x7f6b9d6b, 0x7f6b045d, 0x7f6a6b00, 0x7f69d154, 0x7f69375a, 0x7f689d12,
+ 0x7f68027b, 0x7f676795,
+ 0x7f66cc61, 0x7f6630de, 0x7f65950c, 0x7f64f8ec, 0x7f645c7d, 0x7f63bfc0,
+ 0x7f6322b4, 0x7f62855a,
+ 0x7f61e7b1, 0x7f6149b9, 0x7f60ab73, 0x7f600cdf, 0x7f5f6dfb, 0x7f5ecec9,
+ 0x7f5e2f49, 0x7f5d8f7a,
+ 0x7f5cef5c, 0x7f5c4ef0, 0x7f5bae36, 0x7f5b0d2c, 0x7f5a6bd5, 0x7f59ca2e,
+ 0x7f592839, 0x7f5885f6,
+ 0x7f57e364, 0x7f574083, 0x7f569d54, 0x7f55f9d6, 0x7f55560a, 0x7f54b1ef,
+ 0x7f540d86, 0x7f5368ce,
+ 0x7f52c3c8, 0x7f521e73, 0x7f5178cf, 0x7f50d2dd, 0x7f502c9d, 0x7f4f860e,
+ 0x7f4edf30, 0x7f4e3804,
+ 0x7f4d9089, 0x7f4ce8c0, 0x7f4c40a8, 0x7f4b9842, 0x7f4aef8d, 0x7f4a468a,
+ 0x7f499d38, 0x7f48f398,
+ 0x7f4849a9, 0x7f479f6c, 0x7f46f4e0, 0x7f464a06, 0x7f459edd, 0x7f44f365,
+ 0x7f44479f, 0x7f439b8b,
+ 0x7f42ef28, 0x7f424277, 0x7f419577, 0x7f40e828, 0x7f403a8b, 0x7f3f8ca0,
+ 0x7f3ede66, 0x7f3e2fde,
+ 0x7f3d8107, 0x7f3cd1e2, 0x7f3c226e, 0x7f3b72ab, 0x7f3ac29b, 0x7f3a123b,
+ 0x7f39618e, 0x7f38b091,
+ 0x7f37ff47, 0x7f374dad, 0x7f369bc6, 0x7f35e990, 0x7f35370b, 0x7f348438,
+ 0x7f33d116, 0x7f331da6,
+ 0x7f3269e8, 0x7f31b5db, 0x7f31017f, 0x7f304cd6, 0x7f2f97dd, 0x7f2ee296,
+ 0x7f2e2d01, 0x7f2d771e,
+ 0x7f2cc0eb, 0x7f2c0a6b, 0x7f2b539c, 0x7f2a9c7e, 0x7f29e512, 0x7f292d58,
+ 0x7f28754f, 0x7f27bcf8,
+ 0x7f270452, 0x7f264b5e, 0x7f25921c, 0x7f24d88b, 0x7f241eab, 0x7f23647e,
+ 0x7f22aa01, 0x7f21ef37,
+ 0x7f21341e, 0x7f2078b6, 0x7f1fbd00, 0x7f1f00fc, 0x7f1e44a9, 0x7f1d8808,
+ 0x7f1ccb18, 0x7f1c0dda,
+ 0x7f1b504e, 0x7f1a9273, 0x7f19d44a, 0x7f1915d2, 0x7f18570c, 0x7f1797f8,
+ 0x7f16d895, 0x7f1618e4,
+ 0x7f1558e4, 0x7f149896, 0x7f13d7fa, 0x7f13170f, 0x7f1255d6, 0x7f11944f,
+ 0x7f10d279, 0x7f101054,
+ 0x7f0f4de2, 0x7f0e8b21, 0x7f0dc811, 0x7f0d04b3, 0x7f0c4107, 0x7f0b7d0d,
+ 0x7f0ab8c4, 0x7f09f42d,
+ 0x7f092f47, 0x7f086a13, 0x7f07a491, 0x7f06dec0, 0x7f0618a1, 0x7f055233,
+ 0x7f048b78, 0x7f03c46d,
+ 0x7f02fd15, 0x7f02356e, 0x7f016d79, 0x7f00a535, 0x7effdca4, 0x7eff13c3,
+ 0x7efe4a95, 0x7efd8118,
+ 0x7efcb74d, 0x7efbed33, 0x7efb22cb, 0x7efa5815, 0x7ef98d11, 0x7ef8c1be,
+ 0x7ef7f61d, 0x7ef72a2d,
+ 0x7ef65def, 0x7ef59163, 0x7ef4c489, 0x7ef3f760, 0x7ef329e9, 0x7ef25c24,
+ 0x7ef18e10, 0x7ef0bfae,
+ 0x7eeff0fe, 0x7eef21ff, 0x7eee52b2, 0x7eed8317, 0x7eecb32d, 0x7eebe2f6,
+ 0x7eeb1270, 0x7eea419b,
+ 0x7ee97079, 0x7ee89f08, 0x7ee7cd49, 0x7ee6fb3b, 0x7ee628df, 0x7ee55635,
+ 0x7ee4833d, 0x7ee3aff6,
+ 0x7ee2dc61, 0x7ee2087e, 0x7ee1344d, 0x7ee05fcd, 0x7edf8aff, 0x7edeb5e3,
+ 0x7edde079, 0x7edd0ac0,
+ 0x7edc34b9, 0x7edb5e64, 0x7eda87c0, 0x7ed9b0ce, 0x7ed8d98e, 0x7ed80200,
+ 0x7ed72a24, 0x7ed651f9,
+ 0x7ed57980, 0x7ed4a0b9, 0x7ed3c7a3, 0x7ed2ee40, 0x7ed2148e, 0x7ed13a8e,
+ 0x7ed0603f, 0x7ecf85a3,
+ 0x7eceaab8, 0x7ecdcf7f, 0x7eccf3f8, 0x7ecc1822, 0x7ecb3bff, 0x7eca5f8d,
+ 0x7ec982cd, 0x7ec8a5bf,
+ 0x7ec7c862, 0x7ec6eab7, 0x7ec60cbe, 0x7ec52e77, 0x7ec44fe2, 0x7ec370fe,
+ 0x7ec291cd, 0x7ec1b24d,
+ 0x7ec0d27f, 0x7ebff263, 0x7ebf11f8, 0x7ebe313f, 0x7ebd5039, 0x7ebc6ee4,
+ 0x7ebb8d40, 0x7ebaab4f,
+ 0x7eb9c910, 0x7eb8e682, 0x7eb803a6, 0x7eb7207c, 0x7eb63d04, 0x7eb5593d,
+ 0x7eb47529, 0x7eb390c6,
+ 0x7eb2ac15, 0x7eb1c716, 0x7eb0e1c9, 0x7eaffc2e, 0x7eaf1645, 0x7eae300d,
+ 0x7ead4987, 0x7eac62b3,
+ 0x7eab7b91, 0x7eaa9421, 0x7ea9ac63, 0x7ea8c457, 0x7ea7dbfc, 0x7ea6f353,
+ 0x7ea60a5d, 0x7ea52118,
+ 0x7ea43785, 0x7ea34da4, 0x7ea26374, 0x7ea178f7, 0x7ea08e2b, 0x7e9fa312,
+ 0x7e9eb7aa, 0x7e9dcbf4,
+ 0x7e9cdff0, 0x7e9bf39e, 0x7e9b06fe, 0x7e9a1a10, 0x7e992cd4, 0x7e983f49,
+ 0x7e975171, 0x7e96634a,
+ 0x7e9574d6, 0x7e948613, 0x7e939702, 0x7e92a7a3, 0x7e91b7f6, 0x7e90c7fb,
+ 0x7e8fd7b2, 0x7e8ee71b,
+ 0x7e8df636, 0x7e8d0502, 0x7e8c1381, 0x7e8b21b1, 0x7e8a2f94, 0x7e893d28,
+ 0x7e884a6f, 0x7e875767,
+ 0x7e866411, 0x7e85706d, 0x7e847c7c, 0x7e83883c, 0x7e8293ae, 0x7e819ed2,
+ 0x7e80a9a8, 0x7e7fb430,
+ 0x7e7ebe6a, 0x7e7dc856, 0x7e7cd1f4, 0x7e7bdb44, 0x7e7ae446, 0x7e79ecf9,
+ 0x7e78f55f, 0x7e77fd77,
+ 0x7e770541, 0x7e760cbd, 0x7e7513ea, 0x7e741aca, 0x7e73215c, 0x7e7227a0,
+ 0x7e712d96, 0x7e70333d,
+ 0x7e6f3897, 0x7e6e3da3, 0x7e6d4261, 0x7e6c46d1, 0x7e6b4af2, 0x7e6a4ec6,
+ 0x7e69524c, 0x7e685584,
+ 0x7e67586e, 0x7e665b0a, 0x7e655d58, 0x7e645f58, 0x7e63610a, 0x7e62626e,
+ 0x7e616384, 0x7e60644c,
+ 0x7e5f64c7, 0x7e5e64f3, 0x7e5d64d1, 0x7e5c6461, 0x7e5b63a4, 0x7e5a6298,
+ 0x7e59613f, 0x7e585f97,
+ 0x7e575da2, 0x7e565b5f, 0x7e5558ce, 0x7e5455ef, 0x7e5352c1, 0x7e524f46,
+ 0x7e514b7e, 0x7e504767,
+ 0x7e4f4302, 0x7e4e3e4f, 0x7e4d394f, 0x7e4c3400, 0x7e4b2e64, 0x7e4a287a,
+ 0x7e492241, 0x7e481bbb,
+ 0x7e4714e7, 0x7e460dc5, 0x7e450656, 0x7e43fe98, 0x7e42f68c, 0x7e41ee33,
+ 0x7e40e58c, 0x7e3fdc97,
+ 0x7e3ed353, 0x7e3dc9c3, 0x7e3cbfe4, 0x7e3bb5b7, 0x7e3aab3c, 0x7e39a074,
+ 0x7e38955e, 0x7e3789fa,
+ 0x7e367e48, 0x7e357248, 0x7e3465fa, 0x7e33595e, 0x7e324c75, 0x7e313f3e,
+ 0x7e3031b9, 0x7e2f23e6,
+ 0x7e2e15c5, 0x7e2d0756, 0x7e2bf89a, 0x7e2ae990, 0x7e29da38, 0x7e28ca92,
+ 0x7e27ba9e, 0x7e26aa5d,
+ 0x7e2599cd, 0x7e2488f0, 0x7e2377c5, 0x7e22664c, 0x7e215486, 0x7e204271,
+ 0x7e1f300f, 0x7e1e1d5f,
+ 0x7e1d0a61, 0x7e1bf716, 0x7e1ae37c, 0x7e19cf95, 0x7e18bb60, 0x7e17a6dd,
+ 0x7e16920d, 0x7e157cee,
+ 0x7e146782, 0x7e1351c9, 0x7e123bc1, 0x7e11256c, 0x7e100ec8, 0x7e0ef7d7,
+ 0x7e0de099, 0x7e0cc90c,
+ 0x7e0bb132, 0x7e0a990a, 0x7e098095, 0x7e0867d1, 0x7e074ec0, 0x7e063561,
+ 0x7e051bb4, 0x7e0401ba,
+ 0x7e02e772, 0x7e01ccdc, 0x7e00b1f9, 0x7dff96c7, 0x7dfe7b48, 0x7dfd5f7b,
+ 0x7dfc4361, 0x7dfb26f9,
+ 0x7dfa0a43, 0x7df8ed3f, 0x7df7cfee, 0x7df6b24f, 0x7df59462, 0x7df47628,
+ 0x7df357a0, 0x7df238ca,
+ 0x7df119a7, 0x7deffa35, 0x7deeda77, 0x7dedba6a, 0x7dec9a10, 0x7deb7968,
+ 0x7dea5872, 0x7de9372f,
+ 0x7de8159e, 0x7de6f3c0, 0x7de5d193, 0x7de4af1a, 0x7de38c52, 0x7de2693d,
+ 0x7de145da, 0x7de02229,
+ 0x7ddefe2b, 0x7dddd9e0, 0x7ddcb546, 0x7ddb905f, 0x7dda6b2a, 0x7dd945a8,
+ 0x7dd81fd8, 0x7dd6f9ba,
+ 0x7dd5d34f, 0x7dd4ac96, 0x7dd38590, 0x7dd25e3c, 0x7dd1369a, 0x7dd00eab,
+ 0x7dcee66e, 0x7dcdbde3,
+ 0x7dcc950b, 0x7dcb6be6, 0x7dca4272, 0x7dc918b1, 0x7dc7eea3, 0x7dc6c447,
+ 0x7dc5999d, 0x7dc46ea6,
+ 0x7dc34361, 0x7dc217cf, 0x7dc0ebef, 0x7dbfbfc1, 0x7dbe9346, 0x7dbd667d,
+ 0x7dbc3967, 0x7dbb0c03,
+ 0x7db9de52, 0x7db8b053, 0x7db78207, 0x7db6536d, 0x7db52485, 0x7db3f550,
+ 0x7db2c5cd, 0x7db195fd,
+ 0x7db065df, 0x7daf3574, 0x7dae04bb, 0x7dacd3b5, 0x7daba261, 0x7daa70c0,
+ 0x7da93ed1, 0x7da80c95,
+ 0x7da6da0b, 0x7da5a733, 0x7da4740e, 0x7da3409c, 0x7da20cdc, 0x7da0d8cf,
+ 0x7d9fa474, 0x7d9e6fcb,
+ 0x7d9d3ad6, 0x7d9c0592, 0x7d9ad001, 0x7d999a23, 0x7d9863f7, 0x7d972d7e,
+ 0x7d95f6b7, 0x7d94bfa3,
+ 0x7d938841, 0x7d925092, 0x7d911896, 0x7d8fe04c, 0x7d8ea7b4, 0x7d8d6ecf,
+ 0x7d8c359d, 0x7d8afc1d,
+ 0x7d89c250, 0x7d888835, 0x7d874dcd, 0x7d861317, 0x7d84d814, 0x7d839cc4,
+ 0x7d826126, 0x7d81253a,
+ 0x7d7fe902, 0x7d7eac7c, 0x7d7d6fa8, 0x7d7c3287, 0x7d7af519, 0x7d79b75d,
+ 0x7d787954, 0x7d773afd,
+ 0x7d75fc59, 0x7d74bd68, 0x7d737e29, 0x7d723e9d, 0x7d70fec4, 0x7d6fbe9d,
+ 0x7d6e7e29, 0x7d6d3d67,
+ 0x7d6bfc58, 0x7d6abafc, 0x7d697952, 0x7d68375b, 0x7d66f517, 0x7d65b285,
+ 0x7d646fa6, 0x7d632c79,
+ 0x7d61e8ff, 0x7d60a538, 0x7d5f6124, 0x7d5e1cc2, 0x7d5cd813, 0x7d5b9316,
+ 0x7d5a4dcc, 0x7d590835,
+ 0x7d57c251, 0x7d567c1f, 0x7d5535a0, 0x7d53eed3, 0x7d52a7ba, 0x7d516053,
+ 0x7d50189e, 0x7d4ed09d,
+ 0x7d4d884e, 0x7d4c3fb1, 0x7d4af6c8, 0x7d49ad91, 0x7d48640d, 0x7d471a3c,
+ 0x7d45d01d, 0x7d4485b1,
+ 0x7d433af8, 0x7d41eff1, 0x7d40a49e, 0x7d3f58fd, 0x7d3e0d0e, 0x7d3cc0d3,
+ 0x7d3b744a, 0x7d3a2774,
+ 0x7d38da51, 0x7d378ce0, 0x7d363f23, 0x7d34f118, 0x7d33a2bf, 0x7d32541a,
+ 0x7d310527, 0x7d2fb5e7,
+ 0x7d2e665a, 0x7d2d1680, 0x7d2bc659, 0x7d2a75e4, 0x7d292522, 0x7d27d413,
+ 0x7d2682b6, 0x7d25310d,
+ 0x7d23df16, 0x7d228cd2, 0x7d213a41, 0x7d1fe762, 0x7d1e9437, 0x7d1d40be,
+ 0x7d1becf8, 0x7d1a98e5,
+ 0x7d194485, 0x7d17efd8, 0x7d169add, 0x7d154595, 0x7d13f001, 0x7d129a1f,
+ 0x7d1143ef, 0x7d0fed73,
+ 0x7d0e96aa, 0x7d0d3f93, 0x7d0be82f, 0x7d0a907e, 0x7d093880, 0x7d07e035,
+ 0x7d06879d, 0x7d052eb8,
+ 0x7d03d585, 0x7d027c05, 0x7d012239, 0x7cffc81f, 0x7cfe6db8, 0x7cfd1304,
+ 0x7cfbb803, 0x7cfa5cb4,
+ 0x7cf90119, 0x7cf7a531, 0x7cf648fb, 0x7cf4ec79, 0x7cf38fa9, 0x7cf2328c,
+ 0x7cf0d522, 0x7cef776b,
+ 0x7cee1967, 0x7cecbb16, 0x7ceb5c78, 0x7ce9fd8d, 0x7ce89e55, 0x7ce73ed0,
+ 0x7ce5defd, 0x7ce47ede,
+ 0x7ce31e72, 0x7ce1bdb8, 0x7ce05cb2, 0x7cdefb5e, 0x7cdd99be, 0x7cdc37d0,
+ 0x7cdad596, 0x7cd9730e,
+ 0x7cd8103a, 0x7cd6ad18, 0x7cd549aa, 0x7cd3e5ee, 0x7cd281e5, 0x7cd11d90,
+ 0x7ccfb8ed, 0x7cce53fe,
+ 0x7ccceec1, 0x7ccb8937, 0x7cca2361, 0x7cc8bd3d, 0x7cc756cd, 0x7cc5f010,
+ 0x7cc48905, 0x7cc321ae,
+ 0x7cc1ba09, 0x7cc05218, 0x7cbee9da, 0x7cbd814f, 0x7cbc1877, 0x7cbaaf51,
+ 0x7cb945df, 0x7cb7dc20,
+ 0x7cb67215, 0x7cb507bc, 0x7cb39d16, 0x7cb23223, 0x7cb0c6e4, 0x7caf5b57,
+ 0x7cadef7e, 0x7cac8358,
+ 0x7cab16e4, 0x7ca9aa24, 0x7ca83d17, 0x7ca6cfbd, 0x7ca56216, 0x7ca3f423,
+ 0x7ca285e2, 0x7ca11755,
+ 0x7c9fa87a, 0x7c9e3953, 0x7c9cc9df, 0x7c9b5a1e, 0x7c99ea10, 0x7c9879b6,
+ 0x7c97090e, 0x7c95981a,
+ 0x7c9426d8, 0x7c92b54a, 0x7c91436f, 0x7c8fd148, 0x7c8e5ed3, 0x7c8cec12,
+ 0x7c8b7903, 0x7c8a05a8,
+ 0x7c889200, 0x7c871e0c, 0x7c85a9ca, 0x7c84353c, 0x7c82c060, 0x7c814b39,
+ 0x7c7fd5c4, 0x7c7e6002,
+ 0x7c7ce9f4, 0x7c7b7399, 0x7c79fcf1, 0x7c7885fc, 0x7c770eba, 0x7c75972c,
+ 0x7c741f51, 0x7c72a729,
+ 0x7c712eb5, 0x7c6fb5f3, 0x7c6e3ce5, 0x7c6cc38a, 0x7c6b49e3, 0x7c69cfee,
+ 0x7c6855ad, 0x7c66db1f,
+ 0x7c656045, 0x7c63e51e, 0x7c6269aa, 0x7c60ede9, 0x7c5f71db, 0x7c5df581,
+ 0x7c5c78da, 0x7c5afbe6,
+ 0x7c597ea6, 0x7c580119, 0x7c56833f, 0x7c550519, 0x7c5386a6, 0x7c5207e6,
+ 0x7c5088d9, 0x7c4f0980,
+ 0x7c4d89da, 0x7c4c09e8, 0x7c4a89a8, 0x7c49091c, 0x7c478844, 0x7c46071f,
+ 0x7c4485ad, 0x7c4303ee,
+ 0x7c4181e3, 0x7c3fff8b, 0x7c3e7ce7, 0x7c3cf9f5, 0x7c3b76b8, 0x7c39f32d,
+ 0x7c386f56, 0x7c36eb33,
+ 0x7c3566c2, 0x7c33e205, 0x7c325cfc, 0x7c30d7a6, 0x7c2f5203, 0x7c2dcc14,
+ 0x7c2c45d8, 0x7c2abf4f,
+ 0x7c29387a, 0x7c27b158, 0x7c2629ea, 0x7c24a22f, 0x7c231a28, 0x7c2191d4,
+ 0x7c200933, 0x7c1e8046,
+ 0x7c1cf70c, 0x7c1b6d86, 0x7c19e3b3, 0x7c185994, 0x7c16cf28, 0x7c15446f,
+ 0x7c13b96a, 0x7c122e19,
+ 0x7c10a27b, 0x7c0f1690, 0x7c0d8a59, 0x7c0bfdd5, 0x7c0a7105, 0x7c08e3e8,
+ 0x7c07567f, 0x7c05c8c9,
+ 0x7c043ac7, 0x7c02ac78, 0x7c011ddd, 0x7bff8ef5, 0x7bfdffc1, 0x7bfc7041,
+ 0x7bfae073, 0x7bf9505a,
+ 0x7bf7bff4, 0x7bf62f41, 0x7bf49e42, 0x7bf30cf6, 0x7bf17b5e, 0x7befe97a,
+ 0x7bee5749, 0x7becc4cc,
+ 0x7beb3202, 0x7be99eec, 0x7be80b89, 0x7be677da, 0x7be4e3df, 0x7be34f97,
+ 0x7be1bb02, 0x7be02621,
+ 0x7bde90f4, 0x7bdcfb7b, 0x7bdb65b5, 0x7bd9cfa2, 0x7bd83944, 0x7bd6a298,
+ 0x7bd50ba1, 0x7bd3745d,
+ 0x7bd1dccc, 0x7bd044f0, 0x7bceacc7, 0x7bcd1451, 0x7bcb7b8f, 0x7bc9e281,
+ 0x7bc84927, 0x7bc6af80,
+ 0x7bc5158c, 0x7bc37b4d, 0x7bc1e0c1, 0x7bc045e9, 0x7bbeaac4, 0x7bbd0f53,
+ 0x7bbb7396, 0x7bb9d78c,
+ 0x7bb83b36, 0x7bb69e94, 0x7bb501a5, 0x7bb3646a, 0x7bb1c6e3, 0x7bb02910,
+ 0x7bae8af0, 0x7bacec84,
+ 0x7bab4dcc, 0x7ba9aec7, 0x7ba80f76, 0x7ba66fd9, 0x7ba4cfef, 0x7ba32fba,
+ 0x7ba18f38, 0x7b9fee69,
+ 0x7b9e4d4f, 0x7b9cabe8, 0x7b9b0a35, 0x7b996836, 0x7b97c5ea, 0x7b962352,
+ 0x7b94806e, 0x7b92dd3e,
+ 0x7b9139c2, 0x7b8f95f9, 0x7b8df1e4, 0x7b8c4d83, 0x7b8aa8d6, 0x7b8903dc,
+ 0x7b875e96, 0x7b85b904,
+ 0x7b841326, 0x7b826cfc, 0x7b80c686, 0x7b7f1fc3, 0x7b7d78b4, 0x7b7bd159,
+ 0x7b7a29b2, 0x7b7881be,
+ 0x7b76d97f, 0x7b7530f3, 0x7b73881b, 0x7b71def7, 0x7b703587, 0x7b6e8bcb,
+ 0x7b6ce1c2, 0x7b6b376e,
+ 0x7b698ccd, 0x7b67e1e0, 0x7b6636a7, 0x7b648b22, 0x7b62df51, 0x7b613334,
+ 0x7b5f86ca, 0x7b5dda15,
+ 0x7b5c2d13, 0x7b5a7fc6, 0x7b58d22c, 0x7b572446, 0x7b557614, 0x7b53c796,
+ 0x7b5218cc, 0x7b5069b6,
+ 0x7b4eba53, 0x7b4d0aa5, 0x7b4b5aab, 0x7b49aa64, 0x7b47f9d2, 0x7b4648f3,
+ 0x7b4497c9, 0x7b42e652,
+ 0x7b413490, 0x7b3f8281, 0x7b3dd026, 0x7b3c1d80, 0x7b3a6a8d, 0x7b38b74e,
+ 0x7b3703c3, 0x7b354fed,
+ 0x7b339bca, 0x7b31e75b, 0x7b3032a0, 0x7b2e7d9a, 0x7b2cc847, 0x7b2b12a8,
+ 0x7b295cbe, 0x7b27a687,
+ 0x7b25f004, 0x7b243936, 0x7b22821b, 0x7b20cab5, 0x7b1f1302, 0x7b1d5b04,
+ 0x7b1ba2b9, 0x7b19ea23,
+ 0x7b183141, 0x7b167813, 0x7b14be99, 0x7b1304d3, 0x7b114ac1, 0x7b0f9063,
+ 0x7b0dd5b9, 0x7b0c1ac4,
+ 0x7b0a5f82, 0x7b08a3f5, 0x7b06e81b, 0x7b052bf6, 0x7b036f85, 0x7b01b2c8,
+ 0x7afff5bf, 0x7afe386a,
+ 0x7afc7aca, 0x7afabcdd, 0x7af8fea5, 0x7af74021, 0x7af58151, 0x7af3c235,
+ 0x7af202cd, 0x7af0431a,
+ 0x7aee831a, 0x7aecc2cf, 0x7aeb0238, 0x7ae94155, 0x7ae78026, 0x7ae5beac,
+ 0x7ae3fce6, 0x7ae23ad4,
+ 0x7ae07876, 0x7adeb5cc, 0x7adcf2d6, 0x7adb2f95, 0x7ad96c08, 0x7ad7a82f,
+ 0x7ad5e40a, 0x7ad41f9a,
+ 0x7ad25ade, 0x7ad095d6, 0x7aced082, 0x7acd0ae3, 0x7acb44f8, 0x7ac97ec1,
+ 0x7ac7b83e, 0x7ac5f170,
+ 0x7ac42a55, 0x7ac262ef, 0x7ac09b3e, 0x7abed341, 0x7abd0af7, 0x7abb4263,
+ 0x7ab97982, 0x7ab7b056,
+ 0x7ab5e6de, 0x7ab41d1b, 0x7ab2530b, 0x7ab088b0, 0x7aaebe0a, 0x7aacf318,
+ 0x7aab27da, 0x7aa95c50,
+ 0x7aa7907b, 0x7aa5c45a, 0x7aa3f7ed, 0x7aa22b35, 0x7aa05e31, 0x7a9e90e1,
+ 0x7a9cc346, 0x7a9af55f,
+ 0x7a99272d, 0x7a9758af, 0x7a9589e5, 0x7a93bad0, 0x7a91eb6f, 0x7a901bc2,
+ 0x7a8e4bca, 0x7a8c7b87,
+ 0x7a8aaaf7, 0x7a88da1c, 0x7a8708f6, 0x7a853784, 0x7a8365c6, 0x7a8193bd,
+ 0x7a7fc168, 0x7a7deec8,
+ 0x7a7c1bdc, 0x7a7a48a4, 0x7a787521, 0x7a76a153, 0x7a74cd38, 0x7a72f8d3,
+ 0x7a712422, 0x7a6f4f25,
+ 0x7a6d79dd, 0x7a6ba449, 0x7a69ce6a, 0x7a67f83f, 0x7a6621c9, 0x7a644b07,
+ 0x7a6273fa, 0x7a609ca1,
+ 0x7a5ec4fc, 0x7a5ced0d, 0x7a5b14d1, 0x7a593c4b, 0x7a576379, 0x7a558a5b,
+ 0x7a53b0f2, 0x7a51d73d,
+ 0x7a4ffd3d, 0x7a4e22f2, 0x7a4c485b, 0x7a4a6d78, 0x7a48924b, 0x7a46b6d1,
+ 0x7a44db0d, 0x7a42fefd,
+ 0x7a4122a1, 0x7a3f45fa, 0x7a3d6908, 0x7a3b8bca, 0x7a39ae41, 0x7a37d06d,
+ 0x7a35f24d, 0x7a3413e2,
+ 0x7a32352b, 0x7a305629, 0x7a2e76dc, 0x7a2c9743, 0x7a2ab75f, 0x7a28d72f,
+ 0x7a26f6b4, 0x7a2515ee,
+ 0x7a2334dd, 0x7a215380, 0x7a1f71d7, 0x7a1d8fe4, 0x7a1bada5, 0x7a19cb1b,
+ 0x7a17e845, 0x7a160524,
+ 0x7a1421b8, 0x7a123e01, 0x7a1059fe, 0x7a0e75b0, 0x7a0c9117, 0x7a0aac32,
+ 0x7a08c702, 0x7a06e187,
+ 0x7a04fbc1, 0x7a0315af, 0x7a012f52, 0x79ff48aa, 0x79fd61b6, 0x79fb7a77,
+ 0x79f992ed, 0x79f7ab18,
+ 0x79f5c2f8, 0x79f3da8c, 0x79f1f1d5, 0x79f008d3, 0x79ee1f86, 0x79ec35ed,
+ 0x79ea4c09, 0x79e861da,
+ 0x79e67760, 0x79e48c9b, 0x79e2a18a, 0x79e0b62e, 0x79deca87, 0x79dcde95,
+ 0x79daf258, 0x79d905d0,
+ 0x79d718fc, 0x79d52bdd, 0x79d33e73, 0x79d150be, 0x79cf62be, 0x79cd7473,
+ 0x79cb85dc, 0x79c996fb,
+ 0x79c7a7ce, 0x79c5b856, 0x79c3c893, 0x79c1d885, 0x79bfe82c, 0x79bdf788,
+ 0x79bc0698, 0x79ba155e,
+ 0x79b823d8, 0x79b63207, 0x79b43fec, 0x79b24d85, 0x79b05ad3, 0x79ae67d6,
+ 0x79ac748e, 0x79aa80fb,
+ 0x79a88d1d, 0x79a698f4, 0x79a4a480, 0x79a2afc1, 0x79a0bab6, 0x799ec561,
+ 0x799ccfc1, 0x799ad9d5,
+ 0x7998e39f, 0x7996ed1e, 0x7994f651, 0x7992ff3a, 0x799107d8, 0x798f102a,
+ 0x798d1832, 0x798b1fef,
+ 0x79892761, 0x79872e87, 0x79853563, 0x79833bf4, 0x7981423a, 0x797f4835,
+ 0x797d4de5, 0x797b534a,
+ 0x79795864, 0x79775d33, 0x797561b8, 0x797365f1, 0x797169df, 0x796f6d83,
+ 0x796d70dc, 0x796b73e9,
+ 0x796976ac, 0x79677924, 0x79657b51, 0x79637d33, 0x79617eca, 0x795f8017,
+ 0x795d8118, 0x795b81cf,
+ 0x7959823b, 0x7957825c, 0x79558232, 0x795381bd, 0x795180fe, 0x794f7ff3,
+ 0x794d7e9e, 0x794b7cfe,
+ 0x79497b13, 0x794778dd, 0x7945765d, 0x79437391, 0x7941707b, 0x793f6d1a,
+ 0x793d696f, 0x793b6578,
+ 0x79396137, 0x79375cab, 0x793557d4, 0x793352b2, 0x79314d46, 0x792f478f,
+ 0x792d418d, 0x792b3b40,
+ 0x792934a9, 0x79272dc7, 0x7925269a, 0x79231f22, 0x79211760, 0x791f0f53,
+ 0x791d06fb, 0x791afe59,
+ 0x7918f56c, 0x7916ec34, 0x7914e2b2, 0x7912d8e4, 0x7910cecc, 0x790ec46a,
+ 0x790cb9bd, 0x790aaec5,
+ 0x7908a382, 0x790697f5, 0x79048c1d, 0x79027ffa, 0x7900738d, 0x78fe66d5,
+ 0x78fc59d3, 0x78fa4c86,
+ 0x78f83eee, 0x78f6310c, 0x78f422df, 0x78f21467, 0x78f005a5, 0x78edf698,
+ 0x78ebe741, 0x78e9d79f,
+ 0x78e7c7b2, 0x78e5b77b, 0x78e3a6f9, 0x78e1962d, 0x78df8516, 0x78dd73b5,
+ 0x78db6209, 0x78d95012,
+ 0x78d73dd1, 0x78d52b46, 0x78d31870, 0x78d1054f, 0x78cef1e4, 0x78ccde2e,
+ 0x78caca2e, 0x78c8b5e3,
+ 0x78c6a14e, 0x78c48c6e, 0x78c27744, 0x78c061cf, 0x78be4c10, 0x78bc3606,
+ 0x78ba1fb2, 0x78b80913,
+ 0x78b5f22a, 0x78b3daf7, 0x78b1c379, 0x78afabb0, 0x78ad939d, 0x78ab7b40,
+ 0x78a96298, 0x78a749a6,
+ 0x78a53069, 0x78a316e2, 0x78a0fd11, 0x789ee2f5, 0x789cc88f, 0x789aadde,
+ 0x789892e3, 0x7896779d,
+ 0x78945c0d, 0x78924033, 0x7890240e, 0x788e07a0, 0x788beae6, 0x7889cde2,
+ 0x7887b094, 0x788592fc,
+ 0x78837519, 0x788156ec, 0x787f3875, 0x787d19b3, 0x787afaa7, 0x7878db50,
+ 0x7876bbb0, 0x78749bc5,
+ 0x78727b8f, 0x78705b10, 0x786e3a46, 0x786c1932, 0x7869f7d3, 0x7867d62a,
+ 0x7865b437, 0x786391fa,
+ 0x78616f72, 0x785f4ca1, 0x785d2984, 0x785b061e, 0x7858e26e, 0x7856be73,
+ 0x78549a2e, 0x7852759e,
+ 0x785050c5, 0x784e2ba1, 0x784c0633, 0x7849e07b, 0x7847ba79, 0x7845942c,
+ 0x78436d96, 0x784146b5,
+ 0x783f1f8a, 0x783cf815, 0x783ad055, 0x7838a84c, 0x78367ff8, 0x7834575a,
+ 0x78322e72, 0x78300540,
+ 0x782ddbc4, 0x782bb1fd, 0x782987ed, 0x78275d92, 0x782532ed, 0x782307fe,
+ 0x7820dcc5, 0x781eb142,
+ 0x781c8575, 0x781a595d, 0x78182cfc, 0x78160051, 0x7813d35b, 0x7811a61b,
+ 0x780f7892, 0x780d4abe,
+ 0x780b1ca0, 0x7808ee38, 0x7806bf86, 0x7804908a, 0x78026145, 0x780031b5,
+ 0x77fe01db, 0x77fbd1b6,
+ 0x77f9a148, 0x77f77090, 0x77f53f8e, 0x77f30e42, 0x77f0dcac, 0x77eeaacc,
+ 0x77ec78a2, 0x77ea462e,
+ 0x77e81370, 0x77e5e068, 0x77e3ad17, 0x77e1797b, 0x77df4595, 0x77dd1165,
+ 0x77dadcec, 0x77d8a828,
+ 0x77d6731a, 0x77d43dc3, 0x77d20822, 0x77cfd236, 0x77cd9c01, 0x77cb6582,
+ 0x77c92eb9, 0x77c6f7a6,
+ 0x77c4c04a, 0x77c288a3, 0x77c050b2, 0x77be1878, 0x77bbdff4, 0x77b9a726,
+ 0x77b76e0e, 0x77b534ac,
+ 0x77b2fb00, 0x77b0c10b, 0x77ae86cc, 0x77ac4c43, 0x77aa1170, 0x77a7d653,
+ 0x77a59aec, 0x77a35f3c,
+ 0x77a12342, 0x779ee6fe, 0x779caa70, 0x779a6d99, 0x77983077, 0x7795f30c,
+ 0x7793b557, 0x77917759,
+ 0x778f3910, 0x778cfa7e, 0x778abba2, 0x77887c7d, 0x77863d0d, 0x7783fd54,
+ 0x7781bd52, 0x777f7d05,
+ 0x777d3c6f, 0x777afb8f, 0x7778ba65, 0x777678f2, 0x77743735, 0x7771f52e,
+ 0x776fb2de, 0x776d7044,
+ 0x776b2d60, 0x7768ea33, 0x7766a6bc, 0x776462fb, 0x77621ef1, 0x775fda9d,
+ 0x775d95ff, 0x775b5118,
+ 0x77590be7, 0x7756c66c, 0x775480a8, 0x77523a9b, 0x774ff443, 0x774dada2,
+ 0x774b66b8, 0x77491f84,
+ 0x7746d806, 0x7744903f, 0x7742482e, 0x773fffd4, 0x773db730, 0x773b6e42,
+ 0x7739250b, 0x7736db8b,
+ 0x773491c0, 0x773247ad, 0x772ffd50, 0x772db2a9, 0x772b67b9, 0x77291c7f,
+ 0x7726d0fc, 0x7724852f,
+ 0x77223919, 0x771fecb9, 0x771da010, 0x771b531d, 0x771905e1, 0x7716b85b,
+ 0x77146a8c, 0x77121c74,
+ 0x770fce12, 0x770d7f66, 0x770b3072, 0x7708e133, 0x770691ab, 0x770441da,
+ 0x7701f1c0, 0x76ffa15c,
+ 0x76fd50ae, 0x76faffb8, 0x76f8ae78, 0x76f65cee, 0x76f40b1b, 0x76f1b8ff,
+ 0x76ef6699, 0x76ed13ea,
+ 0x76eac0f2, 0x76e86db0, 0x76e61a25, 0x76e3c650, 0x76e17233, 0x76df1dcb,
+ 0x76dcc91b, 0x76da7421,
+ 0x76d81ede, 0x76d5c952, 0x76d3737c, 0x76d11d5d, 0x76cec6f5, 0x76cc7043,
+ 0x76ca1948, 0x76c7c204,
+ 0x76c56a77, 0x76c312a0, 0x76c0ba80, 0x76be6217, 0x76bc0965, 0x76b9b069,
+ 0x76b75724, 0x76b4fd96,
+ 0x76b2a3bf, 0x76b0499e, 0x76adef34, 0x76ab9481, 0x76a93985, 0x76a6de40,
+ 0x76a482b1, 0x76a226da,
+ 0x769fcab9, 0x769d6e4f, 0x769b119b, 0x7698b49f, 0x76965759, 0x7693f9ca,
+ 0x76919bf3, 0x768f3dd2,
+ 0x768cdf67, 0x768a80b4, 0x768821b8, 0x7685c272, 0x768362e4, 0x7681030c,
+ 0x767ea2eb, 0x767c4281,
+ 0x7679e1ce, 0x767780d2, 0x76751f8d, 0x7672bdfe, 0x76705c27, 0x766dfa07,
+ 0x766b979d, 0x766934eb,
+ 0x7666d1ef, 0x76646eab, 0x76620b1d, 0x765fa747, 0x765d4327, 0x765adebe,
+ 0x76587a0d, 0x76561512,
+ 0x7653afce, 0x76514a42, 0x764ee46c, 0x764c7e4d, 0x764a17e6, 0x7647b135,
+ 0x76454a3c, 0x7642e2f9,
+ 0x76407b6e, 0x763e139a, 0x763bab7c, 0x76394316, 0x7636da67, 0x7634716f,
+ 0x7632082e, 0x762f9ea4,
+ 0x762d34d1, 0x762acab6, 0x76286051, 0x7625f5a3, 0x76238aad, 0x76211f6e,
+ 0x761eb3e6, 0x761c4815,
+ 0x7619dbfb, 0x76176f98, 0x761502ed, 0x761295f9, 0x761028bb, 0x760dbb35,
+ 0x760b4d67, 0x7608df4f,
+ 0x760670ee, 0x76040245, 0x76019353, 0x75ff2418, 0x75fcb495, 0x75fa44c8,
+ 0x75f7d4b3, 0x75f56455,
+ 0x75f2f3ae, 0x75f082bf, 0x75ee1187, 0x75eba006, 0x75e92e3c, 0x75e6bc2a,
+ 0x75e449ce, 0x75e1d72b,
+ 0x75df643e, 0x75dcf109, 0x75da7d8b, 0x75d809c4, 0x75d595b4, 0x75d3215c,
+ 0x75d0acbc, 0x75ce37d2,
+ 0x75cbc2a0, 0x75c94d25, 0x75c6d762, 0x75c46156, 0x75c1eb01, 0x75bf7464,
+ 0x75bcfd7e, 0x75ba864f,
+ 0x75b80ed8, 0x75b59718, 0x75b31f0f, 0x75b0a6be, 0x75ae2e25, 0x75abb542,
+ 0x75a93c18, 0x75a6c2a4,
+ 0x75a448e8, 0x75a1cee4, 0x759f5496, 0x759cda01, 0x759a5f22, 0x7597e3fc,
+ 0x7595688c, 0x7592ecd4,
+ 0x759070d4, 0x758df48b, 0x758b77fa, 0x7588fb20, 0x75867dfd, 0x75840093,
+ 0x758182df, 0x757f04e3,
+ 0x757c869f, 0x757a0812, 0x7577893d, 0x75750a1f, 0x75728ab9, 0x75700b0a,
+ 0x756d8b13, 0x756b0ad3,
+ 0x75688a4b, 0x7566097b, 0x75638862, 0x75610701, 0x755e8557, 0x755c0365,
+ 0x7559812b, 0x7556fea8,
+ 0x75547bdd, 0x7551f8c9, 0x754f756e, 0x754cf1c9, 0x754a6ddd, 0x7547e9a8,
+ 0x7545652a, 0x7542e065,
+ 0x75405b57, 0x753dd600, 0x753b5061, 0x7538ca7b, 0x7536444b, 0x7533bdd4,
+ 0x75313714, 0x752eb00c,
+ 0x752c28bb, 0x7529a122, 0x75271941, 0x75249118, 0x752208a7, 0x751f7fed,
+ 0x751cf6eb, 0x751a6da0,
+ 0x7517e40e, 0x75155a33, 0x7512d010, 0x751045a5, 0x750dbaf2, 0x750b2ff6,
+ 0x7508a4b2, 0x75061926,
+ 0x75038d52, 0x75010136, 0x74fe74d1, 0x74fbe825, 0x74f95b30, 0x74f6cdf3,
+ 0x74f4406d, 0x74f1b2a0,
+ 0x74ef248b, 0x74ec962d, 0x74ea0787, 0x74e7789a, 0x74e4e964, 0x74e259e6,
+ 0x74dfca20, 0x74dd3a11,
+ 0x74daa9bb, 0x74d8191d, 0x74d58836, 0x74d2f708, 0x74d06591, 0x74cdd3d2,
+ 0x74cb41cc, 0x74c8af7d,
+ 0x74c61ce6, 0x74c38a07, 0x74c0f6e0, 0x74be6372, 0x74bbcfbb, 0x74b93bbc,
+ 0x74b6a775, 0x74b412e6,
+ 0x74b17e0f, 0x74aee8f0, 0x74ac5389, 0x74a9bddb, 0x74a727e4, 0x74a491a5,
+ 0x74a1fb1e, 0x749f6450,
+ 0x749ccd39, 0x749a35db, 0x74979e34, 0x74950646, 0x74926e10, 0x748fd592,
+ 0x748d3ccb, 0x748aa3be,
+ 0x74880a68, 0x748570ca, 0x7482d6e4, 0x74803cb7, 0x747da242, 0x747b0784,
+ 0x74786c7f, 0x7475d132,
+ 0x7473359e, 0x747099c1, 0x746dfd9d, 0x746b6131, 0x7468c47c, 0x74662781,
+ 0x74638a3d, 0x7460ecb2,
+ 0x745e4ede, 0x745bb0c3, 0x74591261, 0x745673b6, 0x7453d4c4, 0x7451358a,
+ 0x744e9608, 0x744bf63e,
+ 0x7449562d, 0x7446b5d4, 0x74441533, 0x7441744b, 0x743ed31b, 0x743c31a3,
+ 0x74398fe3, 0x7436eddc,
+ 0x74344b8d, 0x7431a8f6, 0x742f0618, 0x742c62f2, 0x7429bf84, 0x74271bcf,
+ 0x742477d2, 0x7421d38e,
+ 0x741f2f01, 0x741c8a2d, 0x7419e512, 0x74173faf, 0x74149a04, 0x7411f412,
+ 0x740f4dd8, 0x740ca756,
+ 0x740a008d, 0x7407597d, 0x7404b224, 0x74020a85, 0x73ff629d, 0x73fcba6e,
+ 0x73fa11f8, 0x73f7693a,
+ 0x73f4c034, 0x73f216e7, 0x73ef6d53, 0x73ecc377, 0x73ea1953, 0x73e76ee8,
+ 0x73e4c435, 0x73e2193b,
+ 0x73df6df9, 0x73dcc270, 0x73da16a0, 0x73d76a88, 0x73d4be28, 0x73d21182,
+ 0x73cf6493, 0x73ccb75d,
+ 0x73ca09e0, 0x73c75c1c, 0x73c4ae10, 0x73c1ffbc, 0x73bf5121, 0x73bca23f,
+ 0x73b9f315, 0x73b743a4,
+ 0x73b493ec, 0x73b1e3ec, 0x73af33a5, 0x73ac8316, 0x73a9d240, 0x73a72123,
+ 0x73a46fbf, 0x73a1be13,
+ 0x739f0c20, 0x739c59e5, 0x7399a763, 0x7396f49a, 0x73944189, 0x73918e32,
+ 0x738eda93, 0x738c26ac,
+ 0x7389727f, 0x7386be0a, 0x7384094e, 0x7381544a, 0x737e9f00, 0x737be96e,
+ 0x73793395, 0x73767d74,
+ 0x7373c70d, 0x7371105e, 0x736e5968, 0x736ba22b, 0x7368eaa6, 0x736632db,
+ 0x73637ac8, 0x7360c26e,
+ 0x735e09cd, 0x735b50e4, 0x735897b5, 0x7355de3e, 0x73532481, 0x73506a7c,
+ 0x734db030, 0x734af59d,
+ 0x73483ac2, 0x73457fa1, 0x7342c438, 0x73400889, 0x733d4c92, 0x733a9054,
+ 0x7337d3d0, 0x73351704,
+ 0x733259f1, 0x732f9c97, 0x732cdef6, 0x732a210d, 0x732762de, 0x7324a468,
+ 0x7321e5ab, 0x731f26a7,
+ 0x731c675b, 0x7319a7c9, 0x7316e7f0, 0x731427cf, 0x73116768, 0x730ea6ba,
+ 0x730be5c5, 0x73092489,
+ 0x73066306, 0x7303a13b, 0x7300df2a, 0x72fe1cd2, 0x72fb5a34, 0x72f8974e,
+ 0x72f5d421, 0x72f310ad,
+ 0x72f04cf3, 0x72ed88f1, 0x72eac4a9, 0x72e8001a, 0x72e53b44, 0x72e27627,
+ 0x72dfb0c3, 0x72dceb18,
+ 0x72da2526, 0x72d75eee, 0x72d4986f, 0x72d1d1a9, 0x72cf0a9c, 0x72cc4348,
+ 0x72c97bad, 0x72c6b3cc,
+ 0x72c3eba4, 0x72c12335, 0x72be5a7f, 0x72bb9183, 0x72b8c83f, 0x72b5feb5,
+ 0x72b334e4, 0x72b06acd,
+ 0x72ada06f, 0x72aad5c9, 0x72a80ade, 0x72a53fab, 0x72a27432, 0x729fa872,
+ 0x729cdc6b, 0x729a101e,
+ 0x7297438a, 0x729476af, 0x7291a98e, 0x728edc26, 0x728c0e77, 0x72894082,
+ 0x72867245, 0x7283a3c3,
+ 0x7280d4f9, 0x727e05e9, 0x727b3693, 0x727866f6, 0x72759712, 0x7272c6e7,
+ 0x726ff676, 0x726d25bf,
+ 0x726a54c1, 0x7267837c, 0x7264b1f0, 0x7261e01e, 0x725f0e06, 0x725c3ba7,
+ 0x72596901, 0x72569615,
+ 0x7253c2e3, 0x7250ef6a, 0x724e1baa, 0x724b47a4, 0x72487357, 0x72459ec4,
+ 0x7242c9ea, 0x723ff4ca,
+ 0x723d1f63, 0x723a49b6, 0x723773c3, 0x72349d89, 0x7231c708, 0x722ef041,
+ 0x722c1934, 0x722941e0,
+ 0x72266a46, 0x72239266, 0x7220ba3f, 0x721de1d1, 0x721b091d, 0x72183023,
+ 0x721556e3, 0x72127d5c,
+ 0x720fa38e, 0x720cc97b, 0x7209ef21, 0x72071480, 0x7204399a, 0x72015e6d,
+ 0x71fe82f9, 0x71fba740,
+ 0x71f8cb40, 0x71f5eefa, 0x71f3126d, 0x71f0359a, 0x71ed5881, 0x71ea7b22,
+ 0x71e79d7c, 0x71e4bf90,
+ 0x71e1e15e, 0x71df02e5, 0x71dc2427, 0x71d94522, 0x71d665d6, 0x71d38645,
+ 0x71d0a66d, 0x71cdc650,
+ 0x71cae5ec, 0x71c80542, 0x71c52451, 0x71c2431b, 0x71bf619e, 0x71bc7fdb,
+ 0x71b99dd2, 0x71b6bb83,
+ 0x71b3d8ed, 0x71b0f612, 0x71ae12f0, 0x71ab2f89, 0x71a84bdb, 0x71a567e7,
+ 0x71a283ad, 0x719f9f2c,
+ 0x719cba66, 0x7199d55a, 0x7196f008, 0x71940a6f, 0x71912490, 0x718e3e6c,
+ 0x718b5801, 0x71887151,
+ 0x71858a5a, 0x7182a31d, 0x717fbb9a, 0x717cd3d2, 0x7179ebc3, 0x7177036e,
+ 0x71741ad3, 0x717131f3,
+ 0x716e48cc, 0x716b5f5f, 0x716875ad, 0x71658bb4, 0x7162a175, 0x715fb6f1,
+ 0x715ccc26, 0x7159e116,
+ 0x7156f5c0, 0x71540a24, 0x71511e42, 0x714e321a, 0x714b45ac, 0x714858f8,
+ 0x71456bfe, 0x71427ebf,
+ 0x713f9139, 0x713ca36e, 0x7139b55d, 0x7136c706, 0x7133d869, 0x7130e987,
+ 0x712dfa5e, 0x712b0af0,
+ 0x71281b3c, 0x71252b42, 0x71223b02, 0x711f4a7d, 0x711c59b2, 0x711968a1,
+ 0x7116774a, 0x711385ad,
+ 0x711093cb, 0x710da1a3, 0x710aaf35, 0x7107bc82, 0x7104c989, 0x7101d64a,
+ 0x70fee2c5, 0x70fbeefb,
+ 0x70f8faeb, 0x70f60695, 0x70f311fa, 0x70f01d19, 0x70ed27f2, 0x70ea3286,
+ 0x70e73cd4, 0x70e446dc,
+ 0x70e1509f, 0x70de5a1c, 0x70db6353, 0x70d86c45, 0x70d574f1, 0x70d27d58,
+ 0x70cf8579, 0x70cc8d54,
+ 0x70c994ea, 0x70c69c3a, 0x70c3a345, 0x70c0aa0a, 0x70bdb08a, 0x70bab6c4,
+ 0x70b7bcb8, 0x70b4c267,
+ 0x70b1c7d1, 0x70aeccf5, 0x70abd1d3, 0x70a8d66c, 0x70a5dac0, 0x70a2dece,
+ 0x709fe296, 0x709ce619,
+ 0x7099e957, 0x7096ec4f, 0x7093ef01, 0x7090f16e, 0x708df396, 0x708af579,
+ 0x7087f715, 0x7084f86d,
+ 0x7081f97f, 0x707efa4c, 0x707bfad3, 0x7078fb15, 0x7075fb11, 0x7072fac9,
+ 0x706ffa3a, 0x706cf967,
+ 0x7069f84e, 0x7066f6f0, 0x7063f54c, 0x7060f363, 0x705df135, 0x705aeec1,
+ 0x7057ec08, 0x7054e90a,
+ 0x7051e5c7, 0x704ee23e, 0x704bde70, 0x7048da5d, 0x7045d604, 0x7042d166,
+ 0x703fcc83, 0x703cc75b,
+ 0x7039c1ed, 0x7036bc3b, 0x7033b643, 0x7030b005, 0x702da983, 0x702aa2bb,
+ 0x70279baf, 0x7024945d,
+ 0x70218cc6, 0x701e84e9, 0x701b7cc8, 0x70187461, 0x70156bb5, 0x701262c4,
+ 0x700f598e, 0x700c5013,
+ 0x70094653, 0x70063c4e, 0x70033203, 0x70002774, 0x6ffd1c9f, 0x6ffa1185,
+ 0x6ff70626, 0x6ff3fa82,
+ 0x6ff0ee99, 0x6fede26b, 0x6fead5f8, 0x6fe7c940, 0x6fe4bc43, 0x6fe1af01,
+ 0x6fdea17a, 0x6fdb93ae,
+ 0x6fd8859d, 0x6fd57746, 0x6fd268ab, 0x6fcf59cb, 0x6fcc4aa6, 0x6fc93b3c,
+ 0x6fc62b8d, 0x6fc31b99,
+ 0x6fc00b60, 0x6fbcfae2, 0x6fb9ea20, 0x6fb6d918, 0x6fb3c7cb, 0x6fb0b63a,
+ 0x6fada464, 0x6faa9248,
+ 0x6fa77fe8, 0x6fa46d43, 0x6fa15a59, 0x6f9e472b, 0x6f9b33b7, 0x6f981fff,
+ 0x6f950c01, 0x6f91f7bf,
+ 0x6f8ee338, 0x6f8bce6c, 0x6f88b95c, 0x6f85a407, 0x6f828e6c, 0x6f7f788d,
+ 0x6f7c626a, 0x6f794c01,
+ 0x6f763554, 0x6f731e62, 0x6f70072b, 0x6f6cefb0, 0x6f69d7f0, 0x6f66bfeb,
+ 0x6f63a7a1, 0x6f608f13,
+ 0x6f5d7640, 0x6f5a5d28, 0x6f5743cb, 0x6f542a2a, 0x6f511044, 0x6f4df61a,
+ 0x6f4adbab, 0x6f47c0f7,
+ 0x6f44a5ff, 0x6f418ac2, 0x6f3e6f40, 0x6f3b537a, 0x6f38376f, 0x6f351b1f,
+ 0x6f31fe8b, 0x6f2ee1b2,
+ 0x6f2bc495, 0x6f28a733, 0x6f25898d, 0x6f226ba2, 0x6f1f4d72, 0x6f1c2efe,
+ 0x6f191045, 0x6f15f148,
+ 0x6f12d206, 0x6f0fb280, 0x6f0c92b6, 0x6f0972a6, 0x6f065253, 0x6f0331ba,
+ 0x6f0010de, 0x6efcefbd,
+ 0x6ef9ce57, 0x6ef6acad, 0x6ef38abe, 0x6ef0688b, 0x6eed4614, 0x6eea2358,
+ 0x6ee70058, 0x6ee3dd13,
+ 0x6ee0b98a, 0x6edd95bd, 0x6eda71ab, 0x6ed74d55, 0x6ed428ba, 0x6ed103db,
+ 0x6ecddeb8, 0x6ecab950,
+ 0x6ec793a4, 0x6ec46db4, 0x6ec1477f, 0x6ebe2106, 0x6ebafa49, 0x6eb7d347,
+ 0x6eb4ac02, 0x6eb18477,
+ 0x6eae5ca9, 0x6eab3496, 0x6ea80c3f, 0x6ea4e3a4, 0x6ea1bac4, 0x6e9e91a1,
+ 0x6e9b6839, 0x6e983e8d,
+ 0x6e95149c, 0x6e91ea67, 0x6e8ebfef, 0x6e8b9532, 0x6e886a30, 0x6e853eeb,
+ 0x6e821361, 0x6e7ee794,
+ 0x6e7bbb82, 0x6e788f2c, 0x6e756291, 0x6e7235b3, 0x6e6f0890, 0x6e6bdb2a,
+ 0x6e68ad7f, 0x6e657f90,
+ 0x6e62515d, 0x6e5f22e6, 0x6e5bf42b, 0x6e58c52c, 0x6e5595e9, 0x6e526662,
+ 0x6e4f3696, 0x6e4c0687,
+ 0x6e48d633, 0x6e45a59c, 0x6e4274c1, 0x6e3f43a1, 0x6e3c123e, 0x6e38e096,
+ 0x6e35aeab, 0x6e327c7b,
+ 0x6e2f4a08, 0x6e2c1750, 0x6e28e455, 0x6e25b115, 0x6e227d92, 0x6e1f49cb,
+ 0x6e1c15c0, 0x6e18e171,
+ 0x6e15acde, 0x6e127807, 0x6e0f42ec, 0x6e0c0d8e, 0x6e08d7eb, 0x6e05a205,
+ 0x6e026bda, 0x6dff356c,
+ 0x6dfbfeba, 0x6df8c7c4, 0x6df5908b, 0x6df2590d, 0x6def214c, 0x6debe947,
+ 0x6de8b0fe, 0x6de57871,
+ 0x6de23fa0, 0x6ddf068c, 0x6ddbcd34, 0x6dd89398, 0x6dd559b9, 0x6dd21f95,
+ 0x6dcee52e, 0x6dcbaa83,
+ 0x6dc86f95, 0x6dc53462, 0x6dc1f8ec, 0x6dbebd33, 0x6dbb8135, 0x6db844f4,
+ 0x6db5086f, 0x6db1cba7,
+ 0x6dae8e9b, 0x6dab514b, 0x6da813b8, 0x6da4d5e1, 0x6da197c6, 0x6d9e5968,
+ 0x6d9b1ac6, 0x6d97dbe0,
+ 0x6d949cb7, 0x6d915d4a, 0x6d8e1d9a, 0x6d8adda6, 0x6d879d6e, 0x6d845cf3,
+ 0x6d811c35, 0x6d7ddb33,
+ 0x6d7a99ed, 0x6d775864, 0x6d741697, 0x6d70d487, 0x6d6d9233, 0x6d6a4f9c,
+ 0x6d670cc1, 0x6d63c9a3,
+ 0x6d608641, 0x6d5d429c, 0x6d59feb3, 0x6d56ba87, 0x6d537617, 0x6d503164,
+ 0x6d4cec6e, 0x6d49a734,
+ 0x6d4661b7, 0x6d431bf6, 0x6d3fd5f2, 0x6d3c8fab, 0x6d394920, 0x6d360252,
+ 0x6d32bb40, 0x6d2f73eb,
+ 0x6d2c2c53, 0x6d28e477, 0x6d259c58, 0x6d2253f6, 0x6d1f0b50, 0x6d1bc267,
+ 0x6d18793b, 0x6d152fcc,
+ 0x6d11e619, 0x6d0e9c23, 0x6d0b51e9, 0x6d08076d, 0x6d04bcad, 0x6d0171aa,
+ 0x6cfe2663, 0x6cfadada,
+ 0x6cf78f0d, 0x6cf442fd, 0x6cf0f6aa, 0x6cedaa13, 0x6cea5d3a, 0x6ce7101d,
+ 0x6ce3c2bd, 0x6ce0751a,
+ 0x6cdd2733, 0x6cd9d90a, 0x6cd68a9d, 0x6cd33bed, 0x6ccfecfa, 0x6ccc9dc4,
+ 0x6cc94e4b, 0x6cc5fe8f,
+ 0x6cc2ae90, 0x6cbf5e4d, 0x6cbc0dc8, 0x6cb8bcff, 0x6cb56bf4, 0x6cb21aa5,
+ 0x6caec913, 0x6cab773e,
+ 0x6ca82527, 0x6ca4d2cc, 0x6ca1802e, 0x6c9e2d4d, 0x6c9ada29, 0x6c9786c2,
+ 0x6c943318, 0x6c90df2c,
+ 0x6c8d8afc, 0x6c8a3689, 0x6c86e1d3, 0x6c838cdb, 0x6c80379f, 0x6c7ce220,
+ 0x6c798c5f, 0x6c76365b,
+ 0x6c72e013, 0x6c6f8989, 0x6c6c32bc, 0x6c68dbac, 0x6c658459, 0x6c622cc4,
+ 0x6c5ed4eb, 0x6c5b7cd0,
+ 0x6c582472, 0x6c54cbd1, 0x6c5172ed, 0x6c4e19c6, 0x6c4ac05d, 0x6c4766b0,
+ 0x6c440cc1, 0x6c40b28f,
+ 0x6c3d581b, 0x6c39fd63, 0x6c36a269, 0x6c33472c, 0x6c2febad, 0x6c2c8fea,
+ 0x6c2933e5, 0x6c25d79d,
+ 0x6c227b13, 0x6c1f1e45, 0x6c1bc136, 0x6c1863e3, 0x6c15064e, 0x6c11a876,
+ 0x6c0e4a5b, 0x6c0aebfe,
+ 0x6c078d5e, 0x6c042e7b, 0x6c00cf56, 0x6bfd6fee, 0x6bfa1044, 0x6bf6b056,
+ 0x6bf35027, 0x6befefb5,
+ 0x6bec8f00, 0x6be92e08, 0x6be5ccce, 0x6be26b52, 0x6bdf0993, 0x6bdba791,
+ 0x6bd8454d, 0x6bd4e2c6,
+ 0x6bd17ffd, 0x6bce1cf1, 0x6bcab9a3, 0x6bc75613, 0x6bc3f23f, 0x6bc08e2a,
+ 0x6bbd29d2, 0x6bb9c537,
+ 0x6bb6605a, 0x6bb2fb3b, 0x6baf95d9, 0x6bac3034, 0x6ba8ca4e, 0x6ba56425,
+ 0x6ba1fdb9, 0x6b9e970b,
+ 0x6b9b301b, 0x6b97c8e8, 0x6b946173, 0x6b90f9bc, 0x6b8d91c2, 0x6b8a2986,
+ 0x6b86c107, 0x6b835846,
+ 0x6b7fef43, 0x6b7c85fe, 0x6b791c76, 0x6b75b2ac, 0x6b7248a0, 0x6b6ede51,
+ 0x6b6b73c0, 0x6b6808ed,
+ 0x6b649dd8, 0x6b613280, 0x6b5dc6e6, 0x6b5a5b0a, 0x6b56eeec, 0x6b53828b,
+ 0x6b5015e9, 0x6b4ca904,
+ 0x6b493bdd, 0x6b45ce73, 0x6b4260c8, 0x6b3ef2da, 0x6b3b84ab, 0x6b381639,
+ 0x6b34a785, 0x6b31388e,
+ 0x6b2dc956, 0x6b2a59dc, 0x6b26ea1f, 0x6b237a21, 0x6b2009e0, 0x6b1c995d,
+ 0x6b192898, 0x6b15b791,
+ 0x6b124648, 0x6b0ed4bd, 0x6b0b62f0, 0x6b07f0e1, 0x6b047e90, 0x6b010bfd,
+ 0x6afd9928, 0x6afa2610,
+ 0x6af6b2b7, 0x6af33f1c, 0x6aefcb3f, 0x6aec5720, 0x6ae8e2bf, 0x6ae56e1c,
+ 0x6ae1f937, 0x6ade8410,
+ 0x6adb0ea8, 0x6ad798fd, 0x6ad42311, 0x6ad0ace2, 0x6acd3672, 0x6ac9bfc0,
+ 0x6ac648cb, 0x6ac2d195,
+ 0x6abf5a1e, 0x6abbe264, 0x6ab86a68, 0x6ab4f22b, 0x6ab179ac, 0x6aae00eb,
+ 0x6aaa87e8, 0x6aa70ea4,
+ 0x6aa3951d, 0x6aa01b55, 0x6a9ca14b, 0x6a992700, 0x6a95ac72, 0x6a9231a3,
+ 0x6a8eb692, 0x6a8b3b3f,
+ 0x6a87bfab, 0x6a8443d5, 0x6a80c7bd, 0x6a7d4b64, 0x6a79cec8, 0x6a7651ec,
+ 0x6a72d4cd, 0x6a6f576d,
+ 0x6a6bd9cb, 0x6a685be8, 0x6a64ddc2, 0x6a615f5c, 0x6a5de0b3, 0x6a5a61c9,
+ 0x6a56e29e, 0x6a536331,
+ 0x6a4fe382, 0x6a4c6391, 0x6a48e360, 0x6a4562ec, 0x6a41e237, 0x6a3e6140,
+ 0x6a3ae008, 0x6a375e8f,
+ 0x6a33dcd4, 0x6a305ad7, 0x6a2cd899, 0x6a295619, 0x6a25d358, 0x6a225055,
+ 0x6a1ecd11, 0x6a1b498c,
+ 0x6a17c5c5, 0x6a1441bc, 0x6a10bd72, 0x6a0d38e7, 0x6a09b41a, 0x6a062f0c,
+ 0x6a02a9bc, 0x69ff242b,
+ 0x69fb9e59, 0x69f81845, 0x69f491f0, 0x69f10b5a, 0x69ed8482, 0x69e9fd69,
+ 0x69e6760f, 0x69e2ee73,
+ 0x69df6696, 0x69dbde77, 0x69d85618, 0x69d4cd77, 0x69d14494, 0x69cdbb71,
+ 0x69ca320c, 0x69c6a866,
+ 0x69c31e7f, 0x69bf9456, 0x69bc09ec, 0x69b87f41, 0x69b4f455, 0x69b16928,
+ 0x69adddb9, 0x69aa5209,
+ 0x69a6c618, 0x69a339e6, 0x699fad73, 0x699c20be, 0x699893c9, 0x69950692,
+ 0x6991791a, 0x698deb61,
+ 0x698a5d67, 0x6986cf2c, 0x698340af, 0x697fb1f2, 0x697c22f3, 0x697893b4,
+ 0x69750433, 0x69717472,
+ 0x696de46f, 0x696a542b, 0x6966c3a6, 0x696332e1, 0x695fa1da, 0x695c1092,
+ 0x69587f09, 0x6954ed40,
+ 0x69515b35, 0x694dc8e9, 0x694a365c, 0x6946a38f, 0x69431080, 0x693f7d31,
+ 0x693be9a0, 0x693855cf,
+ 0x6934c1bd, 0x69312d6a, 0x692d98d6, 0x692a0401, 0x69266eeb, 0x6922d995,
+ 0x691f43fd, 0x691bae25,
+ 0x6918180c, 0x691481b2, 0x6910eb17, 0x690d543b, 0x6909bd1f, 0x690625c2,
+ 0x69028e24, 0x68fef645,
+ 0x68fb5e25, 0x68f7c5c5, 0x68f42d24, 0x68f09442, 0x68ecfb20, 0x68e961bd,
+ 0x68e5c819, 0x68e22e34,
+ 0x68de940f, 0x68daf9a9, 0x68d75f02, 0x68d3c41b, 0x68d028f2, 0x68cc8d8a,
+ 0x68c8f1e0, 0x68c555f6,
+ 0x68c1b9cc, 0x68be1d61, 0x68ba80b5, 0x68b6e3c8, 0x68b3469b, 0x68afa92e,
+ 0x68ac0b7f, 0x68a86d91,
+ 0x68a4cf61, 0x68a130f1, 0x689d9241, 0x6899f350, 0x6896541f, 0x6892b4ad,
+ 0x688f14fa, 0x688b7507,
+ 0x6887d4d4, 0x68843460, 0x688093ab, 0x687cf2b6, 0x68795181, 0x6875b00b,
+ 0x68720e55, 0x686e6c5e,
+ 0x686aca27, 0x686727b0, 0x686384f8, 0x685fe200, 0x685c3ec7, 0x68589b4e,
+ 0x6854f795, 0x6851539b,
+ 0x684daf61, 0x684a0ae6, 0x6846662c, 0x6842c131, 0x683f1bf5, 0x683b7679,
+ 0x6837d0bd, 0x68342ac1,
+ 0x68308485, 0x682cde08, 0x6829374b, 0x6825904d, 0x6821e910, 0x681e4192,
+ 0x681a99d4, 0x6816f1d6,
+ 0x68134997, 0x680fa118, 0x680bf85a, 0x68084f5a, 0x6804a61b, 0x6800fc9c,
+ 0x67fd52dc, 0x67f9a8dd,
+ 0x67f5fe9d, 0x67f2541d, 0x67eea95d, 0x67eafe5d, 0x67e7531c, 0x67e3a79c,
+ 0x67dffbdc, 0x67dc4fdb,
+ 0x67d8a39a, 0x67d4f71a, 0x67d14a59, 0x67cd9d58, 0x67c9f017, 0x67c64297,
+ 0x67c294d6, 0x67bee6d5,
+ 0x67bb3894, 0x67b78a13, 0x67b3db53, 0x67b02c52, 0x67ac7d11, 0x67a8cd91,
+ 0x67a51dd0, 0x67a16dcf,
+ 0x679dbd8f, 0x679a0d0f, 0x67965c4e, 0x6792ab4e, 0x678efa0e, 0x678b488e,
+ 0x678796ce, 0x6783e4cf,
+ 0x6780328f, 0x677c8010, 0x6778cd50, 0x67751a51, 0x67716713, 0x676db394,
+ 0x6769ffd5, 0x67664bd7,
+ 0x67629799, 0x675ee31b, 0x675b2e5e, 0x67577960, 0x6753c423, 0x67500ea7,
+ 0x674c58ea, 0x6748a2ee,
+ 0x6744ecb2, 0x67413636, 0x673d7f7b, 0x6739c880, 0x67361145, 0x673259ca,
+ 0x672ea210, 0x672aea17,
+ 0x672731dd, 0x67237964, 0x671fc0ac, 0x671c07b4, 0x67184e7c, 0x67149504,
+ 0x6710db4d, 0x670d2157,
+ 0x67096721, 0x6705acab, 0x6701f1f6, 0x66fe3701, 0x66fa7bcd, 0x66f6c059,
+ 0x66f304a6, 0x66ef48b3,
+ 0x66eb8c80, 0x66e7d00f, 0x66e4135d, 0x66e0566c, 0x66dc993c, 0x66d8dbcd,
+ 0x66d51e1d, 0x66d1602f,
+ 0x66cda201, 0x66c9e393, 0x66c624e7, 0x66c265fa, 0x66bea6cf, 0x66bae764,
+ 0x66b727ba, 0x66b367d0,
+ 0x66afa7a7, 0x66abe73f, 0x66a82697, 0x66a465b0, 0x66a0a489, 0x669ce324,
+ 0x6699217f, 0x66955f9b,
+ 0x66919d77, 0x668ddb14, 0x668a1872, 0x66865591, 0x66829270, 0x667ecf11,
+ 0x667b0b72, 0x66774793,
+ 0x66738376, 0x666fbf19, 0x666bfa7d, 0x666835a2, 0x66647088, 0x6660ab2f,
+ 0x665ce596, 0x66591fbf,
+ 0x665559a8, 0x66519352, 0x664dccbd, 0x664a05e9, 0x66463ed6, 0x66427784,
+ 0x663eaff2, 0x663ae822,
+ 0x66372012, 0x663357c4, 0x662f8f36, 0x662bc66a, 0x6627fd5e, 0x66243413,
+ 0x66206a8a, 0x661ca0c1,
+ 0x6618d6b9, 0x66150c73, 0x661141ed, 0x660d7729, 0x6609ac25, 0x6605e0e3,
+ 0x66021561, 0x65fe49a1,
+ 0x65fa7da2, 0x65f6b164, 0x65f2e4e7, 0x65ef182b, 0x65eb4b30, 0x65e77df6,
+ 0x65e3b07e, 0x65dfe2c6,
+ 0x65dc14d0, 0x65d8469b, 0x65d47827, 0x65d0a975, 0x65ccda83, 0x65c90b53,
+ 0x65c53be4, 0x65c16c36,
+ 0x65bd9c49, 0x65b9cc1e, 0x65b5fbb4, 0x65b22b0b, 0x65ae5a23, 0x65aa88fd,
+ 0x65a6b798, 0x65a2e5f4,
+ 0x659f1412, 0x659b41f1, 0x65976f91, 0x65939cf3, 0x658fca15, 0x658bf6fa,
+ 0x6588239f, 0x65845006,
+ 0x65807c2f, 0x657ca818, 0x6578d3c4, 0x6574ff30, 0x65712a5e, 0x656d554d,
+ 0x65697ffe, 0x6565aa71,
+ 0x6561d4a4, 0x655dfe99, 0x655a2850, 0x655651c8, 0x65527b02, 0x654ea3fd,
+ 0x654accba, 0x6546f538,
+ 0x65431d77, 0x653f4579, 0x653b6d3b, 0x653794c0, 0x6533bc06, 0x652fe30d,
+ 0x652c09d6, 0x65283061,
+ 0x652456ad, 0x65207cbb, 0x651ca28a, 0x6518c81b, 0x6514ed6e, 0x65111283,
+ 0x650d3759, 0x65095bf0,
+ 0x6505804a, 0x6501a465, 0x64fdc841, 0x64f9ebe0, 0x64f60f40, 0x64f23262,
+ 0x64ee5546, 0x64ea77eb,
+ 0x64e69a52, 0x64e2bc7b, 0x64dede66, 0x64db0012, 0x64d72180, 0x64d342b0,
+ 0x64cf63a2, 0x64cb8456,
+ 0x64c7a4cb, 0x64c3c502, 0x64bfe4fc, 0x64bc04b6, 0x64b82433, 0x64b44372,
+ 0x64b06273, 0x64ac8135,
+ 0x64a89fba, 0x64a4be00, 0x64a0dc08, 0x649cf9d2, 0x6499175e, 0x649534ac,
+ 0x649151bc, 0x648d6e8e,
+ 0x64898b22, 0x6485a778, 0x6481c390, 0x647ddf6a, 0x6479fb06, 0x64761664,
+ 0x64723184, 0x646e4c66,
+ 0x646a670a, 0x64668170, 0x64629b98, 0x645eb582, 0x645acf2e, 0x6456e89d,
+ 0x645301cd, 0x644f1ac0,
+ 0x644b3375, 0x64474bec, 0x64436425, 0x643f7c20, 0x643b93dd, 0x6437ab5d,
+ 0x6433c29f, 0x642fd9a3,
+ 0x642bf069, 0x642806f1, 0x64241d3c, 0x64203348, 0x641c4917, 0x64185ea9,
+ 0x641473fc, 0x64108912,
+ 0x640c9dea, 0x6408b284, 0x6404c6e1, 0x6400db00, 0x63fceee1, 0x63f90285,
+ 0x63f515eb, 0x63f12913,
+ 0x63ed3bfd, 0x63e94eaa, 0x63e5611a, 0x63e1734b, 0x63dd853f, 0x63d996f6,
+ 0x63d5a86f, 0x63d1b9aa,
+ 0x63cdcaa8, 0x63c9db68, 0x63c5ebeb, 0x63c1fc30, 0x63be0c37, 0x63ba1c01,
+ 0x63b62b8e, 0x63b23add,
+ 0x63ae49ee, 0x63aa58c2, 0x63a66759, 0x63a275b2, 0x639e83cd, 0x639a91ac,
+ 0x63969f4c, 0x6392acaf,
+ 0x638eb9d5, 0x638ac6be, 0x6386d369, 0x6382dfd6, 0x637eec07, 0x637af7fa,
+ 0x637703af, 0x63730f27,
+ 0x636f1a62, 0x636b2560, 0x63673020, 0x63633aa3, 0x635f44e8, 0x635b4ef0,
+ 0x635758bb, 0x63536249,
+ 0x634f6b99, 0x634b74ad, 0x63477d82, 0x6343861b, 0x633f8e76, 0x633b9695,
+ 0x63379e76, 0x6333a619,
+ 0x632fad80, 0x632bb4a9, 0x6327bb96, 0x6323c245, 0x631fc8b7, 0x631bceeb,
+ 0x6317d4e3, 0x6313da9e,
+ 0x630fe01b, 0x630be55b, 0x6307ea5e, 0x6303ef25, 0x62fff3ae, 0x62fbf7fa,
+ 0x62f7fc08, 0x62f3ffda,
+ 0x62f0036f, 0x62ec06c7, 0x62e809e2, 0x62e40cbf, 0x62e00f60, 0x62dc11c4,
+ 0x62d813eb, 0x62d415d4,
+ 0x62d01781, 0x62cc18f1, 0x62c81a24, 0x62c41b1a, 0x62c01bd3, 0x62bc1c4f,
+ 0x62b81c8f, 0x62b41c91,
+ 0x62b01c57, 0x62ac1bdf, 0x62a81b2b, 0x62a41a3a, 0x62a0190c, 0x629c17a1,
+ 0x629815fa, 0x62941415,
+ 0x629011f4, 0x628c0f96, 0x62880cfb, 0x62840a23, 0x6280070f, 0x627c03be,
+ 0x62780030, 0x6273fc65,
+ 0x626ff85e, 0x626bf41a, 0x6267ef99, 0x6263eadc, 0x625fe5e1, 0x625be0ab,
+ 0x6257db37, 0x6253d587,
+ 0x624fcf9a, 0x624bc970, 0x6247c30a, 0x6243bc68, 0x623fb588, 0x623bae6c,
+ 0x6237a714, 0x62339f7e,
+ 0x622f97ad, 0x622b8f9e, 0x62278754, 0x62237ecc, 0x621f7608, 0x621b6d08,
+ 0x621763cb, 0x62135a51,
+ 0x620f509b, 0x620b46a9, 0x62073c7a, 0x6203320e, 0x61ff2766, 0x61fb1c82,
+ 0x61f71161, 0x61f30604,
+ 0x61eefa6b, 0x61eaee95, 0x61e6e282, 0x61e2d633, 0x61dec9a8, 0x61dabce0,
+ 0x61d6afdd, 0x61d2a29c,
+ 0x61ce9520, 0x61ca8767, 0x61c67971, 0x61c26b40, 0x61be5cd2, 0x61ba4e28,
+ 0x61b63f41, 0x61b2301e,
+ 0x61ae20bf, 0x61aa1124, 0x61a6014d, 0x61a1f139, 0x619de0e9, 0x6199d05d,
+ 0x6195bf94, 0x6191ae90,
+ 0x618d9d4f, 0x61898bd2, 0x61857a19, 0x61816824, 0x617d55f2, 0x61794385,
+ 0x617530db, 0x61711df5,
+ 0x616d0ad3, 0x6168f775, 0x6164e3db, 0x6160d005, 0x615cbbf3, 0x6158a7a4,
+ 0x6154931a, 0x61507e54,
+ 0x614c6951, 0x61485413, 0x61443e98, 0x614028e2, 0x613c12f0, 0x6137fcc1,
+ 0x6133e657, 0x612fcfb0,
+ 0x612bb8ce, 0x6127a1b0, 0x61238a56, 0x611f72c0, 0x611b5aee, 0x611742e0,
+ 0x61132a96, 0x610f1210,
+ 0x610af94f, 0x6106e051, 0x6102c718, 0x60feada3, 0x60fa93f2, 0x60f67a05,
+ 0x60f25fdd, 0x60ee4579,
+ 0x60ea2ad8, 0x60e60ffd, 0x60e1f4e5, 0x60ddd991, 0x60d9be02, 0x60d5a237,
+ 0x60d18631, 0x60cd69ee,
+ 0x60c94d70, 0x60c530b6, 0x60c113c1, 0x60bcf690, 0x60b8d923, 0x60b4bb7a,
+ 0x60b09d96, 0x60ac7f76,
+ 0x60a8611b, 0x60a44284, 0x60a023b1, 0x609c04a3, 0x6097e559, 0x6093c5d3,
+ 0x608fa612, 0x608b8616,
+ 0x608765dd, 0x6083456a, 0x607f24ba, 0x607b03d0, 0x6076e2a9, 0x6072c148,
+ 0x606e9faa, 0x606a7dd2,
+ 0x60665bbd, 0x6062396e, 0x605e16e2, 0x6059f41c, 0x6055d11a, 0x6051addc,
+ 0x604d8a63, 0x604966af,
+ 0x604542bf, 0x60411e94, 0x603cfa2e, 0x6038d58c, 0x6034b0af, 0x60308b97,
+ 0x602c6643, 0x602840b4,
+ 0x60241ae9, 0x601ff4e3, 0x601bcea2, 0x6017a826, 0x6013816e, 0x600f5a7b,
+ 0x600b334d, 0x60070be4,
+ 0x6002e43f, 0x5ffebc5f, 0x5ffa9444, 0x5ff66bee, 0x5ff2435d, 0x5fee1a90,
+ 0x5fe9f188, 0x5fe5c845,
+ 0x5fe19ec7, 0x5fdd750e, 0x5fd94b19, 0x5fd520ea, 0x5fd0f67f, 0x5fcccbd9,
+ 0x5fc8a0f8, 0x5fc475dc,
+ 0x5fc04a85, 0x5fbc1ef3, 0x5fb7f326, 0x5fb3c71e, 0x5faf9adb, 0x5fab6e5d,
+ 0x5fa741a3, 0x5fa314af,
+ 0x5f9ee780, 0x5f9aba16, 0x5f968c70, 0x5f925e90, 0x5f8e3075, 0x5f8a021f,
+ 0x5f85d38e, 0x5f81a4c2,
+ 0x5f7d75bb, 0x5f794679, 0x5f7516fd, 0x5f70e745, 0x5f6cb753, 0x5f688726,
+ 0x5f6456be, 0x5f60261b,
+ 0x5f5bf53d, 0x5f57c424, 0x5f5392d1, 0x5f4f6143, 0x5f4b2f7a, 0x5f46fd76,
+ 0x5f42cb37, 0x5f3e98be,
+ 0x5f3a660a, 0x5f36331b, 0x5f31fff1, 0x5f2dcc8d, 0x5f2998ee, 0x5f256515,
+ 0x5f213100, 0x5f1cfcb1,
+ 0x5f18c827, 0x5f149363, 0x5f105e64, 0x5f0c292a, 0x5f07f3b6, 0x5f03be07,
+ 0x5eff881d, 0x5efb51f9,
+ 0x5ef71b9b, 0x5ef2e501, 0x5eeeae2d, 0x5eea771f, 0x5ee63fd6, 0x5ee20853,
+ 0x5eddd094, 0x5ed9989c,
+ 0x5ed56069, 0x5ed127fb, 0x5eccef53, 0x5ec8b671, 0x5ec47d54, 0x5ec043fc,
+ 0x5ebc0a6a, 0x5eb7d09e,
+ 0x5eb39697, 0x5eaf5c56, 0x5eab21da, 0x5ea6e724, 0x5ea2ac34, 0x5e9e7109,
+ 0x5e9a35a4, 0x5e95fa05,
+ 0x5e91be2b, 0x5e8d8217, 0x5e8945c8, 0x5e85093f, 0x5e80cc7c, 0x5e7c8f7f,
+ 0x5e785247, 0x5e7414d5,
+ 0x5e6fd729, 0x5e6b9943, 0x5e675b22, 0x5e631cc7, 0x5e5ede32, 0x5e5a9f62,
+ 0x5e566059, 0x5e522115,
+ 0x5e4de197, 0x5e49a1df, 0x5e4561ed, 0x5e4121c0, 0x5e3ce15a, 0x5e38a0b9,
+ 0x5e345fde, 0x5e301ec9,
+ 0x5e2bdd7a, 0x5e279bf1, 0x5e235a2e, 0x5e1f1830, 0x5e1ad5f9, 0x5e169388,
+ 0x5e1250dc, 0x5e0e0df7,
+ 0x5e09cad7, 0x5e05877e, 0x5e0143ea, 0x5dfd001d, 0x5df8bc15, 0x5df477d4,
+ 0x5df03359, 0x5debeea3,
+ 0x5de7a9b4, 0x5de3648b, 0x5ddf1f28, 0x5ddad98b, 0x5dd693b4, 0x5dd24da3,
+ 0x5dce0759, 0x5dc9c0d4,
+ 0x5dc57a16, 0x5dc1331d, 0x5dbcebeb, 0x5db8a480, 0x5db45cda, 0x5db014fa,
+ 0x5dabcce1, 0x5da7848e,
+ 0x5da33c01, 0x5d9ef33b, 0x5d9aaa3a, 0x5d966100, 0x5d92178d, 0x5d8dcddf,
+ 0x5d8983f8, 0x5d8539d7,
+ 0x5d80ef7c, 0x5d7ca4e8, 0x5d785a1a, 0x5d740f12, 0x5d6fc3d1, 0x5d6b7856,
+ 0x5d672ca2, 0x5d62e0b4,
+ 0x5d5e948c, 0x5d5a482a, 0x5d55fb90, 0x5d51aebb, 0x5d4d61ad, 0x5d491465,
+ 0x5d44c6e4, 0x5d40792a,
+ 0x5d3c2b35, 0x5d37dd08, 0x5d338ea0, 0x5d2f4000, 0x5d2af125, 0x5d26a212,
+ 0x5d2252c5, 0x5d1e033e,
+ 0x5d19b37e, 0x5d156385, 0x5d111352, 0x5d0cc2e5, 0x5d087240, 0x5d042161,
+ 0x5cffd048, 0x5cfb7ef7,
+ 0x5cf72d6b, 0x5cf2dba7, 0x5cee89a9, 0x5cea3772, 0x5ce5e501, 0x5ce19258,
+ 0x5cdd3f75, 0x5cd8ec58,
+ 0x5cd49903, 0x5cd04574, 0x5ccbf1ab, 0x5cc79daa, 0x5cc3496f, 0x5cbef4fc,
+ 0x5cbaa04f, 0x5cb64b68,
+ 0x5cb1f649, 0x5cada0f0, 0x5ca94b5e, 0x5ca4f594, 0x5ca09f8f, 0x5c9c4952,
+ 0x5c97f2dc, 0x5c939c2c,
+ 0x5c8f4544, 0x5c8aee22, 0x5c8696c7, 0x5c823f34, 0x5c7de767, 0x5c798f61,
+ 0x5c753722, 0x5c70deaa,
+ 0x5c6c85f9, 0x5c682d0f, 0x5c63d3eb, 0x5c5f7a8f, 0x5c5b20fa, 0x5c56c72c,
+ 0x5c526d25, 0x5c4e12e5,
+ 0x5c49b86d, 0x5c455dbb, 0x5c4102d0, 0x5c3ca7ad, 0x5c384c50, 0x5c33f0bb,
+ 0x5c2f94ec, 0x5c2b38e5,
+ 0x5c26dca5, 0x5c22802c, 0x5c1e237b, 0x5c19c690, 0x5c15696d, 0x5c110c11,
+ 0x5c0cae7c, 0x5c0850ae,
+ 0x5c03f2a8, 0x5bff9469, 0x5bfb35f1, 0x5bf6d740, 0x5bf27857, 0x5bee1935,
+ 0x5be9b9da, 0x5be55a46,
+ 0x5be0fa7a, 0x5bdc9a75, 0x5bd83a37, 0x5bd3d9c1, 0x5bcf7912, 0x5bcb182b,
+ 0x5bc6b70b, 0x5bc255b2,
+ 0x5bbdf421, 0x5bb99257, 0x5bb53054, 0x5bb0ce19, 0x5bac6ba6, 0x5ba808f9,
+ 0x5ba3a615, 0x5b9f42f7,
+ 0x5b9adfa2, 0x5b967c13, 0x5b92184d, 0x5b8db44d, 0x5b895016, 0x5b84eba6,
+ 0x5b8086fd, 0x5b7c221c,
+ 0x5b77bd02, 0x5b7357b0, 0x5b6ef226, 0x5b6a8c63, 0x5b662668, 0x5b61c035,
+ 0x5b5d59c9, 0x5b58f324,
+ 0x5b548c48, 0x5b502533, 0x5b4bbde6, 0x5b475660, 0x5b42eea2, 0x5b3e86ac,
+ 0x5b3a1e7e, 0x5b35b617,
+ 0x5b314d78, 0x5b2ce4a1, 0x5b287b91, 0x5b241249, 0x5b1fa8c9, 0x5b1b3f11,
+ 0x5b16d521, 0x5b126af8,
+ 0x5b0e0098, 0x5b0995ff, 0x5b052b2e, 0x5b00c025, 0x5afc54e3, 0x5af7e96a,
+ 0x5af37db8, 0x5aef11cf,
+ 0x5aeaa5ad, 0x5ae63953, 0x5ae1ccc1, 0x5add5ff7, 0x5ad8f2f5, 0x5ad485bb,
+ 0x5ad01849, 0x5acbaa9f,
+ 0x5ac73cbd, 0x5ac2cea3, 0x5abe6050, 0x5ab9f1c6, 0x5ab58304, 0x5ab1140a,
+ 0x5aaca4d8, 0x5aa8356f,
+ 0x5aa3c5cd, 0x5a9f55f3, 0x5a9ae5e2, 0x5a967598, 0x5a920517, 0x5a8d945d,
+ 0x5a89236c, 0x5a84b243,
+ 0x5a8040e3, 0x5a7bcf4a, 0x5a775d7a, 0x5a72eb71, 0x5a6e7931, 0x5a6a06ba,
+ 0x5a65940a, 0x5a612123,
+ 0x5a5cae04, 0x5a583aad, 0x5a53c71e, 0x5a4f5358, 0x5a4adf5a, 0x5a466b24,
+ 0x5a41f6b7, 0x5a3d8212,
+ 0x5a390d35, 0x5a349821, 0x5a3022d5, 0x5a2bad51, 0x5a273796, 0x5a22c1a3,
+ 0x5a1e4b79, 0x5a19d517,
+ 0x5a155e7d, 0x5a10e7ac, 0x5a0c70a3, 0x5a07f963, 0x5a0381eb, 0x59ff0a3c,
+ 0x59fa9255, 0x59f61a36,
+ 0x59f1a1e0, 0x59ed2953, 0x59e8b08e, 0x59e43792, 0x59dfbe5e, 0x59db44f3,
+ 0x59d6cb50, 0x59d25176,
+ 0x59cdd765, 0x59c95d1c, 0x59c4e29c, 0x59c067e4, 0x59bbecf5, 0x59b771cf,
+ 0x59b2f671, 0x59ae7add,
+ 0x59a9ff10, 0x59a5830d, 0x59a106d2, 0x599c8a60, 0x59980db6, 0x599390d5,
+ 0x598f13bd, 0x598a966e,
+ 0x598618e8, 0x59819b2a, 0x597d1d35, 0x59789f09, 0x597420a6, 0x596fa20b,
+ 0x596b233a, 0x5966a431,
+ 0x596224f1, 0x595da57a, 0x595925cc, 0x5954a5e6, 0x595025ca, 0x594ba576,
+ 0x594724ec, 0x5942a42a,
+ 0x593e2331, 0x5939a202, 0x5935209b, 0x59309efd, 0x592c1d28, 0x59279b1c,
+ 0x592318d9, 0x591e9660,
+ 0x591a13af, 0x591590c7, 0x59110da8, 0x590c8a53, 0x590806c6, 0x59038302,
+ 0x58feff08, 0x58fa7ad7,
+ 0x58f5f66e, 0x58f171cf, 0x58ececf9, 0x58e867ed, 0x58e3e2a9, 0x58df5d2e,
+ 0x58dad77d, 0x58d65195,
+ 0x58d1cb76, 0x58cd4520, 0x58c8be94, 0x58c437d1, 0x58bfb0d7, 0x58bb29a6,
+ 0x58b6a23e, 0x58b21aa0,
+ 0x58ad92cb, 0x58a90ac0, 0x58a4827d, 0x589ffa04, 0x589b7155, 0x5896e86f,
+ 0x58925f52, 0x588dd5fe,
+ 0x58894c74, 0x5884c2b3, 0x588038bb, 0x587bae8d, 0x58772429, 0x5872998e,
+ 0x586e0ebc, 0x586983b4,
+ 0x5864f875, 0x58606d00, 0x585be154, 0x58575571, 0x5852c958, 0x584e3d09,
+ 0x5849b083, 0x584523c7,
+ 0x584096d4, 0x583c09ab, 0x58377c4c, 0x5832eeb6, 0x582e60e9, 0x5829d2e6,
+ 0x582544ad, 0x5820b63e,
+ 0x581c2798, 0x581798bb, 0x581309a9, 0x580e7a60, 0x5809eae1, 0x58055b2b,
+ 0x5800cb3f, 0x57fc3b1d,
+ 0x57f7aac5, 0x57f31a36, 0x57ee8971, 0x57e9f876, 0x57e56744, 0x57e0d5dd,
+ 0x57dc443f, 0x57d7b26b,
+ 0x57d32061, 0x57ce8e20, 0x57c9fbaa, 0x57c568fd, 0x57c0d61a, 0x57bc4301,
+ 0x57b7afb2, 0x57b31c2d,
+ 0x57ae8872, 0x57a9f480, 0x57a56059, 0x57a0cbfb, 0x579c3768, 0x5797a29e,
+ 0x57930d9e, 0x578e7869,
+ 0x5789e2fd, 0x57854d5b, 0x5780b784, 0x577c2176, 0x57778b32, 0x5772f4b9,
+ 0x576e5e09, 0x5769c724,
+ 0x57653009, 0x576098b7, 0x575c0130, 0x57576973, 0x5752d180, 0x574e3957,
+ 0x5749a0f9, 0x57450864,
+ 0x57406f9a, 0x573bd69a, 0x57373d64, 0x5732a3f8, 0x572e0a56, 0x5729707f,
+ 0x5724d672, 0x57203c2f,
+ 0x571ba1b7, 0x57170708, 0x57126c24, 0x570dd10a, 0x570935bb, 0x57049a36,
+ 0x56fffe7b, 0x56fb628b,
+ 0x56f6c664, 0x56f22a09, 0x56ed8d77, 0x56e8f0b0, 0x56e453b4, 0x56dfb681,
+ 0x56db1919, 0x56d67b7c,
+ 0x56d1dda9, 0x56cd3fa1, 0x56c8a162, 0x56c402ef, 0x56bf6446, 0x56bac567,
+ 0x56b62653, 0x56b18709,
+ 0x56ace78a, 0x56a847d6, 0x56a3a7ec, 0x569f07cc, 0x569a6777, 0x5695c6ed,
+ 0x5691262d, 0x568c8538,
+ 0x5687e40e, 0x568342ae, 0x567ea118, 0x5679ff4e, 0x56755d4e, 0x5670bb19,
+ 0x566c18ae, 0x5667760e,
+ 0x5662d339, 0x565e302e, 0x56598cee, 0x5654e979, 0x565045cf, 0x564ba1f0,
+ 0x5646fddb, 0x56425991,
+ 0x563db512, 0x5639105d, 0x56346b74, 0x562fc655, 0x562b2101, 0x56267b78,
+ 0x5621d5ba, 0x561d2fc6,
+ 0x5618899e, 0x5613e340, 0x560f3cae, 0x560a95e6, 0x5605eee9, 0x560147b7,
+ 0x55fca050, 0x55f7f8b4,
+ 0x55f350e3, 0x55eea8dd, 0x55ea00a2, 0x55e55832, 0x55e0af8d, 0x55dc06b3,
+ 0x55d75da4, 0x55d2b460,
+ 0x55ce0ae7, 0x55c96139, 0x55c4b757, 0x55c00d3f, 0x55bb62f3, 0x55b6b871,
+ 0x55b20dbb, 0x55ad62d0,
+ 0x55a8b7b0, 0x55a40c5b, 0x559f60d1, 0x559ab513, 0x55960920, 0x55915cf8,
+ 0x558cb09b, 0x55880409,
+ 0x55835743, 0x557eaa48, 0x5579fd18, 0x55754fb3, 0x5570a21a, 0x556bf44c,
+ 0x55674649, 0x55629812,
+ 0x555de9a6, 0x55593b05, 0x55548c30, 0x554fdd26, 0x554b2de7, 0x55467e74,
+ 0x5541cecc, 0x553d1ef0,
+ 0x55386edf, 0x5533be99, 0x552f0e1f, 0x552a5d70, 0x5525ac8d, 0x5520fb75,
+ 0x551c4a29, 0x551798a8,
+ 0x5512e6f3, 0x550e3509, 0x550982eb, 0x5504d099, 0x55001e12, 0x54fb6b56,
+ 0x54f6b866, 0x54f20542,
+ 0x54ed51e9, 0x54e89e5c, 0x54e3ea9a, 0x54df36a5, 0x54da827a, 0x54d5ce1c,
+ 0x54d11989, 0x54cc64c2,
+ 0x54c7afc6, 0x54c2fa96, 0x54be4532, 0x54b98f9a, 0x54b4d9cd, 0x54b023cc,
+ 0x54ab6d97, 0x54a6b72e,
+ 0x54a20090, 0x549d49bf, 0x549892b9, 0x5493db7f, 0x548f2410, 0x548a6c6e,
+ 0x5485b497, 0x5480fc8c,
+ 0x547c444d, 0x54778bda, 0x5472d333, 0x546e1a58, 0x54696149, 0x5464a805,
+ 0x545fee8e, 0x545b34e3,
+ 0x54567b03, 0x5451c0f0, 0x544d06a8, 0x54484c2d, 0x5443917d, 0x543ed699,
+ 0x543a1b82, 0x54356037,
+ 0x5430a4b7, 0x542be904, 0x54272d1d, 0x54227102, 0x541db4b3, 0x5418f830,
+ 0x54143b79, 0x540f7e8e,
+ 0x540ac170, 0x5406041d, 0x54014697, 0x53fc88dd, 0x53f7caef, 0x53f30cce,
+ 0x53ee4e78, 0x53e98fef,
+ 0x53e4d132, 0x53e01242, 0x53db531d, 0x53d693c5, 0x53d1d439, 0x53cd147a,
+ 0x53c85486, 0x53c3945f,
+ 0x53bed405, 0x53ba1377, 0x53b552b5, 0x53b091bf, 0x53abd096, 0x53a70f39,
+ 0x53a24da9, 0x539d8be5,
+ 0x5398c9ed, 0x539407c2, 0x538f4564, 0x538a82d1, 0x5385c00c, 0x5380fd12,
+ 0x537c39e6, 0x53777685,
+ 0x5372b2f2, 0x536def2a, 0x53692b30, 0x53646701, 0x535fa2a0, 0x535ade0b,
+ 0x53561942, 0x53515447,
+ 0x534c8f17, 0x5347c9b5, 0x5343041f, 0x533e3e55, 0x53397859, 0x5334b229,
+ 0x532febc5, 0x532b252f,
+ 0x53265e65, 0x53219767, 0x531cd037, 0x531808d3, 0x5313413c, 0x530e7972,
+ 0x5309b174, 0x5304e943,
+ 0x530020df, 0x52fb5848, 0x52f68f7e, 0x52f1c680, 0x52ecfd4f, 0x52e833ec,
+ 0x52e36a55, 0x52dea08a,
+ 0x52d9d68d, 0x52d50c5d, 0x52d041f9, 0x52cb7763, 0x52c6ac99, 0x52c1e19d,
+ 0x52bd166d, 0x52b84b0a,
+ 0x52b37f74, 0x52aeb3ac, 0x52a9e7b0, 0x52a51b81, 0x52a04f1f, 0x529b828a,
+ 0x5296b5c3, 0x5291e8c8,
+ 0x528d1b9b, 0x52884e3a, 0x528380a7, 0x527eb2e0, 0x5279e4e7, 0x527516bb,
+ 0x5270485c, 0x526b79ca,
+ 0x5266ab06, 0x5261dc0e, 0x525d0ce4, 0x52583d87, 0x52536df7, 0x524e9e34,
+ 0x5249ce3f, 0x5244fe17,
+ 0x52402dbc, 0x523b5d2e, 0x52368c6e, 0x5231bb7b, 0x522cea55, 0x522818fc,
+ 0x52234771, 0x521e75b3,
+ 0x5219a3c3, 0x5214d1a0, 0x520fff4a, 0x520b2cc2, 0x52065a07, 0x52018719,
+ 0x51fcb3f9, 0x51f7e0a6,
+ 0x51f30d21, 0x51ee3969, 0x51e9657e, 0x51e49162, 0x51dfbd12, 0x51dae890,
+ 0x51d613dc, 0x51d13ef5,
+ 0x51cc69db, 0x51c79490, 0x51c2bf11, 0x51bde960, 0x51b9137d, 0x51b43d68,
+ 0x51af6720, 0x51aa90a5,
+ 0x51a5b9f9, 0x51a0e31a, 0x519c0c08, 0x519734c4, 0x51925d4e, 0x518d85a6,
+ 0x5188adcb, 0x5183d5be,
+ 0x517efd7f, 0x517a250d, 0x51754c69, 0x51707393, 0x516b9a8b, 0x5166c150,
+ 0x5161e7e4, 0x515d0e45,
+ 0x51583473, 0x51535a70, 0x514e803b, 0x5149a5d3, 0x5144cb39, 0x513ff06d,
+ 0x513b156f, 0x51363a3f,
+ 0x51315edd, 0x512c8348, 0x5127a782, 0x5122cb8a, 0x511def5f, 0x51191302,
+ 0x51143674, 0x510f59b3,
+ 0x510a7cc1, 0x51059f9c, 0x5100c246, 0x50fbe4bd, 0x50f70703, 0x50f22916,
+ 0x50ed4af8, 0x50e86ca8,
+ 0x50e38e25, 0x50deaf71, 0x50d9d08b, 0x50d4f173, 0x50d0122a, 0x50cb32ae,
+ 0x50c65301, 0x50c17322,
+ 0x50bc9311, 0x50b7b2ce, 0x50b2d259, 0x50adf1b3, 0x50a910db, 0x50a42fd1,
+ 0x509f4e95, 0x509a6d28,
+ 0x50958b88, 0x5090a9b8, 0x508bc7b5, 0x5086e581, 0x5082031b, 0x507d2083,
+ 0x50783dba, 0x50735abf,
+ 0x506e7793, 0x50699435, 0x5064b0a5, 0x505fcce4, 0x505ae8f1, 0x505604cd,
+ 0x50512077, 0x504c3bef,
+ 0x50475736, 0x5042724c, 0x503d8d30, 0x5038a7e2, 0x5033c263, 0x502edcb2,
+ 0x5029f6d1, 0x502510bd,
+ 0x50202a78, 0x501b4402, 0x50165d5a, 0x50117681, 0x500c8f77, 0x5007a83b,
+ 0x5002c0cd, 0x4ffdd92f,
+ 0x4ff8f15f, 0x4ff4095e, 0x4fef212b, 0x4fea38c7, 0x4fe55032, 0x4fe0676c,
+ 0x4fdb7e74, 0x4fd6954b,
+ 0x4fd1abf0, 0x4fccc265, 0x4fc7d8a8, 0x4fc2eeba, 0x4fbe049b, 0x4fb91a4b,
+ 0x4fb42fc9, 0x4faf4517,
+ 0x4faa5a33, 0x4fa56f1e, 0x4fa083d8, 0x4f9b9861, 0x4f96acb8, 0x4f91c0df,
+ 0x4f8cd4d4, 0x4f87e899,
+ 0x4f82fc2c, 0x4f7e0f8f, 0x4f7922c0, 0x4f7435c0, 0x4f6f488f, 0x4f6a5b2e,
+ 0x4f656d9b, 0x4f607fd7,
+ 0x4f5b91e3, 0x4f56a3bd, 0x4f51b566, 0x4f4cc6df, 0x4f47d827, 0x4f42e93d,
+ 0x4f3dfa23, 0x4f390ad8,
+ 0x4f341b5c, 0x4f2f2baf, 0x4f2a3bd2, 0x4f254bc3, 0x4f205b84, 0x4f1b6b14,
+ 0x4f167a73, 0x4f1189a1,
+ 0x4f0c989f, 0x4f07a76b, 0x4f02b608, 0x4efdc473, 0x4ef8d2ad, 0x4ef3e0b7,
+ 0x4eeeee90, 0x4ee9fc39,
+ 0x4ee509b1, 0x4ee016f8, 0x4edb240e, 0x4ed630f4, 0x4ed13da9, 0x4ecc4a2e,
+ 0x4ec75682, 0x4ec262a5,
+ 0x4ebd6e98, 0x4eb87a5a, 0x4eb385ec, 0x4eae914d, 0x4ea99c7d, 0x4ea4a77d,
+ 0x4e9fb24d, 0x4e9abcec,
+ 0x4e95c75b, 0x4e90d199, 0x4e8bdba6, 0x4e86e583, 0x4e81ef30, 0x4e7cf8ac,
+ 0x4e7801f8, 0x4e730b14,
+ 0x4e6e13ff, 0x4e691cba, 0x4e642544, 0x4e5f2d9e, 0x4e5a35c7, 0x4e553dc1,
+ 0x4e50458a, 0x4e4b4d22,
+ 0x4e46548b, 0x4e415bc3, 0x4e3c62cb, 0x4e3769a2, 0x4e32704a, 0x4e2d76c1,
+ 0x4e287d08, 0x4e23831e,
+ 0x4e1e8905, 0x4e198ebb, 0x4e149441, 0x4e0f9997, 0x4e0a9ebd, 0x4e05a3b2,
+ 0x4e00a878, 0x4dfbad0d,
+ 0x4df6b173, 0x4df1b5a8, 0x4decb9ad, 0x4de7bd82, 0x4de2c127, 0x4dddc49c,
+ 0x4dd8c7e1, 0x4dd3caf6,
+ 0x4dcecdda, 0x4dc9d08f, 0x4dc4d314, 0x4dbfd569, 0x4dbad78e, 0x4db5d983,
+ 0x4db0db48, 0x4dabdcdd,
+ 0x4da6de43, 0x4da1df78, 0x4d9ce07d, 0x4d97e153, 0x4d92e1f9, 0x4d8de26f,
+ 0x4d88e2b5, 0x4d83e2cb,
+ 0x4d7ee2b1, 0x4d79e268, 0x4d74e1ef, 0x4d6fe146, 0x4d6ae06d, 0x4d65df64,
+ 0x4d60de2c, 0x4d5bdcc4,
+ 0x4d56db2d, 0x4d51d965, 0x4d4cd76e, 0x4d47d547, 0x4d42d2f1, 0x4d3dd06b,
+ 0x4d38cdb5, 0x4d33cad0,
+ 0x4d2ec7bb, 0x4d29c476, 0x4d24c102, 0x4d1fbd5e, 0x4d1ab98b, 0x4d15b588,
+ 0x4d10b155, 0x4d0bacf3,
+ 0x4d06a862, 0x4d01a3a0, 0x4cfc9eb0, 0x4cf79990, 0x4cf29440, 0x4ced8ec1,
+ 0x4ce88913, 0x4ce38335,
+ 0x4cde7d28, 0x4cd976eb, 0x4cd4707f, 0x4ccf69e3, 0x4cca6318, 0x4cc55c1e,
+ 0x4cc054f4, 0x4cbb4d9b,
+ 0x4cb64613, 0x4cb13e5b, 0x4cac3674, 0x4ca72e5e, 0x4ca22619, 0x4c9d1da4,
+ 0x4c981500, 0x4c930c2d,
+ 0x4c8e032a, 0x4c88f9f8, 0x4c83f097, 0x4c7ee707, 0x4c79dd48, 0x4c74d359,
+ 0x4c6fc93b, 0x4c6abeef,
+ 0x4c65b473, 0x4c60a9c8, 0x4c5b9eed, 0x4c5693e4, 0x4c5188ac, 0x4c4c7d44,
+ 0x4c4771ae, 0x4c4265e8,
+ 0x4c3d59f3, 0x4c384dd0, 0x4c33417d, 0x4c2e34fb, 0x4c29284b, 0x4c241b6b,
+ 0x4c1f0e5c, 0x4c1a011f,
+ 0x4c14f3b2, 0x4c0fe617, 0x4c0ad84c, 0x4c05ca53, 0x4c00bc2b, 0x4bfbadd4,
+ 0x4bf69f4e, 0x4bf19099,
+ 0x4bec81b5, 0x4be772a3, 0x4be26362, 0x4bdd53f2, 0x4bd84453, 0x4bd33485,
+ 0x4bce2488, 0x4bc9145d,
+ 0x4bc40403, 0x4bbef37b, 0x4bb9e2c3, 0x4bb4d1dd, 0x4bafc0c8, 0x4baaaf85,
+ 0x4ba59e12, 0x4ba08c72,
+ 0x4b9b7aa2, 0x4b9668a4, 0x4b915677, 0x4b8c441c, 0x4b873192, 0x4b821ed9,
+ 0x4b7d0bf2, 0x4b77f8dc,
+ 0x4b72e598, 0x4b6dd225, 0x4b68be84, 0x4b63aab4, 0x4b5e96b6, 0x4b598289,
+ 0x4b546e2d, 0x4b4f59a4,
+ 0x4b4a44eb, 0x4b453005, 0x4b401aef, 0x4b3b05ac, 0x4b35f03a, 0x4b30da9a,
+ 0x4b2bc4cb, 0x4b26aece,
+ 0x4b2198a2, 0x4b1c8248, 0x4b176bc0, 0x4b12550a, 0x4b0d3e25, 0x4b082712,
+ 0x4b030fd1, 0x4afdf861,
+ 0x4af8e0c3, 0x4af3c8f7, 0x4aeeb0fd, 0x4ae998d4, 0x4ae4807d, 0x4adf67f8,
+ 0x4ada4f45, 0x4ad53664,
+ 0x4ad01d54, 0x4acb0417, 0x4ac5eaab, 0x4ac0d111, 0x4abbb749, 0x4ab69d53,
+ 0x4ab1832f, 0x4aac68dc,
+ 0x4aa74e5c, 0x4aa233ae, 0x4a9d18d1, 0x4a97fdc7, 0x4a92e28e, 0x4a8dc728,
+ 0x4a88ab93, 0x4a838fd1,
+ 0x4a7e73e0, 0x4a7957c2, 0x4a743b76, 0x4a6f1efc, 0x4a6a0253, 0x4a64e57d,
+ 0x4a5fc879, 0x4a5aab48,
+ 0x4a558de8, 0x4a50705a, 0x4a4b529f, 0x4a4634b6, 0x4a41169f, 0x4a3bf85a,
+ 0x4a36d9e7, 0x4a31bb47,
+ 0x4a2c9c79, 0x4a277d7d, 0x4a225e53, 0x4a1d3efc, 0x4a181f77, 0x4a12ffc4,
+ 0x4a0ddfe4, 0x4a08bfd5,
+ 0x4a039f9a, 0x49fe7f30, 0x49f95e99, 0x49f43dd4, 0x49ef1ce2, 0x49e9fbc2,
+ 0x49e4da74, 0x49dfb8f9,
+ 0x49da9750, 0x49d5757a, 0x49d05376, 0x49cb3145, 0x49c60ee6, 0x49c0ec59,
+ 0x49bbc9a0, 0x49b6a6b8,
+ 0x49b183a3, 0x49ac6061, 0x49a73cf1, 0x49a21954, 0x499cf589, 0x4997d191,
+ 0x4992ad6c, 0x498d8919,
+ 0x49886499, 0x49833fec, 0x497e1b11, 0x4978f609, 0x4973d0d3, 0x496eab70,
+ 0x496985e0, 0x49646023,
+ 0x495f3a38, 0x495a1420, 0x4954eddb, 0x494fc768, 0x494aa0c9, 0x494579fc,
+ 0x49405302, 0x493b2bdb,
+ 0x49360486, 0x4930dd05, 0x492bb556, 0x49268d7a, 0x49216571, 0x491c3d3b,
+ 0x491714d8, 0x4911ec47,
+ 0x490cc38a, 0x49079aa0, 0x49027188, 0x48fd4844, 0x48f81ed2, 0x48f2f534,
+ 0x48edcb68, 0x48e8a170,
+ 0x48e3774a, 0x48de4cf8, 0x48d92278, 0x48d3f7cc, 0x48ceccf3, 0x48c9a1ed,
+ 0x48c476b9, 0x48bf4b59,
+ 0x48ba1fcd, 0x48b4f413, 0x48afc82c, 0x48aa9c19, 0x48a56fd9, 0x48a0436c,
+ 0x489b16d2, 0x4895ea0b,
+ 0x4890bd18, 0x488b8ff8, 0x488662ab, 0x48813531, 0x487c078b, 0x4876d9b8,
+ 0x4871abb8, 0x486c7d8c,
+ 0x48674f33, 0x486220ad, 0x485cf1fa, 0x4857c31b, 0x48529410, 0x484d64d7,
+ 0x48483572, 0x484305e1,
+ 0x483dd623, 0x4838a638, 0x48337621, 0x482e45dd, 0x4829156d, 0x4823e4d0,
+ 0x481eb407, 0x48198311,
+ 0x481451ef, 0x480f20a0, 0x4809ef25, 0x4804bd7e, 0x47ff8baa, 0x47fa59a9,
+ 0x47f5277d, 0x47eff523,
+ 0x47eac29e, 0x47e58fec, 0x47e05d0e, 0x47db2a03, 0x47d5f6cc, 0x47d0c369,
+ 0x47cb8fd9, 0x47c65c1d,
+ 0x47c12835, 0x47bbf421, 0x47b6bfe0, 0x47b18b74, 0x47ac56da, 0x47a72215,
+ 0x47a1ed24, 0x479cb806,
+ 0x479782bc, 0x47924d46, 0x478d17a4, 0x4787e1d6, 0x4782abdb, 0x477d75b5,
+ 0x47783f62, 0x477308e3,
+ 0x476dd239, 0x47689b62, 0x4763645f, 0x475e2d30, 0x4758f5d5, 0x4753be4e,
+ 0x474e869b, 0x47494ebc,
+ 0x474416b1, 0x473ede7a, 0x4739a617, 0x47346d89, 0x472f34ce, 0x4729fbe7,
+ 0x4724c2d5, 0x471f8996,
+ 0x471a502c, 0x47151696, 0x470fdcd4, 0x470aa2e6, 0x470568cd, 0x47002e87,
+ 0x46faf416, 0x46f5b979,
+ 0x46f07eb0, 0x46eb43bc, 0x46e6089b, 0x46e0cd4f, 0x46db91d8, 0x46d65634,
+ 0x46d11a65, 0x46cbde6a,
+ 0x46c6a244, 0x46c165f1, 0x46bc2974, 0x46b6ecca, 0x46b1aff5, 0x46ac72f4,
+ 0x46a735c8, 0x46a1f870,
+ 0x469cbaed, 0x46977d3e, 0x46923f63, 0x468d015d, 0x4687c32c, 0x468284cf,
+ 0x467d4646, 0x46780792,
+ 0x4672c8b3, 0x466d89a8, 0x46684a71, 0x46630b0f, 0x465dcb82, 0x46588bc9,
+ 0x46534be5, 0x464e0bd6,
+ 0x4648cb9b, 0x46438b35, 0x463e4aa3, 0x463909e7, 0x4633c8fe, 0x462e87eb,
+ 0x462946ac, 0x46240542,
+ 0x461ec3ad, 0x461981ec, 0x46144001, 0x460efde9, 0x4609bba7, 0x4604793a,
+ 0x45ff36a1, 0x45f9f3dd,
+ 0x45f4b0ee, 0x45ef6dd4, 0x45ea2a8f, 0x45e4e71f, 0x45dfa383, 0x45da5fbc,
+ 0x45d51bcb, 0x45cfd7ae,
+ 0x45ca9366, 0x45c54ef3, 0x45c00a55, 0x45bac58c, 0x45b58098, 0x45b03b79,
+ 0x45aaf630, 0x45a5b0bb,
+ 0x45a06b1b, 0x459b2550, 0x4595df5a, 0x45909939, 0x458b52ee, 0x45860c77,
+ 0x4580c5d6, 0x457b7f0a,
+ 0x45763813, 0x4570f0f1, 0x456ba9a4, 0x4566622c, 0x45611a8a, 0x455bd2bc,
+ 0x45568ac4, 0x455142a2,
+ 0x454bfa54, 0x4546b1dc, 0x45416939, 0x453c206b, 0x4536d773, 0x45318e4f,
+ 0x452c4502, 0x4526fb89,
+ 0x4521b1e6, 0x451c6818, 0x45171e20, 0x4511d3fd, 0x450c89af, 0x45073f37,
+ 0x4501f494, 0x44fca9c6,
+ 0x44f75ecf, 0x44f213ac, 0x44ecc85f, 0x44e77ce7, 0x44e23145, 0x44dce579,
+ 0x44d79982, 0x44d24d60,
+ 0x44cd0114, 0x44c7b49e, 0x44c267fd, 0x44bd1b32, 0x44b7ce3c, 0x44b2811c,
+ 0x44ad33d2, 0x44a7e65d,
+ 0x44a298be, 0x449d4af5, 0x4497fd01, 0x4492aee3, 0x448d609b, 0x44881228,
+ 0x4482c38b, 0x447d74c4,
+ 0x447825d2, 0x4472d6b7, 0x446d8771, 0x44683801, 0x4462e866, 0x445d98a2,
+ 0x445848b3, 0x4452f89b,
+ 0x444da858, 0x444857ea, 0x44430753, 0x443db692, 0x443865a7, 0x44331491,
+ 0x442dc351, 0x442871e8,
+ 0x44232054, 0x441dce96, 0x44187caf, 0x44132a9d, 0x440dd861, 0x440885fc,
+ 0x4403336c, 0x43fde0b2,
+ 0x43f88dcf, 0x43f33ac1, 0x43ede78a, 0x43e89429, 0x43e3409d, 0x43ddece8,
+ 0x43d8990a, 0x43d34501,
+ 0x43cdf0ce, 0x43c89c72, 0x43c347eb, 0x43bdf33b, 0x43b89e62, 0x43b3495e,
+ 0x43adf431, 0x43a89ed9,
+ 0x43a34959, 0x439df3ae, 0x43989dda, 0x439347dc, 0x438df1b4, 0x43889b63,
+ 0x438344e8, 0x437dee43,
+ 0x43789775, 0x4373407d, 0x436de95b, 0x43689210, 0x43633a9c, 0x435de2fd,
+ 0x43588b36, 0x43533344,
+ 0x434ddb29, 0x434882e5, 0x43432a77, 0x433dd1e0, 0x4338791f, 0x43332035,
+ 0x432dc721, 0x43286de4,
+ 0x4323147d, 0x431dbaed, 0x43186133, 0x43130751, 0x430dad44, 0x4308530f,
+ 0x4302f8b0, 0x42fd9e28,
+ 0x42f84376, 0x42f2e89b, 0x42ed8d97, 0x42e83269, 0x42e2d713, 0x42dd7b93,
+ 0x42d81fe9, 0x42d2c417,
+ 0x42cd681b, 0x42c80bf6, 0x42c2afa8, 0x42bd5331, 0x42b7f690, 0x42b299c7,
+ 0x42ad3cd4, 0x42a7dfb8,
+ 0x42a28273, 0x429d2505, 0x4297c76e, 0x429269ae, 0x428d0bc4, 0x4287adb2,
+ 0x42824f76, 0x427cf112,
+ 0x42779285, 0x427233ce, 0x426cd4ef, 0x426775e6, 0x426216b5, 0x425cb75a,
+ 0x425757d7, 0x4251f82b,
+ 0x424c9856, 0x42473858, 0x4241d831, 0x423c77e1, 0x42371769, 0x4231b6c7,
+ 0x422c55fd, 0x4226f50a,
+ 0x422193ee, 0x421c32a9, 0x4216d13c, 0x42116fa5, 0x420c0de6, 0x4206abfe,
+ 0x420149ee, 0x41fbe7b5,
+ 0x41f68553, 0x41f122c8, 0x41ebc015, 0x41e65d39, 0x41e0fa35, 0x41db9707,
+ 0x41d633b1, 0x41d0d033,
+ 0x41cb6c8c, 0x41c608bc, 0x41c0a4c4, 0x41bb40a3, 0x41b5dc5a, 0x41b077e8,
+ 0x41ab134e, 0x41a5ae8b,
+ 0x41a049a0, 0x419ae48c, 0x41957f4f, 0x419019eb, 0x418ab45d, 0x41854ea8,
+ 0x417fe8ca, 0x417a82c3,
+ 0x41751c94, 0x416fb63d, 0x416a4fbd, 0x4164e916, 0x415f8245, 0x415a1b4d,
+ 0x4154b42c, 0x414f4ce2,
+ 0x4149e571, 0x41447dd7, 0x413f1615, 0x4139ae2b, 0x41344618, 0x412edddd,
+ 0x4129757b, 0x41240cef,
+ 0x411ea43c, 0x41193b61, 0x4113d25d, 0x410e6931, 0x4108ffdd, 0x41039661,
+ 0x40fe2cbd, 0x40f8c2f1,
+ 0x40f358fc, 0x40edeee0, 0x40e8849b, 0x40e31a2f, 0x40ddaf9b, 0x40d844de,
+ 0x40d2d9f9, 0x40cd6eed,
+ 0x40c803b8, 0x40c2985c, 0x40bd2cd8, 0x40b7c12b, 0x40b25557, 0x40ace95b,
+ 0x40a77d37, 0x40a210eb,
+ 0x409ca477, 0x409737dc, 0x4091cb18, 0x408c5e2d, 0x4086f11a, 0x408183df,
+ 0x407c167c, 0x4076a8f1,
+ 0x40713b3f, 0x406bcd65, 0x40665f63, 0x4060f13a, 0x405b82e9, 0x40561470,
+ 0x4050a5cf, 0x404b3707,
+ 0x4045c817, 0x404058ff, 0x403ae9c0, 0x40357a59, 0x40300acb, 0x402a9b15,
+ 0x40252b37, 0x401fbb32,
+ 0x401a4b05, 0x4014dab1, 0x400f6a35, 0x4009f992, 0x400488c7, 0x3fff17d5,
+ 0x3ff9a6bb, 0x3ff4357a,
+ 0x3feec411, 0x3fe95281, 0x3fe3e0c9, 0x3fde6eeb, 0x3fd8fce4, 0x3fd38ab6,
+ 0x3fce1861, 0x3fc8a5e5,
+ 0x3fc33341, 0x3fbdc076, 0x3fb84d83, 0x3fb2da6a, 0x3fad6729, 0x3fa7f3c0,
+ 0x3fa28031, 0x3f9d0c7a,
+ 0x3f97989c, 0x3f922496, 0x3f8cb06a, 0x3f873c16, 0x3f81c79b, 0x3f7c52f9,
+ 0x3f76de30, 0x3f71693f,
+ 0x3f6bf428, 0x3f667ee9, 0x3f610983, 0x3f5b93f6, 0x3f561e42, 0x3f50a867,
+ 0x3f4b3265, 0x3f45bc3c,
+ 0x3f4045ec, 0x3f3acf75, 0x3f3558d7, 0x3f2fe211, 0x3f2a6b25, 0x3f24f412,
+ 0x3f1f7cd8, 0x3f1a0577,
+ 0x3f148def, 0x3f0f1640, 0x3f099e6b, 0x3f04266e, 0x3efeae4a, 0x3ef93600,
+ 0x3ef3bd8f, 0x3eee44f7,
+ 0x3ee8cc38, 0x3ee35352, 0x3eddda46, 0x3ed86113, 0x3ed2e7b9, 0x3ecd6e38,
+ 0x3ec7f491, 0x3ec27ac2,
+ 0x3ebd00cd, 0x3eb786b2, 0x3eb20c6f, 0x3eac9206, 0x3ea71777, 0x3ea19cc1,
+ 0x3e9c21e4, 0x3e96a6e0,
+ 0x3e912bb6, 0x3e8bb065, 0x3e8634ee, 0x3e80b950, 0x3e7b3d8c, 0x3e75c1a1,
+ 0x3e70458f, 0x3e6ac957,
+ 0x3e654cf8, 0x3e5fd073, 0x3e5a53c8, 0x3e54d6f6, 0x3e4f59fe, 0x3e49dcdf,
+ 0x3e445f99, 0x3e3ee22e,
+ 0x3e39649c, 0x3e33e6e3, 0x3e2e6904, 0x3e28eaff, 0x3e236cd4, 0x3e1dee82,
+ 0x3e18700a, 0x3e12f16b,
+ 0x3e0d72a6, 0x3e07f3bb, 0x3e0274aa, 0x3dfcf572, 0x3df77615, 0x3df1f691,
+ 0x3dec76e6, 0x3de6f716,
+ 0x3de1771f, 0x3ddbf703, 0x3dd676c0, 0x3dd0f656, 0x3dcb75c7, 0x3dc5f512,
+ 0x3dc07436, 0x3dbaf335,
+ 0x3db5720d, 0x3daff0c0, 0x3daa6f4c, 0x3da4edb2, 0x3d9f6bf2, 0x3d99ea0d,
+ 0x3d946801, 0x3d8ee5cf,
+ 0x3d896377, 0x3d83e0f9, 0x3d7e5e56, 0x3d78db8c, 0x3d73589d, 0x3d6dd587,
+ 0x3d68524c, 0x3d62ceeb,
+ 0x3d5d4b64, 0x3d57c7b7, 0x3d5243e4, 0x3d4cbfeb, 0x3d473bcd, 0x3d41b789,
+ 0x3d3c331f, 0x3d36ae8f,
+ 0x3d3129da, 0x3d2ba4fe, 0x3d261ffd, 0x3d209ad7, 0x3d1b158a, 0x3d159018,
+ 0x3d100a80, 0x3d0a84c3,
+ 0x3d04fee0, 0x3cff78d7, 0x3cf9f2a9, 0x3cf46c55, 0x3ceee5db, 0x3ce95f3c,
+ 0x3ce3d877, 0x3cde518d,
+ 0x3cd8ca7d, 0x3cd34347, 0x3ccdbbed, 0x3cc8346c, 0x3cc2acc6, 0x3cbd24fb,
+ 0x3cb79d0a, 0x3cb214f4,
+ 0x3cac8cb8, 0x3ca70457, 0x3ca17bd0, 0x3c9bf324, 0x3c966a53, 0x3c90e15c,
+ 0x3c8b5840, 0x3c85cefe,
+ 0x3c804598, 0x3c7abc0c, 0x3c75325a, 0x3c6fa883, 0x3c6a1e87, 0x3c649466,
+ 0x3c5f0a20, 0x3c597fb4,
+ 0x3c53f523, 0x3c4e6a6d, 0x3c48df91, 0x3c435491, 0x3c3dc96b, 0x3c383e20,
+ 0x3c32b2b0, 0x3c2d271b,
+ 0x3c279b61, 0x3c220f81, 0x3c1c837d, 0x3c16f753, 0x3c116b04, 0x3c0bde91,
+ 0x3c0651f8, 0x3c00c53a,
+ 0x3bfb3857, 0x3bf5ab50, 0x3bf01e23, 0x3bea90d1, 0x3be5035a, 0x3bdf75bf,
+ 0x3bd9e7fe, 0x3bd45a19,
+ 0x3bcecc0e, 0x3bc93ddf, 0x3bc3af8b, 0x3bbe2112, 0x3bb89274, 0x3bb303b1,
+ 0x3bad74c9, 0x3ba7e5bd,
+ 0x3ba2568c, 0x3b9cc736, 0x3b9737bb, 0x3b91a81c, 0x3b8c1857, 0x3b86886e,
+ 0x3b80f861, 0x3b7b682e,
+ 0x3b75d7d7, 0x3b70475c, 0x3b6ab6bb, 0x3b6525f6, 0x3b5f950c, 0x3b5a03fe,
+ 0x3b5472cb, 0x3b4ee173,
+ 0x3b494ff7, 0x3b43be57, 0x3b3e2c91, 0x3b389aa8, 0x3b330899, 0x3b2d7666,
+ 0x3b27e40f, 0x3b225193,
+ 0x3b1cbef3, 0x3b172c2e, 0x3b119945, 0x3b0c0637, 0x3b067305, 0x3b00dfaf,
+ 0x3afb4c34, 0x3af5b894,
+ 0x3af024d1, 0x3aea90e9, 0x3ae4fcdc, 0x3adf68ac, 0x3ad9d457, 0x3ad43fdd,
+ 0x3aceab40, 0x3ac9167e,
+ 0x3ac38198, 0x3abdec8d, 0x3ab8575f, 0x3ab2c20c, 0x3aad2c95, 0x3aa796fa,
+ 0x3aa2013a, 0x3a9c6b57,
+ 0x3a96d54f, 0x3a913f23, 0x3a8ba8d3, 0x3a86125f, 0x3a807bc7, 0x3a7ae50a,
+ 0x3a754e2a, 0x3a6fb726,
+ 0x3a6a1ffd, 0x3a6488b1, 0x3a5ef140, 0x3a5959ab, 0x3a53c1f3, 0x3a4e2a16,
+ 0x3a489216, 0x3a42f9f2,
+ 0x3a3d61a9, 0x3a37c93d, 0x3a3230ad, 0x3a2c97f9, 0x3a26ff21, 0x3a216625,
+ 0x3a1bcd05, 0x3a1633c1,
+ 0x3a109a5a, 0x3a0b00cf, 0x3a056720, 0x39ffcd4d, 0x39fa3356, 0x39f4993c,
+ 0x39eefefe, 0x39e9649c,
+ 0x39e3ca17, 0x39de2f6d, 0x39d894a0, 0x39d2f9b0, 0x39cd5e9b, 0x39c7c363,
+ 0x39c22808, 0x39bc8c89,
+ 0x39b6f0e6, 0x39b1551f, 0x39abb935, 0x39a61d28, 0x39a080f6, 0x399ae4a2,
+ 0x39954829, 0x398fab8e,
+ 0x398a0ece, 0x398471ec, 0x397ed4e5, 0x397937bc, 0x39739a6e, 0x396dfcfe,
+ 0x39685f6a, 0x3962c1b2,
+ 0x395d23d7, 0x395785d9, 0x3951e7b8, 0x394c4973, 0x3946ab0a, 0x39410c7f,
+ 0x393b6dd0, 0x3935cefd,
+ 0x39303008, 0x392a90ef, 0x3924f1b3, 0x391f5254, 0x3919b2d1, 0x3914132b,
+ 0x390e7362, 0x3908d376,
+ 0x39033367, 0x38fd9334, 0x38f7f2de, 0x38f25266, 0x38ecb1ca, 0x38e7110a,
+ 0x38e17028, 0x38dbcf23,
+ 0x38d62dfb, 0x38d08caf, 0x38caeb41, 0x38c549af, 0x38bfa7fb, 0x38ba0623,
+ 0x38b46429, 0x38aec20b,
+ 0x38a91fcb, 0x38a37d67, 0x389ddae1, 0x38983838, 0x3892956c, 0x388cf27d,
+ 0x38874f6b, 0x3881ac36,
+ 0x387c08de, 0x38766564, 0x3870c1c6, 0x386b1e06, 0x38657a23, 0x385fd61d,
+ 0x385a31f5, 0x38548daa,
+ 0x384ee93b, 0x384944ab, 0x38439ff7, 0x383dfb21, 0x38385628, 0x3832b10d,
+ 0x382d0bce, 0x3827666d,
+ 0x3821c0ea, 0x381c1b44, 0x3816757b, 0x3810cf90, 0x380b2982, 0x38058351,
+ 0x37ffdcfe, 0x37fa3688,
+ 0x37f48ff0, 0x37eee936, 0x37e94259, 0x37e39b59, 0x37ddf437, 0x37d84cf2,
+ 0x37d2a58b, 0x37ccfe02,
+ 0x37c75656, 0x37c1ae87, 0x37bc0697, 0x37b65e84, 0x37b0b64e, 0x37ab0df6,
+ 0x37a5657c, 0x379fbce0,
+ 0x379a1421, 0x37946b40, 0x378ec23d, 0x37891917, 0x37836fcf, 0x377dc665,
+ 0x37781cd9, 0x3772732a,
+ 0x376cc959, 0x37671f66, 0x37617551, 0x375bcb1a, 0x375620c1, 0x37507645,
+ 0x374acba7, 0x374520e7,
+ 0x373f7606, 0x3739cb02, 0x37341fdc, 0x372e7493, 0x3728c929, 0x37231d9d,
+ 0x371d71ef, 0x3717c61f,
+ 0x37121a2d, 0x370c6e19, 0x3706c1e2, 0x3701158a, 0x36fb6910, 0x36f5bc75,
+ 0x36f00fb7, 0x36ea62d7,
+ 0x36e4b5d6, 0x36df08b2, 0x36d95b6d, 0x36d3ae06, 0x36ce007d, 0x36c852d2,
+ 0x36c2a506, 0x36bcf718,
+ 0x36b74908, 0x36b19ad6, 0x36abec82, 0x36a63e0d, 0x36a08f76, 0x369ae0bd,
+ 0x369531e3, 0x368f82e7,
+ 0x3689d3c9, 0x3684248a, 0x367e7529, 0x3678c5a7, 0x36731602, 0x366d663d,
+ 0x3667b655, 0x3662064c,
+ 0x365c5622, 0x3656a5d6, 0x3650f569, 0x364b44da, 0x36459429, 0x363fe357,
+ 0x363a3264, 0x3634814f,
+ 0x362ed019, 0x36291ec1, 0x36236d48, 0x361dbbad, 0x361809f1, 0x36125814,
+ 0x360ca615, 0x3606f3f5,
+ 0x360141b4, 0x35fb8f52, 0x35f5dcce, 0x35f02a28, 0x35ea7762, 0x35e4c47a,
+ 0x35df1171, 0x35d95e47,
+ 0x35d3aafc, 0x35cdf78f, 0x35c84401, 0x35c29052, 0x35bcdc82, 0x35b72891,
+ 0x35b1747e, 0x35abc04b,
+ 0x35a60bf6, 0x35a05781, 0x359aa2ea, 0x3594ee32, 0x358f3959, 0x3589845f,
+ 0x3583cf44, 0x357e1a08,
+ 0x357864ab, 0x3572af2d, 0x356cf98e, 0x356743ce, 0x35618ded, 0x355bd7eb,
+ 0x355621c9, 0x35506b85,
+ 0x354ab520, 0x3544fe9b, 0x353f47f5, 0x3539912e, 0x3533da46, 0x352e233d,
+ 0x35286c14, 0x3522b4c9,
+ 0x351cfd5e, 0x351745d2, 0x35118e26, 0x350bd658, 0x35061e6a, 0x3500665c,
+ 0x34faae2c, 0x34f4f5dc,
+ 0x34ef3d6b, 0x34e984da, 0x34e3cc28, 0x34de1355, 0x34d85a62, 0x34d2a14e,
+ 0x34cce819, 0x34c72ec4,
+ 0x34c1754e, 0x34bbbbb8, 0x34b60202, 0x34b0482a, 0x34aa8e33, 0x34a4d41a,
+ 0x349f19e2, 0x34995f88,
+ 0x3493a50f, 0x348dea75, 0x34882fba, 0x348274e0, 0x347cb9e4, 0x3476fec9,
+ 0x3471438d, 0x346b8830,
+ 0x3465ccb4, 0x34601117, 0x345a5559, 0x3454997c, 0x344edd7e, 0x34492160,
+ 0x34436521, 0x343da8c3,
+ 0x3437ec44, 0x34322fa5, 0x342c72e6, 0x3426b606, 0x3420f907, 0x341b3be7,
+ 0x34157ea7, 0x340fc147,
+ 0x340a03c7, 0x34044626, 0x33fe8866, 0x33f8ca86, 0x33f30c85, 0x33ed4e65,
+ 0x33e79024, 0x33e1d1c4,
+ 0x33dc1343, 0x33d654a2, 0x33d095e2, 0x33cad701, 0x33c51801, 0x33bf58e1,
+ 0x33b999a0, 0x33b3da40,
+ 0x33ae1ac0, 0x33a85b20, 0x33a29b60, 0x339cdb81, 0x33971b81, 0x33915b62,
+ 0x338b9b22, 0x3385dac4,
+ 0x33801a45, 0x337a59a6, 0x337498e8, 0x336ed80a, 0x3369170c, 0x336355ef,
+ 0x335d94b2, 0x3357d355,
+ 0x335211d8, 0x334c503c, 0x33468e80, 0x3340cca5, 0x333b0aaa, 0x3335488f,
+ 0x332f8655, 0x3329c3fb,
+ 0x33240182, 0x331e3ee9, 0x33187c31, 0x3312b959, 0x330cf661, 0x3307334a,
+ 0x33017014, 0x32fbacbe,
+ 0x32f5e948, 0x32f025b4, 0x32ea61ff, 0x32e49e2c, 0x32deda39, 0x32d91626,
+ 0x32d351f5, 0x32cd8da4,
+ 0x32c7c933, 0x32c204a3, 0x32bc3ff4, 0x32b67b26, 0x32b0b638, 0x32aaf12b,
+ 0x32a52bff, 0x329f66b4,
+ 0x3299a149, 0x3293dbbf, 0x328e1616, 0x3288504e, 0x32828a67, 0x327cc460,
+ 0x3276fe3a, 0x327137f6,
+ 0x326b7192, 0x3265ab0f, 0x325fe46c, 0x325a1dab, 0x325456cb, 0x324e8fcc,
+ 0x3248c8ad, 0x32430170,
+ 0x323d3a14, 0x32377298, 0x3231aafe, 0x322be345, 0x32261b6c, 0x32205375,
+ 0x321a8b5f, 0x3214c32a,
+ 0x320efad6, 0x32093263, 0x320369d2, 0x31fda121, 0x31f7d852, 0x31f20f64,
+ 0x31ec4657, 0x31e67d2b,
+ 0x31e0b3e0, 0x31daea77, 0x31d520ef, 0x31cf5748, 0x31c98d83, 0x31c3c39e,
+ 0x31bdf99b, 0x31b82f7a,
+ 0x31b2653a, 0x31ac9adb, 0x31a6d05d, 0x31a105c1, 0x319b3b06, 0x3195702d,
+ 0x318fa535, 0x3189da1e,
+ 0x31840ee9, 0x317e4395, 0x31787823, 0x3172ac92, 0x316ce0e3, 0x31671515,
+ 0x31614929, 0x315b7d1e,
+ 0x3155b0f5, 0x314fe4ae, 0x314a1848, 0x31444bc3, 0x313e7f21, 0x3138b260,
+ 0x3132e580, 0x312d1882,
+ 0x31274b66, 0x31217e2c, 0x311bb0d3, 0x3115e35c, 0x311015c6, 0x310a4813,
+ 0x31047a41, 0x30feac51,
+ 0x30f8de42, 0x30f31016, 0x30ed41cb, 0x30e77362, 0x30e1a4db, 0x30dbd636,
+ 0x30d60772, 0x30d03891,
+ 0x30ca6991, 0x30c49a74, 0x30becb38, 0x30b8fbde, 0x30b32c66, 0x30ad5cd0,
+ 0x30a78d1c, 0x30a1bd4a,
+ 0x309bed5a, 0x30961d4c, 0x30904d20, 0x308a7cd6, 0x3084ac6e, 0x307edbe9,
+ 0x30790b45, 0x30733a83,
+ 0x306d69a4, 0x306798a7, 0x3061c78b, 0x305bf652, 0x305624fb, 0x30505387,
+ 0x304a81f4, 0x3044b044,
+ 0x303ede76, 0x30390c8a, 0x30333a80, 0x302d6859, 0x30279614, 0x3021c3b1,
+ 0x301bf131, 0x30161e93,
+ 0x30104bd7, 0x300a78fe, 0x3004a607, 0x2ffed2f2, 0x2ff8ffc0, 0x2ff32c70,
+ 0x2fed5902, 0x2fe78577,
+ 0x2fe1b1cf, 0x2fdbde09, 0x2fd60a25, 0x2fd03624, 0x2fca6206, 0x2fc48dc9,
+ 0x2fbeb970, 0x2fb8e4f9,
+ 0x2fb31064, 0x2fad3bb3, 0x2fa766e3, 0x2fa191f7, 0x2f9bbced, 0x2f95e7c5,
+ 0x2f901280, 0x2f8a3d1e,
+ 0x2f84679f, 0x2f7e9202, 0x2f78bc48, 0x2f72e671, 0x2f6d107c, 0x2f673a6a,
+ 0x2f61643b, 0x2f5b8def,
+ 0x2f55b785, 0x2f4fe0ff, 0x2f4a0a5b, 0x2f44339a, 0x2f3e5cbb, 0x2f3885c0,
+ 0x2f32aea8, 0x2f2cd772,
+ 0x2f27001f, 0x2f2128af, 0x2f1b5122, 0x2f157979, 0x2f0fa1b2, 0x2f09c9ce,
+ 0x2f03f1cd, 0x2efe19ae,
+ 0x2ef84173, 0x2ef2691b, 0x2eec90a7, 0x2ee6b815, 0x2ee0df66, 0x2edb069a,
+ 0x2ed52db1, 0x2ecf54ac,
+ 0x2ec97b89, 0x2ec3a24a, 0x2ebdc8ee, 0x2eb7ef75, 0x2eb215df, 0x2eac3c2d,
+ 0x2ea6625d, 0x2ea08871,
+ 0x2e9aae68, 0x2e94d443, 0x2e8efa00, 0x2e891fa1, 0x2e834525, 0x2e7d6a8d,
+ 0x2e778fd8, 0x2e71b506,
+ 0x2e6bda17, 0x2e65ff0c, 0x2e6023e5, 0x2e5a48a0, 0x2e546d3f, 0x2e4e91c2,
+ 0x2e48b628, 0x2e42da71,
+ 0x2e3cfe9e, 0x2e3722ae, 0x2e3146a2, 0x2e2b6a79, 0x2e258e34, 0x2e1fb1d3,
+ 0x2e19d554, 0x2e13f8ba,
+ 0x2e0e1c03, 0x2e083f30, 0x2e026240, 0x2dfc8534, 0x2df6a80b, 0x2df0cac6,
+ 0x2deaed65, 0x2de50fe8,
+ 0x2ddf324e, 0x2dd95498, 0x2dd376c5, 0x2dcd98d7, 0x2dc7bacc, 0x2dc1dca4,
+ 0x2dbbfe61, 0x2db62001,
+ 0x2db04186, 0x2daa62ee, 0x2da4843a, 0x2d9ea569, 0x2d98c67d, 0x2d92e774,
+ 0x2d8d084f, 0x2d87290f,
+ 0x2d8149b2, 0x2d7b6a39, 0x2d758aa4, 0x2d6faaf3, 0x2d69cb26, 0x2d63eb3d,
+ 0x2d5e0b38, 0x2d582b17,
+ 0x2d524ada, 0x2d4c6a81, 0x2d468a0c, 0x2d40a97b, 0x2d3ac8ce, 0x2d34e805,
+ 0x2d2f0721, 0x2d292620,
+ 0x2d234504, 0x2d1d63cc, 0x2d178278, 0x2d11a108, 0x2d0bbf7d, 0x2d05ddd5,
+ 0x2cfffc12, 0x2cfa1a33,
+ 0x2cf43839, 0x2cee5622, 0x2ce873f0, 0x2ce291a2, 0x2cdcaf39, 0x2cd6ccb4,
+ 0x2cd0ea13, 0x2ccb0756,
+ 0x2cc5247e, 0x2cbf418b, 0x2cb95e7b, 0x2cb37b51, 0x2cad980a, 0x2ca7b4a8,
+ 0x2ca1d12a, 0x2c9bed91,
+ 0x2c9609dd, 0x2c90260d, 0x2c8a4221, 0x2c845e1a, 0x2c7e79f7, 0x2c7895b9,
+ 0x2c72b160, 0x2c6ccceb,
+ 0x2c66e85b, 0x2c6103af, 0x2c5b1ee8, 0x2c553a06, 0x2c4f5508, 0x2c496fef,
+ 0x2c438abb, 0x2c3da56b,
+ 0x2c37c000, 0x2c31da7a, 0x2c2bf4d8, 0x2c260f1c, 0x2c202944, 0x2c1a4351,
+ 0x2c145d42, 0x2c0e7719,
+ 0x2c0890d4, 0x2c02aa74, 0x2bfcc3f9, 0x2bf6dd63, 0x2bf0f6b1, 0x2beb0fe5,
+ 0x2be528fd, 0x2bdf41fb,
+ 0x2bd95add, 0x2bd373a4, 0x2bcd8c51, 0x2bc7a4e2, 0x2bc1bd58, 0x2bbbd5b3,
+ 0x2bb5edf4, 0x2bb00619,
+ 0x2baa1e23, 0x2ba43613, 0x2b9e4de7, 0x2b9865a1, 0x2b927d3f, 0x2b8c94c3,
+ 0x2b86ac2c, 0x2b80c37a,
+ 0x2b7adaae, 0x2b74f1c6, 0x2b6f08c4, 0x2b691fa6, 0x2b63366f, 0x2b5d4d1c,
+ 0x2b5763ae, 0x2b517a26,
+ 0x2b4b9083, 0x2b45a6c6, 0x2b3fbced, 0x2b39d2fa, 0x2b33e8ed, 0x2b2dfec5,
+ 0x2b281482, 0x2b222a24,
+ 0x2b1c3fac, 0x2b165519, 0x2b106a6c, 0x2b0a7fa4, 0x2b0494c2, 0x2afea9c5,
+ 0x2af8bead, 0x2af2d37b,
+ 0x2aece82f, 0x2ae6fcc8, 0x2ae11146, 0x2adb25aa, 0x2ad539f4, 0x2acf4e23,
+ 0x2ac96238, 0x2ac37633,
+ 0x2abd8a13, 0x2ab79dd8, 0x2ab1b184, 0x2aabc515, 0x2aa5d88b, 0x2a9febe8,
+ 0x2a99ff2a, 0x2a941252,
+ 0x2a8e255f, 0x2a883853, 0x2a824b2c, 0x2a7c5deb, 0x2a76708f, 0x2a70831a,
+ 0x2a6a958a, 0x2a64a7e0,
+ 0x2a5eba1c, 0x2a58cc3e, 0x2a52de46, 0x2a4cf033, 0x2a470207, 0x2a4113c0,
+ 0x2a3b2560, 0x2a3536e5,
+ 0x2a2f4850, 0x2a2959a1, 0x2a236ad9, 0x2a1d7bf6, 0x2a178cf9, 0x2a119de2,
+ 0x2a0baeb2, 0x2a05bf67,
+ 0x29ffd003, 0x29f9e084, 0x29f3f0ec, 0x29ee013a, 0x29e8116e, 0x29e22188,
+ 0x29dc3188, 0x29d6416f,
+ 0x29d0513b, 0x29ca60ee, 0x29c47087, 0x29be8007, 0x29b88f6c, 0x29b29eb8,
+ 0x29acadea, 0x29a6bd02,
+ 0x29a0cc01, 0x299adae6, 0x2994e9b1, 0x298ef863, 0x298906fb, 0x2983157a,
+ 0x297d23df, 0x2977322a,
+ 0x2971405b, 0x296b4e74, 0x29655c72, 0x295f6a57, 0x29597823, 0x295385d5,
+ 0x294d936d, 0x2947a0ec,
+ 0x2941ae52, 0x293bbb9e, 0x2935c8d1, 0x292fd5ea, 0x2929e2ea, 0x2923efd0,
+ 0x291dfc9d, 0x29180951,
+ 0x291215eb, 0x290c226c, 0x29062ed4, 0x29003b23, 0x28fa4758, 0x28f45374,
+ 0x28ee5f76, 0x28e86b5f,
+ 0x28e27730, 0x28dc82e6, 0x28d68e84, 0x28d09a09, 0x28caa574, 0x28c4b0c6,
+ 0x28bebbff, 0x28b8c71f,
+ 0x28b2d226, 0x28acdd13, 0x28a6e7e8, 0x28a0f2a3, 0x289afd46, 0x289507cf,
+ 0x288f123f, 0x28891c97,
+ 0x288326d5, 0x287d30fa, 0x28773b07, 0x287144fa, 0x286b4ed5, 0x28655896,
+ 0x285f623f, 0x28596bce,
+ 0x28537545, 0x284d7ea3, 0x284787e8, 0x28419114, 0x283b9a28, 0x2835a322,
+ 0x282fac04, 0x2829b4cd,
+ 0x2823bd7d, 0x281dc615, 0x2817ce93, 0x2811d6f9, 0x280bdf46, 0x2805e77b,
+ 0x27ffef97, 0x27f9f79a,
+ 0x27f3ff85, 0x27ee0756, 0x27e80f10, 0x27e216b0, 0x27dc1e38, 0x27d625a8,
+ 0x27d02cff, 0x27ca343d,
+ 0x27c43b63, 0x27be4270, 0x27b84965, 0x27b25041, 0x27ac5705, 0x27a65db0,
+ 0x27a06443, 0x279a6abd,
+ 0x2794711f, 0x278e7768, 0x27887d99, 0x278283b2, 0x277c89b3, 0x27768f9b,
+ 0x2770956a, 0x276a9b21,
+ 0x2764a0c0, 0x275ea647, 0x2758abb6, 0x2752b10c, 0x274cb64a, 0x2746bb6f,
+ 0x2740c07d, 0x273ac572,
+ 0x2734ca4f, 0x272ecf14, 0x2728d3c0, 0x2722d855, 0x271cdcd1, 0x2716e136,
+ 0x2710e582, 0x270ae9b6,
+ 0x2704edd2, 0x26fef1d5, 0x26f8f5c1, 0x26f2f995, 0x26ecfd51, 0x26e700f5,
+ 0x26e10480, 0x26db07f4,
+ 0x26d50b50, 0x26cf0e94, 0x26c911c0, 0x26c314d4, 0x26bd17d0, 0x26b71ab4,
+ 0x26b11d80, 0x26ab2034,
+ 0x26a522d1, 0x269f2556, 0x269927c3, 0x26932a18, 0x268d2c55, 0x26872e7b,
+ 0x26813088, 0x267b327e,
+ 0x2675345d, 0x266f3623, 0x266937d2, 0x26633969, 0x265d3ae9, 0x26573c50,
+ 0x26513da1, 0x264b3ed9,
+ 0x26453ffa, 0x263f4103, 0x263941f5, 0x263342cf, 0x262d4392, 0x2627443d,
+ 0x262144d0, 0x261b454c,
+ 0x261545b0, 0x260f45fd, 0x26094633, 0x26034651, 0x25fd4657, 0x25f74646,
+ 0x25f1461e, 0x25eb45de,
+ 0x25e54587, 0x25df4519, 0x25d94493, 0x25d343f6, 0x25cd4341, 0x25c74276,
+ 0x25c14192, 0x25bb4098,
+ 0x25b53f86, 0x25af3e5d, 0x25a93d1d, 0x25a33bc6, 0x259d3a57, 0x259738d1,
+ 0x25913734, 0x258b3580,
+ 0x258533b5, 0x257f31d2, 0x25792fd8, 0x25732dc8, 0x256d2ba0, 0x25672961,
+ 0x2561270b, 0x255b249e,
+ 0x2555221a, 0x254f1f7e, 0x25491ccc, 0x25431a03, 0x253d1723, 0x2537142c,
+ 0x2531111e, 0x252b0df9,
+ 0x25250abd, 0x251f076a, 0x25190400, 0x25130080, 0x250cfce8, 0x2506f93a,
+ 0x2500f574, 0x24faf198,
+ 0x24f4eda6, 0x24eee99c, 0x24e8e57c, 0x24e2e144, 0x24dcdcf6, 0x24d6d892,
+ 0x24d0d416, 0x24cacf84,
+ 0x24c4cadb, 0x24bec61c, 0x24b8c146, 0x24b2bc59, 0x24acb756, 0x24a6b23b,
+ 0x24a0ad0b, 0x249aa7c4,
+ 0x2494a266, 0x248e9cf1, 0x24889766, 0x248291c5, 0x247c8c0d, 0x2476863e,
+ 0x24708059, 0x246a7a5e,
+ 0x2464744c, 0x245e6e23, 0x245867e4, 0x2452618f, 0x244c5b24, 0x244654a1,
+ 0x24404e09, 0x243a475a,
+ 0x24344095, 0x242e39ba, 0x242832c8, 0x24222bc0, 0x241c24a1, 0x24161d6d,
+ 0x24101622, 0x240a0ec1,
+ 0x24040749, 0x23fdffbc, 0x23f7f818, 0x23f1f05e, 0x23ebe88e, 0x23e5e0a7,
+ 0x23dfd8ab, 0x23d9d098,
+ 0x23d3c86f, 0x23cdc031, 0x23c7b7dc, 0x23c1af71, 0x23bba6f0, 0x23b59e59,
+ 0x23af95ac, 0x23a98ce8,
+ 0x23a3840f, 0x239d7b20, 0x2397721b, 0x23916900, 0x238b5fcf, 0x23855688,
+ 0x237f4d2b, 0x237943b9,
+ 0x23733a30, 0x236d3092, 0x236726dd, 0x23611d13, 0x235b1333, 0x2355093e,
+ 0x234eff32, 0x2348f511,
+ 0x2342eada, 0x233ce08d, 0x2336d62a, 0x2330cbb2, 0x232ac124, 0x2324b680,
+ 0x231eabc7, 0x2318a0f8,
+ 0x23129613, 0x230c8b19, 0x23068009, 0x230074e3, 0x22fa69a8, 0x22f45e57,
+ 0x22ee52f1, 0x22e84775,
+ 0x22e23be4, 0x22dc303d, 0x22d62480, 0x22d018ae, 0x22ca0cc7, 0x22c400ca,
+ 0x22bdf4b8, 0x22b7e890,
+ 0x22b1dc53, 0x22abd001, 0x22a5c399, 0x229fb71b, 0x2299aa89, 0x22939de1,
+ 0x228d9123, 0x22878451,
+ 0x22817769, 0x227b6a6c, 0x22755d59, 0x226f5032, 0x226942f5, 0x226335a2,
+ 0x225d283b, 0x22571abe,
+ 0x22510d2d, 0x224aff86, 0x2244f1c9, 0x223ee3f8, 0x2238d612, 0x2232c816,
+ 0x222cba06, 0x2226abe0,
+ 0x22209da5, 0x221a8f56, 0x221480f1, 0x220e7277, 0x220863e8, 0x22025544,
+ 0x21fc468b, 0x21f637be,
+ 0x21f028db, 0x21ea19e3, 0x21e40ad7, 0x21ddfbb5, 0x21d7ec7f, 0x21d1dd34,
+ 0x21cbcdd3, 0x21c5be5e,
+ 0x21bfaed5, 0x21b99f36, 0x21b38f83, 0x21ad7fba, 0x21a76fdd, 0x21a15fec,
+ 0x219b4fe5, 0x21953fca,
+ 0x218f2f9a, 0x21891f55, 0x21830efc, 0x217cfe8e, 0x2176ee0b, 0x2170dd74,
+ 0x216accc8, 0x2164bc08,
+ 0x215eab33, 0x21589a49, 0x2152894b, 0x214c7838, 0x21466710, 0x214055d4,
+ 0x213a4484, 0x2134331f,
+ 0x212e21a6, 0x21281018, 0x2121fe76, 0x211becbf, 0x2115daf4, 0x210fc914,
+ 0x2109b720, 0x2103a518,
+ 0x20fd92fb, 0x20f780ca, 0x20f16e84, 0x20eb5c2b, 0x20e549bd, 0x20df373a,
+ 0x20d924a4, 0x20d311f9,
+ 0x20ccff3a, 0x20c6ec66, 0x20c0d97f, 0x20bac683, 0x20b4b373, 0x20aea04f,
+ 0x20a88d17, 0x20a279ca,
+ 0x209c666a, 0x209652f5, 0x20903f6c, 0x208a2bcf, 0x2084181e, 0x207e0459,
+ 0x2077f080, 0x2071dc93,
+ 0x206bc892, 0x2065b47d, 0x205fa054, 0x20598c17, 0x205377c6, 0x204d6361,
+ 0x20474ee8, 0x20413a5b,
+ 0x203b25bb, 0x20351106, 0x202efc3e, 0x2028e761, 0x2022d271, 0x201cbd6d,
+ 0x2016a856, 0x2010932a,
+ 0x200a7deb, 0x20046898, 0x1ffe5331, 0x1ff83db6, 0x1ff22828, 0x1fec1286,
+ 0x1fe5fcd0, 0x1fdfe707,
+ 0x1fd9d12a, 0x1fd3bb39, 0x1fcda535, 0x1fc78f1d, 0x1fc178f1, 0x1fbb62b2,
+ 0x1fb54c60, 0x1faf35f9,
+ 0x1fa91f80, 0x1fa308f2, 0x1f9cf252, 0x1f96db9d, 0x1f90c4d5, 0x1f8aadfa,
+ 0x1f84970b, 0x1f7e8009,
+ 0x1f7868f4, 0x1f7251ca, 0x1f6c3a8e, 0x1f66233e, 0x1f600bdb, 0x1f59f465,
+ 0x1f53dcdb, 0x1f4dc53d,
+ 0x1f47ad8d, 0x1f4195c9, 0x1f3b7df2, 0x1f356608, 0x1f2f4e0a, 0x1f2935f9,
+ 0x1f231dd5, 0x1f1d059e,
+ 0x1f16ed54, 0x1f10d4f6, 0x1f0abc85, 0x1f04a401, 0x1efe8b6a, 0x1ef872c0,
+ 0x1ef25a03, 0x1eec4132,
+ 0x1ee6284f, 0x1ee00f58, 0x1ed9f64f, 0x1ed3dd32, 0x1ecdc402, 0x1ec7aac0,
+ 0x1ec1916a, 0x1ebb7802,
+ 0x1eb55e86, 0x1eaf44f8, 0x1ea92b56, 0x1ea311a2, 0x1e9cf7db, 0x1e96de01,
+ 0x1e90c414, 0x1e8aaa14,
+ 0x1e849001, 0x1e7e75dc, 0x1e785ba3, 0x1e724158, 0x1e6c26fa, 0x1e660c8a,
+ 0x1e5ff206, 0x1e59d770,
+ 0x1e53bcc7, 0x1e4da20c, 0x1e47873d, 0x1e416c5d, 0x1e3b5169, 0x1e353663,
+ 0x1e2f1b4a, 0x1e29001e,
+ 0x1e22e4e0, 0x1e1cc990, 0x1e16ae2c, 0x1e1092b6, 0x1e0a772e, 0x1e045b93,
+ 0x1dfe3fe6, 0x1df82426,
+ 0x1df20853, 0x1debec6f, 0x1de5d077, 0x1ddfb46e, 0x1dd99851, 0x1dd37c23,
+ 0x1dcd5fe2, 0x1dc7438e,
+ 0x1dc12729, 0x1dbb0ab0, 0x1db4ee26, 0x1daed189, 0x1da8b4da, 0x1da29819,
+ 0x1d9c7b45, 0x1d965e5f,
+ 0x1d904167, 0x1d8a245c, 0x1d840740, 0x1d7dea11, 0x1d77ccd0, 0x1d71af7d,
+ 0x1d6b9217, 0x1d6574a0,
+ 0x1d5f5716, 0x1d59397a, 0x1d531bcc, 0x1d4cfe0d, 0x1d46e03a, 0x1d40c256,
+ 0x1d3aa460, 0x1d348658,
+ 0x1d2e683e, 0x1d284a12, 0x1d222bd3, 0x1d1c0d83, 0x1d15ef21, 0x1d0fd0ad,
+ 0x1d09b227, 0x1d03938f,
+ 0x1cfd74e5, 0x1cf7562a, 0x1cf1375c, 0x1ceb187d, 0x1ce4f98c, 0x1cdeda89,
+ 0x1cd8bb74, 0x1cd29c4d,
+ 0x1ccc7d15, 0x1cc65dca, 0x1cc03e6e, 0x1cba1f01, 0x1cb3ff81, 0x1caddff0,
+ 0x1ca7c04d, 0x1ca1a099,
+ 0x1c9b80d3, 0x1c9560fb, 0x1c8f4112, 0x1c892117, 0x1c83010a, 0x1c7ce0ec,
+ 0x1c76c0bc, 0x1c70a07b,
+ 0x1c6a8028, 0x1c645fc3, 0x1c5e3f4d, 0x1c581ec6, 0x1c51fe2d, 0x1c4bdd83,
+ 0x1c45bcc7, 0x1c3f9bf9,
+ 0x1c397b1b, 0x1c335a2b, 0x1c2d3929, 0x1c271816, 0x1c20f6f2, 0x1c1ad5bc,
+ 0x1c14b475, 0x1c0e931d,
+ 0x1c0871b4, 0x1c025039, 0x1bfc2ead, 0x1bf60d0f, 0x1befeb60, 0x1be9c9a1,
+ 0x1be3a7cf, 0x1bdd85ed,
+ 0x1bd763fa, 0x1bd141f5, 0x1bcb1fdf, 0x1bc4fdb8, 0x1bbedb80, 0x1bb8b937,
+ 0x1bb296dc, 0x1bac7471,
+ 0x1ba651f5, 0x1ba02f67, 0x1b9a0cc8, 0x1b93ea19, 0x1b8dc758, 0x1b87a487,
+ 0x1b8181a4, 0x1b7b5eb0,
+ 0x1b753bac, 0x1b6f1897, 0x1b68f570, 0x1b62d239, 0x1b5caef1, 0x1b568b98,
+ 0x1b50682e, 0x1b4a44b3,
+ 0x1b442127, 0x1b3dfd8b, 0x1b37d9de, 0x1b31b620, 0x1b2b9251, 0x1b256e71,
+ 0x1b1f4a81, 0x1b192680,
+ 0x1b13026e, 0x1b0cde4c, 0x1b06ba19, 0x1b0095d5, 0x1afa7180, 0x1af44d1b,
+ 0x1aee28a6, 0x1ae8041f,
+ 0x1ae1df88, 0x1adbbae1, 0x1ad59629, 0x1acf7160, 0x1ac94c87, 0x1ac3279d,
+ 0x1abd02a3, 0x1ab6dd98,
+ 0x1ab0b87d, 0x1aaa9352, 0x1aa46e16, 0x1a9e48c9, 0x1a98236c, 0x1a91fdff,
+ 0x1a8bd881, 0x1a85b2f3,
+ 0x1a7f8d54, 0x1a7967a6, 0x1a7341e6, 0x1a6d1c17, 0x1a66f637, 0x1a60d047,
+ 0x1a5aaa47, 0x1a548436,
+ 0x1a4e5e15, 0x1a4837e4, 0x1a4211a3, 0x1a3beb52, 0x1a35c4f0, 0x1a2f9e7e,
+ 0x1a2977fc, 0x1a23516a,
+ 0x1a1d2ac8, 0x1a170416, 0x1a10dd53, 0x1a0ab681, 0x1a048f9e, 0x19fe68ac,
+ 0x19f841a9, 0x19f21a96,
+ 0x19ebf374, 0x19e5cc41, 0x19dfa4fe, 0x19d97dac, 0x19d35649, 0x19cd2ed7,
+ 0x19c70754, 0x19c0dfc2,
+ 0x19bab820, 0x19b4906e, 0x19ae68ac, 0x19a840da, 0x19a218f9, 0x199bf107,
+ 0x1995c906, 0x198fa0f5,
+ 0x198978d4, 0x198350a4, 0x197d2864, 0x19770014, 0x1970d7b4, 0x196aaf45,
+ 0x196486c6, 0x195e5e37,
+ 0x19583599, 0x19520ceb, 0x194be42d, 0x1945bb60, 0x193f9283, 0x19396997,
+ 0x1933409b, 0x192d178f,
+ 0x1926ee74, 0x1920c54a, 0x191a9c10, 0x191472c6, 0x190e496d, 0x19082005,
+ 0x1901f68d, 0x18fbcd06,
+ 0x18f5a36f, 0x18ef79c9, 0x18e95014, 0x18e3264f, 0x18dcfc7b, 0x18d6d297,
+ 0x18d0a8a4, 0x18ca7ea2,
+ 0x18c45491, 0x18be2a70, 0x18b80040, 0x18b1d601, 0x18ababb2, 0x18a58154,
+ 0x189f56e8, 0x18992c6b,
+ 0x189301e0, 0x188cd746, 0x1886ac9c, 0x188081e4, 0x187a571c, 0x18742c45,
+ 0x186e015f, 0x1867d66a,
+ 0x1861ab66, 0x185b8053, 0x18555530, 0x184f29ff, 0x1848febf, 0x1842d370,
+ 0x183ca812, 0x18367ca5,
+ 0x18305129, 0x182a259e, 0x1823fa04, 0x181dce5b, 0x1817a2a4, 0x181176dd,
+ 0x180b4b08, 0x18051f24,
+ 0x17fef331, 0x17f8c72f, 0x17f29b1e, 0x17ec6eff, 0x17e642d1, 0x17e01694,
+ 0x17d9ea49, 0x17d3bdee,
+ 0x17cd9186, 0x17c7650e, 0x17c13888, 0x17bb0bf3, 0x17b4df4f, 0x17aeb29d,
+ 0x17a885dc, 0x17a2590d,
+ 0x179c2c2f, 0x1795ff42, 0x178fd247, 0x1789a53d, 0x17837825, 0x177d4afe,
+ 0x17771dc9, 0x1770f086,
+ 0x176ac333, 0x176495d3, 0x175e6864, 0x17583ae7, 0x17520d5b, 0x174bdfc1,
+ 0x1745b218, 0x173f8461,
+ 0x1739569c, 0x173328c8, 0x172cfae6, 0x1726ccf6, 0x17209ef8, 0x171a70eb,
+ 0x171442d0, 0x170e14a7,
+ 0x1707e670, 0x1701b82a, 0x16fb89d6, 0x16f55b74, 0x16ef2d04, 0x16e8fe86,
+ 0x16e2cff9, 0x16dca15f,
+ 0x16d672b6, 0x16d043ff, 0x16ca153a, 0x16c3e667, 0x16bdb787, 0x16b78898,
+ 0x16b1599b, 0x16ab2a90,
+ 0x16a4fb77, 0x169ecc50, 0x16989d1b, 0x16926dd8, 0x168c3e87, 0x16860f29,
+ 0x167fdfbc, 0x1679b042,
+ 0x167380ba, 0x166d5123, 0x1667217f, 0x1660f1ce, 0x165ac20e, 0x16549241,
+ 0x164e6266, 0x1648327d,
+ 0x16420286, 0x163bd282, 0x1635a270, 0x162f7250, 0x16294222, 0x162311e7,
+ 0x161ce19e, 0x1616b148,
+ 0x161080e4, 0x160a5072, 0x16041ff3, 0x15fdef66, 0x15f7becc, 0x15f18e24,
+ 0x15eb5d6e, 0x15e52cab,
+ 0x15defbdb, 0x15d8cafd, 0x15d29a11, 0x15cc6918, 0x15c63812, 0x15c006fe,
+ 0x15b9d5dd, 0x15b3a4ae,
+ 0x15ad7372, 0x15a74228, 0x15a110d2, 0x159adf6e, 0x1594adfc, 0x158e7c7d,
+ 0x15884af1, 0x15821958,
+ 0x157be7b1, 0x1575b5fe, 0x156f843c, 0x1569526e, 0x15632093, 0x155ceeaa,
+ 0x1556bcb4, 0x15508ab1,
+ 0x154a58a1, 0x15442683, 0x153df459, 0x1537c221, 0x15318fdd, 0x152b5d8b,
+ 0x15252b2c, 0x151ef8c0,
+ 0x1518c648, 0x151293c2, 0x150c612f, 0x15062e8f, 0x14fffbe2, 0x14f9c928,
+ 0x14f39662, 0x14ed638e,
+ 0x14e730ae, 0x14e0fdc0, 0x14dacac6, 0x14d497bf, 0x14ce64ab, 0x14c8318a,
+ 0x14c1fe5c, 0x14bbcb22,
+ 0x14b597da, 0x14af6486, 0x14a93125, 0x14a2fdb8, 0x149cca3e, 0x149696b7,
+ 0x14906323, 0x148a2f82,
+ 0x1483fbd5, 0x147dc81c, 0x14779455, 0x14716082, 0x146b2ca3, 0x1464f8b7,
+ 0x145ec4be, 0x145890b9,
+ 0x14525ca7, 0x144c2888, 0x1445f45d, 0x143fc026, 0x14398be2, 0x14335792,
+ 0x142d2335, 0x1426eecb,
+ 0x1420ba56, 0x141a85d3, 0x14145145, 0x140e1caa, 0x1407e803, 0x1401b34f,
+ 0x13fb7e8f, 0x13f549c3,
+ 0x13ef14ea, 0x13e8e005, 0x13e2ab14, 0x13dc7616, 0x13d6410d, 0x13d00bf7,
+ 0x13c9d6d4, 0x13c3a1a6,
+ 0x13bd6c6b, 0x13b73725, 0x13b101d2, 0x13aacc73, 0x13a49707, 0x139e6190,
+ 0x13982c0d, 0x1391f67d,
+ 0x138bc0e1, 0x13858b3a, 0x137f5586, 0x13791fc6, 0x1372e9fb, 0x136cb423,
+ 0x13667e3f, 0x13604850,
+ 0x135a1254, 0x1353dc4c, 0x134da639, 0x1347701a, 0x134139ee, 0x133b03b7,
+ 0x1334cd74, 0x132e9725,
+ 0x132860ca, 0x13222a64, 0x131bf3f2, 0x1315bd73, 0x130f86ea, 0x13095054,
+ 0x130319b3, 0x12fce305,
+ 0x12f6ac4d, 0x12f07588, 0x12ea3eb8, 0x12e407dc, 0x12ddd0f4, 0x12d79a01,
+ 0x12d16303, 0x12cb2bf8,
+ 0x12c4f4e2, 0x12bebdc1, 0x12b88693, 0x12b24f5b, 0x12ac1817, 0x12a5e0c7,
+ 0x129fa96c, 0x12997205,
+ 0x12933a93, 0x128d0315, 0x1286cb8c, 0x128093f7, 0x127a5c57, 0x127424ac,
+ 0x126decf5, 0x1267b533,
+ 0x12617d66, 0x125b458d, 0x12550da9, 0x124ed5ba, 0x12489dbf, 0x124265b9,
+ 0x123c2da8, 0x1235f58b,
+ 0x122fbd63, 0x12298530, 0x12234cf2, 0x121d14a9, 0x1216dc54, 0x1210a3f5,
+ 0x120a6b8a, 0x12043314,
+ 0x11fdfa93, 0x11f7c207, 0x11f18970, 0x11eb50cd, 0x11e51820, 0x11dedf68,
+ 0x11d8a6a4, 0x11d26dd6,
+ 0x11cc34fc, 0x11c5fc18, 0x11bfc329, 0x11b98a2e, 0x11b35129, 0x11ad1819,
+ 0x11a6defe, 0x11a0a5d8,
+ 0x119a6ca7, 0x1194336b, 0x118dfa25, 0x1187c0d3, 0x11818777, 0x117b4e10,
+ 0x1175149e, 0x116edb22,
+ 0x1168a19b, 0x11626809, 0x115c2e6c, 0x1155f4c4, 0x114fbb12, 0x11498156,
+ 0x1143478e, 0x113d0dbc,
+ 0x1136d3df, 0x113099f8, 0x112a6006, 0x11242609, 0x111dec02, 0x1117b1f0,
+ 0x111177d4, 0x110b3dad,
+ 0x1105037c, 0x10fec940, 0x10f88efa, 0x10f254a9, 0x10ec1a4e, 0x10e5dfe8,
+ 0x10dfa578, 0x10d96afe,
+ 0x10d33079, 0x10ccf5ea, 0x10c6bb50, 0x10c080ac, 0x10ba45fe, 0x10b40b45,
+ 0x10add082, 0x10a795b5,
+ 0x10a15ade, 0x109b1ffc, 0x1094e510, 0x108eaa1a, 0x10886f19, 0x1082340f,
+ 0x107bf8fa, 0x1075bddb,
+ 0x106f82b2, 0x1069477f, 0x10630c41, 0x105cd0fa, 0x105695a8, 0x10505a4d,
+ 0x104a1ee7, 0x1043e377,
+ 0x103da7fd, 0x10376c79, 0x103130ec, 0x102af554, 0x1024b9b2, 0x101e7e06,
+ 0x10184251, 0x10120691,
+ 0x100bcac7, 0x10058ef4, 0xfff5317, 0xff91730, 0xff2db3e, 0xfec9f44,
+ 0xfe6633f, 0xfe02730,
+ 0xfd9eb18, 0xfd3aef6, 0xfcd72ca, 0xfc73695, 0xfc0fa55, 0xfbabe0c, 0xfb481ba,
+ 0xfae455d,
+ 0xfa808f7, 0xfa1cc87, 0xf9b900e, 0xf95538b, 0xf8f16fe, 0xf88da68, 0xf829dc8,
+ 0xf7c611f,
+ 0xf76246c, 0xf6fe7af, 0xf69aae9, 0xf636e1a, 0xf5d3141, 0xf56f45e, 0xf50b773,
+ 0xf4a7a7d,
+ 0xf443d7e, 0xf3e0076, 0xf37c365, 0xf318649, 0xf2b4925, 0xf250bf7, 0xf1ecec0,
+ 0xf189180,
+ 0xf125436, 0xf0c16e3, 0xf05d987, 0xeff9c21, 0xef95eb2, 0xef3213a, 0xeece3b9,
+ 0xee6a62f,
+ 0xee0689b, 0xeda2afe, 0xed3ed58, 0xecdafa9, 0xec771f1, 0xec1342f, 0xebaf665,
+ 0xeb4b891,
+ 0xeae7ab4, 0xea83ccf, 0xea1fee0, 0xe9bc0e8, 0xe9582e7, 0xe8f44dd, 0xe8906cb,
+ 0xe82c8af,
+ 0xe7c8a8a, 0xe764c5c, 0xe700e26, 0xe69cfe6, 0xe63919e, 0xe5d534d, 0xe5714f3,
+ 0xe50d690,
+ 0xe4a9824, 0xe4459af, 0xe3e1b32, 0xe37dcac, 0xe319e1d, 0xe2b5f85, 0xe2520e5,
+ 0xe1ee23c,
+ 0xe18a38a, 0xe1264cf, 0xe0c260c, 0xe05e740, 0xdffa86b, 0xdf9698e, 0xdf32aa8,
+ 0xdecebba,
+ 0xde6acc3, 0xde06dc3, 0xdda2ebb, 0xdd3efab, 0xdcdb091, 0xdc77170, 0xdc13245,
+ 0xdbaf313,
+ 0xdb4b3d7, 0xdae7494, 0xda83548, 0xda1f5f3, 0xd9bb696, 0xd957731, 0xd8f37c3,
+ 0xd88f84d,
+ 0xd82b8cf, 0xd7c7948, 0xd7639b9, 0xd6ffa22, 0xd69ba82, 0xd637ada, 0xd5d3b2a,
+ 0xd56fb71,
+ 0xd50bbb1, 0xd4a7be8, 0xd443c17, 0xd3dfc3e, 0xd37bc5c, 0xd317c73, 0xd2b3c81,
+ 0xd24fc87,
+ 0xd1ebc85, 0xd187c7b, 0xd123c69, 0xd0bfc4f, 0xd05bc2d, 0xcff7c02, 0xcf93bd0,
+ 0xcf2fb96,
+ 0xcecbb53, 0xce67b09, 0xce03ab7, 0xcd9fa5d, 0xcd3b9fb, 0xccd7991, 0xcc7391f,
+ 0xcc0f8a5,
+ 0xcbab824, 0xcb4779a, 0xcae3709, 0xca7f670, 0xca1b5cf, 0xc9b7526, 0xc953475,
+ 0xc8ef3bd,
+ 0xc88b2fd, 0xc827235, 0xc7c3166, 0xc75f08f, 0xc6fafb0, 0xc696ec9, 0xc632ddb,
+ 0xc5cece5,
+ 0xc56abe8, 0xc506ae3, 0xc4a29d6, 0xc43e8c2, 0xc3da7a6, 0xc376683, 0xc312558,
+ 0xc2ae425,
+ 0xc24a2eb, 0xc1e61aa, 0xc182061, 0xc11df11, 0xc0b9db9, 0xc055c5a, 0xbff1af3,
+ 0xbf8d985,
+ 0xbf29810, 0xbec5693, 0xbe6150f, 0xbdfd383, 0xbd991f0, 0xbd35056, 0xbcd0eb5,
+ 0xbc6cd0c,
+ 0xbc08b5c, 0xbba49a5, 0xbb407e7, 0xbadc621, 0xba78454, 0xba14280, 0xb9b00a5,
+ 0xb94bec2,
+ 0xb8e7cd9, 0xb883ae8, 0xb81f8f0, 0xb7bb6f2, 0xb7574ec, 0xb6f32df, 0xb68f0cb,
+ 0xb62aeaf,
+ 0xb5c6c8d, 0xb562a64, 0xb4fe834, 0xb49a5fd, 0xb4363bf, 0xb3d217a, 0xb36df2e,
+ 0xb309cdb,
+ 0xb2a5a81, 0xb241820, 0xb1dd5b9, 0xb17934b, 0xb1150d5, 0xb0b0e59, 0xb04cbd6,
+ 0xafe894d,
+ 0xaf846bc, 0xaf20425, 0xaebc187, 0xae57ee2, 0xadf3c37, 0xad8f985, 0xad2b6cc,
+ 0xacc740c,
+ 0xac63146, 0xabfee79, 0xab9aba6, 0xab368cc, 0xaad25eb, 0xaa6e304, 0xaa0a016,
+ 0xa9a5d22,
+ 0xa941a27, 0xa8dd725, 0xa87941d, 0xa81510f, 0xa7b0dfa, 0xa74cadf, 0xa6e87bd,
+ 0xa684495,
+ 0xa620166, 0xa5bbe31, 0xa557af5, 0xa4f37b3, 0xa48f46b, 0xa42b11d, 0xa3c6dc8,
+ 0xa362a6d,
+ 0xa2fe70b, 0xa29a3a3, 0xa236035, 0xa1d1cc1, 0xa16d946, 0xa1095c6, 0xa0a523f,
+ 0xa040eb1,
+ 0x9fdcb1e, 0x9f78784, 0x9f143e5, 0x9eb003f, 0x9e4bc93, 0x9de78e1, 0x9d83529,
+ 0x9d1f16b,
+ 0x9cbada7, 0x9c569dc, 0x9bf260c, 0x9b8e236, 0x9b29e59, 0x9ac5a77, 0x9a6168f,
+ 0x99fd2a0,
+ 0x9998eac, 0x9934ab2, 0x98d06b2, 0x986c2ac, 0x9807ea1, 0x97a3a8f, 0x973f678,
+ 0x96db25a,
+ 0x9676e37, 0x9612a0e, 0x95ae5e0, 0x954a1ab, 0x94e5d71, 0x9481931, 0x941d4eb,
+ 0x93b90a0,
+ 0x9354c4f, 0x92f07f8, 0x928c39b, 0x9227f39, 0x91c3ad2, 0x915f664, 0x90fb1f1,
+ 0x9096d79,
+ 0x90328fb, 0x8fce477, 0x8f69fee, 0x8f05b5f, 0x8ea16cb, 0x8e3d231, 0x8dd8d92,
+ 0x8d748ed,
+ 0x8d10443, 0x8cabf93, 0x8c47ade, 0x8be3624, 0x8b7f164, 0x8b1ac9f, 0x8ab67d4,
+ 0x8a52304,
+ 0x89ede2f, 0x8989955, 0x8925475, 0x88c0f90, 0x885caa5, 0x87f85b5, 0x87940c1,
+ 0x872fbc6,
+ 0x86cb6c7, 0x86671c2, 0x8602cb9, 0x859e7aa, 0x853a296, 0x84d5d7d, 0x847185e,
+ 0x840d33b,
+ 0x83a8e12, 0x83448e5, 0x82e03b2, 0x827be7a, 0x821793e, 0x81b33fc, 0x814eeb5,
+ 0x80ea969,
+ 0x8086419, 0x8021ec3, 0x7fbd968, 0x7f59409, 0x7ef4ea4, 0x7e9093b, 0x7e2c3cd,
+ 0x7dc7e5a,
+ 0x7d638e2, 0x7cff365, 0x7c9ade4, 0x7c3685d, 0x7bd22d2, 0x7b6dd42, 0x7b097ad,
+ 0x7aa5214,
+ 0x7a40c76, 0x79dc6d3, 0x797812b, 0x7913b7f, 0x78af5ce, 0x784b019, 0x77e6a5e,
+ 0x77824a0,
+ 0x771dedc, 0x76b9914, 0x7655347, 0x75f0d76, 0x758c7a1, 0x75281c6, 0x74c3be7,
+ 0x745f604,
+ 0x73fb01c, 0x7396a30, 0x733243f, 0x72cde4a, 0x7269851, 0x7205253, 0x71a0c50,
+ 0x713c64a,
+ 0x70d803f, 0x7073a2f, 0x700f41b, 0x6faae03, 0x6f467e7, 0x6ee21c6, 0x6e7dba1,
+ 0x6e19578,
+ 0x6db4f4a, 0x6d50919, 0x6cec2e3, 0x6c87ca9, 0x6c2366a, 0x6bbf028, 0x6b5a9e1,
+ 0x6af6396,
+ 0x6a91d47, 0x6a2d6f4, 0x69c909d, 0x6964a42, 0x69003e3, 0x689bd80, 0x6837718,
+ 0x67d30ad,
+ 0x676ea3d, 0x670a3ca, 0x66a5d53, 0x66416d8, 0x65dd058, 0x65789d5, 0x651434e,
+ 0x64afcc3,
+ 0x644b634, 0x63e6fa2, 0x638290b, 0x631e271, 0x62b9bd3, 0x6255531, 0x61f0e8b,
+ 0x618c7e1,
+ 0x6128134, 0x60c3a83, 0x605f3ce, 0x5ffad15, 0x5f96659, 0x5f31f99, 0x5ecd8d6,
+ 0x5e6920e,
+ 0x5e04b43, 0x5da0475, 0x5d3bda3, 0x5cd76cd, 0x5c72ff4, 0x5c0e917, 0x5baa237,
+ 0x5b45b53,
+ 0x5ae146b, 0x5a7cd80, 0x5a18692, 0x59b3fa0, 0x594f8aa, 0x58eb1b2, 0x5886ab5,
+ 0x58223b6,
+ 0x57bdcb3, 0x57595ac, 0x56f4ea2, 0x5690795, 0x562c085, 0x55c7971, 0x556325a,
+ 0x54feb3f,
+ 0x549a422, 0x5435d01, 0x53d15dd, 0x536ceb5, 0x530878a, 0x52a405d, 0x523f92c,
+ 0x51db1f7,
+ 0x5176ac0, 0x5112385, 0x50adc48, 0x5049507, 0x4fe4dc3, 0x4f8067c, 0x4f1bf32,
+ 0x4eb77e5,
+ 0x4e53095, 0x4dee942, 0x4d8a1ec, 0x4d25a93, 0x4cc1337, 0x4c5cbd8, 0x4bf8476,
+ 0x4b93d11,
+ 0x4b2f5a9, 0x4acae3e, 0x4a666d1, 0x4a01f60, 0x499d7ed, 0x4939077, 0x48d48fe,
+ 0x4870182,
+ 0x480ba04, 0x47a7282, 0x4742afe, 0x46de377, 0x4679bee, 0x4615461, 0x45b0cd2,
+ 0x454c541,
+ 0x44e7dac, 0x4483615, 0x441ee7c, 0x43ba6df, 0x4355f40, 0x42f179f, 0x428cffb,
+ 0x4228854,
+ 0x41c40ab, 0x415f8ff, 0x40fb151, 0x40969a0, 0x40321ed, 0x3fcda37, 0x3f6927f,
+ 0x3f04ac4,
+ 0x3ea0307, 0x3e3bb48, 0x3dd7386, 0x3d72bc2, 0x3d0e3fb, 0x3ca9c32, 0x3c45467,
+ 0x3be0c99,
+ 0x3b7c4c9, 0x3b17cf7, 0x3ab3523, 0x3a4ed4c, 0x39ea573, 0x3985d97, 0x39215ba,
+ 0x38bcdda,
+ 0x38585f8, 0x37f3e14, 0x378f62e, 0x372ae46, 0x36c665b, 0x3661e6f, 0x35fd680,
+ 0x3598e8f,
+ 0x353469c, 0x34cfea8, 0x346b6b1, 0x3406eb8, 0x33a26bd, 0x333dec0, 0x32d96c1,
+ 0x3274ec0,
+ 0x32106bd, 0x31abeb9, 0x31476b2, 0x30e2ea9, 0x307e69f, 0x3019e93, 0x2fb5684,
+ 0x2f50e74,
+ 0x2eec663, 0x2e87e4f, 0x2e2363a, 0x2dbee22, 0x2d5a609, 0x2cf5def, 0x2c915d2,
+ 0x2c2cdb4,
+ 0x2bc8594, 0x2b63d73, 0x2aff54f, 0x2a9ad2a, 0x2a36504, 0x29d1cdc, 0x296d4b2,
+ 0x2908c87,
+ 0x28a445a, 0x283fc2b, 0x27db3fb, 0x2776bc9, 0x2712396, 0x26adb62, 0x264932b,
+ 0x25e4af4,
+ 0x25802bb, 0x251ba80, 0x24b7244, 0x2452a07, 0x23ee1c8, 0x2389988, 0x2325147,
+ 0x22c0904,
+ 0x225c0bf, 0x21f787a, 0x2193033, 0x212e7eb, 0x20c9fa1, 0x2065757, 0x2000f0b,
+ 0x1f9c6be,
+ 0x1f37e6f, 0x1ed3620, 0x1e6edcf, 0x1e0a57d, 0x1da5d2a, 0x1d414d6, 0x1cdcc80,
+ 0x1c7842a,
+ 0x1c13bd2, 0x1baf37a, 0x1b4ab20, 0x1ae62c5, 0x1a81a69, 0x1a1d20c, 0x19b89ae,
+ 0x1954150,
+ 0x18ef8f0, 0x188b08f, 0x182682d, 0x17c1fcb, 0x175d767, 0x16f8f03, 0x169469d,
+ 0x162fe37,
+ 0x15cb5d0, 0x1566d68, 0x15024ff, 0x149dc96, 0x143942b, 0x13d4bc0, 0x1370354,
+ 0x130bae7,
+ 0x12a727a, 0x1242a0c, 0x11de19d, 0x117992e, 0x11150be, 0x10b084d, 0x104bfdb,
+ 0xfe7769,
+ 0xf82ef6, 0xf1e683, 0xeb9e0f, 0xe5559b, 0xdf0d26, 0xd8c4b0, 0xd27c3a,
+ 0xcc33c3,
+ 0xc5eb4c, 0xbfa2d5, 0xb95a5d, 0xb311e4, 0xacc96b, 0xa680f2, 0xa03878,
+ 0x99effe,
+ 0x93a784, 0x8d5f09, 0x87168e, 0x80ce12, 0x7a8597, 0x743d1a, 0x6df49e,
+ 0x67ac21,
+ 0x6163a5, 0x5b1b27, 0x54d2aa, 0x4e8a2c, 0x4841af, 0x41f931, 0x3bb0b3,
+ 0x356835,
+ 0x2f1fb6, 0x28d738, 0x228eb9, 0x1c463b, 0x15fdbc, 0xfb53d, 0x96cbe, 0x3243f,
+
+};
+
+/**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ * \par Normalizing factor:
+ * The normalizing factor is <code>sqrt(2/N)</code>, which depends on the size of transform <code>N</code>.
+ * Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes:
+ * \image html dct4NormalizingQ31Table.gif
+ */
+
+arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initializing the pointer array with the weight table base addresses of different lengths */
+ q31_t *twiddlePtr[4] = { (q31_t *) WeightsQ31_128, (q31_t *) WeightsQ31_512,
+ (q31_t *) WeightsQ31_2048, (q31_t *) WeightsQ31_8192
+ };
+
+ /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+ q31_t *pCosFactor[4] =
+ { (q31_t *) cos_factorsQ31_128, (q31_t *) cos_factorsQ31_512,
+ (q31_t *) cos_factorsQ31_2048, (q31_t *) cos_factorsQ31_8192
+ };
+
+ /* Initialize the DCT4 length */
+ S->N = N;
+
+ /* Initialize the half of DCT4 length */
+ S->Nby2 = Nby2;
+
+ /* Initialize the DCT4 Normalizing factor */
+ S->normalize = normalize;
+
+ /* Initialize Real FFT Instance */
+ S->pRfft = S_RFFT;
+
+ /* Initialize Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ switch (N)
+ {
+ /* Initialize the table modifier values */
+ case 8192u:
+ S->pTwiddle = twiddlePtr[3];
+ S->pCosFactor = pCosFactor[3];
+ break;
+ case 2048u:
+ S->pTwiddle = twiddlePtr[2];
+ S->pCosFactor = pCosFactor[2];
+ break;
+ case 512u:
+ S->pTwiddle = twiddlePtr[1];
+ S->pCosFactor = pCosFactor[1];
+ break;
+ case 128u:
+ S->pTwiddle = twiddlePtr[0];
+ S->pCosFactor = pCosFactor[0];
+ break;
+ default:
+ status = ARM_MATH_ARGUMENT_ERROR;
+ }
+
+ /* Initialize the RFFT/RIFFT Function */
+ arm_rfft_init_q31(S->pRfft, S->pCfft, S->N, 0, 1);
+
+ /* return the status of DCT4 Init function */
+ return (status);
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_q15.c
new file mode 100644
index 000000000..cc7e76c7f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_q15.c
@@ -0,0 +1,394 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_q15.c
+*
+* Description: Processing function of DCT4 & IDCT4 Q15.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ *
+ * \par Input an output formats:
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.
+ * Number of bits downscaled, depends on the size of the transform.
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:
+ *
+ * \image html dct4FormatsQ15Table.gif
+ */
+
+void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer)
+{
+ uint32_t i; /* Loop counter */
+ q15_t *weights = S->pTwiddle; /* Pointer to the Weights table */
+ q15_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */
+ q15_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */
+ q15_t in; /* Temporary variable */
+
+
+ /* DCT4 computation involves DCT2 (which is calculated using RFFT)
+ * along with some pre-processing and post-processing.
+ * Computational procedure is explained as follows:
+ * (a) Pre-processing involves multiplying input with cos factor,
+ * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
+ * where,
+ * r(n) -- output of preprocessing
+ * u(n) -- input to preprocessing(actual Source buffer)
+ * (b) Calculation of DCT2 using FFT is divided into three steps:
+ * Step1: Re-ordering of even and odd elements of input.
+ * Step2: Calculating FFT of the re-ordered input.
+ * Step3: Taking the real part of the product of FFT output and weights.
+ * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * where,
+ * Y4 -- DCT4 output, Y2 -- DCT2 output
+ * (d) Multiplying the output with the normalizing factor sqrt(2/N).
+ */
+
+ /*-------- Pre-processing ------------*/
+ /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+ arm_mult_q15(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+ arm_shift_q15(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+ /* ----------------------------------------------------------------
+ * Step1: Re-ordering of even and odd elements as
+ * pState[i] = pInlineBuffer[2*i] and
+ * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
+ ---------------------------------------------------------------------*/
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+ pS2 = pState + (S->N - 1u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+ i = (uint32_t) S->Nby2 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = (uint32_t) S->N >> 2u;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4.
+ * Compute 4 outputs at a time */
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+ /* The output of complex multiplication is in 3.13 format.
+ * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+ arm_shift_q15(pState, 2, pState, S->N * 2);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+ i = ((uint32_t) S->N - 1u) >> 2u;
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ >> 1u;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ i = ((uint32_t) S->N - 1u) % 0x4u;
+
+ while(i > 0u)
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = (uint32_t) S->N >> 2u;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializing the loop counter to N/2 */
+ i = (uint32_t) S->Nby2;
+
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter */
+ i = (uint32_t) S->N;
+
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+ /* The output of complex multiplication is in 3.13 format.
+ * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+ arm_shift_q15(pState, 2, pState, S->N * 2);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* Initializing the loop counter */
+ i = ((uint32_t) S->N - 1u);
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ >> 1u;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter */
+ i = (uint32_t) S->N;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_q31.c
new file mode 100644
index 000000000..546686b34
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_dct4_q31.c
@@ -0,0 +1,395 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_dct4_q31.c
+*
+* Description: Processing function of DCT4 & IDCT4 Q31.
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @addtogroup DCT4_IDCT4
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ * \par Input an output formats:
+ * Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process,
+ * as the conversion from DCT2 to DCT4 involves one subtraction.
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.
+ * Number of bits downscaled, depends on the size of the transform.
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:
+ *
+ * \image html dct4FormatsQ31Table.gif
+ */
+
+void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer)
+{
+ uint16_t i; /* Loop counter */
+ q31_t *weights = S->pTwiddle; /* Pointer to the Weights table */
+ q31_t *cosFact = S->pCosFactor; /* Pointer to the cos factors table */
+ q31_t *pS1, *pS2, *pbuff; /* Temporary pointers for input buffer and pState buffer */
+ q31_t in; /* Temporary variable */
+
+
+ /* DCT4 computation involves DCT2 (which is calculated using RFFT)
+ * along with some pre-processing and post-processing.
+ * Computational procedure is explained as follows:
+ * (a) Pre-processing involves multiplying input with cos factor,
+ * r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))
+ * where,
+ * r(n) -- output of preprocessing
+ * u(n) -- input to preprocessing(actual Source buffer)
+ * (b) Calculation of DCT2 using FFT is divided into three steps:
+ * Step1: Re-ordering of even and odd elements of input.
+ * Step2: Calculating FFT of the re-ordered input.
+ * Step3: Taking the real part of the product of FFT output and weights.
+ * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * where,
+ * Y4 -- DCT4 output, Y2 -- DCT2 output
+ * (d) Multiplying the output with the normalizing factor sqrt(2/N).
+ */
+
+ /*-------- Pre-processing ------------*/
+ /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+ arm_mult_q31(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+ arm_shift_q31(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+ /* ----------------------------------------------------------------
+ * Step1: Re-ordering of even and odd elements as
+ * pState[i] = pInlineBuffer[2*i] and
+ * pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2
+ ---------------------------------------------------------------------*/
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+ pS2 = pState + (S->N - 1u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+ i = S->Nby2 >> 2u;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ *pS1++ = *pbuff++;
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = S->N >> 2u;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4.
+ * Compute 4 outputs at a time */
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+ /* The output of complex multiplication is in 3.29 format.
+ * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+ arm_shift_q31(pState, 2, pState, S->N * 2);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+ i = (S->N - 1u) >> 2u;
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ >> 1u;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
+ ** a second loop below computes the remaining 1 to 3 samples. */
+ do
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
+ ** No loop unrolling is used. */
+ i = (S->N - 1u) % 0x4u;
+
+ while(i > 0u)
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+ i = S->N >> 2u;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ /* Processing with loop unrolling 4 times as N is always multiple of 4. Compute 4 outputs at a time */
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ /* Initializing the loop counter to N/2 */
+ i = S->Nby2;
+
+ do
+ {
+ /* Re-ordering of even and odd elements */
+ /* pState[i] = pInlineBuffer[2*i] */
+ *pS1++ = *pbuff++;
+ /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+ *pS2-- = *pbuff++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+ /* pbuff initialized to input buffer */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Initializing the loop counter */
+ i = S->N;
+
+ do
+ {
+ /* Writing the re-ordered output back to inplace input buffer */
+ *pbuff++ = *pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+
+ /* ---------------------------------------------------------
+ * Step2: Calculate RFFT for N-point input
+ * ---------------------------------------------------------- */
+ /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+ arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------
+ * Step3: Multiply the FFT output with the weights.
+ *----------------------------------------------------------------------*/
+ arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+ /* The output of complex multiplication is in 3.29 format.
+ * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+ arm_shift_q31(pState, 2, pState, S->N * 2);
+
+ /* ----------- Post-processing ---------- */
+ /* DCT-IV can be obtained from DCT-II by the equation,
+ * Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)
+ * Hence, Y4(0) = Y2(0)/2 */
+ /* Getting only real part from the output and Converting to DCT-IV */
+
+ /* pbuff initialized to input buffer. */
+ pbuff = pInlineBuffer;
+
+ /* pS1 initialized to pState */
+ pS1 = pState;
+
+ /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+ in = *pS1++ >> 1u;
+ /* input buffer acts as inplace, so output values are stored in the input itself. */
+ *pbuff++ = in;
+
+ /* pState pointer is incremented twice as the real values are located alternatively in the array */
+ pS1++;
+
+ /* Initializing the loop counter */
+ i = (S->N - 1u);
+
+ while(i > 0u)
+ {
+ /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+ /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+ in = *pS1++ - in;
+ *pbuff++ = in;
+ /* points to the next real value */
+ pS1++;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+
+ /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+ /* Initializing the loop counter */
+ i = S->N;
+
+ /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+ pbuff = pInlineBuffer;
+
+ do
+ {
+ /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+ in = *pbuff;
+ *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+ /* Decrement the loop counter */
+ i--;
+ } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+/**
+ * @} end of DCT4_IDCT4 group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_f32.c
new file mode 100644
index 000000000..bb3f35dd4
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_f32.c
@@ -0,0 +1,329 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_f32.c
+*
+* Description: RFFT & RIFFT Floating point process function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+extern void arm_radix4_butterfly_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier);
+
+extern void arm_radix4_butterfly_inverse_f32(
+ float32_t * pSrc,
+ uint16_t fftLen,
+ float32_t * pCoef,
+ uint16_t twidCoefModifier,
+ float32_t onebyfftLen);
+
+extern void arm_bitreversal_f32(
+ float32_t * pSrc,
+ uint16_t fftSize,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/*--------------------------------------------------------------------
+ * Internal functions prototypes
+ *--------------------------------------------------------------------*/
+
+void arm_split_rfft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pATable,
+ float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier);
+void arm_split_rifft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pATable,
+ float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier);
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+ * @brief Processing function for the floating-point RFFT/RIFFT.
+ * @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_f32 and will be removed
+ * in the future.
+ * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ */
+
+void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst)
+{
+ const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft;
+
+
+ /* Calculation of Real IFFT of input */
+ if(S->ifftFlagR == 1u)
+ {
+ /* Real IFFT core process */
+ arm_split_rifft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+
+ /* Complex radix-4 IFFT process */
+ arm_radix4_butterfly_inverse_f32(pDst, S_CFFT->fftLen,
+ S_CFFT->pTwiddle,
+ S_CFFT->twidCoefModifier,
+ S_CFFT->onebyfftLen);
+
+ /* Bit reversal process */
+ if(S->bitReverseFlagR == 1u)
+ {
+ arm_bitreversal_f32(pDst, S_CFFT->fftLen,
+ S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+ }
+ else
+ {
+
+ /* Calculation of RFFT of input */
+
+ /* Complex radix-4 FFT process */
+ arm_radix4_butterfly_f32(pSrc, S_CFFT->fftLen,
+ S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+ /* Bit reversal process */
+ if(S->bitReverseFlagR == 1u)
+ {
+ arm_bitreversal_f32(pSrc, S_CFFT->fftLen,
+ S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+
+
+ /* Real FFT core process */
+ arm_split_rfft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+ }
+
+}
+
+/**
+ * @} end of RealFFT group
+ */
+
+/**
+ * @brief Core Real FFT process
+ * @param[in] *pSrc points to the input buffer.
+ * @param[in] fftLen length of FFT.
+ * @param[in] *pATable points to the twiddle Coef A buffer.
+ * @param[in] *pBTable points to the twiddle Coef B buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_split_rfft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pATable,
+ float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier)
+{
+ uint32_t i; /* Loop Counter */
+ float32_t outR, outI; /* Temporary variables for output */
+ float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
+ float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4u * fftLen) - 1u]; /* temp pointers for output buffer */
+ float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2u * fftLen) - 1u]; /* temp pointers for input buffer */
+
+ /* Init coefficient pointers */
+ pCoefA = &pATable[modifier * 2u];
+ pCoefB = &pBTable[modifier * 2u];
+
+ i = fftLen - 1u;
+
+ while(i > 0u)
+ {
+ /*
+ outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+ + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+ /* read pATable[2 * i] */
+ CoefA1 = *pCoefA++;
+ /* pATable[2 * i + 1] */
+ CoefA2 = *pCoefA;
+
+ /* pSrc[2 * i] * pATable[2 * i] */
+ outR = *pSrc1 * CoefA1;
+ /* pSrc[2 * i] * CoefA2 */
+ outI = *pSrc1++ * CoefA2;
+
+ /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+ outR -= (*pSrc1 + *pSrc2) * CoefA2;
+ /* pSrc[2 * i + 1] * CoefA1 */
+ outI += *pSrc1++ * CoefA1;
+
+ CoefB1 = *pCoefB;
+
+ /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+ outI -= *pSrc2-- * CoefB1;
+ /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+ outI -= *pSrc2 * CoefA2;
+
+ /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+ outR += *pSrc2-- * CoefB1;
+
+ /* write output */
+ *pDst1++ = outR;
+ *pDst1++ = outI;
+
+ /* write complex conjugate output */
+ *pDst2-- = -outI;
+ *pDst2-- = outR;
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (modifier * 2u);
+ pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+ i--;
+
+ }
+
+ pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+ pDst[(2u * fftLen) + 1u] = 0.0f;
+
+ pDst[0] = pSrc[0] + pSrc[1];
+ pDst[1] = 0.0f;
+
+}
+
+
+/**
+ * @brief Core Real IFFT process
+ * @param[in] *pSrc points to the input buffer.
+ * @param[in] fftLen length of FFT.
+ * @param[in] *pATable points to the twiddle Coef A buffer.
+ * @param[in] *pBTable points to the twiddle Coef B buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_split_rifft_f32(
+ float32_t * pSrc,
+ uint32_t fftLen,
+ float32_t * pATable,
+ float32_t * pBTable,
+ float32_t * pDst,
+ uint32_t modifier)
+{
+ float32_t outR, outI; /* Temporary variables for output */
+ float32_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ float32_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
+ float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2u * fftLen) + 1u];
+
+ pCoefA = &pATable[0];
+ pCoefB = &pBTable[0];
+
+ while(fftLen > 0u)
+ {
+ /*
+ outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+
+ outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+
+ */
+
+ CoefA1 = *pCoefA++;
+ CoefA2 = *pCoefA;
+
+ /* outR = (pSrc[2 * i] * CoefA1 */
+ outR = *pSrc1 * CoefA1;
+
+ /* - pSrc[2 * i] * CoefA2 */
+ outI = -(*pSrc1++) * CoefA2;
+
+ /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+ outR += (*pSrc1 + *pSrc2) * CoefA2;
+
+ /* pSrc[2 * i + 1] * CoefA1 */
+ outI += (*pSrc1++) * CoefA1;
+
+ CoefB1 = *pCoefB;
+
+ /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+ outI -= *pSrc2-- * CoefB1;
+
+ /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+ outR += *pSrc2 * CoefB1;
+
+ /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+ outI += *pSrc2-- * CoefA2;
+
+ /* write output */
+ *pDst++ = outR;
+ *pDst++ = outI;
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (modifier * 2u);
+ pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+ /* Decrement loop count */
+ fftLen--;
+ }
+
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_fast_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_fast_f32.c
new file mode 100644
index 000000000..17ef077a7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_fast_f32.c
@@ -0,0 +1,354 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_f32.c
+*
+* Description: RFFT & RIFFT Floating point process function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void stage_rfft_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut)
+{
+ uint32_t k; /* Loop Counter */
+ float32_t twR, twI; /* RFFT Twiddle coefficients */
+ float32_t * pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */
+ float32_t *pA = p; /* increasing pointer */
+ float32_t *pB = p; /* decreasing pointer */
+ float32_t xAR, xAI, xBR, xBI; /* temporary variables */
+ float32_t t1a, t1b; /* temporary variables */
+ float32_t p0, p1, p2, p3; /* temporary variables */
+
+
+ k = (S->Sint).fftLen - 1;
+
+ /* Pack first and last sample of the frequency domain together */
+
+ xBR = pB[0];
+ xBI = pB[1];
+ xAR = pA[0];
+ xAI = pA[1];
+
+ twR = *pCoeff++ ;
+ twI = *pCoeff++ ;
+
+ // U1 = XA(1) + XB(1); % It is real
+ t1a = xBR + xAR ;
+
+ // U2 = XB(1) - XA(1); % It is imaginary
+ t1b = xBI + xAI ;
+
+ // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
+ // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
+ *pOut++ = 0.5f * ( t1a + t1b );
+ *pOut++ = 0.5f * ( t1a - t1b );
+
+ // XA(1) = 1/2*( U1 - imag(U2) + i*( U1 +imag(U2) ));
+ pB = p + 2*k;
+ pA += 2;
+
+ do
+ {
+ /*
+ function X = my_split_rfft(X, ifftFlag)
+ % X is a series of real numbers
+ L = length(X);
+ XC = X(1:2:end) +i*X(2:2:end);
+ XA = fft(XC);
+ XB = conj(XA([1 end:-1:2]));
+ TW = i*exp(-2*pi*i*[0:L/2-1]/L).';
+ for l = 2:L/2
+ XA(l) = 1/2 * (XA(l) + XB(l) + TW(l) * (XB(l) - XA(l)));
+ end
+ XA(1) = 1/2* (XA(1) + XB(1) + TW(1) * (XB(1) - XA(1))) + i*( 1/2*( XA(1) + XB(1) + i*( XA(1) - XB(1))));
+ X = XA;
+ */
+
+ xBI = pB[1];
+ xBR = pB[0];
+ xAR = pA[0];
+ xAI = pA[1];
+
+ twR = *pCoeff++;
+ twI = *pCoeff++;
+
+ t1a = xBR - xAR ;
+ t1b = xBI + xAI ;
+
+ // real(tw * (xB - xA)) = twR * (xBR - xAR) - twI * (xBI - xAI);
+ // imag(tw * (xB - xA)) = twI * (xBR - xAR) + twR * (xBI - xAI);
+ p0 = twR * t1a;
+ p1 = twI * t1a;
+ p2 = twR * t1b;
+ p3 = twI * t1b;
+
+ *pOut++ = 0.5f * (xAR + xBR + p0 + p3 ); //xAR
+ *pOut++ = 0.5f * (xAI - xBI + p1 - p2 ); //xAI
+
+ pA += 2;
+ pB -= 2;
+ k--;
+ } while(k > 0u);
+}
+
+/* Prepares data for inverse cfft */
+void merge_rfft_f32(
+arm_rfft_fast_instance_f32 * S,
+float32_t * p, float32_t * pOut)
+{
+ uint32_t k; /* Loop Counter */
+ float32_t twR, twI; /* RFFT Twiddle coefficients */
+ float32_t *pCoeff = S->pTwiddleRFFT; /* Points to RFFT Twiddle factors */
+ float32_t *pA = p; /* increasing pointer */
+ float32_t *pB = p; /* decreasing pointer */
+ float32_t xAR, xAI, xBR, xBI; /* temporary variables */
+ float32_t t1a, t1b, r, s, t, u; /* temporary variables */
+
+ k = (S->Sint).fftLen - 1;
+
+ xAR = pA[0];
+ xAI = pA[1];
+
+ pCoeff += 2 ;
+
+ *pOut++ = 0.5f * ( xAR + xAI );
+ *pOut++ = 0.5f * ( xAR - xAI );
+
+ pB = p + 2*k ;
+ pA += 2 ;
+
+ while(k > 0u)
+ {
+ /* G is half of the frequency complex spectrum */
+ //for k = 2:N
+ // Xk(k) = 1/2 * (G(k) + conj(G(N-k+2)) + Tw(k)*( G(k) - conj(G(N-k+2))));
+ xBI = pB[1] ;
+ xBR = pB[0] ;
+ xAR = pA[0];
+ xAI = pA[1];
+
+ twR = *pCoeff++;
+ twI = *pCoeff++;
+
+ t1a = xAR - xBR ;
+ t1b = xAI + xBI ;
+
+ r = twR * t1a;
+ s = twI * t1b;
+ t = twI * t1a;
+ u = twR * t1b;
+
+ // real(tw * (xA - xB)) = twR * (xAR - xBR) - twI * (xAI - xBI);
+ // imag(tw * (xA - xB)) = twI * (xAR - xBR) + twR * (xAI - xBI);
+ *pOut++ = 0.5f * (xAR + xBR - r - s ); //xAR
+ *pOut++ = 0.5f * (xAI - xBI + t - u ); //xAI
+
+ pA += 2;
+ pB -= 2;
+ k--;
+ }
+
+}
+
+/**
+* @ingroup groupTransforms
+*/
+
+/**
+ * @defgroup Fast Real FFT Functions
+ *
+ * \par
+ * The CMSIS DSP library includes specialized algorithms for computing the
+ * FFT of real data sequences. The FFT is defined over complex data but
+ * in many applications the input is real. Real FFT algorithms take advantage
+ * of the symmetry properties of the FFT and have a speed advantage over complex
+ * algorithms of the same length.
+ * \par
+ * The Fast RFFT algorith relays on the mixed radix CFFT that save processor usage.
+ * \par
+ * The real length N forward FFT of a sequence is computed using the steps shown below.
+ * \par
+ * \image html RFFT.gif "Real Fast Fourier Transform"
+ * \par
+ * The real sequence is initially treated as if it were complex to perform a CFFT.
+ * Later, a processing stage reshapes the data to obtain half of the frequency spectrum
+ * in complex format. Except the first complex number that contains the two real numbers
+ * X[0] and X[N/2] all the data is complex. In other words, the first complex sample
+ * contains two real values packed.
+ * \par
+ * The input for the inverse RFFT should keep the same format as the output of the
+ * forward RFFT. A first processing stage pre-process the data to later perform an
+ * inverse CFFT.
+ * \par
+ * \image html RIFFT.gif "Real Inverse Fast Fourier Transform"
+ * \par
+ * The algorithms for floating-point, Q15, and Q31 data are slightly different
+ * and we describe each algorithm in turn.
+ * \par Floating-point
+ * The main functions are <code>arm_rfft_fast_f32()</code>
+ * and <code>arm_rfft_fast_init_f32()</code>. The older functions
+ * <code>arm_rfft_f32()</code> and <code>arm_rfft_init_f32()</code> have been
+ * deprecated but are still documented.
+ * \par
+ * The FFT of a real N-point sequence has even symmetry in the frequency
+ * domain. The second half of the data equals the conjugate of the first half
+ * flipped in frequency:
+ * <pre>
+ *X[0] - real data
+ *X[1] - complex data
+ *X[2] - complex data
+ *...
+ *X[fftLen/2-1] - complex data
+ *X[fftLen/2] - real data
+ *X[fftLen/2+1] - conjugate of X[fftLen/2-1]
+ *X[fftLen/2+2] - conjugate of X[fftLen/2-2]
+ *...
+ *X[fftLen-1] - conjugate of X[1]
+ * </pre>
+ * Looking at the data, we see that we can uniquely represent the FFT using only
+ * <pre>
+ *N/2+1 samples:
+ *X[0] - real data
+ *X[1] - complex data
+ *X[2] - complex data
+ *...
+ *X[fftLen/2-1] - complex data
+ *X[fftLen/2] - real data
+ * </pre>
+ * Looking more closely we see that the first and last samples are real valued.
+ * They can be packed together and we can thus represent the FFT of an N-point
+ * real sequence by N/2 complex values:
+ * <pre>
+ *X[0],X[N/2] - packed real data: X[0] + jX[N/2]
+ *X[1] - complex data
+ *X[2] - complex data
+ *...
+ *X[fftLen/2-1] - complex data
+ * </pre>
+ * The real FFT functions pack the frequency domain data in this fashion. The
+ * forward transform outputs the data in this form and the inverse transform
+ * expects input data in this form. The function always performs the needed
+ * bitreversal so that the input and output data is always in normal order. The
+ * functions support lengths of [32, 64, 128, ..., 4096] samples.
+ * \par
+ * The forward and inverse real FFT functions apply the standard FFT scaling; no
+ * scaling on the forward transform and 1/fftLen scaling on the inverse
+ * transform.
+ * \par Q15 and Q31
+ * The real algorithms are defined in a similar manner and utilize N/2 complex
+ * transforms behind the scenes. In the case of fixed-point data, a radix-4
+ * complex transform is performed and this limits the allows sequence lengths to
+ * 128, 512, and 2048 samples.
+ * \par
+ * TBD. We need to document input and output order of data.
+ * \par
+ * The complex transforms used internally include scaling to prevent fixed-point
+ * overflows. The overall scaling equals 1/(fftLen/2).
+ * \par
+ * A separate instance structure must be defined for each transform used but
+ * twiddle factor and bit reversal tables can be reused.
+ * \par
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Sets the values of the internal structure fields.
+ * - Initializes twiddle factor table and bit reversal table pointers.
+ * - Initializes the internal complex FFT data structure.
+ * \par
+ * Use of the initialization function is optional.
+ * However, if the initialization function is used, then the instance structure
+ * cannot be placed into a const data section. To place an instance structure
+ * into a const data section, the instance structure should be manually
+ * initialized as follows:
+ * <pre>
+ *arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+ *arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};
+ * </pre>
+ * where <code>fftLenReal</code> is the length of the real transform;
+ * <code>fftLenBy2</code> length of the internal complex transform.
+ * <code>ifftFlagR</code> Selects forward (=0) or inverse (=1) transform.
+ * <code>bitReverseFlagR</code> Selects bit reversed output (=0) or normal order
+ * output (=1).
+ * <code>twidCoefRModifier</code> stride modifier for the twiddle factor table.
+ * The value is based on the FFT length;
+ * <code>pTwiddleAReal</code>points to the A array of twiddle coefficients;
+ * <code>pTwiddleBReal</code>points to the B array of twiddle coefficients;
+ * <code>pCfft</code> points to the CFFT Instance structure. The CFFT structure
+ * must also be initialized. Refer to arm_cfft_radix4_f32() for details regarding
+ * static initialization of the complex FFT instance structure.
+ */
+
+/**
+* @addtogroup RealFFT
+* @{
+*/
+
+/**
+* @brief Processing function for the floating-point real FFT.
+* @param[in] *S points to an arm_rfft_fast_instance_f32 structure.
+* @param[in] *p points to the input buffer.
+* @param[in] *pOut points to an arm_rfft_fast_instance_f32 structure.
+* @param[in] ifftFlag RFFT if flag is 0, RIFFT if flag is 1
+* @return none.
+*/
+
+void arm_rfft_fast_f32(
+arm_rfft_fast_instance_f32 * S,
+float32_t * p, float32_t * pOut,
+uint8_t ifftFlag)
+{
+ arm_cfft_instance_f32 * Sint = &(S->Sint);
+ Sint->fftLen = S->fftLenRFFT / 2;
+
+ /* Calculation of Real FFT */
+ if(ifftFlag)
+ {
+ /* Real FFT comression */
+ merge_rfft_f32(S, p, pOut);
+
+ /* Complex radix-4 IFFT process */
+ arm_cfft_f32( Sint, pOut, ifftFlag, 1);
+ }
+ else
+ {
+ /* Calculation of RFFT of input */
+ arm_cfft_f32( Sint, p, ifftFlag, 1);
+
+ /* Real FFT extraction */
+ stage_rfft_f32(S, p, pOut);
+ }
+}
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_fast_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_fast_init_f32.c
new file mode 100644
index 000000000..c41537942
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_fast_init_f32.c
@@ -0,0 +1,139 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_cfft_init_f32.c
+*
+* Description: Split Radix Decimation in Frequency CFFT Floating point processing function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+* @brief Initialization function for the floating-point real FFT.
+* @param[in,out] *S points to an arm_rfft_fast_instance_f32 structure.
+* @param[in] fftLen length of the Real Sequence.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLen</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>ifftFlag</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlag for calculation of CIFFT otherwise RFFT is calculated
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* The parameter <code>fftLen</code> Specifies length of RFFT/CIFFT process. Supported FFT Lengths are 16, 32, 64, 128, 256, 512, 1024, 2048, 4096.
+* \par
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.
+*/
+arm_status arm_rfft_fast_init_f32(
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen)
+{
+ arm_cfft_instance_f32 * Sint;
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+ /* Initialise the FFT length */
+ Sint = &(S->Sint);
+ Sint->fftLen = fftLen/2;
+ S->fftLenRFFT = fftLen;
+ /* Initialise the Twiddle coefficient pointer */
+ // S->pTwiddle = (float32_t *) twiddleCoef;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (Sint->fftLen)
+ {
+ case 4096u:
+ /* Initializations of structure parameters for 4096 point FFT */
+ /* Initialise the bit reversal table length */
+ Sint->bitRevLength = ARMBITREVINDEXTABLE4096_TABLE_LENGTH;
+ /* Initialise the bit reversal table pointer */
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable4096;
+ /* Initialise the 1/fftLen Value */
+ break;
+ case 2048u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE2048_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable2048;
+ break;
+ case 1024u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE1024_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable1024;
+ break;
+ case 512u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_512_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable512;
+ break;
+ case 256u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_256_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable256;
+ break;
+ case 128u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE_128_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable128;
+ break;
+ case 64u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE__64_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable64;
+ break;
+ case 32u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE__32_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable32;
+ break;
+ case 16u:
+ Sint->bitRevLength = ARMBITREVINDEXTABLE__16_TABLE_LENGTH;
+ Sint->pBitRevTable = (uint16_t *)armBitRevIndexTable16;
+ break;
+ default:
+ /* Reporting argument error if fftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ return (status);
+}
+
+/**
+ * @} end of RealFFT group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_f32.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_f32.c
new file mode 100644
index 000000000..2f0032968
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_f32.c
@@ -0,0 +1,8376 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_init_f32.c
+*
+* Description: RFFT & RIFFT Floating point initialisation function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+* \par
+* Generation of realCoefA array:
+* \par
+* n = 4096
+* <pre>for (i = 0; i < n; i++)
+* {
+* pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+* pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* } </pre>
+*/
+
+
+
+static const float32_t realCoefA[8192] = {
+ 0.500000000000000f, -0.500000000000000f, 0.499616503715515f,
+ -0.499999850988388f,
+ 0.499233007431030f, -0.499999403953552f, 0.498849511146545f,
+ -0.499998688697815f,
+ 0.498466014862061f, -0.499997645616531f, 0.498082518577576f,
+ -0.499996334314346f,
+ 0.497699022293091f, -0.499994695186615f, 0.497315555810928f,
+ -0.499992787837982f,
+ 0.496932059526443f, -0.499990582466125f, 0.496548563241959f,
+ -0.499988079071045f,
+ 0.496165096759796f, -0.499985307455063f, 0.495781600475311f,
+ -0.499982208013535f,
+ 0.495398133993149f, -0.499978810548782f, 0.495014637708664f,
+ -0.499975144863129f,
+ 0.494631171226501f, -0.499971181154251f, 0.494247704744339f,
+ -0.499966919422150f,
+ 0.493864238262177f, -0.499962359666824f, 0.493480771780014f,
+ -0.499957501888275f,
+ 0.493097305297852f, -0.499952346086502f, 0.492713838815689f,
+ -0.499946922063828f,
+ 0.492330402135849f, -0.499941170215607f, 0.491946935653687f,
+ -0.499935150146484f,
+ 0.491563498973846f, -0.499928832054138f, 0.491180062294006f,
+ -0.499922215938568f,
+ 0.490796625614166f, -0.499915301799774f, 0.490413218736649f,
+ -0.499908089637756f,
+ 0.490029782056808f, -0.499900579452515f, 0.489646375179291f,
+ -0.499892801046371f,
+ 0.489262968301773f, -0.499884694814682f, 0.488879561424255f,
+ -0.499876320362091f,
+ 0.488496154546738f, -0.499867647886276f, 0.488112777471542f,
+ -0.499858677387238f,
+ 0.487729400396347f, -0.499849408864975f, 0.487346023321152f,
+ -0.499839842319489f,
+ 0.486962646245956f, -0.499830007553101f, 0.486579269170761f,
+ -0.499819844961166f,
+ 0.486195921897888f, -0.499809414148331f, 0.485812574625015f,
+ -0.499798685312271f,
+ 0.485429257154465f, -0.499787658452988f, 0.485045909881592f,
+ -0.499776333570480f,
+ 0.484662592411041f, -0.499764710664749f, 0.484279274940491f,
+ -0.499752789735794f,
+ 0.483895987272263f, -0.499740600585938f, 0.483512699604034f,
+ -0.499728083610535f,
+ 0.483129411935806f, -0.499715298414230f, 0.482746154069901f,
+ -0.499702215194702f,
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+ 0.494631171226501f, 0.499971181154251f, 0.495014637708664f,
+ 0.499975144863129f,
+ 0.495398133993149f, 0.499978810548782f, 0.495781600475311f,
+ 0.499982208013535f,
+ 0.496165096759796f, 0.499985307455063f, 0.496548563241959f,
+ 0.499988079071045f,
+ 0.496932059526443f, 0.499990582466125f, 0.497315555810928f,
+ 0.499992787837982f,
+ 0.497699022293091f, 0.499994695186615f, 0.498082518577576f,
+ 0.499996334314346f,
+ 0.498466014862061f, 0.499997645616531f, 0.498849511146545f,
+ 0.499998688697815f,
+ 0.499233007431030f, 0.499999403953552f, 0.499616503715515f,
+ 0.499999850988388f,
+};
+
+
+/**
+* \par
+* Generation of realCoefB array:
+* \par
+* n = 4096
+* <pre>for (i = 0; i < n; i++)
+* {
+* pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+* pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* } </pre>
+*
+*/
+static const float32_t realCoefB[8192] = {
+ 0.500000000000000f, 0.500000000000000f, 0.500383496284485f,
+ 0.499999850988388f,
+ 0.500766992568970f, 0.499999403953552f, 0.501150488853455f,
+ 0.499998688697815f,
+ 0.501533985137939f, 0.499997645616531f, 0.501917481422424f,
+ 0.499996334314346f,
+ 0.502300977706909f, 0.499994695186615f, 0.502684473991394f,
+ 0.499992787837982f,
+ 0.503067970275879f, 0.499990582466125f, 0.503451406955719f,
+ 0.499988079071045f,
+ 0.503834903240204f, 0.499985307455063f, 0.504218399524689f,
+ 0.499982208013535f,
+ 0.504601895809174f, 0.499978810548782f, 0.504985332489014f,
+ 0.499975144863129f,
+ 0.505368828773499f, 0.499971181154251f, 0.505752325057983f,
+ 0.499966919422150f,
+ 0.506135761737823f, 0.499962359666824f, 0.506519258022308f,
+ 0.499957501888275f,
+ 0.506902694702148f, 0.499952346086502f, 0.507286131381989f,
+ 0.499946922063828f,
+ 0.507669627666473f, 0.499941170215607f, 0.508053064346313f,
+ 0.499935150146484f,
+ 0.508436501026154f, 0.499928832054138f, 0.508819937705994f,
+ 0.499922215938568f,
+ 0.509203374385834f, 0.499915301799774f, 0.509586811065674f,
+ 0.499908089637756f,
+ 0.509970188140869f, 0.499900579452515f, 0.510353624820709f,
+ 0.499892801046371f,
+ 0.510737061500549f, 0.499884694814682f, 0.511120438575745f,
+ 0.499876320362091f,
+ 0.511503815650940f, 0.499867647886276f, 0.511887252330780f,
+ 0.499858677387238f,
+ 0.512270629405975f, 0.499849408864975f, 0.512654006481171f,
+ 0.499839842319489f,
+ 0.513037383556366f, 0.499830007553101f, 0.513420701026917f,
+ 0.499819844961166f,
+ 0.513804078102112f, 0.499809414148331f, 0.514187395572662f,
+ 0.499798685312271f,
+ 0.514570772647858f, 0.499787658452988f, 0.514954090118408f,
+ 0.499776333570480f,
+ 0.515337407588959f, 0.499764710664749f, 0.515720725059509f,
+ 0.499752789735794f,
+ 0.516103982925415f, 0.499740600585938f, 0.516487300395966f,
+ 0.499728083610535f,
+ 0.516870558261871f, 0.499715298414230f, 0.517253875732422f,
+ 0.499702215194702f,
+ 0.517637133598328f, 0.499688833951950f, 0.518020391464233f,
+ 0.499675154685974f,
+ 0.518403589725494f, 0.499661177396774f, 0.518786847591400f,
+ 0.499646931886673f,
+ 0.519170045852661f, 0.499632388353348f, 0.519553244113922f,
+ 0.499617516994476f,
+ 0.519936442375183f, 0.499602377414703f, 0.520319640636444f,
+ 0.499586939811707f,
+ 0.520702838897705f, 0.499571204185486f, 0.521085977554321f,
+ 0.499555170536041f,
+ 0.521469116210938f, 0.499538868665695f, 0.521852254867554f,
+ 0.499522238969803f,
+ 0.522235393524170f, 0.499505341053009f, 0.522618472576141f,
+ 0.499488145112991f,
+ 0.523001611232758f, 0.499470651149750f, 0.523384690284729f,
+ 0.499452859163284f,
+ 0.523767769336700f, 0.499434769153595f, 0.524150788784027f,
+ 0.499416410923004f,
+ 0.524533808231354f, 0.499397724866867f, 0.524916887283325f,
+ 0.499378770589828f,
+ 0.525299847126007f, 0.499359518289566f, 0.525682866573334f,
+ 0.499339967966080f,
+ 0.526065826416016f, 0.499320119619370f, 0.526448845863342f,
+ 0.499299973249435f,
+ 0.526831746101379f, 0.499279528856277f, 0.527214705944061f,
+ 0.499258816242218f,
+ 0.527597606182098f, 0.499237775802612f, 0.527980506420136f,
+ 0.499216467142105f,
+ 0.528363406658173f, 0.499194860458374f, 0.528746306896210f,
+ 0.499172955751419f,
+ 0.529129147529602f, 0.499150782823563f, 0.529511988162994f,
+ 0.499128282070160f,
+ 0.529894769191742f, 0.499105513095856f, 0.530277609825134f,
+ 0.499082416296005f,
+ 0.530660390853882f, 0.499059051275253f, 0.531043112277985f,
+ 0.499035388231277f,
+ 0.531425893306732f, 0.499011427164078f, 0.531808614730835f,
+ 0.498987197875977f,
+ 0.532191336154938f, 0.498962640762329f, 0.532573997974396f,
+ 0.498937815427780f,
+ 0.532956659793854f, 0.498912662267685f, 0.533339321613312f,
+ 0.498887240886688f,
+ 0.533721983432770f, 0.498861521482468f, 0.534104585647583f,
+ 0.498835533857346f,
+ 0.534487187862396f, 0.498809218406677f, 0.534869730472565f,
+ 0.498782604932785f,
+ 0.535252273082733f, 0.498755723237991f, 0.535634815692902f,
+ 0.498728543519974f,
+ 0.536017298698425f, 0.498701065778732f, 0.536399841308594f,
+ 0.498673290014267f,
+ 0.536782264709473f, 0.498645216226578f, 0.537164747714996f,
+ 0.498616874217987f,
+ 0.537547171115875f, 0.498588204383850f, 0.537929534912109f,
+ 0.498559266328812f,
+ 0.538311958312988f, 0.498530030250549f, 0.538694262504578f,
+ 0.498500496149063f,
+ 0.539076626300812f, 0.498470664024353f, 0.539458930492401f,
+ 0.498440563678741f,
+ 0.539841234683990f, 0.498410135507584f, 0.540223479270935f,
+ 0.498379439115524f,
+ 0.540605723857880f, 0.498348444700241f, 0.540987968444824f,
+ 0.498317152261734f,
+ 0.541370153427124f, 0.498285561800003f, 0.541752278804779f,
+ 0.498253703117371f,
+ 0.542134463787079f, 0.498221516609192f, 0.542516589164734f,
+ 0.498189061880112f,
+ 0.542898654937744f, 0.498156309127808f, 0.543280720710754f,
+ 0.498123258352280f,
+ 0.543662786483765f, 0.498089909553528f, 0.544044792652130f,
+ 0.498056292533875f,
+ 0.544426798820496f, 0.498022347688675f, 0.544808745384216f,
+ 0.497988134622574f,
+ 0.545190691947937f, 0.497953623533249f, 0.545572578907013f,
+ 0.497918814420700f,
+ 0.545954465866089f, 0.497883707284927f, 0.546336352825165f,
+ 0.497848302125931f,
+ 0.546718180179596f, 0.497812628746033f, 0.547099947929382f,
+ 0.497776657342911f,
+ 0.547481775283813f, 0.497740387916565f, 0.547863483428955f,
+ 0.497703820466995f,
+ 0.548245191574097f, 0.497666954994202f, 0.548626899719238f,
+ 0.497629791498184f,
+ 0.549008548259735f, 0.497592359781265f, 0.549390196800232f,
+ 0.497554630041122f,
+ 0.549771785736084f, 0.497516602277756f, 0.550153374671936f,
+ 0.497478276491165f,
+ 0.550534904003143f, 0.497439652681351f, 0.550916433334351f,
+ 0.497400760650635f,
+ 0.551297962665558f, 0.497361570596695f, 0.551679372787476f,
+ 0.497322082519531f,
+ 0.552060842514038f, 0.497282296419144f, 0.552442193031311f,
+ 0.497242212295532f,
+ 0.552823603153229f, 0.497201830148697f, 0.553204894065857f,
+ 0.497161179780960f,
+ 0.553586184978485f, 0.497120231389999f, 0.553967475891113f,
+ 0.497078984975815f,
+ 0.554348707199097f, 0.497037440538406f, 0.554729938507080f,
+ 0.496995598077774f,
+ 0.555111110210419f, 0.496953487396240f, 0.555492222309113f,
+ 0.496911078691483f,
+ 0.555873334407806f, 0.496868371963501f, 0.556254446506500f,
+ 0.496825367212296f,
+ 0.556635499000549f, 0.496782064437866f, 0.557016491889954f,
+ 0.496738493442535f,
+ 0.557397484779358f, 0.496694594621658f, 0.557778418064117f,
+ 0.496650427579880f,
+ 0.558159291744232f, 0.496605962514877f, 0.558540165424347f,
+ 0.496561229228973f,
+ 0.558921039104462f, 0.496516168117523f, 0.559301853179932f,
+ 0.496470838785172f,
+ 0.559682607650757f, 0.496425211429596f, 0.560063362121582f,
+ 0.496379286050797f,
+ 0.560444056987762f, 0.496333062648773f, 0.560824692249298f,
+ 0.496286571025848f,
+ 0.561205327510834f, 0.496239781379700f, 0.561585903167725f,
+ 0.496192663908005f,
+ 0.561966478824615f, 0.496145308017731f, 0.562346994876862f,
+ 0.496097624301910f,
+ 0.562727510929108f, 0.496049642562866f, 0.563107967376709f,
+ 0.496001392602921f,
+ 0.563488364219666f, 0.495952844619751f, 0.563868701457977f,
+ 0.495903998613358f,
+ 0.564249038696289f, 0.495854884386063f, 0.564629375934601f,
+ 0.495805442333221f,
+ 0.565009593963623f, 0.495755732059479f, 0.565389811992645f,
+ 0.495705723762512f,
+ 0.565770030021667f, 0.495655417442322f, 0.566150128841400f,
+ 0.495604842901230f,
+ 0.566530287265778f, 0.495553970336914f, 0.566910326480865f,
+ 0.495502769947052f,
+ 0.567290365695953f, 0.495451331138611f, 0.567670345306396f,
+ 0.495399564504623f,
+ 0.568050265312195f, 0.495347499847412f, 0.568430185317993f,
+ 0.495295166969299f,
+ 0.568810045719147f, 0.495242536067963f, 0.569189906120300f,
+ 0.495189607143402f,
+ 0.569569647312164f, 0.495136409997940f, 0.569949388504028f,
+ 0.495082914829254f,
+ 0.570329129695892f, 0.495029091835022f, 0.570708811283112f,
+ 0.494975030422211f,
+ 0.571088373661041f, 0.494920641183853f, 0.571467995643616f,
+ 0.494865983724594f,
+ 0.571847498416901f, 0.494810998439789f, 0.572227001190186f,
+ 0.494755744934082f,
+ 0.572606444358826f, 0.494700223207474f, 0.572985887527466f,
+ 0.494644373655319f,
+ 0.573365211486816f, 0.494588255882263f, 0.573744535446167f,
+ 0.494531840085983f,
+ 0.574123859405518f, 0.494475126266479f, 0.574503064155579f,
+ 0.494418144226074f,
+ 0.574882268905640f, 0.494360834360123f, 0.575261414051056f,
+ 0.494303256273270f,
+ 0.575640499591827f, 0.494245409965515f, 0.576019585132599f,
+ 0.494187235832214f,
+ 0.576398611068726f, 0.494128793478012f, 0.576777577400208f,
+ 0.494070053100586f,
+ 0.577156484127045f, 0.494011014699936f, 0.577535390853882f,
+ 0.493951678276062f,
+ 0.577914178371429f, 0.493892073631287f, 0.578292965888977f,
+ 0.493832170963287f,
+ 0.578671753406525f, 0.493771970272064f, 0.579050421714783f,
+ 0.493711471557617f,
+ 0.579429090023041f, 0.493650704622269f, 0.579807698726654f,
+ 0.493589639663696f,
+ 0.580186247825623f, 0.493528276681900f, 0.580564737319946f,
+ 0.493466645479202f,
+ 0.580943167209625f, 0.493404686450958f, 0.581321597099304f,
+ 0.493342459201813f,
+ 0.581699967384338f, 0.493279963731766f, 0.582078278064728f,
+ 0.493217140436172f,
+ 0.582456588745117f, 0.493154048919678f, 0.582834780216217f,
+ 0.493090659379959f,
+ 0.583212971687317f, 0.493026971817017f, 0.583591103553772f,
+ 0.492963016033173f,
+ 0.583969175815582f, 0.492898762226105f, 0.584347188472748f,
+ 0.492834210395813f,
+ 0.584725141525269f, 0.492769360542297f, 0.585103094577789f,
+ 0.492704242467880f,
+ 0.585480928421021f, 0.492638826370239f, 0.585858762264252f,
+ 0.492573112249374f,
+ 0.586236536502838f, 0.492507129907608f, 0.586614251136780f,
+ 0.492440819740295f,
+ 0.586991965770721f, 0.492374241352081f, 0.587369561195374f,
+ 0.492307394742966f,
+ 0.587747097015381f, 0.492240220308304f, 0.588124632835388f,
+ 0.492172777652740f,
+ 0.588502109050751f, 0.492105036973953f, 0.588879525661469f,
+ 0.492037028074265f,
+ 0.589256882667542f, 0.491968721151352f, 0.589634180068970f,
+ 0.491900116205215f,
+ 0.590011477470398f, 0.491831213235855f, 0.590388655662537f,
+ 0.491762012243271f,
+ 0.590765833854675f, 0.491692543029785f, 0.591142892837524f,
+ 0.491622805595398f,
+ 0.591519951820374f, 0.491552740335464f, 0.591896951198578f,
+ 0.491482406854630f,
+ 0.592273890972137f, 0.491411775350571f, 0.592650771141052f,
+ 0.491340845823288f,
+ 0.593027591705322f, 0.491269648075104f, 0.593404352664948f,
+ 0.491198152303696f,
+ 0.593781054019928f, 0.491126358509064f, 0.594157755374908f,
+ 0.491054296493530f,
+ 0.594534337520599f, 0.490981936454773f, 0.594910860061646f,
+ 0.490909278392792f,
+ 0.595287382602692f, 0.490836352109909f, 0.595663845539093f,
+ 0.490763127803802f,
+ 0.596040189266205f, 0.490689605474472f, 0.596416532993317f,
+ 0.490615785121918f,
+ 0.596792817115784f, 0.490541696548462f, 0.597168982028961f,
+ 0.490467309951782f,
+ 0.597545146942139f, 0.490392625331879f, 0.597921252250671f,
+ 0.490317672491074f,
+ 0.598297297954559f, 0.490242421627045f, 0.598673284053802f,
+ 0.490166902542114f,
+ 0.599049210548401f, 0.490091055631638f, 0.599425077438354f,
+ 0.490014940500259f,
+ 0.599800884723663f, 0.489938557147980f, 0.600176632404327f,
+ 0.489861875772476f,
+ 0.600552320480347f, 0.489784896373749f, 0.600927948951721f,
+ 0.489707618951797f,
+ 0.601303517818451f, 0.489630073308945f, 0.601679027080536f,
+ 0.489552229642868f,
+ 0.602054476737976f, 0.489474087953568f, 0.602429866790771f,
+ 0.489395678043365f,
+ 0.602805197238922f, 0.489316970109940f, 0.603180468082428f,
+ 0.489237964153290f,
+ 0.603555679321289f, 0.489158689975739f, 0.603930830955505f,
+ 0.489079117774963f,
+ 0.604305922985077f, 0.488999247550964f, 0.604680955410004f,
+ 0.488919109106064f,
+ 0.605055928230286f, 0.488838672637939f, 0.605430841445923f,
+ 0.488757967948914f,
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+ 0.488595664501190f,
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+ 0.488432198762894f,
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+ 0.488267600536346f,
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+ 0.488101840019226f,
+ 0.608802139759064f, 0.488018542528152f, 0.609176397323608f,
+ 0.487934947013855f,
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+ 0.487766891717911f,
+ 0.610298871994019f, 0.487682431936264f, 0.610672831535339f,
+ 0.487597703933716f,
+ 0.611046791076660f, 0.487512677907944f, 0.611420691013336f,
+ 0.487427353858948f,
+ 0.611794531345367f, 0.487341761589050f, 0.612168252468109f,
+ 0.487255871295929f,
+ 0.612541973590851f, 0.487169682979584f, 0.612915575504303f,
+ 0.487083226442337f,
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+ 0.486909449100494f,
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+ 0.486734509468079f,
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+ 0.486558437347412f,
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+ 0.486381232738495f,
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+ 0.486202865839005f,
+ 0.617020964622498f, 0.486113250255585f, 0.617393791675568f,
+ 0.486023366451263f,
+ 0.617766559123993f, 0.485933154821396f, 0.618139207363129f,
+ 0.485842704772949f,
+ 0.618511795997620f, 0.485751956701279f, 0.618884325027466f,
+ 0.485660910606384f,
+ 0.619256794452667f, 0.485569566488266f, 0.619629204273224f,
+ 0.485477954149246f,
+ 0.620001494884491f, 0.485386073589325f, 0.620373785495758f,
+ 0.485293895006180f,
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+ -0.498189061880112f,
+ 0.542134463787079f, -0.498221516609192f, 0.541752278804779f,
+ -0.498253703117371f,
+ 0.541370153427124f, -0.498285561800003f, 0.540987968444824f,
+ -0.498317152261734f,
+ 0.540605723857880f, -0.498348444700241f, 0.540223479270935f,
+ -0.498379439115524f,
+ 0.539841234683990f, -0.498410135507584f, 0.539458930492401f,
+ -0.498440563678741f,
+ 0.539076626300812f, -0.498470664024353f, 0.538694262504578f,
+ -0.498500496149063f,
+ 0.538311958312988f, -0.498530030250549f, 0.537929534912109f,
+ -0.498559266328812f,
+ 0.537547171115875f, -0.498588204383850f, 0.537164747714996f,
+ -0.498616874217987f,
+ 0.536782264709473f, -0.498645216226578f, 0.536399841308594f,
+ -0.498673290014267f,
+ 0.536017298698425f, -0.498701065778732f, 0.535634815692902f,
+ -0.498728543519974f,
+ 0.535252273082733f, -0.498755723237991f, 0.534869730472565f,
+ -0.498782604932785f,
+ 0.534487187862396f, -0.498809218406677f, 0.534104585647583f,
+ -0.498835533857346f,
+ 0.533721983432770f, -0.498861521482468f, 0.533339321613312f,
+ -0.498887240886688f,
+ 0.532956659793854f, -0.498912662267685f, 0.532573997974396f,
+ -0.498937815427780f,
+ 0.532191336154938f, -0.498962640762329f, 0.531808614730835f,
+ -0.498987197875977f,
+ 0.531425893306732f, -0.499011427164078f, 0.531043112277985f,
+ -0.499035388231277f,
+ 0.530660390853882f, -0.499059051275253f, 0.530277609825134f,
+ -0.499082416296005f,
+ 0.529894769191742f, -0.499105513095856f, 0.529511988162994f,
+ -0.499128282070160f,
+ 0.529129147529602f, -0.499150782823563f, 0.528746306896210f,
+ -0.499172955751419f,
+ 0.528363406658173f, -0.499194860458374f, 0.527980506420136f,
+ -0.499216467142105f,
+ 0.527597606182098f, -0.499237775802612f, 0.527214705944061f,
+ -0.499258816242218f,
+ 0.526831746101379f, -0.499279528856277f, 0.526448845863342f,
+ -0.499299973249435f,
+ 0.526065826416016f, -0.499320119619370f, 0.525682866573334f,
+ -0.499339967966080f,
+ 0.525299847126007f, -0.499359518289566f, 0.524916887283325f,
+ -0.499378770589828f,
+ 0.524533808231354f, -0.499397724866867f, 0.524150788784027f,
+ -0.499416410923004f,
+ 0.523767769336700f, -0.499434769153595f, 0.523384690284729f,
+ -0.499452859163284f,
+ 0.523001611232758f, -0.499470651149750f, 0.522618472576141f,
+ -0.499488145112991f,
+ 0.522235393524170f, -0.499505341053009f, 0.521852254867554f,
+ -0.499522238969803f,
+ 0.521469116210938f, -0.499538868665695f, 0.521085977554321f,
+ -0.499555170536041f,
+ 0.520702838897705f, -0.499571204185486f, 0.520319640636444f,
+ -0.499586939811707f,
+ 0.519936442375183f, -0.499602377414703f, 0.519553244113922f,
+ -0.499617516994476f,
+ 0.519170045852661f, -0.499632388353348f, 0.518786847591400f,
+ -0.499646931886673f,
+ 0.518403589725494f, -0.499661177396774f, 0.518020391464233f,
+ -0.499675154685974f,
+ 0.517637133598328f, -0.499688833951950f, 0.517253875732422f,
+ -0.499702215194702f,
+ 0.516870558261871f, -0.499715298414230f, 0.516487300395966f,
+ -0.499728083610535f,
+ 0.516103982925415f, -0.499740600585938f, 0.515720725059509f,
+ -0.499752789735794f,
+ 0.515337407588959f, -0.499764710664749f, 0.514954090118408f,
+ -0.499776333570480f,
+ 0.514570772647858f, -0.499787658452988f, 0.514187395572662f,
+ -0.499798685312271f,
+ 0.513804078102112f, -0.499809414148331f, 0.513420701026917f,
+ -0.499819844961166f,
+ 0.513037383556366f, -0.499830007553101f, 0.512654006481171f,
+ -0.499839842319489f,
+ 0.512270629405975f, -0.499849408864975f, 0.511887252330780f,
+ -0.499858677387238f,
+ 0.511503815650940f, -0.499867647886276f, 0.511120438575745f,
+ -0.499876320362091f,
+ 0.510737061500549f, -0.499884694814682f, 0.510353624820709f,
+ -0.499892801046371f,
+ 0.509970188140869f, -0.499900579452515f, 0.509586811065674f,
+ -0.499908089637756f,
+ 0.509203374385834f, -0.499915301799774f, 0.508819937705994f,
+ -0.499922215938568f,
+ 0.508436501026154f, -0.499928832054138f, 0.508053064346313f,
+ -0.499935150146484f,
+ 0.507669627666473f, -0.499941170215607f, 0.507286131381989f,
+ -0.499946922063828f,
+ 0.506902694702148f, -0.499952346086502f, 0.506519258022308f,
+ -0.499957501888275f,
+ 0.506135761737823f, -0.499962359666824f, 0.505752325057983f,
+ -0.499966919422150f,
+ 0.505368828773499f, -0.499971181154251f, 0.504985332489014f,
+ -0.499975144863129f,
+ 0.504601895809174f, -0.499978810548782f, 0.504218399524689f,
+ -0.499982208013535f,
+ 0.503834903240204f, -0.499985307455063f, 0.503451406955719f,
+ -0.499988079071045f,
+ 0.503067970275879f, -0.499990582466125f, 0.502684473991394f,
+ -0.499992787837982f,
+ 0.502300977706909f, -0.499994695186615f, 0.501917481422424f,
+ -0.499996334314346f,
+ 0.501533985137939f, -0.499997645616531f, 0.501150488853455f,
+ -0.499998688697815f,
+ 0.500766992568970f, -0.499999403953552f, 0.500383496284485f,
+ -0.499999850988388f,
+};
+
+
+
+/**
+* @brief Initialization function for the floating-point RFFT/RIFFT.
+* @deprecated Do not use this function. It has been superceded by \ref arm_rfft_fast_init_f32 and will be removed
+* in the future.
+* @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure.
+* @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure.
+* @param[in] fftLenReal length of the FFT.
+* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>fftLenReal</code> Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.
+* \par
+* The parameter <code>ifftFlagR</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* This function also initializes Twiddle factor table.
+*/
+
+arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag)
+{
+
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialize the Real FFT length */
+ S->fftLenReal = (uint16_t) fftLenReal;
+
+ /* Initialize the Complex FFT length */
+ S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+ /* Initialize the Twiddle coefficientA pointer */
+ S->pTwiddleAReal = (float32_t *) realCoefA;
+
+ /* Initialize the Twiddle coefficientB pointer */
+ S->pTwiddleBReal = (float32_t *) realCoefB;
+
+ /* Initialize the Flag for selection of RFFT or RIFFT */
+ S->ifftFlagR = (uint8_t) ifftFlagR;
+
+ /* Initialize the Flag for calculation Bit reversal or not */
+ S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+ /* Initializations of structure parameters depending on the FFT length */
+ switch (S->fftLenReal)
+ {
+ /* Init table modifier value */
+ case 8192u:
+ S->twidCoefRModifier = 1u;
+ break;
+ case 2048u:
+ S->twidCoefRModifier = 4u;
+ break;
+ case 512u:
+ S->twidCoefRModifier = 16u;
+ break;
+ case 128u:
+ S->twidCoefRModifier = 64u;
+ break;
+ default:
+ /* Reporting argument error if rfftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ /* Init Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ if(S->ifftFlagR)
+ {
+ /* Initializes the CIFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1u, 0u);
+ }
+ else
+ {
+ /* Initializes the CFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0u, 0u);
+ }
+
+ /* return the status of RFFT Init function */
+ return (status);
+
+}
+
+ /**
+ * @} end of RealFFT group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_q15.c
new file mode 100644
index 000000000..31fa6c2e5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_q15.c
@@ -0,0 +1,2234 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_init_q15.c
+*
+* Description: RFFT & RIFFT Q15 initialisation function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+
+
+/**
+* \par
+* Generation floating point real_CoefA array:
+* \par
+* n = 4096
+* <pre>for (i = 0; i < n; i++)
+* {
+* pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+* pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* } </pre>
+* \par
+* Convert to fixed point Q15 format
+* round(pATable[i] * pow(2, 15))
+*/
+
+
+static const q15_t ALIGN4 realCoefAQ15[8192] = {
+ 0x4000, 0xc000, 0x3ff3, 0xc000, 0x3fe7, 0xc000, 0x3fda, 0xc000,
+ 0x3fce, 0xc000, 0x3fc1, 0xc000, 0x3fb5, 0xc000, 0x3fa8, 0xc000,
+ 0x3f9b, 0xc000, 0x3f8f, 0xc000, 0x3f82, 0xc000, 0x3f76, 0xc001,
+ 0x3f69, 0xc001, 0x3f5d, 0xc001, 0x3f50, 0xc001, 0x3f44, 0xc001,
+ 0x3f37, 0xc001, 0x3f2a, 0xc001, 0x3f1e, 0xc002, 0x3f11, 0xc002,
+ 0x3f05, 0xc002, 0x3ef8, 0xc002, 0x3eec, 0xc002, 0x3edf, 0xc003,
+ 0x3ed2, 0xc003, 0x3ec6, 0xc003, 0x3eb9, 0xc003, 0x3ead, 0xc004,
+ 0x3ea0, 0xc004, 0x3e94, 0xc004, 0x3e87, 0xc004, 0x3e7a, 0xc005,
+ 0x3e6e, 0xc005, 0x3e61, 0xc005, 0x3e55, 0xc006, 0x3e48, 0xc006,
+ 0x3e3c, 0xc006, 0x3e2f, 0xc007, 0x3e23, 0xc007, 0x3e16, 0xc007,
+ 0x3e09, 0xc008, 0x3dfd, 0xc008, 0x3df0, 0xc009, 0x3de4, 0xc009,
+ 0x3dd7, 0xc009, 0x3dcb, 0xc00a, 0x3dbe, 0xc00a, 0x3db2, 0xc00b,
+ 0x3da5, 0xc00b, 0x3d98, 0xc00c, 0x3d8c, 0xc00c, 0x3d7f, 0xc00d,
+ 0x3d73, 0xc00d, 0x3d66, 0xc00e, 0x3d5a, 0xc00e, 0x3d4d, 0xc00f,
+ 0x3d40, 0xc00f, 0x3d34, 0xc010, 0x3d27, 0xc010, 0x3d1b, 0xc011,
+ 0x3d0e, 0xc011, 0x3d02, 0xc012, 0x3cf5, 0xc013, 0x3ce9, 0xc013,
+ 0x3cdc, 0xc014, 0x3cd0, 0xc014, 0x3cc3, 0xc015, 0x3cb6, 0xc016,
+ 0x3caa, 0xc016, 0x3c9d, 0xc017, 0x3c91, 0xc018, 0x3c84, 0xc018,
+ 0x3c78, 0xc019, 0x3c6b, 0xc01a, 0x3c5f, 0xc01a, 0x3c52, 0xc01b,
+ 0x3c45, 0xc01c, 0x3c39, 0xc01d, 0x3c2c, 0xc01d, 0x3c20, 0xc01e,
+ 0x3c13, 0xc01f, 0x3c07, 0xc020, 0x3bfa, 0xc020, 0x3bee, 0xc021,
+ 0x3be1, 0xc022, 0x3bd5, 0xc023, 0x3bc8, 0xc024, 0x3bbc, 0xc024,
+ 0x3baf, 0xc025, 0x3ba2, 0xc026, 0x3b96, 0xc027, 0x3b89, 0xc028,
+ 0x3b7d, 0xc029, 0x3b70, 0xc02a, 0x3b64, 0xc02b, 0x3b57, 0xc02b,
+ 0x3b4b, 0xc02c, 0x3b3e, 0xc02d, 0x3b32, 0xc02e, 0x3b25, 0xc02f,
+ 0x3b19, 0xc030, 0x3b0c, 0xc031, 0x3b00, 0xc032, 0x3af3, 0xc033,
+ 0x3ae6, 0xc034, 0x3ada, 0xc035, 0x3acd, 0xc036, 0x3ac1, 0xc037,
+ 0x3ab4, 0xc038, 0x3aa8, 0xc039, 0x3a9b, 0xc03a, 0x3a8f, 0xc03b,
+ 0x3a82, 0xc03c, 0x3a76, 0xc03d, 0x3a69, 0xc03f, 0x3a5d, 0xc040,
+ 0x3a50, 0xc041, 0x3a44, 0xc042, 0x3a37, 0xc043, 0x3a2b, 0xc044,
+ 0x3a1e, 0xc045, 0x3a12, 0xc047, 0x3a05, 0xc048, 0x39f9, 0xc049,
+ 0x39ec, 0xc04a, 0x39e0, 0xc04b, 0x39d3, 0xc04c, 0x39c7, 0xc04e,
+ 0x39ba, 0xc04f, 0x39ae, 0xc050, 0x39a1, 0xc051, 0x3995, 0xc053,
+ 0x3988, 0xc054, 0x397c, 0xc055, 0x396f, 0xc056, 0x3963, 0xc058,
+ 0x3956, 0xc059, 0x394a, 0xc05a, 0x393d, 0xc05c, 0x3931, 0xc05d,
+ 0x3924, 0xc05e, 0x3918, 0xc060, 0x390b, 0xc061, 0x38ff, 0xc062,
+ 0x38f2, 0xc064, 0x38e6, 0xc065, 0x38d9, 0xc067, 0x38cd, 0xc068,
+ 0x38c0, 0xc069, 0x38b4, 0xc06b, 0x38a7, 0xc06c, 0x389b, 0xc06e,
+ 0x388e, 0xc06f, 0x3882, 0xc071, 0x3875, 0xc072, 0x3869, 0xc074,
+ 0x385c, 0xc075, 0x3850, 0xc077, 0x3843, 0xc078, 0x3837, 0xc07a,
+ 0x382a, 0xc07b, 0x381e, 0xc07d, 0x3811, 0xc07e, 0x3805, 0xc080,
+ 0x37f9, 0xc081, 0x37ec, 0xc083, 0x37e0, 0xc085, 0x37d3, 0xc086,
+ 0x37c7, 0xc088, 0x37ba, 0xc089, 0x37ae, 0xc08b, 0x37a1, 0xc08d,
+ 0x3795, 0xc08e, 0x3788, 0xc090, 0x377c, 0xc092, 0x376f, 0xc093,
+ 0x3763, 0xc095, 0x3757, 0xc097, 0x374a, 0xc098, 0x373e, 0xc09a,
+ 0x3731, 0xc09c, 0x3725, 0xc09e, 0x3718, 0xc09f, 0x370c, 0xc0a1,
+ 0x36ff, 0xc0a3, 0x36f3, 0xc0a5, 0x36e7, 0xc0a6, 0x36da, 0xc0a8,
+ 0x36ce, 0xc0aa, 0x36c1, 0xc0ac, 0x36b5, 0xc0ae, 0x36a8, 0xc0af,
+ 0x369c, 0xc0b1, 0x3690, 0xc0b3, 0x3683, 0xc0b5, 0x3677, 0xc0b7,
+ 0x366a, 0xc0b9, 0x365e, 0xc0bb, 0x3651, 0xc0bd, 0x3645, 0xc0be,
+ 0x3639, 0xc0c0, 0x362c, 0xc0c2, 0x3620, 0xc0c4, 0x3613, 0xc0c6,
+ 0x3607, 0xc0c8, 0x35fa, 0xc0ca, 0x35ee, 0xc0cc, 0x35e2, 0xc0ce,
+ 0x35d5, 0xc0d0, 0x35c9, 0xc0d2, 0x35bc, 0xc0d4, 0x35b0, 0xc0d6,
+ 0x35a4, 0xc0d8, 0x3597, 0xc0da, 0x358b, 0xc0dc, 0x357e, 0xc0de,
+ 0x3572, 0xc0e0, 0x3566, 0xc0e2, 0x3559, 0xc0e4, 0x354d, 0xc0e7,
+ 0x3540, 0xc0e9, 0x3534, 0xc0eb, 0x3528, 0xc0ed, 0x351b, 0xc0ef,
+ 0x350f, 0xc0f1, 0x3503, 0xc0f3, 0x34f6, 0xc0f6, 0x34ea, 0xc0f8,
+ 0x34dd, 0xc0fa, 0x34d1, 0xc0fc, 0x34c5, 0xc0fe, 0x34b8, 0xc100,
+ 0x34ac, 0xc103, 0x34a0, 0xc105, 0x3493, 0xc107, 0x3487, 0xc109,
+ 0x347b, 0xc10c, 0x346e, 0xc10e, 0x3462, 0xc110, 0x3455, 0xc113,
+ 0x3449, 0xc115, 0x343d, 0xc117, 0x3430, 0xc119, 0x3424, 0xc11c,
+ 0x3418, 0xc11e, 0x340b, 0xc120, 0x33ff, 0xc123, 0x33f3, 0xc125,
+ 0x33e6, 0xc128, 0x33da, 0xc12a, 0x33ce, 0xc12c, 0x33c1, 0xc12f,
+ 0x33b5, 0xc131, 0x33a9, 0xc134, 0x339c, 0xc136, 0x3390, 0xc138,
+ 0x3384, 0xc13b, 0x3377, 0xc13d, 0x336b, 0xc140, 0x335f, 0xc142,
+ 0x3352, 0xc145, 0x3346, 0xc147, 0x333a, 0xc14a, 0x332d, 0xc14c,
+ 0x3321, 0xc14f, 0x3315, 0xc151, 0x3308, 0xc154, 0x32fc, 0xc156,
+ 0x32f0, 0xc159, 0x32e4, 0xc15b, 0x32d7, 0xc15e, 0x32cb, 0xc161,
+ 0x32bf, 0xc163, 0x32b2, 0xc166, 0x32a6, 0xc168, 0x329a, 0xc16b,
+ 0x328e, 0xc16e, 0x3281, 0xc170, 0x3275, 0xc173, 0x3269, 0xc176,
+ 0x325c, 0xc178, 0x3250, 0xc17b, 0x3244, 0xc17e, 0x3238, 0xc180,
+ 0x322b, 0xc183, 0x321f, 0xc186, 0x3213, 0xc189, 0x3207, 0xc18b,
+ 0x31fa, 0xc18e, 0x31ee, 0xc191, 0x31e2, 0xc194, 0x31d5, 0xc196,
+ 0x31c9, 0xc199, 0x31bd, 0xc19c, 0x31b1, 0xc19f, 0x31a4, 0xc1a2,
+ 0x3198, 0xc1a4, 0x318c, 0xc1a7, 0x3180, 0xc1aa, 0x3174, 0xc1ad,
+ 0x3167, 0xc1b0, 0x315b, 0xc1b3, 0x314f, 0xc1b6, 0x3143, 0xc1b8,
+ 0x3136, 0xc1bb, 0x312a, 0xc1be, 0x311e, 0xc1c1, 0x3112, 0xc1c4,
+ 0x3105, 0xc1c7, 0x30f9, 0xc1ca, 0x30ed, 0xc1cd, 0x30e1, 0xc1d0,
+ 0x30d5, 0xc1d3, 0x30c8, 0xc1d6, 0x30bc, 0xc1d9, 0x30b0, 0xc1dc,
+ 0x30a4, 0xc1df, 0x3098, 0xc1e2, 0x308b, 0xc1e5, 0x307f, 0xc1e8,
+ 0x3073, 0xc1eb, 0x3067, 0xc1ee, 0x305b, 0xc1f1, 0x304e, 0xc1f4,
+ 0x3042, 0xc1f7, 0x3036, 0xc1fa, 0x302a, 0xc1fd, 0x301e, 0xc201,
+ 0x3012, 0xc204, 0x3005, 0xc207, 0x2ff9, 0xc20a, 0x2fed, 0xc20d,
+ 0x2fe1, 0xc210, 0x2fd5, 0xc213, 0x2fc9, 0xc217, 0x2fbc, 0xc21a,
+ 0x2fb0, 0xc21d, 0x2fa4, 0xc220, 0x2f98, 0xc223, 0x2f8c, 0xc227,
+ 0x2f80, 0xc22a, 0x2f74, 0xc22d, 0x2f67, 0xc230, 0x2f5b, 0xc234,
+ 0x2f4f, 0xc237, 0x2f43, 0xc23a, 0x2f37, 0xc23e, 0x2f2b, 0xc241,
+ 0x2f1f, 0xc244, 0x2f13, 0xc247, 0x2f06, 0xc24b, 0x2efa, 0xc24e,
+ 0x2eee, 0xc251, 0x2ee2, 0xc255, 0x2ed6, 0xc258, 0x2eca, 0xc25c,
+ 0x2ebe, 0xc25f, 0x2eb2, 0xc262, 0x2ea6, 0xc266, 0x2e99, 0xc269,
+ 0x2e8d, 0xc26d, 0x2e81, 0xc270, 0x2e75, 0xc273, 0x2e69, 0xc277,
+ 0x2e5d, 0xc27a, 0x2e51, 0xc27e, 0x2e45, 0xc281, 0x2e39, 0xc285,
+ 0x2e2d, 0xc288, 0x2e21, 0xc28c, 0x2e15, 0xc28f, 0x2e09, 0xc293,
+ 0x2dfc, 0xc296, 0x2df0, 0xc29a, 0x2de4, 0xc29d, 0x2dd8, 0xc2a1,
+ 0x2dcc, 0xc2a5, 0x2dc0, 0xc2a8, 0x2db4, 0xc2ac, 0x2da8, 0xc2af,
+ 0x2d9c, 0xc2b3, 0x2d90, 0xc2b7, 0x2d84, 0xc2ba, 0x2d78, 0xc2be,
+ 0x2d6c, 0xc2c1, 0x2d60, 0xc2c5, 0x2d54, 0xc2c9, 0x2d48, 0xc2cc,
+ 0x2d3c, 0xc2d0, 0x2d30, 0xc2d4, 0x2d24, 0xc2d8, 0x2d18, 0xc2db,
+ 0x2d0c, 0xc2df, 0x2d00, 0xc2e3, 0x2cf4, 0xc2e6, 0x2ce8, 0xc2ea,
+ 0x2cdc, 0xc2ee, 0x2cd0, 0xc2f2, 0x2cc4, 0xc2f5, 0x2cb8, 0xc2f9,
+ 0x2cac, 0xc2fd, 0x2ca0, 0xc301, 0x2c94, 0xc305, 0x2c88, 0xc308,
+ 0x2c7c, 0xc30c, 0x2c70, 0xc310, 0x2c64, 0xc314, 0x2c58, 0xc318,
+ 0x2c4c, 0xc31c, 0x2c40, 0xc320, 0x2c34, 0xc323, 0x2c28, 0xc327,
+ 0x2c1c, 0xc32b, 0x2c10, 0xc32f, 0x2c05, 0xc333, 0x2bf9, 0xc337,
+ 0x2bed, 0xc33b, 0x2be1, 0xc33f, 0x2bd5, 0xc343, 0x2bc9, 0xc347,
+ 0x2bbd, 0xc34b, 0x2bb1, 0xc34f, 0x2ba5, 0xc353, 0x2b99, 0xc357,
+ 0x2b8d, 0xc35b, 0x2b81, 0xc35f, 0x2b75, 0xc363, 0x2b6a, 0xc367,
+ 0x2b5e, 0xc36b, 0x2b52, 0xc36f, 0x2b46, 0xc373, 0x2b3a, 0xc377,
+ 0x2b2e, 0xc37b, 0x2b22, 0xc37f, 0x2b16, 0xc383, 0x2b0a, 0xc387,
+ 0x2aff, 0xc38c, 0x2af3, 0xc390, 0x2ae7, 0xc394, 0x2adb, 0xc398,
+ 0x2acf, 0xc39c, 0x2ac3, 0xc3a0, 0x2ab7, 0xc3a5, 0x2aac, 0xc3a9,
+ 0x2aa0, 0xc3ad, 0x2a94, 0xc3b1, 0x2a88, 0xc3b5, 0x2a7c, 0xc3ba,
+ 0x2a70, 0xc3be, 0x2a65, 0xc3c2, 0x2a59, 0xc3c6, 0x2a4d, 0xc3ca,
+ 0x2a41, 0xc3cf, 0x2a35, 0xc3d3, 0x2a29, 0xc3d7, 0x2a1e, 0xc3dc,
+ 0x2a12, 0xc3e0, 0x2a06, 0xc3e4, 0x29fa, 0xc3e9, 0x29ee, 0xc3ed,
+ 0x29e3, 0xc3f1, 0x29d7, 0xc3f6, 0x29cb, 0xc3fa, 0x29bf, 0xc3fe,
+ 0x29b4, 0xc403, 0x29a8, 0xc407, 0x299c, 0xc40b, 0x2990, 0xc410,
+ 0x2984, 0xc414, 0x2979, 0xc419, 0x296d, 0xc41d, 0x2961, 0xc422,
+ 0x2955, 0xc426, 0x294a, 0xc42a, 0x293e, 0xc42f, 0x2932, 0xc433,
+ 0x2926, 0xc438, 0x291b, 0xc43c, 0x290f, 0xc441, 0x2903, 0xc445,
+ 0x28f7, 0xc44a, 0x28ec, 0xc44e, 0x28e0, 0xc453, 0x28d4, 0xc457,
+ 0x28c9, 0xc45c, 0x28bd, 0xc461, 0x28b1, 0xc465, 0x28a5, 0xc46a,
+ 0x289a, 0xc46e, 0x288e, 0xc473, 0x2882, 0xc478, 0x2877, 0xc47c,
+ 0x286b, 0xc481, 0x285f, 0xc485, 0x2854, 0xc48a, 0x2848, 0xc48f,
+ 0x283c, 0xc493, 0x2831, 0xc498, 0x2825, 0xc49d, 0x2819, 0xc4a1,
+ 0x280e, 0xc4a6, 0x2802, 0xc4ab, 0x27f6, 0xc4b0, 0x27eb, 0xc4b4,
+ 0x27df, 0xc4b9, 0x27d3, 0xc4be, 0x27c8, 0xc4c2, 0x27bc, 0xc4c7,
+ 0x27b1, 0xc4cc, 0x27a5, 0xc4d1, 0x2799, 0xc4d6, 0x278e, 0xc4da,
+ 0x2782, 0xc4df, 0x2777, 0xc4e4, 0x276b, 0xc4e9, 0x275f, 0xc4ee,
+ 0x2754, 0xc4f2, 0x2748, 0xc4f7, 0x273d, 0xc4fc, 0x2731, 0xc501,
+ 0x2725, 0xc506, 0x271a, 0xc50b, 0x270e, 0xc510, 0x2703, 0xc515,
+ 0x26f7, 0xc51a, 0x26ec, 0xc51e, 0x26e0, 0xc523, 0x26d4, 0xc528,
+ 0x26c9, 0xc52d, 0x26bd, 0xc532, 0x26b2, 0xc537, 0x26a6, 0xc53c,
+ 0x269b, 0xc541, 0x268f, 0xc546, 0x2684, 0xc54b, 0x2678, 0xc550,
+ 0x266d, 0xc555, 0x2661, 0xc55a, 0x2656, 0xc55f, 0x264a, 0xc564,
+ 0x263f, 0xc569, 0x2633, 0xc56e, 0x2628, 0xc573, 0x261c, 0xc578,
+ 0x2611, 0xc57e, 0x2605, 0xc583, 0x25fa, 0xc588, 0x25ee, 0xc58d,
+ 0x25e3, 0xc592, 0x25d7, 0xc597, 0x25cc, 0xc59c, 0x25c0, 0xc5a1,
+ 0x25b5, 0xc5a7, 0x25a9, 0xc5ac, 0x259e, 0xc5b1, 0x2592, 0xc5b6,
+ 0x2587, 0xc5bb, 0x257c, 0xc5c1, 0x2570, 0xc5c6, 0x2565, 0xc5cb,
+ 0x2559, 0xc5d0, 0x254e, 0xc5d5, 0x2542, 0xc5db, 0x2537, 0xc5e0,
+ 0x252c, 0xc5e5, 0x2520, 0xc5ea, 0x2515, 0xc5f0, 0x2509, 0xc5f5,
+ 0x24fe, 0xc5fa, 0x24f3, 0xc600, 0x24e7, 0xc605, 0x24dc, 0xc60a,
+ 0x24d0, 0xc610, 0x24c5, 0xc615, 0x24ba, 0xc61a, 0x24ae, 0xc620,
+ 0x24a3, 0xc625, 0x2498, 0xc62a, 0x248c, 0xc630, 0x2481, 0xc635,
+ 0x2476, 0xc63b, 0x246a, 0xc640, 0x245f, 0xc645, 0x2454, 0xc64b,
+ 0x2448, 0xc650, 0x243d, 0xc656, 0x2432, 0xc65b, 0x2426, 0xc661,
+ 0x241b, 0xc666, 0x2410, 0xc66c, 0x2404, 0xc671, 0x23f9, 0xc677,
+ 0x23ee, 0xc67c, 0x23e2, 0xc682, 0x23d7, 0xc687, 0x23cc, 0xc68d,
+ 0x23c1, 0xc692, 0x23b5, 0xc698, 0x23aa, 0xc69d, 0x239f, 0xc6a3,
+ 0x2394, 0xc6a8, 0x2388, 0xc6ae, 0x237d, 0xc6b4, 0x2372, 0xc6b9,
+ 0x2367, 0xc6bf, 0x235b, 0xc6c5, 0x2350, 0xc6ca, 0x2345, 0xc6d0,
+ 0x233a, 0xc6d5, 0x232e, 0xc6db, 0x2323, 0xc6e1, 0x2318, 0xc6e6,
+ 0x230d, 0xc6ec, 0x2301, 0xc6f2, 0x22f6, 0xc6f7, 0x22eb, 0xc6fd,
+ 0x22e0, 0xc703, 0x22d5, 0xc709, 0x22ca, 0xc70e, 0x22be, 0xc714,
+ 0x22b3, 0xc71a, 0x22a8, 0xc720, 0x229d, 0xc725, 0x2292, 0xc72b,
+ 0x2287, 0xc731, 0x227b, 0xc737, 0x2270, 0xc73d, 0x2265, 0xc742,
+ 0x225a, 0xc748, 0x224f, 0xc74e, 0x2244, 0xc754, 0x2239, 0xc75a,
+ 0x222d, 0xc75f, 0x2222, 0xc765, 0x2217, 0xc76b, 0x220c, 0xc771,
+ 0x2201, 0xc777, 0x21f6, 0xc77d, 0x21eb, 0xc783, 0x21e0, 0xc789,
+ 0x21d5, 0xc78f, 0x21ca, 0xc795, 0x21be, 0xc79a, 0x21b3, 0xc7a0,
+ 0x21a8, 0xc7a6, 0x219d, 0xc7ac, 0x2192, 0xc7b2, 0x2187, 0xc7b8,
+ 0x217c, 0xc7be, 0x2171, 0xc7c4, 0x2166, 0xc7ca, 0x215b, 0xc7d0,
+ 0x2150, 0xc7d6, 0x2145, 0xc7dc, 0x213a, 0xc7e2, 0x212f, 0xc7e8,
+ 0x2124, 0xc7ee, 0x2119, 0xc7f5, 0x210e, 0xc7fb, 0x2103, 0xc801,
+ 0x20f8, 0xc807, 0x20ed, 0xc80d, 0x20e2, 0xc813, 0x20d7, 0xc819,
+ 0x20cc, 0xc81f, 0x20c1, 0xc825, 0x20b6, 0xc82b, 0x20ab, 0xc832,
+ 0x20a0, 0xc838, 0x2095, 0xc83e, 0x208a, 0xc844, 0x207f, 0xc84a,
+ 0x2074, 0xc850, 0x2069, 0xc857, 0x205e, 0xc85d, 0x2054, 0xc863,
+ 0x2049, 0xc869, 0x203e, 0xc870, 0x2033, 0xc876, 0x2028, 0xc87c,
+ 0x201d, 0xc882, 0x2012, 0xc889, 0x2007, 0xc88f, 0x1ffc, 0xc895,
+ 0x1ff1, 0xc89b, 0x1fe7, 0xc8a2, 0x1fdc, 0xc8a8, 0x1fd1, 0xc8ae,
+ 0x1fc6, 0xc8b5, 0x1fbb, 0xc8bb, 0x1fb0, 0xc8c1, 0x1fa5, 0xc8c8,
+ 0x1f9b, 0xc8ce, 0x1f90, 0xc8d4, 0x1f85, 0xc8db, 0x1f7a, 0xc8e1,
+ 0x1f6f, 0xc8e8, 0x1f65, 0xc8ee, 0x1f5a, 0xc8f4, 0x1f4f, 0xc8fb,
+ 0x1f44, 0xc901, 0x1f39, 0xc908, 0x1f2f, 0xc90e, 0x1f24, 0xc915,
+ 0x1f19, 0xc91b, 0x1f0e, 0xc921, 0x1f03, 0xc928, 0x1ef9, 0xc92e,
+ 0x1eee, 0xc935, 0x1ee3, 0xc93b, 0x1ed8, 0xc942, 0x1ece, 0xc948,
+ 0x1ec3, 0xc94f, 0x1eb8, 0xc955, 0x1ead, 0xc95c, 0x1ea3, 0xc963,
+ 0x1e98, 0xc969, 0x1e8d, 0xc970, 0x1e83, 0xc976, 0x1e78, 0xc97d,
+ 0x1e6d, 0xc983, 0x1e62, 0xc98a, 0x1e58, 0xc991, 0x1e4d, 0xc997,
+ 0x1e42, 0xc99e, 0x1e38, 0xc9a4, 0x1e2d, 0xc9ab, 0x1e22, 0xc9b2,
+ 0x1e18, 0xc9b8, 0x1e0d, 0xc9bf, 0x1e02, 0xc9c6, 0x1df8, 0xc9cc,
+ 0x1ded, 0xc9d3, 0x1de2, 0xc9da, 0x1dd8, 0xc9e0, 0x1dcd, 0xc9e7,
+ 0x1dc3, 0xc9ee, 0x1db8, 0xc9f5, 0x1dad, 0xc9fb, 0x1da3, 0xca02,
+ 0x1d98, 0xca09, 0x1d8e, 0xca10, 0x1d83, 0xca16, 0x1d78, 0xca1d,
+ 0x1d6e, 0xca24, 0x1d63, 0xca2b, 0x1d59, 0xca32, 0x1d4e, 0xca38,
+ 0x1d44, 0xca3f, 0x1d39, 0xca46, 0x1d2e, 0xca4d, 0x1d24, 0xca54,
+ 0x1d19, 0xca5b, 0x1d0f, 0xca61, 0x1d04, 0xca68, 0x1cfa, 0xca6f,
+ 0x1cef, 0xca76, 0x1ce5, 0xca7d, 0x1cda, 0xca84, 0x1cd0, 0xca8b,
+ 0x1cc5, 0xca92, 0x1cbb, 0xca99, 0x1cb0, 0xca9f, 0x1ca6, 0xcaa6,
+ 0x1c9b, 0xcaad, 0x1c91, 0xcab4, 0x1c86, 0xcabb, 0x1c7c, 0xcac2,
+ 0x1c72, 0xcac9, 0x1c67, 0xcad0, 0x1c5d, 0xcad7, 0x1c52, 0xcade,
+ 0x1c48, 0xcae5, 0x1c3d, 0xcaec, 0x1c33, 0xcaf3, 0x1c29, 0xcafa,
+ 0x1c1e, 0xcb01, 0x1c14, 0xcb08, 0x1c09, 0xcb0f, 0x1bff, 0xcb16,
+ 0x1bf5, 0xcb1e, 0x1bea, 0xcb25, 0x1be0, 0xcb2c, 0x1bd5, 0xcb33,
+ 0x1bcb, 0xcb3a, 0x1bc1, 0xcb41, 0x1bb6, 0xcb48, 0x1bac, 0xcb4f,
+ 0x1ba2, 0xcb56, 0x1b97, 0xcb5e, 0x1b8d, 0xcb65, 0x1b83, 0xcb6c,
+ 0x1b78, 0xcb73, 0x1b6e, 0xcb7a, 0x1b64, 0xcb81, 0x1b59, 0xcb89,
+ 0x1b4f, 0xcb90, 0x1b45, 0xcb97, 0x1b3b, 0xcb9e, 0x1b30, 0xcba5,
+ 0x1b26, 0xcbad, 0x1b1c, 0xcbb4, 0x1b11, 0xcbbb, 0x1b07, 0xcbc2,
+ 0x1afd, 0xcbca, 0x1af3, 0xcbd1, 0x1ae8, 0xcbd8, 0x1ade, 0xcbe0,
+ 0x1ad4, 0xcbe7, 0x1aca, 0xcbee, 0x1abf, 0xcbf5, 0x1ab5, 0xcbfd,
+ 0x1aab, 0xcc04, 0x1aa1, 0xcc0b, 0x1a97, 0xcc13, 0x1a8c, 0xcc1a,
+ 0x1a82, 0xcc21, 0x1a78, 0xcc29, 0x1a6e, 0xcc30, 0x1a64, 0xcc38,
+ 0x1a5a, 0xcc3f, 0x1a4f, 0xcc46, 0x1a45, 0xcc4e, 0x1a3b, 0xcc55,
+ 0x1a31, 0xcc5d, 0x1a27, 0xcc64, 0x1a1d, 0xcc6b, 0x1a13, 0xcc73,
+ 0x1a08, 0xcc7a, 0x19fe, 0xcc82, 0x19f4, 0xcc89, 0x19ea, 0xcc91,
+ 0x19e0, 0xcc98, 0x19d6, 0xcca0, 0x19cc, 0xcca7, 0x19c2, 0xccaf,
+ 0x19b8, 0xccb6, 0x19ae, 0xccbe, 0x19a4, 0xccc5, 0x199a, 0xcccd,
+ 0x198f, 0xccd4, 0x1985, 0xccdc, 0x197b, 0xcce3, 0x1971, 0xcceb,
+ 0x1967, 0xccf3, 0x195d, 0xccfa, 0x1953, 0xcd02, 0x1949, 0xcd09,
+ 0x193f, 0xcd11, 0x1935, 0xcd19, 0x192b, 0xcd20, 0x1921, 0xcd28,
+ 0x1917, 0xcd30, 0x190d, 0xcd37, 0x1903, 0xcd3f, 0x18f9, 0xcd46,
+ 0x18ef, 0xcd4e, 0x18e6, 0xcd56, 0x18dc, 0xcd5d, 0x18d2, 0xcd65,
+ 0x18c8, 0xcd6d, 0x18be, 0xcd75, 0x18b4, 0xcd7c, 0x18aa, 0xcd84,
+ 0x18a0, 0xcd8c, 0x1896, 0xcd93, 0x188c, 0xcd9b, 0x1882, 0xcda3,
+ 0x1878, 0xcdab, 0x186f, 0xcdb2, 0x1865, 0xcdba, 0x185b, 0xcdc2,
+ 0x1851, 0xcdca, 0x1847, 0xcdd2, 0x183d, 0xcdd9, 0x1833, 0xcde1,
+ 0x182a, 0xcde9, 0x1820, 0xcdf1, 0x1816, 0xcdf9, 0x180c, 0xce01,
+ 0x1802, 0xce08, 0x17f8, 0xce10, 0x17ef, 0xce18, 0x17e5, 0xce20,
+ 0x17db, 0xce28, 0x17d1, 0xce30, 0x17c8, 0xce38, 0x17be, 0xce40,
+ 0x17b4, 0xce47, 0x17aa, 0xce4f, 0x17a0, 0xce57, 0x1797, 0xce5f,
+ 0x178d, 0xce67, 0x1783, 0xce6f, 0x177a, 0xce77, 0x1770, 0xce7f,
+ 0x1766, 0xce87, 0x175c, 0xce8f, 0x1753, 0xce97, 0x1749, 0xce9f,
+ 0x173f, 0xcea7, 0x1736, 0xceaf, 0x172c, 0xceb7, 0x1722, 0xcebf,
+ 0x1719, 0xcec7, 0x170f, 0xcecf, 0x1705, 0xced7, 0x16fc, 0xcedf,
+ 0x16f2, 0xcee7, 0x16e8, 0xceef, 0x16df, 0xcef7, 0x16d5, 0xceff,
+ 0x16cb, 0xcf07, 0x16c2, 0xcf10, 0x16b8, 0xcf18, 0x16af, 0xcf20,
+ 0x16a5, 0xcf28, 0x169b, 0xcf30, 0x1692, 0xcf38, 0x1688, 0xcf40,
+ 0x167f, 0xcf48, 0x1675, 0xcf51, 0x166c, 0xcf59, 0x1662, 0xcf61,
+ 0x1659, 0xcf69, 0x164f, 0xcf71, 0x1645, 0xcf79, 0x163c, 0xcf82,
+ 0x1632, 0xcf8a, 0x1629, 0xcf92, 0x161f, 0xcf9a, 0x1616, 0xcfa3,
+ 0x160c, 0xcfab, 0x1603, 0xcfb3, 0x15f9, 0xcfbb, 0x15f0, 0xcfc4,
+ 0x15e6, 0xcfcc, 0x15dd, 0xcfd4, 0x15d4, 0xcfdc, 0x15ca, 0xcfe5,
+ 0x15c1, 0xcfed, 0x15b7, 0xcff5, 0x15ae, 0xcffe, 0x15a4, 0xd006,
+ 0x159b, 0xd00e, 0x1592, 0xd016, 0x1588, 0xd01f, 0x157f, 0xd027,
+ 0x1575, 0xd030, 0x156c, 0xd038, 0x1563, 0xd040, 0x1559, 0xd049,
+ 0x1550, 0xd051, 0x1547, 0xd059, 0x153d, 0xd062, 0x1534, 0xd06a,
+ 0x152a, 0xd073, 0x1521, 0xd07b, 0x1518, 0xd083, 0x150e, 0xd08c,
+ 0x1505, 0xd094, 0x14fc, 0xd09d, 0x14f3, 0xd0a5, 0x14e9, 0xd0ae,
+ 0x14e0, 0xd0b6, 0x14d7, 0xd0bf, 0x14cd, 0xd0c7, 0x14c4, 0xd0d0,
+ 0x14bb, 0xd0d8, 0x14b2, 0xd0e0, 0x14a8, 0xd0e9, 0x149f, 0xd0f2,
+ 0x1496, 0xd0fa, 0x148d, 0xd103, 0x1483, 0xd10b, 0x147a, 0xd114,
+ 0x1471, 0xd11c, 0x1468, 0xd125, 0x145f, 0xd12d, 0x1455, 0xd136,
+ 0x144c, 0xd13e, 0x1443, 0xd147, 0x143a, 0xd150, 0x1431, 0xd158,
+ 0x1428, 0xd161, 0x141e, 0xd169, 0x1415, 0xd172, 0x140c, 0xd17b,
+ 0x1403, 0xd183, 0x13fa, 0xd18c, 0x13f1, 0xd195, 0x13e8, 0xd19d,
+ 0x13df, 0xd1a6, 0x13d5, 0xd1af, 0x13cc, 0xd1b7, 0x13c3, 0xd1c0,
+ 0x13ba, 0xd1c9, 0x13b1, 0xd1d1, 0x13a8, 0xd1da, 0x139f, 0xd1e3,
+ 0x1396, 0xd1eb, 0x138d, 0xd1f4, 0x1384, 0xd1fd, 0x137b, 0xd206,
+ 0x1372, 0xd20e, 0x1369, 0xd217, 0x1360, 0xd220, 0x1357, 0xd229,
+ 0x134e, 0xd231, 0x1345, 0xd23a, 0x133c, 0xd243, 0x1333, 0xd24c,
+ 0x132a, 0xd255, 0x1321, 0xd25d, 0x1318, 0xd266, 0x130f, 0xd26f,
+ 0x1306, 0xd278, 0x12fd, 0xd281, 0x12f4, 0xd28a, 0x12eb, 0xd292,
+ 0x12e2, 0xd29b, 0x12d9, 0xd2a4, 0x12d1, 0xd2ad, 0x12c8, 0xd2b6,
+ 0x12bf, 0xd2bf, 0x12b6, 0xd2c8, 0x12ad, 0xd2d1, 0x12a4, 0xd2d9,
+ 0x129b, 0xd2e2, 0x1292, 0xd2eb, 0x128a, 0xd2f4, 0x1281, 0xd2fd,
+ 0x1278, 0xd306, 0x126f, 0xd30f, 0x1266, 0xd318, 0x125d, 0xd321,
+ 0x1255, 0xd32a, 0x124c, 0xd333, 0x1243, 0xd33c, 0x123a, 0xd345,
+ 0x1231, 0xd34e, 0x1229, 0xd357, 0x1220, 0xd360, 0x1217, 0xd369,
+ 0x120e, 0xd372, 0x1206, 0xd37b, 0x11fd, 0xd384, 0x11f4, 0xd38d,
+ 0x11eb, 0xd396, 0x11e3, 0xd39f, 0x11da, 0xd3a8, 0x11d1, 0xd3b1,
+ 0x11c9, 0xd3ba, 0x11c0, 0xd3c3, 0x11b7, 0xd3cc, 0x11af, 0xd3d5,
+ 0x11a6, 0xd3df, 0x119d, 0xd3e8, 0x1195, 0xd3f1, 0x118c, 0xd3fa,
+ 0x1183, 0xd403, 0x117b, 0xd40c, 0x1172, 0xd415, 0x1169, 0xd41e,
+ 0x1161, 0xd428, 0x1158, 0xd431, 0x1150, 0xd43a, 0x1147, 0xd443,
+ 0x113e, 0xd44c, 0x1136, 0xd455, 0x112d, 0xd45f, 0x1125, 0xd468,
+ 0x111c, 0xd471, 0x1114, 0xd47a, 0x110b, 0xd483, 0x1103, 0xd48d,
+ 0x10fa, 0xd496, 0x10f2, 0xd49f, 0x10e9, 0xd4a8, 0x10e0, 0xd4b2,
+ 0x10d8, 0xd4bb, 0x10d0, 0xd4c4, 0x10c7, 0xd4cd, 0x10bf, 0xd4d7,
+ 0x10b6, 0xd4e0, 0x10ae, 0xd4e9, 0x10a5, 0xd4f3, 0x109d, 0xd4fc,
+ 0x1094, 0xd505, 0x108c, 0xd50e, 0x1083, 0xd518, 0x107b, 0xd521,
+ 0x1073, 0xd52a, 0x106a, 0xd534, 0x1062, 0xd53d, 0x1059, 0xd547,
+ 0x1051, 0xd550, 0x1049, 0xd559, 0x1040, 0xd563, 0x1038, 0xd56c,
+ 0x1030, 0xd575, 0x1027, 0xd57f, 0x101f, 0xd588, 0x1016, 0xd592,
+ 0x100e, 0xd59b, 0x1006, 0xd5a4, 0xffe, 0xd5ae, 0xff5, 0xd5b7,
+ 0xfed, 0xd5c1, 0xfe5, 0xd5ca, 0xfdc, 0xd5d4, 0xfd4, 0xd5dd,
+ 0xfcc, 0xd5e6, 0xfc4, 0xd5f0, 0xfbb, 0xd5f9, 0xfb3, 0xd603,
+ 0xfab, 0xd60c, 0xfa3, 0xd616, 0xf9a, 0xd61f, 0xf92, 0xd629,
+ 0xf8a, 0xd632, 0xf82, 0xd63c, 0xf79, 0xd645, 0xf71, 0xd64f,
+ 0xf69, 0xd659, 0xf61, 0xd662, 0xf59, 0xd66c, 0xf51, 0xd675,
+ 0xf48, 0xd67f, 0xf40, 0xd688, 0xf38, 0xd692, 0xf30, 0xd69b,
+ 0xf28, 0xd6a5, 0xf20, 0xd6af, 0xf18, 0xd6b8, 0xf10, 0xd6c2,
+ 0xf07, 0xd6cb, 0xeff, 0xd6d5, 0xef7, 0xd6df, 0xeef, 0xd6e8,
+ 0xee7, 0xd6f2, 0xedf, 0xd6fc, 0xed7, 0xd705, 0xecf, 0xd70f,
+ 0xec7, 0xd719, 0xebf, 0xd722, 0xeb7, 0xd72c, 0xeaf, 0xd736,
+ 0xea7, 0xd73f, 0xe9f, 0xd749, 0xe97, 0xd753, 0xe8f, 0xd75c,
+ 0xe87, 0xd766, 0xe7f, 0xd770, 0xe77, 0xd77a, 0xe6f, 0xd783,
+ 0xe67, 0xd78d, 0xe5f, 0xd797, 0xe57, 0xd7a0, 0xe4f, 0xd7aa,
+ 0xe47, 0xd7b4, 0xe40, 0xd7be, 0xe38, 0xd7c8, 0xe30, 0xd7d1,
+ 0xe28, 0xd7db, 0xe20, 0xd7e5, 0xe18, 0xd7ef, 0xe10, 0xd7f8,
+ 0xe08, 0xd802, 0xe01, 0xd80c, 0xdf9, 0xd816, 0xdf1, 0xd820,
+ 0xde9, 0xd82a, 0xde1, 0xd833, 0xdd9, 0xd83d, 0xdd2, 0xd847,
+ 0xdca, 0xd851, 0xdc2, 0xd85b, 0xdba, 0xd865, 0xdb2, 0xd86f,
+ 0xdab, 0xd878, 0xda3, 0xd882, 0xd9b, 0xd88c, 0xd93, 0xd896,
+ 0xd8c, 0xd8a0, 0xd84, 0xd8aa, 0xd7c, 0xd8b4, 0xd75, 0xd8be,
+ 0xd6d, 0xd8c8, 0xd65, 0xd8d2, 0xd5d, 0xd8dc, 0xd56, 0xd8e6,
+ 0xd4e, 0xd8ef, 0xd46, 0xd8f9, 0xd3f, 0xd903, 0xd37, 0xd90d,
+ 0xd30, 0xd917, 0xd28, 0xd921, 0xd20, 0xd92b, 0xd19, 0xd935,
+ 0xd11, 0xd93f, 0xd09, 0xd949, 0xd02, 0xd953, 0xcfa, 0xd95d,
+ 0xcf3, 0xd967, 0xceb, 0xd971, 0xce3, 0xd97b, 0xcdc, 0xd985,
+ 0xcd4, 0xd98f, 0xccd, 0xd99a, 0xcc5, 0xd9a4, 0xcbe, 0xd9ae,
+ 0xcb6, 0xd9b8, 0xcaf, 0xd9c2, 0xca7, 0xd9cc, 0xca0, 0xd9d6,
+ 0xc98, 0xd9e0, 0xc91, 0xd9ea, 0xc89, 0xd9f4, 0xc82, 0xd9fe,
+ 0xc7a, 0xda08, 0xc73, 0xda13, 0xc6b, 0xda1d, 0xc64, 0xda27,
+ 0xc5d, 0xda31, 0xc55, 0xda3b, 0xc4e, 0xda45, 0xc46, 0xda4f,
+ 0xc3f, 0xda5a, 0xc38, 0xda64, 0xc30, 0xda6e, 0xc29, 0xda78,
+ 0xc21, 0xda82, 0xc1a, 0xda8c, 0xc13, 0xda97, 0xc0b, 0xdaa1,
+ 0xc04, 0xdaab, 0xbfd, 0xdab5, 0xbf5, 0xdabf, 0xbee, 0xdaca,
+ 0xbe7, 0xdad4, 0xbe0, 0xdade, 0xbd8, 0xdae8, 0xbd1, 0xdaf3,
+ 0xbca, 0xdafd, 0xbc2, 0xdb07, 0xbbb, 0xdb11, 0xbb4, 0xdb1c,
+ 0xbad, 0xdb26, 0xba5, 0xdb30, 0xb9e, 0xdb3b, 0xb97, 0xdb45,
+ 0xb90, 0xdb4f, 0xb89, 0xdb59, 0xb81, 0xdb64, 0xb7a, 0xdb6e,
+ 0xb73, 0xdb78, 0xb6c, 0xdb83, 0xb65, 0xdb8d, 0xb5e, 0xdb97,
+ 0xb56, 0xdba2, 0xb4f, 0xdbac, 0xb48, 0xdbb6, 0xb41, 0xdbc1,
+ 0xb3a, 0xdbcb, 0xb33, 0xdbd5, 0xb2c, 0xdbe0, 0xb25, 0xdbea,
+ 0xb1e, 0xdbf5, 0xb16, 0xdbff, 0xb0f, 0xdc09, 0xb08, 0xdc14,
+ 0xb01, 0xdc1e, 0xafa, 0xdc29, 0xaf3, 0xdc33, 0xaec, 0xdc3d,
+ 0xae5, 0xdc48, 0xade, 0xdc52, 0xad7, 0xdc5d, 0xad0, 0xdc67,
+ 0xac9, 0xdc72, 0xac2, 0xdc7c, 0xabb, 0xdc86, 0xab4, 0xdc91,
+ 0xaad, 0xdc9b, 0xaa6, 0xdca6, 0xa9f, 0xdcb0, 0xa99, 0xdcbb,
+ 0xa92, 0xdcc5, 0xa8b, 0xdcd0, 0xa84, 0xdcda, 0xa7d, 0xdce5,
+ 0xa76, 0xdcef, 0xa6f, 0xdcfa, 0xa68, 0xdd04, 0xa61, 0xdd0f,
+ 0xa5b, 0xdd19, 0xa54, 0xdd24, 0xa4d, 0xdd2e, 0xa46, 0xdd39,
+ 0xa3f, 0xdd44, 0xa38, 0xdd4e, 0xa32, 0xdd59, 0xa2b, 0xdd63,
+ 0xa24, 0xdd6e, 0xa1d, 0xdd78, 0xa16, 0xdd83, 0xa10, 0xdd8e,
+ 0xa09, 0xdd98, 0xa02, 0xdda3, 0x9fb, 0xddad, 0x9f5, 0xddb8,
+ 0x9ee, 0xddc3, 0x9e7, 0xddcd, 0x9e0, 0xddd8, 0x9da, 0xdde2,
+ 0x9d3, 0xdded, 0x9cc, 0xddf8, 0x9c6, 0xde02, 0x9bf, 0xde0d,
+ 0x9b8, 0xde18, 0x9b2, 0xde22, 0x9ab, 0xde2d, 0x9a4, 0xde38,
+ 0x99e, 0xde42, 0x997, 0xde4d, 0x991, 0xde58, 0x98a, 0xde62,
+ 0x983, 0xde6d, 0x97d, 0xde78, 0x976, 0xde83, 0x970, 0xde8d,
+ 0x969, 0xde98, 0x963, 0xdea3, 0x95c, 0xdead, 0x955, 0xdeb8,
+ 0x94f, 0xdec3, 0x948, 0xdece, 0x942, 0xded8, 0x93b, 0xdee3,
+ 0x935, 0xdeee, 0x92e, 0xdef9, 0x928, 0xdf03, 0x921, 0xdf0e,
+ 0x91b, 0xdf19, 0x915, 0xdf24, 0x90e, 0xdf2f, 0x908, 0xdf39,
+ 0x901, 0xdf44, 0x8fb, 0xdf4f, 0x8f4, 0xdf5a, 0x8ee, 0xdf65,
+ 0x8e8, 0xdf6f, 0x8e1, 0xdf7a, 0x8db, 0xdf85, 0x8d4, 0xdf90,
+ 0x8ce, 0xdf9b, 0x8c8, 0xdfa5, 0x8c1, 0xdfb0, 0x8bb, 0xdfbb,
+ 0x8b5, 0xdfc6, 0x8ae, 0xdfd1, 0x8a8, 0xdfdc, 0x8a2, 0xdfe7,
+ 0x89b, 0xdff1, 0x895, 0xdffc, 0x88f, 0xe007, 0x889, 0xe012,
+ 0x882, 0xe01d, 0x87c, 0xe028, 0x876, 0xe033, 0x870, 0xe03e,
+ 0x869, 0xe049, 0x863, 0xe054, 0x85d, 0xe05e, 0x857, 0xe069,
+ 0x850, 0xe074, 0x84a, 0xe07f, 0x844, 0xe08a, 0x83e, 0xe095,
+ 0x838, 0xe0a0, 0x832, 0xe0ab, 0x82b, 0xe0b6, 0x825, 0xe0c1,
+ 0x81f, 0xe0cc, 0x819, 0xe0d7, 0x813, 0xe0e2, 0x80d, 0xe0ed,
+ 0x807, 0xe0f8, 0x801, 0xe103, 0x7fb, 0xe10e, 0x7f5, 0xe119,
+ 0x7ee, 0xe124, 0x7e8, 0xe12f, 0x7e2, 0xe13a, 0x7dc, 0xe145,
+ 0x7d6, 0xe150, 0x7d0, 0xe15b, 0x7ca, 0xe166, 0x7c4, 0xe171,
+ 0x7be, 0xe17c, 0x7b8, 0xe187, 0x7b2, 0xe192, 0x7ac, 0xe19d,
+ 0x7a6, 0xe1a8, 0x7a0, 0xe1b3, 0x79a, 0xe1be, 0x795, 0xe1ca,
+ 0x78f, 0xe1d5, 0x789, 0xe1e0, 0x783, 0xe1eb, 0x77d, 0xe1f6,
+ 0x777, 0xe201, 0x771, 0xe20c, 0x76b, 0xe217, 0x765, 0xe222,
+ 0x75f, 0xe22d, 0x75a, 0xe239, 0x754, 0xe244, 0x74e, 0xe24f,
+ 0x748, 0xe25a, 0x742, 0xe265, 0x73d, 0xe270, 0x737, 0xe27b,
+ 0x731, 0xe287, 0x72b, 0xe292, 0x725, 0xe29d, 0x720, 0xe2a8,
+ 0x71a, 0xe2b3, 0x714, 0xe2be, 0x70e, 0xe2ca, 0x709, 0xe2d5,
+ 0x703, 0xe2e0, 0x6fd, 0xe2eb, 0x6f7, 0xe2f6, 0x6f2, 0xe301,
+ 0x6ec, 0xe30d, 0x6e6, 0xe318, 0x6e1, 0xe323, 0x6db, 0xe32e,
+ 0x6d5, 0xe33a, 0x6d0, 0xe345, 0x6ca, 0xe350, 0x6c5, 0xe35b,
+ 0x6bf, 0xe367, 0x6b9, 0xe372, 0x6b4, 0xe37d, 0x6ae, 0xe388,
+ 0x6a8, 0xe394, 0x6a3, 0xe39f, 0x69d, 0xe3aa, 0x698, 0xe3b5,
+ 0x692, 0xe3c1, 0x68d, 0xe3cc, 0x687, 0xe3d7, 0x682, 0xe3e2,
+ 0x67c, 0xe3ee, 0x677, 0xe3f9, 0x671, 0xe404, 0x66c, 0xe410,
+ 0x666, 0xe41b, 0x661, 0xe426, 0x65b, 0xe432, 0x656, 0xe43d,
+ 0x650, 0xe448, 0x64b, 0xe454, 0x645, 0xe45f, 0x640, 0xe46a,
+ 0x63b, 0xe476, 0x635, 0xe481, 0x630, 0xe48c, 0x62a, 0xe498,
+ 0x625, 0xe4a3, 0x620, 0xe4ae, 0x61a, 0xe4ba, 0x615, 0xe4c5,
+ 0x610, 0xe4d0, 0x60a, 0xe4dc, 0x605, 0xe4e7, 0x600, 0xe4f3,
+ 0x5fa, 0xe4fe, 0x5f5, 0xe509, 0x5f0, 0xe515, 0x5ea, 0xe520,
+ 0x5e5, 0xe52c, 0x5e0, 0xe537, 0x5db, 0xe542, 0x5d5, 0xe54e,
+ 0x5d0, 0xe559, 0x5cb, 0xe565, 0x5c6, 0xe570, 0x5c1, 0xe57c,
+ 0x5bb, 0xe587, 0x5b6, 0xe592, 0x5b1, 0xe59e, 0x5ac, 0xe5a9,
+ 0x5a7, 0xe5b5, 0x5a1, 0xe5c0, 0x59c, 0xe5cc, 0x597, 0xe5d7,
+ 0x592, 0xe5e3, 0x58d, 0xe5ee, 0x588, 0xe5fa, 0x583, 0xe605,
+ 0x57e, 0xe611, 0x578, 0xe61c, 0x573, 0xe628, 0x56e, 0xe633,
+ 0x569, 0xe63f, 0x564, 0xe64a, 0x55f, 0xe656, 0x55a, 0xe661,
+ 0x555, 0xe66d, 0x550, 0xe678, 0x54b, 0xe684, 0x546, 0xe68f,
+ 0x541, 0xe69b, 0x53c, 0xe6a6, 0x537, 0xe6b2, 0x532, 0xe6bd,
+ 0x52d, 0xe6c9, 0x528, 0xe6d4, 0x523, 0xe6e0, 0x51e, 0xe6ec,
+ 0x51a, 0xe6f7, 0x515, 0xe703, 0x510, 0xe70e, 0x50b, 0xe71a,
+ 0x506, 0xe725, 0x501, 0xe731, 0x4fc, 0xe73d, 0x4f7, 0xe748,
+ 0x4f2, 0xe754, 0x4ee, 0xe75f, 0x4e9, 0xe76b, 0x4e4, 0xe777,
+ 0x4df, 0xe782, 0x4da, 0xe78e, 0x4d6, 0xe799, 0x4d1, 0xe7a5,
+ 0x4cc, 0xe7b1, 0x4c7, 0xe7bc, 0x4c2, 0xe7c8, 0x4be, 0xe7d3,
+ 0x4b9, 0xe7df, 0x4b4, 0xe7eb, 0x4b0, 0xe7f6, 0x4ab, 0xe802,
+ 0x4a6, 0xe80e, 0x4a1, 0xe819, 0x49d, 0xe825, 0x498, 0xe831,
+ 0x493, 0xe83c, 0x48f, 0xe848, 0x48a, 0xe854, 0x485, 0xe85f,
+ 0x481, 0xe86b, 0x47c, 0xe877, 0x478, 0xe882, 0x473, 0xe88e,
+ 0x46e, 0xe89a, 0x46a, 0xe8a5, 0x465, 0xe8b1, 0x461, 0xe8bd,
+ 0x45c, 0xe8c9, 0x457, 0xe8d4, 0x453, 0xe8e0, 0x44e, 0xe8ec,
+ 0x44a, 0xe8f7, 0x445, 0xe903, 0x441, 0xe90f, 0x43c, 0xe91b,
+ 0x438, 0xe926, 0x433, 0xe932, 0x42f, 0xe93e, 0x42a, 0xe94a,
+ 0x426, 0xe955, 0x422, 0xe961, 0x41d, 0xe96d, 0x419, 0xe979,
+ 0x414, 0xe984, 0x410, 0xe990, 0x40b, 0xe99c, 0x407, 0xe9a8,
+ 0x403, 0xe9b4, 0x3fe, 0xe9bf, 0x3fa, 0xe9cb, 0x3f6, 0xe9d7,
+ 0x3f1, 0xe9e3, 0x3ed, 0xe9ee, 0x3e9, 0xe9fa, 0x3e4, 0xea06,
+ 0x3e0, 0xea12, 0x3dc, 0xea1e, 0x3d7, 0xea29, 0x3d3, 0xea35,
+ 0x3cf, 0xea41, 0x3ca, 0xea4d, 0x3c6, 0xea59, 0x3c2, 0xea65,
+ 0x3be, 0xea70, 0x3ba, 0xea7c, 0x3b5, 0xea88, 0x3b1, 0xea94,
+ 0x3ad, 0xeaa0, 0x3a9, 0xeaac, 0x3a5, 0xeab7, 0x3a0, 0xeac3,
+ 0x39c, 0xeacf, 0x398, 0xeadb, 0x394, 0xeae7, 0x390, 0xeaf3,
+ 0x38c, 0xeaff, 0x387, 0xeb0a, 0x383, 0xeb16, 0x37f, 0xeb22,
+ 0x37b, 0xeb2e, 0x377, 0xeb3a, 0x373, 0xeb46, 0x36f, 0xeb52,
+ 0x36b, 0xeb5e, 0x367, 0xeb6a, 0x363, 0xeb75, 0x35f, 0xeb81,
+ 0x35b, 0xeb8d, 0x357, 0xeb99, 0x353, 0xeba5, 0x34f, 0xebb1,
+ 0x34b, 0xebbd, 0x347, 0xebc9, 0x343, 0xebd5, 0x33f, 0xebe1,
+ 0x33b, 0xebed, 0x337, 0xebf9, 0x333, 0xec05, 0x32f, 0xec10,
+ 0x32b, 0xec1c, 0x327, 0xec28, 0x323, 0xec34, 0x320, 0xec40,
+ 0x31c, 0xec4c, 0x318, 0xec58, 0x314, 0xec64, 0x310, 0xec70,
+ 0x30c, 0xec7c, 0x308, 0xec88, 0x305, 0xec94, 0x301, 0xeca0,
+ 0x2fd, 0xecac, 0x2f9, 0xecb8, 0x2f5, 0xecc4, 0x2f2, 0xecd0,
+ 0x2ee, 0xecdc, 0x2ea, 0xece8, 0x2e6, 0xecf4, 0x2e3, 0xed00,
+ 0x2df, 0xed0c, 0x2db, 0xed18, 0x2d8, 0xed24, 0x2d4, 0xed30,
+ 0x2d0, 0xed3c, 0x2cc, 0xed48, 0x2c9, 0xed54, 0x2c5, 0xed60,
+ 0x2c1, 0xed6c, 0x2be, 0xed78, 0x2ba, 0xed84, 0x2b7, 0xed90,
+ 0x2b3, 0xed9c, 0x2af, 0xeda8, 0x2ac, 0xedb4, 0x2a8, 0xedc0,
+ 0x2a5, 0xedcc, 0x2a1, 0xedd8, 0x29d, 0xede4, 0x29a, 0xedf0,
+ 0x296, 0xedfc, 0x293, 0xee09, 0x28f, 0xee15, 0x28c, 0xee21,
+ 0x288, 0xee2d, 0x285, 0xee39, 0x281, 0xee45, 0x27e, 0xee51,
+ 0x27a, 0xee5d, 0x277, 0xee69, 0x273, 0xee75, 0x270, 0xee81,
+ 0x26d, 0xee8d, 0x269, 0xee99, 0x266, 0xeea6, 0x262, 0xeeb2,
+ 0x25f, 0xeebe, 0x25c, 0xeeca, 0x258, 0xeed6, 0x255, 0xeee2,
+ 0x251, 0xeeee, 0x24e, 0xeefa, 0x24b, 0xef06, 0x247, 0xef13,
+ 0x244, 0xef1f, 0x241, 0xef2b, 0x23e, 0xef37, 0x23a, 0xef43,
+ 0x237, 0xef4f, 0x234, 0xef5b, 0x230, 0xef67, 0x22d, 0xef74,
+ 0x22a, 0xef80, 0x227, 0xef8c, 0x223, 0xef98, 0x220, 0xefa4,
+ 0x21d, 0xefb0, 0x21a, 0xefbc, 0x217, 0xefc9, 0x213, 0xefd5,
+ 0x210, 0xefe1, 0x20d, 0xefed, 0x20a, 0xeff9, 0x207, 0xf005,
+ 0x204, 0xf012, 0x201, 0xf01e, 0x1fd, 0xf02a, 0x1fa, 0xf036,
+ 0x1f7, 0xf042, 0x1f4, 0xf04e, 0x1f1, 0xf05b, 0x1ee, 0xf067,
+ 0x1eb, 0xf073, 0x1e8, 0xf07f, 0x1e5, 0xf08b, 0x1e2, 0xf098,
+ 0x1df, 0xf0a4, 0x1dc, 0xf0b0, 0x1d9, 0xf0bc, 0x1d6, 0xf0c8,
+ 0x1d3, 0xf0d5, 0x1d0, 0xf0e1, 0x1cd, 0xf0ed, 0x1ca, 0xf0f9,
+ 0x1c7, 0xf105, 0x1c4, 0xf112, 0x1c1, 0xf11e, 0x1be, 0xf12a,
+ 0x1bb, 0xf136, 0x1b8, 0xf143, 0x1b6, 0xf14f, 0x1b3, 0xf15b,
+ 0x1b0, 0xf167, 0x1ad, 0xf174, 0x1aa, 0xf180, 0x1a7, 0xf18c,
+ 0x1a4, 0xf198, 0x1a2, 0xf1a4, 0x19f, 0xf1b1, 0x19c, 0xf1bd,
+ 0x199, 0xf1c9, 0x196, 0xf1d5, 0x194, 0xf1e2, 0x191, 0xf1ee,
+ 0x18e, 0xf1fa, 0x18b, 0xf207, 0x189, 0xf213, 0x186, 0xf21f,
+ 0x183, 0xf22b, 0x180, 0xf238, 0x17e, 0xf244, 0x17b, 0xf250,
+ 0x178, 0xf25c, 0x176, 0xf269, 0x173, 0xf275, 0x170, 0xf281,
+ 0x16e, 0xf28e, 0x16b, 0xf29a, 0x168, 0xf2a6, 0x166, 0xf2b2,
+ 0x163, 0xf2bf, 0x161, 0xf2cb, 0x15e, 0xf2d7, 0x15b, 0xf2e4,
+ 0x159, 0xf2f0, 0x156, 0xf2fc, 0x154, 0xf308, 0x151, 0xf315,
+ 0x14f, 0xf321, 0x14c, 0xf32d, 0x14a, 0xf33a, 0x147, 0xf346,
+ 0x145, 0xf352, 0x142, 0xf35f, 0x140, 0xf36b, 0x13d, 0xf377,
+ 0x13b, 0xf384, 0x138, 0xf390, 0x136, 0xf39c, 0x134, 0xf3a9,
+ 0x131, 0xf3b5, 0x12f, 0xf3c1, 0x12c, 0xf3ce, 0x12a, 0xf3da,
+ 0x128, 0xf3e6, 0x125, 0xf3f3, 0x123, 0xf3ff, 0x120, 0xf40b,
+ 0x11e, 0xf418, 0x11c, 0xf424, 0x119, 0xf430, 0x117, 0xf43d,
+ 0x115, 0xf449, 0x113, 0xf455, 0x110, 0xf462, 0x10e, 0xf46e,
+ 0x10c, 0xf47b, 0x109, 0xf487, 0x107, 0xf493, 0x105, 0xf4a0,
+ 0x103, 0xf4ac, 0x100, 0xf4b8, 0xfe, 0xf4c5, 0xfc, 0xf4d1,
+ 0xfa, 0xf4dd, 0xf8, 0xf4ea, 0xf6, 0xf4f6, 0xf3, 0xf503,
+ 0xf1, 0xf50f, 0xef, 0xf51b, 0xed, 0xf528, 0xeb, 0xf534,
+ 0xe9, 0xf540, 0xe7, 0xf54d, 0xe4, 0xf559, 0xe2, 0xf566,
+ 0xe0, 0xf572, 0xde, 0xf57e, 0xdc, 0xf58b, 0xda, 0xf597,
+ 0xd8, 0xf5a4, 0xd6, 0xf5b0, 0xd4, 0xf5bc, 0xd2, 0xf5c9,
+ 0xd0, 0xf5d5, 0xce, 0xf5e2, 0xcc, 0xf5ee, 0xca, 0xf5fa,
+ 0xc8, 0xf607, 0xc6, 0xf613, 0xc4, 0xf620, 0xc2, 0xf62c,
+ 0xc0, 0xf639, 0xbe, 0xf645, 0xbd, 0xf651, 0xbb, 0xf65e,
+ 0xb9, 0xf66a, 0xb7, 0xf677, 0xb5, 0xf683, 0xb3, 0xf690,
+ 0xb1, 0xf69c, 0xaf, 0xf6a8, 0xae, 0xf6b5, 0xac, 0xf6c1,
+ 0xaa, 0xf6ce, 0xa8, 0xf6da, 0xa6, 0xf6e7, 0xa5, 0xf6f3,
+ 0xa3, 0xf6ff, 0xa1, 0xf70c, 0x9f, 0xf718, 0x9e, 0xf725,
+ 0x9c, 0xf731, 0x9a, 0xf73e, 0x98, 0xf74a, 0x97, 0xf757,
+ 0x95, 0xf763, 0x93, 0xf76f, 0x92, 0xf77c, 0x90, 0xf788,
+ 0x8e, 0xf795, 0x8d, 0xf7a1, 0x8b, 0xf7ae, 0x89, 0xf7ba,
+ 0x88, 0xf7c7, 0x86, 0xf7d3, 0x85, 0xf7e0, 0x83, 0xf7ec,
+ 0x81, 0xf7f9, 0x80, 0xf805, 0x7e, 0xf811, 0x7d, 0xf81e,
+ 0x7b, 0xf82a, 0x7a, 0xf837, 0x78, 0xf843, 0x77, 0xf850,
+ 0x75, 0xf85c, 0x74, 0xf869, 0x72, 0xf875, 0x71, 0xf882,
+ 0x6f, 0xf88e, 0x6e, 0xf89b, 0x6c, 0xf8a7, 0x6b, 0xf8b4,
+ 0x69, 0xf8c0, 0x68, 0xf8cd, 0x67, 0xf8d9, 0x65, 0xf8e6,
+ 0x64, 0xf8f2, 0x62, 0xf8ff, 0x61, 0xf90b, 0x60, 0xf918,
+ 0x5e, 0xf924, 0x5d, 0xf931, 0x5c, 0xf93d, 0x5a, 0xf94a,
+ 0x59, 0xf956, 0x58, 0xf963, 0x56, 0xf96f, 0x55, 0xf97c,
+ 0x54, 0xf988, 0x53, 0xf995, 0x51, 0xf9a1, 0x50, 0xf9ae,
+ 0x4f, 0xf9ba, 0x4e, 0xf9c7, 0x4c, 0xf9d3, 0x4b, 0xf9e0,
+ 0x4a, 0xf9ec, 0x49, 0xf9f9, 0x48, 0xfa05, 0x47, 0xfa12,
+ 0x45, 0xfa1e, 0x44, 0xfa2b, 0x43, 0xfa37, 0x42, 0xfa44,
+ 0x41, 0xfa50, 0x40, 0xfa5d, 0x3f, 0xfa69, 0x3d, 0xfa76,
+ 0x3c, 0xfa82, 0x3b, 0xfa8f, 0x3a, 0xfa9b, 0x39, 0xfaa8,
+ 0x38, 0xfab4, 0x37, 0xfac1, 0x36, 0xfacd, 0x35, 0xfada,
+ 0x34, 0xfae6, 0x33, 0xfaf3, 0x32, 0xfb00, 0x31, 0xfb0c,
+ 0x30, 0xfb19, 0x2f, 0xfb25, 0x2e, 0xfb32, 0x2d, 0xfb3e,
+ 0x2c, 0xfb4b, 0x2b, 0xfb57, 0x2b, 0xfb64, 0x2a, 0xfb70,
+ 0x29, 0xfb7d, 0x28, 0xfb89, 0x27, 0xfb96, 0x26, 0xfba2,
+ 0x25, 0xfbaf, 0x24, 0xfbbc, 0x24, 0xfbc8, 0x23, 0xfbd5,
+ 0x22, 0xfbe1, 0x21, 0xfbee, 0x20, 0xfbfa, 0x20, 0xfc07,
+ 0x1f, 0xfc13, 0x1e, 0xfc20, 0x1d, 0xfc2c, 0x1d, 0xfc39,
+ 0x1c, 0xfc45, 0x1b, 0xfc52, 0x1a, 0xfc5f, 0x1a, 0xfc6b,
+ 0x19, 0xfc78, 0x18, 0xfc84, 0x18, 0xfc91, 0x17, 0xfc9d,
+ 0x16, 0xfcaa, 0x16, 0xfcb6, 0x15, 0xfcc3, 0x14, 0xfcd0,
+ 0x14, 0xfcdc, 0x13, 0xfce9, 0x13, 0xfcf5, 0x12, 0xfd02,
+ 0x11, 0xfd0e, 0x11, 0xfd1b, 0x10, 0xfd27, 0x10, 0xfd34,
+ 0xf, 0xfd40, 0xf, 0xfd4d, 0xe, 0xfd5a, 0xe, 0xfd66,
+ 0xd, 0xfd73, 0xd, 0xfd7f, 0xc, 0xfd8c, 0xc, 0xfd98,
+ 0xb, 0xfda5, 0xb, 0xfdb2, 0xa, 0xfdbe, 0xa, 0xfdcb,
+ 0x9, 0xfdd7, 0x9, 0xfde4, 0x9, 0xfdf0, 0x8, 0xfdfd,
+ 0x8, 0xfe09, 0x7, 0xfe16, 0x7, 0xfe23, 0x7, 0xfe2f,
+ 0x6, 0xfe3c, 0x6, 0xfe48, 0x6, 0xfe55, 0x5, 0xfe61,
+ 0x5, 0xfe6e, 0x5, 0xfe7a, 0x4, 0xfe87, 0x4, 0xfe94,
+ 0x4, 0xfea0, 0x4, 0xfead, 0x3, 0xfeb9, 0x3, 0xfec6,
+ 0x3, 0xfed2, 0x3, 0xfedf, 0x2, 0xfeec, 0x2, 0xfef8,
+ 0x2, 0xff05, 0x2, 0xff11, 0x2, 0xff1e, 0x1, 0xff2a,
+ 0x1, 0xff37, 0x1, 0xff44, 0x1, 0xff50, 0x1, 0xff5d,
+ 0x1, 0xff69, 0x1, 0xff76, 0x0, 0xff82, 0x0, 0xff8f,
+ 0x0, 0xff9b, 0x0, 0xffa8, 0x0, 0xffb5, 0x0, 0xffc1,
+ 0x0, 0xffce, 0x0, 0xffda, 0x0, 0xffe7, 0x0, 0xfff3,
+ 0x0, 0x0, 0x0, 0xd, 0x0, 0x19, 0x0, 0x26,
+ 0x0, 0x32, 0x0, 0x3f, 0x0, 0x4b, 0x0, 0x58,
+ 0x0, 0x65, 0x0, 0x71, 0x0, 0x7e, 0x1, 0x8a,
+ 0x1, 0x97, 0x1, 0xa3, 0x1, 0xb0, 0x1, 0xbc,
+ 0x1, 0xc9, 0x1, 0xd6, 0x2, 0xe2, 0x2, 0xef,
+ 0x2, 0xfb, 0x2, 0x108, 0x2, 0x114, 0x3, 0x121,
+ 0x3, 0x12e, 0x3, 0x13a, 0x3, 0x147, 0x4, 0x153,
+ 0x4, 0x160, 0x4, 0x16c, 0x4, 0x179, 0x5, 0x186,
+ 0x5, 0x192, 0x5, 0x19f, 0x6, 0x1ab, 0x6, 0x1b8,
+ 0x6, 0x1c4, 0x7, 0x1d1, 0x7, 0x1dd, 0x7, 0x1ea,
+ 0x8, 0x1f7, 0x8, 0x203, 0x9, 0x210, 0x9, 0x21c,
+ 0x9, 0x229, 0xa, 0x235, 0xa, 0x242, 0xb, 0x24e,
+ 0xb, 0x25b, 0xc, 0x268, 0xc, 0x274, 0xd, 0x281,
+ 0xd, 0x28d, 0xe, 0x29a, 0xe, 0x2a6, 0xf, 0x2b3,
+ 0xf, 0x2c0, 0x10, 0x2cc, 0x10, 0x2d9, 0x11, 0x2e5,
+ 0x11, 0x2f2, 0x12, 0x2fe, 0x13, 0x30b, 0x13, 0x317,
+ 0x14, 0x324, 0x14, 0x330, 0x15, 0x33d, 0x16, 0x34a,
+ 0x16, 0x356, 0x17, 0x363, 0x18, 0x36f, 0x18, 0x37c,
+ 0x19, 0x388, 0x1a, 0x395, 0x1a, 0x3a1, 0x1b, 0x3ae,
+ 0x1c, 0x3bb, 0x1d, 0x3c7, 0x1d, 0x3d4, 0x1e, 0x3e0,
+ 0x1f, 0x3ed, 0x20, 0x3f9, 0x20, 0x406, 0x21, 0x412,
+ 0x22, 0x41f, 0x23, 0x42b, 0x24, 0x438, 0x24, 0x444,
+ 0x25, 0x451, 0x26, 0x45e, 0x27, 0x46a, 0x28, 0x477,
+ 0x29, 0x483, 0x2a, 0x490, 0x2b, 0x49c, 0x2b, 0x4a9,
+ 0x2c, 0x4b5, 0x2d, 0x4c2, 0x2e, 0x4ce, 0x2f, 0x4db,
+ 0x30, 0x4e7, 0x31, 0x4f4, 0x32, 0x500, 0x33, 0x50d,
+ 0x34, 0x51a, 0x35, 0x526, 0x36, 0x533, 0x37, 0x53f,
+ 0x38, 0x54c, 0x39, 0x558, 0x3a, 0x565, 0x3b, 0x571,
+ 0x3c, 0x57e, 0x3d, 0x58a, 0x3f, 0x597, 0x40, 0x5a3,
+ 0x41, 0x5b0, 0x42, 0x5bc, 0x43, 0x5c9, 0x44, 0x5d5,
+ 0x45, 0x5e2, 0x47, 0x5ee, 0x48, 0x5fb, 0x49, 0x607,
+ 0x4a, 0x614, 0x4b, 0x620, 0x4c, 0x62d, 0x4e, 0x639,
+ 0x4f, 0x646, 0x50, 0x652, 0x51, 0x65f, 0x53, 0x66b,
+ 0x54, 0x678, 0x55, 0x684, 0x56, 0x691, 0x58, 0x69d,
+ 0x59, 0x6aa, 0x5a, 0x6b6, 0x5c, 0x6c3, 0x5d, 0x6cf,
+ 0x5e, 0x6dc, 0x60, 0x6e8, 0x61, 0x6f5, 0x62, 0x701,
+ 0x64, 0x70e, 0x65, 0x71a, 0x67, 0x727, 0x68, 0x733,
+ 0x69, 0x740, 0x6b, 0x74c, 0x6c, 0x759, 0x6e, 0x765,
+ 0x6f, 0x772, 0x71, 0x77e, 0x72, 0x78b, 0x74, 0x797,
+ 0x75, 0x7a4, 0x77, 0x7b0, 0x78, 0x7bd, 0x7a, 0x7c9,
+ 0x7b, 0x7d6, 0x7d, 0x7e2, 0x7e, 0x7ef, 0x80, 0x7fb,
+ 0x81, 0x807, 0x83, 0x814, 0x85, 0x820, 0x86, 0x82d,
+ 0x88, 0x839, 0x89, 0x846, 0x8b, 0x852, 0x8d, 0x85f,
+ 0x8e, 0x86b, 0x90, 0x878, 0x92, 0x884, 0x93, 0x891,
+ 0x95, 0x89d, 0x97, 0x8a9, 0x98, 0x8b6, 0x9a, 0x8c2,
+ 0x9c, 0x8cf, 0x9e, 0x8db, 0x9f, 0x8e8, 0xa1, 0x8f4,
+ 0xa3, 0x901, 0xa5, 0x90d, 0xa6, 0x919, 0xa8, 0x926,
+ 0xaa, 0x932, 0xac, 0x93f, 0xae, 0x94b, 0xaf, 0x958,
+ 0xb1, 0x964, 0xb3, 0x970, 0xb5, 0x97d, 0xb7, 0x989,
+ 0xb9, 0x996, 0xbb, 0x9a2, 0xbd, 0x9af, 0xbe, 0x9bb,
+ 0xc0, 0x9c7, 0xc2, 0x9d4, 0xc4, 0x9e0, 0xc6, 0x9ed,
+ 0xc8, 0x9f9, 0xca, 0xa06, 0xcc, 0xa12, 0xce, 0xa1e,
+ 0xd0, 0xa2b, 0xd2, 0xa37, 0xd4, 0xa44, 0xd6, 0xa50,
+ 0xd8, 0xa5c, 0xda, 0xa69, 0xdc, 0xa75, 0xde, 0xa82,
+ 0xe0, 0xa8e, 0xe2, 0xa9a, 0xe4, 0xaa7, 0xe7, 0xab3,
+ 0xe9, 0xac0, 0xeb, 0xacc, 0xed, 0xad8, 0xef, 0xae5,
+ 0xf1, 0xaf1, 0xf3, 0xafd, 0xf6, 0xb0a, 0xf8, 0xb16,
+ 0xfa, 0xb23, 0xfc, 0xb2f, 0xfe, 0xb3b, 0x100, 0xb48,
+ 0x103, 0xb54, 0x105, 0xb60, 0x107, 0xb6d, 0x109, 0xb79,
+ 0x10c, 0xb85, 0x10e, 0xb92, 0x110, 0xb9e, 0x113, 0xbab,
+ 0x115, 0xbb7, 0x117, 0xbc3, 0x119, 0xbd0, 0x11c, 0xbdc,
+ 0x11e, 0xbe8, 0x120, 0xbf5, 0x123, 0xc01, 0x125, 0xc0d,
+ 0x128, 0xc1a, 0x12a, 0xc26, 0x12c, 0xc32, 0x12f, 0xc3f,
+ 0x131, 0xc4b, 0x134, 0xc57, 0x136, 0xc64, 0x138, 0xc70,
+ 0x13b, 0xc7c, 0x13d, 0xc89, 0x140, 0xc95, 0x142, 0xca1,
+ 0x145, 0xcae, 0x147, 0xcba, 0x14a, 0xcc6, 0x14c, 0xcd3,
+ 0x14f, 0xcdf, 0x151, 0xceb, 0x154, 0xcf8, 0x156, 0xd04,
+ 0x159, 0xd10, 0x15b, 0xd1c, 0x15e, 0xd29, 0x161, 0xd35,
+ 0x163, 0xd41, 0x166, 0xd4e, 0x168, 0xd5a, 0x16b, 0xd66,
+ 0x16e, 0xd72, 0x170, 0xd7f, 0x173, 0xd8b, 0x176, 0xd97,
+ 0x178, 0xda4, 0x17b, 0xdb0, 0x17e, 0xdbc, 0x180, 0xdc8,
+ 0x183, 0xdd5, 0x186, 0xde1, 0x189, 0xded, 0x18b, 0xdf9,
+ 0x18e, 0xe06, 0x191, 0xe12, 0x194, 0xe1e, 0x196, 0xe2b,
+ 0x199, 0xe37, 0x19c, 0xe43, 0x19f, 0xe4f, 0x1a2, 0xe5c,
+ 0x1a4, 0xe68, 0x1a7, 0xe74, 0x1aa, 0xe80, 0x1ad, 0xe8c,
+ 0x1b0, 0xe99, 0x1b3, 0xea5, 0x1b6, 0xeb1, 0x1b8, 0xebd,
+ 0x1bb, 0xeca, 0x1be, 0xed6, 0x1c1, 0xee2, 0x1c4, 0xeee,
+ 0x1c7, 0xefb, 0x1ca, 0xf07, 0x1cd, 0xf13, 0x1d0, 0xf1f,
+ 0x1d3, 0xf2b, 0x1d6, 0xf38, 0x1d9, 0xf44, 0x1dc, 0xf50,
+ 0x1df, 0xf5c, 0x1e2, 0xf68, 0x1e5, 0xf75, 0x1e8, 0xf81,
+ 0x1eb, 0xf8d, 0x1ee, 0xf99, 0x1f1, 0xfa5, 0x1f4, 0xfb2,
+ 0x1f7, 0xfbe, 0x1fa, 0xfca, 0x1fd, 0xfd6, 0x201, 0xfe2,
+ 0x204, 0xfee, 0x207, 0xffb, 0x20a, 0x1007, 0x20d, 0x1013,
+ 0x210, 0x101f, 0x213, 0x102b, 0x217, 0x1037, 0x21a, 0x1044,
+ 0x21d, 0x1050, 0x220, 0x105c, 0x223, 0x1068, 0x227, 0x1074,
+ 0x22a, 0x1080, 0x22d, 0x108c, 0x230, 0x1099, 0x234, 0x10a5,
+ 0x237, 0x10b1, 0x23a, 0x10bd, 0x23e, 0x10c9, 0x241, 0x10d5,
+ 0x244, 0x10e1, 0x247, 0x10ed, 0x24b, 0x10fa, 0x24e, 0x1106,
+ 0x251, 0x1112, 0x255, 0x111e, 0x258, 0x112a, 0x25c, 0x1136,
+ 0x25f, 0x1142, 0x262, 0x114e, 0x266, 0x115a, 0x269, 0x1167,
+ 0x26d, 0x1173, 0x270, 0x117f, 0x273, 0x118b, 0x277, 0x1197,
+ 0x27a, 0x11a3, 0x27e, 0x11af, 0x281, 0x11bb, 0x285, 0x11c7,
+ 0x288, 0x11d3, 0x28c, 0x11df, 0x28f, 0x11eb, 0x293, 0x11f7,
+ 0x296, 0x1204, 0x29a, 0x1210, 0x29d, 0x121c, 0x2a1, 0x1228,
+ 0x2a5, 0x1234, 0x2a8, 0x1240, 0x2ac, 0x124c, 0x2af, 0x1258,
+ 0x2b3, 0x1264, 0x2b7, 0x1270, 0x2ba, 0x127c, 0x2be, 0x1288,
+ 0x2c1, 0x1294, 0x2c5, 0x12a0, 0x2c9, 0x12ac, 0x2cc, 0x12b8,
+ 0x2d0, 0x12c4, 0x2d4, 0x12d0, 0x2d8, 0x12dc, 0x2db, 0x12e8,
+ 0x2df, 0x12f4, 0x2e3, 0x1300, 0x2e6, 0x130c, 0x2ea, 0x1318,
+ 0x2ee, 0x1324, 0x2f2, 0x1330, 0x2f5, 0x133c, 0x2f9, 0x1348,
+ 0x2fd, 0x1354, 0x301, 0x1360, 0x305, 0x136c, 0x308, 0x1378,
+ 0x30c, 0x1384, 0x310, 0x1390, 0x314, 0x139c, 0x318, 0x13a8,
+ 0x31c, 0x13b4, 0x320, 0x13c0, 0x323, 0x13cc, 0x327, 0x13d8,
+ 0x32b, 0x13e4, 0x32f, 0x13f0, 0x333, 0x13fb, 0x337, 0x1407,
+ 0x33b, 0x1413, 0x33f, 0x141f, 0x343, 0x142b, 0x347, 0x1437,
+ 0x34b, 0x1443, 0x34f, 0x144f, 0x353, 0x145b, 0x357, 0x1467,
+ 0x35b, 0x1473, 0x35f, 0x147f, 0x363, 0x148b, 0x367, 0x1496,
+ 0x36b, 0x14a2, 0x36f, 0x14ae, 0x373, 0x14ba, 0x377, 0x14c6,
+ 0x37b, 0x14d2, 0x37f, 0x14de, 0x383, 0x14ea, 0x387, 0x14f6,
+ 0x38c, 0x1501, 0x390, 0x150d, 0x394, 0x1519, 0x398, 0x1525,
+ 0x39c, 0x1531, 0x3a0, 0x153d, 0x3a5, 0x1549, 0x3a9, 0x1554,
+ 0x3ad, 0x1560, 0x3b1, 0x156c, 0x3b5, 0x1578, 0x3ba, 0x1584,
+ 0x3be, 0x1590, 0x3c2, 0x159b, 0x3c6, 0x15a7, 0x3ca, 0x15b3,
+ 0x3cf, 0x15bf, 0x3d3, 0x15cb, 0x3d7, 0x15d7, 0x3dc, 0x15e2,
+ 0x3e0, 0x15ee, 0x3e4, 0x15fa, 0x3e9, 0x1606, 0x3ed, 0x1612,
+ 0x3f1, 0x161d, 0x3f6, 0x1629, 0x3fa, 0x1635, 0x3fe, 0x1641,
+ 0x403, 0x164c, 0x407, 0x1658, 0x40b, 0x1664, 0x410, 0x1670,
+ 0x414, 0x167c, 0x419, 0x1687, 0x41d, 0x1693, 0x422, 0x169f,
+ 0x426, 0x16ab, 0x42a, 0x16b6, 0x42f, 0x16c2, 0x433, 0x16ce,
+ 0x438, 0x16da, 0x43c, 0x16e5, 0x441, 0x16f1, 0x445, 0x16fd,
+ 0x44a, 0x1709, 0x44e, 0x1714, 0x453, 0x1720, 0x457, 0x172c,
+ 0x45c, 0x1737, 0x461, 0x1743, 0x465, 0x174f, 0x46a, 0x175b,
+ 0x46e, 0x1766, 0x473, 0x1772, 0x478, 0x177e, 0x47c, 0x1789,
+ 0x481, 0x1795, 0x485, 0x17a1, 0x48a, 0x17ac, 0x48f, 0x17b8,
+ 0x493, 0x17c4, 0x498, 0x17cf, 0x49d, 0x17db, 0x4a1, 0x17e7,
+ 0x4a6, 0x17f2, 0x4ab, 0x17fe, 0x4b0, 0x180a, 0x4b4, 0x1815,
+ 0x4b9, 0x1821, 0x4be, 0x182d, 0x4c2, 0x1838, 0x4c7, 0x1844,
+ 0x4cc, 0x184f, 0x4d1, 0x185b, 0x4d6, 0x1867, 0x4da, 0x1872,
+ 0x4df, 0x187e, 0x4e4, 0x1889, 0x4e9, 0x1895, 0x4ee, 0x18a1,
+ 0x4f2, 0x18ac, 0x4f7, 0x18b8, 0x4fc, 0x18c3, 0x501, 0x18cf,
+ 0x506, 0x18db, 0x50b, 0x18e6, 0x510, 0x18f2, 0x515, 0x18fd,
+ 0x51a, 0x1909, 0x51e, 0x1914, 0x523, 0x1920, 0x528, 0x192c,
+ 0x52d, 0x1937, 0x532, 0x1943, 0x537, 0x194e, 0x53c, 0x195a,
+ 0x541, 0x1965, 0x546, 0x1971, 0x54b, 0x197c, 0x550, 0x1988,
+ 0x555, 0x1993, 0x55a, 0x199f, 0x55f, 0x19aa, 0x564, 0x19b6,
+ 0x569, 0x19c1, 0x56e, 0x19cd, 0x573, 0x19d8, 0x578, 0x19e4,
+ 0x57e, 0x19ef, 0x583, 0x19fb, 0x588, 0x1a06, 0x58d, 0x1a12,
+ 0x592, 0x1a1d, 0x597, 0x1a29, 0x59c, 0x1a34, 0x5a1, 0x1a40,
+ 0x5a7, 0x1a4b, 0x5ac, 0x1a57, 0x5b1, 0x1a62, 0x5b6, 0x1a6e,
+ 0x5bb, 0x1a79, 0x5c1, 0x1a84, 0x5c6, 0x1a90, 0x5cb, 0x1a9b,
+ 0x5d0, 0x1aa7, 0x5d5, 0x1ab2, 0x5db, 0x1abe, 0x5e0, 0x1ac9,
+ 0x5e5, 0x1ad4, 0x5ea, 0x1ae0, 0x5f0, 0x1aeb, 0x5f5, 0x1af7,
+ 0x5fa, 0x1b02, 0x600, 0x1b0d, 0x605, 0x1b19, 0x60a, 0x1b24,
+ 0x610, 0x1b30, 0x615, 0x1b3b, 0x61a, 0x1b46, 0x620, 0x1b52,
+ 0x625, 0x1b5d, 0x62a, 0x1b68, 0x630, 0x1b74, 0x635, 0x1b7f,
+ 0x63b, 0x1b8a, 0x640, 0x1b96, 0x645, 0x1ba1, 0x64b, 0x1bac,
+ 0x650, 0x1bb8, 0x656, 0x1bc3, 0x65b, 0x1bce, 0x661, 0x1bda,
+ 0x666, 0x1be5, 0x66c, 0x1bf0, 0x671, 0x1bfc, 0x677, 0x1c07,
+ 0x67c, 0x1c12, 0x682, 0x1c1e, 0x687, 0x1c29, 0x68d, 0x1c34,
+ 0x692, 0x1c3f, 0x698, 0x1c4b, 0x69d, 0x1c56, 0x6a3, 0x1c61,
+ 0x6a8, 0x1c6c, 0x6ae, 0x1c78, 0x6b4, 0x1c83, 0x6b9, 0x1c8e,
+ 0x6bf, 0x1c99, 0x6c5, 0x1ca5, 0x6ca, 0x1cb0, 0x6d0, 0x1cbb,
+ 0x6d5, 0x1cc6, 0x6db, 0x1cd2, 0x6e1, 0x1cdd, 0x6e6, 0x1ce8,
+ 0x6ec, 0x1cf3, 0x6f2, 0x1cff, 0x6f7, 0x1d0a, 0x6fd, 0x1d15,
+ 0x703, 0x1d20, 0x709, 0x1d2b, 0x70e, 0x1d36, 0x714, 0x1d42,
+ 0x71a, 0x1d4d, 0x720, 0x1d58, 0x725, 0x1d63, 0x72b, 0x1d6e,
+ 0x731, 0x1d79, 0x737, 0x1d85, 0x73d, 0x1d90, 0x742, 0x1d9b,
+ 0x748, 0x1da6, 0x74e, 0x1db1, 0x754, 0x1dbc, 0x75a, 0x1dc7,
+ 0x75f, 0x1dd3, 0x765, 0x1dde, 0x76b, 0x1de9, 0x771, 0x1df4,
+ 0x777, 0x1dff, 0x77d, 0x1e0a, 0x783, 0x1e15, 0x789, 0x1e20,
+ 0x78f, 0x1e2b, 0x795, 0x1e36, 0x79a, 0x1e42, 0x7a0, 0x1e4d,
+ 0x7a6, 0x1e58, 0x7ac, 0x1e63, 0x7b2, 0x1e6e, 0x7b8, 0x1e79,
+ 0x7be, 0x1e84, 0x7c4, 0x1e8f, 0x7ca, 0x1e9a, 0x7d0, 0x1ea5,
+ 0x7d6, 0x1eb0, 0x7dc, 0x1ebb, 0x7e2, 0x1ec6, 0x7e8, 0x1ed1,
+ 0x7ee, 0x1edc, 0x7f5, 0x1ee7, 0x7fb, 0x1ef2, 0x801, 0x1efd,
+ 0x807, 0x1f08, 0x80d, 0x1f13, 0x813, 0x1f1e, 0x819, 0x1f29,
+ 0x81f, 0x1f34, 0x825, 0x1f3f, 0x82b, 0x1f4a, 0x832, 0x1f55,
+ 0x838, 0x1f60, 0x83e, 0x1f6b, 0x844, 0x1f76, 0x84a, 0x1f81,
+ 0x850, 0x1f8c, 0x857, 0x1f97, 0x85d, 0x1fa2, 0x863, 0x1fac,
+ 0x869, 0x1fb7, 0x870, 0x1fc2, 0x876, 0x1fcd, 0x87c, 0x1fd8,
+ 0x882, 0x1fe3, 0x889, 0x1fee, 0x88f, 0x1ff9, 0x895, 0x2004,
+ 0x89b, 0x200f, 0x8a2, 0x2019, 0x8a8, 0x2024, 0x8ae, 0x202f,
+ 0x8b5, 0x203a, 0x8bb, 0x2045, 0x8c1, 0x2050, 0x8c8, 0x205b,
+ 0x8ce, 0x2065, 0x8d4, 0x2070, 0x8db, 0x207b, 0x8e1, 0x2086,
+ 0x8e8, 0x2091, 0x8ee, 0x209b, 0x8f4, 0x20a6, 0x8fb, 0x20b1,
+ 0x901, 0x20bc, 0x908, 0x20c7, 0x90e, 0x20d1, 0x915, 0x20dc,
+ 0x91b, 0x20e7, 0x921, 0x20f2, 0x928, 0x20fd, 0x92e, 0x2107,
+ 0x935, 0x2112, 0x93b, 0x211d, 0x942, 0x2128, 0x948, 0x2132,
+ 0x94f, 0x213d, 0x955, 0x2148, 0x95c, 0x2153, 0x963, 0x215d,
+ 0x969, 0x2168, 0x970, 0x2173, 0x976, 0x217d, 0x97d, 0x2188,
+ 0x983, 0x2193, 0x98a, 0x219e, 0x991, 0x21a8, 0x997, 0x21b3,
+ 0x99e, 0x21be, 0x9a4, 0x21c8, 0x9ab, 0x21d3, 0x9b2, 0x21de,
+ 0x9b8, 0x21e8, 0x9bf, 0x21f3, 0x9c6, 0x21fe, 0x9cc, 0x2208,
+ 0x9d3, 0x2213, 0x9da, 0x221e, 0x9e0, 0x2228, 0x9e7, 0x2233,
+ 0x9ee, 0x223d, 0x9f5, 0x2248, 0x9fb, 0x2253, 0xa02, 0x225d,
+ 0xa09, 0x2268, 0xa10, 0x2272, 0xa16, 0x227d, 0xa1d, 0x2288,
+ 0xa24, 0x2292, 0xa2b, 0x229d, 0xa32, 0x22a7, 0xa38, 0x22b2,
+ 0xa3f, 0x22bc, 0xa46, 0x22c7, 0xa4d, 0x22d2, 0xa54, 0x22dc,
+ 0xa5b, 0x22e7, 0xa61, 0x22f1, 0xa68, 0x22fc, 0xa6f, 0x2306,
+ 0xa76, 0x2311, 0xa7d, 0x231b, 0xa84, 0x2326, 0xa8b, 0x2330,
+ 0xa92, 0x233b, 0xa99, 0x2345, 0xa9f, 0x2350, 0xaa6, 0x235a,
+ 0xaad, 0x2365, 0xab4, 0x236f, 0xabb, 0x237a, 0xac2, 0x2384,
+ 0xac9, 0x238e, 0xad0, 0x2399, 0xad7, 0x23a3, 0xade, 0x23ae,
+ 0xae5, 0x23b8, 0xaec, 0x23c3, 0xaf3, 0x23cd, 0xafa, 0x23d7,
+ 0xb01, 0x23e2, 0xb08, 0x23ec, 0xb0f, 0x23f7, 0xb16, 0x2401,
+ 0xb1e, 0x240b, 0xb25, 0x2416, 0xb2c, 0x2420, 0xb33, 0x242b,
+ 0xb3a, 0x2435, 0xb41, 0x243f, 0xb48, 0x244a, 0xb4f, 0x2454,
+ 0xb56, 0x245e, 0xb5e, 0x2469, 0xb65, 0x2473, 0xb6c, 0x247d,
+ 0xb73, 0x2488, 0xb7a, 0x2492, 0xb81, 0x249c, 0xb89, 0x24a7,
+ 0xb90, 0x24b1, 0xb97, 0x24bb, 0xb9e, 0x24c5, 0xba5, 0x24d0,
+ 0xbad, 0x24da, 0xbb4, 0x24e4, 0xbbb, 0x24ef, 0xbc2, 0x24f9,
+ 0xbca, 0x2503, 0xbd1, 0x250d, 0xbd8, 0x2518, 0xbe0, 0x2522,
+ 0xbe7, 0x252c, 0xbee, 0x2536, 0xbf5, 0x2541, 0xbfd, 0x254b,
+ 0xc04, 0x2555, 0xc0b, 0x255f, 0xc13, 0x2569, 0xc1a, 0x2574,
+ 0xc21, 0x257e, 0xc29, 0x2588, 0xc30, 0x2592, 0xc38, 0x259c,
+ 0xc3f, 0x25a6, 0xc46, 0x25b1, 0xc4e, 0x25bb, 0xc55, 0x25c5,
+ 0xc5d, 0x25cf, 0xc64, 0x25d9, 0xc6b, 0x25e3, 0xc73, 0x25ed,
+ 0xc7a, 0x25f8, 0xc82, 0x2602, 0xc89, 0x260c, 0xc91, 0x2616,
+ 0xc98, 0x2620, 0xca0, 0x262a, 0xca7, 0x2634, 0xcaf, 0x263e,
+ 0xcb6, 0x2648, 0xcbe, 0x2652, 0xcc5, 0x265c, 0xccd, 0x2666,
+ 0xcd4, 0x2671, 0xcdc, 0x267b, 0xce3, 0x2685, 0xceb, 0x268f,
+ 0xcf3, 0x2699, 0xcfa, 0x26a3, 0xd02, 0x26ad, 0xd09, 0x26b7,
+ 0xd11, 0x26c1, 0xd19, 0x26cb, 0xd20, 0x26d5, 0xd28, 0x26df,
+ 0xd30, 0x26e9, 0xd37, 0x26f3, 0xd3f, 0x26fd, 0xd46, 0x2707,
+ 0xd4e, 0x2711, 0xd56, 0x271a, 0xd5d, 0x2724, 0xd65, 0x272e,
+ 0xd6d, 0x2738, 0xd75, 0x2742, 0xd7c, 0x274c, 0xd84, 0x2756,
+ 0xd8c, 0x2760, 0xd93, 0x276a, 0xd9b, 0x2774, 0xda3, 0x277e,
+ 0xdab, 0x2788, 0xdb2, 0x2791, 0xdba, 0x279b, 0xdc2, 0x27a5,
+ 0xdca, 0x27af, 0xdd2, 0x27b9, 0xdd9, 0x27c3, 0xde1, 0x27cd,
+ 0xde9, 0x27d6, 0xdf1, 0x27e0, 0xdf9, 0x27ea, 0xe01, 0x27f4,
+ 0xe08, 0x27fe, 0xe10, 0x2808, 0xe18, 0x2811, 0xe20, 0x281b,
+ 0xe28, 0x2825, 0xe30, 0x282f, 0xe38, 0x2838, 0xe40, 0x2842,
+ 0xe47, 0x284c, 0xe4f, 0x2856, 0xe57, 0x2860, 0xe5f, 0x2869,
+ 0xe67, 0x2873, 0xe6f, 0x287d, 0xe77, 0x2886, 0xe7f, 0x2890,
+ 0xe87, 0x289a, 0xe8f, 0x28a4, 0xe97, 0x28ad, 0xe9f, 0x28b7,
+ 0xea7, 0x28c1, 0xeaf, 0x28ca, 0xeb7, 0x28d4, 0xebf, 0x28de,
+ 0xec7, 0x28e7, 0xecf, 0x28f1, 0xed7, 0x28fb, 0xedf, 0x2904,
+ 0xee7, 0x290e, 0xeef, 0x2918, 0xef7, 0x2921, 0xeff, 0x292b,
+ 0xf07, 0x2935, 0xf10, 0x293e, 0xf18, 0x2948, 0xf20, 0x2951,
+ 0xf28, 0x295b, 0xf30, 0x2965, 0xf38, 0x296e, 0xf40, 0x2978,
+ 0xf48, 0x2981, 0xf51, 0x298b, 0xf59, 0x2994, 0xf61, 0x299e,
+ 0xf69, 0x29a7, 0xf71, 0x29b1, 0xf79, 0x29bb, 0xf82, 0x29c4,
+ 0xf8a, 0x29ce, 0xf92, 0x29d7, 0xf9a, 0x29e1, 0xfa3, 0x29ea,
+ 0xfab, 0x29f4, 0xfb3, 0x29fd, 0xfbb, 0x2a07, 0xfc4, 0x2a10,
+ 0xfcc, 0x2a1a, 0xfd4, 0x2a23, 0xfdc, 0x2a2c, 0xfe5, 0x2a36,
+ 0xfed, 0x2a3f, 0xff5, 0x2a49, 0xffe, 0x2a52, 0x1006, 0x2a5c,
+ 0x100e, 0x2a65, 0x1016, 0x2a6e, 0x101f, 0x2a78, 0x1027, 0x2a81,
+ 0x1030, 0x2a8b, 0x1038, 0x2a94, 0x1040, 0x2a9d, 0x1049, 0x2aa7,
+ 0x1051, 0x2ab0, 0x1059, 0x2ab9, 0x1062, 0x2ac3, 0x106a, 0x2acc,
+ 0x1073, 0x2ad6, 0x107b, 0x2adf, 0x1083, 0x2ae8, 0x108c, 0x2af2,
+ 0x1094, 0x2afb, 0x109d, 0x2b04, 0x10a5, 0x2b0d, 0x10ae, 0x2b17,
+ 0x10b6, 0x2b20, 0x10bf, 0x2b29, 0x10c7, 0x2b33, 0x10d0, 0x2b3c,
+ 0x10d8, 0x2b45, 0x10e0, 0x2b4e, 0x10e9, 0x2b58, 0x10f2, 0x2b61,
+ 0x10fa, 0x2b6a, 0x1103, 0x2b73, 0x110b, 0x2b7d, 0x1114, 0x2b86,
+ 0x111c, 0x2b8f, 0x1125, 0x2b98, 0x112d, 0x2ba1, 0x1136, 0x2bab,
+ 0x113e, 0x2bb4, 0x1147, 0x2bbd, 0x1150, 0x2bc6, 0x1158, 0x2bcf,
+ 0x1161, 0x2bd8, 0x1169, 0x2be2, 0x1172, 0x2beb, 0x117b, 0x2bf4,
+ 0x1183, 0x2bfd, 0x118c, 0x2c06, 0x1195, 0x2c0f, 0x119d, 0x2c18,
+ 0x11a6, 0x2c21, 0x11af, 0x2c2b, 0x11b7, 0x2c34, 0x11c0, 0x2c3d,
+ 0x11c9, 0x2c46, 0x11d1, 0x2c4f, 0x11da, 0x2c58, 0x11e3, 0x2c61,
+ 0x11eb, 0x2c6a, 0x11f4, 0x2c73, 0x11fd, 0x2c7c, 0x1206, 0x2c85,
+ 0x120e, 0x2c8e, 0x1217, 0x2c97, 0x1220, 0x2ca0, 0x1229, 0x2ca9,
+ 0x1231, 0x2cb2, 0x123a, 0x2cbb, 0x1243, 0x2cc4, 0x124c, 0x2ccd,
+ 0x1255, 0x2cd6, 0x125d, 0x2cdf, 0x1266, 0x2ce8, 0x126f, 0x2cf1,
+ 0x1278, 0x2cfa, 0x1281, 0x2d03, 0x128a, 0x2d0c, 0x1292, 0x2d15,
+ 0x129b, 0x2d1e, 0x12a4, 0x2d27, 0x12ad, 0x2d2f, 0x12b6, 0x2d38,
+ 0x12bf, 0x2d41, 0x12c8, 0x2d4a, 0x12d1, 0x2d53, 0x12d9, 0x2d5c,
+ 0x12e2, 0x2d65, 0x12eb, 0x2d6e, 0x12f4, 0x2d76, 0x12fd, 0x2d7f,
+ 0x1306, 0x2d88, 0x130f, 0x2d91, 0x1318, 0x2d9a, 0x1321, 0x2da3,
+ 0x132a, 0x2dab, 0x1333, 0x2db4, 0x133c, 0x2dbd, 0x1345, 0x2dc6,
+ 0x134e, 0x2dcf, 0x1357, 0x2dd7, 0x1360, 0x2de0, 0x1369, 0x2de9,
+ 0x1372, 0x2df2, 0x137b, 0x2dfa, 0x1384, 0x2e03, 0x138d, 0x2e0c,
+ 0x1396, 0x2e15, 0x139f, 0x2e1d, 0x13a8, 0x2e26, 0x13b1, 0x2e2f,
+ 0x13ba, 0x2e37, 0x13c3, 0x2e40, 0x13cc, 0x2e49, 0x13d5, 0x2e51,
+ 0x13df, 0x2e5a, 0x13e8, 0x2e63, 0x13f1, 0x2e6b, 0x13fa, 0x2e74,
+ 0x1403, 0x2e7d, 0x140c, 0x2e85, 0x1415, 0x2e8e, 0x141e, 0x2e97,
+ 0x1428, 0x2e9f, 0x1431, 0x2ea8, 0x143a, 0x2eb0, 0x1443, 0x2eb9,
+ 0x144c, 0x2ec2, 0x1455, 0x2eca, 0x145f, 0x2ed3, 0x1468, 0x2edb,
+ 0x1471, 0x2ee4, 0x147a, 0x2eec, 0x1483, 0x2ef5, 0x148d, 0x2efd,
+ 0x1496, 0x2f06, 0x149f, 0x2f0e, 0x14a8, 0x2f17, 0x14b2, 0x2f20,
+ 0x14bb, 0x2f28, 0x14c4, 0x2f30, 0x14cd, 0x2f39, 0x14d7, 0x2f41,
+ 0x14e0, 0x2f4a, 0x14e9, 0x2f52, 0x14f3, 0x2f5b, 0x14fc, 0x2f63,
+ 0x1505, 0x2f6c, 0x150e, 0x2f74, 0x1518, 0x2f7d, 0x1521, 0x2f85,
+ 0x152a, 0x2f8d, 0x1534, 0x2f96, 0x153d, 0x2f9e, 0x1547, 0x2fa7,
+ 0x1550, 0x2faf, 0x1559, 0x2fb7, 0x1563, 0x2fc0, 0x156c, 0x2fc8,
+ 0x1575, 0x2fd0, 0x157f, 0x2fd9, 0x1588, 0x2fe1, 0x1592, 0x2fea,
+ 0x159b, 0x2ff2, 0x15a4, 0x2ffa, 0x15ae, 0x3002, 0x15b7, 0x300b,
+ 0x15c1, 0x3013, 0x15ca, 0x301b, 0x15d4, 0x3024, 0x15dd, 0x302c,
+ 0x15e6, 0x3034, 0x15f0, 0x303c, 0x15f9, 0x3045, 0x1603, 0x304d,
+ 0x160c, 0x3055, 0x1616, 0x305d, 0x161f, 0x3066, 0x1629, 0x306e,
+ 0x1632, 0x3076, 0x163c, 0x307e, 0x1645, 0x3087, 0x164f, 0x308f,
+ 0x1659, 0x3097, 0x1662, 0x309f, 0x166c, 0x30a7, 0x1675, 0x30af,
+ 0x167f, 0x30b8, 0x1688, 0x30c0, 0x1692, 0x30c8, 0x169b, 0x30d0,
+ 0x16a5, 0x30d8, 0x16af, 0x30e0, 0x16b8, 0x30e8, 0x16c2, 0x30f0,
+ 0x16cb, 0x30f9, 0x16d5, 0x3101, 0x16df, 0x3109, 0x16e8, 0x3111,
+ 0x16f2, 0x3119, 0x16fc, 0x3121, 0x1705, 0x3129, 0x170f, 0x3131,
+ 0x1719, 0x3139, 0x1722, 0x3141, 0x172c, 0x3149, 0x1736, 0x3151,
+ 0x173f, 0x3159, 0x1749, 0x3161, 0x1753, 0x3169, 0x175c, 0x3171,
+ 0x1766, 0x3179, 0x1770, 0x3181, 0x177a, 0x3189, 0x1783, 0x3191,
+ 0x178d, 0x3199, 0x1797, 0x31a1, 0x17a0, 0x31a9, 0x17aa, 0x31b1,
+ 0x17b4, 0x31b9, 0x17be, 0x31c0, 0x17c8, 0x31c8, 0x17d1, 0x31d0,
+ 0x17db, 0x31d8, 0x17e5, 0x31e0, 0x17ef, 0x31e8, 0x17f8, 0x31f0,
+ 0x1802, 0x31f8, 0x180c, 0x31ff, 0x1816, 0x3207, 0x1820, 0x320f,
+ 0x182a, 0x3217, 0x1833, 0x321f, 0x183d, 0x3227, 0x1847, 0x322e,
+ 0x1851, 0x3236, 0x185b, 0x323e, 0x1865, 0x3246, 0x186f, 0x324e,
+ 0x1878, 0x3255, 0x1882, 0x325d, 0x188c, 0x3265, 0x1896, 0x326d,
+ 0x18a0, 0x3274, 0x18aa, 0x327c, 0x18b4, 0x3284, 0x18be, 0x328b,
+ 0x18c8, 0x3293, 0x18d2, 0x329b, 0x18dc, 0x32a3, 0x18e6, 0x32aa,
+ 0x18ef, 0x32b2, 0x18f9, 0x32ba, 0x1903, 0x32c1, 0x190d, 0x32c9,
+ 0x1917, 0x32d0, 0x1921, 0x32d8, 0x192b, 0x32e0, 0x1935, 0x32e7,
+ 0x193f, 0x32ef, 0x1949, 0x32f7, 0x1953, 0x32fe, 0x195d, 0x3306,
+ 0x1967, 0x330d, 0x1971, 0x3315, 0x197b, 0x331d, 0x1985, 0x3324,
+ 0x198f, 0x332c, 0x199a, 0x3333, 0x19a4, 0x333b, 0x19ae, 0x3342,
+ 0x19b8, 0x334a, 0x19c2, 0x3351, 0x19cc, 0x3359, 0x19d6, 0x3360,
+ 0x19e0, 0x3368, 0x19ea, 0x336f, 0x19f4, 0x3377, 0x19fe, 0x337e,
+ 0x1a08, 0x3386, 0x1a13, 0x338d, 0x1a1d, 0x3395, 0x1a27, 0x339c,
+ 0x1a31, 0x33a3, 0x1a3b, 0x33ab, 0x1a45, 0x33b2, 0x1a4f, 0x33ba,
+ 0x1a5a, 0x33c1, 0x1a64, 0x33c8, 0x1a6e, 0x33d0, 0x1a78, 0x33d7,
+ 0x1a82, 0x33df, 0x1a8c, 0x33e6, 0x1a97, 0x33ed, 0x1aa1, 0x33f5,
+ 0x1aab, 0x33fc, 0x1ab5, 0x3403, 0x1abf, 0x340b, 0x1aca, 0x3412,
+ 0x1ad4, 0x3419, 0x1ade, 0x3420, 0x1ae8, 0x3428, 0x1af3, 0x342f,
+ 0x1afd, 0x3436, 0x1b07, 0x343e, 0x1b11, 0x3445, 0x1b1c, 0x344c,
+ 0x1b26, 0x3453, 0x1b30, 0x345b, 0x1b3b, 0x3462, 0x1b45, 0x3469,
+ 0x1b4f, 0x3470, 0x1b59, 0x3477, 0x1b64, 0x347f, 0x1b6e, 0x3486,
+ 0x1b78, 0x348d, 0x1b83, 0x3494, 0x1b8d, 0x349b, 0x1b97, 0x34a2,
+ 0x1ba2, 0x34aa, 0x1bac, 0x34b1, 0x1bb6, 0x34b8, 0x1bc1, 0x34bf,
+ 0x1bcb, 0x34c6, 0x1bd5, 0x34cd, 0x1be0, 0x34d4, 0x1bea, 0x34db,
+ 0x1bf5, 0x34e2, 0x1bff, 0x34ea, 0x1c09, 0x34f1, 0x1c14, 0x34f8,
+ 0x1c1e, 0x34ff, 0x1c29, 0x3506, 0x1c33, 0x350d, 0x1c3d, 0x3514,
+ 0x1c48, 0x351b, 0x1c52, 0x3522, 0x1c5d, 0x3529, 0x1c67, 0x3530,
+ 0x1c72, 0x3537, 0x1c7c, 0x353e, 0x1c86, 0x3545, 0x1c91, 0x354c,
+ 0x1c9b, 0x3553, 0x1ca6, 0x355a, 0x1cb0, 0x3561, 0x1cbb, 0x3567,
+ 0x1cc5, 0x356e, 0x1cd0, 0x3575, 0x1cda, 0x357c, 0x1ce5, 0x3583,
+ 0x1cef, 0x358a, 0x1cfa, 0x3591, 0x1d04, 0x3598, 0x1d0f, 0x359f,
+ 0x1d19, 0x35a5, 0x1d24, 0x35ac, 0x1d2e, 0x35b3, 0x1d39, 0x35ba,
+ 0x1d44, 0x35c1, 0x1d4e, 0x35c8, 0x1d59, 0x35ce, 0x1d63, 0x35d5,
+ 0x1d6e, 0x35dc, 0x1d78, 0x35e3, 0x1d83, 0x35ea, 0x1d8e, 0x35f0,
+ 0x1d98, 0x35f7, 0x1da3, 0x35fe, 0x1dad, 0x3605, 0x1db8, 0x360b,
+ 0x1dc3, 0x3612, 0x1dcd, 0x3619, 0x1dd8, 0x3620, 0x1de2, 0x3626,
+ 0x1ded, 0x362d, 0x1df8, 0x3634, 0x1e02, 0x363a, 0x1e0d, 0x3641,
+ 0x1e18, 0x3648, 0x1e22, 0x364e, 0x1e2d, 0x3655, 0x1e38, 0x365c,
+ 0x1e42, 0x3662, 0x1e4d, 0x3669, 0x1e58, 0x366f, 0x1e62, 0x3676,
+ 0x1e6d, 0x367d, 0x1e78, 0x3683, 0x1e83, 0x368a, 0x1e8d, 0x3690,
+ 0x1e98, 0x3697, 0x1ea3, 0x369d, 0x1ead, 0x36a4, 0x1eb8, 0x36ab,
+ 0x1ec3, 0x36b1, 0x1ece, 0x36b8, 0x1ed8, 0x36be, 0x1ee3, 0x36c5,
+ 0x1eee, 0x36cb, 0x1ef9, 0x36d2, 0x1f03, 0x36d8, 0x1f0e, 0x36df,
+ 0x1f19, 0x36e5, 0x1f24, 0x36eb, 0x1f2f, 0x36f2, 0x1f39, 0x36f8,
+ 0x1f44, 0x36ff, 0x1f4f, 0x3705, 0x1f5a, 0x370c, 0x1f65, 0x3712,
+ 0x1f6f, 0x3718, 0x1f7a, 0x371f, 0x1f85, 0x3725, 0x1f90, 0x372c,
+ 0x1f9b, 0x3732, 0x1fa5, 0x3738, 0x1fb0, 0x373f, 0x1fbb, 0x3745,
+ 0x1fc6, 0x374b, 0x1fd1, 0x3752, 0x1fdc, 0x3758, 0x1fe7, 0x375e,
+ 0x1ff1, 0x3765, 0x1ffc, 0x376b, 0x2007, 0x3771, 0x2012, 0x3777,
+ 0x201d, 0x377e, 0x2028, 0x3784, 0x2033, 0x378a, 0x203e, 0x3790,
+ 0x2049, 0x3797, 0x2054, 0x379d, 0x205e, 0x37a3, 0x2069, 0x37a9,
+ 0x2074, 0x37b0, 0x207f, 0x37b6, 0x208a, 0x37bc, 0x2095, 0x37c2,
+ 0x20a0, 0x37c8, 0x20ab, 0x37ce, 0x20b6, 0x37d5, 0x20c1, 0x37db,
+ 0x20cc, 0x37e1, 0x20d7, 0x37e7, 0x20e2, 0x37ed, 0x20ed, 0x37f3,
+ 0x20f8, 0x37f9, 0x2103, 0x37ff, 0x210e, 0x3805, 0x2119, 0x380b,
+ 0x2124, 0x3812, 0x212f, 0x3818, 0x213a, 0x381e, 0x2145, 0x3824,
+ 0x2150, 0x382a, 0x215b, 0x3830, 0x2166, 0x3836, 0x2171, 0x383c,
+ 0x217c, 0x3842, 0x2187, 0x3848, 0x2192, 0x384e, 0x219d, 0x3854,
+ 0x21a8, 0x385a, 0x21b3, 0x3860, 0x21be, 0x3866, 0x21ca, 0x386b,
+ 0x21d5, 0x3871, 0x21e0, 0x3877, 0x21eb, 0x387d, 0x21f6, 0x3883,
+ 0x2201, 0x3889, 0x220c, 0x388f, 0x2217, 0x3895, 0x2222, 0x389b,
+ 0x222d, 0x38a1, 0x2239, 0x38a6, 0x2244, 0x38ac, 0x224f, 0x38b2,
+ 0x225a, 0x38b8, 0x2265, 0x38be, 0x2270, 0x38c3, 0x227b, 0x38c9,
+ 0x2287, 0x38cf, 0x2292, 0x38d5, 0x229d, 0x38db, 0x22a8, 0x38e0,
+ 0x22b3, 0x38e6, 0x22be, 0x38ec, 0x22ca, 0x38f2, 0x22d5, 0x38f7,
+ 0x22e0, 0x38fd, 0x22eb, 0x3903, 0x22f6, 0x3909, 0x2301, 0x390e,
+ 0x230d, 0x3914, 0x2318, 0x391a, 0x2323, 0x391f, 0x232e, 0x3925,
+ 0x233a, 0x392b, 0x2345, 0x3930, 0x2350, 0x3936, 0x235b, 0x393b,
+ 0x2367, 0x3941, 0x2372, 0x3947, 0x237d, 0x394c, 0x2388, 0x3952,
+ 0x2394, 0x3958, 0x239f, 0x395d, 0x23aa, 0x3963, 0x23b5, 0x3968,
+ 0x23c1, 0x396e, 0x23cc, 0x3973, 0x23d7, 0x3979, 0x23e2, 0x397e,
+ 0x23ee, 0x3984, 0x23f9, 0x3989, 0x2404, 0x398f, 0x2410, 0x3994,
+ 0x241b, 0x399a, 0x2426, 0x399f, 0x2432, 0x39a5, 0x243d, 0x39aa,
+ 0x2448, 0x39b0, 0x2454, 0x39b5, 0x245f, 0x39bb, 0x246a, 0x39c0,
+ 0x2476, 0x39c5, 0x2481, 0x39cb, 0x248c, 0x39d0, 0x2498, 0x39d6,
+ 0x24a3, 0x39db, 0x24ae, 0x39e0, 0x24ba, 0x39e6, 0x24c5, 0x39eb,
+ 0x24d0, 0x39f0, 0x24dc, 0x39f6, 0x24e7, 0x39fb, 0x24f3, 0x3a00,
+ 0x24fe, 0x3a06, 0x2509, 0x3a0b, 0x2515, 0x3a10, 0x2520, 0x3a16,
+ 0x252c, 0x3a1b, 0x2537, 0x3a20, 0x2542, 0x3a25, 0x254e, 0x3a2b,
+ 0x2559, 0x3a30, 0x2565, 0x3a35, 0x2570, 0x3a3a, 0x257c, 0x3a3f,
+ 0x2587, 0x3a45, 0x2592, 0x3a4a, 0x259e, 0x3a4f, 0x25a9, 0x3a54,
+ 0x25b5, 0x3a59, 0x25c0, 0x3a5f, 0x25cc, 0x3a64, 0x25d7, 0x3a69,
+ 0x25e3, 0x3a6e, 0x25ee, 0x3a73, 0x25fa, 0x3a78, 0x2605, 0x3a7d,
+ 0x2611, 0x3a82, 0x261c, 0x3a88, 0x2628, 0x3a8d, 0x2633, 0x3a92,
+ 0x263f, 0x3a97, 0x264a, 0x3a9c, 0x2656, 0x3aa1, 0x2661, 0x3aa6,
+ 0x266d, 0x3aab, 0x2678, 0x3ab0, 0x2684, 0x3ab5, 0x268f, 0x3aba,
+ 0x269b, 0x3abf, 0x26a6, 0x3ac4, 0x26b2, 0x3ac9, 0x26bd, 0x3ace,
+ 0x26c9, 0x3ad3, 0x26d4, 0x3ad8, 0x26e0, 0x3add, 0x26ec, 0x3ae2,
+ 0x26f7, 0x3ae6, 0x2703, 0x3aeb, 0x270e, 0x3af0, 0x271a, 0x3af5,
+ 0x2725, 0x3afa, 0x2731, 0x3aff, 0x273d, 0x3b04, 0x2748, 0x3b09,
+ 0x2754, 0x3b0e, 0x275f, 0x3b12, 0x276b, 0x3b17, 0x2777, 0x3b1c,
+ 0x2782, 0x3b21, 0x278e, 0x3b26, 0x2799, 0x3b2a, 0x27a5, 0x3b2f,
+ 0x27b1, 0x3b34, 0x27bc, 0x3b39, 0x27c8, 0x3b3e, 0x27d3, 0x3b42,
+ 0x27df, 0x3b47, 0x27eb, 0x3b4c, 0x27f6, 0x3b50, 0x2802, 0x3b55,
+ 0x280e, 0x3b5a, 0x2819, 0x3b5f, 0x2825, 0x3b63, 0x2831, 0x3b68,
+ 0x283c, 0x3b6d, 0x2848, 0x3b71, 0x2854, 0x3b76, 0x285f, 0x3b7b,
+ 0x286b, 0x3b7f, 0x2877, 0x3b84, 0x2882, 0x3b88, 0x288e, 0x3b8d,
+ 0x289a, 0x3b92, 0x28a5, 0x3b96, 0x28b1, 0x3b9b, 0x28bd, 0x3b9f,
+ 0x28c9, 0x3ba4, 0x28d4, 0x3ba9, 0x28e0, 0x3bad, 0x28ec, 0x3bb2,
+ 0x28f7, 0x3bb6, 0x2903, 0x3bbb, 0x290f, 0x3bbf, 0x291b, 0x3bc4,
+ 0x2926, 0x3bc8, 0x2932, 0x3bcd, 0x293e, 0x3bd1, 0x294a, 0x3bd6,
+ 0x2955, 0x3bda, 0x2961, 0x3bde, 0x296d, 0x3be3, 0x2979, 0x3be7,
+ 0x2984, 0x3bec, 0x2990, 0x3bf0, 0x299c, 0x3bf5, 0x29a8, 0x3bf9,
+ 0x29b4, 0x3bfd, 0x29bf, 0x3c02, 0x29cb, 0x3c06, 0x29d7, 0x3c0a,
+ 0x29e3, 0x3c0f, 0x29ee, 0x3c13, 0x29fa, 0x3c17, 0x2a06, 0x3c1c,
+ 0x2a12, 0x3c20, 0x2a1e, 0x3c24, 0x2a29, 0x3c29, 0x2a35, 0x3c2d,
+ 0x2a41, 0x3c31, 0x2a4d, 0x3c36, 0x2a59, 0x3c3a, 0x2a65, 0x3c3e,
+ 0x2a70, 0x3c42, 0x2a7c, 0x3c46, 0x2a88, 0x3c4b, 0x2a94, 0x3c4f,
+ 0x2aa0, 0x3c53, 0x2aac, 0x3c57, 0x2ab7, 0x3c5b, 0x2ac3, 0x3c60,
+ 0x2acf, 0x3c64, 0x2adb, 0x3c68, 0x2ae7, 0x3c6c, 0x2af3, 0x3c70,
+ 0x2aff, 0x3c74, 0x2b0a, 0x3c79, 0x2b16, 0x3c7d, 0x2b22, 0x3c81,
+ 0x2b2e, 0x3c85, 0x2b3a, 0x3c89, 0x2b46, 0x3c8d, 0x2b52, 0x3c91,
+ 0x2b5e, 0x3c95, 0x2b6a, 0x3c99, 0x2b75, 0x3c9d, 0x2b81, 0x3ca1,
+ 0x2b8d, 0x3ca5, 0x2b99, 0x3ca9, 0x2ba5, 0x3cad, 0x2bb1, 0x3cb1,
+ 0x2bbd, 0x3cb5, 0x2bc9, 0x3cb9, 0x2bd5, 0x3cbd, 0x2be1, 0x3cc1,
+ 0x2bed, 0x3cc5, 0x2bf9, 0x3cc9, 0x2c05, 0x3ccd, 0x2c10, 0x3cd1,
+ 0x2c1c, 0x3cd5, 0x2c28, 0x3cd9, 0x2c34, 0x3cdd, 0x2c40, 0x3ce0,
+ 0x2c4c, 0x3ce4, 0x2c58, 0x3ce8, 0x2c64, 0x3cec, 0x2c70, 0x3cf0,
+ 0x2c7c, 0x3cf4, 0x2c88, 0x3cf8, 0x2c94, 0x3cfb, 0x2ca0, 0x3cff,
+ 0x2cac, 0x3d03, 0x2cb8, 0x3d07, 0x2cc4, 0x3d0b, 0x2cd0, 0x3d0e,
+ 0x2cdc, 0x3d12, 0x2ce8, 0x3d16, 0x2cf4, 0x3d1a, 0x2d00, 0x3d1d,
+ 0x2d0c, 0x3d21, 0x2d18, 0x3d25, 0x2d24, 0x3d28, 0x2d30, 0x3d2c,
+ 0x2d3c, 0x3d30, 0x2d48, 0x3d34, 0x2d54, 0x3d37, 0x2d60, 0x3d3b,
+ 0x2d6c, 0x3d3f, 0x2d78, 0x3d42, 0x2d84, 0x3d46, 0x2d90, 0x3d49,
+ 0x2d9c, 0x3d4d, 0x2da8, 0x3d51, 0x2db4, 0x3d54, 0x2dc0, 0x3d58,
+ 0x2dcc, 0x3d5b, 0x2dd8, 0x3d5f, 0x2de4, 0x3d63, 0x2df0, 0x3d66,
+ 0x2dfc, 0x3d6a, 0x2e09, 0x3d6d, 0x2e15, 0x3d71, 0x2e21, 0x3d74,
+ 0x2e2d, 0x3d78, 0x2e39, 0x3d7b, 0x2e45, 0x3d7f, 0x2e51, 0x3d82,
+ 0x2e5d, 0x3d86, 0x2e69, 0x3d89, 0x2e75, 0x3d8d, 0x2e81, 0x3d90,
+ 0x2e8d, 0x3d93, 0x2e99, 0x3d97, 0x2ea6, 0x3d9a, 0x2eb2, 0x3d9e,
+ 0x2ebe, 0x3da1, 0x2eca, 0x3da4, 0x2ed6, 0x3da8, 0x2ee2, 0x3dab,
+ 0x2eee, 0x3daf, 0x2efa, 0x3db2, 0x2f06, 0x3db5, 0x2f13, 0x3db9,
+ 0x2f1f, 0x3dbc, 0x2f2b, 0x3dbf, 0x2f37, 0x3dc2, 0x2f43, 0x3dc6,
+ 0x2f4f, 0x3dc9, 0x2f5b, 0x3dcc, 0x2f67, 0x3dd0, 0x2f74, 0x3dd3,
+ 0x2f80, 0x3dd6, 0x2f8c, 0x3dd9, 0x2f98, 0x3ddd, 0x2fa4, 0x3de0,
+ 0x2fb0, 0x3de3, 0x2fbc, 0x3de6, 0x2fc9, 0x3de9, 0x2fd5, 0x3ded,
+ 0x2fe1, 0x3df0, 0x2fed, 0x3df3, 0x2ff9, 0x3df6, 0x3005, 0x3df9,
+ 0x3012, 0x3dfc, 0x301e, 0x3dff, 0x302a, 0x3e03, 0x3036, 0x3e06,
+ 0x3042, 0x3e09, 0x304e, 0x3e0c, 0x305b, 0x3e0f, 0x3067, 0x3e12,
+ 0x3073, 0x3e15, 0x307f, 0x3e18, 0x308b, 0x3e1b, 0x3098, 0x3e1e,
+ 0x30a4, 0x3e21, 0x30b0, 0x3e24, 0x30bc, 0x3e27, 0x30c8, 0x3e2a,
+ 0x30d5, 0x3e2d, 0x30e1, 0x3e30, 0x30ed, 0x3e33, 0x30f9, 0x3e36,
+ 0x3105, 0x3e39, 0x3112, 0x3e3c, 0x311e, 0x3e3f, 0x312a, 0x3e42,
+ 0x3136, 0x3e45, 0x3143, 0x3e48, 0x314f, 0x3e4a, 0x315b, 0x3e4d,
+ 0x3167, 0x3e50, 0x3174, 0x3e53, 0x3180, 0x3e56, 0x318c, 0x3e59,
+ 0x3198, 0x3e5c, 0x31a4, 0x3e5e, 0x31b1, 0x3e61, 0x31bd, 0x3e64,
+ 0x31c9, 0x3e67, 0x31d5, 0x3e6a, 0x31e2, 0x3e6c, 0x31ee, 0x3e6f,
+ 0x31fa, 0x3e72, 0x3207, 0x3e75, 0x3213, 0x3e77, 0x321f, 0x3e7a,
+ 0x322b, 0x3e7d, 0x3238, 0x3e80, 0x3244, 0x3e82, 0x3250, 0x3e85,
+ 0x325c, 0x3e88, 0x3269, 0x3e8a, 0x3275, 0x3e8d, 0x3281, 0x3e90,
+ 0x328e, 0x3e92, 0x329a, 0x3e95, 0x32a6, 0x3e98, 0x32b2, 0x3e9a,
+ 0x32bf, 0x3e9d, 0x32cb, 0x3e9f, 0x32d7, 0x3ea2, 0x32e4, 0x3ea5,
+ 0x32f0, 0x3ea7, 0x32fc, 0x3eaa, 0x3308, 0x3eac, 0x3315, 0x3eaf,
+ 0x3321, 0x3eb1, 0x332d, 0x3eb4, 0x333a, 0x3eb6, 0x3346, 0x3eb9,
+ 0x3352, 0x3ebb, 0x335f, 0x3ebe, 0x336b, 0x3ec0, 0x3377, 0x3ec3,
+ 0x3384, 0x3ec5, 0x3390, 0x3ec8, 0x339c, 0x3eca, 0x33a9, 0x3ecc,
+ 0x33b5, 0x3ecf, 0x33c1, 0x3ed1, 0x33ce, 0x3ed4, 0x33da, 0x3ed6,
+ 0x33e6, 0x3ed8, 0x33f3, 0x3edb, 0x33ff, 0x3edd, 0x340b, 0x3ee0,
+ 0x3418, 0x3ee2, 0x3424, 0x3ee4, 0x3430, 0x3ee7, 0x343d, 0x3ee9,
+ 0x3449, 0x3eeb, 0x3455, 0x3eed, 0x3462, 0x3ef0, 0x346e, 0x3ef2,
+ 0x347b, 0x3ef4, 0x3487, 0x3ef7, 0x3493, 0x3ef9, 0x34a0, 0x3efb,
+ 0x34ac, 0x3efd, 0x34b8, 0x3f00, 0x34c5, 0x3f02, 0x34d1, 0x3f04,
+ 0x34dd, 0x3f06, 0x34ea, 0x3f08, 0x34f6, 0x3f0a, 0x3503, 0x3f0d,
+ 0x350f, 0x3f0f, 0x351b, 0x3f11, 0x3528, 0x3f13, 0x3534, 0x3f15,
+ 0x3540, 0x3f17, 0x354d, 0x3f19, 0x3559, 0x3f1c, 0x3566, 0x3f1e,
+ 0x3572, 0x3f20, 0x357e, 0x3f22, 0x358b, 0x3f24, 0x3597, 0x3f26,
+ 0x35a4, 0x3f28, 0x35b0, 0x3f2a, 0x35bc, 0x3f2c, 0x35c9, 0x3f2e,
+ 0x35d5, 0x3f30, 0x35e2, 0x3f32, 0x35ee, 0x3f34, 0x35fa, 0x3f36,
+ 0x3607, 0x3f38, 0x3613, 0x3f3a, 0x3620, 0x3f3c, 0x362c, 0x3f3e,
+ 0x3639, 0x3f40, 0x3645, 0x3f42, 0x3651, 0x3f43, 0x365e, 0x3f45,
+ 0x366a, 0x3f47, 0x3677, 0x3f49, 0x3683, 0x3f4b, 0x3690, 0x3f4d,
+ 0x369c, 0x3f4f, 0x36a8, 0x3f51, 0x36b5, 0x3f52, 0x36c1, 0x3f54,
+ 0x36ce, 0x3f56, 0x36da, 0x3f58, 0x36e7, 0x3f5a, 0x36f3, 0x3f5b,
+ 0x36ff, 0x3f5d, 0x370c, 0x3f5f, 0x3718, 0x3f61, 0x3725, 0x3f62,
+ 0x3731, 0x3f64, 0x373e, 0x3f66, 0x374a, 0x3f68, 0x3757, 0x3f69,
+ 0x3763, 0x3f6b, 0x376f, 0x3f6d, 0x377c, 0x3f6e, 0x3788, 0x3f70,
+ 0x3795, 0x3f72, 0x37a1, 0x3f73, 0x37ae, 0x3f75, 0x37ba, 0x3f77,
+ 0x37c7, 0x3f78, 0x37d3, 0x3f7a, 0x37e0, 0x3f7b, 0x37ec, 0x3f7d,
+ 0x37f9, 0x3f7f, 0x3805, 0x3f80, 0x3811, 0x3f82, 0x381e, 0x3f83,
+ 0x382a, 0x3f85, 0x3837, 0x3f86, 0x3843, 0x3f88, 0x3850, 0x3f89,
+ 0x385c, 0x3f8b, 0x3869, 0x3f8c, 0x3875, 0x3f8e, 0x3882, 0x3f8f,
+ 0x388e, 0x3f91, 0x389b, 0x3f92, 0x38a7, 0x3f94, 0x38b4, 0x3f95,
+ 0x38c0, 0x3f97, 0x38cd, 0x3f98, 0x38d9, 0x3f99, 0x38e6, 0x3f9b,
+ 0x38f2, 0x3f9c, 0x38ff, 0x3f9e, 0x390b, 0x3f9f, 0x3918, 0x3fa0,
+ 0x3924, 0x3fa2, 0x3931, 0x3fa3, 0x393d, 0x3fa4, 0x394a, 0x3fa6,
+ 0x3956, 0x3fa7, 0x3963, 0x3fa8, 0x396f, 0x3faa, 0x397c, 0x3fab,
+ 0x3988, 0x3fac, 0x3995, 0x3fad, 0x39a1, 0x3faf, 0x39ae, 0x3fb0,
+ 0x39ba, 0x3fb1, 0x39c7, 0x3fb2, 0x39d3, 0x3fb4, 0x39e0, 0x3fb5,
+ 0x39ec, 0x3fb6, 0x39f9, 0x3fb7, 0x3a05, 0x3fb8, 0x3a12, 0x3fb9,
+ 0x3a1e, 0x3fbb, 0x3a2b, 0x3fbc, 0x3a37, 0x3fbd, 0x3a44, 0x3fbe,
+ 0x3a50, 0x3fbf, 0x3a5d, 0x3fc0, 0x3a69, 0x3fc1, 0x3a76, 0x3fc3,
+ 0x3a82, 0x3fc4, 0x3a8f, 0x3fc5, 0x3a9b, 0x3fc6, 0x3aa8, 0x3fc7,
+ 0x3ab4, 0x3fc8, 0x3ac1, 0x3fc9, 0x3acd, 0x3fca, 0x3ada, 0x3fcb,
+ 0x3ae6, 0x3fcc, 0x3af3, 0x3fcd, 0x3b00, 0x3fce, 0x3b0c, 0x3fcf,
+ 0x3b19, 0x3fd0, 0x3b25, 0x3fd1, 0x3b32, 0x3fd2, 0x3b3e, 0x3fd3,
+ 0x3b4b, 0x3fd4, 0x3b57, 0x3fd5, 0x3b64, 0x3fd5, 0x3b70, 0x3fd6,
+ 0x3b7d, 0x3fd7, 0x3b89, 0x3fd8, 0x3b96, 0x3fd9, 0x3ba2, 0x3fda,
+ 0x3baf, 0x3fdb, 0x3bbc, 0x3fdc, 0x3bc8, 0x3fdc, 0x3bd5, 0x3fdd,
+ 0x3be1, 0x3fde, 0x3bee, 0x3fdf, 0x3bfa, 0x3fe0, 0x3c07, 0x3fe0,
+ 0x3c13, 0x3fe1, 0x3c20, 0x3fe2, 0x3c2c, 0x3fe3, 0x3c39, 0x3fe3,
+ 0x3c45, 0x3fe4, 0x3c52, 0x3fe5, 0x3c5f, 0x3fe6, 0x3c6b, 0x3fe6,
+ 0x3c78, 0x3fe7, 0x3c84, 0x3fe8, 0x3c91, 0x3fe8, 0x3c9d, 0x3fe9,
+ 0x3caa, 0x3fea, 0x3cb6, 0x3fea, 0x3cc3, 0x3feb, 0x3cd0, 0x3fec,
+ 0x3cdc, 0x3fec, 0x3ce9, 0x3fed, 0x3cf5, 0x3fed, 0x3d02, 0x3fee,
+ 0x3d0e, 0x3fef, 0x3d1b, 0x3fef, 0x3d27, 0x3ff0, 0x3d34, 0x3ff0,
+ 0x3d40, 0x3ff1, 0x3d4d, 0x3ff1, 0x3d5a, 0x3ff2, 0x3d66, 0x3ff2,
+ 0x3d73, 0x3ff3, 0x3d7f, 0x3ff3, 0x3d8c, 0x3ff4, 0x3d98, 0x3ff4,
+ 0x3da5, 0x3ff5, 0x3db2, 0x3ff5, 0x3dbe, 0x3ff6, 0x3dcb, 0x3ff6,
+ 0x3dd7, 0x3ff7, 0x3de4, 0x3ff7, 0x3df0, 0x3ff7, 0x3dfd, 0x3ff8,
+ 0x3e09, 0x3ff8, 0x3e16, 0x3ff9, 0x3e23, 0x3ff9, 0x3e2f, 0x3ff9,
+ 0x3e3c, 0x3ffa, 0x3e48, 0x3ffa, 0x3e55, 0x3ffa, 0x3e61, 0x3ffb,
+ 0x3e6e, 0x3ffb, 0x3e7a, 0x3ffb, 0x3e87, 0x3ffc, 0x3e94, 0x3ffc,
+ 0x3ea0, 0x3ffc, 0x3ead, 0x3ffc, 0x3eb9, 0x3ffd, 0x3ec6, 0x3ffd,
+ 0x3ed2, 0x3ffd, 0x3edf, 0x3ffd, 0x3eec, 0x3ffe, 0x3ef8, 0x3ffe,
+ 0x3f05, 0x3ffe, 0x3f11, 0x3ffe, 0x3f1e, 0x3ffe, 0x3f2a, 0x3fff,
+ 0x3f37, 0x3fff, 0x3f44, 0x3fff, 0x3f50, 0x3fff, 0x3f5d, 0x3fff,
+ 0x3f69, 0x3fff, 0x3f76, 0x3fff, 0x3f82, 0x4000, 0x3f8f, 0x4000,
+ 0x3f9b, 0x4000, 0x3fa8, 0x4000, 0x3fb5, 0x4000, 0x3fc1, 0x4000,
+ 0x3fce, 0x4000, 0x3fda, 0x4000, 0x3fe7, 0x4000, 0x3ff3, 0x4000,
+};
+
+/**
+* \par
+* Generation of real_CoefB array:
+* \par
+* n = 4096
+* <pre>for (i = 0; i < n; i++)
+* {
+* pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+* pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* } </pre>
+* \par
+* Convert to fixed point Q15 format
+* round(pBTable[i] * pow(2, 15))
+*
+*/
+
+static const q15_t ALIGN4 realCoefBQ15[8192] = {
+ 0x4000, 0x4000, 0x400d, 0x4000, 0x4019, 0x4000, 0x4026, 0x4000,
+ 0x4032, 0x4000, 0x403f, 0x4000, 0x404b, 0x4000, 0x4058, 0x4000,
+ 0x4065, 0x4000, 0x4071, 0x4000, 0x407e, 0x4000, 0x408a, 0x3fff,
+ 0x4097, 0x3fff, 0x40a3, 0x3fff, 0x40b0, 0x3fff, 0x40bc, 0x3fff,
+ 0x40c9, 0x3fff, 0x40d6, 0x3fff, 0x40e2, 0x3ffe, 0x40ef, 0x3ffe,
+ 0x40fb, 0x3ffe, 0x4108, 0x3ffe, 0x4114, 0x3ffe, 0x4121, 0x3ffd,
+ 0x412e, 0x3ffd, 0x413a, 0x3ffd, 0x4147, 0x3ffd, 0x4153, 0x3ffc,
+ 0x4160, 0x3ffc, 0x416c, 0x3ffc, 0x4179, 0x3ffc, 0x4186, 0x3ffb,
+ 0x4192, 0x3ffb, 0x419f, 0x3ffb, 0x41ab, 0x3ffa, 0x41b8, 0x3ffa,
+ 0x41c4, 0x3ffa, 0x41d1, 0x3ff9, 0x41dd, 0x3ff9, 0x41ea, 0x3ff9,
+ 0x41f7, 0x3ff8, 0x4203, 0x3ff8, 0x4210, 0x3ff7, 0x421c, 0x3ff7,
+ 0x4229, 0x3ff7, 0x4235, 0x3ff6, 0x4242, 0x3ff6, 0x424e, 0x3ff5,
+ 0x425b, 0x3ff5, 0x4268, 0x3ff4, 0x4274, 0x3ff4, 0x4281, 0x3ff3,
+ 0x428d, 0x3ff3, 0x429a, 0x3ff2, 0x42a6, 0x3ff2, 0x42b3, 0x3ff1,
+ 0x42c0, 0x3ff1, 0x42cc, 0x3ff0, 0x42d9, 0x3ff0, 0x42e5, 0x3fef,
+ 0x42f2, 0x3fef, 0x42fe, 0x3fee, 0x430b, 0x3fed, 0x4317, 0x3fed,
+ 0x4324, 0x3fec, 0x4330, 0x3fec, 0x433d, 0x3feb, 0x434a, 0x3fea,
+ 0x4356, 0x3fea, 0x4363, 0x3fe9, 0x436f, 0x3fe8, 0x437c, 0x3fe8,
+ 0x4388, 0x3fe7, 0x4395, 0x3fe6, 0x43a1, 0x3fe6, 0x43ae, 0x3fe5,
+ 0x43bb, 0x3fe4, 0x43c7, 0x3fe3, 0x43d4, 0x3fe3, 0x43e0, 0x3fe2,
+ 0x43ed, 0x3fe1, 0x43f9, 0x3fe0, 0x4406, 0x3fe0, 0x4412, 0x3fdf,
+ 0x441f, 0x3fde, 0x442b, 0x3fdd, 0x4438, 0x3fdc, 0x4444, 0x3fdc,
+ 0x4451, 0x3fdb, 0x445e, 0x3fda, 0x446a, 0x3fd9, 0x4477, 0x3fd8,
+ 0x4483, 0x3fd7, 0x4490, 0x3fd6, 0x449c, 0x3fd5, 0x44a9, 0x3fd5,
+ 0x44b5, 0x3fd4, 0x44c2, 0x3fd3, 0x44ce, 0x3fd2, 0x44db, 0x3fd1,
+ 0x44e7, 0x3fd0, 0x44f4, 0x3fcf, 0x4500, 0x3fce, 0x450d, 0x3fcd,
+ 0x451a, 0x3fcc, 0x4526, 0x3fcb, 0x4533, 0x3fca, 0x453f, 0x3fc9,
+ 0x454c, 0x3fc8, 0x4558, 0x3fc7, 0x4565, 0x3fc6, 0x4571, 0x3fc5,
+ 0x457e, 0x3fc4, 0x458a, 0x3fc3, 0x4597, 0x3fc1, 0x45a3, 0x3fc0,
+ 0x45b0, 0x3fbf, 0x45bc, 0x3fbe, 0x45c9, 0x3fbd, 0x45d5, 0x3fbc,
+ 0x45e2, 0x3fbb, 0x45ee, 0x3fb9, 0x45fb, 0x3fb8, 0x4607, 0x3fb7,
+ 0x4614, 0x3fb6, 0x4620, 0x3fb5, 0x462d, 0x3fb4, 0x4639, 0x3fb2,
+ 0x4646, 0x3fb1, 0x4652, 0x3fb0, 0x465f, 0x3faf, 0x466b, 0x3fad,
+ 0x4678, 0x3fac, 0x4684, 0x3fab, 0x4691, 0x3faa, 0x469d, 0x3fa8,
+ 0x46aa, 0x3fa7, 0x46b6, 0x3fa6, 0x46c3, 0x3fa4, 0x46cf, 0x3fa3,
+ 0x46dc, 0x3fa2, 0x46e8, 0x3fa0, 0x46f5, 0x3f9f, 0x4701, 0x3f9e,
+ 0x470e, 0x3f9c, 0x471a, 0x3f9b, 0x4727, 0x3f99, 0x4733, 0x3f98,
+ 0x4740, 0x3f97, 0x474c, 0x3f95, 0x4759, 0x3f94, 0x4765, 0x3f92,
+ 0x4772, 0x3f91, 0x477e, 0x3f8f, 0x478b, 0x3f8e, 0x4797, 0x3f8c,
+ 0x47a4, 0x3f8b, 0x47b0, 0x3f89, 0x47bd, 0x3f88, 0x47c9, 0x3f86,
+ 0x47d6, 0x3f85, 0x47e2, 0x3f83, 0x47ef, 0x3f82, 0x47fb, 0x3f80,
+ 0x4807, 0x3f7f, 0x4814, 0x3f7d, 0x4820, 0x3f7b, 0x482d, 0x3f7a,
+ 0x4839, 0x3f78, 0x4846, 0x3f77, 0x4852, 0x3f75, 0x485f, 0x3f73,
+ 0x486b, 0x3f72, 0x4878, 0x3f70, 0x4884, 0x3f6e, 0x4891, 0x3f6d,
+ 0x489d, 0x3f6b, 0x48a9, 0x3f69, 0x48b6, 0x3f68, 0x48c2, 0x3f66,
+ 0x48cf, 0x3f64, 0x48db, 0x3f62, 0x48e8, 0x3f61, 0x48f4, 0x3f5f,
+ 0x4901, 0x3f5d, 0x490d, 0x3f5b, 0x4919, 0x3f5a, 0x4926, 0x3f58,
+ 0x4932, 0x3f56, 0x493f, 0x3f54, 0x494b, 0x3f52, 0x4958, 0x3f51,
+ 0x4964, 0x3f4f, 0x4970, 0x3f4d, 0x497d, 0x3f4b, 0x4989, 0x3f49,
+ 0x4996, 0x3f47, 0x49a2, 0x3f45, 0x49af, 0x3f43, 0x49bb, 0x3f42,
+ 0x49c7, 0x3f40, 0x49d4, 0x3f3e, 0x49e0, 0x3f3c, 0x49ed, 0x3f3a,
+ 0x49f9, 0x3f38, 0x4a06, 0x3f36, 0x4a12, 0x3f34, 0x4a1e, 0x3f32,
+ 0x4a2b, 0x3f30, 0x4a37, 0x3f2e, 0x4a44, 0x3f2c, 0x4a50, 0x3f2a,
+ 0x4a5c, 0x3f28, 0x4a69, 0x3f26, 0x4a75, 0x3f24, 0x4a82, 0x3f22,
+ 0x4a8e, 0x3f20, 0x4a9a, 0x3f1e, 0x4aa7, 0x3f1c, 0x4ab3, 0x3f19,
+ 0x4ac0, 0x3f17, 0x4acc, 0x3f15, 0x4ad8, 0x3f13, 0x4ae5, 0x3f11,
+ 0x4af1, 0x3f0f, 0x4afd, 0x3f0d, 0x4b0a, 0x3f0a, 0x4b16, 0x3f08,
+ 0x4b23, 0x3f06, 0x4b2f, 0x3f04, 0x4b3b, 0x3f02, 0x4b48, 0x3f00,
+ 0x4b54, 0x3efd, 0x4b60, 0x3efb, 0x4b6d, 0x3ef9, 0x4b79, 0x3ef7,
+ 0x4b85, 0x3ef4, 0x4b92, 0x3ef2, 0x4b9e, 0x3ef0, 0x4bab, 0x3eed,
+ 0x4bb7, 0x3eeb, 0x4bc3, 0x3ee9, 0x4bd0, 0x3ee7, 0x4bdc, 0x3ee4,
+ 0x4be8, 0x3ee2, 0x4bf5, 0x3ee0, 0x4c01, 0x3edd, 0x4c0d, 0x3edb,
+ 0x4c1a, 0x3ed8, 0x4c26, 0x3ed6, 0x4c32, 0x3ed4, 0x4c3f, 0x3ed1,
+ 0x4c4b, 0x3ecf, 0x4c57, 0x3ecc, 0x4c64, 0x3eca, 0x4c70, 0x3ec8,
+ 0x4c7c, 0x3ec5, 0x4c89, 0x3ec3, 0x4c95, 0x3ec0, 0x4ca1, 0x3ebe,
+ 0x4cae, 0x3ebb, 0x4cba, 0x3eb9, 0x4cc6, 0x3eb6, 0x4cd3, 0x3eb4,
+ 0x4cdf, 0x3eb1, 0x4ceb, 0x3eaf, 0x4cf8, 0x3eac, 0x4d04, 0x3eaa,
+ 0x4d10, 0x3ea7, 0x4d1c, 0x3ea5, 0x4d29, 0x3ea2, 0x4d35, 0x3e9f,
+ 0x4d41, 0x3e9d, 0x4d4e, 0x3e9a, 0x4d5a, 0x3e98, 0x4d66, 0x3e95,
+ 0x4d72, 0x3e92, 0x4d7f, 0x3e90, 0x4d8b, 0x3e8d, 0x4d97, 0x3e8a,
+ 0x4da4, 0x3e88, 0x4db0, 0x3e85, 0x4dbc, 0x3e82, 0x4dc8, 0x3e80,
+ 0x4dd5, 0x3e7d, 0x4de1, 0x3e7a, 0x4ded, 0x3e77, 0x4df9, 0x3e75,
+ 0x4e06, 0x3e72, 0x4e12, 0x3e6f, 0x4e1e, 0x3e6c, 0x4e2b, 0x3e6a,
+ 0x4e37, 0x3e67, 0x4e43, 0x3e64, 0x4e4f, 0x3e61, 0x4e5c, 0x3e5e,
+ 0x4e68, 0x3e5c, 0x4e74, 0x3e59, 0x4e80, 0x3e56, 0x4e8c, 0x3e53,
+ 0x4e99, 0x3e50, 0x4ea5, 0x3e4d, 0x4eb1, 0x3e4a, 0x4ebd, 0x3e48,
+ 0x4eca, 0x3e45, 0x4ed6, 0x3e42, 0x4ee2, 0x3e3f, 0x4eee, 0x3e3c,
+ 0x4efb, 0x3e39, 0x4f07, 0x3e36, 0x4f13, 0x3e33, 0x4f1f, 0x3e30,
+ 0x4f2b, 0x3e2d, 0x4f38, 0x3e2a, 0x4f44, 0x3e27, 0x4f50, 0x3e24,
+ 0x4f5c, 0x3e21, 0x4f68, 0x3e1e, 0x4f75, 0x3e1b, 0x4f81, 0x3e18,
+ 0x4f8d, 0x3e15, 0x4f99, 0x3e12, 0x4fa5, 0x3e0f, 0x4fb2, 0x3e0c,
+ 0x4fbe, 0x3e09, 0x4fca, 0x3e06, 0x4fd6, 0x3e03, 0x4fe2, 0x3dff,
+ 0x4fee, 0x3dfc, 0x4ffb, 0x3df9, 0x5007, 0x3df6, 0x5013, 0x3df3,
+ 0x501f, 0x3df0, 0x502b, 0x3ded, 0x5037, 0x3de9, 0x5044, 0x3de6,
+ 0x5050, 0x3de3, 0x505c, 0x3de0, 0x5068, 0x3ddd, 0x5074, 0x3dd9,
+ 0x5080, 0x3dd6, 0x508c, 0x3dd3, 0x5099, 0x3dd0, 0x50a5, 0x3dcc,
+ 0x50b1, 0x3dc9, 0x50bd, 0x3dc6, 0x50c9, 0x3dc2, 0x50d5, 0x3dbf,
+ 0x50e1, 0x3dbc, 0x50ed, 0x3db9, 0x50fa, 0x3db5, 0x5106, 0x3db2,
+ 0x5112, 0x3daf, 0x511e, 0x3dab, 0x512a, 0x3da8, 0x5136, 0x3da4,
+ 0x5142, 0x3da1, 0x514e, 0x3d9e, 0x515a, 0x3d9a, 0x5167, 0x3d97,
+ 0x5173, 0x3d93, 0x517f, 0x3d90, 0x518b, 0x3d8d, 0x5197, 0x3d89,
+ 0x51a3, 0x3d86, 0x51af, 0x3d82, 0x51bb, 0x3d7f, 0x51c7, 0x3d7b,
+ 0x51d3, 0x3d78, 0x51df, 0x3d74, 0x51eb, 0x3d71, 0x51f7, 0x3d6d,
+ 0x5204, 0x3d6a, 0x5210, 0x3d66, 0x521c, 0x3d63, 0x5228, 0x3d5f,
+ 0x5234, 0x3d5b, 0x5240, 0x3d58, 0x524c, 0x3d54, 0x5258, 0x3d51,
+ 0x5264, 0x3d4d, 0x5270, 0x3d49, 0x527c, 0x3d46, 0x5288, 0x3d42,
+ 0x5294, 0x3d3f, 0x52a0, 0x3d3b, 0x52ac, 0x3d37, 0x52b8, 0x3d34,
+ 0x52c4, 0x3d30, 0x52d0, 0x3d2c, 0x52dc, 0x3d28, 0x52e8, 0x3d25,
+ 0x52f4, 0x3d21, 0x5300, 0x3d1d, 0x530c, 0x3d1a, 0x5318, 0x3d16,
+ 0x5324, 0x3d12, 0x5330, 0x3d0e, 0x533c, 0x3d0b, 0x5348, 0x3d07,
+ 0x5354, 0x3d03, 0x5360, 0x3cff, 0x536c, 0x3cfb, 0x5378, 0x3cf8,
+ 0x5384, 0x3cf4, 0x5390, 0x3cf0, 0x539c, 0x3cec, 0x53a8, 0x3ce8,
+ 0x53b4, 0x3ce4, 0x53c0, 0x3ce0, 0x53cc, 0x3cdd, 0x53d8, 0x3cd9,
+ 0x53e4, 0x3cd5, 0x53f0, 0x3cd1, 0x53fb, 0x3ccd, 0x5407, 0x3cc9,
+ 0x5413, 0x3cc5, 0x541f, 0x3cc1, 0x542b, 0x3cbd, 0x5437, 0x3cb9,
+ 0x5443, 0x3cb5, 0x544f, 0x3cb1, 0x545b, 0x3cad, 0x5467, 0x3ca9,
+ 0x5473, 0x3ca5, 0x547f, 0x3ca1, 0x548b, 0x3c9d, 0x5496, 0x3c99,
+ 0x54a2, 0x3c95, 0x54ae, 0x3c91, 0x54ba, 0x3c8d, 0x54c6, 0x3c89,
+ 0x54d2, 0x3c85, 0x54de, 0x3c81, 0x54ea, 0x3c7d, 0x54f6, 0x3c79,
+ 0x5501, 0x3c74, 0x550d, 0x3c70, 0x5519, 0x3c6c, 0x5525, 0x3c68,
+ 0x5531, 0x3c64, 0x553d, 0x3c60, 0x5549, 0x3c5b, 0x5554, 0x3c57,
+ 0x5560, 0x3c53, 0x556c, 0x3c4f, 0x5578, 0x3c4b, 0x5584, 0x3c46,
+ 0x5590, 0x3c42, 0x559b, 0x3c3e, 0x55a7, 0x3c3a, 0x55b3, 0x3c36,
+ 0x55bf, 0x3c31, 0x55cb, 0x3c2d, 0x55d7, 0x3c29, 0x55e2, 0x3c24,
+ 0x55ee, 0x3c20, 0x55fa, 0x3c1c, 0x5606, 0x3c17, 0x5612, 0x3c13,
+ 0x561d, 0x3c0f, 0x5629, 0x3c0a, 0x5635, 0x3c06, 0x5641, 0x3c02,
+ 0x564c, 0x3bfd, 0x5658, 0x3bf9, 0x5664, 0x3bf5, 0x5670, 0x3bf0,
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+ 0x56da, 0x3bc8, 0x56e5, 0x3bc4, 0x56f1, 0x3bbf, 0x56fd, 0x3bbb,
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+ 0x5737, 0x3ba4, 0x5743, 0x3b9f, 0x574f, 0x3b9b, 0x575b, 0x3b96,
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+ 0x57f2, 0x3b5a, 0x57fe, 0x3b55, 0x580a, 0x3b50, 0x5815, 0x3b4c,
+ 0x5821, 0x3b47, 0x582d, 0x3b42, 0x5838, 0x3b3e, 0x5844, 0x3b39,
+ 0x584f, 0x3b34, 0x585b, 0x3b2f, 0x5867, 0x3b2a, 0x5872, 0x3b26,
+ 0x587e, 0x3b21, 0x5889, 0x3b1c, 0x5895, 0x3b17, 0x58a1, 0x3b12,
+ 0x58ac, 0x3b0e, 0x58b8, 0x3b09, 0x58c3, 0x3b04, 0x58cf, 0x3aff,
+ 0x58db, 0x3afa, 0x58e6, 0x3af5, 0x58f2, 0x3af0, 0x58fd, 0x3aeb,
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+ 0x59c1, 0x3a97, 0x59cd, 0x3a92, 0x59d8, 0x3a8d, 0x59e4, 0x3a88,
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+ 0x5b02, 0x3a06, 0x5b0d, 0x3a00, 0x5b19, 0x39fb, 0x5b24, 0x39f6,
+ 0x5b30, 0x39f0, 0x5b3b, 0x39eb, 0x5b46, 0x39e6, 0x5b52, 0x39e0,
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+ 0x70d8, 0x295b, 0x70e0, 0x2951, 0x70e8, 0x2948, 0x70f0, 0x293e,
+ 0x70f9, 0x2935, 0x7101, 0x292b, 0x7109, 0x2921, 0x7111, 0x2918,
+ 0x7119, 0x290e, 0x7121, 0x2904, 0x7129, 0x28fb, 0x7131, 0x28f1,
+ 0x7139, 0x28e7, 0x7141, 0x28de, 0x7149, 0x28d4, 0x7151, 0x28ca,
+ 0x7159, 0x28c1, 0x7161, 0x28b7, 0x7169, 0x28ad, 0x7171, 0x28a4,
+ 0x7179, 0x289a, 0x7181, 0x2890, 0x7189, 0x2886, 0x7191, 0x287d,
+ 0x7199, 0x2873, 0x71a1, 0x2869, 0x71a9, 0x2860, 0x71b1, 0x2856,
+ 0x71b9, 0x284c, 0x71c0, 0x2842, 0x71c8, 0x2838, 0x71d0, 0x282f,
+ 0x71d8, 0x2825, 0x71e0, 0x281b, 0x71e8, 0x2811, 0x71f0, 0x2808,
+ 0x71f8, 0x27fe, 0x71ff, 0x27f4, 0x7207, 0x27ea, 0x720f, 0x27e0,
+ 0x7217, 0x27d6, 0x721f, 0x27cd, 0x7227, 0x27c3, 0x722e, 0x27b9,
+ 0x7236, 0x27af, 0x723e, 0x27a5, 0x7246, 0x279b, 0x724e, 0x2791,
+ 0x7255, 0x2788, 0x725d, 0x277e, 0x7265, 0x2774, 0x726d, 0x276a,
+ 0x7274, 0x2760, 0x727c, 0x2756, 0x7284, 0x274c, 0x728b, 0x2742,
+ 0x7293, 0x2738, 0x729b, 0x272e, 0x72a3, 0x2724, 0x72aa, 0x271a,
+ 0x72b2, 0x2711, 0x72ba, 0x2707, 0x72c1, 0x26fd, 0x72c9, 0x26f3,
+ 0x72d0, 0x26e9, 0x72d8, 0x26df, 0x72e0, 0x26d5, 0x72e7, 0x26cb,
+ 0x72ef, 0x26c1, 0x72f7, 0x26b7, 0x72fe, 0x26ad, 0x7306, 0x26a3,
+ 0x730d, 0x2699, 0x7315, 0x268f, 0x731d, 0x2685, 0x7324, 0x267b,
+ 0x732c, 0x2671, 0x7333, 0x2666, 0x733b, 0x265c, 0x7342, 0x2652,
+ 0x734a, 0x2648, 0x7351, 0x263e, 0x7359, 0x2634, 0x7360, 0x262a,
+ 0x7368, 0x2620, 0x736f, 0x2616, 0x7377, 0x260c, 0x737e, 0x2602,
+ 0x7386, 0x25f8, 0x738d, 0x25ed, 0x7395, 0x25e3, 0x739c, 0x25d9,
+ 0x73a3, 0x25cf, 0x73ab, 0x25c5, 0x73b2, 0x25bb, 0x73ba, 0x25b1,
+ 0x73c1, 0x25a6, 0x73c8, 0x259c, 0x73d0, 0x2592, 0x73d7, 0x2588,
+ 0x73df, 0x257e, 0x73e6, 0x2574, 0x73ed, 0x2569, 0x73f5, 0x255f,
+ 0x73fc, 0x2555, 0x7403, 0x254b, 0x740b, 0x2541, 0x7412, 0x2536,
+ 0x7419, 0x252c, 0x7420, 0x2522, 0x7428, 0x2518, 0x742f, 0x250d,
+ 0x7436, 0x2503, 0x743e, 0x24f9, 0x7445, 0x24ef, 0x744c, 0x24e4,
+ 0x7453, 0x24da, 0x745b, 0x24d0, 0x7462, 0x24c5, 0x7469, 0x24bb,
+ 0x7470, 0x24b1, 0x7477, 0x24a7, 0x747f, 0x249c, 0x7486, 0x2492,
+ 0x748d, 0x2488, 0x7494, 0x247d, 0x749b, 0x2473, 0x74a2, 0x2469,
+ 0x74aa, 0x245e, 0x74b1, 0x2454, 0x74b8, 0x244a, 0x74bf, 0x243f,
+ 0x74c6, 0x2435, 0x74cd, 0x242b, 0x74d4, 0x2420, 0x74db, 0x2416,
+ 0x74e2, 0x240b, 0x74ea, 0x2401, 0x74f1, 0x23f7, 0x74f8, 0x23ec,
+ 0x74ff, 0x23e2, 0x7506, 0x23d7, 0x750d, 0x23cd, 0x7514, 0x23c3,
+ 0x751b, 0x23b8, 0x7522, 0x23ae, 0x7529, 0x23a3, 0x7530, 0x2399,
+ 0x7537, 0x238e, 0x753e, 0x2384, 0x7545, 0x237a, 0x754c, 0x236f,
+ 0x7553, 0x2365, 0x755a, 0x235a, 0x7561, 0x2350, 0x7567, 0x2345,
+ 0x756e, 0x233b, 0x7575, 0x2330, 0x757c, 0x2326, 0x7583, 0x231b,
+ 0x758a, 0x2311, 0x7591, 0x2306, 0x7598, 0x22fc, 0x759f, 0x22f1,
+ 0x75a5, 0x22e7, 0x75ac, 0x22dc, 0x75b3, 0x22d2, 0x75ba, 0x22c7,
+ 0x75c1, 0x22bc, 0x75c8, 0x22b2, 0x75ce, 0x22a7, 0x75d5, 0x229d,
+ 0x75dc, 0x2292, 0x75e3, 0x2288, 0x75ea, 0x227d, 0x75f0, 0x2272,
+ 0x75f7, 0x2268, 0x75fe, 0x225d, 0x7605, 0x2253, 0x760b, 0x2248,
+ 0x7612, 0x223d, 0x7619, 0x2233, 0x7620, 0x2228, 0x7626, 0x221e,
+ 0x762d, 0x2213, 0x7634, 0x2208, 0x763a, 0x21fe, 0x7641, 0x21f3,
+ 0x7648, 0x21e8, 0x764e, 0x21de, 0x7655, 0x21d3, 0x765c, 0x21c8,
+ 0x7662, 0x21be, 0x7669, 0x21b3, 0x766f, 0x21a8, 0x7676, 0x219e,
+ 0x767d, 0x2193, 0x7683, 0x2188, 0x768a, 0x217d, 0x7690, 0x2173,
+ 0x7697, 0x2168, 0x769d, 0x215d, 0x76a4, 0x2153, 0x76ab, 0x2148,
+ 0x76b1, 0x213d, 0x76b8, 0x2132, 0x76be, 0x2128, 0x76c5, 0x211d,
+ 0x76cb, 0x2112, 0x76d2, 0x2107, 0x76d8, 0x20fd, 0x76df, 0x20f2,
+ 0x76e5, 0x20e7, 0x76eb, 0x20dc, 0x76f2, 0x20d1, 0x76f8, 0x20c7,
+ 0x76ff, 0x20bc, 0x7705, 0x20b1, 0x770c, 0x20a6, 0x7712, 0x209b,
+ 0x7718, 0x2091, 0x771f, 0x2086, 0x7725, 0x207b, 0x772c, 0x2070,
+ 0x7732, 0x2065, 0x7738, 0x205b, 0x773f, 0x2050, 0x7745, 0x2045,
+ 0x774b, 0x203a, 0x7752, 0x202f, 0x7758, 0x2024, 0x775e, 0x2019,
+ 0x7765, 0x200f, 0x776b, 0x2004, 0x7771, 0x1ff9, 0x7777, 0x1fee,
+ 0x777e, 0x1fe3, 0x7784, 0x1fd8, 0x778a, 0x1fcd, 0x7790, 0x1fc2,
+ 0x7797, 0x1fb7, 0x779d, 0x1fac, 0x77a3, 0x1fa2, 0x77a9, 0x1f97,
+ 0x77b0, 0x1f8c, 0x77b6, 0x1f81, 0x77bc, 0x1f76, 0x77c2, 0x1f6b,
+ 0x77c8, 0x1f60, 0x77ce, 0x1f55, 0x77d5, 0x1f4a, 0x77db, 0x1f3f,
+ 0x77e1, 0x1f34, 0x77e7, 0x1f29, 0x77ed, 0x1f1e, 0x77f3, 0x1f13,
+ 0x77f9, 0x1f08, 0x77ff, 0x1efd, 0x7805, 0x1ef2, 0x780b, 0x1ee7,
+ 0x7812, 0x1edc, 0x7818, 0x1ed1, 0x781e, 0x1ec6, 0x7824, 0x1ebb,
+ 0x782a, 0x1eb0, 0x7830, 0x1ea5, 0x7836, 0x1e9a, 0x783c, 0x1e8f,
+ 0x7842, 0x1e84, 0x7848, 0x1e79, 0x784e, 0x1e6e, 0x7854, 0x1e63,
+ 0x785a, 0x1e58, 0x7860, 0x1e4d, 0x7866, 0x1e42, 0x786b, 0x1e36,
+ 0x7871, 0x1e2b, 0x7877, 0x1e20, 0x787d, 0x1e15, 0x7883, 0x1e0a,
+ 0x7889, 0x1dff, 0x788f, 0x1df4, 0x7895, 0x1de9, 0x789b, 0x1dde,
+ 0x78a1, 0x1dd3, 0x78a6, 0x1dc7, 0x78ac, 0x1dbc, 0x78b2, 0x1db1,
+ 0x78b8, 0x1da6, 0x78be, 0x1d9b, 0x78c3, 0x1d90, 0x78c9, 0x1d85,
+ 0x78cf, 0x1d79, 0x78d5, 0x1d6e, 0x78db, 0x1d63, 0x78e0, 0x1d58,
+ 0x78e6, 0x1d4d, 0x78ec, 0x1d42, 0x78f2, 0x1d36, 0x78f7, 0x1d2b,
+ 0x78fd, 0x1d20, 0x7903, 0x1d15, 0x7909, 0x1d0a, 0x790e, 0x1cff,
+ 0x7914, 0x1cf3, 0x791a, 0x1ce8, 0x791f, 0x1cdd, 0x7925, 0x1cd2,
+ 0x792b, 0x1cc6, 0x7930, 0x1cbb, 0x7936, 0x1cb0, 0x793b, 0x1ca5,
+ 0x7941, 0x1c99, 0x7947, 0x1c8e, 0x794c, 0x1c83, 0x7952, 0x1c78,
+ 0x7958, 0x1c6c, 0x795d, 0x1c61, 0x7963, 0x1c56, 0x7968, 0x1c4b,
+ 0x796e, 0x1c3f, 0x7973, 0x1c34, 0x7979, 0x1c29, 0x797e, 0x1c1e,
+ 0x7984, 0x1c12, 0x7989, 0x1c07, 0x798f, 0x1bfc, 0x7994, 0x1bf0,
+ 0x799a, 0x1be5, 0x799f, 0x1bda, 0x79a5, 0x1bce, 0x79aa, 0x1bc3,
+ 0x79b0, 0x1bb8, 0x79b5, 0x1bac, 0x79bb, 0x1ba1, 0x79c0, 0x1b96,
+ 0x79c5, 0x1b8a, 0x79cb, 0x1b7f, 0x79d0, 0x1b74, 0x79d6, 0x1b68,
+ 0x79db, 0x1b5d, 0x79e0, 0x1b52, 0x79e6, 0x1b46, 0x79eb, 0x1b3b,
+ 0x79f0, 0x1b30, 0x79f6, 0x1b24, 0x79fb, 0x1b19, 0x7a00, 0x1b0d,
+ 0x7a06, 0x1b02, 0x7a0b, 0x1af7, 0x7a10, 0x1aeb, 0x7a16, 0x1ae0,
+ 0x7a1b, 0x1ad4, 0x7a20, 0x1ac9, 0x7a25, 0x1abe, 0x7a2b, 0x1ab2,
+ 0x7a30, 0x1aa7, 0x7a35, 0x1a9b, 0x7a3a, 0x1a90, 0x7a3f, 0x1a84,
+ 0x7a45, 0x1a79, 0x7a4a, 0x1a6e, 0x7a4f, 0x1a62, 0x7a54, 0x1a57,
+ 0x7a59, 0x1a4b, 0x7a5f, 0x1a40, 0x7a64, 0x1a34, 0x7a69, 0x1a29,
+ 0x7a6e, 0x1a1d, 0x7a73, 0x1a12, 0x7a78, 0x1a06, 0x7a7d, 0x19fb,
+ 0x7a82, 0x19ef, 0x7a88, 0x19e4, 0x7a8d, 0x19d8, 0x7a92, 0x19cd,
+ 0x7a97, 0x19c1, 0x7a9c, 0x19b6, 0x7aa1, 0x19aa, 0x7aa6, 0x199f,
+ 0x7aab, 0x1993, 0x7ab0, 0x1988, 0x7ab5, 0x197c, 0x7aba, 0x1971,
+ 0x7abf, 0x1965, 0x7ac4, 0x195a, 0x7ac9, 0x194e, 0x7ace, 0x1943,
+ 0x7ad3, 0x1937, 0x7ad8, 0x192c, 0x7add, 0x1920, 0x7ae2, 0x1914,
+ 0x7ae6, 0x1909, 0x7aeb, 0x18fd, 0x7af0, 0x18f2, 0x7af5, 0x18e6,
+ 0x7afa, 0x18db, 0x7aff, 0x18cf, 0x7b04, 0x18c3, 0x7b09, 0x18b8,
+ 0x7b0e, 0x18ac, 0x7b12, 0x18a1, 0x7b17, 0x1895, 0x7b1c, 0x1889,
+ 0x7b21, 0x187e, 0x7b26, 0x1872, 0x7b2a, 0x1867, 0x7b2f, 0x185b,
+ 0x7b34, 0x184f, 0x7b39, 0x1844, 0x7b3e, 0x1838, 0x7b42, 0x182d,
+ 0x7b47, 0x1821, 0x7b4c, 0x1815, 0x7b50, 0x180a, 0x7b55, 0x17fe,
+ 0x7b5a, 0x17f2, 0x7b5f, 0x17e7, 0x7b63, 0x17db, 0x7b68, 0x17cf,
+ 0x7b6d, 0x17c4, 0x7b71, 0x17b8, 0x7b76, 0x17ac, 0x7b7b, 0x17a1,
+ 0x7b7f, 0x1795, 0x7b84, 0x1789, 0x7b88, 0x177e, 0x7b8d, 0x1772,
+ 0x7b92, 0x1766, 0x7b96, 0x175b, 0x7b9b, 0x174f, 0x7b9f, 0x1743,
+ 0x7ba4, 0x1737, 0x7ba9, 0x172c, 0x7bad, 0x1720, 0x7bb2, 0x1714,
+ 0x7bb6, 0x1709, 0x7bbb, 0x16fd, 0x7bbf, 0x16f1, 0x7bc4, 0x16e5,
+ 0x7bc8, 0x16da, 0x7bcd, 0x16ce, 0x7bd1, 0x16c2, 0x7bd6, 0x16b6,
+ 0x7bda, 0x16ab, 0x7bde, 0x169f, 0x7be3, 0x1693, 0x7be7, 0x1687,
+ 0x7bec, 0x167c, 0x7bf0, 0x1670, 0x7bf5, 0x1664, 0x7bf9, 0x1658,
+ 0x7bfd, 0x164c, 0x7c02, 0x1641, 0x7c06, 0x1635, 0x7c0a, 0x1629,
+ 0x7c0f, 0x161d, 0x7c13, 0x1612, 0x7c17, 0x1606, 0x7c1c, 0x15fa,
+ 0x7c20, 0x15ee, 0x7c24, 0x15e2, 0x7c29, 0x15d7, 0x7c2d, 0x15cb,
+ 0x7c31, 0x15bf, 0x7c36, 0x15b3, 0x7c3a, 0x15a7, 0x7c3e, 0x159b,
+ 0x7c42, 0x1590, 0x7c46, 0x1584, 0x7c4b, 0x1578, 0x7c4f, 0x156c,
+ 0x7c53, 0x1560, 0x7c57, 0x1554, 0x7c5b, 0x1549, 0x7c60, 0x153d,
+ 0x7c64, 0x1531, 0x7c68, 0x1525, 0x7c6c, 0x1519, 0x7c70, 0x150d,
+ 0x7c74, 0x1501, 0x7c79, 0x14f6, 0x7c7d, 0x14ea, 0x7c81, 0x14de,
+ 0x7c85, 0x14d2, 0x7c89, 0x14c6, 0x7c8d, 0x14ba, 0x7c91, 0x14ae,
+ 0x7c95, 0x14a2, 0x7c99, 0x1496, 0x7c9d, 0x148b, 0x7ca1, 0x147f,
+ 0x7ca5, 0x1473, 0x7ca9, 0x1467, 0x7cad, 0x145b, 0x7cb1, 0x144f,
+ 0x7cb5, 0x1443, 0x7cb9, 0x1437, 0x7cbd, 0x142b, 0x7cc1, 0x141f,
+ 0x7cc5, 0x1413, 0x7cc9, 0x1407, 0x7ccd, 0x13fb, 0x7cd1, 0x13f0,
+ 0x7cd5, 0x13e4, 0x7cd9, 0x13d8, 0x7cdd, 0x13cc, 0x7ce0, 0x13c0,
+ 0x7ce4, 0x13b4, 0x7ce8, 0x13a8, 0x7cec, 0x139c, 0x7cf0, 0x1390,
+ 0x7cf4, 0x1384, 0x7cf8, 0x1378, 0x7cfb, 0x136c, 0x7cff, 0x1360,
+ 0x7d03, 0x1354, 0x7d07, 0x1348, 0x7d0b, 0x133c, 0x7d0e, 0x1330,
+ 0x7d12, 0x1324, 0x7d16, 0x1318, 0x7d1a, 0x130c, 0x7d1d, 0x1300,
+ 0x7d21, 0x12f4, 0x7d25, 0x12e8, 0x7d28, 0x12dc, 0x7d2c, 0x12d0,
+ 0x7d30, 0x12c4, 0x7d34, 0x12b8, 0x7d37, 0x12ac, 0x7d3b, 0x12a0,
+ 0x7d3f, 0x1294, 0x7d42, 0x1288, 0x7d46, 0x127c, 0x7d49, 0x1270,
+ 0x7d4d, 0x1264, 0x7d51, 0x1258, 0x7d54, 0x124c, 0x7d58, 0x1240,
+ 0x7d5b, 0x1234, 0x7d5f, 0x1228, 0x7d63, 0x121c, 0x7d66, 0x1210,
+ 0x7d6a, 0x1204, 0x7d6d, 0x11f7, 0x7d71, 0x11eb, 0x7d74, 0x11df,
+ 0x7d78, 0x11d3, 0x7d7b, 0x11c7, 0x7d7f, 0x11bb, 0x7d82, 0x11af,
+ 0x7d86, 0x11a3, 0x7d89, 0x1197, 0x7d8d, 0x118b, 0x7d90, 0x117f,
+ 0x7d93, 0x1173, 0x7d97, 0x1167, 0x7d9a, 0x115a, 0x7d9e, 0x114e,
+ 0x7da1, 0x1142, 0x7da4, 0x1136, 0x7da8, 0x112a, 0x7dab, 0x111e,
+ 0x7daf, 0x1112, 0x7db2, 0x1106, 0x7db5, 0x10fa, 0x7db9, 0x10ed,
+ 0x7dbc, 0x10e1, 0x7dbf, 0x10d5, 0x7dc2, 0x10c9, 0x7dc6, 0x10bd,
+ 0x7dc9, 0x10b1, 0x7dcc, 0x10a5, 0x7dd0, 0x1099, 0x7dd3, 0x108c,
+ 0x7dd6, 0x1080, 0x7dd9, 0x1074, 0x7ddd, 0x1068, 0x7de0, 0x105c,
+ 0x7de3, 0x1050, 0x7de6, 0x1044, 0x7de9, 0x1037, 0x7ded, 0x102b,
+ 0x7df0, 0x101f, 0x7df3, 0x1013, 0x7df6, 0x1007, 0x7df9, 0xffb,
+ 0x7dfc, 0xfee, 0x7dff, 0xfe2, 0x7e03, 0xfd6, 0x7e06, 0xfca,
+ 0x7e09, 0xfbe, 0x7e0c, 0xfb2, 0x7e0f, 0xfa5, 0x7e12, 0xf99,
+ 0x7e15, 0xf8d, 0x7e18, 0xf81, 0x7e1b, 0xf75, 0x7e1e, 0xf68,
+ 0x7e21, 0xf5c, 0x7e24, 0xf50, 0x7e27, 0xf44, 0x7e2a, 0xf38,
+ 0x7e2d, 0xf2b, 0x7e30, 0xf1f, 0x7e33, 0xf13, 0x7e36, 0xf07,
+ 0x7e39, 0xefb, 0x7e3c, 0xeee, 0x7e3f, 0xee2, 0x7e42, 0xed6,
+ 0x7e45, 0xeca, 0x7e48, 0xebd, 0x7e4a, 0xeb1, 0x7e4d, 0xea5,
+ 0x7e50, 0xe99, 0x7e53, 0xe8c, 0x7e56, 0xe80, 0x7e59, 0xe74,
+ 0x7e5c, 0xe68, 0x7e5e, 0xe5c, 0x7e61, 0xe4f, 0x7e64, 0xe43,
+ 0x7e67, 0xe37, 0x7e6a, 0xe2b, 0x7e6c, 0xe1e, 0x7e6f, 0xe12,
+ 0x7e72, 0xe06, 0x7e75, 0xdf9, 0x7e77, 0xded, 0x7e7a, 0xde1,
+ 0x7e7d, 0xdd5, 0x7e80, 0xdc8, 0x7e82, 0xdbc, 0x7e85, 0xdb0,
+ 0x7e88, 0xda4, 0x7e8a, 0xd97, 0x7e8d, 0xd8b, 0x7e90, 0xd7f,
+ 0x7e92, 0xd72, 0x7e95, 0xd66, 0x7e98, 0xd5a, 0x7e9a, 0xd4e,
+ 0x7e9d, 0xd41, 0x7e9f, 0xd35, 0x7ea2, 0xd29, 0x7ea5, 0xd1c,
+ 0x7ea7, 0xd10, 0x7eaa, 0xd04, 0x7eac, 0xcf8, 0x7eaf, 0xceb,
+ 0x7eb1, 0xcdf, 0x7eb4, 0xcd3, 0x7eb6, 0xcc6, 0x7eb9, 0xcba,
+ 0x7ebb, 0xcae, 0x7ebe, 0xca1, 0x7ec0, 0xc95, 0x7ec3, 0xc89,
+ 0x7ec5, 0xc7c, 0x7ec8, 0xc70, 0x7eca, 0xc64, 0x7ecc, 0xc57,
+ 0x7ecf, 0xc4b, 0x7ed1, 0xc3f, 0x7ed4, 0xc32, 0x7ed6, 0xc26,
+ 0x7ed8, 0xc1a, 0x7edb, 0xc0d, 0x7edd, 0xc01, 0x7ee0, 0xbf5,
+ 0x7ee2, 0xbe8, 0x7ee4, 0xbdc, 0x7ee7, 0xbd0, 0x7ee9, 0xbc3,
+ 0x7eeb, 0xbb7, 0x7eed, 0xbab, 0x7ef0, 0xb9e, 0x7ef2, 0xb92,
+ 0x7ef4, 0xb85, 0x7ef7, 0xb79, 0x7ef9, 0xb6d, 0x7efb, 0xb60,
+ 0x7efd, 0xb54, 0x7f00, 0xb48, 0x7f02, 0xb3b, 0x7f04, 0xb2f,
+ 0x7f06, 0xb23, 0x7f08, 0xb16, 0x7f0a, 0xb0a, 0x7f0d, 0xafd,
+ 0x7f0f, 0xaf1, 0x7f11, 0xae5, 0x7f13, 0xad8, 0x7f15, 0xacc,
+ 0x7f17, 0xac0, 0x7f19, 0xab3, 0x7f1c, 0xaa7, 0x7f1e, 0xa9a,
+ 0x7f20, 0xa8e, 0x7f22, 0xa82, 0x7f24, 0xa75, 0x7f26, 0xa69,
+ 0x7f28, 0xa5c, 0x7f2a, 0xa50, 0x7f2c, 0xa44, 0x7f2e, 0xa37,
+ 0x7f30, 0xa2b, 0x7f32, 0xa1e, 0x7f34, 0xa12, 0x7f36, 0xa06,
+ 0x7f38, 0x9f9, 0x7f3a, 0x9ed, 0x7f3c, 0x9e0, 0x7f3e, 0x9d4,
+ 0x7f40, 0x9c7, 0x7f42, 0x9bb, 0x7f43, 0x9af, 0x7f45, 0x9a2,
+ 0x7f47, 0x996, 0x7f49, 0x989, 0x7f4b, 0x97d, 0x7f4d, 0x970,
+ 0x7f4f, 0x964, 0x7f51, 0x958, 0x7f52, 0x94b, 0x7f54, 0x93f,
+ 0x7f56, 0x932, 0x7f58, 0x926, 0x7f5a, 0x919, 0x7f5b, 0x90d,
+ 0x7f5d, 0x901, 0x7f5f, 0x8f4, 0x7f61, 0x8e8, 0x7f62, 0x8db,
+ 0x7f64, 0x8cf, 0x7f66, 0x8c2, 0x7f68, 0x8b6, 0x7f69, 0x8a9,
+ 0x7f6b, 0x89d, 0x7f6d, 0x891, 0x7f6e, 0x884, 0x7f70, 0x878,
+ 0x7f72, 0x86b, 0x7f73, 0x85f, 0x7f75, 0x852, 0x7f77, 0x846,
+ 0x7f78, 0x839, 0x7f7a, 0x82d, 0x7f7b, 0x820, 0x7f7d, 0x814,
+ 0x7f7f, 0x807, 0x7f80, 0x7fb, 0x7f82, 0x7ef, 0x7f83, 0x7e2,
+ 0x7f85, 0x7d6, 0x7f86, 0x7c9, 0x7f88, 0x7bd, 0x7f89, 0x7b0,
+ 0x7f8b, 0x7a4, 0x7f8c, 0x797, 0x7f8e, 0x78b, 0x7f8f, 0x77e,
+ 0x7f91, 0x772, 0x7f92, 0x765, 0x7f94, 0x759, 0x7f95, 0x74c,
+ 0x7f97, 0x740, 0x7f98, 0x733, 0x7f99, 0x727, 0x7f9b, 0x71a,
+ 0x7f9c, 0x70e, 0x7f9e, 0x701, 0x7f9f, 0x6f5, 0x7fa0, 0x6e8,
+ 0x7fa2, 0x6dc, 0x7fa3, 0x6cf, 0x7fa4, 0x6c3, 0x7fa6, 0x6b6,
+ 0x7fa7, 0x6aa, 0x7fa8, 0x69d, 0x7faa, 0x691, 0x7fab, 0x684,
+ 0x7fac, 0x678, 0x7fad, 0x66b, 0x7faf, 0x65f, 0x7fb0, 0x652,
+ 0x7fb1, 0x646, 0x7fb2, 0x639, 0x7fb4, 0x62d, 0x7fb5, 0x620,
+ 0x7fb6, 0x614, 0x7fb7, 0x607, 0x7fb8, 0x5fb, 0x7fb9, 0x5ee,
+ 0x7fbb, 0x5e2, 0x7fbc, 0x5d5, 0x7fbd, 0x5c9, 0x7fbe, 0x5bc,
+ 0x7fbf, 0x5b0, 0x7fc0, 0x5a3, 0x7fc1, 0x597, 0x7fc3, 0x58a,
+ 0x7fc4, 0x57e, 0x7fc5, 0x571, 0x7fc6, 0x565, 0x7fc7, 0x558,
+ 0x7fc8, 0x54c, 0x7fc9, 0x53f, 0x7fca, 0x533, 0x7fcb, 0x526,
+ 0x7fcc, 0x51a, 0x7fcd, 0x50d, 0x7fce, 0x500, 0x7fcf, 0x4f4,
+ 0x7fd0, 0x4e7, 0x7fd1, 0x4db, 0x7fd2, 0x4ce, 0x7fd3, 0x4c2,
+ 0x7fd4, 0x4b5, 0x7fd5, 0x4a9, 0x7fd5, 0x49c, 0x7fd6, 0x490,
+ 0x7fd7, 0x483, 0x7fd8, 0x477, 0x7fd9, 0x46a, 0x7fda, 0x45e,
+ 0x7fdb, 0x451, 0x7fdc, 0x444, 0x7fdc, 0x438, 0x7fdd, 0x42b,
+ 0x7fde, 0x41f, 0x7fdf, 0x412, 0x7fe0, 0x406, 0x7fe0, 0x3f9,
+ 0x7fe1, 0x3ed, 0x7fe2, 0x3e0, 0x7fe3, 0x3d4, 0x7fe3, 0x3c7,
+ 0x7fe4, 0x3bb, 0x7fe5, 0x3ae, 0x7fe6, 0x3a1, 0x7fe6, 0x395,
+ 0x7fe7, 0x388, 0x7fe8, 0x37c, 0x7fe8, 0x36f, 0x7fe9, 0x363,
+ 0x7fea, 0x356, 0x7fea, 0x34a, 0x7feb, 0x33d, 0x7fec, 0x330,
+ 0x7fec, 0x324, 0x7fed, 0x317, 0x7fed, 0x30b, 0x7fee, 0x2fe,
+ 0x7fef, 0x2f2, 0x7fef, 0x2e5, 0x7ff0, 0x2d9, 0x7ff0, 0x2cc,
+ 0x7ff1, 0x2c0, 0x7ff1, 0x2b3, 0x7ff2, 0x2a6, 0x7ff2, 0x29a,
+ 0x7ff3, 0x28d, 0x7ff3, 0x281, 0x7ff4, 0x274, 0x7ff4, 0x268,
+ 0x7ff5, 0x25b, 0x7ff5, 0x24e, 0x7ff6, 0x242, 0x7ff6, 0x235,
+ 0x7ff7, 0x229, 0x7ff7, 0x21c, 0x7ff7, 0x210, 0x7ff8, 0x203,
+ 0x7ff8, 0x1f7, 0x7ff9, 0x1ea, 0x7ff9, 0x1dd, 0x7ff9, 0x1d1,
+ 0x7ffa, 0x1c4, 0x7ffa, 0x1b8, 0x7ffa, 0x1ab, 0x7ffb, 0x19f,
+ 0x7ffb, 0x192, 0x7ffb, 0x186, 0x7ffc, 0x179, 0x7ffc, 0x16c,
+ 0x7ffc, 0x160, 0x7ffc, 0x153, 0x7ffd, 0x147, 0x7ffd, 0x13a,
+ 0x7ffd, 0x12e, 0x7ffd, 0x121, 0x7ffe, 0x114, 0x7ffe, 0x108,
+ 0x7ffe, 0xfb, 0x7ffe, 0xef, 0x7ffe, 0xe2, 0x7fff, 0xd6,
+ 0x7fff, 0xc9, 0x7fff, 0xbc, 0x7fff, 0xb0, 0x7fff, 0xa3,
+ 0x7fff, 0x97, 0x7fff, 0x8a, 0x7fff, 0x7e, 0x7fff, 0x71,
+ 0x7fff, 0x65, 0x7fff, 0x58, 0x7fff, 0x4b, 0x7fff, 0x3f,
+ 0x7fff, 0x32, 0x7fff, 0x26, 0x7fff, 0x19, 0x7fff, 0xd,
+ 0x7fff, 0x0, 0x7fff, 0xfff3, 0x7fff, 0xffe7, 0x7fff, 0xffda,
+ 0x7fff, 0xffce, 0x7fff, 0xffc1, 0x7fff, 0xffb5, 0x7fff, 0xffa8,
+ 0x7fff, 0xff9b, 0x7fff, 0xff8f, 0x7fff, 0xff82, 0x7fff, 0xff76,
+ 0x7fff, 0xff69, 0x7fff, 0xff5d, 0x7fff, 0xff50, 0x7fff, 0xff44,
+ 0x7fff, 0xff37, 0x7fff, 0xff2a, 0x7ffe, 0xff1e, 0x7ffe, 0xff11,
+ 0x7ffe, 0xff05, 0x7ffe, 0xfef8, 0x7ffe, 0xfeec, 0x7ffd, 0xfedf,
+ 0x7ffd, 0xfed2, 0x7ffd, 0xfec6, 0x7ffd, 0xfeb9, 0x7ffc, 0xfead,
+ 0x7ffc, 0xfea0, 0x7ffc, 0xfe94, 0x7ffc, 0xfe87, 0x7ffb, 0xfe7a,
+ 0x7ffb, 0xfe6e, 0x7ffb, 0xfe61, 0x7ffa, 0xfe55, 0x7ffa, 0xfe48,
+ 0x7ffa, 0xfe3c, 0x7ff9, 0xfe2f, 0x7ff9, 0xfe23, 0x7ff9, 0xfe16,
+ 0x7ff8, 0xfe09, 0x7ff8, 0xfdfd, 0x7ff7, 0xfdf0, 0x7ff7, 0xfde4,
+ 0x7ff7, 0xfdd7, 0x7ff6, 0xfdcb, 0x7ff6, 0xfdbe, 0x7ff5, 0xfdb2,
+ 0x7ff5, 0xfda5, 0x7ff4, 0xfd98, 0x7ff4, 0xfd8c, 0x7ff3, 0xfd7f,
+ 0x7ff3, 0xfd73, 0x7ff2, 0xfd66, 0x7ff2, 0xfd5a, 0x7ff1, 0xfd4d,
+ 0x7ff1, 0xfd40, 0x7ff0, 0xfd34, 0x7ff0, 0xfd27, 0x7fef, 0xfd1b,
+ 0x7fef, 0xfd0e, 0x7fee, 0xfd02, 0x7fed, 0xfcf5, 0x7fed, 0xfce9,
+ 0x7fec, 0xfcdc, 0x7fec, 0xfcd0, 0x7feb, 0xfcc3, 0x7fea, 0xfcb6,
+ 0x7fea, 0xfcaa, 0x7fe9, 0xfc9d, 0x7fe8, 0xfc91, 0x7fe8, 0xfc84,
+ 0x7fe7, 0xfc78, 0x7fe6, 0xfc6b, 0x7fe6, 0xfc5f, 0x7fe5, 0xfc52,
+ 0x7fe4, 0xfc45, 0x7fe3, 0xfc39, 0x7fe3, 0xfc2c, 0x7fe2, 0xfc20,
+ 0x7fe1, 0xfc13, 0x7fe0, 0xfc07, 0x7fe0, 0xfbfa, 0x7fdf, 0xfbee,
+ 0x7fde, 0xfbe1, 0x7fdd, 0xfbd5, 0x7fdc, 0xfbc8, 0x7fdc, 0xfbbc,
+ 0x7fdb, 0xfbaf, 0x7fda, 0xfba2, 0x7fd9, 0xfb96, 0x7fd8, 0xfb89,
+ 0x7fd7, 0xfb7d, 0x7fd6, 0xfb70, 0x7fd5, 0xfb64, 0x7fd5, 0xfb57,
+ 0x7fd4, 0xfb4b, 0x7fd3, 0xfb3e, 0x7fd2, 0xfb32, 0x7fd1, 0xfb25,
+ 0x7fd0, 0xfb19, 0x7fcf, 0xfb0c, 0x7fce, 0xfb00, 0x7fcd, 0xfaf3,
+ 0x7fcc, 0xfae6, 0x7fcb, 0xfada, 0x7fca, 0xfacd, 0x7fc9, 0xfac1,
+ 0x7fc8, 0xfab4, 0x7fc7, 0xfaa8, 0x7fc6, 0xfa9b, 0x7fc5, 0xfa8f,
+ 0x7fc4, 0xfa82, 0x7fc3, 0xfa76, 0x7fc1, 0xfa69, 0x7fc0, 0xfa5d,
+ 0x7fbf, 0xfa50, 0x7fbe, 0xfa44, 0x7fbd, 0xfa37, 0x7fbc, 0xfa2b,
+ 0x7fbb, 0xfa1e, 0x7fb9, 0xfa12, 0x7fb8, 0xfa05, 0x7fb7, 0xf9f9,
+ 0x7fb6, 0xf9ec, 0x7fb5, 0xf9e0, 0x7fb4, 0xf9d3, 0x7fb2, 0xf9c7,
+ 0x7fb1, 0xf9ba, 0x7fb0, 0xf9ae, 0x7faf, 0xf9a1, 0x7fad, 0xf995,
+ 0x7fac, 0xf988, 0x7fab, 0xf97c, 0x7faa, 0xf96f, 0x7fa8, 0xf963,
+ 0x7fa7, 0xf956, 0x7fa6, 0xf94a, 0x7fa4, 0xf93d, 0x7fa3, 0xf931,
+ 0x7fa2, 0xf924, 0x7fa0, 0xf918, 0x7f9f, 0xf90b, 0x7f9e, 0xf8ff,
+ 0x7f9c, 0xf8f2, 0x7f9b, 0xf8e6, 0x7f99, 0xf8d9, 0x7f98, 0xf8cd,
+ 0x7f97, 0xf8c0, 0x7f95, 0xf8b4, 0x7f94, 0xf8a7, 0x7f92, 0xf89b,
+ 0x7f91, 0xf88e, 0x7f8f, 0xf882, 0x7f8e, 0xf875, 0x7f8c, 0xf869,
+ 0x7f8b, 0xf85c, 0x7f89, 0xf850, 0x7f88, 0xf843, 0x7f86, 0xf837,
+ 0x7f85, 0xf82a, 0x7f83, 0xf81e, 0x7f82, 0xf811, 0x7f80, 0xf805,
+ 0x7f7f, 0xf7f9, 0x7f7d, 0xf7ec, 0x7f7b, 0xf7e0, 0x7f7a, 0xf7d3,
+ 0x7f78, 0xf7c7, 0x7f77, 0xf7ba, 0x7f75, 0xf7ae, 0x7f73, 0xf7a1,
+ 0x7f72, 0xf795, 0x7f70, 0xf788, 0x7f6e, 0xf77c, 0x7f6d, 0xf76f,
+ 0x7f6b, 0xf763, 0x7f69, 0xf757, 0x7f68, 0xf74a, 0x7f66, 0xf73e,
+ 0x7f64, 0xf731, 0x7f62, 0xf725, 0x7f61, 0xf718, 0x7f5f, 0xf70c,
+ 0x7f5d, 0xf6ff, 0x7f5b, 0xf6f3, 0x7f5a, 0xf6e7, 0x7f58, 0xf6da,
+ 0x7f56, 0xf6ce, 0x7f54, 0xf6c1, 0x7f52, 0xf6b5, 0x7f51, 0xf6a8,
+ 0x7f4f, 0xf69c, 0x7f4d, 0xf690, 0x7f4b, 0xf683, 0x7f49, 0xf677,
+ 0x7f47, 0xf66a, 0x7f45, 0xf65e, 0x7f43, 0xf651, 0x7f42, 0xf645,
+ 0x7f40, 0xf639, 0x7f3e, 0xf62c, 0x7f3c, 0xf620, 0x7f3a, 0xf613,
+ 0x7f38, 0xf607, 0x7f36, 0xf5fa, 0x7f34, 0xf5ee, 0x7f32, 0xf5e2,
+ 0x7f30, 0xf5d5, 0x7f2e, 0xf5c9, 0x7f2c, 0xf5bc, 0x7f2a, 0xf5b0,
+ 0x7f28, 0xf5a4, 0x7f26, 0xf597, 0x7f24, 0xf58b, 0x7f22, 0xf57e,
+ 0x7f20, 0xf572, 0x7f1e, 0xf566, 0x7f1c, 0xf559, 0x7f19, 0xf54d,
+ 0x7f17, 0xf540, 0x7f15, 0xf534, 0x7f13, 0xf528, 0x7f11, 0xf51b,
+ 0x7f0f, 0xf50f, 0x7f0d, 0xf503, 0x7f0a, 0xf4f6, 0x7f08, 0xf4ea,
+ 0x7f06, 0xf4dd, 0x7f04, 0xf4d1, 0x7f02, 0xf4c5, 0x7f00, 0xf4b8,
+ 0x7efd, 0xf4ac, 0x7efb, 0xf4a0, 0x7ef9, 0xf493, 0x7ef7, 0xf487,
+ 0x7ef4, 0xf47b, 0x7ef2, 0xf46e, 0x7ef0, 0xf462, 0x7eed, 0xf455,
+ 0x7eeb, 0xf449, 0x7ee9, 0xf43d, 0x7ee7, 0xf430, 0x7ee4, 0xf424,
+ 0x7ee2, 0xf418, 0x7ee0, 0xf40b, 0x7edd, 0xf3ff, 0x7edb, 0xf3f3,
+ 0x7ed8, 0xf3e6, 0x7ed6, 0xf3da, 0x7ed4, 0xf3ce, 0x7ed1, 0xf3c1,
+ 0x7ecf, 0xf3b5, 0x7ecc, 0xf3a9, 0x7eca, 0xf39c, 0x7ec8, 0xf390,
+ 0x7ec5, 0xf384, 0x7ec3, 0xf377, 0x7ec0, 0xf36b, 0x7ebe, 0xf35f,
+ 0x7ebb, 0xf352, 0x7eb9, 0xf346, 0x7eb6, 0xf33a, 0x7eb4, 0xf32d,
+ 0x7eb1, 0xf321, 0x7eaf, 0xf315, 0x7eac, 0xf308, 0x7eaa, 0xf2fc,
+ 0x7ea7, 0xf2f0, 0x7ea5, 0xf2e4, 0x7ea2, 0xf2d7, 0x7e9f, 0xf2cb,
+ 0x7e9d, 0xf2bf, 0x7e9a, 0xf2b2, 0x7e98, 0xf2a6, 0x7e95, 0xf29a,
+ 0x7e92, 0xf28e, 0x7e90, 0xf281, 0x7e8d, 0xf275, 0x7e8a, 0xf269,
+ 0x7e88, 0xf25c, 0x7e85, 0xf250, 0x7e82, 0xf244, 0x7e80, 0xf238,
+ 0x7e7d, 0xf22b, 0x7e7a, 0xf21f, 0x7e77, 0xf213, 0x7e75, 0xf207,
+ 0x7e72, 0xf1fa, 0x7e6f, 0xf1ee, 0x7e6c, 0xf1e2, 0x7e6a, 0xf1d5,
+ 0x7e67, 0xf1c9, 0x7e64, 0xf1bd, 0x7e61, 0xf1b1, 0x7e5e, 0xf1a4,
+ 0x7e5c, 0xf198, 0x7e59, 0xf18c, 0x7e56, 0xf180, 0x7e53, 0xf174,
+ 0x7e50, 0xf167, 0x7e4d, 0xf15b, 0x7e4a, 0xf14f, 0x7e48, 0xf143,
+ 0x7e45, 0xf136, 0x7e42, 0xf12a, 0x7e3f, 0xf11e, 0x7e3c, 0xf112,
+ 0x7e39, 0xf105, 0x7e36, 0xf0f9, 0x7e33, 0xf0ed, 0x7e30, 0xf0e1,
+ 0x7e2d, 0xf0d5, 0x7e2a, 0xf0c8, 0x7e27, 0xf0bc, 0x7e24, 0xf0b0,
+ 0x7e21, 0xf0a4, 0x7e1e, 0xf098, 0x7e1b, 0xf08b, 0x7e18, 0xf07f,
+ 0x7e15, 0xf073, 0x7e12, 0xf067, 0x7e0f, 0xf05b, 0x7e0c, 0xf04e,
+ 0x7e09, 0xf042, 0x7e06, 0xf036, 0x7e03, 0xf02a, 0x7dff, 0xf01e,
+ 0x7dfc, 0xf012, 0x7df9, 0xf005, 0x7df6, 0xeff9, 0x7df3, 0xefed,
+ 0x7df0, 0xefe1, 0x7ded, 0xefd5, 0x7de9, 0xefc9, 0x7de6, 0xefbc,
+ 0x7de3, 0xefb0, 0x7de0, 0xefa4, 0x7ddd, 0xef98, 0x7dd9, 0xef8c,
+ 0x7dd6, 0xef80, 0x7dd3, 0xef74, 0x7dd0, 0xef67, 0x7dcc, 0xef5b,
+ 0x7dc9, 0xef4f, 0x7dc6, 0xef43, 0x7dc2, 0xef37, 0x7dbf, 0xef2b,
+ 0x7dbc, 0xef1f, 0x7db9, 0xef13, 0x7db5, 0xef06, 0x7db2, 0xeefa,
+ 0x7daf, 0xeeee, 0x7dab, 0xeee2, 0x7da8, 0xeed6, 0x7da4, 0xeeca,
+ 0x7da1, 0xeebe, 0x7d9e, 0xeeb2, 0x7d9a, 0xeea6, 0x7d97, 0xee99,
+ 0x7d93, 0xee8d, 0x7d90, 0xee81, 0x7d8d, 0xee75, 0x7d89, 0xee69,
+ 0x7d86, 0xee5d, 0x7d82, 0xee51, 0x7d7f, 0xee45, 0x7d7b, 0xee39,
+ 0x7d78, 0xee2d, 0x7d74, 0xee21, 0x7d71, 0xee15, 0x7d6d, 0xee09,
+ 0x7d6a, 0xedfc, 0x7d66, 0xedf0, 0x7d63, 0xede4, 0x7d5f, 0xedd8,
+ 0x7d5b, 0xedcc, 0x7d58, 0xedc0, 0x7d54, 0xedb4, 0x7d51, 0xeda8,
+ 0x7d4d, 0xed9c, 0x7d49, 0xed90, 0x7d46, 0xed84, 0x7d42, 0xed78,
+ 0x7d3f, 0xed6c, 0x7d3b, 0xed60, 0x7d37, 0xed54, 0x7d34, 0xed48,
+ 0x7d30, 0xed3c, 0x7d2c, 0xed30, 0x7d28, 0xed24, 0x7d25, 0xed18,
+ 0x7d21, 0xed0c, 0x7d1d, 0xed00, 0x7d1a, 0xecf4, 0x7d16, 0xece8,
+ 0x7d12, 0xecdc, 0x7d0e, 0xecd0, 0x7d0b, 0xecc4, 0x7d07, 0xecb8,
+ 0x7d03, 0xecac, 0x7cff, 0xeca0, 0x7cfb, 0xec94, 0x7cf8, 0xec88,
+ 0x7cf4, 0xec7c, 0x7cf0, 0xec70, 0x7cec, 0xec64, 0x7ce8, 0xec58,
+ 0x7ce4, 0xec4c, 0x7ce0, 0xec40, 0x7cdd, 0xec34, 0x7cd9, 0xec28,
+ 0x7cd5, 0xec1c, 0x7cd1, 0xec10, 0x7ccd, 0xec05, 0x7cc9, 0xebf9,
+ 0x7cc5, 0xebed, 0x7cc1, 0xebe1, 0x7cbd, 0xebd5, 0x7cb9, 0xebc9,
+ 0x7cb5, 0xebbd, 0x7cb1, 0xebb1, 0x7cad, 0xeba5, 0x7ca9, 0xeb99,
+ 0x7ca5, 0xeb8d, 0x7ca1, 0xeb81, 0x7c9d, 0xeb75, 0x7c99, 0xeb6a,
+ 0x7c95, 0xeb5e, 0x7c91, 0xeb52, 0x7c8d, 0xeb46, 0x7c89, 0xeb3a,
+ 0x7c85, 0xeb2e, 0x7c81, 0xeb22, 0x7c7d, 0xeb16, 0x7c79, 0xeb0a,
+ 0x7c74, 0xeaff, 0x7c70, 0xeaf3, 0x7c6c, 0xeae7, 0x7c68, 0xeadb,
+ 0x7c64, 0xeacf, 0x7c60, 0xeac3, 0x7c5b, 0xeab7, 0x7c57, 0xeaac,
+ 0x7c53, 0xeaa0, 0x7c4f, 0xea94, 0x7c4b, 0xea88, 0x7c46, 0xea7c,
+ 0x7c42, 0xea70, 0x7c3e, 0xea65, 0x7c3a, 0xea59, 0x7c36, 0xea4d,
+ 0x7c31, 0xea41, 0x7c2d, 0xea35, 0x7c29, 0xea29, 0x7c24, 0xea1e,
+ 0x7c20, 0xea12, 0x7c1c, 0xea06, 0x7c17, 0xe9fa, 0x7c13, 0xe9ee,
+ 0x7c0f, 0xe9e3, 0x7c0a, 0xe9d7, 0x7c06, 0xe9cb, 0x7c02, 0xe9bf,
+ 0x7bfd, 0xe9b4, 0x7bf9, 0xe9a8, 0x7bf5, 0xe99c, 0x7bf0, 0xe990,
+ 0x7bec, 0xe984, 0x7be7, 0xe979, 0x7be3, 0xe96d, 0x7bde, 0xe961,
+ 0x7bda, 0xe955, 0x7bd6, 0xe94a, 0x7bd1, 0xe93e, 0x7bcd, 0xe932,
+ 0x7bc8, 0xe926, 0x7bc4, 0xe91b, 0x7bbf, 0xe90f, 0x7bbb, 0xe903,
+ 0x7bb6, 0xe8f7, 0x7bb2, 0xe8ec, 0x7bad, 0xe8e0, 0x7ba9, 0xe8d4,
+ 0x7ba4, 0xe8c9, 0x7b9f, 0xe8bd, 0x7b9b, 0xe8b1, 0x7b96, 0xe8a5,
+ 0x7b92, 0xe89a, 0x7b8d, 0xe88e, 0x7b88, 0xe882, 0x7b84, 0xe877,
+ 0x7b7f, 0xe86b, 0x7b7b, 0xe85f, 0x7b76, 0xe854, 0x7b71, 0xe848,
+ 0x7b6d, 0xe83c, 0x7b68, 0xe831, 0x7b63, 0xe825, 0x7b5f, 0xe819,
+ 0x7b5a, 0xe80e, 0x7b55, 0xe802, 0x7b50, 0xe7f6, 0x7b4c, 0xe7eb,
+ 0x7b47, 0xe7df, 0x7b42, 0xe7d3, 0x7b3e, 0xe7c8, 0x7b39, 0xe7bc,
+ 0x7b34, 0xe7b1, 0x7b2f, 0xe7a5, 0x7b2a, 0xe799, 0x7b26, 0xe78e,
+ 0x7b21, 0xe782, 0x7b1c, 0xe777, 0x7b17, 0xe76b, 0x7b12, 0xe75f,
+ 0x7b0e, 0xe754, 0x7b09, 0xe748, 0x7b04, 0xe73d, 0x7aff, 0xe731,
+ 0x7afa, 0xe725, 0x7af5, 0xe71a, 0x7af0, 0xe70e, 0x7aeb, 0xe703,
+ 0x7ae6, 0xe6f7, 0x7ae2, 0xe6ec, 0x7add, 0xe6e0, 0x7ad8, 0xe6d4,
+ 0x7ad3, 0xe6c9, 0x7ace, 0xe6bd, 0x7ac9, 0xe6b2, 0x7ac4, 0xe6a6,
+ 0x7abf, 0xe69b, 0x7aba, 0xe68f, 0x7ab5, 0xe684, 0x7ab0, 0xe678,
+ 0x7aab, 0xe66d, 0x7aa6, 0xe661, 0x7aa1, 0xe656, 0x7a9c, 0xe64a,
+ 0x7a97, 0xe63f, 0x7a92, 0xe633, 0x7a8d, 0xe628, 0x7a88, 0xe61c,
+ 0x7a82, 0xe611, 0x7a7d, 0xe605, 0x7a78, 0xe5fa, 0x7a73, 0xe5ee,
+ 0x7a6e, 0xe5e3, 0x7a69, 0xe5d7, 0x7a64, 0xe5cc, 0x7a5f, 0xe5c0,
+ 0x7a59, 0xe5b5, 0x7a54, 0xe5a9, 0x7a4f, 0xe59e, 0x7a4a, 0xe592,
+ 0x7a45, 0xe587, 0x7a3f, 0xe57c, 0x7a3a, 0xe570, 0x7a35, 0xe565,
+ 0x7a30, 0xe559, 0x7a2b, 0xe54e, 0x7a25, 0xe542, 0x7a20, 0xe537,
+ 0x7a1b, 0xe52c, 0x7a16, 0xe520, 0x7a10, 0xe515, 0x7a0b, 0xe509,
+ 0x7a06, 0xe4fe, 0x7a00, 0xe4f3, 0x79fb, 0xe4e7, 0x79f6, 0xe4dc,
+ 0x79f0, 0xe4d0, 0x79eb, 0xe4c5, 0x79e6, 0xe4ba, 0x79e0, 0xe4ae,
+ 0x79db, 0xe4a3, 0x79d6, 0xe498, 0x79d0, 0xe48c, 0x79cb, 0xe481,
+ 0x79c5, 0xe476, 0x79c0, 0xe46a, 0x79bb, 0xe45f, 0x79b5, 0xe454,
+ 0x79b0, 0xe448, 0x79aa, 0xe43d, 0x79a5, 0xe432, 0x799f, 0xe426,
+ 0x799a, 0xe41b, 0x7994, 0xe410, 0x798f, 0xe404, 0x7989, 0xe3f9,
+ 0x7984, 0xe3ee, 0x797e, 0xe3e2, 0x7979, 0xe3d7, 0x7973, 0xe3cc,
+ 0x796e, 0xe3c1, 0x7968, 0xe3b5, 0x7963, 0xe3aa, 0x795d, 0xe39f,
+ 0x7958, 0xe394, 0x7952, 0xe388, 0x794c, 0xe37d, 0x7947, 0xe372,
+ 0x7941, 0xe367, 0x793b, 0xe35b, 0x7936, 0xe350, 0x7930, 0xe345,
+ 0x792b, 0xe33a, 0x7925, 0xe32e, 0x791f, 0xe323, 0x791a, 0xe318,
+ 0x7914, 0xe30d, 0x790e, 0xe301, 0x7909, 0xe2f6, 0x7903, 0xe2eb,
+ 0x78fd, 0xe2e0, 0x78f7, 0xe2d5, 0x78f2, 0xe2ca, 0x78ec, 0xe2be,
+ 0x78e6, 0xe2b3, 0x78e0, 0xe2a8, 0x78db, 0xe29d, 0x78d5, 0xe292,
+ 0x78cf, 0xe287, 0x78c9, 0xe27b, 0x78c3, 0xe270, 0x78be, 0xe265,
+ 0x78b8, 0xe25a, 0x78b2, 0xe24f, 0x78ac, 0xe244, 0x78a6, 0xe239,
+ 0x78a1, 0xe22d, 0x789b, 0xe222, 0x7895, 0xe217, 0x788f, 0xe20c,
+ 0x7889, 0xe201, 0x7883, 0xe1f6, 0x787d, 0xe1eb, 0x7877, 0xe1e0,
+ 0x7871, 0xe1d5, 0x786b, 0xe1ca, 0x7866, 0xe1be, 0x7860, 0xe1b3,
+ 0x785a, 0xe1a8, 0x7854, 0xe19d, 0x784e, 0xe192, 0x7848, 0xe187,
+ 0x7842, 0xe17c, 0x783c, 0xe171, 0x7836, 0xe166, 0x7830, 0xe15b,
+ 0x782a, 0xe150, 0x7824, 0xe145, 0x781e, 0xe13a, 0x7818, 0xe12f,
+ 0x7812, 0xe124, 0x780b, 0xe119, 0x7805, 0xe10e, 0x77ff, 0xe103,
+ 0x77f9, 0xe0f8, 0x77f3, 0xe0ed, 0x77ed, 0xe0e2, 0x77e7, 0xe0d7,
+ 0x77e1, 0xe0cc, 0x77db, 0xe0c1, 0x77d5, 0xe0b6, 0x77ce, 0xe0ab,
+ 0x77c8, 0xe0a0, 0x77c2, 0xe095, 0x77bc, 0xe08a, 0x77b6, 0xe07f,
+ 0x77b0, 0xe074, 0x77a9, 0xe069, 0x77a3, 0xe05e, 0x779d, 0xe054,
+ 0x7797, 0xe049, 0x7790, 0xe03e, 0x778a, 0xe033, 0x7784, 0xe028,
+ 0x777e, 0xe01d, 0x7777, 0xe012, 0x7771, 0xe007, 0x776b, 0xdffc,
+ 0x7765, 0xdff1, 0x775e, 0xdfe7, 0x7758, 0xdfdc, 0x7752, 0xdfd1,
+ 0x774b, 0xdfc6, 0x7745, 0xdfbb, 0x773f, 0xdfb0, 0x7738, 0xdfa5,
+ 0x7732, 0xdf9b, 0x772c, 0xdf90, 0x7725, 0xdf85, 0x771f, 0xdf7a,
+ 0x7718, 0xdf6f, 0x7712, 0xdf65, 0x770c, 0xdf5a, 0x7705, 0xdf4f,
+ 0x76ff, 0xdf44, 0x76f8, 0xdf39, 0x76f2, 0xdf2f, 0x76eb, 0xdf24,
+ 0x76e5, 0xdf19, 0x76df, 0xdf0e, 0x76d8, 0xdf03, 0x76d2, 0xdef9,
+ 0x76cb, 0xdeee, 0x76c5, 0xdee3, 0x76be, 0xded8, 0x76b8, 0xdece,
+ 0x76b1, 0xdec3, 0x76ab, 0xdeb8, 0x76a4, 0xdead, 0x769d, 0xdea3,
+ 0x7697, 0xde98, 0x7690, 0xde8d, 0x768a, 0xde83, 0x7683, 0xde78,
+ 0x767d, 0xde6d, 0x7676, 0xde62, 0x766f, 0xde58, 0x7669, 0xde4d,
+ 0x7662, 0xde42, 0x765c, 0xde38, 0x7655, 0xde2d, 0x764e, 0xde22,
+ 0x7648, 0xde18, 0x7641, 0xde0d, 0x763a, 0xde02, 0x7634, 0xddf8,
+ 0x762d, 0xdded, 0x7626, 0xdde2, 0x7620, 0xddd8, 0x7619, 0xddcd,
+ 0x7612, 0xddc3, 0x760b, 0xddb8, 0x7605, 0xddad, 0x75fe, 0xdda3,
+ 0x75f7, 0xdd98, 0x75f0, 0xdd8e, 0x75ea, 0xdd83, 0x75e3, 0xdd78,
+ 0x75dc, 0xdd6e, 0x75d5, 0xdd63, 0x75ce, 0xdd59, 0x75c8, 0xdd4e,
+ 0x75c1, 0xdd44, 0x75ba, 0xdd39, 0x75b3, 0xdd2e, 0x75ac, 0xdd24,
+ 0x75a5, 0xdd19, 0x759f, 0xdd0f, 0x7598, 0xdd04, 0x7591, 0xdcfa,
+ 0x758a, 0xdcef, 0x7583, 0xdce5, 0x757c, 0xdcda, 0x7575, 0xdcd0,
+ 0x756e, 0xdcc5, 0x7567, 0xdcbb, 0x7561, 0xdcb0, 0x755a, 0xdca6,
+ 0x7553, 0xdc9b, 0x754c, 0xdc91, 0x7545, 0xdc86, 0x753e, 0xdc7c,
+ 0x7537, 0xdc72, 0x7530, 0xdc67, 0x7529, 0xdc5d, 0x7522, 0xdc52,
+ 0x751b, 0xdc48, 0x7514, 0xdc3d, 0x750d, 0xdc33, 0x7506, 0xdc29,
+ 0x74ff, 0xdc1e, 0x74f8, 0xdc14, 0x74f1, 0xdc09, 0x74ea, 0xdbff,
+ 0x74e2, 0xdbf5, 0x74db, 0xdbea, 0x74d4, 0xdbe0, 0x74cd, 0xdbd5,
+ 0x74c6, 0xdbcb, 0x74bf, 0xdbc1, 0x74b8, 0xdbb6, 0x74b1, 0xdbac,
+ 0x74aa, 0xdba2, 0x74a2, 0xdb97, 0x749b, 0xdb8d, 0x7494, 0xdb83,
+ 0x748d, 0xdb78, 0x7486, 0xdb6e, 0x747f, 0xdb64, 0x7477, 0xdb59,
+ 0x7470, 0xdb4f, 0x7469, 0xdb45, 0x7462, 0xdb3b, 0x745b, 0xdb30,
+ 0x7453, 0xdb26, 0x744c, 0xdb1c, 0x7445, 0xdb11, 0x743e, 0xdb07,
+ 0x7436, 0xdafd, 0x742f, 0xdaf3, 0x7428, 0xdae8, 0x7420, 0xdade,
+ 0x7419, 0xdad4, 0x7412, 0xdaca, 0x740b, 0xdabf, 0x7403, 0xdab5,
+ 0x73fc, 0xdaab, 0x73f5, 0xdaa1, 0x73ed, 0xda97, 0x73e6, 0xda8c,
+ 0x73df, 0xda82, 0x73d7, 0xda78, 0x73d0, 0xda6e, 0x73c8, 0xda64,
+ 0x73c1, 0xda5a, 0x73ba, 0xda4f, 0x73b2, 0xda45, 0x73ab, 0xda3b,
+ 0x73a3, 0xda31, 0x739c, 0xda27, 0x7395, 0xda1d, 0x738d, 0xda13,
+ 0x7386, 0xda08, 0x737e, 0xd9fe, 0x7377, 0xd9f4, 0x736f, 0xd9ea,
+ 0x7368, 0xd9e0, 0x7360, 0xd9d6, 0x7359, 0xd9cc, 0x7351, 0xd9c2,
+ 0x734a, 0xd9b8, 0x7342, 0xd9ae, 0x733b, 0xd9a4, 0x7333, 0xd99a,
+ 0x732c, 0xd98f, 0x7324, 0xd985, 0x731d, 0xd97b, 0x7315, 0xd971,
+ 0x730d, 0xd967, 0x7306, 0xd95d, 0x72fe, 0xd953, 0x72f7, 0xd949,
+ 0x72ef, 0xd93f, 0x72e7, 0xd935, 0x72e0, 0xd92b, 0x72d8, 0xd921,
+ 0x72d0, 0xd917, 0x72c9, 0xd90d, 0x72c1, 0xd903, 0x72ba, 0xd8f9,
+ 0x72b2, 0xd8ef, 0x72aa, 0xd8e6, 0x72a3, 0xd8dc, 0x729b, 0xd8d2,
+ 0x7293, 0xd8c8, 0x728b, 0xd8be, 0x7284, 0xd8b4, 0x727c, 0xd8aa,
+ 0x7274, 0xd8a0, 0x726d, 0xd896, 0x7265, 0xd88c, 0x725d, 0xd882,
+ 0x7255, 0xd878, 0x724e, 0xd86f, 0x7246, 0xd865, 0x723e, 0xd85b,
+ 0x7236, 0xd851, 0x722e, 0xd847, 0x7227, 0xd83d, 0x721f, 0xd833,
+ 0x7217, 0xd82a, 0x720f, 0xd820, 0x7207, 0xd816, 0x71ff, 0xd80c,
+ 0x71f8, 0xd802, 0x71f0, 0xd7f8, 0x71e8, 0xd7ef, 0x71e0, 0xd7e5,
+ 0x71d8, 0xd7db, 0x71d0, 0xd7d1, 0x71c8, 0xd7c8, 0x71c0, 0xd7be,
+ 0x71b9, 0xd7b4, 0x71b1, 0xd7aa, 0x71a9, 0xd7a0, 0x71a1, 0xd797,
+ 0x7199, 0xd78d, 0x7191, 0xd783, 0x7189, 0xd77a, 0x7181, 0xd770,
+ 0x7179, 0xd766, 0x7171, 0xd75c, 0x7169, 0xd753, 0x7161, 0xd749,
+ 0x7159, 0xd73f, 0x7151, 0xd736, 0x7149, 0xd72c, 0x7141, 0xd722,
+ 0x7139, 0xd719, 0x7131, 0xd70f, 0x7129, 0xd705, 0x7121, 0xd6fc,
+ 0x7119, 0xd6f2, 0x7111, 0xd6e8, 0x7109, 0xd6df, 0x7101, 0xd6d5,
+ 0x70f9, 0xd6cb, 0x70f0, 0xd6c2, 0x70e8, 0xd6b8, 0x70e0, 0xd6af,
+ 0x70d8, 0xd6a5, 0x70d0, 0xd69b, 0x70c8, 0xd692, 0x70c0, 0xd688,
+ 0x70b8, 0xd67f, 0x70af, 0xd675, 0x70a7, 0xd66c, 0x709f, 0xd662,
+ 0x7097, 0xd659, 0x708f, 0xd64f, 0x7087, 0xd645, 0x707e, 0xd63c,
+ 0x7076, 0xd632, 0x706e, 0xd629, 0x7066, 0xd61f, 0x705d, 0xd616,
+ 0x7055, 0xd60c, 0x704d, 0xd603, 0x7045, 0xd5f9, 0x703c, 0xd5f0,
+ 0x7034, 0xd5e6, 0x702c, 0xd5dd, 0x7024, 0xd5d4, 0x701b, 0xd5ca,
+ 0x7013, 0xd5c1, 0x700b, 0xd5b7, 0x7002, 0xd5ae, 0x6ffa, 0xd5a4,
+ 0x6ff2, 0xd59b, 0x6fea, 0xd592, 0x6fe1, 0xd588, 0x6fd9, 0xd57f,
+ 0x6fd0, 0xd575, 0x6fc8, 0xd56c, 0x6fc0, 0xd563, 0x6fb7, 0xd559,
+ 0x6faf, 0xd550, 0x6fa7, 0xd547, 0x6f9e, 0xd53d, 0x6f96, 0xd534,
+ 0x6f8d, 0xd52a, 0x6f85, 0xd521, 0x6f7d, 0xd518, 0x6f74, 0xd50e,
+ 0x6f6c, 0xd505, 0x6f63, 0xd4fc, 0x6f5b, 0xd4f3, 0x6f52, 0xd4e9,
+ 0x6f4a, 0xd4e0, 0x6f41, 0xd4d7, 0x6f39, 0xd4cd, 0x6f30, 0xd4c4,
+ 0x6f28, 0xd4bb, 0x6f20, 0xd4b2, 0x6f17, 0xd4a8, 0x6f0e, 0xd49f,
+ 0x6f06, 0xd496, 0x6efd, 0xd48d, 0x6ef5, 0xd483, 0x6eec, 0xd47a,
+ 0x6ee4, 0xd471, 0x6edb, 0xd468, 0x6ed3, 0xd45f, 0x6eca, 0xd455,
+ 0x6ec2, 0xd44c, 0x6eb9, 0xd443, 0x6eb0, 0xd43a, 0x6ea8, 0xd431,
+ 0x6e9f, 0xd428, 0x6e97, 0xd41e, 0x6e8e, 0xd415, 0x6e85, 0xd40c,
+ 0x6e7d, 0xd403, 0x6e74, 0xd3fa, 0x6e6b, 0xd3f1, 0x6e63, 0xd3e8,
+ 0x6e5a, 0xd3df, 0x6e51, 0xd3d5, 0x6e49, 0xd3cc, 0x6e40, 0xd3c3,
+ 0x6e37, 0xd3ba, 0x6e2f, 0xd3b1, 0x6e26, 0xd3a8, 0x6e1d, 0xd39f,
+ 0x6e15, 0xd396, 0x6e0c, 0xd38d, 0x6e03, 0xd384, 0x6dfa, 0xd37b,
+ 0x6df2, 0xd372, 0x6de9, 0xd369, 0x6de0, 0xd360, 0x6dd7, 0xd357,
+ 0x6dcf, 0xd34e, 0x6dc6, 0xd345, 0x6dbd, 0xd33c, 0x6db4, 0xd333,
+ 0x6dab, 0xd32a, 0x6da3, 0xd321, 0x6d9a, 0xd318, 0x6d91, 0xd30f,
+ 0x6d88, 0xd306, 0x6d7f, 0xd2fd, 0x6d76, 0xd2f4, 0x6d6e, 0xd2eb,
+ 0x6d65, 0xd2e2, 0x6d5c, 0xd2d9, 0x6d53, 0xd2d1, 0x6d4a, 0xd2c8,
+ 0x6d41, 0xd2bf, 0x6d38, 0xd2b6, 0x6d2f, 0xd2ad, 0x6d27, 0xd2a4,
+ 0x6d1e, 0xd29b, 0x6d15, 0xd292, 0x6d0c, 0xd28a, 0x6d03, 0xd281,
+ 0x6cfa, 0xd278, 0x6cf1, 0xd26f, 0x6ce8, 0xd266, 0x6cdf, 0xd25d,
+ 0x6cd6, 0xd255, 0x6ccd, 0xd24c, 0x6cc4, 0xd243, 0x6cbb, 0xd23a,
+ 0x6cb2, 0xd231, 0x6ca9, 0xd229, 0x6ca0, 0xd220, 0x6c97, 0xd217,
+ 0x6c8e, 0xd20e, 0x6c85, 0xd206, 0x6c7c, 0xd1fd, 0x6c73, 0xd1f4,
+ 0x6c6a, 0xd1eb, 0x6c61, 0xd1e3, 0x6c58, 0xd1da, 0x6c4f, 0xd1d1,
+ 0x6c46, 0xd1c9, 0x6c3d, 0xd1c0, 0x6c34, 0xd1b7, 0x6c2b, 0xd1af,
+ 0x6c21, 0xd1a6, 0x6c18, 0xd19d, 0x6c0f, 0xd195, 0x6c06, 0xd18c,
+ 0x6bfd, 0xd183, 0x6bf4, 0xd17b, 0x6beb, 0xd172, 0x6be2, 0xd169,
+ 0x6bd8, 0xd161, 0x6bcf, 0xd158, 0x6bc6, 0xd150, 0x6bbd, 0xd147,
+ 0x6bb4, 0xd13e, 0x6bab, 0xd136, 0x6ba1, 0xd12d, 0x6b98, 0xd125,
+ 0x6b8f, 0xd11c, 0x6b86, 0xd114, 0x6b7d, 0xd10b, 0x6b73, 0xd103,
+ 0x6b6a, 0xd0fa, 0x6b61, 0xd0f2, 0x6b58, 0xd0e9, 0x6b4e, 0xd0e0,
+ 0x6b45, 0xd0d8, 0x6b3c, 0xd0d0, 0x6b33, 0xd0c7, 0x6b29, 0xd0bf,
+ 0x6b20, 0xd0b6, 0x6b17, 0xd0ae, 0x6b0d, 0xd0a5, 0x6b04, 0xd09d,
+ 0x6afb, 0xd094, 0x6af2, 0xd08c, 0x6ae8, 0xd083, 0x6adf, 0xd07b,
+ 0x6ad6, 0xd073, 0x6acc, 0xd06a, 0x6ac3, 0xd062, 0x6ab9, 0xd059,
+ 0x6ab0, 0xd051, 0x6aa7, 0xd049, 0x6a9d, 0xd040, 0x6a94, 0xd038,
+ 0x6a8b, 0xd030, 0x6a81, 0xd027, 0x6a78, 0xd01f, 0x6a6e, 0xd016,
+ 0x6a65, 0xd00e, 0x6a5c, 0xd006, 0x6a52, 0xcffe, 0x6a49, 0xcff5,
+ 0x6a3f, 0xcfed, 0x6a36, 0xcfe5, 0x6a2c, 0xcfdc, 0x6a23, 0xcfd4,
+ 0x6a1a, 0xcfcc, 0x6a10, 0xcfc4, 0x6a07, 0xcfbb, 0x69fd, 0xcfb3,
+ 0x69f4, 0xcfab, 0x69ea, 0xcfa3, 0x69e1, 0xcf9a, 0x69d7, 0xcf92,
+ 0x69ce, 0xcf8a, 0x69c4, 0xcf82, 0x69bb, 0xcf79, 0x69b1, 0xcf71,
+ 0x69a7, 0xcf69, 0x699e, 0xcf61, 0x6994, 0xcf59, 0x698b, 0xcf51,
+ 0x6981, 0xcf48, 0x6978, 0xcf40, 0x696e, 0xcf38, 0x6965, 0xcf30,
+ 0x695b, 0xcf28, 0x6951, 0xcf20, 0x6948, 0xcf18, 0x693e, 0xcf10,
+ 0x6935, 0xcf07, 0x692b, 0xceff, 0x6921, 0xcef7, 0x6918, 0xceef,
+ 0x690e, 0xcee7, 0x6904, 0xcedf, 0x68fb, 0xced7, 0x68f1, 0xcecf,
+ 0x68e7, 0xcec7, 0x68de, 0xcebf, 0x68d4, 0xceb7, 0x68ca, 0xceaf,
+ 0x68c1, 0xcea7, 0x68b7, 0xce9f, 0x68ad, 0xce97, 0x68a4, 0xce8f,
+ 0x689a, 0xce87, 0x6890, 0xce7f, 0x6886, 0xce77, 0x687d, 0xce6f,
+ 0x6873, 0xce67, 0x6869, 0xce5f, 0x6860, 0xce57, 0x6856, 0xce4f,
+ 0x684c, 0xce47, 0x6842, 0xce40, 0x6838, 0xce38, 0x682f, 0xce30,
+ 0x6825, 0xce28, 0x681b, 0xce20, 0x6811, 0xce18, 0x6808, 0xce10,
+ 0x67fe, 0xce08, 0x67f4, 0xce01, 0x67ea, 0xcdf9, 0x67e0, 0xcdf1,
+ 0x67d6, 0xcde9, 0x67cd, 0xcde1, 0x67c3, 0xcdd9, 0x67b9, 0xcdd2,
+ 0x67af, 0xcdca, 0x67a5, 0xcdc2, 0x679b, 0xcdba, 0x6791, 0xcdb2,
+ 0x6788, 0xcdab, 0x677e, 0xcda3, 0x6774, 0xcd9b, 0x676a, 0xcd93,
+ 0x6760, 0xcd8c, 0x6756, 0xcd84, 0x674c, 0xcd7c, 0x6742, 0xcd75,
+ 0x6738, 0xcd6d, 0x672e, 0xcd65, 0x6724, 0xcd5d, 0x671a, 0xcd56,
+ 0x6711, 0xcd4e, 0x6707, 0xcd46, 0x66fd, 0xcd3f, 0x66f3, 0xcd37,
+ 0x66e9, 0xcd30, 0x66df, 0xcd28, 0x66d5, 0xcd20, 0x66cb, 0xcd19,
+ 0x66c1, 0xcd11, 0x66b7, 0xcd09, 0x66ad, 0xcd02, 0x66a3, 0xccfa,
+ 0x6699, 0xccf3, 0x668f, 0xcceb, 0x6685, 0xcce3, 0x667b, 0xccdc,
+ 0x6671, 0xccd4, 0x6666, 0xcccd, 0x665c, 0xccc5, 0x6652, 0xccbe,
+ 0x6648, 0xccb6, 0x663e, 0xccaf, 0x6634, 0xcca7, 0x662a, 0xcca0,
+ 0x6620, 0xcc98, 0x6616, 0xcc91, 0x660c, 0xcc89, 0x6602, 0xcc82,
+ 0x65f8, 0xcc7a, 0x65ed, 0xcc73, 0x65e3, 0xcc6b, 0x65d9, 0xcc64,
+ 0x65cf, 0xcc5d, 0x65c5, 0xcc55, 0x65bb, 0xcc4e, 0x65b1, 0xcc46,
+ 0x65a6, 0xcc3f, 0x659c, 0xcc38, 0x6592, 0xcc30, 0x6588, 0xcc29,
+ 0x657e, 0xcc21, 0x6574, 0xcc1a, 0x6569, 0xcc13, 0x655f, 0xcc0b,
+ 0x6555, 0xcc04, 0x654b, 0xcbfd, 0x6541, 0xcbf5, 0x6536, 0xcbee,
+ 0x652c, 0xcbe7, 0x6522, 0xcbe0, 0x6518, 0xcbd8, 0x650d, 0xcbd1,
+ 0x6503, 0xcbca, 0x64f9, 0xcbc2, 0x64ef, 0xcbbb, 0x64e4, 0xcbb4,
+ 0x64da, 0xcbad, 0x64d0, 0xcba5, 0x64c5, 0xcb9e, 0x64bb, 0xcb97,
+ 0x64b1, 0xcb90, 0x64a7, 0xcb89, 0x649c, 0xcb81, 0x6492, 0xcb7a,
+ 0x6488, 0xcb73, 0x647d, 0xcb6c, 0x6473, 0xcb65, 0x6469, 0xcb5e,
+ 0x645e, 0xcb56, 0x6454, 0xcb4f, 0x644a, 0xcb48, 0x643f, 0xcb41,
+ 0x6435, 0xcb3a, 0x642b, 0xcb33, 0x6420, 0xcb2c, 0x6416, 0xcb25,
+ 0x640b, 0xcb1e, 0x6401, 0xcb16, 0x63f7, 0xcb0f, 0x63ec, 0xcb08,
+ 0x63e2, 0xcb01, 0x63d7, 0xcafa, 0x63cd, 0xcaf3, 0x63c3, 0xcaec,
+ 0x63b8, 0xcae5, 0x63ae, 0xcade, 0x63a3, 0xcad7, 0x6399, 0xcad0,
+ 0x638e, 0xcac9, 0x6384, 0xcac2, 0x637a, 0xcabb, 0x636f, 0xcab4,
+ 0x6365, 0xcaad, 0x635a, 0xcaa6, 0x6350, 0xca9f, 0x6345, 0xca99,
+ 0x633b, 0xca92, 0x6330, 0xca8b, 0x6326, 0xca84, 0x631b, 0xca7d,
+ 0x6311, 0xca76, 0x6306, 0xca6f, 0x62fc, 0xca68, 0x62f1, 0xca61,
+ 0x62e7, 0xca5b, 0x62dc, 0xca54, 0x62d2, 0xca4d, 0x62c7, 0xca46,
+ 0x62bc, 0xca3f, 0x62b2, 0xca38, 0x62a7, 0xca32, 0x629d, 0xca2b,
+ 0x6292, 0xca24, 0x6288, 0xca1d, 0x627d, 0xca16, 0x6272, 0xca10,
+ 0x6268, 0xca09, 0x625d, 0xca02, 0x6253, 0xc9fb, 0x6248, 0xc9f5,
+ 0x623d, 0xc9ee, 0x6233, 0xc9e7, 0x6228, 0xc9e0, 0x621e, 0xc9da,
+ 0x6213, 0xc9d3, 0x6208, 0xc9cc, 0x61fe, 0xc9c6, 0x61f3, 0xc9bf,
+ 0x61e8, 0xc9b8, 0x61de, 0xc9b2, 0x61d3, 0xc9ab, 0x61c8, 0xc9a4,
+ 0x61be, 0xc99e, 0x61b3, 0xc997, 0x61a8, 0xc991, 0x619e, 0xc98a,
+ 0x6193, 0xc983, 0x6188, 0xc97d, 0x617d, 0xc976, 0x6173, 0xc970,
+ 0x6168, 0xc969, 0x615d, 0xc963, 0x6153, 0xc95c, 0x6148, 0xc955,
+ 0x613d, 0xc94f, 0x6132, 0xc948, 0x6128, 0xc942, 0x611d, 0xc93b,
+ 0x6112, 0xc935, 0x6107, 0xc92e, 0x60fd, 0xc928, 0x60f2, 0xc921,
+ 0x60e7, 0xc91b, 0x60dc, 0xc915, 0x60d1, 0xc90e, 0x60c7, 0xc908,
+ 0x60bc, 0xc901, 0x60b1, 0xc8fb, 0x60a6, 0xc8f4, 0x609b, 0xc8ee,
+ 0x6091, 0xc8e8, 0x6086, 0xc8e1, 0x607b, 0xc8db, 0x6070, 0xc8d4,
+ 0x6065, 0xc8ce, 0x605b, 0xc8c8, 0x6050, 0xc8c1, 0x6045, 0xc8bb,
+ 0x603a, 0xc8b5, 0x602f, 0xc8ae, 0x6024, 0xc8a8, 0x6019, 0xc8a2,
+ 0x600f, 0xc89b, 0x6004, 0xc895, 0x5ff9, 0xc88f, 0x5fee, 0xc889,
+ 0x5fe3, 0xc882, 0x5fd8, 0xc87c, 0x5fcd, 0xc876, 0x5fc2, 0xc870,
+ 0x5fb7, 0xc869, 0x5fac, 0xc863, 0x5fa2, 0xc85d, 0x5f97, 0xc857,
+ 0x5f8c, 0xc850, 0x5f81, 0xc84a, 0x5f76, 0xc844, 0x5f6b, 0xc83e,
+ 0x5f60, 0xc838, 0x5f55, 0xc832, 0x5f4a, 0xc82b, 0x5f3f, 0xc825,
+ 0x5f34, 0xc81f, 0x5f29, 0xc819, 0x5f1e, 0xc813, 0x5f13, 0xc80d,
+ 0x5f08, 0xc807, 0x5efd, 0xc801, 0x5ef2, 0xc7fb, 0x5ee7, 0xc7f5,
+ 0x5edc, 0xc7ee, 0x5ed1, 0xc7e8, 0x5ec6, 0xc7e2, 0x5ebb, 0xc7dc,
+ 0x5eb0, 0xc7d6, 0x5ea5, 0xc7d0, 0x5e9a, 0xc7ca, 0x5e8f, 0xc7c4,
+ 0x5e84, 0xc7be, 0x5e79, 0xc7b8, 0x5e6e, 0xc7b2, 0x5e63, 0xc7ac,
+ 0x5e58, 0xc7a6, 0x5e4d, 0xc7a0, 0x5e42, 0xc79a, 0x5e36, 0xc795,
+ 0x5e2b, 0xc78f, 0x5e20, 0xc789, 0x5e15, 0xc783, 0x5e0a, 0xc77d,
+ 0x5dff, 0xc777, 0x5df4, 0xc771, 0x5de9, 0xc76b, 0x5dde, 0xc765,
+ 0x5dd3, 0xc75f, 0x5dc7, 0xc75a, 0x5dbc, 0xc754, 0x5db1, 0xc74e,
+ 0x5da6, 0xc748, 0x5d9b, 0xc742, 0x5d90, 0xc73d, 0x5d85, 0xc737,
+ 0x5d79, 0xc731, 0x5d6e, 0xc72b, 0x5d63, 0xc725, 0x5d58, 0xc720,
+ 0x5d4d, 0xc71a, 0x5d42, 0xc714, 0x5d36, 0xc70e, 0x5d2b, 0xc709,
+ 0x5d20, 0xc703, 0x5d15, 0xc6fd, 0x5d0a, 0xc6f7, 0x5cff, 0xc6f2,
+ 0x5cf3, 0xc6ec, 0x5ce8, 0xc6e6, 0x5cdd, 0xc6e1, 0x5cd2, 0xc6db,
+ 0x5cc6, 0xc6d5, 0x5cbb, 0xc6d0, 0x5cb0, 0xc6ca, 0x5ca5, 0xc6c5,
+ 0x5c99, 0xc6bf, 0x5c8e, 0xc6b9, 0x5c83, 0xc6b4, 0x5c78, 0xc6ae,
+ 0x5c6c, 0xc6a8, 0x5c61, 0xc6a3, 0x5c56, 0xc69d, 0x5c4b, 0xc698,
+ 0x5c3f, 0xc692, 0x5c34, 0xc68d, 0x5c29, 0xc687, 0x5c1e, 0xc682,
+ 0x5c12, 0xc67c, 0x5c07, 0xc677, 0x5bfc, 0xc671, 0x5bf0, 0xc66c,
+ 0x5be5, 0xc666, 0x5bda, 0xc661, 0x5bce, 0xc65b, 0x5bc3, 0xc656,
+ 0x5bb8, 0xc650, 0x5bac, 0xc64b, 0x5ba1, 0xc645, 0x5b96, 0xc640,
+ 0x5b8a, 0xc63b, 0x5b7f, 0xc635, 0x5b74, 0xc630, 0x5b68, 0xc62a,
+ 0x5b5d, 0xc625, 0x5b52, 0xc620, 0x5b46, 0xc61a, 0x5b3b, 0xc615,
+ 0x5b30, 0xc610, 0x5b24, 0xc60a, 0x5b19, 0xc605, 0x5b0d, 0xc600,
+ 0x5b02, 0xc5fa, 0x5af7, 0xc5f5, 0x5aeb, 0xc5f0, 0x5ae0, 0xc5ea,
+ 0x5ad4, 0xc5e5, 0x5ac9, 0xc5e0, 0x5abe, 0xc5db, 0x5ab2, 0xc5d5,
+ 0x5aa7, 0xc5d0, 0x5a9b, 0xc5cb, 0x5a90, 0xc5c6, 0x5a84, 0xc5c1,
+ 0x5a79, 0xc5bb, 0x5a6e, 0xc5b6, 0x5a62, 0xc5b1, 0x5a57, 0xc5ac,
+ 0x5a4b, 0xc5a7, 0x5a40, 0xc5a1, 0x5a34, 0xc59c, 0x5a29, 0xc597,
+ 0x5a1d, 0xc592, 0x5a12, 0xc58d, 0x5a06, 0xc588, 0x59fb, 0xc583,
+ 0x59ef, 0xc57e, 0x59e4, 0xc578, 0x59d8, 0xc573, 0x59cd, 0xc56e,
+ 0x59c1, 0xc569, 0x59b6, 0xc564, 0x59aa, 0xc55f, 0x599f, 0xc55a,
+ 0x5993, 0xc555, 0x5988, 0xc550, 0x597c, 0xc54b, 0x5971, 0xc546,
+ 0x5965, 0xc541, 0x595a, 0xc53c, 0x594e, 0xc537, 0x5943, 0xc532,
+ 0x5937, 0xc52d, 0x592c, 0xc528, 0x5920, 0xc523, 0x5914, 0xc51e,
+ 0x5909, 0xc51a, 0x58fd, 0xc515, 0x58f2, 0xc510, 0x58e6, 0xc50b,
+ 0x58db, 0xc506, 0x58cf, 0xc501, 0x58c3, 0xc4fc, 0x58b8, 0xc4f7,
+ 0x58ac, 0xc4f2, 0x58a1, 0xc4ee, 0x5895, 0xc4e9, 0x5889, 0xc4e4,
+ 0x587e, 0xc4df, 0x5872, 0xc4da, 0x5867, 0xc4d6, 0x585b, 0xc4d1,
+ 0x584f, 0xc4cc, 0x5844, 0xc4c7, 0x5838, 0xc4c2, 0x582d, 0xc4be,
+ 0x5821, 0xc4b9, 0x5815, 0xc4b4, 0x580a, 0xc4b0, 0x57fe, 0xc4ab,
+ 0x57f2, 0xc4a6, 0x57e7, 0xc4a1, 0x57db, 0xc49d, 0x57cf, 0xc498,
+ 0x57c4, 0xc493, 0x57b8, 0xc48f, 0x57ac, 0xc48a, 0x57a1, 0xc485,
+ 0x5795, 0xc481, 0x5789, 0xc47c, 0x577e, 0xc478, 0x5772, 0xc473,
+ 0x5766, 0xc46e, 0x575b, 0xc46a, 0x574f, 0xc465, 0x5743, 0xc461,
+ 0x5737, 0xc45c, 0x572c, 0xc457, 0x5720, 0xc453, 0x5714, 0xc44e,
+ 0x5709, 0xc44a, 0x56fd, 0xc445, 0x56f1, 0xc441, 0x56e5, 0xc43c,
+ 0x56da, 0xc438, 0x56ce, 0xc433, 0x56c2, 0xc42f, 0x56b6, 0xc42a,
+ 0x56ab, 0xc426, 0x569f, 0xc422, 0x5693, 0xc41d, 0x5687, 0xc419,
+ 0x567c, 0xc414, 0x5670, 0xc410, 0x5664, 0xc40b, 0x5658, 0xc407,
+ 0x564c, 0xc403, 0x5641, 0xc3fe, 0x5635, 0xc3fa, 0x5629, 0xc3f6,
+ 0x561d, 0xc3f1, 0x5612, 0xc3ed, 0x5606, 0xc3e9, 0x55fa, 0xc3e4,
+ 0x55ee, 0xc3e0, 0x55e2, 0xc3dc, 0x55d7, 0xc3d7, 0x55cb, 0xc3d3,
+ 0x55bf, 0xc3cf, 0x55b3, 0xc3ca, 0x55a7, 0xc3c6, 0x559b, 0xc3c2,
+ 0x5590, 0xc3be, 0x5584, 0xc3ba, 0x5578, 0xc3b5, 0x556c, 0xc3b1,
+ 0x5560, 0xc3ad, 0x5554, 0xc3a9, 0x5549, 0xc3a5, 0x553d, 0xc3a0,
+ 0x5531, 0xc39c, 0x5525, 0xc398, 0x5519, 0xc394, 0x550d, 0xc390,
+ 0x5501, 0xc38c, 0x54f6, 0xc387, 0x54ea, 0xc383, 0x54de, 0xc37f,
+ 0x54d2, 0xc37b, 0x54c6, 0xc377, 0x54ba, 0xc373, 0x54ae, 0xc36f,
+ 0x54a2, 0xc36b, 0x5496, 0xc367, 0x548b, 0xc363, 0x547f, 0xc35f,
+ 0x5473, 0xc35b, 0x5467, 0xc357, 0x545b, 0xc353, 0x544f, 0xc34f,
+ 0x5443, 0xc34b, 0x5437, 0xc347, 0x542b, 0xc343, 0x541f, 0xc33f,
+ 0x5413, 0xc33b, 0x5407, 0xc337, 0x53fb, 0xc333, 0x53f0, 0xc32f,
+ 0x53e4, 0xc32b, 0x53d8, 0xc327, 0x53cc, 0xc323, 0x53c0, 0xc320,
+ 0x53b4, 0xc31c, 0x53a8, 0xc318, 0x539c, 0xc314, 0x5390, 0xc310,
+ 0x5384, 0xc30c, 0x5378, 0xc308, 0x536c, 0xc305, 0x5360, 0xc301,
+ 0x5354, 0xc2fd, 0x5348, 0xc2f9, 0x533c, 0xc2f5, 0x5330, 0xc2f2,
+ 0x5324, 0xc2ee, 0x5318, 0xc2ea, 0x530c, 0xc2e6, 0x5300, 0xc2e3,
+ 0x52f4, 0xc2df, 0x52e8, 0xc2db, 0x52dc, 0xc2d8, 0x52d0, 0xc2d4,
+ 0x52c4, 0xc2d0, 0x52b8, 0xc2cc, 0x52ac, 0xc2c9, 0x52a0, 0xc2c5,
+ 0x5294, 0xc2c1, 0x5288, 0xc2be, 0x527c, 0xc2ba, 0x5270, 0xc2b7,
+ 0x5264, 0xc2b3, 0x5258, 0xc2af, 0x524c, 0xc2ac, 0x5240, 0xc2a8,
+ 0x5234, 0xc2a5, 0x5228, 0xc2a1, 0x521c, 0xc29d, 0x5210, 0xc29a,
+ 0x5204, 0xc296, 0x51f7, 0xc293, 0x51eb, 0xc28f, 0x51df, 0xc28c,
+ 0x51d3, 0xc288, 0x51c7, 0xc285, 0x51bb, 0xc281, 0x51af, 0xc27e,
+ 0x51a3, 0xc27a, 0x5197, 0xc277, 0x518b, 0xc273, 0x517f, 0xc270,
+ 0x5173, 0xc26d, 0x5167, 0xc269, 0x515a, 0xc266, 0x514e, 0xc262,
+ 0x5142, 0xc25f, 0x5136, 0xc25c, 0x512a, 0xc258, 0x511e, 0xc255,
+ 0x5112, 0xc251, 0x5106, 0xc24e, 0x50fa, 0xc24b, 0x50ed, 0xc247,
+ 0x50e1, 0xc244, 0x50d5, 0xc241, 0x50c9, 0xc23e, 0x50bd, 0xc23a,
+ 0x50b1, 0xc237, 0x50a5, 0xc234, 0x5099, 0xc230, 0x508c, 0xc22d,
+ 0x5080, 0xc22a, 0x5074, 0xc227, 0x5068, 0xc223, 0x505c, 0xc220,
+ 0x5050, 0xc21d, 0x5044, 0xc21a, 0x5037, 0xc217, 0x502b, 0xc213,
+ 0x501f, 0xc210, 0x5013, 0xc20d, 0x5007, 0xc20a, 0x4ffb, 0xc207,
+ 0x4fee, 0xc204, 0x4fe2, 0xc201, 0x4fd6, 0xc1fd, 0x4fca, 0xc1fa,
+ 0x4fbe, 0xc1f7, 0x4fb2, 0xc1f4, 0x4fa5, 0xc1f1, 0x4f99, 0xc1ee,
+ 0x4f8d, 0xc1eb, 0x4f81, 0xc1e8, 0x4f75, 0xc1e5, 0x4f68, 0xc1e2,
+ 0x4f5c, 0xc1df, 0x4f50, 0xc1dc, 0x4f44, 0xc1d9, 0x4f38, 0xc1d6,
+ 0x4f2b, 0xc1d3, 0x4f1f, 0xc1d0, 0x4f13, 0xc1cd, 0x4f07, 0xc1ca,
+ 0x4efb, 0xc1c7, 0x4eee, 0xc1c4, 0x4ee2, 0xc1c1, 0x4ed6, 0xc1be,
+ 0x4eca, 0xc1bb, 0x4ebd, 0xc1b8, 0x4eb1, 0xc1b6, 0x4ea5, 0xc1b3,
+ 0x4e99, 0xc1b0, 0x4e8c, 0xc1ad, 0x4e80, 0xc1aa, 0x4e74, 0xc1a7,
+ 0x4e68, 0xc1a4, 0x4e5c, 0xc1a2, 0x4e4f, 0xc19f, 0x4e43, 0xc19c,
+ 0x4e37, 0xc199, 0x4e2b, 0xc196, 0x4e1e, 0xc194, 0x4e12, 0xc191,
+ 0x4e06, 0xc18e, 0x4df9, 0xc18b, 0x4ded, 0xc189, 0x4de1, 0xc186,
+ 0x4dd5, 0xc183, 0x4dc8, 0xc180, 0x4dbc, 0xc17e, 0x4db0, 0xc17b,
+ 0x4da4, 0xc178, 0x4d97, 0xc176, 0x4d8b, 0xc173, 0x4d7f, 0xc170,
+ 0x4d72, 0xc16e, 0x4d66, 0xc16b, 0x4d5a, 0xc168, 0x4d4e, 0xc166,
+ 0x4d41, 0xc163, 0x4d35, 0xc161, 0x4d29, 0xc15e, 0x4d1c, 0xc15b,
+ 0x4d10, 0xc159, 0x4d04, 0xc156, 0x4cf8, 0xc154, 0x4ceb, 0xc151,
+ 0x4cdf, 0xc14f, 0x4cd3, 0xc14c, 0x4cc6, 0xc14a, 0x4cba, 0xc147,
+ 0x4cae, 0xc145, 0x4ca1, 0xc142, 0x4c95, 0xc140, 0x4c89, 0xc13d,
+ 0x4c7c, 0xc13b, 0x4c70, 0xc138, 0x4c64, 0xc136, 0x4c57, 0xc134,
+ 0x4c4b, 0xc131, 0x4c3f, 0xc12f, 0x4c32, 0xc12c, 0x4c26, 0xc12a,
+ 0x4c1a, 0xc128, 0x4c0d, 0xc125, 0x4c01, 0xc123, 0x4bf5, 0xc120,
+ 0x4be8, 0xc11e, 0x4bdc, 0xc11c, 0x4bd0, 0xc119, 0x4bc3, 0xc117,
+ 0x4bb7, 0xc115, 0x4bab, 0xc113, 0x4b9e, 0xc110, 0x4b92, 0xc10e,
+ 0x4b85, 0xc10c, 0x4b79, 0xc109, 0x4b6d, 0xc107, 0x4b60, 0xc105,
+ 0x4b54, 0xc103, 0x4b48, 0xc100, 0x4b3b, 0xc0fe, 0x4b2f, 0xc0fc,
+ 0x4b23, 0xc0fa, 0x4b16, 0xc0f8, 0x4b0a, 0xc0f6, 0x4afd, 0xc0f3,
+ 0x4af1, 0xc0f1, 0x4ae5, 0xc0ef, 0x4ad8, 0xc0ed, 0x4acc, 0xc0eb,
+ 0x4ac0, 0xc0e9, 0x4ab3, 0xc0e7, 0x4aa7, 0xc0e4, 0x4a9a, 0xc0e2,
+ 0x4a8e, 0xc0e0, 0x4a82, 0xc0de, 0x4a75, 0xc0dc, 0x4a69, 0xc0da,
+ 0x4a5c, 0xc0d8, 0x4a50, 0xc0d6, 0x4a44, 0xc0d4, 0x4a37, 0xc0d2,
+ 0x4a2b, 0xc0d0, 0x4a1e, 0xc0ce, 0x4a12, 0xc0cc, 0x4a06, 0xc0ca,
+ 0x49f9, 0xc0c8, 0x49ed, 0xc0c6, 0x49e0, 0xc0c4, 0x49d4, 0xc0c2,
+ 0x49c7, 0xc0c0, 0x49bb, 0xc0be, 0x49af, 0xc0bd, 0x49a2, 0xc0bb,
+ 0x4996, 0xc0b9, 0x4989, 0xc0b7, 0x497d, 0xc0b5, 0x4970, 0xc0b3,
+ 0x4964, 0xc0b1, 0x4958, 0xc0af, 0x494b, 0xc0ae, 0x493f, 0xc0ac,
+ 0x4932, 0xc0aa, 0x4926, 0xc0a8, 0x4919, 0xc0a6, 0x490d, 0xc0a5,
+ 0x4901, 0xc0a3, 0x48f4, 0xc0a1, 0x48e8, 0xc09f, 0x48db, 0xc09e,
+ 0x48cf, 0xc09c, 0x48c2, 0xc09a, 0x48b6, 0xc098, 0x48a9, 0xc097,
+ 0x489d, 0xc095, 0x4891, 0xc093, 0x4884, 0xc092, 0x4878, 0xc090,
+ 0x486b, 0xc08e, 0x485f, 0xc08d, 0x4852, 0xc08b, 0x4846, 0xc089,
+ 0x4839, 0xc088, 0x482d, 0xc086, 0x4820, 0xc085, 0x4814, 0xc083,
+ 0x4807, 0xc081, 0x47fb, 0xc080, 0x47ef, 0xc07e, 0x47e2, 0xc07d,
+ 0x47d6, 0xc07b, 0x47c9, 0xc07a, 0x47bd, 0xc078, 0x47b0, 0xc077,
+ 0x47a4, 0xc075, 0x4797, 0xc074, 0x478b, 0xc072, 0x477e, 0xc071,
+ 0x4772, 0xc06f, 0x4765, 0xc06e, 0x4759, 0xc06c, 0x474c, 0xc06b,
+ 0x4740, 0xc069, 0x4733, 0xc068, 0x4727, 0xc067, 0x471a, 0xc065,
+ 0x470e, 0xc064, 0x4701, 0xc062, 0x46f5, 0xc061, 0x46e8, 0xc060,
+ 0x46dc, 0xc05e, 0x46cf, 0xc05d, 0x46c3, 0xc05c, 0x46b6, 0xc05a,
+ 0x46aa, 0xc059, 0x469d, 0xc058, 0x4691, 0xc056, 0x4684, 0xc055,
+ 0x4678, 0xc054, 0x466b, 0xc053, 0x465f, 0xc051, 0x4652, 0xc050,
+ 0x4646, 0xc04f, 0x4639, 0xc04e, 0x462d, 0xc04c, 0x4620, 0xc04b,
+ 0x4614, 0xc04a, 0x4607, 0xc049, 0x45fb, 0xc048, 0x45ee, 0xc047,
+ 0x45e2, 0xc045, 0x45d5, 0xc044, 0x45c9, 0xc043, 0x45bc, 0xc042,
+ 0x45b0, 0xc041, 0x45a3, 0xc040, 0x4597, 0xc03f, 0x458a, 0xc03d,
+ 0x457e, 0xc03c, 0x4571, 0xc03b, 0x4565, 0xc03a, 0x4558, 0xc039,
+ 0x454c, 0xc038, 0x453f, 0xc037, 0x4533, 0xc036, 0x4526, 0xc035,
+ 0x451a, 0xc034, 0x450d, 0xc033, 0x4500, 0xc032, 0x44f4, 0xc031,
+ 0x44e7, 0xc030, 0x44db, 0xc02f, 0x44ce, 0xc02e, 0x44c2, 0xc02d,
+ 0x44b5, 0xc02c, 0x44a9, 0xc02b, 0x449c, 0xc02b, 0x4490, 0xc02a,
+ 0x4483, 0xc029, 0x4477, 0xc028, 0x446a, 0xc027, 0x445e, 0xc026,
+ 0x4451, 0xc025, 0x4444, 0xc024, 0x4438, 0xc024, 0x442b, 0xc023,
+ 0x441f, 0xc022, 0x4412, 0xc021, 0x4406, 0xc020, 0x43f9, 0xc020,
+ 0x43ed, 0xc01f, 0x43e0, 0xc01e, 0x43d4, 0xc01d, 0x43c7, 0xc01d,
+ 0x43bb, 0xc01c, 0x43ae, 0xc01b, 0x43a1, 0xc01a, 0x4395, 0xc01a,
+ 0x4388, 0xc019, 0x437c, 0xc018, 0x436f, 0xc018, 0x4363, 0xc017,
+ 0x4356, 0xc016, 0x434a, 0xc016, 0x433d, 0xc015, 0x4330, 0xc014,
+ 0x4324, 0xc014, 0x4317, 0xc013, 0x430b, 0xc013, 0x42fe, 0xc012,
+ 0x42f2, 0xc011, 0x42e5, 0xc011, 0x42d9, 0xc010, 0x42cc, 0xc010,
+ 0x42c0, 0xc00f, 0x42b3, 0xc00f, 0x42a6, 0xc00e, 0x429a, 0xc00e,
+ 0x428d, 0xc00d, 0x4281, 0xc00d, 0x4274, 0xc00c, 0x4268, 0xc00c,
+ 0x425b, 0xc00b, 0x424e, 0xc00b, 0x4242, 0xc00a, 0x4235, 0xc00a,
+ 0x4229, 0xc009, 0x421c, 0xc009, 0x4210, 0xc009, 0x4203, 0xc008,
+ 0x41f7, 0xc008, 0x41ea, 0xc007, 0x41dd, 0xc007, 0x41d1, 0xc007,
+ 0x41c4, 0xc006, 0x41b8, 0xc006, 0x41ab, 0xc006, 0x419f, 0xc005,
+ 0x4192, 0xc005, 0x4186, 0xc005, 0x4179, 0xc004, 0x416c, 0xc004,
+ 0x4160, 0xc004, 0x4153, 0xc004, 0x4147, 0xc003, 0x413a, 0xc003,
+ 0x412e, 0xc003, 0x4121, 0xc003, 0x4114, 0xc002, 0x4108, 0xc002,
+ 0x40fb, 0xc002, 0x40ef, 0xc002, 0x40e2, 0xc002, 0x40d6, 0xc001,
+ 0x40c9, 0xc001, 0x40bc, 0xc001, 0x40b0, 0xc001, 0x40a3, 0xc001,
+ 0x4097, 0xc001, 0x408a, 0xc001, 0x407e, 0xc000, 0x4071, 0xc000,
+ 0x4065, 0xc000, 0x4058, 0xc000, 0x404b, 0xc000, 0x403f, 0xc000,
+ 0x4032, 0xc000, 0x4026, 0xc000, 0x4019, 0xc000, 0x400d, 0xc000,
+};
+
+/**
+* @brief Initialization function for the Q15 RFFT/RIFFT.
+* @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure.
+* @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure.
+* @param[in] fftLenReal length of the FFT.
+* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>fftLenReal</code> Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.
+* \par
+* The parameter <code>ifftFlagR</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* This function also initializes Twiddle factor table.
+*/
+
+arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag)
+{
+
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialize the Real FFT length */
+ S->fftLenReal = (uint16_t) fftLenReal;
+
+ /* Initialize the Complex FFT length */
+ S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+ /* Initialize the Twiddle coefficientA pointer */
+ S->pTwiddleAReal = (q15_t *) realCoefAQ15;
+
+ /* Initialize the Twiddle coefficientB pointer */
+ S->pTwiddleBReal = (q15_t *) realCoefBQ15;
+
+ /* Initialize the Flag for selection of RFFT or RIFFT */
+ S->ifftFlagR = (uint8_t) ifftFlagR;
+
+ /* Initialize the Flag for calculation Bit reversal or not */
+ S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+ /* Initialization of coef modifier depending on the FFT length */
+ switch (S->fftLenReal)
+ {
+ case 8192:
+ S->twidCoefRModifier = 1u;
+ break;
+ case 2048u:
+ S->twidCoefRModifier = 4u;
+ break;
+ case 512u:
+ S->twidCoefRModifier = 16u;
+ break;
+ case 128u:
+ S->twidCoefRModifier = 64u;
+ break;
+ default:
+ /* Reporting argument error if rfftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ /* Init Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ if(S->ifftFlagR)
+ {
+ /* Initializes the CIFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 1u, 1u);
+ }
+ else
+ {
+ /* Initializes the CFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 0u, 1u);
+ }
+
+ /* return the status of RFFT Init function */
+ return (status);
+
+}
+
+ /**
+ * @} end of RealFFT group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_q31.c
new file mode 100644
index 000000000..da815cff0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_init_q31.c
@@ -0,0 +1,4279 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_init_q31.c
+*
+* Description: RFFT & RIFFT Q31 initialisation function
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**
+ * @ingroup groupTransforms
+ */
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+* \par
+* Generation floating point realCoefAQ31 array:
+* \par
+* n = 4096
+* <pre>for (i = 0; i < n; i++)
+* {
+* pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));
+* pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* }</pre>
+* \par
+* Convert to fixed point Q31 format
+* round(pATable[i] * pow(2, 31))
+*/
+
+
+static const q31_t realCoefAQ31[8192] = {
+ 0x40000000, 0xc0000000, 0x3ff36f02, 0xc000013c,
+ 0x3fe6de05, 0xc00004ef, 0x3fda4d09, 0xc0000b1a,
+ 0x3fcdbc0f, 0xc00013bd, 0x3fc12b16, 0xc0001ed8,
+ 0x3fb49a1f, 0xc0002c6a, 0x3fa8092c, 0xc0003c74,
+ 0x3f9b783c, 0xc0004ef5, 0x3f8ee750, 0xc00063ee,
+ 0x3f825668, 0xc0007b5f, 0x3f75c585, 0xc0009547,
+ 0x3f6934a8, 0xc000b1a7, 0x3f5ca3d0, 0xc000d07e,
+ 0x3f5012fe, 0xc000f1ce, 0x3f438234, 0xc0011594,
+ 0x3f36f170, 0xc0013bd3, 0x3f2a60b4, 0xc0016489,
+ 0x3f1dd001, 0xc0018fb6, 0x3f113f56, 0xc001bd5c,
+ 0x3f04aeb5, 0xc001ed78, 0x3ef81e1d, 0xc002200d,
+ 0x3eeb8d8f, 0xc0025519, 0x3edefd0c, 0xc0028c9c,
+ 0x3ed26c94, 0xc002c697, 0x3ec5dc28, 0xc003030a,
+ 0x3eb94bc8, 0xc00341f4, 0x3eacbb74, 0xc0038356,
+ 0x3ea02b2e, 0xc003c72f, 0x3e939af5, 0xc0040d80,
+ 0x3e870aca, 0xc0045648, 0x3e7a7aae, 0xc004a188,
+ 0x3e6deaa1, 0xc004ef3f, 0x3e615aa3, 0xc0053f6e,
+ 0x3e54cab5, 0xc0059214, 0x3e483ad8, 0xc005e731,
+ 0x3e3bab0b, 0xc0063ec6, 0x3e2f1b50, 0xc00698d3,
+ 0x3e228ba7, 0xc006f556, 0x3e15fc11, 0xc0075452,
+ 0x3e096c8d, 0xc007b5c4, 0x3dfcdd1d, 0xc00819ae,
+ 0x3df04dc0, 0xc008800f, 0x3de3be78, 0xc008e8e8,
+ 0x3dd72f45, 0xc0095438, 0x3dcaa027, 0xc009c1ff,
+ 0x3dbe111e, 0xc00a323d, 0x3db1822c, 0xc00aa4f3,
+ 0x3da4f351, 0xc00b1a20, 0x3d98648d, 0xc00b91c4,
+ 0x3d8bd5e1, 0xc00c0be0, 0x3d7f474d, 0xc00c8872,
+ 0x3d72b8d2, 0xc00d077c, 0x3d662a70, 0xc00d88fd,
+ 0x3d599c28, 0xc00e0cf5, 0x3d4d0df9, 0xc00e9364,
+ 0x3d407fe6, 0xc00f1c4a, 0x3d33f1ed, 0xc00fa7a8,
+ 0x3d276410, 0xc010357c, 0x3d1ad650, 0xc010c5c7,
+ 0x3d0e48ab, 0xc011588a, 0x3d01bb24, 0xc011edc3,
+ 0x3cf52dbb, 0xc0128574, 0x3ce8a06f, 0xc0131f9b,
+ 0x3cdc1342, 0xc013bc39, 0x3ccf8634, 0xc0145b4e,
+ 0x3cc2f945, 0xc014fcda, 0x3cb66c77, 0xc015a0dd,
+ 0x3ca9dfc8, 0xc0164757, 0x3c9d533b, 0xc016f047,
+ 0x3c90c6cf, 0xc0179bae, 0x3c843a85, 0xc018498c,
+ 0x3c77ae5e, 0xc018f9e1, 0x3c6b2259, 0xc019acac,
+ 0x3c5e9678, 0xc01a61ee, 0x3c520aba, 0xc01b19a7,
+ 0x3c457f21, 0xc01bd3d6, 0x3c38f3ac, 0xc01c907c,
+ 0x3c2c685d, 0xc01d4f99, 0x3c1fdd34, 0xc01e112b,
+ 0x3c135231, 0xc01ed535, 0x3c06c754, 0xc01f9bb5,
+ 0x3bfa3c9f, 0xc02064ab, 0x3bedb212, 0xc0213018,
+ 0x3be127ac, 0xc021fdfb, 0x3bd49d70, 0xc022ce54,
+ 0x3bc8135c, 0xc023a124, 0x3bbb8973, 0xc024766a,
+ 0x3baeffb3, 0xc0254e27, 0x3ba2761e, 0xc0262859,
+ 0x3b95ecb4, 0xc0270502, 0x3b896375, 0xc027e421,
+ 0x3b7cda63, 0xc028c5b6, 0x3b70517d, 0xc029a9c1,
+ 0x3b63c8c4, 0xc02a9042, 0x3b574039, 0xc02b7939,
+ 0x3b4ab7db, 0xc02c64a6, 0x3b3e2fac, 0xc02d5289,
+ 0x3b31a7ac, 0xc02e42e2, 0x3b251fdc, 0xc02f35b1,
+ 0x3b18983b, 0xc0302af5, 0x3b0c10cb, 0xc03122b0,
+ 0x3aff898c, 0xc0321ce0, 0x3af3027e, 0xc0331986,
+ 0x3ae67ba2, 0xc03418a2, 0x3ad9f4f8, 0xc0351a33,
+ 0x3acd6e81, 0xc0361e3a, 0x3ac0e83d, 0xc03724b6,
+ 0x3ab4622d, 0xc0382da8, 0x3aa7dc52, 0xc0393910,
+ 0x3a9b56ab, 0xc03a46ed, 0x3a8ed139, 0xc03b573f,
+ 0x3a824bfd, 0xc03c6a07, 0x3a75c6f8, 0xc03d7f44,
+ 0x3a694229, 0xc03e96f6, 0x3a5cbd91, 0xc03fb11d,
+ 0x3a503930, 0xc040cdba, 0x3a43b508, 0xc041eccc,
+ 0x3a373119, 0xc0430e53, 0x3a2aad62, 0xc044324f,
+ 0x3a1e29e5, 0xc04558c0, 0x3a11a6a3, 0xc04681a6,
+ 0x3a05239a, 0xc047ad01, 0x39f8a0cd, 0xc048dad1,
+ 0x39ec1e3b, 0xc04a0b16, 0x39df9be6, 0xc04b3dcf,
+ 0x39d319cc, 0xc04c72fe, 0x39c697f0, 0xc04daaa1,
+ 0x39ba1651, 0xc04ee4b8, 0x39ad94f0, 0xc0502145,
+ 0x39a113cd, 0xc0516045, 0x399492ea, 0xc052a1bb,
+ 0x39881245, 0xc053e5a5, 0x397b91e1, 0xc0552c03,
+ 0x396f11bc, 0xc05674d6, 0x396291d9, 0xc057c01d,
+ 0x39561237, 0xc0590dd8, 0x394992d7, 0xc05a5e07,
+ 0x393d13b8, 0xc05bb0ab, 0x393094dd, 0xc05d05c3,
+ 0x39241645, 0xc05e5d4e, 0x391797f0, 0xc05fb74e,
+ 0x390b19e0, 0xc06113c2, 0x38fe9c15, 0xc06272aa,
+ 0x38f21e8e, 0xc063d405, 0x38e5a14d, 0xc06537d4,
+ 0x38d92452, 0xc0669e18, 0x38cca79e, 0xc06806ce,
+ 0x38c02b31, 0xc06971f9, 0x38b3af0c, 0xc06adf97,
+ 0x38a7332e, 0xc06c4fa8, 0x389ab799, 0xc06dc22e,
+ 0x388e3c4d, 0xc06f3726, 0x3881c14b, 0xc070ae92,
+ 0x38754692, 0xc0722871, 0x3868cc24, 0xc073a4c3,
+ 0x385c5201, 0xc0752389, 0x384fd829, 0xc076a4c2,
+ 0x38435e9d, 0xc078286e, 0x3836e55d, 0xc079ae8c,
+ 0x382a6c6a, 0xc07b371e, 0x381df3c5, 0xc07cc223,
+ 0x38117b6d, 0xc07e4f9b, 0x38050364, 0xc07fdf85,
+ 0x37f88ba9, 0xc08171e2, 0x37ec143e, 0xc08306b2,
+ 0x37df9d22, 0xc0849df4, 0x37d32657, 0xc08637a9,
+ 0x37c6afdc, 0xc087d3d0, 0x37ba39b3, 0xc089726a,
+ 0x37adc3db, 0xc08b1376, 0x37a14e55, 0xc08cb6f5,
+ 0x3794d922, 0xc08e5ce5, 0x37886442, 0xc0900548,
+ 0x377befb5, 0xc091b01d, 0x376f7b7d, 0xc0935d64,
+ 0x37630799, 0xc0950d1d, 0x3756940a, 0xc096bf48,
+ 0x374a20d0, 0xc09873e4, 0x373daded, 0xc09a2af3,
+ 0x37313b60, 0xc09be473, 0x3724c92a, 0xc09da065,
+ 0x3718574b, 0xc09f5ec8, 0x370be5c4, 0xc0a11f9d,
+ 0x36ff7496, 0xc0a2e2e3, 0x36f303c0, 0xc0a4a89b,
+ 0x36e69344, 0xc0a670c4, 0x36da2321, 0xc0a83b5e,
+ 0x36cdb359, 0xc0aa086a, 0x36c143ec, 0xc0abd7e6,
+ 0x36b4d4d9, 0xc0ada9d4, 0x36a86623, 0xc0af7e33,
+ 0x369bf7c9, 0xc0b15502, 0x368f89cb, 0xc0b32e42,
+ 0x36831c2b, 0xc0b509f3, 0x3676aee8, 0xc0b6e815,
+ 0x366a4203, 0xc0b8c8a7, 0x365dd57d, 0xc0baabaa,
+ 0x36516956, 0xc0bc911d, 0x3644fd8f, 0xc0be7901,
+ 0x36389228, 0xc0c06355, 0x362c2721, 0xc0c25019,
+ 0x361fbc7b, 0xc0c43f4d, 0x36135237, 0xc0c630f2,
+ 0x3606e854, 0xc0c82506, 0x35fa7ed4, 0xc0ca1b8a,
+ 0x35ee15b7, 0xc0cc147f, 0x35e1acfd, 0xc0ce0fe3,
+ 0x35d544a7, 0xc0d00db6, 0x35c8dcb6, 0xc0d20dfa,
+ 0x35bc7529, 0xc0d410ad, 0x35b00e02, 0xc0d615cf,
+ 0x35a3a740, 0xc0d81d61, 0x359740e5, 0xc0da2762,
+ 0x358adaf0, 0xc0dc33d2, 0x357e7563, 0xc0de42b2,
+ 0x3572103d, 0xc0e05401, 0x3565ab80, 0xc0e267be,
+ 0x3559472b, 0xc0e47deb, 0x354ce33f, 0xc0e69686,
+ 0x35407fbd, 0xc0e8b190, 0x35341ca5, 0xc0eacf09,
+ 0x3527b9f7, 0xc0eceef1, 0x351b57b5, 0xc0ef1147,
+ 0x350ef5de, 0xc0f1360b, 0x35029473, 0xc0f35d3e,
+ 0x34f63374, 0xc0f586df, 0x34e9d2e3, 0xc0f7b2ee,
+ 0x34dd72be, 0xc0f9e16b, 0x34d11308, 0xc0fc1257,
+ 0x34c4b3c0, 0xc0fe45b0, 0x34b854e7, 0xc1007b77,
+ 0x34abf67e, 0xc102b3ac, 0x349f9884, 0xc104ee4f,
+ 0x34933afa, 0xc1072b5f, 0x3486dde1, 0xc1096add,
+ 0x347a8139, 0xc10bacc8, 0x346e2504, 0xc10df120,
+ 0x3461c940, 0xc11037e6, 0x34556def, 0xc1128119,
+ 0x34491311, 0xc114ccb9, 0x343cb8a7, 0xc1171ac6,
+ 0x34305eb0, 0xc1196b3f, 0x3424052f, 0xc11bbe26,
+ 0x3417ac22, 0xc11e1379, 0x340b538b, 0xc1206b39,
+ 0x33fefb6a, 0xc122c566, 0x33f2a3bf, 0xc12521ff,
+ 0x33e64c8c, 0xc1278104, 0x33d9f5cf, 0xc129e276,
+ 0x33cd9f8b, 0xc12c4653, 0x33c149bf, 0xc12eac9d,
+ 0x33b4f46c, 0xc1311553, 0x33a89f92, 0xc1338075,
+ 0x339c4b32, 0xc135ee02, 0x338ff74d, 0xc1385dfb,
+ 0x3383a3e2, 0xc13ad060, 0x337750f2, 0xc13d4530,
+ 0x336afe7e, 0xc13fbc6c, 0x335eac86, 0xc1423613,
+ 0x33525b0b, 0xc144b225, 0x33460a0d, 0xc14730a3,
+ 0x3339b98d, 0xc149b18b, 0x332d698a, 0xc14c34df,
+ 0x33211a07, 0xc14eba9d, 0x3314cb02, 0xc15142c6,
+ 0x33087c7d, 0xc153cd5a, 0x32fc2e77, 0xc1565a58,
+ 0x32efe0f2, 0xc158e9c1, 0x32e393ef, 0xc15b7b94,
+ 0x32d7476c, 0xc15e0fd1, 0x32cafb6b, 0xc160a678,
+ 0x32beafed, 0xc1633f8a, 0x32b264f2, 0xc165db05,
+ 0x32a61a7a, 0xc16878eb, 0x3299d085, 0xc16b193a,
+ 0x328d8715, 0xc16dbbf3, 0x32813e2a, 0xc1706115,
+ 0x3274f5c3, 0xc17308a1, 0x3268ade3, 0xc175b296,
+ 0x325c6688, 0xc1785ef4, 0x32501fb5, 0xc17b0dbb,
+ 0x3243d968, 0xc17dbeec, 0x323793a3, 0xc1807285,
+ 0x322b4e66, 0xc1832888, 0x321f09b1, 0xc185e0f3,
+ 0x3212c585, 0xc1889bc6, 0x320681e3, 0xc18b5903,
+ 0x31fa3ecb, 0xc18e18a7, 0x31edfc3d, 0xc190dab4,
+ 0x31e1ba3a, 0xc1939f29, 0x31d578c2, 0xc1966606,
+ 0x31c937d6, 0xc1992f4c, 0x31bcf777, 0xc19bfaf9,
+ 0x31b0b7a4, 0xc19ec90d, 0x31a4785e, 0xc1a1998a,
+ 0x319839a6, 0xc1a46c6e, 0x318bfb7d, 0xc1a741b9,
+ 0x317fbde2, 0xc1aa196c, 0x317380d6, 0xc1acf386,
+ 0x31674459, 0xc1afd007, 0x315b086d, 0xc1b2aef0,
+ 0x314ecd11, 0xc1b5903f, 0x31429247, 0xc1b873f5,
+ 0x3136580d, 0xc1bb5a11, 0x312a1e66, 0xc1be4294,
+ 0x311de551, 0xc1c12d7e, 0x3111accf, 0xc1c41ace,
+ 0x310574e0, 0xc1c70a84, 0x30f93d86, 0xc1c9fca0,
+ 0x30ed06bf, 0xc1ccf122, 0x30e0d08d, 0xc1cfe80a,
+ 0x30d49af1, 0xc1d2e158, 0x30c865ea, 0xc1d5dd0c,
+ 0x30bc317a, 0xc1d8db25, 0x30affda0, 0xc1dbdba3,
+ 0x30a3ca5d, 0xc1dede87, 0x309797b2, 0xc1e1e3d0,
+ 0x308b659f, 0xc1e4eb7e, 0x307f3424, 0xc1e7f591,
+ 0x30730342, 0xc1eb0209, 0x3066d2fa, 0xc1ee10e5,
+ 0x305aa34c, 0xc1f12227, 0x304e7438, 0xc1f435cc,
+ 0x304245c0, 0xc1f74bd6, 0x303617e2, 0xc1fa6445,
+ 0x3029eaa1, 0xc1fd7f17, 0x301dbdfb, 0xc2009c4e,
+ 0x301191f3, 0xc203bbe8, 0x30056687, 0xc206dde6,
+ 0x2ff93bba, 0xc20a0248, 0x2fed118a, 0xc20d290d,
+ 0x2fe0e7f9, 0xc2105236, 0x2fd4bf08, 0xc2137dc2,
+ 0x2fc896b5, 0xc216abb1, 0x2fbc6f03, 0xc219dc03,
+ 0x2fb047f2, 0xc21d0eb8, 0x2fa42181, 0xc22043d0,
+ 0x2f97fbb2, 0xc2237b4b, 0x2f8bd685, 0xc226b528,
+ 0x2f7fb1fa, 0xc229f167, 0x2f738e12, 0xc22d3009,
+ 0x2f676ace, 0xc230710d, 0x2f5b482d, 0xc233b473,
+ 0x2f4f2630, 0xc236fa3b, 0x2f4304d8, 0xc23a4265,
+ 0x2f36e426, 0xc23d8cf1, 0x2f2ac419, 0xc240d9de,
+ 0x2f1ea4b2, 0xc244292c, 0x2f1285f2, 0xc2477adc,
+ 0x2f0667d9, 0xc24aceed, 0x2efa4a67, 0xc24e255e,
+ 0x2eee2d9d, 0xc2517e31, 0x2ee2117c, 0xc254d965,
+ 0x2ed5f604, 0xc25836f9, 0x2ec9db35, 0xc25b96ee,
+ 0x2ebdc110, 0xc25ef943, 0x2eb1a796, 0xc2625df8,
+ 0x2ea58ec6, 0xc265c50e, 0x2e9976a1, 0xc2692e83,
+ 0x2e8d5f29, 0xc26c9a58, 0x2e81485c, 0xc270088e,
+ 0x2e75323c, 0xc2737922, 0x2e691cc9, 0xc276ec16,
+ 0x2e5d0804, 0xc27a616a, 0x2e50f3ed, 0xc27dd91c,
+ 0x2e44e084, 0xc281532e, 0x2e38cdcb, 0xc284cf9f,
+ 0x2e2cbbc1, 0xc2884e6e, 0x2e20aa67, 0xc28bcf9c,
+ 0x2e1499bd, 0xc28f5329, 0x2e0889c4, 0xc292d914,
+ 0x2dfc7a7c, 0xc296615d, 0x2df06be6, 0xc299ec05,
+ 0x2de45e03, 0xc29d790a, 0x2dd850d2, 0xc2a1086d,
+ 0x2dcc4454, 0xc2a49a2e, 0x2dc0388a, 0xc2a82e4d,
+ 0x2db42d74, 0xc2abc4c9, 0x2da82313, 0xc2af5da2,
+ 0x2d9c1967, 0xc2b2f8d8, 0x2d901070, 0xc2b6966c,
+ 0x2d84082f, 0xc2ba365c, 0x2d7800a5, 0xc2bdd8a9,
+ 0x2d6bf9d1, 0xc2c17d52, 0x2d5ff3b5, 0xc2c52459,
+ 0x2d53ee51, 0xc2c8cdbb, 0x2d47e9a5, 0xc2cc7979,
+ 0x2d3be5b1, 0xc2d02794, 0x2d2fe277, 0xc2d3d80a,
+ 0x2d23dff7, 0xc2d78add, 0x2d17de31, 0xc2db400a,
+ 0x2d0bdd25, 0xc2def794, 0x2cffdcd4, 0xc2e2b178,
+ 0x2cf3dd3f, 0xc2e66db8, 0x2ce7de66, 0xc2ea2c53,
+ 0x2cdbe04a, 0xc2eded49, 0x2ccfe2ea, 0xc2f1b099,
+ 0x2cc3e648, 0xc2f57644, 0x2cb7ea63, 0xc2f93e4a,
+ 0x2cabef3d, 0xc2fd08a9, 0x2c9ff4d6, 0xc300d563,
+ 0x2c93fb2e, 0xc304a477, 0x2c880245, 0xc30875e5,
+ 0x2c7c0a1d, 0xc30c49ad, 0x2c7012b5, 0xc3101fce,
+ 0x2c641c0e, 0xc313f848, 0x2c582629, 0xc317d31c,
+ 0x2c4c3106, 0xc31bb049, 0x2c403ca5, 0xc31f8fcf,
+ 0x2c344908, 0xc32371ae, 0x2c28562d, 0xc32755e5,
+ 0x2c1c6417, 0xc32b3c75, 0x2c1072c4, 0xc32f255e,
+ 0x2c048237, 0xc333109e, 0x2bf8926f, 0xc336fe37,
+ 0x2beca36c, 0xc33aee27, 0x2be0b52f, 0xc33ee070,
+ 0x2bd4c7ba, 0xc342d510, 0x2bc8db0b, 0xc346cc07,
+ 0x2bbcef23, 0xc34ac556, 0x2bb10404, 0xc34ec0fc,
+ 0x2ba519ad, 0xc352bef9, 0x2b99301f, 0xc356bf4d,
+ 0x2b8d475b, 0xc35ac1f7, 0x2b815f60, 0xc35ec6f8,
+ 0x2b75782f, 0xc362ce50, 0x2b6991ca, 0xc366d7fd,
+ 0x2b5dac2f, 0xc36ae401, 0x2b51c760, 0xc36ef25b,
+ 0x2b45e35d, 0xc373030a, 0x2b3a0027, 0xc377160f,
+ 0x2b2e1dbe, 0xc37b2b6a, 0x2b223c22, 0xc37f4319,
+ 0x2b165b54, 0xc3835d1e, 0x2b0a7b54, 0xc3877978,
+ 0x2afe9c24, 0xc38b9827, 0x2af2bdc3, 0xc38fb92a,
+ 0x2ae6e031, 0xc393dc82, 0x2adb0370, 0xc398022f,
+ 0x2acf277f, 0xc39c2a2f, 0x2ac34c60, 0xc3a05484,
+ 0x2ab77212, 0xc3a4812c, 0x2aab9896, 0xc3a8b028,
+ 0x2a9fbfed, 0xc3ace178, 0x2a93e817, 0xc3b1151b,
+ 0x2a881114, 0xc3b54b11, 0x2a7c3ae5, 0xc3b9835a,
+ 0x2a70658a, 0xc3bdbdf6, 0x2a649105, 0xc3c1fae5,
+ 0x2a58bd54, 0xc3c63a26, 0x2a4cea79, 0xc3ca7bba,
+ 0x2a411874, 0xc3cebfa0, 0x2a354746, 0xc3d305d8,
+ 0x2a2976ef, 0xc3d74e62, 0x2a1da770, 0xc3db993e,
+ 0x2a11d8c8, 0xc3dfe66c, 0x2a060af9, 0xc3e435ea,
+ 0x29fa3e03, 0xc3e887bb, 0x29ee71e6, 0xc3ecdbdc,
+ 0x29e2a6a3, 0xc3f1324e, 0x29d6dc3b, 0xc3f58b10,
+ 0x29cb12ad, 0xc3f9e624, 0x29bf49fa, 0xc3fe4388,
+ 0x29b38223, 0xc402a33c, 0x29a7bb28, 0xc4070540,
+ 0x299bf509, 0xc40b6994, 0x29902fc7, 0xc40fd037,
+ 0x29846b63, 0xc414392b, 0x2978a7dd, 0xc418a46d,
+ 0x296ce535, 0xc41d11ff, 0x2961236c, 0xc42181e0,
+ 0x29556282, 0xc425f410, 0x2949a278, 0xc42a688f,
+ 0x293de34e, 0xc42edf5c, 0x29322505, 0xc4335877,
+ 0x2926679c, 0xc437d3e1, 0x291aab16, 0xc43c5199,
+ 0x290eef71, 0xc440d19e, 0x290334af, 0xc44553f2,
+ 0x28f77acf, 0xc449d892, 0x28ebc1d3, 0xc44e5f80,
+ 0x28e009ba, 0xc452e8bc, 0x28d45286, 0xc4577444,
+ 0x28c89c37, 0xc45c0219, 0x28bce6cd, 0xc460923b,
+ 0x28b13248, 0xc46524a9, 0x28a57ea9, 0xc469b963,
+ 0x2899cbf1, 0xc46e5069, 0x288e1a20, 0xc472e9bc,
+ 0x28826936, 0xc477855a, 0x2876b934, 0xc47c2344,
+ 0x286b0a1a, 0xc480c379, 0x285f5be9, 0xc48565f9,
+ 0x2853aea1, 0xc48a0ac4, 0x28480243, 0xc48eb1db,
+ 0x283c56cf, 0xc4935b3c, 0x2830ac45, 0xc49806e7,
+ 0x282502a7, 0xc49cb4dd, 0x281959f4, 0xc4a1651c,
+ 0x280db22d, 0xc4a617a6, 0x28020b52, 0xc4aacc7a,
+ 0x27f66564, 0xc4af8397, 0x27eac063, 0xc4b43cfd,
+ 0x27df1c50, 0xc4b8f8ad, 0x27d3792b, 0xc4bdb6a6,
+ 0x27c7d6f4, 0xc4c276e8, 0x27bc35ad, 0xc4c73972,
+ 0x27b09555, 0xc4cbfe45, 0x27a4f5ed, 0xc4d0c560,
+ 0x27995776, 0xc4d58ec3, 0x278db9ef, 0xc4da5a6f,
+ 0x27821d59, 0xc4df2862, 0x277681b6, 0xc4e3f89c,
+ 0x276ae704, 0xc4e8cb1e, 0x275f4d45, 0xc4ed9fe7,
+ 0x2753b479, 0xc4f276f7, 0x27481ca1, 0xc4f7504e,
+ 0x273c85bc, 0xc4fc2bec, 0x2730efcc, 0xc50109d0,
+ 0x27255ad1, 0xc505e9fb, 0x2719c6cb, 0xc50acc6b,
+ 0x270e33bb, 0xc50fb121, 0x2702a1a1, 0xc514981d,
+ 0x26f7107e, 0xc519815f, 0x26eb8052, 0xc51e6ce6,
+ 0x26dff11d, 0xc5235ab2, 0x26d462e1, 0xc5284ac3,
+ 0x26c8d59c, 0xc52d3d18, 0x26bd4951, 0xc53231b3,
+ 0x26b1bdff, 0xc5372891, 0x26a633a6, 0xc53c21b4,
+ 0x269aaa48, 0xc5411d1b, 0x268f21e5, 0xc5461ac6,
+ 0x26839a7c, 0xc54b1ab4, 0x26781410, 0xc5501ce5,
+ 0x266c8e9f, 0xc555215a, 0x26610a2a, 0xc55a2812,
+ 0x265586b3, 0xc55f310d, 0x264a0438, 0xc5643c4a,
+ 0x263e82bc, 0xc56949ca, 0x2633023e, 0xc56e598c,
+ 0x262782be, 0xc5736b90, 0x261c043d, 0xc5787fd6,
+ 0x261086bc, 0xc57d965d, 0x26050a3b, 0xc582af26,
+ 0x25f98ebb, 0xc587ca31, 0x25ee143b, 0xc58ce77c,
+ 0x25e29abc, 0xc5920708, 0x25d72240, 0xc59728d5,
+ 0x25cbaac5, 0xc59c4ce3, 0x25c0344d, 0xc5a17330,
+ 0x25b4bed8, 0xc5a69bbe, 0x25a94a67, 0xc5abc68c,
+ 0x259dd6f9, 0xc5b0f399, 0x25926490, 0xc5b622e6,
+ 0x2586f32c, 0xc5bb5472, 0x257b82cd, 0xc5c0883d,
+ 0x25701374, 0xc5c5be47, 0x2564a521, 0xc5caf690,
+ 0x255937d5, 0xc5d03118, 0x254dcb8f, 0xc5d56ddd,
+ 0x25426051, 0xc5daace1, 0x2536f61b, 0xc5dfee22,
+ 0x252b8cee, 0xc5e531a1, 0x252024c9, 0xc5ea775e,
+ 0x2514bdad, 0xc5efbf58, 0x2509579b, 0xc5f5098f,
+ 0x24fdf294, 0xc5fa5603, 0x24f28e96, 0xc5ffa4b3,
+ 0x24e72ba4, 0xc604f5a0, 0x24dbc9bd, 0xc60a48c9,
+ 0x24d068e2, 0xc60f9e2e, 0x24c50914, 0xc614f5cf,
+ 0x24b9aa52, 0xc61a4fac, 0x24ae4c9d, 0xc61fabc4,
+ 0x24a2eff6, 0xc6250a18, 0x2497945d, 0xc62a6aa6,
+ 0x248c39d3, 0xc62fcd6f, 0x2480e057, 0xc6353273,
+ 0x247587eb, 0xc63a99b1, 0x246a308f, 0xc6400329,
+ 0x245eda43, 0xc6456edb, 0x24538507, 0xc64adcc7,
+ 0x244830dd, 0xc6504ced, 0x243cddc4, 0xc655bf4c,
+ 0x24318bbe, 0xc65b33e4, 0x24263ac9, 0xc660aab5,
+ 0x241aeae8, 0xc66623be, 0x240f9c1a, 0xc66b9f01,
+ 0x24044e60, 0xc6711c7b, 0x23f901ba, 0xc6769c2e,
+ 0x23edb628, 0xc67c1e18, 0x23e26bac, 0xc681a23a,
+ 0x23d72245, 0xc6872894, 0x23cbd9f4, 0xc68cb124,
+ 0x23c092b9, 0xc6923bec, 0x23b54c95, 0xc697c8eb,
+ 0x23aa0788, 0xc69d5820, 0x239ec393, 0xc6a2e98b,
+ 0x239380b6, 0xc6a87d2d, 0x23883ef2, 0xc6ae1304,
+ 0x237cfe47, 0xc6b3ab12, 0x2371beb5, 0xc6b94554,
+ 0x2366803c, 0xc6bee1cd, 0x235b42df, 0xc6c4807a,
+ 0x2350069b, 0xc6ca215c, 0x2344cb73, 0xc6cfc472,
+ 0x23399167, 0xc6d569be, 0x232e5876, 0xc6db113d,
+ 0x232320a2, 0xc6e0baf0, 0x2317e9eb, 0xc6e666d7,
+ 0x230cb451, 0xc6ec14f2, 0x23017fd5, 0xc6f1c540,
+ 0x22f64c77, 0xc6f777c1, 0x22eb1a37, 0xc6fd2c75,
+ 0x22dfe917, 0xc702e35c, 0x22d4b916, 0xc7089c75,
+ 0x22c98a35, 0xc70e57c0, 0x22be5c74, 0xc714153e,
+ 0x22b32fd4, 0xc719d4ed, 0x22a80456, 0xc71f96ce,
+ 0x229cd9f8, 0xc7255ae0, 0x2291b0bd, 0xc72b2123,
+ 0x228688a4, 0xc730e997, 0x227b61af, 0xc736b43c,
+ 0x22703bdc, 0xc73c8111, 0x2265172e, 0xc7425016,
+ 0x2259f3a3, 0xc748214c, 0x224ed13d, 0xc74df4b1,
+ 0x2243affc, 0xc753ca46, 0x22388fe1, 0xc759a20a,
+ 0x222d70eb, 0xc75f7bfe, 0x2222531c, 0xc7655820,
+ 0x22173674, 0xc76b3671, 0x220c1af3, 0xc77116f0,
+ 0x22010099, 0xc776f99d, 0x21f5e768, 0xc77cde79,
+ 0x21eacf5f, 0xc782c582, 0x21dfb87f, 0xc788aeb9,
+ 0x21d4a2c8, 0xc78e9a1d, 0x21c98e3b, 0xc79487ae,
+ 0x21be7ad8, 0xc79a776c, 0x21b368a0, 0xc7a06957,
+ 0x21a85793, 0xc7a65d6e, 0x219d47b1, 0xc7ac53b1,
+ 0x219238fb, 0xc7b24c20, 0x21872b72, 0xc7b846ba,
+ 0x217c1f15, 0xc7be4381, 0x217113e5, 0xc7c44272,
+ 0x216609e3, 0xc7ca438f, 0x215b0110, 0xc7d046d6,
+ 0x214ff96a, 0xc7d64c47, 0x2144f2f3, 0xc7dc53e3,
+ 0x2139edac, 0xc7e25daa, 0x212ee995, 0xc7e8699a,
+ 0x2123e6ad, 0xc7ee77b3, 0x2118e4f6, 0xc7f487f6,
+ 0x210de470, 0xc7fa9a62, 0x2102e51c, 0xc800aef7,
+ 0x20f7e6f9, 0xc806c5b5, 0x20ecea09, 0xc80cde9b,
+ 0x20e1ee4b, 0xc812f9a9, 0x20d6f3c1, 0xc81916df,
+ 0x20cbfa6a, 0xc81f363d, 0x20c10247, 0xc82557c3,
+ 0x20b60b58, 0xc82b7b70, 0x20ab159e, 0xc831a143,
+ 0x20a0211a, 0xc837c93e, 0x20952dcb, 0xc83df35f,
+ 0x208a3bb2, 0xc8441fa6, 0x207f4acf, 0xc84a4e14,
+ 0x20745b24, 0xc8507ea7, 0x20696cb0, 0xc856b160,
+ 0x205e7f74, 0xc85ce63e, 0x2053936f, 0xc8631d42,
+ 0x2048a8a4, 0xc869566a, 0x203dbf11, 0xc86f91b7,
+ 0x2032d6b8, 0xc875cf28, 0x2027ef99, 0xc87c0ebd,
+ 0x201d09b4, 0xc8825077, 0x2012250a, 0xc8889454,
+ 0x2007419b, 0xc88eda54, 0x1ffc5f67, 0xc8952278,
+ 0x1ff17e70, 0xc89b6cbf, 0x1fe69eb4, 0xc8a1b928,
+ 0x1fdbc036, 0xc8a807b4, 0x1fd0e2f5, 0xc8ae5862,
+ 0x1fc606f1, 0xc8b4ab32, 0x1fbb2c2c, 0xc8bb0023,
+ 0x1fb052a5, 0xc8c15736, 0x1fa57a5d, 0xc8c7b06b,
+ 0x1f9aa354, 0xc8ce0bc0, 0x1f8fcd8b, 0xc8d46936,
+ 0x1f84f902, 0xc8dac8cd, 0x1f7a25ba, 0xc8e12a84,
+ 0x1f6f53b3, 0xc8e78e5b, 0x1f6482ed, 0xc8edf452,
+ 0x1f59b369, 0xc8f45c68, 0x1f4ee527, 0xc8fac69e,
+ 0x1f441828, 0xc90132f2, 0x1f394c6b, 0xc907a166,
+ 0x1f2e81f3, 0xc90e11f7, 0x1f23b8be, 0xc91484a8,
+ 0x1f18f0ce, 0xc91af976, 0x1f0e2a22, 0xc9217062,
+ 0x1f0364bc, 0xc927e96b, 0x1ef8a09b, 0xc92e6492,
+ 0x1eedddc0, 0xc934e1d6, 0x1ee31c2b, 0xc93b6137,
+ 0x1ed85bdd, 0xc941e2b4, 0x1ecd9cd7, 0xc948664d,
+ 0x1ec2df18, 0xc94eec03, 0x1eb822a1, 0xc95573d4,
+ 0x1ead6773, 0xc95bfdc1, 0x1ea2ad8d, 0xc96289c9,
+ 0x1e97f4f1, 0xc96917ec, 0x1e8d3d9e, 0xc96fa82a,
+ 0x1e828796, 0xc9763a83, 0x1e77d2d8, 0xc97ccef5,
+ 0x1e6d1f65, 0xc9836582, 0x1e626d3e, 0xc989fe29,
+ 0x1e57bc62, 0xc99098e9, 0x1e4d0cd2, 0xc99735c2,
+ 0x1e425e8f, 0xc99dd4b4, 0x1e37b199, 0xc9a475bf,
+ 0x1e2d05f1, 0xc9ab18e3, 0x1e225b96, 0xc9b1be1e,
+ 0x1e17b28a, 0xc9b86572, 0x1e0d0acc, 0xc9bf0edd,
+ 0x1e02645d, 0xc9c5ba60, 0x1df7bf3e, 0xc9cc67fa,
+ 0x1ded1b6e, 0xc9d317ab, 0x1de278ef, 0xc9d9c973,
+ 0x1dd7d7c1, 0xc9e07d51, 0x1dcd37e4, 0xc9e73346,
+ 0x1dc29958, 0xc9edeb50, 0x1db7fc1e, 0xc9f4a570,
+ 0x1dad6036, 0xc9fb61a5, 0x1da2c5a2, 0xca021fef,
+ 0x1d982c60, 0xca08e04f, 0x1d8d9472, 0xca0fa2c3,
+ 0x1d82fdd8, 0xca16674b, 0x1d786892, 0xca1d2de7,
+ 0x1d6dd4a2, 0xca23f698, 0x1d634206, 0xca2ac15b,
+ 0x1d58b0c0, 0xca318e32, 0x1d4e20d0, 0xca385d1d,
+ 0x1d439236, 0xca3f2e19, 0x1d3904f4, 0xca460129,
+ 0x1d2e7908, 0xca4cd64b, 0x1d23ee74, 0xca53ad7e,
+ 0x1d196538, 0xca5a86c4, 0x1d0edd55, 0xca61621b,
+ 0x1d0456ca, 0xca683f83, 0x1cf9d199, 0xca6f1efc,
+ 0x1cef4dc2, 0xca760086, 0x1ce4cb44, 0xca7ce420,
+ 0x1cda4a21, 0xca83c9ca, 0x1ccfca59, 0xca8ab184,
+ 0x1cc54bec, 0xca919b4e, 0x1cbacedb, 0xca988727,
+ 0x1cb05326, 0xca9f750f, 0x1ca5d8cd, 0xcaa66506,
+ 0x1c9b5fd2, 0xcaad570c, 0x1c90e834, 0xcab44b1f,
+ 0x1c8671f3, 0xcabb4141, 0x1c7bfd11, 0xcac23971,
+ 0x1c71898d, 0xcac933ae, 0x1c671768, 0xcad02ff8,
+ 0x1c5ca6a2, 0xcad72e4f, 0x1c52373c, 0xcade2eb3,
+ 0x1c47c936, 0xcae53123, 0x1c3d5c91, 0xcaec35a0,
+ 0x1c32f14d, 0xcaf33c28, 0x1c28876a, 0xcafa44bc,
+ 0x1c1e1ee9, 0xcb014f5b, 0x1c13b7c9, 0xcb085c05,
+ 0x1c09520d, 0xcb0f6aba, 0x1bfeedb3, 0xcb167b79,
+ 0x1bf48abd, 0xcb1d8e43, 0x1bea292b, 0xcb24a316,
+ 0x1bdfc8fc, 0xcb2bb9f4, 0x1bd56a32, 0xcb32d2da,
+ 0x1bcb0cce, 0xcb39edca, 0x1bc0b0ce, 0xcb410ac3,
+ 0x1bb65634, 0xcb4829c4, 0x1babfd01, 0xcb4f4acd,
+ 0x1ba1a534, 0xcb566ddf, 0x1b974ece, 0xcb5d92f8,
+ 0x1b8cf9cf, 0xcb64ba19, 0x1b82a638, 0xcb6be341,
+ 0x1b785409, 0xcb730e70, 0x1b6e0342, 0xcb7a3ba5,
+ 0x1b63b3e5, 0xcb816ae1, 0x1b5965f1, 0xcb889c23,
+ 0x1b4f1967, 0xcb8fcf6b, 0x1b44ce46, 0xcb9704b9,
+ 0x1b3a8491, 0xcb9e3c0b, 0x1b303c46, 0xcba57563,
+ 0x1b25f566, 0xcbacb0bf, 0x1b1baff2, 0xcbb3ee20,
+ 0x1b116beb, 0xcbbb2d85, 0x1b072950, 0xcbc26eee,
+ 0x1afce821, 0xcbc9b25a, 0x1af2a860, 0xcbd0f7ca,
+ 0x1ae86a0d, 0xcbd83f3d, 0x1ade2d28, 0xcbdf88b3,
+ 0x1ad3f1b1, 0xcbe6d42b, 0x1ac9b7a9, 0xcbee21a5,
+ 0x1abf7f11, 0xcbf57121, 0x1ab547e8, 0xcbfcc29f,
+ 0x1aab122f, 0xcc04161e, 0x1aa0dde7, 0xcc0b6b9e,
+ 0x1a96ab0f, 0xcc12c31f, 0x1a8c79a9, 0xcc1a1ca0,
+ 0x1a8249b4, 0xcc217822, 0x1a781b31, 0xcc28d5a3,
+ 0x1a6dee21, 0xcc303524, 0x1a63c284, 0xcc3796a5,
+ 0x1a599859, 0xcc3efa25, 0x1a4f6fa3, 0xcc465fa3,
+ 0x1a454860, 0xcc4dc720, 0x1a3b2292, 0xcc55309b,
+ 0x1a30fe38, 0xcc5c9c14, 0x1a26db54, 0xcc64098b,
+ 0x1a1cb9e5, 0xcc6b78ff, 0x1a1299ec, 0xcc72ea70,
+ 0x1a087b69, 0xcc7a5dde, 0x19fe5e5e, 0xcc81d349,
+ 0x19f442c9, 0xcc894aaf, 0x19ea28ac, 0xcc90c412,
+ 0x19e01006, 0xcc983f70, 0x19d5f8d9, 0xcc9fbcca,
+ 0x19cbe325, 0xcca73c1e, 0x19c1cee9, 0xccaebd6e,
+ 0x19b7bc27, 0xccb640b8, 0x19adaadf, 0xccbdc5fc,
+ 0x19a39b11, 0xccc54d3a, 0x19998cbe, 0xccccd671,
+ 0x198f7fe6, 0xccd461a2, 0x19857489, 0xccdbeecc,
+ 0x197b6aa8, 0xcce37def, 0x19716243, 0xcceb0f0a,
+ 0x19675b5a, 0xccf2a21d, 0x195d55ef, 0xccfa3729,
+ 0x19535201, 0xcd01ce2b, 0x19494f90, 0xcd096725,
+ 0x193f4e9e, 0xcd110216, 0x19354f2a, 0xcd189efe,
+ 0x192b5135, 0xcd203ddc, 0x192154bf, 0xcd27deb0,
+ 0x191759c9, 0xcd2f817b, 0x190d6053, 0xcd37263a,
+ 0x1903685d, 0xcd3eccef, 0x18f971e8, 0xcd467599,
+ 0x18ef7cf4, 0xcd4e2037, 0x18e58982, 0xcd55ccca,
+ 0x18db9792, 0xcd5d7b50, 0x18d1a724, 0xcd652bcb,
+ 0x18c7b838, 0xcd6cde39, 0x18bdcad0, 0xcd74929a,
+ 0x18b3deeb, 0xcd7c48ee, 0x18a9f48a, 0xcd840134,
+ 0x18a00bae, 0xcd8bbb6d, 0x18962456, 0xcd937798,
+ 0x188c3e83, 0xcd9b35b4, 0x18825a35, 0xcda2f5c2,
+ 0x1878776d, 0xcdaab7c0, 0x186e962b, 0xcdb27bb0,
+ 0x1864b670, 0xcdba4190, 0x185ad83c, 0xcdc20960,
+ 0x1850fb8e, 0xcdc9d320, 0x18472069, 0xcdd19ed0,
+ 0x183d46cc, 0xcdd96c6f, 0x18336eb7, 0xcde13bfd,
+ 0x1829982b, 0xcde90d79, 0x181fc328, 0xcdf0e0e4,
+ 0x1815efae, 0xcdf8b63d, 0x180c1dbf, 0xce008d84,
+ 0x18024d59, 0xce0866b8, 0x17f87e7f, 0xce1041d9,
+ 0x17eeb130, 0xce181ee8, 0x17e4e56c, 0xce1ffde2,
+ 0x17db1b34, 0xce27dec9, 0x17d15288, 0xce2fc19c,
+ 0x17c78b68, 0xce37a65b, 0x17bdc5d6, 0xce3f8d05,
+ 0x17b401d1, 0xce47759a, 0x17aa3f5a, 0xce4f6019,
+ 0x17a07e70, 0xce574c84, 0x1796bf16, 0xce5f3ad8,
+ 0x178d014a, 0xce672b16, 0x1783450d, 0xce6f1d3d,
+ 0x17798a60, 0xce77114e, 0x176fd143, 0xce7f0748,
+ 0x176619b6, 0xce86ff2a, 0x175c63ba, 0xce8ef8f4,
+ 0x1752af4f, 0xce96f4a7, 0x1748fc75, 0xce9ef241,
+ 0x173f4b2e, 0xcea6f1c2, 0x17359b78, 0xceaef32b,
+ 0x172bed55, 0xceb6f67a, 0x172240c5, 0xcebefbb0,
+ 0x171895c9, 0xcec702cb, 0x170eec60, 0xcecf0bcd,
+ 0x1705448b, 0xced716b4, 0x16fb9e4b, 0xcedf2380,
+ 0x16f1f99f, 0xcee73231, 0x16e85689, 0xceef42c7,
+ 0x16deb508, 0xcef75541, 0x16d5151d, 0xceff699f,
+ 0x16cb76c9, 0xcf077fe1, 0x16c1da0b, 0xcf0f9805,
+ 0x16b83ee4, 0xcf17b20d, 0x16aea555, 0xcf1fcdf8,
+ 0x16a50d5d, 0xcf27ebc5, 0x169b76fe, 0xcf300b74,
+ 0x1691e237, 0xcf382d05, 0x16884f09, 0xcf405077,
+ 0x167ebd74, 0xcf4875ca, 0x16752d79, 0xcf509cfe,
+ 0x166b9f18, 0xcf58c613, 0x16621251, 0xcf60f108,
+ 0x16588725, 0xcf691ddd, 0x164efd94, 0xcf714c91,
+ 0x1645759f, 0xcf797d24, 0x163bef46, 0xcf81af97,
+ 0x16326a88, 0xcf89e3e8, 0x1628e767, 0xcf921a17,
+ 0x161f65e4, 0xcf9a5225, 0x1615e5fd, 0xcfa28c10,
+ 0x160c67b4, 0xcfaac7d8, 0x1602eb0a, 0xcfb3057d,
+ 0x15f96ffd, 0xcfbb4500, 0x15eff690, 0xcfc3865e,
+ 0x15e67ec1, 0xcfcbc999, 0x15dd0892, 0xcfd40eaf,
+ 0x15d39403, 0xcfdc55a1, 0x15ca2115, 0xcfe49e6d,
+ 0x15c0afc6, 0xcfece915, 0x15b74019, 0xcff53597,
+ 0x15add20d, 0xcffd83f4, 0x15a465a3, 0xd005d42a,
+ 0x159afadb, 0xd00e2639, 0x159191b5, 0xd0167a22,
+ 0x15882a32, 0xd01ecfe4, 0x157ec452, 0xd027277e,
+ 0x15756016, 0xd02f80f1, 0x156bfd7d, 0xd037dc3b,
+ 0x15629c89, 0xd040395d, 0x15593d3a, 0xd0489856,
+ 0x154fdf8f, 0xd050f926, 0x15468389, 0xd0595bcd,
+ 0x153d292a, 0xd061c04a, 0x1533d070, 0xd06a269d,
+ 0x152a795d, 0xd0728ec6, 0x152123f0, 0xd07af8c4,
+ 0x1517d02b, 0xd0836497, 0x150e7e0d, 0xd08bd23f,
+ 0x15052d97, 0xd09441bb, 0x14fbdec9, 0xd09cb30b,
+ 0x14f291a4, 0xd0a5262f, 0x14e94627, 0xd0ad9b26,
+ 0x14dffc54, 0xd0b611f1, 0x14d6b42b, 0xd0be8a8d,
+ 0x14cd6dab, 0xd0c704fd, 0x14c428d6, 0xd0cf813e,
+ 0x14bae5ab, 0xd0d7ff51, 0x14b1a42c, 0xd0e07f36,
+ 0x14a86458, 0xd0e900ec, 0x149f2630, 0xd0f18472,
+ 0x1495e9b3, 0xd0fa09c9, 0x148caee4, 0xd10290f0,
+ 0x148375c1, 0xd10b19e7, 0x147a3e4b, 0xd113a4ad,
+ 0x14710883, 0xd11c3142, 0x1467d469, 0xd124bfa6,
+ 0x145ea1fd, 0xd12d4fd9, 0x14557140, 0xd135e1d9,
+ 0x144c4232, 0xd13e75a8, 0x144314d3, 0xd1470b44,
+ 0x1439e923, 0xd14fa2ad, 0x1430bf24, 0xd1583be2,
+ 0x142796d5, 0xd160d6e5, 0x141e7037, 0xd16973b3,
+ 0x14154b4a, 0xd172124d, 0x140c280e, 0xd17ab2b3,
+ 0x14030684, 0xd18354e4, 0x13f9e6ad, 0xd18bf8e0,
+ 0x13f0c887, 0xd1949ea6, 0x13e7ac15, 0xd19d4636,
+ 0x13de9156, 0xd1a5ef90, 0x13d5784a, 0xd1ae9ab4,
+ 0x13cc60f2, 0xd1b747a0, 0x13c34b4f, 0xd1bff656,
+ 0x13ba3760, 0xd1c8a6d4, 0x13b12526, 0xd1d1591a,
+ 0x13a814a2, 0xd1da0d28, 0x139f05d3, 0xd1e2c2fd,
+ 0x1395f8ba, 0xd1eb7a9a, 0x138ced57, 0xd1f433fd,
+ 0x1383e3ab, 0xd1fcef27, 0x137adbb6, 0xd205ac17,
+ 0x1371d579, 0xd20e6acc, 0x1368d0f3, 0xd2172b48,
+ 0x135fce26, 0xd21fed88, 0x1356cd11, 0xd228b18d,
+ 0x134dcdb4, 0xd2317756, 0x1344d011, 0xd23a3ee4,
+ 0x133bd427, 0xd2430835, 0x1332d9f7, 0xd24bd34a,
+ 0x1329e181, 0xd254a021, 0x1320eac6, 0xd25d6ebc,
+ 0x1317f5c6, 0xd2663f19, 0x130f0280, 0xd26f1138,
+ 0x130610f7, 0xd277e518, 0x12fd2129, 0xd280babb,
+ 0x12f43318, 0xd289921e, 0x12eb46c3, 0xd2926b41,
+ 0x12e25c2b, 0xd29b4626, 0x12d97350, 0xd2a422ca,
+ 0x12d08c33, 0xd2ad012e, 0x12c7a6d4, 0xd2b5e151,
+ 0x12bec333, 0xd2bec333, 0x12b5e151, 0xd2c7a6d4,
+ 0x12ad012e, 0xd2d08c33, 0x12a422ca, 0xd2d97350,
+ 0x129b4626, 0xd2e25c2b, 0x12926b41, 0xd2eb46c3,
+ 0x1289921e, 0xd2f43318, 0x1280babb, 0xd2fd2129,
+ 0x1277e518, 0xd30610f7, 0x126f1138, 0xd30f0280,
+ 0x12663f19, 0xd317f5c6, 0x125d6ebc, 0xd320eac6,
+ 0x1254a021, 0xd329e181, 0x124bd34a, 0xd332d9f7,
+ 0x12430835, 0xd33bd427, 0x123a3ee4, 0xd344d011,
+ 0x12317756, 0xd34dcdb4, 0x1228b18d, 0xd356cd11,
+ 0x121fed88, 0xd35fce26, 0x12172b48, 0xd368d0f3,
+ 0x120e6acc, 0xd371d579, 0x1205ac17, 0xd37adbb6,
+ 0x11fcef27, 0xd383e3ab, 0x11f433fd, 0xd38ced57,
+ 0x11eb7a9a, 0xd395f8ba, 0x11e2c2fd, 0xd39f05d3,
+ 0x11da0d28, 0xd3a814a2, 0x11d1591a, 0xd3b12526,
+ 0x11c8a6d4, 0xd3ba3760, 0x11bff656, 0xd3c34b4f,
+ 0x11b747a0, 0xd3cc60f2, 0x11ae9ab4, 0xd3d5784a,
+ 0x11a5ef90, 0xd3de9156, 0x119d4636, 0xd3e7ac15,
+ 0x11949ea6, 0xd3f0c887, 0x118bf8e0, 0xd3f9e6ad,
+ 0x118354e4, 0xd4030684, 0x117ab2b3, 0xd40c280e,
+ 0x1172124d, 0xd4154b4a, 0x116973b3, 0xd41e7037,
+ 0x1160d6e5, 0xd42796d5, 0x11583be2, 0xd430bf24,
+ 0x114fa2ad, 0xd439e923, 0x11470b44, 0xd44314d3,
+ 0x113e75a8, 0xd44c4232, 0x1135e1d9, 0xd4557140,
+ 0x112d4fd9, 0xd45ea1fd, 0x1124bfa6, 0xd467d469,
+ 0x111c3142, 0xd4710883, 0x1113a4ad, 0xd47a3e4b,
+ 0x110b19e7, 0xd48375c1, 0x110290f0, 0xd48caee4,
+ 0x10fa09c9, 0xd495e9b3, 0x10f18472, 0xd49f2630,
+ 0x10e900ec, 0xd4a86458, 0x10e07f36, 0xd4b1a42c,
+ 0x10d7ff51, 0xd4bae5ab, 0x10cf813e, 0xd4c428d6,
+ 0x10c704fd, 0xd4cd6dab, 0x10be8a8d, 0xd4d6b42b,
+ 0x10b611f1, 0xd4dffc54, 0x10ad9b26, 0xd4e94627,
+ 0x10a5262f, 0xd4f291a4, 0x109cb30b, 0xd4fbdec9,
+ 0x109441bb, 0xd5052d97, 0x108bd23f, 0xd50e7e0d,
+ 0x10836497, 0xd517d02b, 0x107af8c4, 0xd52123f0,
+ 0x10728ec6, 0xd52a795d, 0x106a269d, 0xd533d070,
+ 0x1061c04a, 0xd53d292a, 0x10595bcd, 0xd5468389,
+ 0x1050f926, 0xd54fdf8f, 0x10489856, 0xd5593d3a,
+ 0x1040395d, 0xd5629c89, 0x1037dc3b, 0xd56bfd7d,
+ 0x102f80f1, 0xd5756016, 0x1027277e, 0xd57ec452,
+ 0x101ecfe4, 0xd5882a32, 0x10167a22, 0xd59191b5,
+ 0x100e2639, 0xd59afadb, 0x1005d42a, 0xd5a465a3,
+ 0xffd83f4, 0xd5add20d, 0xff53597, 0xd5b74019,
+ 0xfece915, 0xd5c0afc6, 0xfe49e6d, 0xd5ca2115,
+ 0xfdc55a1, 0xd5d39403, 0xfd40eaf, 0xd5dd0892,
+ 0xfcbc999, 0xd5e67ec1, 0xfc3865e, 0xd5eff690,
+ 0xfbb4500, 0xd5f96ffd, 0xfb3057d, 0xd602eb0a,
+ 0xfaac7d8, 0xd60c67b4, 0xfa28c10, 0xd615e5fd,
+ 0xf9a5225, 0xd61f65e4, 0xf921a17, 0xd628e767,
+ 0xf89e3e8, 0xd6326a88, 0xf81af97, 0xd63bef46,
+ 0xf797d24, 0xd645759f, 0xf714c91, 0xd64efd94,
+ 0xf691ddd, 0xd6588725, 0xf60f108, 0xd6621251,
+ 0xf58c613, 0xd66b9f18, 0xf509cfe, 0xd6752d79,
+ 0xf4875ca, 0xd67ebd74, 0xf405077, 0xd6884f09,
+ 0xf382d05, 0xd691e237, 0xf300b74, 0xd69b76fe,
+ 0xf27ebc5, 0xd6a50d5d, 0xf1fcdf8, 0xd6aea555,
+ 0xf17b20d, 0xd6b83ee4, 0xf0f9805, 0xd6c1da0b,
+ 0xf077fe1, 0xd6cb76c9, 0xeff699f, 0xd6d5151d,
+ 0xef75541, 0xd6deb508, 0xeef42c7, 0xd6e85689,
+ 0xee73231, 0xd6f1f99f, 0xedf2380, 0xd6fb9e4b,
+ 0xed716b4, 0xd705448b, 0xecf0bcd, 0xd70eec60,
+ 0xec702cb, 0xd71895c9, 0xebefbb0, 0xd72240c5,
+ 0xeb6f67a, 0xd72bed55, 0xeaef32b, 0xd7359b78,
+ 0xea6f1c2, 0xd73f4b2e, 0xe9ef241, 0xd748fc75,
+ 0xe96f4a7, 0xd752af4f, 0xe8ef8f4, 0xd75c63ba,
+ 0xe86ff2a, 0xd76619b6, 0xe7f0748, 0xd76fd143,
+ 0xe77114e, 0xd7798a60, 0xe6f1d3d, 0xd783450d,
+ 0xe672b16, 0xd78d014a, 0xe5f3ad8, 0xd796bf16,
+ 0xe574c84, 0xd7a07e70, 0xe4f6019, 0xd7aa3f5a,
+ 0xe47759a, 0xd7b401d1, 0xe3f8d05, 0xd7bdc5d6,
+ 0xe37a65b, 0xd7c78b68, 0xe2fc19c, 0xd7d15288,
+ 0xe27dec9, 0xd7db1b34, 0xe1ffde2, 0xd7e4e56c,
+ 0xe181ee8, 0xd7eeb130, 0xe1041d9, 0xd7f87e7f,
+ 0xe0866b8, 0xd8024d59, 0xe008d84, 0xd80c1dbf,
+ 0xdf8b63d, 0xd815efae, 0xdf0e0e4, 0xd81fc328,
+ 0xde90d79, 0xd829982b, 0xde13bfd, 0xd8336eb7,
+ 0xdd96c6f, 0xd83d46cc, 0xdd19ed0, 0xd8472069,
+ 0xdc9d320, 0xd850fb8e, 0xdc20960, 0xd85ad83c,
+ 0xdba4190, 0xd864b670, 0xdb27bb0, 0xd86e962b,
+ 0xdaab7c0, 0xd878776d, 0xda2f5c2, 0xd8825a35,
+ 0xd9b35b4, 0xd88c3e83, 0xd937798, 0xd8962456,
+ 0xd8bbb6d, 0xd8a00bae, 0xd840134, 0xd8a9f48a,
+ 0xd7c48ee, 0xd8b3deeb, 0xd74929a, 0xd8bdcad0,
+ 0xd6cde39, 0xd8c7b838, 0xd652bcb, 0xd8d1a724,
+ 0xd5d7b50, 0xd8db9792, 0xd55ccca, 0xd8e58982,
+ 0xd4e2037, 0xd8ef7cf4, 0xd467599, 0xd8f971e8,
+ 0xd3eccef, 0xd903685d, 0xd37263a, 0xd90d6053,
+ 0xd2f817b, 0xd91759c9, 0xd27deb0, 0xd92154bf,
+ 0xd203ddc, 0xd92b5135, 0xd189efe, 0xd9354f2a,
+ 0xd110216, 0xd93f4e9e, 0xd096725, 0xd9494f90,
+ 0xd01ce2b, 0xd9535201, 0xcfa3729, 0xd95d55ef,
+ 0xcf2a21d, 0xd9675b5a, 0xceb0f0a, 0xd9716243,
+ 0xce37def, 0xd97b6aa8, 0xcdbeecc, 0xd9857489,
+ 0xcd461a2, 0xd98f7fe6, 0xcccd671, 0xd9998cbe,
+ 0xcc54d3a, 0xd9a39b11, 0xcbdc5fc, 0xd9adaadf,
+ 0xcb640b8, 0xd9b7bc27, 0xcaebd6e, 0xd9c1cee9,
+ 0xca73c1e, 0xd9cbe325, 0xc9fbcca, 0xd9d5f8d9,
+ 0xc983f70, 0xd9e01006, 0xc90c412, 0xd9ea28ac,
+ 0xc894aaf, 0xd9f442c9, 0xc81d349, 0xd9fe5e5e,
+ 0xc7a5dde, 0xda087b69, 0xc72ea70, 0xda1299ec,
+ 0xc6b78ff, 0xda1cb9e5, 0xc64098b, 0xda26db54,
+ 0xc5c9c14, 0xda30fe38, 0xc55309b, 0xda3b2292,
+ 0xc4dc720, 0xda454860, 0xc465fa3, 0xda4f6fa3,
+ 0xc3efa25, 0xda599859, 0xc3796a5, 0xda63c284,
+ 0xc303524, 0xda6dee21, 0xc28d5a3, 0xda781b31,
+ 0xc217822, 0xda8249b4, 0xc1a1ca0, 0xda8c79a9,
+ 0xc12c31f, 0xda96ab0f, 0xc0b6b9e, 0xdaa0dde7,
+ 0xc04161e, 0xdaab122f, 0xbfcc29f, 0xdab547e8,
+ 0xbf57121, 0xdabf7f11, 0xbee21a5, 0xdac9b7a9,
+ 0xbe6d42b, 0xdad3f1b1, 0xbdf88b3, 0xdade2d28,
+ 0xbd83f3d, 0xdae86a0d, 0xbd0f7ca, 0xdaf2a860,
+ 0xbc9b25a, 0xdafce821, 0xbc26eee, 0xdb072950,
+ 0xbbb2d85, 0xdb116beb, 0xbb3ee20, 0xdb1baff2,
+ 0xbacb0bf, 0xdb25f566, 0xba57563, 0xdb303c46,
+ 0xb9e3c0b, 0xdb3a8491, 0xb9704b9, 0xdb44ce46,
+ 0xb8fcf6b, 0xdb4f1967, 0xb889c23, 0xdb5965f1,
+ 0xb816ae1, 0xdb63b3e5, 0xb7a3ba5, 0xdb6e0342,
+ 0xb730e70, 0xdb785409, 0xb6be341, 0xdb82a638,
+ 0xb64ba19, 0xdb8cf9cf, 0xb5d92f8, 0xdb974ece,
+ 0xb566ddf, 0xdba1a534, 0xb4f4acd, 0xdbabfd01,
+ 0xb4829c4, 0xdbb65634, 0xb410ac3, 0xdbc0b0ce,
+ 0xb39edca, 0xdbcb0cce, 0xb32d2da, 0xdbd56a32,
+ 0xb2bb9f4, 0xdbdfc8fc, 0xb24a316, 0xdbea292b,
+ 0xb1d8e43, 0xdbf48abd, 0xb167b79, 0xdbfeedb3,
+ 0xb0f6aba, 0xdc09520d, 0xb085c05, 0xdc13b7c9,
+ 0xb014f5b, 0xdc1e1ee9, 0xafa44bc, 0xdc28876a,
+ 0xaf33c28, 0xdc32f14d, 0xaec35a0, 0xdc3d5c91,
+ 0xae53123, 0xdc47c936, 0xade2eb3, 0xdc52373c,
+ 0xad72e4f, 0xdc5ca6a2, 0xad02ff8, 0xdc671768,
+ 0xac933ae, 0xdc71898d, 0xac23971, 0xdc7bfd11,
+ 0xabb4141, 0xdc8671f3, 0xab44b1f, 0xdc90e834,
+ 0xaad570c, 0xdc9b5fd2, 0xaa66506, 0xdca5d8cd,
+ 0xa9f750f, 0xdcb05326, 0xa988727, 0xdcbacedb,
+ 0xa919b4e, 0xdcc54bec, 0xa8ab184, 0xdccfca59,
+ 0xa83c9ca, 0xdcda4a21, 0xa7ce420, 0xdce4cb44,
+ 0xa760086, 0xdcef4dc2, 0xa6f1efc, 0xdcf9d199,
+ 0xa683f83, 0xdd0456ca, 0xa61621b, 0xdd0edd55,
+ 0xa5a86c4, 0xdd196538, 0xa53ad7e, 0xdd23ee74,
+ 0xa4cd64b, 0xdd2e7908, 0xa460129, 0xdd3904f4,
+ 0xa3f2e19, 0xdd439236, 0xa385d1d, 0xdd4e20d0,
+ 0xa318e32, 0xdd58b0c0, 0xa2ac15b, 0xdd634206,
+ 0xa23f698, 0xdd6dd4a2, 0xa1d2de7, 0xdd786892,
+ 0xa16674b, 0xdd82fdd8, 0xa0fa2c3, 0xdd8d9472,
+ 0xa08e04f, 0xdd982c60, 0xa021fef, 0xdda2c5a2,
+ 0x9fb61a5, 0xddad6036, 0x9f4a570, 0xddb7fc1e,
+ 0x9edeb50, 0xddc29958, 0x9e73346, 0xddcd37e4,
+ 0x9e07d51, 0xddd7d7c1, 0x9d9c973, 0xdde278ef,
+ 0x9d317ab, 0xdded1b6e, 0x9cc67fa, 0xddf7bf3e,
+ 0x9c5ba60, 0xde02645d, 0x9bf0edd, 0xde0d0acc,
+ 0x9b86572, 0xde17b28a, 0x9b1be1e, 0xde225b96,
+ 0x9ab18e3, 0xde2d05f1, 0x9a475bf, 0xde37b199,
+ 0x99dd4b4, 0xde425e8f, 0x99735c2, 0xde4d0cd2,
+ 0x99098e9, 0xde57bc62, 0x989fe29, 0xde626d3e,
+ 0x9836582, 0xde6d1f65, 0x97ccef5, 0xde77d2d8,
+ 0x9763a83, 0xde828796, 0x96fa82a, 0xde8d3d9e,
+ 0x96917ec, 0xde97f4f1, 0x96289c9, 0xdea2ad8d,
+ 0x95bfdc1, 0xdead6773, 0x95573d4, 0xdeb822a1,
+ 0x94eec03, 0xdec2df18, 0x948664d, 0xdecd9cd7,
+ 0x941e2b4, 0xded85bdd, 0x93b6137, 0xdee31c2b,
+ 0x934e1d6, 0xdeedddc0, 0x92e6492, 0xdef8a09b,
+ 0x927e96b, 0xdf0364bc, 0x9217062, 0xdf0e2a22,
+ 0x91af976, 0xdf18f0ce, 0x91484a8, 0xdf23b8be,
+ 0x90e11f7, 0xdf2e81f3, 0x907a166, 0xdf394c6b,
+ 0x90132f2, 0xdf441828, 0x8fac69e, 0xdf4ee527,
+ 0x8f45c68, 0xdf59b369, 0x8edf452, 0xdf6482ed,
+ 0x8e78e5b, 0xdf6f53b3, 0x8e12a84, 0xdf7a25ba,
+ 0x8dac8cd, 0xdf84f902, 0x8d46936, 0xdf8fcd8b,
+ 0x8ce0bc0, 0xdf9aa354, 0x8c7b06b, 0xdfa57a5d,
+ 0x8c15736, 0xdfb052a5, 0x8bb0023, 0xdfbb2c2c,
+ 0x8b4ab32, 0xdfc606f1, 0x8ae5862, 0xdfd0e2f5,
+ 0x8a807b4, 0xdfdbc036, 0x8a1b928, 0xdfe69eb4,
+ 0x89b6cbf, 0xdff17e70, 0x8952278, 0xdffc5f67,
+ 0x88eda54, 0xe007419b, 0x8889454, 0xe012250a,
+ 0x8825077, 0xe01d09b4, 0x87c0ebd, 0xe027ef99,
+ 0x875cf28, 0xe032d6b8, 0x86f91b7, 0xe03dbf11,
+ 0x869566a, 0xe048a8a4, 0x8631d42, 0xe053936f,
+ 0x85ce63e, 0xe05e7f74, 0x856b160, 0xe0696cb0,
+ 0x8507ea7, 0xe0745b24, 0x84a4e14, 0xe07f4acf,
+ 0x8441fa6, 0xe08a3bb2, 0x83df35f, 0xe0952dcb,
+ 0x837c93e, 0xe0a0211a, 0x831a143, 0xe0ab159e,
+ 0x82b7b70, 0xe0b60b58, 0x82557c3, 0xe0c10247,
+ 0x81f363d, 0xe0cbfa6a, 0x81916df, 0xe0d6f3c1,
+ 0x812f9a9, 0xe0e1ee4b, 0x80cde9b, 0xe0ecea09,
+ 0x806c5b5, 0xe0f7e6f9, 0x800aef7, 0xe102e51c,
+ 0x7fa9a62, 0xe10de470, 0x7f487f6, 0xe118e4f6,
+ 0x7ee77b3, 0xe123e6ad, 0x7e8699a, 0xe12ee995,
+ 0x7e25daa, 0xe139edac, 0x7dc53e3, 0xe144f2f3,
+ 0x7d64c47, 0xe14ff96a, 0x7d046d6, 0xe15b0110,
+ 0x7ca438f, 0xe16609e3, 0x7c44272, 0xe17113e5,
+ 0x7be4381, 0xe17c1f15, 0x7b846ba, 0xe1872b72,
+ 0x7b24c20, 0xe19238fb, 0x7ac53b1, 0xe19d47b1,
+ 0x7a65d6e, 0xe1a85793, 0x7a06957, 0xe1b368a0,
+ 0x79a776c, 0xe1be7ad8, 0x79487ae, 0xe1c98e3b,
+ 0x78e9a1d, 0xe1d4a2c8, 0x788aeb9, 0xe1dfb87f,
+ 0x782c582, 0xe1eacf5f, 0x77cde79, 0xe1f5e768,
+ 0x776f99d, 0xe2010099, 0x77116f0, 0xe20c1af3,
+ 0x76b3671, 0xe2173674, 0x7655820, 0xe222531c,
+ 0x75f7bfe, 0xe22d70eb, 0x759a20a, 0xe2388fe1,
+ 0x753ca46, 0xe243affc, 0x74df4b1, 0xe24ed13d,
+ 0x748214c, 0xe259f3a3, 0x7425016, 0xe265172e,
+ 0x73c8111, 0xe2703bdc, 0x736b43c, 0xe27b61af,
+ 0x730e997, 0xe28688a4, 0x72b2123, 0xe291b0bd,
+ 0x7255ae0, 0xe29cd9f8, 0x71f96ce, 0xe2a80456,
+ 0x719d4ed, 0xe2b32fd4, 0x714153e, 0xe2be5c74,
+ 0x70e57c0, 0xe2c98a35, 0x7089c75, 0xe2d4b916,
+ 0x702e35c, 0xe2dfe917, 0x6fd2c75, 0xe2eb1a37,
+ 0x6f777c1, 0xe2f64c77, 0x6f1c540, 0xe3017fd5,
+ 0x6ec14f2, 0xe30cb451, 0x6e666d7, 0xe317e9eb,
+ 0x6e0baf0, 0xe32320a2, 0x6db113d, 0xe32e5876,
+ 0x6d569be, 0xe3399167, 0x6cfc472, 0xe344cb73,
+ 0x6ca215c, 0xe350069b, 0x6c4807a, 0xe35b42df,
+ 0x6bee1cd, 0xe366803c, 0x6b94554, 0xe371beb5,
+ 0x6b3ab12, 0xe37cfe47, 0x6ae1304, 0xe3883ef2,
+ 0x6a87d2d, 0xe39380b6, 0x6a2e98b, 0xe39ec393,
+ 0x69d5820, 0xe3aa0788, 0x697c8eb, 0xe3b54c95,
+ 0x6923bec, 0xe3c092b9, 0x68cb124, 0xe3cbd9f4,
+ 0x6872894, 0xe3d72245, 0x681a23a, 0xe3e26bac,
+ 0x67c1e18, 0xe3edb628, 0x6769c2e, 0xe3f901ba,
+ 0x6711c7b, 0xe4044e60, 0x66b9f01, 0xe40f9c1a,
+ 0x66623be, 0xe41aeae8, 0x660aab5, 0xe4263ac9,
+ 0x65b33e4, 0xe4318bbe, 0x655bf4c, 0xe43cddc4,
+ 0x6504ced, 0xe44830dd, 0x64adcc7, 0xe4538507,
+ 0x6456edb, 0xe45eda43, 0x6400329, 0xe46a308f,
+ 0x63a99b1, 0xe47587eb, 0x6353273, 0xe480e057,
+ 0x62fcd6f, 0xe48c39d3, 0x62a6aa6, 0xe497945d,
+ 0x6250a18, 0xe4a2eff6, 0x61fabc4, 0xe4ae4c9d,
+ 0x61a4fac, 0xe4b9aa52, 0x614f5cf, 0xe4c50914,
+ 0x60f9e2e, 0xe4d068e2, 0x60a48c9, 0xe4dbc9bd,
+ 0x604f5a0, 0xe4e72ba4, 0x5ffa4b3, 0xe4f28e96,
+ 0x5fa5603, 0xe4fdf294, 0x5f5098f, 0xe509579b,
+ 0x5efbf58, 0xe514bdad, 0x5ea775e, 0xe52024c9,
+ 0x5e531a1, 0xe52b8cee, 0x5dfee22, 0xe536f61b,
+ 0x5daace1, 0xe5426051, 0x5d56ddd, 0xe54dcb8f,
+ 0x5d03118, 0xe55937d5, 0x5caf690, 0xe564a521,
+ 0x5c5be47, 0xe5701374, 0x5c0883d, 0xe57b82cd,
+ 0x5bb5472, 0xe586f32c, 0x5b622e6, 0xe5926490,
+ 0x5b0f399, 0xe59dd6f9, 0x5abc68c, 0xe5a94a67,
+ 0x5a69bbe, 0xe5b4bed8, 0x5a17330, 0xe5c0344d,
+ 0x59c4ce3, 0xe5cbaac5, 0x59728d5, 0xe5d72240,
+ 0x5920708, 0xe5e29abc, 0x58ce77c, 0xe5ee143b,
+ 0x587ca31, 0xe5f98ebb, 0x582af26, 0xe6050a3b,
+ 0x57d965d, 0xe61086bc, 0x5787fd6, 0xe61c043d,
+ 0x5736b90, 0xe62782be, 0x56e598c, 0xe633023e,
+ 0x56949ca, 0xe63e82bc, 0x5643c4a, 0xe64a0438,
+ 0x55f310d, 0xe65586b3, 0x55a2812, 0xe6610a2a,
+ 0x555215a, 0xe66c8e9f, 0x5501ce5, 0xe6781410,
+ 0x54b1ab4, 0xe6839a7c, 0x5461ac6, 0xe68f21e5,
+ 0x5411d1b, 0xe69aaa48, 0x53c21b4, 0xe6a633a6,
+ 0x5372891, 0xe6b1bdff, 0x53231b3, 0xe6bd4951,
+ 0x52d3d18, 0xe6c8d59c, 0x5284ac3, 0xe6d462e1,
+ 0x5235ab2, 0xe6dff11d, 0x51e6ce6, 0xe6eb8052,
+ 0x519815f, 0xe6f7107e, 0x514981d, 0xe702a1a1,
+ 0x50fb121, 0xe70e33bb, 0x50acc6b, 0xe719c6cb,
+ 0x505e9fb, 0xe7255ad1, 0x50109d0, 0xe730efcc,
+ 0x4fc2bec, 0xe73c85bc, 0x4f7504e, 0xe7481ca1,
+ 0x4f276f7, 0xe753b479, 0x4ed9fe7, 0xe75f4d45,
+ 0x4e8cb1e, 0xe76ae704, 0x4e3f89c, 0xe77681b6,
+ 0x4df2862, 0xe7821d59, 0x4da5a6f, 0xe78db9ef,
+ 0x4d58ec3, 0xe7995776, 0x4d0c560, 0xe7a4f5ed,
+ 0x4cbfe45, 0xe7b09555, 0x4c73972, 0xe7bc35ad,
+ 0x4c276e8, 0xe7c7d6f4, 0x4bdb6a6, 0xe7d3792b,
+ 0x4b8f8ad, 0xe7df1c50, 0x4b43cfd, 0xe7eac063,
+ 0x4af8397, 0xe7f66564, 0x4aacc7a, 0xe8020b52,
+ 0x4a617a6, 0xe80db22d, 0x4a1651c, 0xe81959f4,
+ 0x49cb4dd, 0xe82502a7, 0x49806e7, 0xe830ac45,
+ 0x4935b3c, 0xe83c56cf, 0x48eb1db, 0xe8480243,
+ 0x48a0ac4, 0xe853aea1, 0x48565f9, 0xe85f5be9,
+ 0x480c379, 0xe86b0a1a, 0x47c2344, 0xe876b934,
+ 0x477855a, 0xe8826936, 0x472e9bc, 0xe88e1a20,
+ 0x46e5069, 0xe899cbf1, 0x469b963, 0xe8a57ea9,
+ 0x46524a9, 0xe8b13248, 0x460923b, 0xe8bce6cd,
+ 0x45c0219, 0xe8c89c37, 0x4577444, 0xe8d45286,
+ 0x452e8bc, 0xe8e009ba, 0x44e5f80, 0xe8ebc1d3,
+ 0x449d892, 0xe8f77acf, 0x44553f2, 0xe90334af,
+ 0x440d19e, 0xe90eef71, 0x43c5199, 0xe91aab16,
+ 0x437d3e1, 0xe926679c, 0x4335877, 0xe9322505,
+ 0x42edf5c, 0xe93de34e, 0x42a688f, 0xe949a278,
+ 0x425f410, 0xe9556282, 0x42181e0, 0xe961236c,
+ 0x41d11ff, 0xe96ce535, 0x418a46d, 0xe978a7dd,
+ 0x414392b, 0xe9846b63, 0x40fd037, 0xe9902fc7,
+ 0x40b6994, 0xe99bf509, 0x4070540, 0xe9a7bb28,
+ 0x402a33c, 0xe9b38223, 0x3fe4388, 0xe9bf49fa,
+ 0x3f9e624, 0xe9cb12ad, 0x3f58b10, 0xe9d6dc3b,
+ 0x3f1324e, 0xe9e2a6a3, 0x3ecdbdc, 0xe9ee71e6,
+ 0x3e887bb, 0xe9fa3e03, 0x3e435ea, 0xea060af9,
+ 0x3dfe66c, 0xea11d8c8, 0x3db993e, 0xea1da770,
+ 0x3d74e62, 0xea2976ef, 0x3d305d8, 0xea354746,
+ 0x3cebfa0, 0xea411874, 0x3ca7bba, 0xea4cea79,
+ 0x3c63a26, 0xea58bd54, 0x3c1fae5, 0xea649105,
+ 0x3bdbdf6, 0xea70658a, 0x3b9835a, 0xea7c3ae5,
+ 0x3b54b11, 0xea881114, 0x3b1151b, 0xea93e817,
+ 0x3ace178, 0xea9fbfed, 0x3a8b028, 0xeaab9896,
+ 0x3a4812c, 0xeab77212, 0x3a05484, 0xeac34c60,
+ 0x39c2a2f, 0xeacf277f, 0x398022f, 0xeadb0370,
+ 0x393dc82, 0xeae6e031, 0x38fb92a, 0xeaf2bdc3,
+ 0x38b9827, 0xeafe9c24, 0x3877978, 0xeb0a7b54,
+ 0x3835d1e, 0xeb165b54, 0x37f4319, 0xeb223c22,
+ 0x37b2b6a, 0xeb2e1dbe, 0x377160f, 0xeb3a0027,
+ 0x373030a, 0xeb45e35d, 0x36ef25b, 0xeb51c760,
+ 0x36ae401, 0xeb5dac2f, 0x366d7fd, 0xeb6991ca,
+ 0x362ce50, 0xeb75782f, 0x35ec6f8, 0xeb815f60,
+ 0x35ac1f7, 0xeb8d475b, 0x356bf4d, 0xeb99301f,
+ 0x352bef9, 0xeba519ad, 0x34ec0fc, 0xebb10404,
+ 0x34ac556, 0xebbcef23, 0x346cc07, 0xebc8db0b,
+ 0x342d510, 0xebd4c7ba, 0x33ee070, 0xebe0b52f,
+ 0x33aee27, 0xebeca36c, 0x336fe37, 0xebf8926f,
+ 0x333109e, 0xec048237, 0x32f255e, 0xec1072c4,
+ 0x32b3c75, 0xec1c6417, 0x32755e5, 0xec28562d,
+ 0x32371ae, 0xec344908, 0x31f8fcf, 0xec403ca5,
+ 0x31bb049, 0xec4c3106, 0x317d31c, 0xec582629,
+ 0x313f848, 0xec641c0e, 0x3101fce, 0xec7012b5,
+ 0x30c49ad, 0xec7c0a1d, 0x30875e5, 0xec880245,
+ 0x304a477, 0xec93fb2e, 0x300d563, 0xec9ff4d6,
+ 0x2fd08a9, 0xecabef3d, 0x2f93e4a, 0xecb7ea63,
+ 0x2f57644, 0xecc3e648, 0x2f1b099, 0xeccfe2ea,
+ 0x2eded49, 0xecdbe04a, 0x2ea2c53, 0xece7de66,
+ 0x2e66db8, 0xecf3dd3f, 0x2e2b178, 0xecffdcd4,
+ 0x2def794, 0xed0bdd25, 0x2db400a, 0xed17de31,
+ 0x2d78add, 0xed23dff7, 0x2d3d80a, 0xed2fe277,
+ 0x2d02794, 0xed3be5b1, 0x2cc7979, 0xed47e9a5,
+ 0x2c8cdbb, 0xed53ee51, 0x2c52459, 0xed5ff3b5,
+ 0x2c17d52, 0xed6bf9d1, 0x2bdd8a9, 0xed7800a5,
+ 0x2ba365c, 0xed84082f, 0x2b6966c, 0xed901070,
+ 0x2b2f8d8, 0xed9c1967, 0x2af5da2, 0xeda82313,
+ 0x2abc4c9, 0xedb42d74, 0x2a82e4d, 0xedc0388a,
+ 0x2a49a2e, 0xedcc4454, 0x2a1086d, 0xedd850d2,
+ 0x29d790a, 0xede45e03, 0x299ec05, 0xedf06be6,
+ 0x296615d, 0xedfc7a7c, 0x292d914, 0xee0889c4,
+ 0x28f5329, 0xee1499bd, 0x28bcf9c, 0xee20aa67,
+ 0x2884e6e, 0xee2cbbc1, 0x284cf9f, 0xee38cdcb,
+ 0x281532e, 0xee44e084, 0x27dd91c, 0xee50f3ed,
+ 0x27a616a, 0xee5d0804, 0x276ec16, 0xee691cc9,
+ 0x2737922, 0xee75323c, 0x270088e, 0xee81485c,
+ 0x26c9a58, 0xee8d5f29, 0x2692e83, 0xee9976a1,
+ 0x265c50e, 0xeea58ec6, 0x2625df8, 0xeeb1a796,
+ 0x25ef943, 0xeebdc110, 0x25b96ee, 0xeec9db35,
+ 0x25836f9, 0xeed5f604, 0x254d965, 0xeee2117c,
+ 0x2517e31, 0xeeee2d9d, 0x24e255e, 0xeefa4a67,
+ 0x24aceed, 0xef0667d9, 0x2477adc, 0xef1285f2,
+ 0x244292c, 0xef1ea4b2, 0x240d9de, 0xef2ac419,
+ 0x23d8cf1, 0xef36e426, 0x23a4265, 0xef4304d8,
+ 0x236fa3b, 0xef4f2630, 0x233b473, 0xef5b482d,
+ 0x230710d, 0xef676ace, 0x22d3009, 0xef738e12,
+ 0x229f167, 0xef7fb1fa, 0x226b528, 0xef8bd685,
+ 0x2237b4b, 0xef97fbb2, 0x22043d0, 0xefa42181,
+ 0x21d0eb8, 0xefb047f2, 0x219dc03, 0xefbc6f03,
+ 0x216abb1, 0xefc896b5, 0x2137dc2, 0xefd4bf08,
+ 0x2105236, 0xefe0e7f9, 0x20d290d, 0xefed118a,
+ 0x20a0248, 0xeff93bba, 0x206dde6, 0xf0056687,
+ 0x203bbe8, 0xf01191f3, 0x2009c4e, 0xf01dbdfb,
+ 0x1fd7f17, 0xf029eaa1, 0x1fa6445, 0xf03617e2,
+ 0x1f74bd6, 0xf04245c0, 0x1f435cc, 0xf04e7438,
+ 0x1f12227, 0xf05aa34c, 0x1ee10e5, 0xf066d2fa,
+ 0x1eb0209, 0xf0730342, 0x1e7f591, 0xf07f3424,
+ 0x1e4eb7e, 0xf08b659f, 0x1e1e3d0, 0xf09797b2,
+ 0x1dede87, 0xf0a3ca5d, 0x1dbdba3, 0xf0affda0,
+ 0x1d8db25, 0xf0bc317a, 0x1d5dd0c, 0xf0c865ea,
+ 0x1d2e158, 0xf0d49af1, 0x1cfe80a, 0xf0e0d08d,
+ 0x1ccf122, 0xf0ed06bf, 0x1c9fca0, 0xf0f93d86,
+ 0x1c70a84, 0xf10574e0, 0x1c41ace, 0xf111accf,
+ 0x1c12d7e, 0xf11de551, 0x1be4294, 0xf12a1e66,
+ 0x1bb5a11, 0xf136580d, 0x1b873f5, 0xf1429247,
+ 0x1b5903f, 0xf14ecd11, 0x1b2aef0, 0xf15b086d,
+ 0x1afd007, 0xf1674459, 0x1acf386, 0xf17380d6,
+ 0x1aa196c, 0xf17fbde2, 0x1a741b9, 0xf18bfb7d,
+ 0x1a46c6e, 0xf19839a6, 0x1a1998a, 0xf1a4785e,
+ 0x19ec90d, 0xf1b0b7a4, 0x19bfaf9, 0xf1bcf777,
+ 0x1992f4c, 0xf1c937d6, 0x1966606, 0xf1d578c2,
+ 0x1939f29, 0xf1e1ba3a, 0x190dab4, 0xf1edfc3d,
+ 0x18e18a7, 0xf1fa3ecb, 0x18b5903, 0xf20681e3,
+ 0x1889bc6, 0xf212c585, 0x185e0f3, 0xf21f09b1,
+ 0x1832888, 0xf22b4e66, 0x1807285, 0xf23793a3,
+ 0x17dbeec, 0xf243d968, 0x17b0dbb, 0xf2501fb5,
+ 0x1785ef4, 0xf25c6688, 0x175b296, 0xf268ade3,
+ 0x17308a1, 0xf274f5c3, 0x1706115, 0xf2813e2a,
+ 0x16dbbf3, 0xf28d8715, 0x16b193a, 0xf299d085,
+ 0x16878eb, 0xf2a61a7a, 0x165db05, 0xf2b264f2,
+ 0x1633f8a, 0xf2beafed, 0x160a678, 0xf2cafb6b,
+ 0x15e0fd1, 0xf2d7476c, 0x15b7b94, 0xf2e393ef,
+ 0x158e9c1, 0xf2efe0f2, 0x1565a58, 0xf2fc2e77,
+ 0x153cd5a, 0xf3087c7d, 0x15142c6, 0xf314cb02,
+ 0x14eba9d, 0xf3211a07, 0x14c34df, 0xf32d698a,
+ 0x149b18b, 0xf339b98d, 0x14730a3, 0xf3460a0d,
+ 0x144b225, 0xf3525b0b, 0x1423613, 0xf35eac86,
+ 0x13fbc6c, 0xf36afe7e, 0x13d4530, 0xf37750f2,
+ 0x13ad060, 0xf383a3e2, 0x1385dfb, 0xf38ff74d,
+ 0x135ee02, 0xf39c4b32, 0x1338075, 0xf3a89f92,
+ 0x1311553, 0xf3b4f46c, 0x12eac9d, 0xf3c149bf,
+ 0x12c4653, 0xf3cd9f8b, 0x129e276, 0xf3d9f5cf,
+ 0x1278104, 0xf3e64c8c, 0x12521ff, 0xf3f2a3bf,
+ 0x122c566, 0xf3fefb6a, 0x1206b39, 0xf40b538b,
+ 0x11e1379, 0xf417ac22, 0x11bbe26, 0xf424052f,
+ 0x1196b3f, 0xf4305eb0, 0x1171ac6, 0xf43cb8a7,
+ 0x114ccb9, 0xf4491311, 0x1128119, 0xf4556def,
+ 0x11037e6, 0xf461c940, 0x10df120, 0xf46e2504,
+ 0x10bacc8, 0xf47a8139, 0x1096add, 0xf486dde1,
+ 0x1072b5f, 0xf4933afa, 0x104ee4f, 0xf49f9884,
+ 0x102b3ac, 0xf4abf67e, 0x1007b77, 0xf4b854e7,
+ 0xfe45b0, 0xf4c4b3c0, 0xfc1257, 0xf4d11308,
+ 0xf9e16b, 0xf4dd72be, 0xf7b2ee, 0xf4e9d2e3,
+ 0xf586df, 0xf4f63374, 0xf35d3e, 0xf5029473,
+ 0xf1360b, 0xf50ef5de, 0xef1147, 0xf51b57b5,
+ 0xeceef1, 0xf527b9f7, 0xeacf09, 0xf5341ca5,
+ 0xe8b190, 0xf5407fbd, 0xe69686, 0xf54ce33f,
+ 0xe47deb, 0xf559472b, 0xe267be, 0xf565ab80,
+ 0xe05401, 0xf572103d, 0xde42b2, 0xf57e7563,
+ 0xdc33d2, 0xf58adaf0, 0xda2762, 0xf59740e5,
+ 0xd81d61, 0xf5a3a740, 0xd615cf, 0xf5b00e02,
+ 0xd410ad, 0xf5bc7529, 0xd20dfa, 0xf5c8dcb6,
+ 0xd00db6, 0xf5d544a7, 0xce0fe3, 0xf5e1acfd,
+ 0xcc147f, 0xf5ee15b7, 0xca1b8a, 0xf5fa7ed4,
+ 0xc82506, 0xf606e854, 0xc630f2, 0xf6135237,
+ 0xc43f4d, 0xf61fbc7b, 0xc25019, 0xf62c2721,
+ 0xc06355, 0xf6389228, 0xbe7901, 0xf644fd8f,
+ 0xbc911d, 0xf6516956, 0xbaabaa, 0xf65dd57d,
+ 0xb8c8a7, 0xf66a4203, 0xb6e815, 0xf676aee8,
+ 0xb509f3, 0xf6831c2b, 0xb32e42, 0xf68f89cb,
+ 0xb15502, 0xf69bf7c9, 0xaf7e33, 0xf6a86623,
+ 0xada9d4, 0xf6b4d4d9, 0xabd7e6, 0xf6c143ec,
+ 0xaa086a, 0xf6cdb359, 0xa83b5e, 0xf6da2321,
+ 0xa670c4, 0xf6e69344, 0xa4a89b, 0xf6f303c0,
+ 0xa2e2e3, 0xf6ff7496, 0xa11f9d, 0xf70be5c4,
+ 0x9f5ec8, 0xf718574b, 0x9da065, 0xf724c92a,
+ 0x9be473, 0xf7313b60, 0x9a2af3, 0xf73daded,
+ 0x9873e4, 0xf74a20d0, 0x96bf48, 0xf756940a,
+ 0x950d1d, 0xf7630799, 0x935d64, 0xf76f7b7d,
+ 0x91b01d, 0xf77befb5, 0x900548, 0xf7886442,
+ 0x8e5ce5, 0xf794d922, 0x8cb6f5, 0xf7a14e55,
+ 0x8b1376, 0xf7adc3db, 0x89726a, 0xf7ba39b3,
+ 0x87d3d0, 0xf7c6afdc, 0x8637a9, 0xf7d32657,
+ 0x849df4, 0xf7df9d22, 0x8306b2, 0xf7ec143e,
+ 0x8171e2, 0xf7f88ba9, 0x7fdf85, 0xf8050364,
+ 0x7e4f9b, 0xf8117b6d, 0x7cc223, 0xf81df3c5,
+ 0x7b371e, 0xf82a6c6a, 0x79ae8c, 0xf836e55d,
+ 0x78286e, 0xf8435e9d, 0x76a4c2, 0xf84fd829,
+ 0x752389, 0xf85c5201, 0x73a4c3, 0xf868cc24,
+ 0x722871, 0xf8754692, 0x70ae92, 0xf881c14b,
+ 0x6f3726, 0xf88e3c4d, 0x6dc22e, 0xf89ab799,
+ 0x6c4fa8, 0xf8a7332e, 0x6adf97, 0xf8b3af0c,
+ 0x6971f9, 0xf8c02b31, 0x6806ce, 0xf8cca79e,
+ 0x669e18, 0xf8d92452, 0x6537d4, 0xf8e5a14d,
+ 0x63d405, 0xf8f21e8e, 0x6272aa, 0xf8fe9c15,
+ 0x6113c2, 0xf90b19e0, 0x5fb74e, 0xf91797f0,
+ 0x5e5d4e, 0xf9241645, 0x5d05c3, 0xf93094dd,
+ 0x5bb0ab, 0xf93d13b8, 0x5a5e07, 0xf94992d7,
+ 0x590dd8, 0xf9561237, 0x57c01d, 0xf96291d9,
+ 0x5674d6, 0xf96f11bc, 0x552c03, 0xf97b91e1,
+ 0x53e5a5, 0xf9881245, 0x52a1bb, 0xf99492ea,
+ 0x516045, 0xf9a113cd, 0x502145, 0xf9ad94f0,
+ 0x4ee4b8, 0xf9ba1651, 0x4daaa1, 0xf9c697f0,
+ 0x4c72fe, 0xf9d319cc, 0x4b3dcf, 0xf9df9be6,
+ 0x4a0b16, 0xf9ec1e3b, 0x48dad1, 0xf9f8a0cd,
+ 0x47ad01, 0xfa05239a, 0x4681a6, 0xfa11a6a3,
+ 0x4558c0, 0xfa1e29e5, 0x44324f, 0xfa2aad62,
+ 0x430e53, 0xfa373119, 0x41eccc, 0xfa43b508,
+ 0x40cdba, 0xfa503930, 0x3fb11d, 0xfa5cbd91,
+ 0x3e96f6, 0xfa694229, 0x3d7f44, 0xfa75c6f8,
+ 0x3c6a07, 0xfa824bfd, 0x3b573f, 0xfa8ed139,
+ 0x3a46ed, 0xfa9b56ab, 0x393910, 0xfaa7dc52,
+ 0x382da8, 0xfab4622d, 0x3724b6, 0xfac0e83d,
+ 0x361e3a, 0xfacd6e81, 0x351a33, 0xfad9f4f8,
+ 0x3418a2, 0xfae67ba2, 0x331986, 0xfaf3027e,
+ 0x321ce0, 0xfaff898c, 0x3122b0, 0xfb0c10cb,
+ 0x302af5, 0xfb18983b, 0x2f35b1, 0xfb251fdc,
+ 0x2e42e2, 0xfb31a7ac, 0x2d5289, 0xfb3e2fac,
+ 0x2c64a6, 0xfb4ab7db, 0x2b7939, 0xfb574039,
+ 0x2a9042, 0xfb63c8c4, 0x29a9c1, 0xfb70517d,
+ 0x28c5b6, 0xfb7cda63, 0x27e421, 0xfb896375,
+ 0x270502, 0xfb95ecb4, 0x262859, 0xfba2761e,
+ 0x254e27, 0xfbaeffb3, 0x24766a, 0xfbbb8973,
+ 0x23a124, 0xfbc8135c, 0x22ce54, 0xfbd49d70,
+ 0x21fdfb, 0xfbe127ac, 0x213018, 0xfbedb212,
+ 0x2064ab, 0xfbfa3c9f, 0x1f9bb5, 0xfc06c754,
+ 0x1ed535, 0xfc135231, 0x1e112b, 0xfc1fdd34,
+ 0x1d4f99, 0xfc2c685d, 0x1c907c, 0xfc38f3ac,
+ 0x1bd3d6, 0xfc457f21, 0x1b19a7, 0xfc520aba,
+ 0x1a61ee, 0xfc5e9678, 0x19acac, 0xfc6b2259,
+ 0x18f9e1, 0xfc77ae5e, 0x18498c, 0xfc843a85,
+ 0x179bae, 0xfc90c6cf, 0x16f047, 0xfc9d533b,
+ 0x164757, 0xfca9dfc8, 0x15a0dd, 0xfcb66c77,
+ 0x14fcda, 0xfcc2f945, 0x145b4e, 0xfccf8634,
+ 0x13bc39, 0xfcdc1342, 0x131f9b, 0xfce8a06f,
+ 0x128574, 0xfcf52dbb, 0x11edc3, 0xfd01bb24,
+ 0x11588a, 0xfd0e48ab, 0x10c5c7, 0xfd1ad650,
+ 0x10357c, 0xfd276410, 0xfa7a8, 0xfd33f1ed,
+ 0xf1c4a, 0xfd407fe6, 0xe9364, 0xfd4d0df9,
+ 0xe0cf5, 0xfd599c28, 0xd88fd, 0xfd662a70,
+ 0xd077c, 0xfd72b8d2, 0xc8872, 0xfd7f474d,
+ 0xc0be0, 0xfd8bd5e1, 0xb91c4, 0xfd98648d,
+ 0xb1a20, 0xfda4f351, 0xaa4f3, 0xfdb1822c,
+ 0xa323d, 0xfdbe111e, 0x9c1ff, 0xfdcaa027,
+ 0x95438, 0xfdd72f45, 0x8e8e8, 0xfde3be78,
+ 0x8800f, 0xfdf04dc0, 0x819ae, 0xfdfcdd1d,
+ 0x7b5c4, 0xfe096c8d, 0x75452, 0xfe15fc11,
+ 0x6f556, 0xfe228ba7, 0x698d3, 0xfe2f1b50,
+ 0x63ec6, 0xfe3bab0b, 0x5e731, 0xfe483ad8,
+ 0x59214, 0xfe54cab5, 0x53f6e, 0xfe615aa3,
+ 0x4ef3f, 0xfe6deaa1, 0x4a188, 0xfe7a7aae,
+ 0x45648, 0xfe870aca, 0x40d80, 0xfe939af5,
+ 0x3c72f, 0xfea02b2e, 0x38356, 0xfeacbb74,
+ 0x341f4, 0xfeb94bc8, 0x3030a, 0xfec5dc28,
+ 0x2c697, 0xfed26c94, 0x28c9c, 0xfedefd0c,
+ 0x25519, 0xfeeb8d8f, 0x2200d, 0xfef81e1d,
+ 0x1ed78, 0xff04aeb5, 0x1bd5c, 0xff113f56,
+ 0x18fb6, 0xff1dd001, 0x16489, 0xff2a60b4,
+ 0x13bd3, 0xff36f170, 0x11594, 0xff438234,
+ 0xf1ce, 0xff5012fe, 0xd07e, 0xff5ca3d0,
+ 0xb1a7, 0xff6934a8, 0x9547, 0xff75c585,
+ 0x7b5f, 0xff825668, 0x63ee, 0xff8ee750,
+ 0x4ef5, 0xff9b783c, 0x3c74, 0xffa8092c,
+ 0x2c6a, 0xffb49a1f, 0x1ed8, 0xffc12b16,
+ 0x13bd, 0xffcdbc0f, 0xb1a, 0xffda4d09,
+ 0x4ef, 0xffe6de05, 0x13c, 0xfff36f02,
+ 0x0, 0x0, 0x13c, 0xc90fe,
+ 0x4ef, 0x1921fb, 0xb1a, 0x25b2f7,
+ 0x13bd, 0x3243f1, 0x1ed8, 0x3ed4ea,
+ 0x2c6a, 0x4b65e1, 0x3c74, 0x57f6d4,
+ 0x4ef5, 0x6487c4, 0x63ee, 0x7118b0,
+ 0x7b5f, 0x7da998, 0x9547, 0x8a3a7b,
+ 0xb1a7, 0x96cb58, 0xd07e, 0xa35c30,
+ 0xf1ce, 0xafed02, 0x11594, 0xbc7dcc,
+ 0x13bd3, 0xc90e90, 0x16489, 0xd59f4c,
+ 0x18fb6, 0xe22fff, 0x1bd5c, 0xeec0aa,
+ 0x1ed78, 0xfb514b, 0x2200d, 0x107e1e3,
+ 0x25519, 0x1147271, 0x28c9c, 0x12102f4,
+ 0x2c697, 0x12d936c, 0x3030a, 0x13a23d8,
+ 0x341f4, 0x146b438, 0x38356, 0x153448c,
+ 0x3c72f, 0x15fd4d2, 0x40d80, 0x16c650b,
+ 0x45648, 0x178f536, 0x4a188, 0x1858552,
+ 0x4ef3f, 0x192155f, 0x53f6e, 0x19ea55d,
+ 0x59214, 0x1ab354b, 0x5e731, 0x1b7c528,
+ 0x63ec6, 0x1c454f5, 0x698d3, 0x1d0e4b0,
+ 0x6f556, 0x1dd7459, 0x75452, 0x1ea03ef,
+ 0x7b5c4, 0x1f69373, 0x819ae, 0x20322e3,
+ 0x8800f, 0x20fb240, 0x8e8e8, 0x21c4188,
+ 0x95438, 0x228d0bb, 0x9c1ff, 0x2355fd9,
+ 0xa323d, 0x241eee2, 0xaa4f3, 0x24e7dd4,
+ 0xb1a20, 0x25b0caf, 0xb91c4, 0x2679b73,
+ 0xc0be0, 0x2742a1f, 0xc8872, 0x280b8b3,
+ 0xd077c, 0x28d472e, 0xd88fd, 0x299d590,
+ 0xe0cf5, 0x2a663d8, 0xe9364, 0x2b2f207,
+ 0xf1c4a, 0x2bf801a, 0xfa7a8, 0x2cc0e13,
+ 0x10357c, 0x2d89bf0, 0x10c5c7, 0x2e529b0,
+ 0x11588a, 0x2f1b755, 0x11edc3, 0x2fe44dc,
+ 0x128574, 0x30ad245, 0x131f9b, 0x3175f91,
+ 0x13bc39, 0x323ecbe, 0x145b4e, 0x33079cc,
+ 0x14fcda, 0x33d06bb, 0x15a0dd, 0x3499389,
+ 0x164757, 0x3562038, 0x16f047, 0x362acc5,
+ 0x179bae, 0x36f3931, 0x18498c, 0x37bc57b,
+ 0x18f9e1, 0x38851a2, 0x19acac, 0x394dda7,
+ 0x1a61ee, 0x3a16988, 0x1b19a7, 0x3adf546,
+ 0x1bd3d6, 0x3ba80df, 0x1c907c, 0x3c70c54,
+ 0x1d4f99, 0x3d397a3, 0x1e112b, 0x3e022cc,
+ 0x1ed535, 0x3ecadcf, 0x1f9bb5, 0x3f938ac,
+ 0x2064ab, 0x405c361, 0x213018, 0x4124dee,
+ 0x21fdfb, 0x41ed854, 0x22ce54, 0x42b6290,
+ 0x23a124, 0x437eca4, 0x24766a, 0x444768d,
+ 0x254e27, 0x451004d, 0x262859, 0x45d89e2,
+ 0x270502, 0x46a134c, 0x27e421, 0x4769c8b,
+ 0x28c5b6, 0x483259d, 0x29a9c1, 0x48fae83,
+ 0x2a9042, 0x49c373c, 0x2b7939, 0x4a8bfc7,
+ 0x2c64a6, 0x4b54825, 0x2d5289, 0x4c1d054,
+ 0x2e42e2, 0x4ce5854, 0x2f35b1, 0x4dae024,
+ 0x302af5, 0x4e767c5, 0x3122b0, 0x4f3ef35,
+ 0x321ce0, 0x5007674, 0x331986, 0x50cfd82,
+ 0x3418a2, 0x519845e, 0x351a33, 0x5260b08,
+ 0x361e3a, 0x532917f, 0x3724b6, 0x53f17c3,
+ 0x382da8, 0x54b9dd3, 0x393910, 0x55823ae,
+ 0x3a46ed, 0x564a955, 0x3b573f, 0x5712ec7,
+ 0x3c6a07, 0x57db403, 0x3d7f44, 0x58a3908,
+ 0x3e96f6, 0x596bdd7, 0x3fb11d, 0x5a3426f,
+ 0x40cdba, 0x5afc6d0, 0x41eccc, 0x5bc4af8,
+ 0x430e53, 0x5c8cee7, 0x44324f, 0x5d5529e,
+ 0x4558c0, 0x5e1d61b, 0x4681a6, 0x5ee595d,
+ 0x47ad01, 0x5fadc66, 0x48dad1, 0x6075f33,
+ 0x4a0b16, 0x613e1c5, 0x4b3dcf, 0x620641a,
+ 0x4c72fe, 0x62ce634, 0x4daaa1, 0x6396810,
+ 0x4ee4b8, 0x645e9af, 0x502145, 0x6526b10,
+ 0x516045, 0x65eec33, 0x52a1bb, 0x66b6d16,
+ 0x53e5a5, 0x677edbb, 0x552c03, 0x6846e1f,
+ 0x5674d6, 0x690ee44, 0x57c01d, 0x69d6e27,
+ 0x590dd8, 0x6a9edc9, 0x5a5e07, 0x6b66d29,
+ 0x5bb0ab, 0x6c2ec48, 0x5d05c3, 0x6cf6b23,
+ 0x5e5d4e, 0x6dbe9bb, 0x5fb74e, 0x6e86810,
+ 0x6113c2, 0x6f4e620, 0x6272aa, 0x70163eb,
+ 0x63d405, 0x70de172, 0x6537d4, 0x71a5eb3,
+ 0x669e18, 0x726dbae, 0x6806ce, 0x7335862,
+ 0x6971f9, 0x73fd4cf, 0x6adf97, 0x74c50f4,
+ 0x6c4fa8, 0x758ccd2, 0x6dc22e, 0x7654867,
+ 0x6f3726, 0x771c3b3, 0x70ae92, 0x77e3eb5,
+ 0x722871, 0x78ab96e, 0x73a4c3, 0x79733dc,
+ 0x752389, 0x7a3adff, 0x76a4c2, 0x7b027d7,
+ 0x78286e, 0x7bca163, 0x79ae8c, 0x7c91aa3,
+ 0x7b371e, 0x7d59396, 0x7cc223, 0x7e20c3b,
+ 0x7e4f9b, 0x7ee8493, 0x7fdf85, 0x7fafc9c,
+ 0x8171e2, 0x8077457, 0x8306b2, 0x813ebc2,
+ 0x849df4, 0x82062de, 0x8637a9, 0x82cd9a9,
+ 0x87d3d0, 0x8395024, 0x89726a, 0x845c64d,
+ 0x8b1376, 0x8523c25, 0x8cb6f5, 0x85eb1ab,
+ 0x8e5ce5, 0x86b26de, 0x900548, 0x8779bbe,
+ 0x91b01d, 0x884104b, 0x935d64, 0x8908483,
+ 0x950d1d, 0x89cf867, 0x96bf48, 0x8a96bf6,
+ 0x9873e4, 0x8b5df30, 0x9a2af3, 0x8c25213,
+ 0x9be473, 0x8cec4a0, 0x9da065, 0x8db36d6,
+ 0x9f5ec8, 0x8e7a8b5, 0xa11f9d, 0x8f41a3c,
+ 0xa2e2e3, 0x9008b6a, 0xa4a89b, 0x90cfc40,
+ 0xa670c4, 0x9196cbc, 0xa83b5e, 0x925dcdf,
+ 0xaa086a, 0x9324ca7, 0xabd7e6, 0x93ebc14,
+ 0xada9d4, 0x94b2b27, 0xaf7e33, 0x95799dd,
+ 0xb15502, 0x9640837, 0xb32e42, 0x9707635,
+ 0xb509f3, 0x97ce3d5, 0xb6e815, 0x9895118,
+ 0xb8c8a7, 0x995bdfd, 0xbaabaa, 0x9a22a83,
+ 0xbc911d, 0x9ae96aa, 0xbe7901, 0x9bb0271,
+ 0xc06355, 0x9c76dd8, 0xc25019, 0x9d3d8df,
+ 0xc43f4d, 0x9e04385, 0xc630f2, 0x9ecadc9,
+ 0xc82506, 0x9f917ac, 0xca1b8a, 0xa05812c,
+ 0xcc147f, 0xa11ea49, 0xce0fe3, 0xa1e5303,
+ 0xd00db6, 0xa2abb59, 0xd20dfa, 0xa37234a,
+ 0xd410ad, 0xa438ad7, 0xd615cf, 0xa4ff1fe,
+ 0xd81d61, 0xa5c58c0, 0xda2762, 0xa68bf1b,
+ 0xdc33d2, 0xa752510, 0xde42b2, 0xa818a9d,
+ 0xe05401, 0xa8defc3, 0xe267be, 0xa9a5480,
+ 0xe47deb, 0xaa6b8d5, 0xe69686, 0xab31cc1,
+ 0xe8b190, 0xabf8043, 0xeacf09, 0xacbe35b,
+ 0xeceef1, 0xad84609, 0xef1147, 0xae4a84b,
+ 0xf1360b, 0xaf10a22, 0xf35d3e, 0xafd6b8d,
+ 0xf586df, 0xb09cc8c, 0xf7b2ee, 0xb162d1d,
+ 0xf9e16b, 0xb228d42, 0xfc1257, 0xb2eecf8,
+ 0xfe45b0, 0xb3b4c40, 0x1007b77, 0xb47ab19,
+ 0x102b3ac, 0xb540982, 0x104ee4f, 0xb60677c,
+ 0x1072b5f, 0xb6cc506, 0x1096add, 0xb79221f,
+ 0x10bacc8, 0xb857ec7, 0x10df120, 0xb91dafc,
+ 0x11037e6, 0xb9e36c0, 0x1128119, 0xbaa9211,
+ 0x114ccb9, 0xbb6ecef, 0x1171ac6, 0xbc34759,
+ 0x1196b3f, 0xbcfa150, 0x11bbe26, 0xbdbfad1,
+ 0x11e1379, 0xbe853de, 0x1206b39, 0xbf4ac75,
+ 0x122c566, 0xc010496, 0x12521ff, 0xc0d5c41,
+ 0x1278104, 0xc19b374, 0x129e276, 0xc260a31,
+ 0x12c4653, 0xc326075, 0x12eac9d, 0xc3eb641,
+ 0x1311553, 0xc4b0b94, 0x1338075, 0xc57606e,
+ 0x135ee02, 0xc63b4ce, 0x1385dfb, 0xc7008b3,
+ 0x13ad060, 0xc7c5c1e, 0x13d4530, 0xc88af0e,
+ 0x13fbc6c, 0xc950182, 0x1423613, 0xca1537a,
+ 0x144b225, 0xcada4f5, 0x14730a3, 0xcb9f5f3,
+ 0x149b18b, 0xcc64673, 0x14c34df, 0xcd29676,
+ 0x14eba9d, 0xcdee5f9, 0x15142c6, 0xceb34fe,
+ 0x153cd5a, 0xcf78383, 0x1565a58, 0xd03d189,
+ 0x158e9c1, 0xd101f0e, 0x15b7b94, 0xd1c6c11,
+ 0x15e0fd1, 0xd28b894, 0x160a678, 0xd350495,
+ 0x1633f8a, 0xd415013, 0x165db05, 0xd4d9b0e,
+ 0x16878eb, 0xd59e586, 0x16b193a, 0xd662f7b,
+ 0x16dbbf3, 0xd7278eb, 0x1706115, 0xd7ec1d6,
+ 0x17308a1, 0xd8b0a3d, 0x175b296, 0xd97521d,
+ 0x1785ef4, 0xda39978, 0x17b0dbb, 0xdafe04b,
+ 0x17dbeec, 0xdbc2698, 0x1807285, 0xdc86c5d,
+ 0x1832888, 0xdd4b19a, 0x185e0f3, 0xde0f64f,
+ 0x1889bc6, 0xded3a7b, 0x18b5903, 0xdf97e1d,
+ 0x18e18a7, 0xe05c135, 0x190dab4, 0xe1203c3,
+ 0x1939f29, 0xe1e45c6, 0x1966606, 0xe2a873e,
+ 0x1992f4c, 0xe36c82a, 0x19bfaf9, 0xe430889,
+ 0x19ec90d, 0xe4f485c, 0x1a1998a, 0xe5b87a2,
+ 0x1a46c6e, 0xe67c65a, 0x1a741b9, 0xe740483,
+ 0x1aa196c, 0xe80421e, 0x1acf386, 0xe8c7f2a,
+ 0x1afd007, 0xe98bba7, 0x1b2aef0, 0xea4f793,
+ 0x1b5903f, 0xeb132ef, 0x1b873f5, 0xebd6db9,
+ 0x1bb5a11, 0xec9a7f3, 0x1be4294, 0xed5e19a,
+ 0x1c12d7e, 0xee21aaf, 0x1c41ace, 0xeee5331,
+ 0x1c70a84, 0xefa8b20, 0x1c9fca0, 0xf06c27a,
+ 0x1ccf122, 0xf12f941, 0x1cfe80a, 0xf1f2f73,
+ 0x1d2e158, 0xf2b650f, 0x1d5dd0c, 0xf379a16,
+ 0x1d8db25, 0xf43ce86, 0x1dbdba3, 0xf500260,
+ 0x1dede87, 0xf5c35a3, 0x1e1e3d0, 0xf68684e,
+ 0x1e4eb7e, 0xf749a61, 0x1e7f591, 0xf80cbdc,
+ 0x1eb0209, 0xf8cfcbe, 0x1ee10e5, 0xf992d06,
+ 0x1f12227, 0xfa55cb4, 0x1f435cc, 0xfb18bc8,
+ 0x1f74bd6, 0xfbdba40, 0x1fa6445, 0xfc9e81e,
+ 0x1fd7f17, 0xfd6155f, 0x2009c4e, 0xfe24205,
+ 0x203bbe8, 0xfee6e0d, 0x206dde6, 0xffa9979,
+ 0x20a0248, 0x1006c446, 0x20d290d, 0x1012ee76,
+ 0x2105236, 0x101f1807, 0x2137dc2, 0x102b40f8,
+ 0x216abb1, 0x1037694b, 0x219dc03, 0x104390fd,
+ 0x21d0eb8, 0x104fb80e, 0x22043d0, 0x105bde7f,
+ 0x2237b4b, 0x1068044e, 0x226b528, 0x1074297b,
+ 0x229f167, 0x10804e06, 0x22d3009, 0x108c71ee,
+ 0x230710d, 0x10989532, 0x233b473, 0x10a4b7d3,
+ 0x236fa3b, 0x10b0d9d0, 0x23a4265, 0x10bcfb28,
+ 0x23d8cf1, 0x10c91bda, 0x240d9de, 0x10d53be7,
+ 0x244292c, 0x10e15b4e, 0x2477adc, 0x10ed7a0e,
+ 0x24aceed, 0x10f99827, 0x24e255e, 0x1105b599,
+ 0x2517e31, 0x1111d263, 0x254d965, 0x111dee84,
+ 0x25836f9, 0x112a09fc, 0x25b96ee, 0x113624cb,
+ 0x25ef943, 0x11423ef0, 0x2625df8, 0x114e586a,
+ 0x265c50e, 0x115a713a, 0x2692e83, 0x1166895f,
+ 0x26c9a58, 0x1172a0d7, 0x270088e, 0x117eb7a4,
+ 0x2737922, 0x118acdc4, 0x276ec16, 0x1196e337,
+ 0x27a616a, 0x11a2f7fc, 0x27dd91c, 0x11af0c13,
+ 0x281532e, 0x11bb1f7c, 0x284cf9f, 0x11c73235,
+ 0x2884e6e, 0x11d3443f, 0x28bcf9c, 0x11df5599,
+ 0x28f5329, 0x11eb6643, 0x292d914, 0x11f7763c,
+ 0x296615d, 0x12038584, 0x299ec05, 0x120f941a,
+ 0x29d790a, 0x121ba1fd, 0x2a1086d, 0x1227af2e,
+ 0x2a49a2e, 0x1233bbac, 0x2a82e4d, 0x123fc776,
+ 0x2abc4c9, 0x124bd28c, 0x2af5da2, 0x1257dced,
+ 0x2b2f8d8, 0x1263e699, 0x2b6966c, 0x126fef90,
+ 0x2ba365c, 0x127bf7d1, 0x2bdd8a9, 0x1287ff5b,
+ 0x2c17d52, 0x1294062f, 0x2c52459, 0x12a00c4b,
+ 0x2c8cdbb, 0x12ac11af, 0x2cc7979, 0x12b8165b,
+ 0x2d02794, 0x12c41a4f, 0x2d3d80a, 0x12d01d89,
+ 0x2d78add, 0x12dc2009, 0x2db400a, 0x12e821cf,
+ 0x2def794, 0x12f422db, 0x2e2b178, 0x1300232c,
+ 0x2e66db8, 0x130c22c1, 0x2ea2c53, 0x1318219a,
+ 0x2eded49, 0x13241fb6, 0x2f1b099, 0x13301d16,
+ 0x2f57644, 0x133c19b8, 0x2f93e4a, 0x1348159d,
+ 0x2fd08a9, 0x135410c3, 0x300d563, 0x13600b2a,
+ 0x304a477, 0x136c04d2, 0x30875e5, 0x1377fdbb,
+ 0x30c49ad, 0x1383f5e3, 0x3101fce, 0x138fed4b,
+ 0x313f848, 0x139be3f2, 0x317d31c, 0x13a7d9d7,
+ 0x31bb049, 0x13b3cefa, 0x31f8fcf, 0x13bfc35b,
+ 0x32371ae, 0x13cbb6f8, 0x32755e5, 0x13d7a9d3,
+ 0x32b3c75, 0x13e39be9, 0x32f255e, 0x13ef8d3c,
+ 0x333109e, 0x13fb7dc9, 0x336fe37, 0x14076d91,
+ 0x33aee27, 0x14135c94, 0x33ee070, 0x141f4ad1,
+ 0x342d510, 0x142b3846, 0x346cc07, 0x143724f5,
+ 0x34ac556, 0x144310dd, 0x34ec0fc, 0x144efbfc,
+ 0x352bef9, 0x145ae653, 0x356bf4d, 0x1466cfe1,
+ 0x35ac1f7, 0x1472b8a5, 0x35ec6f8, 0x147ea0a0,
+ 0x362ce50, 0x148a87d1, 0x366d7fd, 0x14966e36,
+ 0x36ae401, 0x14a253d1, 0x36ef25b, 0x14ae38a0,
+ 0x373030a, 0x14ba1ca3, 0x377160f, 0x14c5ffd9,
+ 0x37b2b6a, 0x14d1e242, 0x37f4319, 0x14ddc3de,
+ 0x3835d1e, 0x14e9a4ac, 0x3877978, 0x14f584ac,
+ 0x38b9827, 0x150163dc, 0x38fb92a, 0x150d423d,
+ 0x393dc82, 0x15191fcf, 0x398022f, 0x1524fc90,
+ 0x39c2a2f, 0x1530d881, 0x3a05484, 0x153cb3a0,
+ 0x3a4812c, 0x15488dee, 0x3a8b028, 0x1554676a,
+ 0x3ace178, 0x15604013, 0x3b1151b, 0x156c17e9,
+ 0x3b54b11, 0x1577eeec, 0x3b9835a, 0x1583c51b,
+ 0x3bdbdf6, 0x158f9a76, 0x3c1fae5, 0x159b6efb,
+ 0x3c63a26, 0x15a742ac, 0x3ca7bba, 0x15b31587,
+ 0x3cebfa0, 0x15bee78c, 0x3d305d8, 0x15cab8ba,
+ 0x3d74e62, 0x15d68911, 0x3db993e, 0x15e25890,
+ 0x3dfe66c, 0x15ee2738, 0x3e435ea, 0x15f9f507,
+ 0x3e887bb, 0x1605c1fd, 0x3ecdbdc, 0x16118e1a,
+ 0x3f1324e, 0x161d595d, 0x3f58b10, 0x162923c5,
+ 0x3f9e624, 0x1634ed53, 0x3fe4388, 0x1640b606,
+ 0x402a33c, 0x164c7ddd, 0x4070540, 0x165844d8,
+ 0x40b6994, 0x16640af7, 0x40fd037, 0x166fd039,
+ 0x414392b, 0x167b949d, 0x418a46d, 0x16875823,
+ 0x41d11ff, 0x16931acb, 0x42181e0, 0x169edc94,
+ 0x425f410, 0x16aa9d7e, 0x42a688f, 0x16b65d88,
+ 0x42edf5c, 0x16c21cb2, 0x4335877, 0x16cddafb,
+ 0x437d3e1, 0x16d99864, 0x43c5199, 0x16e554ea,
+ 0x440d19e, 0x16f1108f, 0x44553f2, 0x16fccb51,
+ 0x449d892, 0x17088531, 0x44e5f80, 0x17143e2d,
+ 0x452e8bc, 0x171ff646, 0x4577444, 0x172bad7a,
+ 0x45c0219, 0x173763c9, 0x460923b, 0x17431933,
+ 0x46524a9, 0x174ecdb8, 0x469b963, 0x175a8157,
+ 0x46e5069, 0x1766340f, 0x472e9bc, 0x1771e5e0,
+ 0x477855a, 0x177d96ca, 0x47c2344, 0x178946cc,
+ 0x480c379, 0x1794f5e6, 0x48565f9, 0x17a0a417,
+ 0x48a0ac4, 0x17ac515f, 0x48eb1db, 0x17b7fdbd,
+ 0x4935b3c, 0x17c3a931, 0x49806e7, 0x17cf53bb,
+ 0x49cb4dd, 0x17dafd59, 0x4a1651c, 0x17e6a60c,
+ 0x4a617a6, 0x17f24dd3, 0x4aacc7a, 0x17fdf4ae,
+ 0x4af8397, 0x18099a9c, 0x4b43cfd, 0x18153f9d,
+ 0x4b8f8ad, 0x1820e3b0, 0x4bdb6a6, 0x182c86d5,
+ 0x4c276e8, 0x1838290c, 0x4c73972, 0x1843ca53,
+ 0x4cbfe45, 0x184f6aab, 0x4d0c560, 0x185b0a13,
+ 0x4d58ec3, 0x1866a88a, 0x4da5a6f, 0x18724611,
+ 0x4df2862, 0x187de2a7, 0x4e3f89c, 0x18897e4a,
+ 0x4e8cb1e, 0x189518fc, 0x4ed9fe7, 0x18a0b2bb,
+ 0x4f276f7, 0x18ac4b87, 0x4f7504e, 0x18b7e35f,
+ 0x4fc2bec, 0x18c37a44, 0x50109d0, 0x18cf1034,
+ 0x505e9fb, 0x18daa52f, 0x50acc6b, 0x18e63935,
+ 0x50fb121, 0x18f1cc45, 0x514981d, 0x18fd5e5f,
+ 0x519815f, 0x1908ef82, 0x51e6ce6, 0x19147fae,
+ 0x5235ab2, 0x19200ee3, 0x5284ac3, 0x192b9d1f,
+ 0x52d3d18, 0x19372a64, 0x53231b3, 0x1942b6af,
+ 0x5372891, 0x194e4201, 0x53c21b4, 0x1959cc5a,
+ 0x5411d1b, 0x196555b8, 0x5461ac6, 0x1970de1b,
+ 0x54b1ab4, 0x197c6584, 0x5501ce5, 0x1987ebf0,
+ 0x555215a, 0x19937161, 0x55a2812, 0x199ef5d6,
+ 0x55f310d, 0x19aa794d, 0x5643c4a, 0x19b5fbc8,
+ 0x56949ca, 0x19c17d44, 0x56e598c, 0x19ccfdc2,
+ 0x5736b90, 0x19d87d42, 0x5787fd6, 0x19e3fbc3,
+ 0x57d965d, 0x19ef7944, 0x582af26, 0x19faf5c5,
+ 0x587ca31, 0x1a067145, 0x58ce77c, 0x1a11ebc5,
+ 0x5920708, 0x1a1d6544, 0x59728d5, 0x1a28ddc0,
+ 0x59c4ce3, 0x1a34553b, 0x5a17330, 0x1a3fcbb3,
+ 0x5a69bbe, 0x1a4b4128, 0x5abc68c, 0x1a56b599,
+ 0x5b0f399, 0x1a622907, 0x5b622e6, 0x1a6d9b70,
+ 0x5bb5472, 0x1a790cd4, 0x5c0883d, 0x1a847d33,
+ 0x5c5be47, 0x1a8fec8c, 0x5caf690, 0x1a9b5adf,
+ 0x5d03118, 0x1aa6c82b, 0x5d56ddd, 0x1ab23471,
+ 0x5daace1, 0x1abd9faf, 0x5dfee22, 0x1ac909e5,
+ 0x5e531a1, 0x1ad47312, 0x5ea775e, 0x1adfdb37,
+ 0x5efbf58, 0x1aeb4253, 0x5f5098f, 0x1af6a865,
+ 0x5fa5603, 0x1b020d6c, 0x5ffa4b3, 0x1b0d716a,
+ 0x604f5a0, 0x1b18d45c, 0x60a48c9, 0x1b243643,
+ 0x60f9e2e, 0x1b2f971e, 0x614f5cf, 0x1b3af6ec,
+ 0x61a4fac, 0x1b4655ae, 0x61fabc4, 0x1b51b363,
+ 0x6250a18, 0x1b5d100a, 0x62a6aa6, 0x1b686ba3,
+ 0x62fcd6f, 0x1b73c62d, 0x6353273, 0x1b7f1fa9,
+ 0x63a99b1, 0x1b8a7815, 0x6400329, 0x1b95cf71,
+ 0x6456edb, 0x1ba125bd, 0x64adcc7, 0x1bac7af9,
+ 0x6504ced, 0x1bb7cf23, 0x655bf4c, 0x1bc3223c,
+ 0x65b33e4, 0x1bce7442, 0x660aab5, 0x1bd9c537,
+ 0x66623be, 0x1be51518, 0x66b9f01, 0x1bf063e6,
+ 0x6711c7b, 0x1bfbb1a0, 0x6769c2e, 0x1c06fe46,
+ 0x67c1e18, 0x1c1249d8, 0x681a23a, 0x1c1d9454,
+ 0x6872894, 0x1c28ddbb, 0x68cb124, 0x1c34260c,
+ 0x6923bec, 0x1c3f6d47, 0x697c8eb, 0x1c4ab36b,
+ 0x69d5820, 0x1c55f878, 0x6a2e98b, 0x1c613c6d,
+ 0x6a87d2d, 0x1c6c7f4a, 0x6ae1304, 0x1c77c10e,
+ 0x6b3ab12, 0x1c8301b9, 0x6b94554, 0x1c8e414b,
+ 0x6bee1cd, 0x1c997fc4, 0x6c4807a, 0x1ca4bd21,
+ 0x6ca215c, 0x1caff965, 0x6cfc472, 0x1cbb348d,
+ 0x6d569be, 0x1cc66e99, 0x6db113d, 0x1cd1a78a,
+ 0x6e0baf0, 0x1cdcdf5e, 0x6e666d7, 0x1ce81615,
+ 0x6ec14f2, 0x1cf34baf, 0x6f1c540, 0x1cfe802b,
+ 0x6f777c1, 0x1d09b389, 0x6fd2c75, 0x1d14e5c9,
+ 0x702e35c, 0x1d2016e9, 0x7089c75, 0x1d2b46ea,
+ 0x70e57c0, 0x1d3675cb, 0x714153e, 0x1d41a38c,
+ 0x719d4ed, 0x1d4cd02c, 0x71f96ce, 0x1d57fbaa,
+ 0x7255ae0, 0x1d632608, 0x72b2123, 0x1d6e4f43,
+ 0x730e997, 0x1d79775c, 0x736b43c, 0x1d849e51,
+ 0x73c8111, 0x1d8fc424, 0x7425016, 0x1d9ae8d2,
+ 0x748214c, 0x1da60c5d, 0x74df4b1, 0x1db12ec3,
+ 0x753ca46, 0x1dbc5004, 0x759a20a, 0x1dc7701f,
+ 0x75f7bfe, 0x1dd28f15, 0x7655820, 0x1dddace4,
+ 0x76b3671, 0x1de8c98c, 0x77116f0, 0x1df3e50d,
+ 0x776f99d, 0x1dfeff67, 0x77cde79, 0x1e0a1898,
+ 0x782c582, 0x1e1530a1, 0x788aeb9, 0x1e204781,
+ 0x78e9a1d, 0x1e2b5d38, 0x79487ae, 0x1e3671c5,
+ 0x79a776c, 0x1e418528, 0x7a06957, 0x1e4c9760,
+ 0x7a65d6e, 0x1e57a86d, 0x7ac53b1, 0x1e62b84f,
+ 0x7b24c20, 0x1e6dc705, 0x7b846ba, 0x1e78d48e,
+ 0x7be4381, 0x1e83e0eb, 0x7c44272, 0x1e8eec1b,
+ 0x7ca438f, 0x1e99f61d, 0x7d046d6, 0x1ea4fef0,
+ 0x7d64c47, 0x1eb00696, 0x7dc53e3, 0x1ebb0d0d,
+ 0x7e25daa, 0x1ec61254, 0x7e8699a, 0x1ed1166b,
+ 0x7ee77b3, 0x1edc1953, 0x7f487f6, 0x1ee71b0a,
+ 0x7fa9a62, 0x1ef21b90, 0x800aef7, 0x1efd1ae4,
+ 0x806c5b5, 0x1f081907, 0x80cde9b, 0x1f1315f7,
+ 0x812f9a9, 0x1f1e11b5, 0x81916df, 0x1f290c3f,
+ 0x81f363d, 0x1f340596, 0x82557c3, 0x1f3efdb9,
+ 0x82b7b70, 0x1f49f4a8, 0x831a143, 0x1f54ea62,
+ 0x837c93e, 0x1f5fdee6, 0x83df35f, 0x1f6ad235,
+ 0x8441fa6, 0x1f75c44e, 0x84a4e14, 0x1f80b531,
+ 0x8507ea7, 0x1f8ba4dc, 0x856b160, 0x1f969350,
+ 0x85ce63e, 0x1fa1808c, 0x8631d42, 0x1fac6c91,
+ 0x869566a, 0x1fb7575c, 0x86f91b7, 0x1fc240ef,
+ 0x875cf28, 0x1fcd2948, 0x87c0ebd, 0x1fd81067,
+ 0x8825077, 0x1fe2f64c, 0x8889454, 0x1feddaf6,
+ 0x88eda54, 0x1ff8be65, 0x8952278, 0x2003a099,
+ 0x89b6cbf, 0x200e8190, 0x8a1b928, 0x2019614c,
+ 0x8a807b4, 0x20243fca, 0x8ae5862, 0x202f1d0b,
+ 0x8b4ab32, 0x2039f90f, 0x8bb0023, 0x2044d3d4,
+ 0x8c15736, 0x204fad5b, 0x8c7b06b, 0x205a85a3,
+ 0x8ce0bc0, 0x20655cac, 0x8d46936, 0x20703275,
+ 0x8dac8cd, 0x207b06fe, 0x8e12a84, 0x2085da46,
+ 0x8e78e5b, 0x2090ac4d, 0x8edf452, 0x209b7d13,
+ 0x8f45c68, 0x20a64c97, 0x8fac69e, 0x20b11ad9,
+ 0x90132f2, 0x20bbe7d8, 0x907a166, 0x20c6b395,
+ 0x90e11f7, 0x20d17e0d, 0x91484a8, 0x20dc4742,
+ 0x91af976, 0x20e70f32, 0x9217062, 0x20f1d5de,
+ 0x927e96b, 0x20fc9b44, 0x92e6492, 0x21075f65,
+ 0x934e1d6, 0x21122240, 0x93b6137, 0x211ce3d5,
+ 0x941e2b4, 0x2127a423, 0x948664d, 0x21326329,
+ 0x94eec03, 0x213d20e8, 0x95573d4, 0x2147dd5f,
+ 0x95bfdc1, 0x2152988d, 0x96289c9, 0x215d5273,
+ 0x96917ec, 0x21680b0f, 0x96fa82a, 0x2172c262,
+ 0x9763a83, 0x217d786a, 0x97ccef5, 0x21882d28,
+ 0x9836582, 0x2192e09b, 0x989fe29, 0x219d92c2,
+ 0x99098e9, 0x21a8439e, 0x99735c2, 0x21b2f32e,
+ 0x99dd4b4, 0x21bda171, 0x9a475bf, 0x21c84e67,
+ 0x9ab18e3, 0x21d2fa0f, 0x9b1be1e, 0x21dda46a,
+ 0x9b86572, 0x21e84d76, 0x9bf0edd, 0x21f2f534,
+ 0x9c5ba60, 0x21fd9ba3, 0x9cc67fa, 0x220840c2,
+ 0x9d317ab, 0x2212e492, 0x9d9c973, 0x221d8711,
+ 0x9e07d51, 0x2228283f, 0x9e73346, 0x2232c81c,
+ 0x9edeb50, 0x223d66a8, 0x9f4a570, 0x224803e2,
+ 0x9fb61a5, 0x22529fca, 0xa021fef, 0x225d3a5e,
+ 0xa08e04f, 0x2267d3a0, 0xa0fa2c3, 0x22726b8e,
+ 0xa16674b, 0x227d0228, 0xa1d2de7, 0x2287976e,
+ 0xa23f698, 0x22922b5e, 0xa2ac15b, 0x229cbdfa,
+ 0xa318e32, 0x22a74f40, 0xa385d1d, 0x22b1df30,
+ 0xa3f2e19, 0x22bc6dca, 0xa460129, 0x22c6fb0c,
+ 0xa4cd64b, 0x22d186f8, 0xa53ad7e, 0x22dc118c,
+ 0xa5a86c4, 0x22e69ac8, 0xa61621b, 0x22f122ab,
+ 0xa683f83, 0x22fba936, 0xa6f1efc, 0x23062e67,
+ 0xa760086, 0x2310b23e, 0xa7ce420, 0x231b34bc,
+ 0xa83c9ca, 0x2325b5df, 0xa8ab184, 0x233035a7,
+ 0xa919b4e, 0x233ab414, 0xa988727, 0x23453125,
+ 0xa9f750f, 0x234facda, 0xaa66506, 0x235a2733,
+ 0xaad570c, 0x2364a02e, 0xab44b1f, 0x236f17cc,
+ 0xabb4141, 0x23798e0d, 0xac23971, 0x238402ef,
+ 0xac933ae, 0x238e7673, 0xad02ff8, 0x2398e898,
+ 0xad72e4f, 0x23a3595e, 0xade2eb3, 0x23adc8c4,
+ 0xae53123, 0x23b836ca, 0xaec35a0, 0x23c2a36f,
+ 0xaf33c28, 0x23cd0eb3, 0xafa44bc, 0x23d77896,
+ 0xb014f5b, 0x23e1e117, 0xb085c05, 0x23ec4837,
+ 0xb0f6aba, 0x23f6adf3, 0xb167b79, 0x2401124d,
+ 0xb1d8e43, 0x240b7543, 0xb24a316, 0x2415d6d5,
+ 0xb2bb9f4, 0x24203704, 0xb32d2da, 0x242a95ce,
+ 0xb39edca, 0x2434f332, 0xb410ac3, 0x243f4f32,
+ 0xb4829c4, 0x2449a9cc, 0xb4f4acd, 0x245402ff,
+ 0xb566ddf, 0x245e5acc, 0xb5d92f8, 0x2468b132,
+ 0xb64ba19, 0x24730631, 0xb6be341, 0x247d59c8,
+ 0xb730e70, 0x2487abf7, 0xb7a3ba5, 0x2491fcbe,
+ 0xb816ae1, 0x249c4c1b, 0xb889c23, 0x24a69a0f,
+ 0xb8fcf6b, 0x24b0e699, 0xb9704b9, 0x24bb31ba,
+ 0xb9e3c0b, 0x24c57b6f, 0xba57563, 0x24cfc3ba,
+ 0xbacb0bf, 0x24da0a9a, 0xbb3ee20, 0x24e4500e,
+ 0xbbb2d85, 0x24ee9415, 0xbc26eee, 0x24f8d6b0,
+ 0xbc9b25a, 0x250317df, 0xbd0f7ca, 0x250d57a0,
+ 0xbd83f3d, 0x251795f3, 0xbdf88b3, 0x2521d2d8,
+ 0xbe6d42b, 0x252c0e4f, 0xbee21a5, 0x25364857,
+ 0xbf57121, 0x254080ef, 0xbfcc29f, 0x254ab818,
+ 0xc04161e, 0x2554edd1, 0xc0b6b9e, 0x255f2219,
+ 0xc12c31f, 0x256954f1, 0xc1a1ca0, 0x25738657,
+ 0xc217822, 0x257db64c, 0xc28d5a3, 0x2587e4cf,
+ 0xc303524, 0x259211df, 0xc3796a5, 0x259c3d7c,
+ 0xc3efa25, 0x25a667a7, 0xc465fa3, 0x25b0905d,
+ 0xc4dc720, 0x25bab7a0, 0xc55309b, 0x25c4dd6e,
+ 0xc5c9c14, 0x25cf01c8, 0xc64098b, 0x25d924ac,
+ 0xc6b78ff, 0x25e3461b, 0xc72ea70, 0x25ed6614,
+ 0xc7a5dde, 0x25f78497, 0xc81d349, 0x2601a1a2,
+ 0xc894aaf, 0x260bbd37, 0xc90c412, 0x2615d754,
+ 0xc983f70, 0x261feffa, 0xc9fbcca, 0x262a0727,
+ 0xca73c1e, 0x26341cdb, 0xcaebd6e, 0x263e3117,
+ 0xcb640b8, 0x264843d9, 0xcbdc5fc, 0x26525521,
+ 0xcc54d3a, 0x265c64ef, 0xcccd671, 0x26667342,
+ 0xcd461a2, 0x2670801a, 0xcdbeecc, 0x267a8b77,
+ 0xce37def, 0x26849558, 0xceb0f0a, 0x268e9dbd,
+ 0xcf2a21d, 0x2698a4a6, 0xcfa3729, 0x26a2aa11,
+ 0xd01ce2b, 0x26acadff, 0xd096725, 0x26b6b070,
+ 0xd110216, 0x26c0b162, 0xd189efe, 0x26cab0d6,
+ 0xd203ddc, 0x26d4aecb, 0xd27deb0, 0x26deab41,
+ 0xd2f817b, 0x26e8a637, 0xd37263a, 0x26f29fad,
+ 0xd3eccef, 0x26fc97a3, 0xd467599, 0x27068e18,
+ 0xd4e2037, 0x2710830c, 0xd55ccca, 0x271a767e,
+ 0xd5d7b50, 0x2724686e, 0xd652bcb, 0x272e58dc,
+ 0xd6cde39, 0x273847c8, 0xd74929a, 0x27423530,
+ 0xd7c48ee, 0x274c2115, 0xd840134, 0x27560b76,
+ 0xd8bbb6d, 0x275ff452, 0xd937798, 0x2769dbaa,
+ 0xd9b35b4, 0x2773c17d, 0xda2f5c2, 0x277da5cb,
+ 0xdaab7c0, 0x27878893, 0xdb27bb0, 0x279169d5,
+ 0xdba4190, 0x279b4990, 0xdc20960, 0x27a527c4,
+ 0xdc9d320, 0x27af0472, 0xdd19ed0, 0x27b8df97,
+ 0xdd96c6f, 0x27c2b934, 0xde13bfd, 0x27cc9149,
+ 0xde90d79, 0x27d667d5, 0xdf0e0e4, 0x27e03cd8,
+ 0xdf8b63d, 0x27ea1052, 0xe008d84, 0x27f3e241,
+ 0xe0866b8, 0x27fdb2a7, 0xe1041d9, 0x28078181,
+ 0xe181ee8, 0x28114ed0, 0xe1ffde2, 0x281b1a94,
+ 0xe27dec9, 0x2824e4cc, 0xe2fc19c, 0x282ead78,
+ 0xe37a65b, 0x28387498, 0xe3f8d05, 0x28423a2a,
+ 0xe47759a, 0x284bfe2f, 0xe4f6019, 0x2855c0a6,
+ 0xe574c84, 0x285f8190, 0xe5f3ad8, 0x286940ea,
+ 0xe672b16, 0x2872feb6, 0xe6f1d3d, 0x287cbaf3,
+ 0xe77114e, 0x288675a0, 0xe7f0748, 0x28902ebd,
+ 0xe86ff2a, 0x2899e64a, 0xe8ef8f4, 0x28a39c46,
+ 0xe96f4a7, 0x28ad50b1, 0xe9ef241, 0x28b7038b,
+ 0xea6f1c2, 0x28c0b4d2, 0xeaef32b, 0x28ca6488,
+ 0xeb6f67a, 0x28d412ab, 0xebefbb0, 0x28ddbf3b,
+ 0xec702cb, 0x28e76a37, 0xecf0bcd, 0x28f113a0,
+ 0xed716b4, 0x28fabb75, 0xedf2380, 0x290461b5,
+ 0xee73231, 0x290e0661, 0xeef42c7, 0x2917a977,
+ 0xef75541, 0x29214af8, 0xeff699f, 0x292aeae3,
+ 0xf077fe1, 0x29348937, 0xf0f9805, 0x293e25f5,
+ 0xf17b20d, 0x2947c11c, 0xf1fcdf8, 0x29515aab,
+ 0xf27ebc5, 0x295af2a3, 0xf300b74, 0x29648902,
+ 0xf382d05, 0x296e1dc9, 0xf405077, 0x2977b0f7,
+ 0xf4875ca, 0x2981428c, 0xf509cfe, 0x298ad287,
+ 0xf58c613, 0x299460e8, 0xf60f108, 0x299dedaf,
+ 0xf691ddd, 0x29a778db, 0xf714c91, 0x29b1026c,
+ 0xf797d24, 0x29ba8a61, 0xf81af97, 0x29c410ba,
+ 0xf89e3e8, 0x29cd9578, 0xf921a17, 0x29d71899,
+ 0xf9a5225, 0x29e09a1c, 0xfa28c10, 0x29ea1a03,
+ 0xfaac7d8, 0x29f3984c, 0xfb3057d, 0x29fd14f6,
+ 0xfbb4500, 0x2a069003, 0xfc3865e, 0x2a100970,
+ 0xfcbc999, 0x2a19813f, 0xfd40eaf, 0x2a22f76e,
+ 0xfdc55a1, 0x2a2c6bfd, 0xfe49e6d, 0x2a35deeb,
+ 0xfece915, 0x2a3f503a, 0xff53597, 0x2a48bfe7,
+ 0xffd83f4, 0x2a522df3, 0x1005d42a, 0x2a5b9a5d,
+ 0x100e2639, 0x2a650525, 0x10167a22, 0x2a6e6e4b,
+ 0x101ecfe4, 0x2a77d5ce, 0x1027277e, 0x2a813bae,
+ 0x102f80f1, 0x2a8a9fea, 0x1037dc3b, 0x2a940283,
+ 0x1040395d, 0x2a9d6377, 0x10489856, 0x2aa6c2c6,
+ 0x1050f926, 0x2ab02071, 0x10595bcd, 0x2ab97c77,
+ 0x1061c04a, 0x2ac2d6d6, 0x106a269d, 0x2acc2f90,
+ 0x10728ec6, 0x2ad586a3, 0x107af8c4, 0x2adedc10,
+ 0x10836497, 0x2ae82fd5, 0x108bd23f, 0x2af181f3,
+ 0x109441bb, 0x2afad269, 0x109cb30b, 0x2b042137,
+ 0x10a5262f, 0x2b0d6e5c, 0x10ad9b26, 0x2b16b9d9,
+ 0x10b611f1, 0x2b2003ac, 0x10be8a8d, 0x2b294bd5,
+ 0x10c704fd, 0x2b329255, 0x10cf813e, 0x2b3bd72a,
+ 0x10d7ff51, 0x2b451a55, 0x10e07f36, 0x2b4e5bd4,
+ 0x10e900ec, 0x2b579ba8, 0x10f18472, 0x2b60d9d0,
+ 0x10fa09c9, 0x2b6a164d, 0x110290f0, 0x2b73511c,
+ 0x110b19e7, 0x2b7c8a3f, 0x1113a4ad, 0x2b85c1b5,
+ 0x111c3142, 0x2b8ef77d, 0x1124bfa6, 0x2b982b97,
+ 0x112d4fd9, 0x2ba15e03, 0x1135e1d9, 0x2baa8ec0,
+ 0x113e75a8, 0x2bb3bdce, 0x11470b44, 0x2bbceb2d,
+ 0x114fa2ad, 0x2bc616dd, 0x11583be2, 0x2bcf40dc,
+ 0x1160d6e5, 0x2bd8692b, 0x116973b3, 0x2be18fc9,
+ 0x1172124d, 0x2beab4b6, 0x117ab2b3, 0x2bf3d7f2,
+ 0x118354e4, 0x2bfcf97c, 0x118bf8e0, 0x2c061953,
+ 0x11949ea6, 0x2c0f3779, 0x119d4636, 0x2c1853eb,
+ 0x11a5ef90, 0x2c216eaa, 0x11ae9ab4, 0x2c2a87b6,
+ 0x11b747a0, 0x2c339f0e, 0x11bff656, 0x2c3cb4b1,
+ 0x11c8a6d4, 0x2c45c8a0, 0x11d1591a, 0x2c4edada,
+ 0x11da0d28, 0x2c57eb5e, 0x11e2c2fd, 0x2c60fa2d,
+ 0x11eb7a9a, 0x2c6a0746, 0x11f433fd, 0x2c7312a9,
+ 0x11fcef27, 0x2c7c1c55, 0x1205ac17, 0x2c85244a,
+ 0x120e6acc, 0x2c8e2a87, 0x12172b48, 0x2c972f0d,
+ 0x121fed88, 0x2ca031da, 0x1228b18d, 0x2ca932ef,
+ 0x12317756, 0x2cb2324c, 0x123a3ee4, 0x2cbb2fef,
+ 0x12430835, 0x2cc42bd9, 0x124bd34a, 0x2ccd2609,
+ 0x1254a021, 0x2cd61e7f, 0x125d6ebc, 0x2cdf153a,
+ 0x12663f19, 0x2ce80a3a, 0x126f1138, 0x2cf0fd80,
+ 0x1277e518, 0x2cf9ef09, 0x1280babb, 0x2d02ded7,
+ 0x1289921e, 0x2d0bcce8, 0x12926b41, 0x2d14b93d,
+ 0x129b4626, 0x2d1da3d5, 0x12a422ca, 0x2d268cb0,
+ 0x12ad012e, 0x2d2f73cd, 0x12b5e151, 0x2d38592c,
+ 0x12bec333, 0x2d413ccd, 0x12c7a6d4, 0x2d4a1eaf,
+ 0x12d08c33, 0x2d52fed2, 0x12d97350, 0x2d5bdd36,
+ 0x12e25c2b, 0x2d64b9da, 0x12eb46c3, 0x2d6d94bf,
+ 0x12f43318, 0x2d766de2, 0x12fd2129, 0x2d7f4545,
+ 0x130610f7, 0x2d881ae8, 0x130f0280, 0x2d90eec8,
+ 0x1317f5c6, 0x2d99c0e7, 0x1320eac6, 0x2da29144,
+ 0x1329e181, 0x2dab5fdf, 0x1332d9f7, 0x2db42cb6,
+ 0x133bd427, 0x2dbcf7cb, 0x1344d011, 0x2dc5c11c,
+ 0x134dcdb4, 0x2dce88aa, 0x1356cd11, 0x2dd74e73,
+ 0x135fce26, 0x2de01278, 0x1368d0f3, 0x2de8d4b8,
+ 0x1371d579, 0x2df19534, 0x137adbb6, 0x2dfa53e9,
+ 0x1383e3ab, 0x2e0310d9, 0x138ced57, 0x2e0bcc03,
+ 0x1395f8ba, 0x2e148566, 0x139f05d3, 0x2e1d3d03,
+ 0x13a814a2, 0x2e25f2d8, 0x13b12526, 0x2e2ea6e6,
+ 0x13ba3760, 0x2e37592c, 0x13c34b4f, 0x2e4009aa,
+ 0x13cc60f2, 0x2e48b860, 0x13d5784a, 0x2e51654c,
+ 0x13de9156, 0x2e5a1070, 0x13e7ac15, 0x2e62b9ca,
+ 0x13f0c887, 0x2e6b615a, 0x13f9e6ad, 0x2e740720,
+ 0x14030684, 0x2e7cab1c, 0x140c280e, 0x2e854d4d,
+ 0x14154b4a, 0x2e8dedb3, 0x141e7037, 0x2e968c4d,
+ 0x142796d5, 0x2e9f291b, 0x1430bf24, 0x2ea7c41e,
+ 0x1439e923, 0x2eb05d53, 0x144314d3, 0x2eb8f4bc,
+ 0x144c4232, 0x2ec18a58, 0x14557140, 0x2eca1e27,
+ 0x145ea1fd, 0x2ed2b027, 0x1467d469, 0x2edb405a,
+ 0x14710883, 0x2ee3cebe, 0x147a3e4b, 0x2eec5b53,
+ 0x148375c1, 0x2ef4e619, 0x148caee4, 0x2efd6f10,
+ 0x1495e9b3, 0x2f05f637, 0x149f2630, 0x2f0e7b8e,
+ 0x14a86458, 0x2f16ff14, 0x14b1a42c, 0x2f1f80ca,
+ 0x14bae5ab, 0x2f2800af, 0x14c428d6, 0x2f307ec2,
+ 0x14cd6dab, 0x2f38fb03, 0x14d6b42b, 0x2f417573,
+ 0x14dffc54, 0x2f49ee0f, 0x14e94627, 0x2f5264da,
+ 0x14f291a4, 0x2f5ad9d1, 0x14fbdec9, 0x2f634cf5,
+ 0x15052d97, 0x2f6bbe45, 0x150e7e0d, 0x2f742dc1,
+ 0x1517d02b, 0x2f7c9b69, 0x152123f0, 0x2f85073c,
+ 0x152a795d, 0x2f8d713a, 0x1533d070, 0x2f95d963,
+ 0x153d292a, 0x2f9e3fb6, 0x15468389, 0x2fa6a433,
+ 0x154fdf8f, 0x2faf06da, 0x15593d3a, 0x2fb767aa,
+ 0x15629c89, 0x2fbfc6a3, 0x156bfd7d, 0x2fc823c5,
+ 0x15756016, 0x2fd07f0f, 0x157ec452, 0x2fd8d882,
+ 0x15882a32, 0x2fe1301c, 0x159191b5, 0x2fe985de,
+ 0x159afadb, 0x2ff1d9c7, 0x15a465a3, 0x2ffa2bd6,
+ 0x15add20d, 0x30027c0c, 0x15b74019, 0x300aca69,
+ 0x15c0afc6, 0x301316eb, 0x15ca2115, 0x301b6193,
+ 0x15d39403, 0x3023aa5f, 0x15dd0892, 0x302bf151,
+ 0x15e67ec1, 0x30343667, 0x15eff690, 0x303c79a2,
+ 0x15f96ffd, 0x3044bb00, 0x1602eb0a, 0x304cfa83,
+ 0x160c67b4, 0x30553828, 0x1615e5fd, 0x305d73f0,
+ 0x161f65e4, 0x3065addb, 0x1628e767, 0x306de5e9,
+ 0x16326a88, 0x30761c18, 0x163bef46, 0x307e5069,
+ 0x1645759f, 0x308682dc, 0x164efd94, 0x308eb36f,
+ 0x16588725, 0x3096e223, 0x16621251, 0x309f0ef8,
+ 0x166b9f18, 0x30a739ed, 0x16752d79, 0x30af6302,
+ 0x167ebd74, 0x30b78a36, 0x16884f09, 0x30bfaf89,
+ 0x1691e237, 0x30c7d2fb, 0x169b76fe, 0x30cff48c,
+ 0x16a50d5d, 0x30d8143b, 0x16aea555, 0x30e03208,
+ 0x16b83ee4, 0x30e84df3, 0x16c1da0b, 0x30f067fb,
+ 0x16cb76c9, 0x30f8801f, 0x16d5151d, 0x31009661,
+ 0x16deb508, 0x3108aabf, 0x16e85689, 0x3110bd39,
+ 0x16f1f99f, 0x3118cdcf, 0x16fb9e4b, 0x3120dc80,
+ 0x1705448b, 0x3128e94c, 0x170eec60, 0x3130f433,
+ 0x171895c9, 0x3138fd35, 0x172240c5, 0x31410450,
+ 0x172bed55, 0x31490986, 0x17359b78, 0x31510cd5,
+ 0x173f4b2e, 0x31590e3e, 0x1748fc75, 0x31610dbf,
+ 0x1752af4f, 0x31690b59, 0x175c63ba, 0x3171070c,
+ 0x176619b6, 0x317900d6, 0x176fd143, 0x3180f8b8,
+ 0x17798a60, 0x3188eeb2, 0x1783450d, 0x3190e2c3,
+ 0x178d014a, 0x3198d4ea, 0x1796bf16, 0x31a0c528,
+ 0x17a07e70, 0x31a8b37c, 0x17aa3f5a, 0x31b09fe7,
+ 0x17b401d1, 0x31b88a66, 0x17bdc5d6, 0x31c072fb,
+ 0x17c78b68, 0x31c859a5, 0x17d15288, 0x31d03e64,
+ 0x17db1b34, 0x31d82137, 0x17e4e56c, 0x31e0021e,
+ 0x17eeb130, 0x31e7e118, 0x17f87e7f, 0x31efbe27,
+ 0x18024d59, 0x31f79948, 0x180c1dbf, 0x31ff727c,
+ 0x1815efae, 0x320749c3, 0x181fc328, 0x320f1f1c,
+ 0x1829982b, 0x3216f287, 0x18336eb7, 0x321ec403,
+ 0x183d46cc, 0x32269391, 0x18472069, 0x322e6130,
+ 0x1850fb8e, 0x32362ce0, 0x185ad83c, 0x323df6a0,
+ 0x1864b670, 0x3245be70, 0x186e962b, 0x324d8450,
+ 0x1878776d, 0x32554840, 0x18825a35, 0x325d0a3e,
+ 0x188c3e83, 0x3264ca4c, 0x18962456, 0x326c8868,
+ 0x18a00bae, 0x32744493, 0x18a9f48a, 0x327bfecc,
+ 0x18b3deeb, 0x3283b712, 0x18bdcad0, 0x328b6d66,
+ 0x18c7b838, 0x329321c7, 0x18d1a724, 0x329ad435,
+ 0x18db9792, 0x32a284b0, 0x18e58982, 0x32aa3336,
+ 0x18ef7cf4, 0x32b1dfc9, 0x18f971e8, 0x32b98a67,
+ 0x1903685d, 0x32c13311, 0x190d6053, 0x32c8d9c6,
+ 0x191759c9, 0x32d07e85, 0x192154bf, 0x32d82150,
+ 0x192b5135, 0x32dfc224, 0x19354f2a, 0x32e76102,
+ 0x193f4e9e, 0x32eefdea, 0x19494f90, 0x32f698db,
+ 0x19535201, 0x32fe31d5, 0x195d55ef, 0x3305c8d7,
+ 0x19675b5a, 0x330d5de3, 0x19716243, 0x3314f0f6,
+ 0x197b6aa8, 0x331c8211, 0x19857489, 0x33241134,
+ 0x198f7fe6, 0x332b9e5e, 0x19998cbe, 0x3333298f,
+ 0x19a39b11, 0x333ab2c6, 0x19adaadf, 0x33423a04,
+ 0x19b7bc27, 0x3349bf48, 0x19c1cee9, 0x33514292,
+ 0x19cbe325, 0x3358c3e2, 0x19d5f8d9, 0x33604336,
+ 0x19e01006, 0x3367c090, 0x19ea28ac, 0x336f3bee,
+ 0x19f442c9, 0x3376b551, 0x19fe5e5e, 0x337e2cb7,
+ 0x1a087b69, 0x3385a222, 0x1a1299ec, 0x338d1590,
+ 0x1a1cb9e5, 0x33948701, 0x1a26db54, 0x339bf675,
+ 0x1a30fe38, 0x33a363ec, 0x1a3b2292, 0x33aacf65,
+ 0x1a454860, 0x33b238e0, 0x1a4f6fa3, 0x33b9a05d,
+ 0x1a599859, 0x33c105db, 0x1a63c284, 0x33c8695b,
+ 0x1a6dee21, 0x33cfcadc, 0x1a781b31, 0x33d72a5d,
+ 0x1a8249b4, 0x33de87de, 0x1a8c79a9, 0x33e5e360,
+ 0x1a96ab0f, 0x33ed3ce1, 0x1aa0dde7, 0x33f49462,
+ 0x1aab122f, 0x33fbe9e2, 0x1ab547e8, 0x34033d61,
+ 0x1abf7f11, 0x340a8edf, 0x1ac9b7a9, 0x3411de5b,
+ 0x1ad3f1b1, 0x34192bd5, 0x1ade2d28, 0x3420774d,
+ 0x1ae86a0d, 0x3427c0c3, 0x1af2a860, 0x342f0836,
+ 0x1afce821, 0x34364da6, 0x1b072950, 0x343d9112,
+ 0x1b116beb, 0x3444d27b, 0x1b1baff2, 0x344c11e0,
+ 0x1b25f566, 0x34534f41, 0x1b303c46, 0x345a8a9d,
+ 0x1b3a8491, 0x3461c3f5, 0x1b44ce46, 0x3468fb47,
+ 0x1b4f1967, 0x34703095, 0x1b5965f1, 0x347763dd,
+ 0x1b63b3e5, 0x347e951f, 0x1b6e0342, 0x3485c45b,
+ 0x1b785409, 0x348cf190, 0x1b82a638, 0x34941cbf,
+ 0x1b8cf9cf, 0x349b45e7, 0x1b974ece, 0x34a26d08,
+ 0x1ba1a534, 0x34a99221, 0x1babfd01, 0x34b0b533,
+ 0x1bb65634, 0x34b7d63c, 0x1bc0b0ce, 0x34bef53d,
+ 0x1bcb0cce, 0x34c61236, 0x1bd56a32, 0x34cd2d26,
+ 0x1bdfc8fc, 0x34d4460c, 0x1bea292b, 0x34db5cea,
+ 0x1bf48abd, 0x34e271bd, 0x1bfeedb3, 0x34e98487,
+ 0x1c09520d, 0x34f09546, 0x1c13b7c9, 0x34f7a3fb,
+ 0x1c1e1ee9, 0x34feb0a5, 0x1c28876a, 0x3505bb44,
+ 0x1c32f14d, 0x350cc3d8, 0x1c3d5c91, 0x3513ca60,
+ 0x1c47c936, 0x351acedd, 0x1c52373c, 0x3521d14d,
+ 0x1c5ca6a2, 0x3528d1b1, 0x1c671768, 0x352fd008,
+ 0x1c71898d, 0x3536cc52, 0x1c7bfd11, 0x353dc68f,
+ 0x1c8671f3, 0x3544bebf, 0x1c90e834, 0x354bb4e1,
+ 0x1c9b5fd2, 0x3552a8f4, 0x1ca5d8cd, 0x35599afa,
+ 0x1cb05326, 0x35608af1, 0x1cbacedb, 0x356778d9,
+ 0x1cc54bec, 0x356e64b2, 0x1ccfca59, 0x35754e7c,
+ 0x1cda4a21, 0x357c3636, 0x1ce4cb44, 0x35831be0,
+ 0x1cef4dc2, 0x3589ff7a, 0x1cf9d199, 0x3590e104,
+ 0x1d0456ca, 0x3597c07d, 0x1d0edd55, 0x359e9de5,
+ 0x1d196538, 0x35a5793c, 0x1d23ee74, 0x35ac5282,
+ 0x1d2e7908, 0x35b329b5, 0x1d3904f4, 0x35b9fed7,
+ 0x1d439236, 0x35c0d1e7, 0x1d4e20d0, 0x35c7a2e3,
+ 0x1d58b0c0, 0x35ce71ce, 0x1d634206, 0x35d53ea5,
+ 0x1d6dd4a2, 0x35dc0968, 0x1d786892, 0x35e2d219,
+ 0x1d82fdd8, 0x35e998b5, 0x1d8d9472, 0x35f05d3d,
+ 0x1d982c60, 0x35f71fb1, 0x1da2c5a2, 0x35fde011,
+ 0x1dad6036, 0x36049e5b, 0x1db7fc1e, 0x360b5a90,
+ 0x1dc29958, 0x361214b0, 0x1dcd37e4, 0x3618ccba,
+ 0x1dd7d7c1, 0x361f82af, 0x1de278ef, 0x3626368d,
+ 0x1ded1b6e, 0x362ce855, 0x1df7bf3e, 0x36339806,
+ 0x1e02645d, 0x363a45a0, 0x1e0d0acc, 0x3640f123,
+ 0x1e17b28a, 0x36479a8e, 0x1e225b96, 0x364e41e2,
+ 0x1e2d05f1, 0x3654e71d, 0x1e37b199, 0x365b8a41,
+ 0x1e425e8f, 0x36622b4c, 0x1e4d0cd2, 0x3668ca3e,
+ 0x1e57bc62, 0x366f6717, 0x1e626d3e, 0x367601d7,
+ 0x1e6d1f65, 0x367c9a7e, 0x1e77d2d8, 0x3683310b,
+ 0x1e828796, 0x3689c57d, 0x1e8d3d9e, 0x369057d6,
+ 0x1e97f4f1, 0x3696e814, 0x1ea2ad8d, 0x369d7637,
+ 0x1ead6773, 0x36a4023f, 0x1eb822a1, 0x36aa8c2c,
+ 0x1ec2df18, 0x36b113fd, 0x1ecd9cd7, 0x36b799b3,
+ 0x1ed85bdd, 0x36be1d4c, 0x1ee31c2b, 0x36c49ec9,
+ 0x1eedddc0, 0x36cb1e2a, 0x1ef8a09b, 0x36d19b6e,
+ 0x1f0364bc, 0x36d81695, 0x1f0e2a22, 0x36de8f9e,
+ 0x1f18f0ce, 0x36e5068a, 0x1f23b8be, 0x36eb7b58,
+ 0x1f2e81f3, 0x36f1ee09, 0x1f394c6b, 0x36f85e9a,
+ 0x1f441828, 0x36fecd0e, 0x1f4ee527, 0x37053962,
+ 0x1f59b369, 0x370ba398, 0x1f6482ed, 0x37120bae,
+ 0x1f6f53b3, 0x371871a5, 0x1f7a25ba, 0x371ed57c,
+ 0x1f84f902, 0x37253733, 0x1f8fcd8b, 0x372b96ca,
+ 0x1f9aa354, 0x3731f440, 0x1fa57a5d, 0x37384f95,
+ 0x1fb052a5, 0x373ea8ca, 0x1fbb2c2c, 0x3744ffdd,
+ 0x1fc606f1, 0x374b54ce, 0x1fd0e2f5, 0x3751a79e,
+ 0x1fdbc036, 0x3757f84c, 0x1fe69eb4, 0x375e46d8,
+ 0x1ff17e70, 0x37649341, 0x1ffc5f67, 0x376add88,
+ 0x2007419b, 0x377125ac, 0x2012250a, 0x37776bac,
+ 0x201d09b4, 0x377daf89, 0x2027ef99, 0x3783f143,
+ 0x2032d6b8, 0x378a30d8, 0x203dbf11, 0x37906e49,
+ 0x2048a8a4, 0x3796a996, 0x2053936f, 0x379ce2be,
+ 0x205e7f74, 0x37a319c2, 0x20696cb0, 0x37a94ea0,
+ 0x20745b24, 0x37af8159, 0x207f4acf, 0x37b5b1ec,
+ 0x208a3bb2, 0x37bbe05a, 0x20952dcb, 0x37c20ca1,
+ 0x20a0211a, 0x37c836c2, 0x20ab159e, 0x37ce5ebd,
+ 0x20b60b58, 0x37d48490, 0x20c10247, 0x37daa83d,
+ 0x20cbfa6a, 0x37e0c9c3, 0x20d6f3c1, 0x37e6e921,
+ 0x20e1ee4b, 0x37ed0657, 0x20ecea09, 0x37f32165,
+ 0x20f7e6f9, 0x37f93a4b, 0x2102e51c, 0x37ff5109,
+ 0x210de470, 0x3805659e, 0x2118e4f6, 0x380b780a,
+ 0x2123e6ad, 0x3811884d, 0x212ee995, 0x38179666,
+ 0x2139edac, 0x381da256, 0x2144f2f3, 0x3823ac1d,
+ 0x214ff96a, 0x3829b3b9, 0x215b0110, 0x382fb92a,
+ 0x216609e3, 0x3835bc71, 0x217113e5, 0x383bbd8e,
+ 0x217c1f15, 0x3841bc7f, 0x21872b72, 0x3847b946,
+ 0x219238fb, 0x384db3e0, 0x219d47b1, 0x3853ac4f,
+ 0x21a85793, 0x3859a292, 0x21b368a0, 0x385f96a9,
+ 0x21be7ad8, 0x38658894, 0x21c98e3b, 0x386b7852,
+ 0x21d4a2c8, 0x387165e3, 0x21dfb87f, 0x38775147,
+ 0x21eacf5f, 0x387d3a7e, 0x21f5e768, 0x38832187,
+ 0x22010099, 0x38890663, 0x220c1af3, 0x388ee910,
+ 0x22173674, 0x3894c98f, 0x2222531c, 0x389aa7e0,
+ 0x222d70eb, 0x38a08402, 0x22388fe1, 0x38a65df6,
+ 0x2243affc, 0x38ac35ba, 0x224ed13d, 0x38b20b4f,
+ 0x2259f3a3, 0x38b7deb4, 0x2265172e, 0x38bdafea,
+ 0x22703bdc, 0x38c37eef, 0x227b61af, 0x38c94bc4,
+ 0x228688a4, 0x38cf1669, 0x2291b0bd, 0x38d4dedd,
+ 0x229cd9f8, 0x38daa520, 0x22a80456, 0x38e06932,
+ 0x22b32fd4, 0x38e62b13, 0x22be5c74, 0x38ebeac2,
+ 0x22c98a35, 0x38f1a840, 0x22d4b916, 0x38f7638b,
+ 0x22dfe917, 0x38fd1ca4, 0x22eb1a37, 0x3902d38b,
+ 0x22f64c77, 0x3908883f, 0x23017fd5, 0x390e3ac0,
+ 0x230cb451, 0x3913eb0e, 0x2317e9eb, 0x39199929,
+ 0x232320a2, 0x391f4510, 0x232e5876, 0x3924eec3,
+ 0x23399167, 0x392a9642, 0x2344cb73, 0x39303b8e,
+ 0x2350069b, 0x3935dea4, 0x235b42df, 0x393b7f86,
+ 0x2366803c, 0x39411e33, 0x2371beb5, 0x3946baac,
+ 0x237cfe47, 0x394c54ee, 0x23883ef2, 0x3951ecfc,
+ 0x239380b6, 0x395782d3, 0x239ec393, 0x395d1675,
+ 0x23aa0788, 0x3962a7e0, 0x23b54c95, 0x39683715,
+ 0x23c092b9, 0x396dc414, 0x23cbd9f4, 0x39734edc,
+ 0x23d72245, 0x3978d76c, 0x23e26bac, 0x397e5dc6,
+ 0x23edb628, 0x3983e1e8, 0x23f901ba, 0x398963d2,
+ 0x24044e60, 0x398ee385, 0x240f9c1a, 0x399460ff,
+ 0x241aeae8, 0x3999dc42, 0x24263ac9, 0x399f554b,
+ 0x24318bbe, 0x39a4cc1c, 0x243cddc4, 0x39aa40b4,
+ 0x244830dd, 0x39afb313, 0x24538507, 0x39b52339,
+ 0x245eda43, 0x39ba9125, 0x246a308f, 0x39bffcd7,
+ 0x247587eb, 0x39c5664f, 0x2480e057, 0x39cacd8d,
+ 0x248c39d3, 0x39d03291, 0x2497945d, 0x39d5955a,
+ 0x24a2eff6, 0x39daf5e8, 0x24ae4c9d, 0x39e0543c,
+ 0x24b9aa52, 0x39e5b054, 0x24c50914, 0x39eb0a31,
+ 0x24d068e2, 0x39f061d2, 0x24dbc9bd, 0x39f5b737,
+ 0x24e72ba4, 0x39fb0a60, 0x24f28e96, 0x3a005b4d,
+ 0x24fdf294, 0x3a05a9fd, 0x2509579b, 0x3a0af671,
+ 0x2514bdad, 0x3a1040a8, 0x252024c9, 0x3a1588a2,
+ 0x252b8cee, 0x3a1ace5f, 0x2536f61b, 0x3a2011de,
+ 0x25426051, 0x3a25531f, 0x254dcb8f, 0x3a2a9223,
+ 0x255937d5, 0x3a2fcee8, 0x2564a521, 0x3a350970,
+ 0x25701374, 0x3a3a41b9, 0x257b82cd, 0x3a3f77c3,
+ 0x2586f32c, 0x3a44ab8e, 0x25926490, 0x3a49dd1a,
+ 0x259dd6f9, 0x3a4f0c67, 0x25a94a67, 0x3a543974,
+ 0x25b4bed8, 0x3a596442, 0x25c0344d, 0x3a5e8cd0,
+ 0x25cbaac5, 0x3a63b31d, 0x25d72240, 0x3a68d72b,
+ 0x25e29abc, 0x3a6df8f8, 0x25ee143b, 0x3a731884,
+ 0x25f98ebb, 0x3a7835cf, 0x26050a3b, 0x3a7d50da,
+ 0x261086bc, 0x3a8269a3, 0x261c043d, 0x3a87802a,
+ 0x262782be, 0x3a8c9470, 0x2633023e, 0x3a91a674,
+ 0x263e82bc, 0x3a96b636, 0x264a0438, 0x3a9bc3b6,
+ 0x265586b3, 0x3aa0cef3, 0x26610a2a, 0x3aa5d7ee,
+ 0x266c8e9f, 0x3aaadea6, 0x26781410, 0x3aafe31b,
+ 0x26839a7c, 0x3ab4e54c, 0x268f21e5, 0x3ab9e53a,
+ 0x269aaa48, 0x3abee2e5, 0x26a633a6, 0x3ac3de4c,
+ 0x26b1bdff, 0x3ac8d76f, 0x26bd4951, 0x3acdce4d,
+ 0x26c8d59c, 0x3ad2c2e8, 0x26d462e1, 0x3ad7b53d,
+ 0x26dff11d, 0x3adca54e, 0x26eb8052, 0x3ae1931a,
+ 0x26f7107e, 0x3ae67ea1, 0x2702a1a1, 0x3aeb67e3,
+ 0x270e33bb, 0x3af04edf, 0x2719c6cb, 0x3af53395,
+ 0x27255ad1, 0x3afa1605, 0x2730efcc, 0x3afef630,
+ 0x273c85bc, 0x3b03d414, 0x27481ca1, 0x3b08afb2,
+ 0x2753b479, 0x3b0d8909, 0x275f4d45, 0x3b126019,
+ 0x276ae704, 0x3b1734e2, 0x277681b6, 0x3b1c0764,
+ 0x27821d59, 0x3b20d79e, 0x278db9ef, 0x3b25a591,
+ 0x27995776, 0x3b2a713d, 0x27a4f5ed, 0x3b2f3aa0,
+ 0x27b09555, 0x3b3401bb, 0x27bc35ad, 0x3b38c68e,
+ 0x27c7d6f4, 0x3b3d8918, 0x27d3792b, 0x3b42495a,
+ 0x27df1c50, 0x3b470753, 0x27eac063, 0x3b4bc303,
+ 0x27f66564, 0x3b507c69, 0x28020b52, 0x3b553386,
+ 0x280db22d, 0x3b59e85a, 0x281959f4, 0x3b5e9ae4,
+ 0x282502a7, 0x3b634b23, 0x2830ac45, 0x3b67f919,
+ 0x283c56cf, 0x3b6ca4c4, 0x28480243, 0x3b714e25,
+ 0x2853aea1, 0x3b75f53c, 0x285f5be9, 0x3b7a9a07,
+ 0x286b0a1a, 0x3b7f3c87, 0x2876b934, 0x3b83dcbc,
+ 0x28826936, 0x3b887aa6, 0x288e1a20, 0x3b8d1644,
+ 0x2899cbf1, 0x3b91af97, 0x28a57ea9, 0x3b96469d,
+ 0x28b13248, 0x3b9adb57, 0x28bce6cd, 0x3b9f6dc5,
+ 0x28c89c37, 0x3ba3fde7, 0x28d45286, 0x3ba88bbc,
+ 0x28e009ba, 0x3bad1744, 0x28ebc1d3, 0x3bb1a080,
+ 0x28f77acf, 0x3bb6276e, 0x290334af, 0x3bbaac0e,
+ 0x290eef71, 0x3bbf2e62, 0x291aab16, 0x3bc3ae67,
+ 0x2926679c, 0x3bc82c1f, 0x29322505, 0x3bcca789,
+ 0x293de34e, 0x3bd120a4, 0x2949a278, 0x3bd59771,
+ 0x29556282, 0x3bda0bf0, 0x2961236c, 0x3bde7e20,
+ 0x296ce535, 0x3be2ee01, 0x2978a7dd, 0x3be75b93,
+ 0x29846b63, 0x3bebc6d5, 0x29902fc7, 0x3bf02fc9,
+ 0x299bf509, 0x3bf4966c, 0x29a7bb28, 0x3bf8fac0,
+ 0x29b38223, 0x3bfd5cc4, 0x29bf49fa, 0x3c01bc78,
+ 0x29cb12ad, 0x3c0619dc, 0x29d6dc3b, 0x3c0a74f0,
+ 0x29e2a6a3, 0x3c0ecdb2, 0x29ee71e6, 0x3c132424,
+ 0x29fa3e03, 0x3c177845, 0x2a060af9, 0x3c1bca16,
+ 0x2a11d8c8, 0x3c201994, 0x2a1da770, 0x3c2466c2,
+ 0x2a2976ef, 0x3c28b19e, 0x2a354746, 0x3c2cfa28,
+ 0x2a411874, 0x3c314060, 0x2a4cea79, 0x3c358446,
+ 0x2a58bd54, 0x3c39c5da, 0x2a649105, 0x3c3e051b,
+ 0x2a70658a, 0x3c42420a, 0x2a7c3ae5, 0x3c467ca6,
+ 0x2a881114, 0x3c4ab4ef, 0x2a93e817, 0x3c4eeae5,
+ 0x2a9fbfed, 0x3c531e88, 0x2aab9896, 0x3c574fd8,
+ 0x2ab77212, 0x3c5b7ed4, 0x2ac34c60, 0x3c5fab7c,
+ 0x2acf277f, 0x3c63d5d1, 0x2adb0370, 0x3c67fdd1,
+ 0x2ae6e031, 0x3c6c237e, 0x2af2bdc3, 0x3c7046d6,
+ 0x2afe9c24, 0x3c7467d9, 0x2b0a7b54, 0x3c788688,
+ 0x2b165b54, 0x3c7ca2e2, 0x2b223c22, 0x3c80bce7,
+ 0x2b2e1dbe, 0x3c84d496, 0x2b3a0027, 0x3c88e9f1,
+ 0x2b45e35d, 0x3c8cfcf6, 0x2b51c760, 0x3c910da5,
+ 0x2b5dac2f, 0x3c951bff, 0x2b6991ca, 0x3c992803,
+ 0x2b75782f, 0x3c9d31b0, 0x2b815f60, 0x3ca13908,
+ 0x2b8d475b, 0x3ca53e09, 0x2b99301f, 0x3ca940b3,
+ 0x2ba519ad, 0x3cad4107, 0x2bb10404, 0x3cb13f04,
+ 0x2bbcef23, 0x3cb53aaa, 0x2bc8db0b, 0x3cb933f9,
+ 0x2bd4c7ba, 0x3cbd2af0, 0x2be0b52f, 0x3cc11f90,
+ 0x2beca36c, 0x3cc511d9, 0x2bf8926f, 0x3cc901c9,
+ 0x2c048237, 0x3cccef62, 0x2c1072c4, 0x3cd0daa2,
+ 0x2c1c6417, 0x3cd4c38b, 0x2c28562d, 0x3cd8aa1b,
+ 0x2c344908, 0x3cdc8e52, 0x2c403ca5, 0x3ce07031,
+ 0x2c4c3106, 0x3ce44fb7, 0x2c582629, 0x3ce82ce4,
+ 0x2c641c0e, 0x3cec07b8, 0x2c7012b5, 0x3cefe032,
+ 0x2c7c0a1d, 0x3cf3b653, 0x2c880245, 0x3cf78a1b,
+ 0x2c93fb2e, 0x3cfb5b89, 0x2c9ff4d6, 0x3cff2a9d,
+ 0x2cabef3d, 0x3d02f757, 0x2cb7ea63, 0x3d06c1b6,
+ 0x2cc3e648, 0x3d0a89bc, 0x2ccfe2ea, 0x3d0e4f67,
+ 0x2cdbe04a, 0x3d1212b7, 0x2ce7de66, 0x3d15d3ad,
+ 0x2cf3dd3f, 0x3d199248, 0x2cffdcd4, 0x3d1d4e88,
+ 0x2d0bdd25, 0x3d21086c, 0x2d17de31, 0x3d24bff6,
+ 0x2d23dff7, 0x3d287523, 0x2d2fe277, 0x3d2c27f6,
+ 0x2d3be5b1, 0x3d2fd86c, 0x2d47e9a5, 0x3d338687,
+ 0x2d53ee51, 0x3d373245, 0x2d5ff3b5, 0x3d3adba7,
+ 0x2d6bf9d1, 0x3d3e82ae, 0x2d7800a5, 0x3d422757,
+ 0x2d84082f, 0x3d45c9a4, 0x2d901070, 0x3d496994,
+ 0x2d9c1967, 0x3d4d0728, 0x2da82313, 0x3d50a25e,
+ 0x2db42d74, 0x3d543b37, 0x2dc0388a, 0x3d57d1b3,
+ 0x2dcc4454, 0x3d5b65d2, 0x2dd850d2, 0x3d5ef793,
+ 0x2de45e03, 0x3d6286f6, 0x2df06be6, 0x3d6613fb,
+ 0x2dfc7a7c, 0x3d699ea3, 0x2e0889c4, 0x3d6d26ec,
+ 0x2e1499bd, 0x3d70acd7, 0x2e20aa67, 0x3d743064,
+ 0x2e2cbbc1, 0x3d77b192, 0x2e38cdcb, 0x3d7b3061,
+ 0x2e44e084, 0x3d7eacd2, 0x2e50f3ed, 0x3d8226e4,
+ 0x2e5d0804, 0x3d859e96, 0x2e691cc9, 0x3d8913ea,
+ 0x2e75323c, 0x3d8c86de, 0x2e81485c, 0x3d8ff772,
+ 0x2e8d5f29, 0x3d9365a8, 0x2e9976a1, 0x3d96d17d,
+ 0x2ea58ec6, 0x3d9a3af2, 0x2eb1a796, 0x3d9da208,
+ 0x2ebdc110, 0x3da106bd, 0x2ec9db35, 0x3da46912,
+ 0x2ed5f604, 0x3da7c907, 0x2ee2117c, 0x3dab269b,
+ 0x2eee2d9d, 0x3dae81cf, 0x2efa4a67, 0x3db1daa2,
+ 0x2f0667d9, 0x3db53113, 0x2f1285f2, 0x3db88524,
+ 0x2f1ea4b2, 0x3dbbd6d4, 0x2f2ac419, 0x3dbf2622,
+ 0x2f36e426, 0x3dc2730f, 0x2f4304d8, 0x3dc5bd9b,
+ 0x2f4f2630, 0x3dc905c5, 0x2f5b482d, 0x3dcc4b8d,
+ 0x2f676ace, 0x3dcf8ef3, 0x2f738e12, 0x3dd2cff7,
+ 0x2f7fb1fa, 0x3dd60e99, 0x2f8bd685, 0x3dd94ad8,
+ 0x2f97fbb2, 0x3ddc84b5, 0x2fa42181, 0x3ddfbc30,
+ 0x2fb047f2, 0x3de2f148, 0x2fbc6f03, 0x3de623fd,
+ 0x2fc896b5, 0x3de9544f, 0x2fd4bf08, 0x3dec823e,
+ 0x2fe0e7f9, 0x3defadca, 0x2fed118a, 0x3df2d6f3,
+ 0x2ff93bba, 0x3df5fdb8, 0x30056687, 0x3df9221a,
+ 0x301191f3, 0x3dfc4418, 0x301dbdfb, 0x3dff63b2,
+ 0x3029eaa1, 0x3e0280e9, 0x303617e2, 0x3e059bbb,
+ 0x304245c0, 0x3e08b42a, 0x304e7438, 0x3e0bca34,
+ 0x305aa34c, 0x3e0eddd9, 0x3066d2fa, 0x3e11ef1b,
+ 0x30730342, 0x3e14fdf7, 0x307f3424, 0x3e180a6f,
+ 0x308b659f, 0x3e1b1482, 0x309797b2, 0x3e1e1c30,
+ 0x30a3ca5d, 0x3e212179, 0x30affda0, 0x3e24245d,
+ 0x30bc317a, 0x3e2724db, 0x30c865ea, 0x3e2a22f4,
+ 0x30d49af1, 0x3e2d1ea8, 0x30e0d08d, 0x3e3017f6,
+ 0x30ed06bf, 0x3e330ede, 0x30f93d86, 0x3e360360,
+ 0x310574e0, 0x3e38f57c, 0x3111accf, 0x3e3be532,
+ 0x311de551, 0x3e3ed282, 0x312a1e66, 0x3e41bd6c,
+ 0x3136580d, 0x3e44a5ef, 0x31429247, 0x3e478c0b,
+ 0x314ecd11, 0x3e4a6fc1, 0x315b086d, 0x3e4d5110,
+ 0x31674459, 0x3e502ff9, 0x317380d6, 0x3e530c7a,
+ 0x317fbde2, 0x3e55e694, 0x318bfb7d, 0x3e58be47,
+ 0x319839a6, 0x3e5b9392, 0x31a4785e, 0x3e5e6676,
+ 0x31b0b7a4, 0x3e6136f3, 0x31bcf777, 0x3e640507,
+ 0x31c937d6, 0x3e66d0b4, 0x31d578c2, 0x3e6999fa,
+ 0x31e1ba3a, 0x3e6c60d7, 0x31edfc3d, 0x3e6f254c,
+ 0x31fa3ecb, 0x3e71e759, 0x320681e3, 0x3e74a6fd,
+ 0x3212c585, 0x3e77643a, 0x321f09b1, 0x3e7a1f0d,
+ 0x322b4e66, 0x3e7cd778, 0x323793a3, 0x3e7f8d7b,
+ 0x3243d968, 0x3e824114, 0x32501fb5, 0x3e84f245,
+ 0x325c6688, 0x3e87a10c, 0x3268ade3, 0x3e8a4d6a,
+ 0x3274f5c3, 0x3e8cf75f, 0x32813e2a, 0x3e8f9eeb,
+ 0x328d8715, 0x3e92440d, 0x3299d085, 0x3e94e6c6,
+ 0x32a61a7a, 0x3e978715, 0x32b264f2, 0x3e9a24fb,
+ 0x32beafed, 0x3e9cc076, 0x32cafb6b, 0x3e9f5988,
+ 0x32d7476c, 0x3ea1f02f, 0x32e393ef, 0x3ea4846c,
+ 0x32efe0f2, 0x3ea7163f, 0x32fc2e77, 0x3ea9a5a8,
+ 0x33087c7d, 0x3eac32a6, 0x3314cb02, 0x3eaebd3a,
+ 0x33211a07, 0x3eb14563, 0x332d698a, 0x3eb3cb21,
+ 0x3339b98d, 0x3eb64e75, 0x33460a0d, 0x3eb8cf5d,
+ 0x33525b0b, 0x3ebb4ddb, 0x335eac86, 0x3ebdc9ed,
+ 0x336afe7e, 0x3ec04394, 0x337750f2, 0x3ec2bad0,
+ 0x3383a3e2, 0x3ec52fa0, 0x338ff74d, 0x3ec7a205,
+ 0x339c4b32, 0x3eca11fe, 0x33a89f92, 0x3ecc7f8b,
+ 0x33b4f46c, 0x3eceeaad, 0x33c149bf, 0x3ed15363,
+ 0x33cd9f8b, 0x3ed3b9ad, 0x33d9f5cf, 0x3ed61d8a,
+ 0x33e64c8c, 0x3ed87efc, 0x33f2a3bf, 0x3edade01,
+ 0x33fefb6a, 0x3edd3a9a, 0x340b538b, 0x3edf94c7,
+ 0x3417ac22, 0x3ee1ec87, 0x3424052f, 0x3ee441da,
+ 0x34305eb0, 0x3ee694c1, 0x343cb8a7, 0x3ee8e53a,
+ 0x34491311, 0x3eeb3347, 0x34556def, 0x3eed7ee7,
+ 0x3461c940, 0x3eefc81a, 0x346e2504, 0x3ef20ee0,
+ 0x347a8139, 0x3ef45338, 0x3486dde1, 0x3ef69523,
+ 0x34933afa, 0x3ef8d4a1, 0x349f9884, 0x3efb11b1,
+ 0x34abf67e, 0x3efd4c54, 0x34b854e7, 0x3eff8489,
+ 0x34c4b3c0, 0x3f01ba50, 0x34d11308, 0x3f03eda9,
+ 0x34dd72be, 0x3f061e95, 0x34e9d2e3, 0x3f084d12,
+ 0x34f63374, 0x3f0a7921, 0x35029473, 0x3f0ca2c2,
+ 0x350ef5de, 0x3f0ec9f5, 0x351b57b5, 0x3f10eeb9,
+ 0x3527b9f7, 0x3f13110f, 0x35341ca5, 0x3f1530f7,
+ 0x35407fbd, 0x3f174e70, 0x354ce33f, 0x3f19697a,
+ 0x3559472b, 0x3f1b8215, 0x3565ab80, 0x3f1d9842,
+ 0x3572103d, 0x3f1fabff, 0x357e7563, 0x3f21bd4e,
+ 0x358adaf0, 0x3f23cc2e, 0x359740e5, 0x3f25d89e,
+ 0x35a3a740, 0x3f27e29f, 0x35b00e02, 0x3f29ea31,
+ 0x35bc7529, 0x3f2bef53, 0x35c8dcb6, 0x3f2df206,
+ 0x35d544a7, 0x3f2ff24a, 0x35e1acfd, 0x3f31f01d,
+ 0x35ee15b7, 0x3f33eb81, 0x35fa7ed4, 0x3f35e476,
+ 0x3606e854, 0x3f37dafa, 0x36135237, 0x3f39cf0e,
+ 0x361fbc7b, 0x3f3bc0b3, 0x362c2721, 0x3f3dafe7,
+ 0x36389228, 0x3f3f9cab, 0x3644fd8f, 0x3f4186ff,
+ 0x36516956, 0x3f436ee3, 0x365dd57d, 0x3f455456,
+ 0x366a4203, 0x3f473759, 0x3676aee8, 0x3f4917eb,
+ 0x36831c2b, 0x3f4af60d, 0x368f89cb, 0x3f4cd1be,
+ 0x369bf7c9, 0x3f4eaafe, 0x36a86623, 0x3f5081cd,
+ 0x36b4d4d9, 0x3f52562c, 0x36c143ec, 0x3f54281a,
+ 0x36cdb359, 0x3f55f796, 0x36da2321, 0x3f57c4a2,
+ 0x36e69344, 0x3f598f3c, 0x36f303c0, 0x3f5b5765,
+ 0x36ff7496, 0x3f5d1d1d, 0x370be5c4, 0x3f5ee063,
+ 0x3718574b, 0x3f60a138, 0x3724c92a, 0x3f625f9b,
+ 0x37313b60, 0x3f641b8d, 0x373daded, 0x3f65d50d,
+ 0x374a20d0, 0x3f678c1c, 0x3756940a, 0x3f6940b8,
+ 0x37630799, 0x3f6af2e3, 0x376f7b7d, 0x3f6ca29c,
+ 0x377befb5, 0x3f6e4fe3, 0x37886442, 0x3f6ffab8,
+ 0x3794d922, 0x3f71a31b, 0x37a14e55, 0x3f73490b,
+ 0x37adc3db, 0x3f74ec8a, 0x37ba39b3, 0x3f768d96,
+ 0x37c6afdc, 0x3f782c30, 0x37d32657, 0x3f79c857,
+ 0x37df9d22, 0x3f7b620c, 0x37ec143e, 0x3f7cf94e,
+ 0x37f88ba9, 0x3f7e8e1e, 0x38050364, 0x3f80207b,
+ 0x38117b6d, 0x3f81b065, 0x381df3c5, 0x3f833ddd,
+ 0x382a6c6a, 0x3f84c8e2, 0x3836e55d, 0x3f865174,
+ 0x38435e9d, 0x3f87d792, 0x384fd829, 0x3f895b3e,
+ 0x385c5201, 0x3f8adc77, 0x3868cc24, 0x3f8c5b3d,
+ 0x38754692, 0x3f8dd78f, 0x3881c14b, 0x3f8f516e,
+ 0x388e3c4d, 0x3f90c8da, 0x389ab799, 0x3f923dd2,
+ 0x38a7332e, 0x3f93b058, 0x38b3af0c, 0x3f952069,
+ 0x38c02b31, 0x3f968e07, 0x38cca79e, 0x3f97f932,
+ 0x38d92452, 0x3f9961e8, 0x38e5a14d, 0x3f9ac82c,
+ 0x38f21e8e, 0x3f9c2bfb, 0x38fe9c15, 0x3f9d8d56,
+ 0x390b19e0, 0x3f9eec3e, 0x391797f0, 0x3fa048b2,
+ 0x39241645, 0x3fa1a2b2, 0x393094dd, 0x3fa2fa3d,
+ 0x393d13b8, 0x3fa44f55, 0x394992d7, 0x3fa5a1f9,
+ 0x39561237, 0x3fa6f228, 0x396291d9, 0x3fa83fe3,
+ 0x396f11bc, 0x3fa98b2a, 0x397b91e1, 0x3faad3fd,
+ 0x39881245, 0x3fac1a5b, 0x399492ea, 0x3fad5e45,
+ 0x39a113cd, 0x3fae9fbb, 0x39ad94f0, 0x3fafdebb,
+ 0x39ba1651, 0x3fb11b48, 0x39c697f0, 0x3fb2555f,
+ 0x39d319cc, 0x3fb38d02, 0x39df9be6, 0x3fb4c231,
+ 0x39ec1e3b, 0x3fb5f4ea, 0x39f8a0cd, 0x3fb7252f,
+ 0x3a05239a, 0x3fb852ff, 0x3a11a6a3, 0x3fb97e5a,
+ 0x3a1e29e5, 0x3fbaa740, 0x3a2aad62, 0x3fbbcdb1,
+ 0x3a373119, 0x3fbcf1ad, 0x3a43b508, 0x3fbe1334,
+ 0x3a503930, 0x3fbf3246, 0x3a5cbd91, 0x3fc04ee3,
+ 0x3a694229, 0x3fc1690a, 0x3a75c6f8, 0x3fc280bc,
+ 0x3a824bfd, 0x3fc395f9, 0x3a8ed139, 0x3fc4a8c1,
+ 0x3a9b56ab, 0x3fc5b913, 0x3aa7dc52, 0x3fc6c6f0,
+ 0x3ab4622d, 0x3fc7d258, 0x3ac0e83d, 0x3fc8db4a,
+ 0x3acd6e81, 0x3fc9e1c6, 0x3ad9f4f8, 0x3fcae5cd,
+ 0x3ae67ba2, 0x3fcbe75e, 0x3af3027e, 0x3fcce67a,
+ 0x3aff898c, 0x3fcde320, 0x3b0c10cb, 0x3fcedd50,
+ 0x3b18983b, 0x3fcfd50b, 0x3b251fdc, 0x3fd0ca4f,
+ 0x3b31a7ac, 0x3fd1bd1e, 0x3b3e2fac, 0x3fd2ad77,
+ 0x3b4ab7db, 0x3fd39b5a, 0x3b574039, 0x3fd486c7,
+ 0x3b63c8c4, 0x3fd56fbe, 0x3b70517d, 0x3fd6563f,
+ 0x3b7cda63, 0x3fd73a4a, 0x3b896375, 0x3fd81bdf,
+ 0x3b95ecb4, 0x3fd8fafe, 0x3ba2761e, 0x3fd9d7a7,
+ 0x3baeffb3, 0x3fdab1d9, 0x3bbb8973, 0x3fdb8996,
+ 0x3bc8135c, 0x3fdc5edc, 0x3bd49d70, 0x3fdd31ac,
+ 0x3be127ac, 0x3fde0205, 0x3bedb212, 0x3fdecfe8,
+ 0x3bfa3c9f, 0x3fdf9b55, 0x3c06c754, 0x3fe0644b,
+ 0x3c135231, 0x3fe12acb, 0x3c1fdd34, 0x3fe1eed5,
+ 0x3c2c685d, 0x3fe2b067, 0x3c38f3ac, 0x3fe36f84,
+ 0x3c457f21, 0x3fe42c2a, 0x3c520aba, 0x3fe4e659,
+ 0x3c5e9678, 0x3fe59e12, 0x3c6b2259, 0x3fe65354,
+ 0x3c77ae5e, 0x3fe7061f, 0x3c843a85, 0x3fe7b674,
+ 0x3c90c6cf, 0x3fe86452, 0x3c9d533b, 0x3fe90fb9,
+ 0x3ca9dfc8, 0x3fe9b8a9, 0x3cb66c77, 0x3fea5f23,
+ 0x3cc2f945, 0x3feb0326, 0x3ccf8634, 0x3feba4b2,
+ 0x3cdc1342, 0x3fec43c7, 0x3ce8a06f, 0x3fece065,
+ 0x3cf52dbb, 0x3fed7a8c, 0x3d01bb24, 0x3fee123d,
+ 0x3d0e48ab, 0x3feea776, 0x3d1ad650, 0x3fef3a39,
+ 0x3d276410, 0x3fefca84, 0x3d33f1ed, 0x3ff05858,
+ 0x3d407fe6, 0x3ff0e3b6, 0x3d4d0df9, 0x3ff16c9c,
+ 0x3d599c28, 0x3ff1f30b, 0x3d662a70, 0x3ff27703,
+ 0x3d72b8d2, 0x3ff2f884, 0x3d7f474d, 0x3ff3778e,
+ 0x3d8bd5e1, 0x3ff3f420, 0x3d98648d, 0x3ff46e3c,
+ 0x3da4f351, 0x3ff4e5e0, 0x3db1822c, 0x3ff55b0d,
+ 0x3dbe111e, 0x3ff5cdc3, 0x3dcaa027, 0x3ff63e01,
+ 0x3dd72f45, 0x3ff6abc8, 0x3de3be78, 0x3ff71718,
+ 0x3df04dc0, 0x3ff77ff1, 0x3dfcdd1d, 0x3ff7e652,
+ 0x3e096c8d, 0x3ff84a3c, 0x3e15fc11, 0x3ff8abae,
+ 0x3e228ba7, 0x3ff90aaa, 0x3e2f1b50, 0x3ff9672d,
+ 0x3e3bab0b, 0x3ff9c13a, 0x3e483ad8, 0x3ffa18cf,
+ 0x3e54cab5, 0x3ffa6dec, 0x3e615aa3, 0x3ffac092,
+ 0x3e6deaa1, 0x3ffb10c1, 0x3e7a7aae, 0x3ffb5e78,
+ 0x3e870aca, 0x3ffba9b8, 0x3e939af5, 0x3ffbf280,
+ 0x3ea02b2e, 0x3ffc38d1, 0x3eacbb74, 0x3ffc7caa,
+ 0x3eb94bc8, 0x3ffcbe0c, 0x3ec5dc28, 0x3ffcfcf6,
+ 0x3ed26c94, 0x3ffd3969, 0x3edefd0c, 0x3ffd7364,
+ 0x3eeb8d8f, 0x3ffdaae7, 0x3ef81e1d, 0x3ffddff3,
+ 0x3f04aeb5, 0x3ffe1288, 0x3f113f56, 0x3ffe42a4,
+ 0x3f1dd001, 0x3ffe704a, 0x3f2a60b4, 0x3ffe9b77,
+ 0x3f36f170, 0x3ffec42d, 0x3f438234, 0x3ffeea6c,
+ 0x3f5012fe, 0x3fff0e32, 0x3f5ca3d0, 0x3fff2f82,
+ 0x3f6934a8, 0x3fff4e59, 0x3f75c585, 0x3fff6ab9,
+ 0x3f825668, 0x3fff84a1, 0x3f8ee750, 0x3fff9c12,
+ 0x3f9b783c, 0x3fffb10b, 0x3fa8092c, 0x3fffc38c,
+ 0x3fb49a1f, 0x3fffd396, 0x3fc12b16, 0x3fffe128,
+ 0x3fcdbc0f, 0x3fffec43, 0x3fda4d09, 0x3ffff4e6,
+ 0x3fe6de05, 0x3ffffb11, 0x3ff36f02, 0x3ffffec4,
+};
+
+
+/**
+* \par
+* Generation of realCoefBQ31 array:
+* \par
+* n = 4096
+* <pre>for (i = 0; i < n; i++)
+* {
+* pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));
+* pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));
+* } </pre>
+* \par
+* Convert to fixed point Q31 format
+* round(pBTable[i] * pow(2, 31))
+*
+*/
+
+static const q31_t realCoefBQ31[8192] = {
+ 0x40000000, 0x40000000, 0x400c90fe, 0x3ffffec4,
+ 0x401921fb, 0x3ffffb11, 0x4025b2f7, 0x3ffff4e6,
+ 0x403243f1, 0x3fffec43, 0x403ed4ea, 0x3fffe128,
+ 0x404b65e1, 0x3fffd396, 0x4057f6d4, 0x3fffc38c,
+ 0x406487c4, 0x3fffb10b, 0x407118b0, 0x3fff9c12,
+ 0x407da998, 0x3fff84a1, 0x408a3a7b, 0x3fff6ab9,
+ 0x4096cb58, 0x3fff4e59, 0x40a35c30, 0x3fff2f82,
+ 0x40afed02, 0x3fff0e32, 0x40bc7dcc, 0x3ffeea6c,
+ 0x40c90e90, 0x3ffec42d, 0x40d59f4c, 0x3ffe9b77,
+ 0x40e22fff, 0x3ffe704a, 0x40eec0aa, 0x3ffe42a4,
+ 0x40fb514b, 0x3ffe1288, 0x4107e1e3, 0x3ffddff3,
+ 0x41147271, 0x3ffdaae7, 0x412102f4, 0x3ffd7364,
+ 0x412d936c, 0x3ffd3969, 0x413a23d8, 0x3ffcfcf6,
+ 0x4146b438, 0x3ffcbe0c, 0x4153448c, 0x3ffc7caa,
+ 0x415fd4d2, 0x3ffc38d1, 0x416c650b, 0x3ffbf280,
+ 0x4178f536, 0x3ffba9b8, 0x41858552, 0x3ffb5e78,
+ 0x4192155f, 0x3ffb10c1, 0x419ea55d, 0x3ffac092,
+ 0x41ab354b, 0x3ffa6dec, 0x41b7c528, 0x3ffa18cf,
+ 0x41c454f5, 0x3ff9c13a, 0x41d0e4b0, 0x3ff9672d,
+ 0x41dd7459, 0x3ff90aaa, 0x41ea03ef, 0x3ff8abae,
+ 0x41f69373, 0x3ff84a3c, 0x420322e3, 0x3ff7e652,
+ 0x420fb240, 0x3ff77ff1, 0x421c4188, 0x3ff71718,
+ 0x4228d0bb, 0x3ff6abc8, 0x42355fd9, 0x3ff63e01,
+ 0x4241eee2, 0x3ff5cdc3, 0x424e7dd4, 0x3ff55b0d,
+ 0x425b0caf, 0x3ff4e5e0, 0x42679b73, 0x3ff46e3c,
+ 0x42742a1f, 0x3ff3f420, 0x4280b8b3, 0x3ff3778e,
+ 0x428d472e, 0x3ff2f884, 0x4299d590, 0x3ff27703,
+ 0x42a663d8, 0x3ff1f30b, 0x42b2f207, 0x3ff16c9c,
+ 0x42bf801a, 0x3ff0e3b6, 0x42cc0e13, 0x3ff05858,
+ 0x42d89bf0, 0x3fefca84, 0x42e529b0, 0x3fef3a39,
+ 0x42f1b755, 0x3feea776, 0x42fe44dc, 0x3fee123d,
+ 0x430ad245, 0x3fed7a8c, 0x43175f91, 0x3fece065,
+ 0x4323ecbe, 0x3fec43c7, 0x433079cc, 0x3feba4b2,
+ 0x433d06bb, 0x3feb0326, 0x43499389, 0x3fea5f23,
+ 0x43562038, 0x3fe9b8a9, 0x4362acc5, 0x3fe90fb9,
+ 0x436f3931, 0x3fe86452, 0x437bc57b, 0x3fe7b674,
+ 0x438851a2, 0x3fe7061f, 0x4394dda7, 0x3fe65354,
+ 0x43a16988, 0x3fe59e12, 0x43adf546, 0x3fe4e659,
+ 0x43ba80df, 0x3fe42c2a, 0x43c70c54, 0x3fe36f84,
+ 0x43d397a3, 0x3fe2b067, 0x43e022cc, 0x3fe1eed5,
+ 0x43ecadcf, 0x3fe12acb, 0x43f938ac, 0x3fe0644b,
+ 0x4405c361, 0x3fdf9b55, 0x44124dee, 0x3fdecfe8,
+ 0x441ed854, 0x3fde0205, 0x442b6290, 0x3fdd31ac,
+ 0x4437eca4, 0x3fdc5edc, 0x4444768d, 0x3fdb8996,
+ 0x4451004d, 0x3fdab1d9, 0x445d89e2, 0x3fd9d7a7,
+ 0x446a134c, 0x3fd8fafe, 0x44769c8b, 0x3fd81bdf,
+ 0x4483259d, 0x3fd73a4a, 0x448fae83, 0x3fd6563f,
+ 0x449c373c, 0x3fd56fbe, 0x44a8bfc7, 0x3fd486c7,
+ 0x44b54825, 0x3fd39b5a, 0x44c1d054, 0x3fd2ad77,
+ 0x44ce5854, 0x3fd1bd1e, 0x44dae024, 0x3fd0ca4f,
+ 0x44e767c5, 0x3fcfd50b, 0x44f3ef35, 0x3fcedd50,
+ 0x45007674, 0x3fcde320, 0x450cfd82, 0x3fcce67a,
+ 0x4519845e, 0x3fcbe75e, 0x45260b08, 0x3fcae5cd,
+ 0x4532917f, 0x3fc9e1c6, 0x453f17c3, 0x3fc8db4a,
+ 0x454b9dd3, 0x3fc7d258, 0x455823ae, 0x3fc6c6f0,
+ 0x4564a955, 0x3fc5b913, 0x45712ec7, 0x3fc4a8c1,
+ 0x457db403, 0x3fc395f9, 0x458a3908, 0x3fc280bc,
+ 0x4596bdd7, 0x3fc1690a, 0x45a3426f, 0x3fc04ee3,
+ 0x45afc6d0, 0x3fbf3246, 0x45bc4af8, 0x3fbe1334,
+ 0x45c8cee7, 0x3fbcf1ad, 0x45d5529e, 0x3fbbcdb1,
+ 0x45e1d61b, 0x3fbaa740, 0x45ee595d, 0x3fb97e5a,
+ 0x45fadc66, 0x3fb852ff, 0x46075f33, 0x3fb7252f,
+ 0x4613e1c5, 0x3fb5f4ea, 0x4620641a, 0x3fb4c231,
+ 0x462ce634, 0x3fb38d02, 0x46396810, 0x3fb2555f,
+ 0x4645e9af, 0x3fb11b48, 0x46526b10, 0x3fafdebb,
+ 0x465eec33, 0x3fae9fbb, 0x466b6d16, 0x3fad5e45,
+ 0x4677edbb, 0x3fac1a5b, 0x46846e1f, 0x3faad3fd,
+ 0x4690ee44, 0x3fa98b2a, 0x469d6e27, 0x3fa83fe3,
+ 0x46a9edc9, 0x3fa6f228, 0x46b66d29, 0x3fa5a1f9,
+ 0x46c2ec48, 0x3fa44f55, 0x46cf6b23, 0x3fa2fa3d,
+ 0x46dbe9bb, 0x3fa1a2b2, 0x46e86810, 0x3fa048b2,
+ 0x46f4e620, 0x3f9eec3e, 0x470163eb, 0x3f9d8d56,
+ 0x470de172, 0x3f9c2bfb, 0x471a5eb3, 0x3f9ac82c,
+ 0x4726dbae, 0x3f9961e8, 0x47335862, 0x3f97f932,
+ 0x473fd4cf, 0x3f968e07, 0x474c50f4, 0x3f952069,
+ 0x4758ccd2, 0x3f93b058, 0x47654867, 0x3f923dd2,
+ 0x4771c3b3, 0x3f90c8da, 0x477e3eb5, 0x3f8f516e,
+ 0x478ab96e, 0x3f8dd78f, 0x479733dc, 0x3f8c5b3d,
+ 0x47a3adff, 0x3f8adc77, 0x47b027d7, 0x3f895b3e,
+ 0x47bca163, 0x3f87d792, 0x47c91aa3, 0x3f865174,
+ 0x47d59396, 0x3f84c8e2, 0x47e20c3b, 0x3f833ddd,
+ 0x47ee8493, 0x3f81b065, 0x47fafc9c, 0x3f80207b,
+ 0x48077457, 0x3f7e8e1e, 0x4813ebc2, 0x3f7cf94e,
+ 0x482062de, 0x3f7b620c, 0x482cd9a9, 0x3f79c857,
+ 0x48395024, 0x3f782c30, 0x4845c64d, 0x3f768d96,
+ 0x48523c25, 0x3f74ec8a, 0x485eb1ab, 0x3f73490b,
+ 0x486b26de, 0x3f71a31b, 0x48779bbe, 0x3f6ffab8,
+ 0x4884104b, 0x3f6e4fe3, 0x48908483, 0x3f6ca29c,
+ 0x489cf867, 0x3f6af2e3, 0x48a96bf6, 0x3f6940b8,
+ 0x48b5df30, 0x3f678c1c, 0x48c25213, 0x3f65d50d,
+ 0x48cec4a0, 0x3f641b8d, 0x48db36d6, 0x3f625f9b,
+ 0x48e7a8b5, 0x3f60a138, 0x48f41a3c, 0x3f5ee063,
+ 0x49008b6a, 0x3f5d1d1d, 0x490cfc40, 0x3f5b5765,
+ 0x49196cbc, 0x3f598f3c, 0x4925dcdf, 0x3f57c4a2,
+ 0x49324ca7, 0x3f55f796, 0x493ebc14, 0x3f54281a,
+ 0x494b2b27, 0x3f52562c, 0x495799dd, 0x3f5081cd,
+ 0x49640837, 0x3f4eaafe, 0x49707635, 0x3f4cd1be,
+ 0x497ce3d5, 0x3f4af60d, 0x49895118, 0x3f4917eb,
+ 0x4995bdfd, 0x3f473759, 0x49a22a83, 0x3f455456,
+ 0x49ae96aa, 0x3f436ee3, 0x49bb0271, 0x3f4186ff,
+ 0x49c76dd8, 0x3f3f9cab, 0x49d3d8df, 0x3f3dafe7,
+ 0x49e04385, 0x3f3bc0b3, 0x49ecadc9, 0x3f39cf0e,
+ 0x49f917ac, 0x3f37dafa, 0x4a05812c, 0x3f35e476,
+ 0x4a11ea49, 0x3f33eb81, 0x4a1e5303, 0x3f31f01d,
+ 0x4a2abb59, 0x3f2ff24a, 0x4a37234a, 0x3f2df206,
+ 0x4a438ad7, 0x3f2bef53, 0x4a4ff1fe, 0x3f29ea31,
+ 0x4a5c58c0, 0x3f27e29f, 0x4a68bf1b, 0x3f25d89e,
+ 0x4a752510, 0x3f23cc2e, 0x4a818a9d, 0x3f21bd4e,
+ 0x4a8defc3, 0x3f1fabff, 0x4a9a5480, 0x3f1d9842,
+ 0x4aa6b8d5, 0x3f1b8215, 0x4ab31cc1, 0x3f19697a,
+ 0x4abf8043, 0x3f174e70, 0x4acbe35b, 0x3f1530f7,
+ 0x4ad84609, 0x3f13110f, 0x4ae4a84b, 0x3f10eeb9,
+ 0x4af10a22, 0x3f0ec9f5, 0x4afd6b8d, 0x3f0ca2c2,
+ 0x4b09cc8c, 0x3f0a7921, 0x4b162d1d, 0x3f084d12,
+ 0x4b228d42, 0x3f061e95, 0x4b2eecf8, 0x3f03eda9,
+ 0x4b3b4c40, 0x3f01ba50, 0x4b47ab19, 0x3eff8489,
+ 0x4b540982, 0x3efd4c54, 0x4b60677c, 0x3efb11b1,
+ 0x4b6cc506, 0x3ef8d4a1, 0x4b79221f, 0x3ef69523,
+ 0x4b857ec7, 0x3ef45338, 0x4b91dafc, 0x3ef20ee0,
+ 0x4b9e36c0, 0x3eefc81a, 0x4baa9211, 0x3eed7ee7,
+ 0x4bb6ecef, 0x3eeb3347, 0x4bc34759, 0x3ee8e53a,
+ 0x4bcfa150, 0x3ee694c1, 0x4bdbfad1, 0x3ee441da,
+ 0x4be853de, 0x3ee1ec87, 0x4bf4ac75, 0x3edf94c7,
+ 0x4c010496, 0x3edd3a9a, 0x4c0d5c41, 0x3edade01,
+ 0x4c19b374, 0x3ed87efc, 0x4c260a31, 0x3ed61d8a,
+ 0x4c326075, 0x3ed3b9ad, 0x4c3eb641, 0x3ed15363,
+ 0x4c4b0b94, 0x3eceeaad, 0x4c57606e, 0x3ecc7f8b,
+ 0x4c63b4ce, 0x3eca11fe, 0x4c7008b3, 0x3ec7a205,
+ 0x4c7c5c1e, 0x3ec52fa0, 0x4c88af0e, 0x3ec2bad0,
+ 0x4c950182, 0x3ec04394, 0x4ca1537a, 0x3ebdc9ed,
+ 0x4cada4f5, 0x3ebb4ddb, 0x4cb9f5f3, 0x3eb8cf5d,
+ 0x4cc64673, 0x3eb64e75, 0x4cd29676, 0x3eb3cb21,
+ 0x4cdee5f9, 0x3eb14563, 0x4ceb34fe, 0x3eaebd3a,
+ 0x4cf78383, 0x3eac32a6, 0x4d03d189, 0x3ea9a5a8,
+ 0x4d101f0e, 0x3ea7163f, 0x4d1c6c11, 0x3ea4846c,
+ 0x4d28b894, 0x3ea1f02f, 0x4d350495, 0x3e9f5988,
+ 0x4d415013, 0x3e9cc076, 0x4d4d9b0e, 0x3e9a24fb,
+ 0x4d59e586, 0x3e978715, 0x4d662f7b, 0x3e94e6c6,
+ 0x4d7278eb, 0x3e92440d, 0x4d7ec1d6, 0x3e8f9eeb,
+ 0x4d8b0a3d, 0x3e8cf75f, 0x4d97521d, 0x3e8a4d6a,
+ 0x4da39978, 0x3e87a10c, 0x4dafe04b, 0x3e84f245,
+ 0x4dbc2698, 0x3e824114, 0x4dc86c5d, 0x3e7f8d7b,
+ 0x4dd4b19a, 0x3e7cd778, 0x4de0f64f, 0x3e7a1f0d,
+ 0x4ded3a7b, 0x3e77643a, 0x4df97e1d, 0x3e74a6fd,
+ 0x4e05c135, 0x3e71e759, 0x4e1203c3, 0x3e6f254c,
+ 0x4e1e45c6, 0x3e6c60d7, 0x4e2a873e, 0x3e6999fa,
+ 0x4e36c82a, 0x3e66d0b4, 0x4e430889, 0x3e640507,
+ 0x4e4f485c, 0x3e6136f3, 0x4e5b87a2, 0x3e5e6676,
+ 0x4e67c65a, 0x3e5b9392, 0x4e740483, 0x3e58be47,
+ 0x4e80421e, 0x3e55e694, 0x4e8c7f2a, 0x3e530c7a,
+ 0x4e98bba7, 0x3e502ff9, 0x4ea4f793, 0x3e4d5110,
+ 0x4eb132ef, 0x3e4a6fc1, 0x4ebd6db9, 0x3e478c0b,
+ 0x4ec9a7f3, 0x3e44a5ef, 0x4ed5e19a, 0x3e41bd6c,
+ 0x4ee21aaf, 0x3e3ed282, 0x4eee5331, 0x3e3be532,
+ 0x4efa8b20, 0x3e38f57c, 0x4f06c27a, 0x3e360360,
+ 0x4f12f941, 0x3e330ede, 0x4f1f2f73, 0x3e3017f6,
+ 0x4f2b650f, 0x3e2d1ea8, 0x4f379a16, 0x3e2a22f4,
+ 0x4f43ce86, 0x3e2724db, 0x4f500260, 0x3e24245d,
+ 0x4f5c35a3, 0x3e212179, 0x4f68684e, 0x3e1e1c30,
+ 0x4f749a61, 0x3e1b1482, 0x4f80cbdc, 0x3e180a6f,
+ 0x4f8cfcbe, 0x3e14fdf7, 0x4f992d06, 0x3e11ef1b,
+ 0x4fa55cb4, 0x3e0eddd9, 0x4fb18bc8, 0x3e0bca34,
+ 0x4fbdba40, 0x3e08b42a, 0x4fc9e81e, 0x3e059bbb,
+ 0x4fd6155f, 0x3e0280e9, 0x4fe24205, 0x3dff63b2,
+ 0x4fee6e0d, 0x3dfc4418, 0x4ffa9979, 0x3df9221a,
+ 0x5006c446, 0x3df5fdb8, 0x5012ee76, 0x3df2d6f3,
+ 0x501f1807, 0x3defadca, 0x502b40f8, 0x3dec823e,
+ 0x5037694b, 0x3de9544f, 0x504390fd, 0x3de623fd,
+ 0x504fb80e, 0x3de2f148, 0x505bde7f, 0x3ddfbc30,
+ 0x5068044e, 0x3ddc84b5, 0x5074297b, 0x3dd94ad8,
+ 0x50804e06, 0x3dd60e99, 0x508c71ee, 0x3dd2cff7,
+ 0x50989532, 0x3dcf8ef3, 0x50a4b7d3, 0x3dcc4b8d,
+ 0x50b0d9d0, 0x3dc905c5, 0x50bcfb28, 0x3dc5bd9b,
+ 0x50c91bda, 0x3dc2730f, 0x50d53be7, 0x3dbf2622,
+ 0x50e15b4e, 0x3dbbd6d4, 0x50ed7a0e, 0x3db88524,
+ 0x50f99827, 0x3db53113, 0x5105b599, 0x3db1daa2,
+ 0x5111d263, 0x3dae81cf, 0x511dee84, 0x3dab269b,
+ 0x512a09fc, 0x3da7c907, 0x513624cb, 0x3da46912,
+ 0x51423ef0, 0x3da106bd, 0x514e586a, 0x3d9da208,
+ 0x515a713a, 0x3d9a3af2, 0x5166895f, 0x3d96d17d,
+ 0x5172a0d7, 0x3d9365a8, 0x517eb7a4, 0x3d8ff772,
+ 0x518acdc4, 0x3d8c86de, 0x5196e337, 0x3d8913ea,
+ 0x51a2f7fc, 0x3d859e96, 0x51af0c13, 0x3d8226e4,
+ 0x51bb1f7c, 0x3d7eacd2, 0x51c73235, 0x3d7b3061,
+ 0x51d3443f, 0x3d77b192, 0x51df5599, 0x3d743064,
+ 0x51eb6643, 0x3d70acd7, 0x51f7763c, 0x3d6d26ec,
+ 0x52038584, 0x3d699ea3, 0x520f941a, 0x3d6613fb,
+ 0x521ba1fd, 0x3d6286f6, 0x5227af2e, 0x3d5ef793,
+ 0x5233bbac, 0x3d5b65d2, 0x523fc776, 0x3d57d1b3,
+ 0x524bd28c, 0x3d543b37, 0x5257dced, 0x3d50a25e,
+ 0x5263e699, 0x3d4d0728, 0x526fef90, 0x3d496994,
+ 0x527bf7d1, 0x3d45c9a4, 0x5287ff5b, 0x3d422757,
+ 0x5294062f, 0x3d3e82ae, 0x52a00c4b, 0x3d3adba7,
+ 0x52ac11af, 0x3d373245, 0x52b8165b, 0x3d338687,
+ 0x52c41a4f, 0x3d2fd86c, 0x52d01d89, 0x3d2c27f6,
+ 0x52dc2009, 0x3d287523, 0x52e821cf, 0x3d24bff6,
+ 0x52f422db, 0x3d21086c, 0x5300232c, 0x3d1d4e88,
+ 0x530c22c1, 0x3d199248, 0x5318219a, 0x3d15d3ad,
+ 0x53241fb6, 0x3d1212b7, 0x53301d16, 0x3d0e4f67,
+ 0x533c19b8, 0x3d0a89bc, 0x5348159d, 0x3d06c1b6,
+ 0x535410c3, 0x3d02f757, 0x53600b2a, 0x3cff2a9d,
+ 0x536c04d2, 0x3cfb5b89, 0x5377fdbb, 0x3cf78a1b,
+ 0x5383f5e3, 0x3cf3b653, 0x538fed4b, 0x3cefe032,
+ 0x539be3f2, 0x3cec07b8, 0x53a7d9d7, 0x3ce82ce4,
+ 0x53b3cefa, 0x3ce44fb7, 0x53bfc35b, 0x3ce07031,
+ 0x53cbb6f8, 0x3cdc8e52, 0x53d7a9d3, 0x3cd8aa1b,
+ 0x53e39be9, 0x3cd4c38b, 0x53ef8d3c, 0x3cd0daa2,
+ 0x53fb7dc9, 0x3cccef62, 0x54076d91, 0x3cc901c9,
+ 0x54135c94, 0x3cc511d9, 0x541f4ad1, 0x3cc11f90,
+ 0x542b3846, 0x3cbd2af0, 0x543724f5, 0x3cb933f9,
+ 0x544310dd, 0x3cb53aaa, 0x544efbfc, 0x3cb13f04,
+ 0x545ae653, 0x3cad4107, 0x5466cfe1, 0x3ca940b3,
+ 0x5472b8a5, 0x3ca53e09, 0x547ea0a0, 0x3ca13908,
+ 0x548a87d1, 0x3c9d31b0, 0x54966e36, 0x3c992803,
+ 0x54a253d1, 0x3c951bff, 0x54ae38a0, 0x3c910da5,
+ 0x54ba1ca3, 0x3c8cfcf6, 0x54c5ffd9, 0x3c88e9f1,
+ 0x54d1e242, 0x3c84d496, 0x54ddc3de, 0x3c80bce7,
+ 0x54e9a4ac, 0x3c7ca2e2, 0x54f584ac, 0x3c788688,
+ 0x550163dc, 0x3c7467d9, 0x550d423d, 0x3c7046d6,
+ 0x55191fcf, 0x3c6c237e, 0x5524fc90, 0x3c67fdd1,
+ 0x5530d881, 0x3c63d5d1, 0x553cb3a0, 0x3c5fab7c,
+ 0x55488dee, 0x3c5b7ed4, 0x5554676a, 0x3c574fd8,
+ 0x55604013, 0x3c531e88, 0x556c17e9, 0x3c4eeae5,
+ 0x5577eeec, 0x3c4ab4ef, 0x5583c51b, 0x3c467ca6,
+ 0x558f9a76, 0x3c42420a, 0x559b6efb, 0x3c3e051b,
+ 0x55a742ac, 0x3c39c5da, 0x55b31587, 0x3c358446,
+ 0x55bee78c, 0x3c314060, 0x55cab8ba, 0x3c2cfa28,
+ 0x55d68911, 0x3c28b19e, 0x55e25890, 0x3c2466c2,
+ 0x55ee2738, 0x3c201994, 0x55f9f507, 0x3c1bca16,
+ 0x5605c1fd, 0x3c177845, 0x56118e1a, 0x3c132424,
+ 0x561d595d, 0x3c0ecdb2, 0x562923c5, 0x3c0a74f0,
+ 0x5634ed53, 0x3c0619dc, 0x5640b606, 0x3c01bc78,
+ 0x564c7ddd, 0x3bfd5cc4, 0x565844d8, 0x3bf8fac0,
+ 0x56640af7, 0x3bf4966c, 0x566fd039, 0x3bf02fc9,
+ 0x567b949d, 0x3bebc6d5, 0x56875823, 0x3be75b93,
+ 0x56931acb, 0x3be2ee01, 0x569edc94, 0x3bde7e20,
+ 0x56aa9d7e, 0x3bda0bf0, 0x56b65d88, 0x3bd59771,
+ 0x56c21cb2, 0x3bd120a4, 0x56cddafb, 0x3bcca789,
+ 0x56d99864, 0x3bc82c1f, 0x56e554ea, 0x3bc3ae67,
+ 0x56f1108f, 0x3bbf2e62, 0x56fccb51, 0x3bbaac0e,
+ 0x57088531, 0x3bb6276e, 0x57143e2d, 0x3bb1a080,
+ 0x571ff646, 0x3bad1744, 0x572bad7a, 0x3ba88bbc,
+ 0x573763c9, 0x3ba3fde7, 0x57431933, 0x3b9f6dc5,
+ 0x574ecdb8, 0x3b9adb57, 0x575a8157, 0x3b96469d,
+ 0x5766340f, 0x3b91af97, 0x5771e5e0, 0x3b8d1644,
+ 0x577d96ca, 0x3b887aa6, 0x578946cc, 0x3b83dcbc,
+ 0x5794f5e6, 0x3b7f3c87, 0x57a0a417, 0x3b7a9a07,
+ 0x57ac515f, 0x3b75f53c, 0x57b7fdbd, 0x3b714e25,
+ 0x57c3a931, 0x3b6ca4c4, 0x57cf53bb, 0x3b67f919,
+ 0x57dafd59, 0x3b634b23, 0x57e6a60c, 0x3b5e9ae4,
+ 0x57f24dd3, 0x3b59e85a, 0x57fdf4ae, 0x3b553386,
+ 0x58099a9c, 0x3b507c69, 0x58153f9d, 0x3b4bc303,
+ 0x5820e3b0, 0x3b470753, 0x582c86d5, 0x3b42495a,
+ 0x5838290c, 0x3b3d8918, 0x5843ca53, 0x3b38c68e,
+ 0x584f6aab, 0x3b3401bb, 0x585b0a13, 0x3b2f3aa0,
+ 0x5866a88a, 0x3b2a713d, 0x58724611, 0x3b25a591,
+ 0x587de2a7, 0x3b20d79e, 0x58897e4a, 0x3b1c0764,
+ 0x589518fc, 0x3b1734e2, 0x58a0b2bb, 0x3b126019,
+ 0x58ac4b87, 0x3b0d8909, 0x58b7e35f, 0x3b08afb2,
+ 0x58c37a44, 0x3b03d414, 0x58cf1034, 0x3afef630,
+ 0x58daa52f, 0x3afa1605, 0x58e63935, 0x3af53395,
+ 0x58f1cc45, 0x3af04edf, 0x58fd5e5f, 0x3aeb67e3,
+ 0x5908ef82, 0x3ae67ea1, 0x59147fae, 0x3ae1931a,
+ 0x59200ee3, 0x3adca54e, 0x592b9d1f, 0x3ad7b53d,
+ 0x59372a64, 0x3ad2c2e8, 0x5942b6af, 0x3acdce4d,
+ 0x594e4201, 0x3ac8d76f, 0x5959cc5a, 0x3ac3de4c,
+ 0x596555b8, 0x3abee2e5, 0x5970de1b, 0x3ab9e53a,
+ 0x597c6584, 0x3ab4e54c, 0x5987ebf0, 0x3aafe31b,
+ 0x59937161, 0x3aaadea6, 0x599ef5d6, 0x3aa5d7ee,
+ 0x59aa794d, 0x3aa0cef3, 0x59b5fbc8, 0x3a9bc3b6,
+ 0x59c17d44, 0x3a96b636, 0x59ccfdc2, 0x3a91a674,
+ 0x59d87d42, 0x3a8c9470, 0x59e3fbc3, 0x3a87802a,
+ 0x59ef7944, 0x3a8269a3, 0x59faf5c5, 0x3a7d50da,
+ 0x5a067145, 0x3a7835cf, 0x5a11ebc5, 0x3a731884,
+ 0x5a1d6544, 0x3a6df8f8, 0x5a28ddc0, 0x3a68d72b,
+ 0x5a34553b, 0x3a63b31d, 0x5a3fcbb3, 0x3a5e8cd0,
+ 0x5a4b4128, 0x3a596442, 0x5a56b599, 0x3a543974,
+ 0x5a622907, 0x3a4f0c67, 0x5a6d9b70, 0x3a49dd1a,
+ 0x5a790cd4, 0x3a44ab8e, 0x5a847d33, 0x3a3f77c3,
+ 0x5a8fec8c, 0x3a3a41b9, 0x5a9b5adf, 0x3a350970,
+ 0x5aa6c82b, 0x3a2fcee8, 0x5ab23471, 0x3a2a9223,
+ 0x5abd9faf, 0x3a25531f, 0x5ac909e5, 0x3a2011de,
+ 0x5ad47312, 0x3a1ace5f, 0x5adfdb37, 0x3a1588a2,
+ 0x5aeb4253, 0x3a1040a8, 0x5af6a865, 0x3a0af671,
+ 0x5b020d6c, 0x3a05a9fd, 0x5b0d716a, 0x3a005b4d,
+ 0x5b18d45c, 0x39fb0a60, 0x5b243643, 0x39f5b737,
+ 0x5b2f971e, 0x39f061d2, 0x5b3af6ec, 0x39eb0a31,
+ 0x5b4655ae, 0x39e5b054, 0x5b51b363, 0x39e0543c,
+ 0x5b5d100a, 0x39daf5e8, 0x5b686ba3, 0x39d5955a,
+ 0x5b73c62d, 0x39d03291, 0x5b7f1fa9, 0x39cacd8d,
+ 0x5b8a7815, 0x39c5664f, 0x5b95cf71, 0x39bffcd7,
+ 0x5ba125bd, 0x39ba9125, 0x5bac7af9, 0x39b52339,
+ 0x5bb7cf23, 0x39afb313, 0x5bc3223c, 0x39aa40b4,
+ 0x5bce7442, 0x39a4cc1c, 0x5bd9c537, 0x399f554b,
+ 0x5be51518, 0x3999dc42, 0x5bf063e6, 0x399460ff,
+ 0x5bfbb1a0, 0x398ee385, 0x5c06fe46, 0x398963d2,
+ 0x5c1249d8, 0x3983e1e8, 0x5c1d9454, 0x397e5dc6,
+ 0x5c28ddbb, 0x3978d76c, 0x5c34260c, 0x39734edc,
+ 0x5c3f6d47, 0x396dc414, 0x5c4ab36b, 0x39683715,
+ 0x5c55f878, 0x3962a7e0, 0x5c613c6d, 0x395d1675,
+ 0x5c6c7f4a, 0x395782d3, 0x5c77c10e, 0x3951ecfc,
+ 0x5c8301b9, 0x394c54ee, 0x5c8e414b, 0x3946baac,
+ 0x5c997fc4, 0x39411e33, 0x5ca4bd21, 0x393b7f86,
+ 0x5caff965, 0x3935dea4, 0x5cbb348d, 0x39303b8e,
+ 0x5cc66e99, 0x392a9642, 0x5cd1a78a, 0x3924eec3,
+ 0x5cdcdf5e, 0x391f4510, 0x5ce81615, 0x39199929,
+ 0x5cf34baf, 0x3913eb0e, 0x5cfe802b, 0x390e3ac0,
+ 0x5d09b389, 0x3908883f, 0x5d14e5c9, 0x3902d38b,
+ 0x5d2016e9, 0x38fd1ca4, 0x5d2b46ea, 0x38f7638b,
+ 0x5d3675cb, 0x38f1a840, 0x5d41a38c, 0x38ebeac2,
+ 0x5d4cd02c, 0x38e62b13, 0x5d57fbaa, 0x38e06932,
+ 0x5d632608, 0x38daa520, 0x5d6e4f43, 0x38d4dedd,
+ 0x5d79775c, 0x38cf1669, 0x5d849e51, 0x38c94bc4,
+ 0x5d8fc424, 0x38c37eef, 0x5d9ae8d2, 0x38bdafea,
+ 0x5da60c5d, 0x38b7deb4, 0x5db12ec3, 0x38b20b4f,
+ 0x5dbc5004, 0x38ac35ba, 0x5dc7701f, 0x38a65df6,
+ 0x5dd28f15, 0x38a08402, 0x5dddace4, 0x389aa7e0,
+ 0x5de8c98c, 0x3894c98f, 0x5df3e50d, 0x388ee910,
+ 0x5dfeff67, 0x38890663, 0x5e0a1898, 0x38832187,
+ 0x5e1530a1, 0x387d3a7e, 0x5e204781, 0x38775147,
+ 0x5e2b5d38, 0x387165e3, 0x5e3671c5, 0x386b7852,
+ 0x5e418528, 0x38658894, 0x5e4c9760, 0x385f96a9,
+ 0x5e57a86d, 0x3859a292, 0x5e62b84f, 0x3853ac4f,
+ 0x5e6dc705, 0x384db3e0, 0x5e78d48e, 0x3847b946,
+ 0x5e83e0eb, 0x3841bc7f, 0x5e8eec1b, 0x383bbd8e,
+ 0x5e99f61d, 0x3835bc71, 0x5ea4fef0, 0x382fb92a,
+ 0x5eb00696, 0x3829b3b9, 0x5ebb0d0d, 0x3823ac1d,
+ 0x5ec61254, 0x381da256, 0x5ed1166b, 0x38179666,
+ 0x5edc1953, 0x3811884d, 0x5ee71b0a, 0x380b780a,
+ 0x5ef21b90, 0x3805659e, 0x5efd1ae4, 0x37ff5109,
+ 0x5f081907, 0x37f93a4b, 0x5f1315f7, 0x37f32165,
+ 0x5f1e11b5, 0x37ed0657, 0x5f290c3f, 0x37e6e921,
+ 0x5f340596, 0x37e0c9c3, 0x5f3efdb9, 0x37daa83d,
+ 0x5f49f4a8, 0x37d48490, 0x5f54ea62, 0x37ce5ebd,
+ 0x5f5fdee6, 0x37c836c2, 0x5f6ad235, 0x37c20ca1,
+ 0x5f75c44e, 0x37bbe05a, 0x5f80b531, 0x37b5b1ec,
+ 0x5f8ba4dc, 0x37af8159, 0x5f969350, 0x37a94ea0,
+ 0x5fa1808c, 0x37a319c2, 0x5fac6c91, 0x379ce2be,
+ 0x5fb7575c, 0x3796a996, 0x5fc240ef, 0x37906e49,
+ 0x5fcd2948, 0x378a30d8, 0x5fd81067, 0x3783f143,
+ 0x5fe2f64c, 0x377daf89, 0x5feddaf6, 0x37776bac,
+ 0x5ff8be65, 0x377125ac, 0x6003a099, 0x376add88,
+ 0x600e8190, 0x37649341, 0x6019614c, 0x375e46d8,
+ 0x60243fca, 0x3757f84c, 0x602f1d0b, 0x3751a79e,
+ 0x6039f90f, 0x374b54ce, 0x6044d3d4, 0x3744ffdd,
+ 0x604fad5b, 0x373ea8ca, 0x605a85a3, 0x37384f95,
+ 0x60655cac, 0x3731f440, 0x60703275, 0x372b96ca,
+ 0x607b06fe, 0x37253733, 0x6085da46, 0x371ed57c,
+ 0x6090ac4d, 0x371871a5, 0x609b7d13, 0x37120bae,
+ 0x60a64c97, 0x370ba398, 0x60b11ad9, 0x37053962,
+ 0x60bbe7d8, 0x36fecd0e, 0x60c6b395, 0x36f85e9a,
+ 0x60d17e0d, 0x36f1ee09, 0x60dc4742, 0x36eb7b58,
+ 0x60e70f32, 0x36e5068a, 0x60f1d5de, 0x36de8f9e,
+ 0x60fc9b44, 0x36d81695, 0x61075f65, 0x36d19b6e,
+ 0x61122240, 0x36cb1e2a, 0x611ce3d5, 0x36c49ec9,
+ 0x6127a423, 0x36be1d4c, 0x61326329, 0x36b799b3,
+ 0x613d20e8, 0x36b113fd, 0x6147dd5f, 0x36aa8c2c,
+ 0x6152988d, 0x36a4023f, 0x615d5273, 0x369d7637,
+ 0x61680b0f, 0x3696e814, 0x6172c262, 0x369057d6,
+ 0x617d786a, 0x3689c57d, 0x61882d28, 0x3683310b,
+ 0x6192e09b, 0x367c9a7e, 0x619d92c2, 0x367601d7,
+ 0x61a8439e, 0x366f6717, 0x61b2f32e, 0x3668ca3e,
+ 0x61bda171, 0x36622b4c, 0x61c84e67, 0x365b8a41,
+ 0x61d2fa0f, 0x3654e71d, 0x61dda46a, 0x364e41e2,
+ 0x61e84d76, 0x36479a8e, 0x61f2f534, 0x3640f123,
+ 0x61fd9ba3, 0x363a45a0, 0x620840c2, 0x36339806,
+ 0x6212e492, 0x362ce855, 0x621d8711, 0x3626368d,
+ 0x6228283f, 0x361f82af, 0x6232c81c, 0x3618ccba,
+ 0x623d66a8, 0x361214b0, 0x624803e2, 0x360b5a90,
+ 0x62529fca, 0x36049e5b, 0x625d3a5e, 0x35fde011,
+ 0x6267d3a0, 0x35f71fb1, 0x62726b8e, 0x35f05d3d,
+ 0x627d0228, 0x35e998b5, 0x6287976e, 0x35e2d219,
+ 0x62922b5e, 0x35dc0968, 0x629cbdfa, 0x35d53ea5,
+ 0x62a74f40, 0x35ce71ce, 0x62b1df30, 0x35c7a2e3,
+ 0x62bc6dca, 0x35c0d1e7, 0x62c6fb0c, 0x35b9fed7,
+ 0x62d186f8, 0x35b329b5, 0x62dc118c, 0x35ac5282,
+ 0x62e69ac8, 0x35a5793c, 0x62f122ab, 0x359e9de5,
+ 0x62fba936, 0x3597c07d, 0x63062e67, 0x3590e104,
+ 0x6310b23e, 0x3589ff7a, 0x631b34bc, 0x35831be0,
+ 0x6325b5df, 0x357c3636, 0x633035a7, 0x35754e7c,
+ 0x633ab414, 0x356e64b2, 0x63453125, 0x356778d9,
+ 0x634facda, 0x35608af1, 0x635a2733, 0x35599afa,
+ 0x6364a02e, 0x3552a8f4, 0x636f17cc, 0x354bb4e1,
+ 0x63798e0d, 0x3544bebf, 0x638402ef, 0x353dc68f,
+ 0x638e7673, 0x3536cc52, 0x6398e898, 0x352fd008,
+ 0x63a3595e, 0x3528d1b1, 0x63adc8c4, 0x3521d14d,
+ 0x63b836ca, 0x351acedd, 0x63c2a36f, 0x3513ca60,
+ 0x63cd0eb3, 0x350cc3d8, 0x63d77896, 0x3505bb44,
+ 0x63e1e117, 0x34feb0a5, 0x63ec4837, 0x34f7a3fb,
+ 0x63f6adf3, 0x34f09546, 0x6401124d, 0x34e98487,
+ 0x640b7543, 0x34e271bd, 0x6415d6d5, 0x34db5cea,
+ 0x64203704, 0x34d4460c, 0x642a95ce, 0x34cd2d26,
+ 0x6434f332, 0x34c61236, 0x643f4f32, 0x34bef53d,
+ 0x6449a9cc, 0x34b7d63c, 0x645402ff, 0x34b0b533,
+ 0x645e5acc, 0x34a99221, 0x6468b132, 0x34a26d08,
+ 0x64730631, 0x349b45e7, 0x647d59c8, 0x34941cbf,
+ 0x6487abf7, 0x348cf190, 0x6491fcbe, 0x3485c45b,
+ 0x649c4c1b, 0x347e951f, 0x64a69a0f, 0x347763dd,
+ 0x64b0e699, 0x34703095, 0x64bb31ba, 0x3468fb47,
+ 0x64c57b6f, 0x3461c3f5, 0x64cfc3ba, 0x345a8a9d,
+ 0x64da0a9a, 0x34534f41, 0x64e4500e, 0x344c11e0,
+ 0x64ee9415, 0x3444d27b, 0x64f8d6b0, 0x343d9112,
+ 0x650317df, 0x34364da6, 0x650d57a0, 0x342f0836,
+ 0x651795f3, 0x3427c0c3, 0x6521d2d8, 0x3420774d,
+ 0x652c0e4f, 0x34192bd5, 0x65364857, 0x3411de5b,
+ 0x654080ef, 0x340a8edf, 0x654ab818, 0x34033d61,
+ 0x6554edd1, 0x33fbe9e2, 0x655f2219, 0x33f49462,
+ 0x656954f1, 0x33ed3ce1, 0x65738657, 0x33e5e360,
+ 0x657db64c, 0x33de87de, 0x6587e4cf, 0x33d72a5d,
+ 0x659211df, 0x33cfcadc, 0x659c3d7c, 0x33c8695b,
+ 0x65a667a7, 0x33c105db, 0x65b0905d, 0x33b9a05d,
+ 0x65bab7a0, 0x33b238e0, 0x65c4dd6e, 0x33aacf65,
+ 0x65cf01c8, 0x33a363ec, 0x65d924ac, 0x339bf675,
+ 0x65e3461b, 0x33948701, 0x65ed6614, 0x338d1590,
+ 0x65f78497, 0x3385a222, 0x6601a1a2, 0x337e2cb7,
+ 0x660bbd37, 0x3376b551, 0x6615d754, 0x336f3bee,
+ 0x661feffa, 0x3367c090, 0x662a0727, 0x33604336,
+ 0x66341cdb, 0x3358c3e2, 0x663e3117, 0x33514292,
+ 0x664843d9, 0x3349bf48, 0x66525521, 0x33423a04,
+ 0x665c64ef, 0x333ab2c6, 0x66667342, 0x3333298f,
+ 0x6670801a, 0x332b9e5e, 0x667a8b77, 0x33241134,
+ 0x66849558, 0x331c8211, 0x668e9dbd, 0x3314f0f6,
+ 0x6698a4a6, 0x330d5de3, 0x66a2aa11, 0x3305c8d7,
+ 0x66acadff, 0x32fe31d5, 0x66b6b070, 0x32f698db,
+ 0x66c0b162, 0x32eefdea, 0x66cab0d6, 0x32e76102,
+ 0x66d4aecb, 0x32dfc224, 0x66deab41, 0x32d82150,
+ 0x66e8a637, 0x32d07e85, 0x66f29fad, 0x32c8d9c6,
+ 0x66fc97a3, 0x32c13311, 0x67068e18, 0x32b98a67,
+ 0x6710830c, 0x32b1dfc9, 0x671a767e, 0x32aa3336,
+ 0x6724686e, 0x32a284b0, 0x672e58dc, 0x329ad435,
+ 0x673847c8, 0x329321c7, 0x67423530, 0x328b6d66,
+ 0x674c2115, 0x3283b712, 0x67560b76, 0x327bfecc,
+ 0x675ff452, 0x32744493, 0x6769dbaa, 0x326c8868,
+ 0x6773c17d, 0x3264ca4c, 0x677da5cb, 0x325d0a3e,
+ 0x67878893, 0x32554840, 0x679169d5, 0x324d8450,
+ 0x679b4990, 0x3245be70, 0x67a527c4, 0x323df6a0,
+ 0x67af0472, 0x32362ce0, 0x67b8df97, 0x322e6130,
+ 0x67c2b934, 0x32269391, 0x67cc9149, 0x321ec403,
+ 0x67d667d5, 0x3216f287, 0x67e03cd8, 0x320f1f1c,
+ 0x67ea1052, 0x320749c3, 0x67f3e241, 0x31ff727c,
+ 0x67fdb2a7, 0x31f79948, 0x68078181, 0x31efbe27,
+ 0x68114ed0, 0x31e7e118, 0x681b1a94, 0x31e0021e,
+ 0x6824e4cc, 0x31d82137, 0x682ead78, 0x31d03e64,
+ 0x68387498, 0x31c859a5, 0x68423a2a, 0x31c072fb,
+ 0x684bfe2f, 0x31b88a66, 0x6855c0a6, 0x31b09fe7,
+ 0x685f8190, 0x31a8b37c, 0x686940ea, 0x31a0c528,
+ 0x6872feb6, 0x3198d4ea, 0x687cbaf3, 0x3190e2c3,
+ 0x688675a0, 0x3188eeb2, 0x68902ebd, 0x3180f8b8,
+ 0x6899e64a, 0x317900d6, 0x68a39c46, 0x3171070c,
+ 0x68ad50b1, 0x31690b59, 0x68b7038b, 0x31610dbf,
+ 0x68c0b4d2, 0x31590e3e, 0x68ca6488, 0x31510cd5,
+ 0x68d412ab, 0x31490986, 0x68ddbf3b, 0x31410450,
+ 0x68e76a37, 0x3138fd35, 0x68f113a0, 0x3130f433,
+ 0x68fabb75, 0x3128e94c, 0x690461b5, 0x3120dc80,
+ 0x690e0661, 0x3118cdcf, 0x6917a977, 0x3110bd39,
+ 0x69214af8, 0x3108aabf, 0x692aeae3, 0x31009661,
+ 0x69348937, 0x30f8801f, 0x693e25f5, 0x30f067fb,
+ 0x6947c11c, 0x30e84df3, 0x69515aab, 0x30e03208,
+ 0x695af2a3, 0x30d8143b, 0x69648902, 0x30cff48c,
+ 0x696e1dc9, 0x30c7d2fb, 0x6977b0f7, 0x30bfaf89,
+ 0x6981428c, 0x30b78a36, 0x698ad287, 0x30af6302,
+ 0x699460e8, 0x30a739ed, 0x699dedaf, 0x309f0ef8,
+ 0x69a778db, 0x3096e223, 0x69b1026c, 0x308eb36f,
+ 0x69ba8a61, 0x308682dc, 0x69c410ba, 0x307e5069,
+ 0x69cd9578, 0x30761c18, 0x69d71899, 0x306de5e9,
+ 0x69e09a1c, 0x3065addb, 0x69ea1a03, 0x305d73f0,
+ 0x69f3984c, 0x30553828, 0x69fd14f6, 0x304cfa83,
+ 0x6a069003, 0x3044bb00, 0x6a100970, 0x303c79a2,
+ 0x6a19813f, 0x30343667, 0x6a22f76e, 0x302bf151,
+ 0x6a2c6bfd, 0x3023aa5f, 0x6a35deeb, 0x301b6193,
+ 0x6a3f503a, 0x301316eb, 0x6a48bfe7, 0x300aca69,
+ 0x6a522df3, 0x30027c0c, 0x6a5b9a5d, 0x2ffa2bd6,
+ 0x6a650525, 0x2ff1d9c7, 0x6a6e6e4b, 0x2fe985de,
+ 0x6a77d5ce, 0x2fe1301c, 0x6a813bae, 0x2fd8d882,
+ 0x6a8a9fea, 0x2fd07f0f, 0x6a940283, 0x2fc823c5,
+ 0x6a9d6377, 0x2fbfc6a3, 0x6aa6c2c6, 0x2fb767aa,
+ 0x6ab02071, 0x2faf06da, 0x6ab97c77, 0x2fa6a433,
+ 0x6ac2d6d6, 0x2f9e3fb6, 0x6acc2f90, 0x2f95d963,
+ 0x6ad586a3, 0x2f8d713a, 0x6adedc10, 0x2f85073c,
+ 0x6ae82fd5, 0x2f7c9b69, 0x6af181f3, 0x2f742dc1,
+ 0x6afad269, 0x2f6bbe45, 0x6b042137, 0x2f634cf5,
+ 0x6b0d6e5c, 0x2f5ad9d1, 0x6b16b9d9, 0x2f5264da,
+ 0x6b2003ac, 0x2f49ee0f, 0x6b294bd5, 0x2f417573,
+ 0x6b329255, 0x2f38fb03, 0x6b3bd72a, 0x2f307ec2,
+ 0x6b451a55, 0x2f2800af, 0x6b4e5bd4, 0x2f1f80ca,
+ 0x6b579ba8, 0x2f16ff14, 0x6b60d9d0, 0x2f0e7b8e,
+ 0x6b6a164d, 0x2f05f637, 0x6b73511c, 0x2efd6f10,
+ 0x6b7c8a3f, 0x2ef4e619, 0x6b85c1b5, 0x2eec5b53,
+ 0x6b8ef77d, 0x2ee3cebe, 0x6b982b97, 0x2edb405a,
+ 0x6ba15e03, 0x2ed2b027, 0x6baa8ec0, 0x2eca1e27,
+ 0x6bb3bdce, 0x2ec18a58, 0x6bbceb2d, 0x2eb8f4bc,
+ 0x6bc616dd, 0x2eb05d53, 0x6bcf40dc, 0x2ea7c41e,
+ 0x6bd8692b, 0x2e9f291b, 0x6be18fc9, 0x2e968c4d,
+ 0x6beab4b6, 0x2e8dedb3, 0x6bf3d7f2, 0x2e854d4d,
+ 0x6bfcf97c, 0x2e7cab1c, 0x6c061953, 0x2e740720,
+ 0x6c0f3779, 0x2e6b615a, 0x6c1853eb, 0x2e62b9ca,
+ 0x6c216eaa, 0x2e5a1070, 0x6c2a87b6, 0x2e51654c,
+ 0x6c339f0e, 0x2e48b860, 0x6c3cb4b1, 0x2e4009aa,
+ 0x6c45c8a0, 0x2e37592c, 0x6c4edada, 0x2e2ea6e6,
+ 0x6c57eb5e, 0x2e25f2d8, 0x6c60fa2d, 0x2e1d3d03,
+ 0x6c6a0746, 0x2e148566, 0x6c7312a9, 0x2e0bcc03,
+ 0x6c7c1c55, 0x2e0310d9, 0x6c85244a, 0x2dfa53e9,
+ 0x6c8e2a87, 0x2df19534, 0x6c972f0d, 0x2de8d4b8,
+ 0x6ca031da, 0x2de01278, 0x6ca932ef, 0x2dd74e73,
+ 0x6cb2324c, 0x2dce88aa, 0x6cbb2fef, 0x2dc5c11c,
+ 0x6cc42bd9, 0x2dbcf7cb, 0x6ccd2609, 0x2db42cb6,
+ 0x6cd61e7f, 0x2dab5fdf, 0x6cdf153a, 0x2da29144,
+ 0x6ce80a3a, 0x2d99c0e7, 0x6cf0fd80, 0x2d90eec8,
+ 0x6cf9ef09, 0x2d881ae8, 0x6d02ded7, 0x2d7f4545,
+ 0x6d0bcce8, 0x2d766de2, 0x6d14b93d, 0x2d6d94bf,
+ 0x6d1da3d5, 0x2d64b9da, 0x6d268cb0, 0x2d5bdd36,
+ 0x6d2f73cd, 0x2d52fed2, 0x6d38592c, 0x2d4a1eaf,
+ 0x6d413ccd, 0x2d413ccd, 0x6d4a1eaf, 0x2d38592c,
+ 0x6d52fed2, 0x2d2f73cd, 0x6d5bdd36, 0x2d268cb0,
+ 0x6d64b9da, 0x2d1da3d5, 0x6d6d94bf, 0x2d14b93d,
+ 0x6d766de2, 0x2d0bcce8, 0x6d7f4545, 0x2d02ded7,
+ 0x6d881ae8, 0x2cf9ef09, 0x6d90eec8, 0x2cf0fd80,
+ 0x6d99c0e7, 0x2ce80a3a, 0x6da29144, 0x2cdf153a,
+ 0x6dab5fdf, 0x2cd61e7f, 0x6db42cb6, 0x2ccd2609,
+ 0x6dbcf7cb, 0x2cc42bd9, 0x6dc5c11c, 0x2cbb2fef,
+ 0x6dce88aa, 0x2cb2324c, 0x6dd74e73, 0x2ca932ef,
+ 0x6de01278, 0x2ca031da, 0x6de8d4b8, 0x2c972f0d,
+ 0x6df19534, 0x2c8e2a87, 0x6dfa53e9, 0x2c85244a,
+ 0x6e0310d9, 0x2c7c1c55, 0x6e0bcc03, 0x2c7312a9,
+ 0x6e148566, 0x2c6a0746, 0x6e1d3d03, 0x2c60fa2d,
+ 0x6e25f2d8, 0x2c57eb5e, 0x6e2ea6e6, 0x2c4edada,
+ 0x6e37592c, 0x2c45c8a0, 0x6e4009aa, 0x2c3cb4b1,
+ 0x6e48b860, 0x2c339f0e, 0x6e51654c, 0x2c2a87b6,
+ 0x6e5a1070, 0x2c216eaa, 0x6e62b9ca, 0x2c1853eb,
+ 0x6e6b615a, 0x2c0f3779, 0x6e740720, 0x2c061953,
+ 0x6e7cab1c, 0x2bfcf97c, 0x6e854d4d, 0x2bf3d7f2,
+ 0x6e8dedb3, 0x2beab4b6, 0x6e968c4d, 0x2be18fc9,
+ 0x6e9f291b, 0x2bd8692b, 0x6ea7c41e, 0x2bcf40dc,
+ 0x6eb05d53, 0x2bc616dd, 0x6eb8f4bc, 0x2bbceb2d,
+ 0x6ec18a58, 0x2bb3bdce, 0x6eca1e27, 0x2baa8ec0,
+ 0x6ed2b027, 0x2ba15e03, 0x6edb405a, 0x2b982b97,
+ 0x6ee3cebe, 0x2b8ef77d, 0x6eec5b53, 0x2b85c1b5,
+ 0x6ef4e619, 0x2b7c8a3f, 0x6efd6f10, 0x2b73511c,
+ 0x6f05f637, 0x2b6a164d, 0x6f0e7b8e, 0x2b60d9d0,
+ 0x6f16ff14, 0x2b579ba8, 0x6f1f80ca, 0x2b4e5bd4,
+ 0x6f2800af, 0x2b451a55, 0x6f307ec2, 0x2b3bd72a,
+ 0x6f38fb03, 0x2b329255, 0x6f417573, 0x2b294bd5,
+ 0x6f49ee0f, 0x2b2003ac, 0x6f5264da, 0x2b16b9d9,
+ 0x6f5ad9d1, 0x2b0d6e5c, 0x6f634cf5, 0x2b042137,
+ 0x6f6bbe45, 0x2afad269, 0x6f742dc1, 0x2af181f3,
+ 0x6f7c9b69, 0x2ae82fd5, 0x6f85073c, 0x2adedc10,
+ 0x6f8d713a, 0x2ad586a3, 0x6f95d963, 0x2acc2f90,
+ 0x6f9e3fb6, 0x2ac2d6d6, 0x6fa6a433, 0x2ab97c77,
+ 0x6faf06da, 0x2ab02071, 0x6fb767aa, 0x2aa6c2c6,
+ 0x6fbfc6a3, 0x2a9d6377, 0x6fc823c5, 0x2a940283,
+ 0x6fd07f0f, 0x2a8a9fea, 0x6fd8d882, 0x2a813bae,
+ 0x6fe1301c, 0x2a77d5ce, 0x6fe985de, 0x2a6e6e4b,
+ 0x6ff1d9c7, 0x2a650525, 0x6ffa2bd6, 0x2a5b9a5d,
+ 0x70027c0c, 0x2a522df3, 0x700aca69, 0x2a48bfe7,
+ 0x701316eb, 0x2a3f503a, 0x701b6193, 0x2a35deeb,
+ 0x7023aa5f, 0x2a2c6bfd, 0x702bf151, 0x2a22f76e,
+ 0x70343667, 0x2a19813f, 0x703c79a2, 0x2a100970,
+ 0x7044bb00, 0x2a069003, 0x704cfa83, 0x29fd14f6,
+ 0x70553828, 0x29f3984c, 0x705d73f0, 0x29ea1a03,
+ 0x7065addb, 0x29e09a1c, 0x706de5e9, 0x29d71899,
+ 0x70761c18, 0x29cd9578, 0x707e5069, 0x29c410ba,
+ 0x708682dc, 0x29ba8a61, 0x708eb36f, 0x29b1026c,
+ 0x7096e223, 0x29a778db, 0x709f0ef8, 0x299dedaf,
+ 0x70a739ed, 0x299460e8, 0x70af6302, 0x298ad287,
+ 0x70b78a36, 0x2981428c, 0x70bfaf89, 0x2977b0f7,
+ 0x70c7d2fb, 0x296e1dc9, 0x70cff48c, 0x29648902,
+ 0x70d8143b, 0x295af2a3, 0x70e03208, 0x29515aab,
+ 0x70e84df3, 0x2947c11c, 0x70f067fb, 0x293e25f5,
+ 0x70f8801f, 0x29348937, 0x71009661, 0x292aeae3,
+ 0x7108aabf, 0x29214af8, 0x7110bd39, 0x2917a977,
+ 0x7118cdcf, 0x290e0661, 0x7120dc80, 0x290461b5,
+ 0x7128e94c, 0x28fabb75, 0x7130f433, 0x28f113a0,
+ 0x7138fd35, 0x28e76a37, 0x71410450, 0x28ddbf3b,
+ 0x71490986, 0x28d412ab, 0x71510cd5, 0x28ca6488,
+ 0x71590e3e, 0x28c0b4d2, 0x71610dbf, 0x28b7038b,
+ 0x71690b59, 0x28ad50b1, 0x7171070c, 0x28a39c46,
+ 0x717900d6, 0x2899e64a, 0x7180f8b8, 0x28902ebd,
+ 0x7188eeb2, 0x288675a0, 0x7190e2c3, 0x287cbaf3,
+ 0x7198d4ea, 0x2872feb6, 0x71a0c528, 0x286940ea,
+ 0x71a8b37c, 0x285f8190, 0x71b09fe7, 0x2855c0a6,
+ 0x71b88a66, 0x284bfe2f, 0x71c072fb, 0x28423a2a,
+ 0x71c859a5, 0x28387498, 0x71d03e64, 0x282ead78,
+ 0x71d82137, 0x2824e4cc, 0x71e0021e, 0x281b1a94,
+ 0x71e7e118, 0x28114ed0, 0x71efbe27, 0x28078181,
+ 0x71f79948, 0x27fdb2a7, 0x71ff727c, 0x27f3e241,
+ 0x720749c3, 0x27ea1052, 0x720f1f1c, 0x27e03cd8,
+ 0x7216f287, 0x27d667d5, 0x721ec403, 0x27cc9149,
+ 0x72269391, 0x27c2b934, 0x722e6130, 0x27b8df97,
+ 0x72362ce0, 0x27af0472, 0x723df6a0, 0x27a527c4,
+ 0x7245be70, 0x279b4990, 0x724d8450, 0x279169d5,
+ 0x72554840, 0x27878893, 0x725d0a3e, 0x277da5cb,
+ 0x7264ca4c, 0x2773c17d, 0x726c8868, 0x2769dbaa,
+ 0x72744493, 0x275ff452, 0x727bfecc, 0x27560b76,
+ 0x7283b712, 0x274c2115, 0x728b6d66, 0x27423530,
+ 0x729321c7, 0x273847c8, 0x729ad435, 0x272e58dc,
+ 0x72a284b0, 0x2724686e, 0x72aa3336, 0x271a767e,
+ 0x72b1dfc9, 0x2710830c, 0x72b98a67, 0x27068e18,
+ 0x72c13311, 0x26fc97a3, 0x72c8d9c6, 0x26f29fad,
+ 0x72d07e85, 0x26e8a637, 0x72d82150, 0x26deab41,
+ 0x72dfc224, 0x26d4aecb, 0x72e76102, 0x26cab0d6,
+ 0x72eefdea, 0x26c0b162, 0x72f698db, 0x26b6b070,
+ 0x72fe31d5, 0x26acadff, 0x7305c8d7, 0x26a2aa11,
+ 0x730d5de3, 0x2698a4a6, 0x7314f0f6, 0x268e9dbd,
+ 0x731c8211, 0x26849558, 0x73241134, 0x267a8b77,
+ 0x732b9e5e, 0x2670801a, 0x7333298f, 0x26667342,
+ 0x733ab2c6, 0x265c64ef, 0x73423a04, 0x26525521,
+ 0x7349bf48, 0x264843d9, 0x73514292, 0x263e3117,
+ 0x7358c3e2, 0x26341cdb, 0x73604336, 0x262a0727,
+ 0x7367c090, 0x261feffa, 0x736f3bee, 0x2615d754,
+ 0x7376b551, 0x260bbd37, 0x737e2cb7, 0x2601a1a2,
+ 0x7385a222, 0x25f78497, 0x738d1590, 0x25ed6614,
+ 0x73948701, 0x25e3461b, 0x739bf675, 0x25d924ac,
+ 0x73a363ec, 0x25cf01c8, 0x73aacf65, 0x25c4dd6e,
+ 0x73b238e0, 0x25bab7a0, 0x73b9a05d, 0x25b0905d,
+ 0x73c105db, 0x25a667a7, 0x73c8695b, 0x259c3d7c,
+ 0x73cfcadc, 0x259211df, 0x73d72a5d, 0x2587e4cf,
+ 0x73de87de, 0x257db64c, 0x73e5e360, 0x25738657,
+ 0x73ed3ce1, 0x256954f1, 0x73f49462, 0x255f2219,
+ 0x73fbe9e2, 0x2554edd1, 0x74033d61, 0x254ab818,
+ 0x740a8edf, 0x254080ef, 0x7411de5b, 0x25364857,
+ 0x74192bd5, 0x252c0e4f, 0x7420774d, 0x2521d2d8,
+ 0x7427c0c3, 0x251795f3, 0x742f0836, 0x250d57a0,
+ 0x74364da6, 0x250317df, 0x743d9112, 0x24f8d6b0,
+ 0x7444d27b, 0x24ee9415, 0x744c11e0, 0x24e4500e,
+ 0x74534f41, 0x24da0a9a, 0x745a8a9d, 0x24cfc3ba,
+ 0x7461c3f5, 0x24c57b6f, 0x7468fb47, 0x24bb31ba,
+ 0x74703095, 0x24b0e699, 0x747763dd, 0x24a69a0f,
+ 0x747e951f, 0x249c4c1b, 0x7485c45b, 0x2491fcbe,
+ 0x748cf190, 0x2487abf7, 0x74941cbf, 0x247d59c8,
+ 0x749b45e7, 0x24730631, 0x74a26d08, 0x2468b132,
+ 0x74a99221, 0x245e5acc, 0x74b0b533, 0x245402ff,
+ 0x74b7d63c, 0x2449a9cc, 0x74bef53d, 0x243f4f32,
+ 0x74c61236, 0x2434f332, 0x74cd2d26, 0x242a95ce,
+ 0x74d4460c, 0x24203704, 0x74db5cea, 0x2415d6d5,
+ 0x74e271bd, 0x240b7543, 0x74e98487, 0x2401124d,
+ 0x74f09546, 0x23f6adf3, 0x74f7a3fb, 0x23ec4837,
+ 0x74feb0a5, 0x23e1e117, 0x7505bb44, 0x23d77896,
+ 0x750cc3d8, 0x23cd0eb3, 0x7513ca60, 0x23c2a36f,
+ 0x751acedd, 0x23b836ca, 0x7521d14d, 0x23adc8c4,
+ 0x7528d1b1, 0x23a3595e, 0x752fd008, 0x2398e898,
+ 0x7536cc52, 0x238e7673, 0x753dc68f, 0x238402ef,
+ 0x7544bebf, 0x23798e0d, 0x754bb4e1, 0x236f17cc,
+ 0x7552a8f4, 0x2364a02e, 0x75599afa, 0x235a2733,
+ 0x75608af1, 0x234facda, 0x756778d9, 0x23453125,
+ 0x756e64b2, 0x233ab414, 0x75754e7c, 0x233035a7,
+ 0x757c3636, 0x2325b5df, 0x75831be0, 0x231b34bc,
+ 0x7589ff7a, 0x2310b23e, 0x7590e104, 0x23062e67,
+ 0x7597c07d, 0x22fba936, 0x759e9de5, 0x22f122ab,
+ 0x75a5793c, 0x22e69ac8, 0x75ac5282, 0x22dc118c,
+ 0x75b329b5, 0x22d186f8, 0x75b9fed7, 0x22c6fb0c,
+ 0x75c0d1e7, 0x22bc6dca, 0x75c7a2e3, 0x22b1df30,
+ 0x75ce71ce, 0x22a74f40, 0x75d53ea5, 0x229cbdfa,
+ 0x75dc0968, 0x22922b5e, 0x75e2d219, 0x2287976e,
+ 0x75e998b5, 0x227d0228, 0x75f05d3d, 0x22726b8e,
+ 0x75f71fb1, 0x2267d3a0, 0x75fde011, 0x225d3a5e,
+ 0x76049e5b, 0x22529fca, 0x760b5a90, 0x224803e2,
+ 0x761214b0, 0x223d66a8, 0x7618ccba, 0x2232c81c,
+ 0x761f82af, 0x2228283f, 0x7626368d, 0x221d8711,
+ 0x762ce855, 0x2212e492, 0x76339806, 0x220840c2,
+ 0x763a45a0, 0x21fd9ba3, 0x7640f123, 0x21f2f534,
+ 0x76479a8e, 0x21e84d76, 0x764e41e2, 0x21dda46a,
+ 0x7654e71d, 0x21d2fa0f, 0x765b8a41, 0x21c84e67,
+ 0x76622b4c, 0x21bda171, 0x7668ca3e, 0x21b2f32e,
+ 0x766f6717, 0x21a8439e, 0x767601d7, 0x219d92c2,
+ 0x767c9a7e, 0x2192e09b, 0x7683310b, 0x21882d28,
+ 0x7689c57d, 0x217d786a, 0x769057d6, 0x2172c262,
+ 0x7696e814, 0x21680b0f, 0x769d7637, 0x215d5273,
+ 0x76a4023f, 0x2152988d, 0x76aa8c2c, 0x2147dd5f,
+ 0x76b113fd, 0x213d20e8, 0x76b799b3, 0x21326329,
+ 0x76be1d4c, 0x2127a423, 0x76c49ec9, 0x211ce3d5,
+ 0x76cb1e2a, 0x21122240, 0x76d19b6e, 0x21075f65,
+ 0x76d81695, 0x20fc9b44, 0x76de8f9e, 0x20f1d5de,
+ 0x76e5068a, 0x20e70f32, 0x76eb7b58, 0x20dc4742,
+ 0x76f1ee09, 0x20d17e0d, 0x76f85e9a, 0x20c6b395,
+ 0x76fecd0e, 0x20bbe7d8, 0x77053962, 0x20b11ad9,
+ 0x770ba398, 0x20a64c97, 0x77120bae, 0x209b7d13,
+ 0x771871a5, 0x2090ac4d, 0x771ed57c, 0x2085da46,
+ 0x77253733, 0x207b06fe, 0x772b96ca, 0x20703275,
+ 0x7731f440, 0x20655cac, 0x77384f95, 0x205a85a3,
+ 0x773ea8ca, 0x204fad5b, 0x7744ffdd, 0x2044d3d4,
+ 0x774b54ce, 0x2039f90f, 0x7751a79e, 0x202f1d0b,
+ 0x7757f84c, 0x20243fca, 0x775e46d8, 0x2019614c,
+ 0x77649341, 0x200e8190, 0x776add88, 0x2003a099,
+ 0x777125ac, 0x1ff8be65, 0x77776bac, 0x1feddaf6,
+ 0x777daf89, 0x1fe2f64c, 0x7783f143, 0x1fd81067,
+ 0x778a30d8, 0x1fcd2948, 0x77906e49, 0x1fc240ef,
+ 0x7796a996, 0x1fb7575c, 0x779ce2be, 0x1fac6c91,
+ 0x77a319c2, 0x1fa1808c, 0x77a94ea0, 0x1f969350,
+ 0x77af8159, 0x1f8ba4dc, 0x77b5b1ec, 0x1f80b531,
+ 0x77bbe05a, 0x1f75c44e, 0x77c20ca1, 0x1f6ad235,
+ 0x77c836c2, 0x1f5fdee6, 0x77ce5ebd, 0x1f54ea62,
+ 0x77d48490, 0x1f49f4a8, 0x77daa83d, 0x1f3efdb9,
+ 0x77e0c9c3, 0x1f340596, 0x77e6e921, 0x1f290c3f,
+ 0x77ed0657, 0x1f1e11b5, 0x77f32165, 0x1f1315f7,
+ 0x77f93a4b, 0x1f081907, 0x77ff5109, 0x1efd1ae4,
+ 0x7805659e, 0x1ef21b90, 0x780b780a, 0x1ee71b0a,
+ 0x7811884d, 0x1edc1953, 0x78179666, 0x1ed1166b,
+ 0x781da256, 0x1ec61254, 0x7823ac1d, 0x1ebb0d0d,
+ 0x7829b3b9, 0x1eb00696, 0x782fb92a, 0x1ea4fef0,
+ 0x7835bc71, 0x1e99f61d, 0x783bbd8e, 0x1e8eec1b,
+ 0x7841bc7f, 0x1e83e0eb, 0x7847b946, 0x1e78d48e,
+ 0x784db3e0, 0x1e6dc705, 0x7853ac4f, 0x1e62b84f,
+ 0x7859a292, 0x1e57a86d, 0x785f96a9, 0x1e4c9760,
+ 0x78658894, 0x1e418528, 0x786b7852, 0x1e3671c5,
+ 0x787165e3, 0x1e2b5d38, 0x78775147, 0x1e204781,
+ 0x787d3a7e, 0x1e1530a1, 0x78832187, 0x1e0a1898,
+ 0x78890663, 0x1dfeff67, 0x788ee910, 0x1df3e50d,
+ 0x7894c98f, 0x1de8c98c, 0x789aa7e0, 0x1dddace4,
+ 0x78a08402, 0x1dd28f15, 0x78a65df6, 0x1dc7701f,
+ 0x78ac35ba, 0x1dbc5004, 0x78b20b4f, 0x1db12ec3,
+ 0x78b7deb4, 0x1da60c5d, 0x78bdafea, 0x1d9ae8d2,
+ 0x78c37eef, 0x1d8fc424, 0x78c94bc4, 0x1d849e51,
+ 0x78cf1669, 0x1d79775c, 0x78d4dedd, 0x1d6e4f43,
+ 0x78daa520, 0x1d632608, 0x78e06932, 0x1d57fbaa,
+ 0x78e62b13, 0x1d4cd02c, 0x78ebeac2, 0x1d41a38c,
+ 0x78f1a840, 0x1d3675cb, 0x78f7638b, 0x1d2b46ea,
+ 0x78fd1ca4, 0x1d2016e9, 0x7902d38b, 0x1d14e5c9,
+ 0x7908883f, 0x1d09b389, 0x790e3ac0, 0x1cfe802b,
+ 0x7913eb0e, 0x1cf34baf, 0x79199929, 0x1ce81615,
+ 0x791f4510, 0x1cdcdf5e, 0x7924eec3, 0x1cd1a78a,
+ 0x792a9642, 0x1cc66e99, 0x79303b8e, 0x1cbb348d,
+ 0x7935dea4, 0x1caff965, 0x793b7f86, 0x1ca4bd21,
+ 0x79411e33, 0x1c997fc4, 0x7946baac, 0x1c8e414b,
+ 0x794c54ee, 0x1c8301b9, 0x7951ecfc, 0x1c77c10e,
+ 0x795782d3, 0x1c6c7f4a, 0x795d1675, 0x1c613c6d,
+ 0x7962a7e0, 0x1c55f878, 0x79683715, 0x1c4ab36b,
+ 0x796dc414, 0x1c3f6d47, 0x79734edc, 0x1c34260c,
+ 0x7978d76c, 0x1c28ddbb, 0x797e5dc6, 0x1c1d9454,
+ 0x7983e1e8, 0x1c1249d8, 0x798963d2, 0x1c06fe46,
+ 0x798ee385, 0x1bfbb1a0, 0x799460ff, 0x1bf063e6,
+ 0x7999dc42, 0x1be51518, 0x799f554b, 0x1bd9c537,
+ 0x79a4cc1c, 0x1bce7442, 0x79aa40b4, 0x1bc3223c,
+ 0x79afb313, 0x1bb7cf23, 0x79b52339, 0x1bac7af9,
+ 0x79ba9125, 0x1ba125bd, 0x79bffcd7, 0x1b95cf71,
+ 0x79c5664f, 0x1b8a7815, 0x79cacd8d, 0x1b7f1fa9,
+ 0x79d03291, 0x1b73c62d, 0x79d5955a, 0x1b686ba3,
+ 0x79daf5e8, 0x1b5d100a, 0x79e0543c, 0x1b51b363,
+ 0x79e5b054, 0x1b4655ae, 0x79eb0a31, 0x1b3af6ec,
+ 0x79f061d2, 0x1b2f971e, 0x79f5b737, 0x1b243643,
+ 0x79fb0a60, 0x1b18d45c, 0x7a005b4d, 0x1b0d716a,
+ 0x7a05a9fd, 0x1b020d6c, 0x7a0af671, 0x1af6a865,
+ 0x7a1040a8, 0x1aeb4253, 0x7a1588a2, 0x1adfdb37,
+ 0x7a1ace5f, 0x1ad47312, 0x7a2011de, 0x1ac909e5,
+ 0x7a25531f, 0x1abd9faf, 0x7a2a9223, 0x1ab23471,
+ 0x7a2fcee8, 0x1aa6c82b, 0x7a350970, 0x1a9b5adf,
+ 0x7a3a41b9, 0x1a8fec8c, 0x7a3f77c3, 0x1a847d33,
+ 0x7a44ab8e, 0x1a790cd4, 0x7a49dd1a, 0x1a6d9b70,
+ 0x7a4f0c67, 0x1a622907, 0x7a543974, 0x1a56b599,
+ 0x7a596442, 0x1a4b4128, 0x7a5e8cd0, 0x1a3fcbb3,
+ 0x7a63b31d, 0x1a34553b, 0x7a68d72b, 0x1a28ddc0,
+ 0x7a6df8f8, 0x1a1d6544, 0x7a731884, 0x1a11ebc5,
+ 0x7a7835cf, 0x1a067145, 0x7a7d50da, 0x19faf5c5,
+ 0x7a8269a3, 0x19ef7944, 0x7a87802a, 0x19e3fbc3,
+ 0x7a8c9470, 0x19d87d42, 0x7a91a674, 0x19ccfdc2,
+ 0x7a96b636, 0x19c17d44, 0x7a9bc3b6, 0x19b5fbc8,
+ 0x7aa0cef3, 0x19aa794d, 0x7aa5d7ee, 0x199ef5d6,
+ 0x7aaadea6, 0x19937161, 0x7aafe31b, 0x1987ebf0,
+ 0x7ab4e54c, 0x197c6584, 0x7ab9e53a, 0x1970de1b,
+ 0x7abee2e5, 0x196555b8, 0x7ac3de4c, 0x1959cc5a,
+ 0x7ac8d76f, 0x194e4201, 0x7acdce4d, 0x1942b6af,
+ 0x7ad2c2e8, 0x19372a64, 0x7ad7b53d, 0x192b9d1f,
+ 0x7adca54e, 0x19200ee3, 0x7ae1931a, 0x19147fae,
+ 0x7ae67ea1, 0x1908ef82, 0x7aeb67e3, 0x18fd5e5f,
+ 0x7af04edf, 0x18f1cc45, 0x7af53395, 0x18e63935,
+ 0x7afa1605, 0x18daa52f, 0x7afef630, 0x18cf1034,
+ 0x7b03d414, 0x18c37a44, 0x7b08afb2, 0x18b7e35f,
+ 0x7b0d8909, 0x18ac4b87, 0x7b126019, 0x18a0b2bb,
+ 0x7b1734e2, 0x189518fc, 0x7b1c0764, 0x18897e4a,
+ 0x7b20d79e, 0x187de2a7, 0x7b25a591, 0x18724611,
+ 0x7b2a713d, 0x1866a88a, 0x7b2f3aa0, 0x185b0a13,
+ 0x7b3401bb, 0x184f6aab, 0x7b38c68e, 0x1843ca53,
+ 0x7b3d8918, 0x1838290c, 0x7b42495a, 0x182c86d5,
+ 0x7b470753, 0x1820e3b0, 0x7b4bc303, 0x18153f9d,
+ 0x7b507c69, 0x18099a9c, 0x7b553386, 0x17fdf4ae,
+ 0x7b59e85a, 0x17f24dd3, 0x7b5e9ae4, 0x17e6a60c,
+ 0x7b634b23, 0x17dafd59, 0x7b67f919, 0x17cf53bb,
+ 0x7b6ca4c4, 0x17c3a931, 0x7b714e25, 0x17b7fdbd,
+ 0x7b75f53c, 0x17ac515f, 0x7b7a9a07, 0x17a0a417,
+ 0x7b7f3c87, 0x1794f5e6, 0x7b83dcbc, 0x178946cc,
+ 0x7b887aa6, 0x177d96ca, 0x7b8d1644, 0x1771e5e0,
+ 0x7b91af97, 0x1766340f, 0x7b96469d, 0x175a8157,
+ 0x7b9adb57, 0x174ecdb8, 0x7b9f6dc5, 0x17431933,
+ 0x7ba3fde7, 0x173763c9, 0x7ba88bbc, 0x172bad7a,
+ 0x7bad1744, 0x171ff646, 0x7bb1a080, 0x17143e2d,
+ 0x7bb6276e, 0x17088531, 0x7bbaac0e, 0x16fccb51,
+ 0x7bbf2e62, 0x16f1108f, 0x7bc3ae67, 0x16e554ea,
+ 0x7bc82c1f, 0x16d99864, 0x7bcca789, 0x16cddafb,
+ 0x7bd120a4, 0x16c21cb2, 0x7bd59771, 0x16b65d88,
+ 0x7bda0bf0, 0x16aa9d7e, 0x7bde7e20, 0x169edc94,
+ 0x7be2ee01, 0x16931acb, 0x7be75b93, 0x16875823,
+ 0x7bebc6d5, 0x167b949d, 0x7bf02fc9, 0x166fd039,
+ 0x7bf4966c, 0x16640af7, 0x7bf8fac0, 0x165844d8,
+ 0x7bfd5cc4, 0x164c7ddd, 0x7c01bc78, 0x1640b606,
+ 0x7c0619dc, 0x1634ed53, 0x7c0a74f0, 0x162923c5,
+ 0x7c0ecdb2, 0x161d595d, 0x7c132424, 0x16118e1a,
+ 0x7c177845, 0x1605c1fd, 0x7c1bca16, 0x15f9f507,
+ 0x7c201994, 0x15ee2738, 0x7c2466c2, 0x15e25890,
+ 0x7c28b19e, 0x15d68911, 0x7c2cfa28, 0x15cab8ba,
+ 0x7c314060, 0x15bee78c, 0x7c358446, 0x15b31587,
+ 0x7c39c5da, 0x15a742ac, 0x7c3e051b, 0x159b6efb,
+ 0x7c42420a, 0x158f9a76, 0x7c467ca6, 0x1583c51b,
+ 0x7c4ab4ef, 0x1577eeec, 0x7c4eeae5, 0x156c17e9,
+ 0x7c531e88, 0x15604013, 0x7c574fd8, 0x1554676a,
+ 0x7c5b7ed4, 0x15488dee, 0x7c5fab7c, 0x153cb3a0,
+ 0x7c63d5d1, 0x1530d881, 0x7c67fdd1, 0x1524fc90,
+ 0x7c6c237e, 0x15191fcf, 0x7c7046d6, 0x150d423d,
+ 0x7c7467d9, 0x150163dc, 0x7c788688, 0x14f584ac,
+ 0x7c7ca2e2, 0x14e9a4ac, 0x7c80bce7, 0x14ddc3de,
+ 0x7c84d496, 0x14d1e242, 0x7c88e9f1, 0x14c5ffd9,
+ 0x7c8cfcf6, 0x14ba1ca3, 0x7c910da5, 0x14ae38a0,
+ 0x7c951bff, 0x14a253d1, 0x7c992803, 0x14966e36,
+ 0x7c9d31b0, 0x148a87d1, 0x7ca13908, 0x147ea0a0,
+ 0x7ca53e09, 0x1472b8a5, 0x7ca940b3, 0x1466cfe1,
+ 0x7cad4107, 0x145ae653, 0x7cb13f04, 0x144efbfc,
+ 0x7cb53aaa, 0x144310dd, 0x7cb933f9, 0x143724f5,
+ 0x7cbd2af0, 0x142b3846, 0x7cc11f90, 0x141f4ad1,
+ 0x7cc511d9, 0x14135c94, 0x7cc901c9, 0x14076d91,
+ 0x7cccef62, 0x13fb7dc9, 0x7cd0daa2, 0x13ef8d3c,
+ 0x7cd4c38b, 0x13e39be9, 0x7cd8aa1b, 0x13d7a9d3,
+ 0x7cdc8e52, 0x13cbb6f8, 0x7ce07031, 0x13bfc35b,
+ 0x7ce44fb7, 0x13b3cefa, 0x7ce82ce4, 0x13a7d9d7,
+ 0x7cec07b8, 0x139be3f2, 0x7cefe032, 0x138fed4b,
+ 0x7cf3b653, 0x1383f5e3, 0x7cf78a1b, 0x1377fdbb,
+ 0x7cfb5b89, 0x136c04d2, 0x7cff2a9d, 0x13600b2a,
+ 0x7d02f757, 0x135410c3, 0x7d06c1b6, 0x1348159d,
+ 0x7d0a89bc, 0x133c19b8, 0x7d0e4f67, 0x13301d16,
+ 0x7d1212b7, 0x13241fb6, 0x7d15d3ad, 0x1318219a,
+ 0x7d199248, 0x130c22c1, 0x7d1d4e88, 0x1300232c,
+ 0x7d21086c, 0x12f422db, 0x7d24bff6, 0x12e821cf,
+ 0x7d287523, 0x12dc2009, 0x7d2c27f6, 0x12d01d89,
+ 0x7d2fd86c, 0x12c41a4f, 0x7d338687, 0x12b8165b,
+ 0x7d373245, 0x12ac11af, 0x7d3adba7, 0x12a00c4b,
+ 0x7d3e82ae, 0x1294062f, 0x7d422757, 0x1287ff5b,
+ 0x7d45c9a4, 0x127bf7d1, 0x7d496994, 0x126fef90,
+ 0x7d4d0728, 0x1263e699, 0x7d50a25e, 0x1257dced,
+ 0x7d543b37, 0x124bd28c, 0x7d57d1b3, 0x123fc776,
+ 0x7d5b65d2, 0x1233bbac, 0x7d5ef793, 0x1227af2e,
+ 0x7d6286f6, 0x121ba1fd, 0x7d6613fb, 0x120f941a,
+ 0x7d699ea3, 0x12038584, 0x7d6d26ec, 0x11f7763c,
+ 0x7d70acd7, 0x11eb6643, 0x7d743064, 0x11df5599,
+ 0x7d77b192, 0x11d3443f, 0x7d7b3061, 0x11c73235,
+ 0x7d7eacd2, 0x11bb1f7c, 0x7d8226e4, 0x11af0c13,
+ 0x7d859e96, 0x11a2f7fc, 0x7d8913ea, 0x1196e337,
+ 0x7d8c86de, 0x118acdc4, 0x7d8ff772, 0x117eb7a4,
+ 0x7d9365a8, 0x1172a0d7, 0x7d96d17d, 0x1166895f,
+ 0x7d9a3af2, 0x115a713a, 0x7d9da208, 0x114e586a,
+ 0x7da106bd, 0x11423ef0, 0x7da46912, 0x113624cb,
+ 0x7da7c907, 0x112a09fc, 0x7dab269b, 0x111dee84,
+ 0x7dae81cf, 0x1111d263, 0x7db1daa2, 0x1105b599,
+ 0x7db53113, 0x10f99827, 0x7db88524, 0x10ed7a0e,
+ 0x7dbbd6d4, 0x10e15b4e, 0x7dbf2622, 0x10d53be7,
+ 0x7dc2730f, 0x10c91bda, 0x7dc5bd9b, 0x10bcfb28,
+ 0x7dc905c5, 0x10b0d9d0, 0x7dcc4b8d, 0x10a4b7d3,
+ 0x7dcf8ef3, 0x10989532, 0x7dd2cff7, 0x108c71ee,
+ 0x7dd60e99, 0x10804e06, 0x7dd94ad8, 0x1074297b,
+ 0x7ddc84b5, 0x1068044e, 0x7ddfbc30, 0x105bde7f,
+ 0x7de2f148, 0x104fb80e, 0x7de623fd, 0x104390fd,
+ 0x7de9544f, 0x1037694b, 0x7dec823e, 0x102b40f8,
+ 0x7defadca, 0x101f1807, 0x7df2d6f3, 0x1012ee76,
+ 0x7df5fdb8, 0x1006c446, 0x7df9221a, 0xffa9979,
+ 0x7dfc4418, 0xfee6e0d, 0x7dff63b2, 0xfe24205,
+ 0x7e0280e9, 0xfd6155f, 0x7e059bbb, 0xfc9e81e,
+ 0x7e08b42a, 0xfbdba40, 0x7e0bca34, 0xfb18bc8,
+ 0x7e0eddd9, 0xfa55cb4, 0x7e11ef1b, 0xf992d06,
+ 0x7e14fdf7, 0xf8cfcbe, 0x7e180a6f, 0xf80cbdc,
+ 0x7e1b1482, 0xf749a61, 0x7e1e1c30, 0xf68684e,
+ 0x7e212179, 0xf5c35a3, 0x7e24245d, 0xf500260,
+ 0x7e2724db, 0xf43ce86, 0x7e2a22f4, 0xf379a16,
+ 0x7e2d1ea8, 0xf2b650f, 0x7e3017f6, 0xf1f2f73,
+ 0x7e330ede, 0xf12f941, 0x7e360360, 0xf06c27a,
+ 0x7e38f57c, 0xefa8b20, 0x7e3be532, 0xeee5331,
+ 0x7e3ed282, 0xee21aaf, 0x7e41bd6c, 0xed5e19a,
+ 0x7e44a5ef, 0xec9a7f3, 0x7e478c0b, 0xebd6db9,
+ 0x7e4a6fc1, 0xeb132ef, 0x7e4d5110, 0xea4f793,
+ 0x7e502ff9, 0xe98bba7, 0x7e530c7a, 0xe8c7f2a,
+ 0x7e55e694, 0xe80421e, 0x7e58be47, 0xe740483,
+ 0x7e5b9392, 0xe67c65a, 0x7e5e6676, 0xe5b87a2,
+ 0x7e6136f3, 0xe4f485c, 0x7e640507, 0xe430889,
+ 0x7e66d0b4, 0xe36c82a, 0x7e6999fa, 0xe2a873e,
+ 0x7e6c60d7, 0xe1e45c6, 0x7e6f254c, 0xe1203c3,
+ 0x7e71e759, 0xe05c135, 0x7e74a6fd, 0xdf97e1d,
+ 0x7e77643a, 0xded3a7b, 0x7e7a1f0d, 0xde0f64f,
+ 0x7e7cd778, 0xdd4b19a, 0x7e7f8d7b, 0xdc86c5d,
+ 0x7e824114, 0xdbc2698, 0x7e84f245, 0xdafe04b,
+ 0x7e87a10c, 0xda39978, 0x7e8a4d6a, 0xd97521d,
+ 0x7e8cf75f, 0xd8b0a3d, 0x7e8f9eeb, 0xd7ec1d6,
+ 0x7e92440d, 0xd7278eb, 0x7e94e6c6, 0xd662f7b,
+ 0x7e978715, 0xd59e586, 0x7e9a24fb, 0xd4d9b0e,
+ 0x7e9cc076, 0xd415013, 0x7e9f5988, 0xd350495,
+ 0x7ea1f02f, 0xd28b894, 0x7ea4846c, 0xd1c6c11,
+ 0x7ea7163f, 0xd101f0e, 0x7ea9a5a8, 0xd03d189,
+ 0x7eac32a6, 0xcf78383, 0x7eaebd3a, 0xceb34fe,
+ 0x7eb14563, 0xcdee5f9, 0x7eb3cb21, 0xcd29676,
+ 0x7eb64e75, 0xcc64673, 0x7eb8cf5d, 0xcb9f5f3,
+ 0x7ebb4ddb, 0xcada4f5, 0x7ebdc9ed, 0xca1537a,
+ 0x7ec04394, 0xc950182, 0x7ec2bad0, 0xc88af0e,
+ 0x7ec52fa0, 0xc7c5c1e, 0x7ec7a205, 0xc7008b3,
+ 0x7eca11fe, 0xc63b4ce, 0x7ecc7f8b, 0xc57606e,
+ 0x7eceeaad, 0xc4b0b94, 0x7ed15363, 0xc3eb641,
+ 0x7ed3b9ad, 0xc326075, 0x7ed61d8a, 0xc260a31,
+ 0x7ed87efc, 0xc19b374, 0x7edade01, 0xc0d5c41,
+ 0x7edd3a9a, 0xc010496, 0x7edf94c7, 0xbf4ac75,
+ 0x7ee1ec87, 0xbe853de, 0x7ee441da, 0xbdbfad1,
+ 0x7ee694c1, 0xbcfa150, 0x7ee8e53a, 0xbc34759,
+ 0x7eeb3347, 0xbb6ecef, 0x7eed7ee7, 0xbaa9211,
+ 0x7eefc81a, 0xb9e36c0, 0x7ef20ee0, 0xb91dafc,
+ 0x7ef45338, 0xb857ec7, 0x7ef69523, 0xb79221f,
+ 0x7ef8d4a1, 0xb6cc506, 0x7efb11b1, 0xb60677c,
+ 0x7efd4c54, 0xb540982, 0x7eff8489, 0xb47ab19,
+ 0x7f01ba50, 0xb3b4c40, 0x7f03eda9, 0xb2eecf8,
+ 0x7f061e95, 0xb228d42, 0x7f084d12, 0xb162d1d,
+ 0x7f0a7921, 0xb09cc8c, 0x7f0ca2c2, 0xafd6b8d,
+ 0x7f0ec9f5, 0xaf10a22, 0x7f10eeb9, 0xae4a84b,
+ 0x7f13110f, 0xad84609, 0x7f1530f7, 0xacbe35b,
+ 0x7f174e70, 0xabf8043, 0x7f19697a, 0xab31cc1,
+ 0x7f1b8215, 0xaa6b8d5, 0x7f1d9842, 0xa9a5480,
+ 0x7f1fabff, 0xa8defc3, 0x7f21bd4e, 0xa818a9d,
+ 0x7f23cc2e, 0xa752510, 0x7f25d89e, 0xa68bf1b,
+ 0x7f27e29f, 0xa5c58c0, 0x7f29ea31, 0xa4ff1fe,
+ 0x7f2bef53, 0xa438ad7, 0x7f2df206, 0xa37234a,
+ 0x7f2ff24a, 0xa2abb59, 0x7f31f01d, 0xa1e5303,
+ 0x7f33eb81, 0xa11ea49, 0x7f35e476, 0xa05812c,
+ 0x7f37dafa, 0x9f917ac, 0x7f39cf0e, 0x9ecadc9,
+ 0x7f3bc0b3, 0x9e04385, 0x7f3dafe7, 0x9d3d8df,
+ 0x7f3f9cab, 0x9c76dd8, 0x7f4186ff, 0x9bb0271,
+ 0x7f436ee3, 0x9ae96aa, 0x7f455456, 0x9a22a83,
+ 0x7f473759, 0x995bdfd, 0x7f4917eb, 0x9895118,
+ 0x7f4af60d, 0x97ce3d5, 0x7f4cd1be, 0x9707635,
+ 0x7f4eaafe, 0x9640837, 0x7f5081cd, 0x95799dd,
+ 0x7f52562c, 0x94b2b27, 0x7f54281a, 0x93ebc14,
+ 0x7f55f796, 0x9324ca7, 0x7f57c4a2, 0x925dcdf,
+ 0x7f598f3c, 0x9196cbc, 0x7f5b5765, 0x90cfc40,
+ 0x7f5d1d1d, 0x9008b6a, 0x7f5ee063, 0x8f41a3c,
+ 0x7f60a138, 0x8e7a8b5, 0x7f625f9b, 0x8db36d6,
+ 0x7f641b8d, 0x8cec4a0, 0x7f65d50d, 0x8c25213,
+ 0x7f678c1c, 0x8b5df30, 0x7f6940b8, 0x8a96bf6,
+ 0x7f6af2e3, 0x89cf867, 0x7f6ca29c, 0x8908483,
+ 0x7f6e4fe3, 0x884104b, 0x7f6ffab8, 0x8779bbe,
+ 0x7f71a31b, 0x86b26de, 0x7f73490b, 0x85eb1ab,
+ 0x7f74ec8a, 0x8523c25, 0x7f768d96, 0x845c64d,
+ 0x7f782c30, 0x8395024, 0x7f79c857, 0x82cd9a9,
+ 0x7f7b620c, 0x82062de, 0x7f7cf94e, 0x813ebc2,
+ 0x7f7e8e1e, 0x8077457, 0x7f80207b, 0x7fafc9c,
+ 0x7f81b065, 0x7ee8493, 0x7f833ddd, 0x7e20c3b,
+ 0x7f84c8e2, 0x7d59396, 0x7f865174, 0x7c91aa3,
+ 0x7f87d792, 0x7bca163, 0x7f895b3e, 0x7b027d7,
+ 0x7f8adc77, 0x7a3adff, 0x7f8c5b3d, 0x79733dc,
+ 0x7f8dd78f, 0x78ab96e, 0x7f8f516e, 0x77e3eb5,
+ 0x7f90c8da, 0x771c3b3, 0x7f923dd2, 0x7654867,
+ 0x7f93b058, 0x758ccd2, 0x7f952069, 0x74c50f4,
+ 0x7f968e07, 0x73fd4cf, 0x7f97f932, 0x7335862,
+ 0x7f9961e8, 0x726dbae, 0x7f9ac82c, 0x71a5eb3,
+ 0x7f9c2bfb, 0x70de172, 0x7f9d8d56, 0x70163eb,
+ 0x7f9eec3e, 0x6f4e620, 0x7fa048b2, 0x6e86810,
+ 0x7fa1a2b2, 0x6dbe9bb, 0x7fa2fa3d, 0x6cf6b23,
+ 0x7fa44f55, 0x6c2ec48, 0x7fa5a1f9, 0x6b66d29,
+ 0x7fa6f228, 0x6a9edc9, 0x7fa83fe3, 0x69d6e27,
+ 0x7fa98b2a, 0x690ee44, 0x7faad3fd, 0x6846e1f,
+ 0x7fac1a5b, 0x677edbb, 0x7fad5e45, 0x66b6d16,
+ 0x7fae9fbb, 0x65eec33, 0x7fafdebb, 0x6526b10,
+ 0x7fb11b48, 0x645e9af, 0x7fb2555f, 0x6396810,
+ 0x7fb38d02, 0x62ce634, 0x7fb4c231, 0x620641a,
+ 0x7fb5f4ea, 0x613e1c5, 0x7fb7252f, 0x6075f33,
+ 0x7fb852ff, 0x5fadc66, 0x7fb97e5a, 0x5ee595d,
+ 0x7fbaa740, 0x5e1d61b, 0x7fbbcdb1, 0x5d5529e,
+ 0x7fbcf1ad, 0x5c8cee7, 0x7fbe1334, 0x5bc4af8,
+ 0x7fbf3246, 0x5afc6d0, 0x7fc04ee3, 0x5a3426f,
+ 0x7fc1690a, 0x596bdd7, 0x7fc280bc, 0x58a3908,
+ 0x7fc395f9, 0x57db403, 0x7fc4a8c1, 0x5712ec7,
+ 0x7fc5b913, 0x564a955, 0x7fc6c6f0, 0x55823ae,
+ 0x7fc7d258, 0x54b9dd3, 0x7fc8db4a, 0x53f17c3,
+ 0x7fc9e1c6, 0x532917f, 0x7fcae5cd, 0x5260b08,
+ 0x7fcbe75e, 0x519845e, 0x7fcce67a, 0x50cfd82,
+ 0x7fcde320, 0x5007674, 0x7fcedd50, 0x4f3ef35,
+ 0x7fcfd50b, 0x4e767c5, 0x7fd0ca4f, 0x4dae024,
+ 0x7fd1bd1e, 0x4ce5854, 0x7fd2ad77, 0x4c1d054,
+ 0x7fd39b5a, 0x4b54825, 0x7fd486c7, 0x4a8bfc7,
+ 0x7fd56fbe, 0x49c373c, 0x7fd6563f, 0x48fae83,
+ 0x7fd73a4a, 0x483259d, 0x7fd81bdf, 0x4769c8b,
+ 0x7fd8fafe, 0x46a134c, 0x7fd9d7a7, 0x45d89e2,
+ 0x7fdab1d9, 0x451004d, 0x7fdb8996, 0x444768d,
+ 0x7fdc5edc, 0x437eca4, 0x7fdd31ac, 0x42b6290,
+ 0x7fde0205, 0x41ed854, 0x7fdecfe8, 0x4124dee,
+ 0x7fdf9b55, 0x405c361, 0x7fe0644b, 0x3f938ac,
+ 0x7fe12acb, 0x3ecadcf, 0x7fe1eed5, 0x3e022cc,
+ 0x7fe2b067, 0x3d397a3, 0x7fe36f84, 0x3c70c54,
+ 0x7fe42c2a, 0x3ba80df, 0x7fe4e659, 0x3adf546,
+ 0x7fe59e12, 0x3a16988, 0x7fe65354, 0x394dda7,
+ 0x7fe7061f, 0x38851a2, 0x7fe7b674, 0x37bc57b,
+ 0x7fe86452, 0x36f3931, 0x7fe90fb9, 0x362acc5,
+ 0x7fe9b8a9, 0x3562038, 0x7fea5f23, 0x3499389,
+ 0x7feb0326, 0x33d06bb, 0x7feba4b2, 0x33079cc,
+ 0x7fec43c7, 0x323ecbe, 0x7fece065, 0x3175f91,
+ 0x7fed7a8c, 0x30ad245, 0x7fee123d, 0x2fe44dc,
+ 0x7feea776, 0x2f1b755, 0x7fef3a39, 0x2e529b0,
+ 0x7fefca84, 0x2d89bf0, 0x7ff05858, 0x2cc0e13,
+ 0x7ff0e3b6, 0x2bf801a, 0x7ff16c9c, 0x2b2f207,
+ 0x7ff1f30b, 0x2a663d8, 0x7ff27703, 0x299d590,
+ 0x7ff2f884, 0x28d472e, 0x7ff3778e, 0x280b8b3,
+ 0x7ff3f420, 0x2742a1f, 0x7ff46e3c, 0x2679b73,
+ 0x7ff4e5e0, 0x25b0caf, 0x7ff55b0d, 0x24e7dd4,
+ 0x7ff5cdc3, 0x241eee2, 0x7ff63e01, 0x2355fd9,
+ 0x7ff6abc8, 0x228d0bb, 0x7ff71718, 0x21c4188,
+ 0x7ff77ff1, 0x20fb240, 0x7ff7e652, 0x20322e3,
+ 0x7ff84a3c, 0x1f69373, 0x7ff8abae, 0x1ea03ef,
+ 0x7ff90aaa, 0x1dd7459, 0x7ff9672d, 0x1d0e4b0,
+ 0x7ff9c13a, 0x1c454f5, 0x7ffa18cf, 0x1b7c528,
+ 0x7ffa6dec, 0x1ab354b, 0x7ffac092, 0x19ea55d,
+ 0x7ffb10c1, 0x192155f, 0x7ffb5e78, 0x1858552,
+ 0x7ffba9b8, 0x178f536, 0x7ffbf280, 0x16c650b,
+ 0x7ffc38d1, 0x15fd4d2, 0x7ffc7caa, 0x153448c,
+ 0x7ffcbe0c, 0x146b438, 0x7ffcfcf6, 0x13a23d8,
+ 0x7ffd3969, 0x12d936c, 0x7ffd7364, 0x12102f4,
+ 0x7ffdaae7, 0x1147271, 0x7ffddff3, 0x107e1e3,
+ 0x7ffe1288, 0xfb514b, 0x7ffe42a4, 0xeec0aa,
+ 0x7ffe704a, 0xe22fff, 0x7ffe9b77, 0xd59f4c,
+ 0x7ffec42d, 0xc90e90, 0x7ffeea6c, 0xbc7dcc,
+ 0x7fff0e32, 0xafed02, 0x7fff2f82, 0xa35c30,
+ 0x7fff4e59, 0x96cb58, 0x7fff6ab9, 0x8a3a7b,
+ 0x7fff84a1, 0x7da998, 0x7fff9c12, 0x7118b0,
+ 0x7fffb10b, 0x6487c4, 0x7fffc38c, 0x57f6d4,
+ 0x7fffd396, 0x4b65e1, 0x7fffe128, 0x3ed4ea,
+ 0x7fffec43, 0x3243f1, 0x7ffff4e6, 0x25b2f7,
+ 0x7ffffb11, 0x1921fb, 0x7ffffec4, 0xc90fe,
+ 0x7fffffff, 0x0, 0x7ffffec4, 0xfff36f02,
+ 0x7ffffb11, 0xffe6de05, 0x7ffff4e6, 0xffda4d09,
+ 0x7fffec43, 0xffcdbc0f, 0x7fffe128, 0xffc12b16,
+ 0x7fffd396, 0xffb49a1f, 0x7fffc38c, 0xffa8092c,
+ 0x7fffb10b, 0xff9b783c, 0x7fff9c12, 0xff8ee750,
+ 0x7fff84a1, 0xff825668, 0x7fff6ab9, 0xff75c585,
+ 0x7fff4e59, 0xff6934a8, 0x7fff2f82, 0xff5ca3d0,
+ 0x7fff0e32, 0xff5012fe, 0x7ffeea6c, 0xff438234,
+ 0x7ffec42d, 0xff36f170, 0x7ffe9b77, 0xff2a60b4,
+ 0x7ffe704a, 0xff1dd001, 0x7ffe42a4, 0xff113f56,
+ 0x7ffe1288, 0xff04aeb5, 0x7ffddff3, 0xfef81e1d,
+ 0x7ffdaae7, 0xfeeb8d8f, 0x7ffd7364, 0xfedefd0c,
+ 0x7ffd3969, 0xfed26c94, 0x7ffcfcf6, 0xfec5dc28,
+ 0x7ffcbe0c, 0xfeb94bc8, 0x7ffc7caa, 0xfeacbb74,
+ 0x7ffc38d1, 0xfea02b2e, 0x7ffbf280, 0xfe939af5,
+ 0x7ffba9b8, 0xfe870aca, 0x7ffb5e78, 0xfe7a7aae,
+ 0x7ffb10c1, 0xfe6deaa1, 0x7ffac092, 0xfe615aa3,
+ 0x7ffa6dec, 0xfe54cab5, 0x7ffa18cf, 0xfe483ad8,
+ 0x7ff9c13a, 0xfe3bab0b, 0x7ff9672d, 0xfe2f1b50,
+ 0x7ff90aaa, 0xfe228ba7, 0x7ff8abae, 0xfe15fc11,
+ 0x7ff84a3c, 0xfe096c8d, 0x7ff7e652, 0xfdfcdd1d,
+ 0x7ff77ff1, 0xfdf04dc0, 0x7ff71718, 0xfde3be78,
+ 0x7ff6abc8, 0xfdd72f45, 0x7ff63e01, 0xfdcaa027,
+ 0x7ff5cdc3, 0xfdbe111e, 0x7ff55b0d, 0xfdb1822c,
+ 0x7ff4e5e0, 0xfda4f351, 0x7ff46e3c, 0xfd98648d,
+ 0x7ff3f420, 0xfd8bd5e1, 0x7ff3778e, 0xfd7f474d,
+ 0x7ff2f884, 0xfd72b8d2, 0x7ff27703, 0xfd662a70,
+ 0x7ff1f30b, 0xfd599c28, 0x7ff16c9c, 0xfd4d0df9,
+ 0x7ff0e3b6, 0xfd407fe6, 0x7ff05858, 0xfd33f1ed,
+ 0x7fefca84, 0xfd276410, 0x7fef3a39, 0xfd1ad650,
+ 0x7feea776, 0xfd0e48ab, 0x7fee123d, 0xfd01bb24,
+ 0x7fed7a8c, 0xfcf52dbb, 0x7fece065, 0xfce8a06f,
+ 0x7fec43c7, 0xfcdc1342, 0x7feba4b2, 0xfccf8634,
+ 0x7feb0326, 0xfcc2f945, 0x7fea5f23, 0xfcb66c77,
+ 0x7fe9b8a9, 0xfca9dfc8, 0x7fe90fb9, 0xfc9d533b,
+ 0x7fe86452, 0xfc90c6cf, 0x7fe7b674, 0xfc843a85,
+ 0x7fe7061f, 0xfc77ae5e, 0x7fe65354, 0xfc6b2259,
+ 0x7fe59e12, 0xfc5e9678, 0x7fe4e659, 0xfc520aba,
+ 0x7fe42c2a, 0xfc457f21, 0x7fe36f84, 0xfc38f3ac,
+ 0x7fe2b067, 0xfc2c685d, 0x7fe1eed5, 0xfc1fdd34,
+ 0x7fe12acb, 0xfc135231, 0x7fe0644b, 0xfc06c754,
+ 0x7fdf9b55, 0xfbfa3c9f, 0x7fdecfe8, 0xfbedb212,
+ 0x7fde0205, 0xfbe127ac, 0x7fdd31ac, 0xfbd49d70,
+ 0x7fdc5edc, 0xfbc8135c, 0x7fdb8996, 0xfbbb8973,
+ 0x7fdab1d9, 0xfbaeffb3, 0x7fd9d7a7, 0xfba2761e,
+ 0x7fd8fafe, 0xfb95ecb4, 0x7fd81bdf, 0xfb896375,
+ 0x7fd73a4a, 0xfb7cda63, 0x7fd6563f, 0xfb70517d,
+ 0x7fd56fbe, 0xfb63c8c4, 0x7fd486c7, 0xfb574039,
+ 0x7fd39b5a, 0xfb4ab7db, 0x7fd2ad77, 0xfb3e2fac,
+ 0x7fd1bd1e, 0xfb31a7ac, 0x7fd0ca4f, 0xfb251fdc,
+ 0x7fcfd50b, 0xfb18983b, 0x7fcedd50, 0xfb0c10cb,
+ 0x7fcde320, 0xfaff898c, 0x7fcce67a, 0xfaf3027e,
+ 0x7fcbe75e, 0xfae67ba2, 0x7fcae5cd, 0xfad9f4f8,
+ 0x7fc9e1c6, 0xfacd6e81, 0x7fc8db4a, 0xfac0e83d,
+ 0x7fc7d258, 0xfab4622d, 0x7fc6c6f0, 0xfaa7dc52,
+ 0x7fc5b913, 0xfa9b56ab, 0x7fc4a8c1, 0xfa8ed139,
+ 0x7fc395f9, 0xfa824bfd, 0x7fc280bc, 0xfa75c6f8,
+ 0x7fc1690a, 0xfa694229, 0x7fc04ee3, 0xfa5cbd91,
+ 0x7fbf3246, 0xfa503930, 0x7fbe1334, 0xfa43b508,
+ 0x7fbcf1ad, 0xfa373119, 0x7fbbcdb1, 0xfa2aad62,
+ 0x7fbaa740, 0xfa1e29e5, 0x7fb97e5a, 0xfa11a6a3,
+ 0x7fb852ff, 0xfa05239a, 0x7fb7252f, 0xf9f8a0cd,
+ 0x7fb5f4ea, 0xf9ec1e3b, 0x7fb4c231, 0xf9df9be6,
+ 0x7fb38d02, 0xf9d319cc, 0x7fb2555f, 0xf9c697f0,
+ 0x7fb11b48, 0xf9ba1651, 0x7fafdebb, 0xf9ad94f0,
+ 0x7fae9fbb, 0xf9a113cd, 0x7fad5e45, 0xf99492ea,
+ 0x7fac1a5b, 0xf9881245, 0x7faad3fd, 0xf97b91e1,
+ 0x7fa98b2a, 0xf96f11bc, 0x7fa83fe3, 0xf96291d9,
+ 0x7fa6f228, 0xf9561237, 0x7fa5a1f9, 0xf94992d7,
+ 0x7fa44f55, 0xf93d13b8, 0x7fa2fa3d, 0xf93094dd,
+ 0x7fa1a2b2, 0xf9241645, 0x7fa048b2, 0xf91797f0,
+ 0x7f9eec3e, 0xf90b19e0, 0x7f9d8d56, 0xf8fe9c15,
+ 0x7f9c2bfb, 0xf8f21e8e, 0x7f9ac82c, 0xf8e5a14d,
+ 0x7f9961e8, 0xf8d92452, 0x7f97f932, 0xf8cca79e,
+ 0x7f968e07, 0xf8c02b31, 0x7f952069, 0xf8b3af0c,
+ 0x7f93b058, 0xf8a7332e, 0x7f923dd2, 0xf89ab799,
+ 0x7f90c8da, 0xf88e3c4d, 0x7f8f516e, 0xf881c14b,
+ 0x7f8dd78f, 0xf8754692, 0x7f8c5b3d, 0xf868cc24,
+ 0x7f8adc77, 0xf85c5201, 0x7f895b3e, 0xf84fd829,
+ 0x7f87d792, 0xf8435e9d, 0x7f865174, 0xf836e55d,
+ 0x7f84c8e2, 0xf82a6c6a, 0x7f833ddd, 0xf81df3c5,
+ 0x7f81b065, 0xf8117b6d, 0x7f80207b, 0xf8050364,
+ 0x7f7e8e1e, 0xf7f88ba9, 0x7f7cf94e, 0xf7ec143e,
+ 0x7f7b620c, 0xf7df9d22, 0x7f79c857, 0xf7d32657,
+ 0x7f782c30, 0xf7c6afdc, 0x7f768d96, 0xf7ba39b3,
+ 0x7f74ec8a, 0xf7adc3db, 0x7f73490b, 0xf7a14e55,
+ 0x7f71a31b, 0xf794d922, 0x7f6ffab8, 0xf7886442,
+ 0x7f6e4fe3, 0xf77befb5, 0x7f6ca29c, 0xf76f7b7d,
+ 0x7f6af2e3, 0xf7630799, 0x7f6940b8, 0xf756940a,
+ 0x7f678c1c, 0xf74a20d0, 0x7f65d50d, 0xf73daded,
+ 0x7f641b8d, 0xf7313b60, 0x7f625f9b, 0xf724c92a,
+ 0x7f60a138, 0xf718574b, 0x7f5ee063, 0xf70be5c4,
+ 0x7f5d1d1d, 0xf6ff7496, 0x7f5b5765, 0xf6f303c0,
+ 0x7f598f3c, 0xf6e69344, 0x7f57c4a2, 0xf6da2321,
+ 0x7f55f796, 0xf6cdb359, 0x7f54281a, 0xf6c143ec,
+ 0x7f52562c, 0xf6b4d4d9, 0x7f5081cd, 0xf6a86623,
+ 0x7f4eaafe, 0xf69bf7c9, 0x7f4cd1be, 0xf68f89cb,
+ 0x7f4af60d, 0xf6831c2b, 0x7f4917eb, 0xf676aee8,
+ 0x7f473759, 0xf66a4203, 0x7f455456, 0xf65dd57d,
+ 0x7f436ee3, 0xf6516956, 0x7f4186ff, 0xf644fd8f,
+ 0x7f3f9cab, 0xf6389228, 0x7f3dafe7, 0xf62c2721,
+ 0x7f3bc0b3, 0xf61fbc7b, 0x7f39cf0e, 0xf6135237,
+ 0x7f37dafa, 0xf606e854, 0x7f35e476, 0xf5fa7ed4,
+ 0x7f33eb81, 0xf5ee15b7, 0x7f31f01d, 0xf5e1acfd,
+ 0x7f2ff24a, 0xf5d544a7, 0x7f2df206, 0xf5c8dcb6,
+ 0x7f2bef53, 0xf5bc7529, 0x7f29ea31, 0xf5b00e02,
+ 0x7f27e29f, 0xf5a3a740, 0x7f25d89e, 0xf59740e5,
+ 0x7f23cc2e, 0xf58adaf0, 0x7f21bd4e, 0xf57e7563,
+ 0x7f1fabff, 0xf572103d, 0x7f1d9842, 0xf565ab80,
+ 0x7f1b8215, 0xf559472b, 0x7f19697a, 0xf54ce33f,
+ 0x7f174e70, 0xf5407fbd, 0x7f1530f7, 0xf5341ca5,
+ 0x7f13110f, 0xf527b9f7, 0x7f10eeb9, 0xf51b57b5,
+ 0x7f0ec9f5, 0xf50ef5de, 0x7f0ca2c2, 0xf5029473,
+ 0x7f0a7921, 0xf4f63374, 0x7f084d12, 0xf4e9d2e3,
+ 0x7f061e95, 0xf4dd72be, 0x7f03eda9, 0xf4d11308,
+ 0x7f01ba50, 0xf4c4b3c0, 0x7eff8489, 0xf4b854e7,
+ 0x7efd4c54, 0xf4abf67e, 0x7efb11b1, 0xf49f9884,
+ 0x7ef8d4a1, 0xf4933afa, 0x7ef69523, 0xf486dde1,
+ 0x7ef45338, 0xf47a8139, 0x7ef20ee0, 0xf46e2504,
+ 0x7eefc81a, 0xf461c940, 0x7eed7ee7, 0xf4556def,
+ 0x7eeb3347, 0xf4491311, 0x7ee8e53a, 0xf43cb8a7,
+ 0x7ee694c1, 0xf4305eb0, 0x7ee441da, 0xf424052f,
+ 0x7ee1ec87, 0xf417ac22, 0x7edf94c7, 0xf40b538b,
+ 0x7edd3a9a, 0xf3fefb6a, 0x7edade01, 0xf3f2a3bf,
+ 0x7ed87efc, 0xf3e64c8c, 0x7ed61d8a, 0xf3d9f5cf,
+ 0x7ed3b9ad, 0xf3cd9f8b, 0x7ed15363, 0xf3c149bf,
+ 0x7eceeaad, 0xf3b4f46c, 0x7ecc7f8b, 0xf3a89f92,
+ 0x7eca11fe, 0xf39c4b32, 0x7ec7a205, 0xf38ff74d,
+ 0x7ec52fa0, 0xf383a3e2, 0x7ec2bad0, 0xf37750f2,
+ 0x7ec04394, 0xf36afe7e, 0x7ebdc9ed, 0xf35eac86,
+ 0x7ebb4ddb, 0xf3525b0b, 0x7eb8cf5d, 0xf3460a0d,
+ 0x7eb64e75, 0xf339b98d, 0x7eb3cb21, 0xf32d698a,
+ 0x7eb14563, 0xf3211a07, 0x7eaebd3a, 0xf314cb02,
+ 0x7eac32a6, 0xf3087c7d, 0x7ea9a5a8, 0xf2fc2e77,
+ 0x7ea7163f, 0xf2efe0f2, 0x7ea4846c, 0xf2e393ef,
+ 0x7ea1f02f, 0xf2d7476c, 0x7e9f5988, 0xf2cafb6b,
+ 0x7e9cc076, 0xf2beafed, 0x7e9a24fb, 0xf2b264f2,
+ 0x7e978715, 0xf2a61a7a, 0x7e94e6c6, 0xf299d085,
+ 0x7e92440d, 0xf28d8715, 0x7e8f9eeb, 0xf2813e2a,
+ 0x7e8cf75f, 0xf274f5c3, 0x7e8a4d6a, 0xf268ade3,
+ 0x7e87a10c, 0xf25c6688, 0x7e84f245, 0xf2501fb5,
+ 0x7e824114, 0xf243d968, 0x7e7f8d7b, 0xf23793a3,
+ 0x7e7cd778, 0xf22b4e66, 0x7e7a1f0d, 0xf21f09b1,
+ 0x7e77643a, 0xf212c585, 0x7e74a6fd, 0xf20681e3,
+ 0x7e71e759, 0xf1fa3ecb, 0x7e6f254c, 0xf1edfc3d,
+ 0x7e6c60d7, 0xf1e1ba3a, 0x7e6999fa, 0xf1d578c2,
+ 0x7e66d0b4, 0xf1c937d6, 0x7e640507, 0xf1bcf777,
+ 0x7e6136f3, 0xf1b0b7a4, 0x7e5e6676, 0xf1a4785e,
+ 0x7e5b9392, 0xf19839a6, 0x7e58be47, 0xf18bfb7d,
+ 0x7e55e694, 0xf17fbde2, 0x7e530c7a, 0xf17380d6,
+ 0x7e502ff9, 0xf1674459, 0x7e4d5110, 0xf15b086d,
+ 0x7e4a6fc1, 0xf14ecd11, 0x7e478c0b, 0xf1429247,
+ 0x7e44a5ef, 0xf136580d, 0x7e41bd6c, 0xf12a1e66,
+ 0x7e3ed282, 0xf11de551, 0x7e3be532, 0xf111accf,
+ 0x7e38f57c, 0xf10574e0, 0x7e360360, 0xf0f93d86,
+ 0x7e330ede, 0xf0ed06bf, 0x7e3017f6, 0xf0e0d08d,
+ 0x7e2d1ea8, 0xf0d49af1, 0x7e2a22f4, 0xf0c865ea,
+ 0x7e2724db, 0xf0bc317a, 0x7e24245d, 0xf0affda0,
+ 0x7e212179, 0xf0a3ca5d, 0x7e1e1c30, 0xf09797b2,
+ 0x7e1b1482, 0xf08b659f, 0x7e180a6f, 0xf07f3424,
+ 0x7e14fdf7, 0xf0730342, 0x7e11ef1b, 0xf066d2fa,
+ 0x7e0eddd9, 0xf05aa34c, 0x7e0bca34, 0xf04e7438,
+ 0x7e08b42a, 0xf04245c0, 0x7e059bbb, 0xf03617e2,
+ 0x7e0280e9, 0xf029eaa1, 0x7dff63b2, 0xf01dbdfb,
+ 0x7dfc4418, 0xf01191f3, 0x7df9221a, 0xf0056687,
+ 0x7df5fdb8, 0xeff93bba, 0x7df2d6f3, 0xefed118a,
+ 0x7defadca, 0xefe0e7f9, 0x7dec823e, 0xefd4bf08,
+ 0x7de9544f, 0xefc896b5, 0x7de623fd, 0xefbc6f03,
+ 0x7de2f148, 0xefb047f2, 0x7ddfbc30, 0xefa42181,
+ 0x7ddc84b5, 0xef97fbb2, 0x7dd94ad8, 0xef8bd685,
+ 0x7dd60e99, 0xef7fb1fa, 0x7dd2cff7, 0xef738e12,
+ 0x7dcf8ef3, 0xef676ace, 0x7dcc4b8d, 0xef5b482d,
+ 0x7dc905c5, 0xef4f2630, 0x7dc5bd9b, 0xef4304d8,
+ 0x7dc2730f, 0xef36e426, 0x7dbf2622, 0xef2ac419,
+ 0x7dbbd6d4, 0xef1ea4b2, 0x7db88524, 0xef1285f2,
+ 0x7db53113, 0xef0667d9, 0x7db1daa2, 0xeefa4a67,
+ 0x7dae81cf, 0xeeee2d9d, 0x7dab269b, 0xeee2117c,
+ 0x7da7c907, 0xeed5f604, 0x7da46912, 0xeec9db35,
+ 0x7da106bd, 0xeebdc110, 0x7d9da208, 0xeeb1a796,
+ 0x7d9a3af2, 0xeea58ec6, 0x7d96d17d, 0xee9976a1,
+ 0x7d9365a8, 0xee8d5f29, 0x7d8ff772, 0xee81485c,
+ 0x7d8c86de, 0xee75323c, 0x7d8913ea, 0xee691cc9,
+ 0x7d859e96, 0xee5d0804, 0x7d8226e4, 0xee50f3ed,
+ 0x7d7eacd2, 0xee44e084, 0x7d7b3061, 0xee38cdcb,
+ 0x7d77b192, 0xee2cbbc1, 0x7d743064, 0xee20aa67,
+ 0x7d70acd7, 0xee1499bd, 0x7d6d26ec, 0xee0889c4,
+ 0x7d699ea3, 0xedfc7a7c, 0x7d6613fb, 0xedf06be6,
+ 0x7d6286f6, 0xede45e03, 0x7d5ef793, 0xedd850d2,
+ 0x7d5b65d2, 0xedcc4454, 0x7d57d1b3, 0xedc0388a,
+ 0x7d543b37, 0xedb42d74, 0x7d50a25e, 0xeda82313,
+ 0x7d4d0728, 0xed9c1967, 0x7d496994, 0xed901070,
+ 0x7d45c9a4, 0xed84082f, 0x7d422757, 0xed7800a5,
+ 0x7d3e82ae, 0xed6bf9d1, 0x7d3adba7, 0xed5ff3b5,
+ 0x7d373245, 0xed53ee51, 0x7d338687, 0xed47e9a5,
+ 0x7d2fd86c, 0xed3be5b1, 0x7d2c27f6, 0xed2fe277,
+ 0x7d287523, 0xed23dff7, 0x7d24bff6, 0xed17de31,
+ 0x7d21086c, 0xed0bdd25, 0x7d1d4e88, 0xecffdcd4,
+ 0x7d199248, 0xecf3dd3f, 0x7d15d3ad, 0xece7de66,
+ 0x7d1212b7, 0xecdbe04a, 0x7d0e4f67, 0xeccfe2ea,
+ 0x7d0a89bc, 0xecc3e648, 0x7d06c1b6, 0xecb7ea63,
+ 0x7d02f757, 0xecabef3d, 0x7cff2a9d, 0xec9ff4d6,
+ 0x7cfb5b89, 0xec93fb2e, 0x7cf78a1b, 0xec880245,
+ 0x7cf3b653, 0xec7c0a1d, 0x7cefe032, 0xec7012b5,
+ 0x7cec07b8, 0xec641c0e, 0x7ce82ce4, 0xec582629,
+ 0x7ce44fb7, 0xec4c3106, 0x7ce07031, 0xec403ca5,
+ 0x7cdc8e52, 0xec344908, 0x7cd8aa1b, 0xec28562d,
+ 0x7cd4c38b, 0xec1c6417, 0x7cd0daa2, 0xec1072c4,
+ 0x7cccef62, 0xec048237, 0x7cc901c9, 0xebf8926f,
+ 0x7cc511d9, 0xebeca36c, 0x7cc11f90, 0xebe0b52f,
+ 0x7cbd2af0, 0xebd4c7ba, 0x7cb933f9, 0xebc8db0b,
+ 0x7cb53aaa, 0xebbcef23, 0x7cb13f04, 0xebb10404,
+ 0x7cad4107, 0xeba519ad, 0x7ca940b3, 0xeb99301f,
+ 0x7ca53e09, 0xeb8d475b, 0x7ca13908, 0xeb815f60,
+ 0x7c9d31b0, 0xeb75782f, 0x7c992803, 0xeb6991ca,
+ 0x7c951bff, 0xeb5dac2f, 0x7c910da5, 0xeb51c760,
+ 0x7c8cfcf6, 0xeb45e35d, 0x7c88e9f1, 0xeb3a0027,
+ 0x7c84d496, 0xeb2e1dbe, 0x7c80bce7, 0xeb223c22,
+ 0x7c7ca2e2, 0xeb165b54, 0x7c788688, 0xeb0a7b54,
+ 0x7c7467d9, 0xeafe9c24, 0x7c7046d6, 0xeaf2bdc3,
+ 0x7c6c237e, 0xeae6e031, 0x7c67fdd1, 0xeadb0370,
+ 0x7c63d5d1, 0xeacf277f, 0x7c5fab7c, 0xeac34c60,
+ 0x7c5b7ed4, 0xeab77212, 0x7c574fd8, 0xeaab9896,
+ 0x7c531e88, 0xea9fbfed, 0x7c4eeae5, 0xea93e817,
+ 0x7c4ab4ef, 0xea881114, 0x7c467ca6, 0xea7c3ae5,
+ 0x7c42420a, 0xea70658a, 0x7c3e051b, 0xea649105,
+ 0x7c39c5da, 0xea58bd54, 0x7c358446, 0xea4cea79,
+ 0x7c314060, 0xea411874, 0x7c2cfa28, 0xea354746,
+ 0x7c28b19e, 0xea2976ef, 0x7c2466c2, 0xea1da770,
+ 0x7c201994, 0xea11d8c8, 0x7c1bca16, 0xea060af9,
+ 0x7c177845, 0xe9fa3e03, 0x7c132424, 0xe9ee71e6,
+ 0x7c0ecdb2, 0xe9e2a6a3, 0x7c0a74f0, 0xe9d6dc3b,
+ 0x7c0619dc, 0xe9cb12ad, 0x7c01bc78, 0xe9bf49fa,
+ 0x7bfd5cc4, 0xe9b38223, 0x7bf8fac0, 0xe9a7bb28,
+ 0x7bf4966c, 0xe99bf509, 0x7bf02fc9, 0xe9902fc7,
+ 0x7bebc6d5, 0xe9846b63, 0x7be75b93, 0xe978a7dd,
+ 0x7be2ee01, 0xe96ce535, 0x7bde7e20, 0xe961236c,
+ 0x7bda0bf0, 0xe9556282, 0x7bd59771, 0xe949a278,
+ 0x7bd120a4, 0xe93de34e, 0x7bcca789, 0xe9322505,
+ 0x7bc82c1f, 0xe926679c, 0x7bc3ae67, 0xe91aab16,
+ 0x7bbf2e62, 0xe90eef71, 0x7bbaac0e, 0xe90334af,
+ 0x7bb6276e, 0xe8f77acf, 0x7bb1a080, 0xe8ebc1d3,
+ 0x7bad1744, 0xe8e009ba, 0x7ba88bbc, 0xe8d45286,
+ 0x7ba3fde7, 0xe8c89c37, 0x7b9f6dc5, 0xe8bce6cd,
+ 0x7b9adb57, 0xe8b13248, 0x7b96469d, 0xe8a57ea9,
+ 0x7b91af97, 0xe899cbf1, 0x7b8d1644, 0xe88e1a20,
+ 0x7b887aa6, 0xe8826936, 0x7b83dcbc, 0xe876b934,
+ 0x7b7f3c87, 0xe86b0a1a, 0x7b7a9a07, 0xe85f5be9,
+ 0x7b75f53c, 0xe853aea1, 0x7b714e25, 0xe8480243,
+ 0x7b6ca4c4, 0xe83c56cf, 0x7b67f919, 0xe830ac45,
+ 0x7b634b23, 0xe82502a7, 0x7b5e9ae4, 0xe81959f4,
+ 0x7b59e85a, 0xe80db22d, 0x7b553386, 0xe8020b52,
+ 0x7b507c69, 0xe7f66564, 0x7b4bc303, 0xe7eac063,
+ 0x7b470753, 0xe7df1c50, 0x7b42495a, 0xe7d3792b,
+ 0x7b3d8918, 0xe7c7d6f4, 0x7b38c68e, 0xe7bc35ad,
+ 0x7b3401bb, 0xe7b09555, 0x7b2f3aa0, 0xe7a4f5ed,
+ 0x7b2a713d, 0xe7995776, 0x7b25a591, 0xe78db9ef,
+ 0x7b20d79e, 0xe7821d59, 0x7b1c0764, 0xe77681b6,
+ 0x7b1734e2, 0xe76ae704, 0x7b126019, 0xe75f4d45,
+ 0x7b0d8909, 0xe753b479, 0x7b08afb2, 0xe7481ca1,
+ 0x7b03d414, 0xe73c85bc, 0x7afef630, 0xe730efcc,
+ 0x7afa1605, 0xe7255ad1, 0x7af53395, 0xe719c6cb,
+ 0x7af04edf, 0xe70e33bb, 0x7aeb67e3, 0xe702a1a1,
+ 0x7ae67ea1, 0xe6f7107e, 0x7ae1931a, 0xe6eb8052,
+ 0x7adca54e, 0xe6dff11d, 0x7ad7b53d, 0xe6d462e1,
+ 0x7ad2c2e8, 0xe6c8d59c, 0x7acdce4d, 0xe6bd4951,
+ 0x7ac8d76f, 0xe6b1bdff, 0x7ac3de4c, 0xe6a633a6,
+ 0x7abee2e5, 0xe69aaa48, 0x7ab9e53a, 0xe68f21e5,
+ 0x7ab4e54c, 0xe6839a7c, 0x7aafe31b, 0xe6781410,
+ 0x7aaadea6, 0xe66c8e9f, 0x7aa5d7ee, 0xe6610a2a,
+ 0x7aa0cef3, 0xe65586b3, 0x7a9bc3b6, 0xe64a0438,
+ 0x7a96b636, 0xe63e82bc, 0x7a91a674, 0xe633023e,
+ 0x7a8c9470, 0xe62782be, 0x7a87802a, 0xe61c043d,
+ 0x7a8269a3, 0xe61086bc, 0x7a7d50da, 0xe6050a3b,
+ 0x7a7835cf, 0xe5f98ebb, 0x7a731884, 0xe5ee143b,
+ 0x7a6df8f8, 0xe5e29abc, 0x7a68d72b, 0xe5d72240,
+ 0x7a63b31d, 0xe5cbaac5, 0x7a5e8cd0, 0xe5c0344d,
+ 0x7a596442, 0xe5b4bed8, 0x7a543974, 0xe5a94a67,
+ 0x7a4f0c67, 0xe59dd6f9, 0x7a49dd1a, 0xe5926490,
+ 0x7a44ab8e, 0xe586f32c, 0x7a3f77c3, 0xe57b82cd,
+ 0x7a3a41b9, 0xe5701374, 0x7a350970, 0xe564a521,
+ 0x7a2fcee8, 0xe55937d5, 0x7a2a9223, 0xe54dcb8f,
+ 0x7a25531f, 0xe5426051, 0x7a2011de, 0xe536f61b,
+ 0x7a1ace5f, 0xe52b8cee, 0x7a1588a2, 0xe52024c9,
+ 0x7a1040a8, 0xe514bdad, 0x7a0af671, 0xe509579b,
+ 0x7a05a9fd, 0xe4fdf294, 0x7a005b4d, 0xe4f28e96,
+ 0x79fb0a60, 0xe4e72ba4, 0x79f5b737, 0xe4dbc9bd,
+ 0x79f061d2, 0xe4d068e2, 0x79eb0a31, 0xe4c50914,
+ 0x79e5b054, 0xe4b9aa52, 0x79e0543c, 0xe4ae4c9d,
+ 0x79daf5e8, 0xe4a2eff6, 0x79d5955a, 0xe497945d,
+ 0x79d03291, 0xe48c39d3, 0x79cacd8d, 0xe480e057,
+ 0x79c5664f, 0xe47587eb, 0x79bffcd7, 0xe46a308f,
+ 0x79ba9125, 0xe45eda43, 0x79b52339, 0xe4538507,
+ 0x79afb313, 0xe44830dd, 0x79aa40b4, 0xe43cddc4,
+ 0x79a4cc1c, 0xe4318bbe, 0x799f554b, 0xe4263ac9,
+ 0x7999dc42, 0xe41aeae8, 0x799460ff, 0xe40f9c1a,
+ 0x798ee385, 0xe4044e60, 0x798963d2, 0xe3f901ba,
+ 0x7983e1e8, 0xe3edb628, 0x797e5dc6, 0xe3e26bac,
+ 0x7978d76c, 0xe3d72245, 0x79734edc, 0xe3cbd9f4,
+ 0x796dc414, 0xe3c092b9, 0x79683715, 0xe3b54c95,
+ 0x7962a7e0, 0xe3aa0788, 0x795d1675, 0xe39ec393,
+ 0x795782d3, 0xe39380b6, 0x7951ecfc, 0xe3883ef2,
+ 0x794c54ee, 0xe37cfe47, 0x7946baac, 0xe371beb5,
+ 0x79411e33, 0xe366803c, 0x793b7f86, 0xe35b42df,
+ 0x7935dea4, 0xe350069b, 0x79303b8e, 0xe344cb73,
+ 0x792a9642, 0xe3399167, 0x7924eec3, 0xe32e5876,
+ 0x791f4510, 0xe32320a2, 0x79199929, 0xe317e9eb,
+ 0x7913eb0e, 0xe30cb451, 0x790e3ac0, 0xe3017fd5,
+ 0x7908883f, 0xe2f64c77, 0x7902d38b, 0xe2eb1a37,
+ 0x78fd1ca4, 0xe2dfe917, 0x78f7638b, 0xe2d4b916,
+ 0x78f1a840, 0xe2c98a35, 0x78ebeac2, 0xe2be5c74,
+ 0x78e62b13, 0xe2b32fd4, 0x78e06932, 0xe2a80456,
+ 0x78daa520, 0xe29cd9f8, 0x78d4dedd, 0xe291b0bd,
+ 0x78cf1669, 0xe28688a4, 0x78c94bc4, 0xe27b61af,
+ 0x78c37eef, 0xe2703bdc, 0x78bdafea, 0xe265172e,
+ 0x78b7deb4, 0xe259f3a3, 0x78b20b4f, 0xe24ed13d,
+ 0x78ac35ba, 0xe243affc, 0x78a65df6, 0xe2388fe1,
+ 0x78a08402, 0xe22d70eb, 0x789aa7e0, 0xe222531c,
+ 0x7894c98f, 0xe2173674, 0x788ee910, 0xe20c1af3,
+ 0x78890663, 0xe2010099, 0x78832187, 0xe1f5e768,
+ 0x787d3a7e, 0xe1eacf5f, 0x78775147, 0xe1dfb87f,
+ 0x787165e3, 0xe1d4a2c8, 0x786b7852, 0xe1c98e3b,
+ 0x78658894, 0xe1be7ad8, 0x785f96a9, 0xe1b368a0,
+ 0x7859a292, 0xe1a85793, 0x7853ac4f, 0xe19d47b1,
+ 0x784db3e0, 0xe19238fb, 0x7847b946, 0xe1872b72,
+ 0x7841bc7f, 0xe17c1f15, 0x783bbd8e, 0xe17113e5,
+ 0x7835bc71, 0xe16609e3, 0x782fb92a, 0xe15b0110,
+ 0x7829b3b9, 0xe14ff96a, 0x7823ac1d, 0xe144f2f3,
+ 0x781da256, 0xe139edac, 0x78179666, 0xe12ee995,
+ 0x7811884d, 0xe123e6ad, 0x780b780a, 0xe118e4f6,
+ 0x7805659e, 0xe10de470, 0x77ff5109, 0xe102e51c,
+ 0x77f93a4b, 0xe0f7e6f9, 0x77f32165, 0xe0ecea09,
+ 0x77ed0657, 0xe0e1ee4b, 0x77e6e921, 0xe0d6f3c1,
+ 0x77e0c9c3, 0xe0cbfa6a, 0x77daa83d, 0xe0c10247,
+ 0x77d48490, 0xe0b60b58, 0x77ce5ebd, 0xe0ab159e,
+ 0x77c836c2, 0xe0a0211a, 0x77c20ca1, 0xe0952dcb,
+ 0x77bbe05a, 0xe08a3bb2, 0x77b5b1ec, 0xe07f4acf,
+ 0x77af8159, 0xe0745b24, 0x77a94ea0, 0xe0696cb0,
+ 0x77a319c2, 0xe05e7f74, 0x779ce2be, 0xe053936f,
+ 0x7796a996, 0xe048a8a4, 0x77906e49, 0xe03dbf11,
+ 0x778a30d8, 0xe032d6b8, 0x7783f143, 0xe027ef99,
+ 0x777daf89, 0xe01d09b4, 0x77776bac, 0xe012250a,
+ 0x777125ac, 0xe007419b, 0x776add88, 0xdffc5f67,
+ 0x77649341, 0xdff17e70, 0x775e46d8, 0xdfe69eb4,
+ 0x7757f84c, 0xdfdbc036, 0x7751a79e, 0xdfd0e2f5,
+ 0x774b54ce, 0xdfc606f1, 0x7744ffdd, 0xdfbb2c2c,
+ 0x773ea8ca, 0xdfb052a5, 0x77384f95, 0xdfa57a5d,
+ 0x7731f440, 0xdf9aa354, 0x772b96ca, 0xdf8fcd8b,
+ 0x77253733, 0xdf84f902, 0x771ed57c, 0xdf7a25ba,
+ 0x771871a5, 0xdf6f53b3, 0x77120bae, 0xdf6482ed,
+ 0x770ba398, 0xdf59b369, 0x77053962, 0xdf4ee527,
+ 0x76fecd0e, 0xdf441828, 0x76f85e9a, 0xdf394c6b,
+ 0x76f1ee09, 0xdf2e81f3, 0x76eb7b58, 0xdf23b8be,
+ 0x76e5068a, 0xdf18f0ce, 0x76de8f9e, 0xdf0e2a22,
+ 0x76d81695, 0xdf0364bc, 0x76d19b6e, 0xdef8a09b,
+ 0x76cb1e2a, 0xdeedddc0, 0x76c49ec9, 0xdee31c2b,
+ 0x76be1d4c, 0xded85bdd, 0x76b799b3, 0xdecd9cd7,
+ 0x76b113fd, 0xdec2df18, 0x76aa8c2c, 0xdeb822a1,
+ 0x76a4023f, 0xdead6773, 0x769d7637, 0xdea2ad8d,
+ 0x7696e814, 0xde97f4f1, 0x769057d6, 0xde8d3d9e,
+ 0x7689c57d, 0xde828796, 0x7683310b, 0xde77d2d8,
+ 0x767c9a7e, 0xde6d1f65, 0x767601d7, 0xde626d3e,
+ 0x766f6717, 0xde57bc62, 0x7668ca3e, 0xde4d0cd2,
+ 0x76622b4c, 0xde425e8f, 0x765b8a41, 0xde37b199,
+ 0x7654e71d, 0xde2d05f1, 0x764e41e2, 0xde225b96,
+ 0x76479a8e, 0xde17b28a, 0x7640f123, 0xde0d0acc,
+ 0x763a45a0, 0xde02645d, 0x76339806, 0xddf7bf3e,
+ 0x762ce855, 0xdded1b6e, 0x7626368d, 0xdde278ef,
+ 0x761f82af, 0xddd7d7c1, 0x7618ccba, 0xddcd37e4,
+ 0x761214b0, 0xddc29958, 0x760b5a90, 0xddb7fc1e,
+ 0x76049e5b, 0xddad6036, 0x75fde011, 0xdda2c5a2,
+ 0x75f71fb1, 0xdd982c60, 0x75f05d3d, 0xdd8d9472,
+ 0x75e998b5, 0xdd82fdd8, 0x75e2d219, 0xdd786892,
+ 0x75dc0968, 0xdd6dd4a2, 0x75d53ea5, 0xdd634206,
+ 0x75ce71ce, 0xdd58b0c0, 0x75c7a2e3, 0xdd4e20d0,
+ 0x75c0d1e7, 0xdd439236, 0x75b9fed7, 0xdd3904f4,
+ 0x75b329b5, 0xdd2e7908, 0x75ac5282, 0xdd23ee74,
+ 0x75a5793c, 0xdd196538, 0x759e9de5, 0xdd0edd55,
+ 0x7597c07d, 0xdd0456ca, 0x7590e104, 0xdcf9d199,
+ 0x7589ff7a, 0xdcef4dc2, 0x75831be0, 0xdce4cb44,
+ 0x757c3636, 0xdcda4a21, 0x75754e7c, 0xdccfca59,
+ 0x756e64b2, 0xdcc54bec, 0x756778d9, 0xdcbacedb,
+ 0x75608af1, 0xdcb05326, 0x75599afa, 0xdca5d8cd,
+ 0x7552a8f4, 0xdc9b5fd2, 0x754bb4e1, 0xdc90e834,
+ 0x7544bebf, 0xdc8671f3, 0x753dc68f, 0xdc7bfd11,
+ 0x7536cc52, 0xdc71898d, 0x752fd008, 0xdc671768,
+ 0x7528d1b1, 0xdc5ca6a2, 0x7521d14d, 0xdc52373c,
+ 0x751acedd, 0xdc47c936, 0x7513ca60, 0xdc3d5c91,
+ 0x750cc3d8, 0xdc32f14d, 0x7505bb44, 0xdc28876a,
+ 0x74feb0a5, 0xdc1e1ee9, 0x74f7a3fb, 0xdc13b7c9,
+ 0x74f09546, 0xdc09520d, 0x74e98487, 0xdbfeedb3,
+ 0x74e271bd, 0xdbf48abd, 0x74db5cea, 0xdbea292b,
+ 0x74d4460c, 0xdbdfc8fc, 0x74cd2d26, 0xdbd56a32,
+ 0x74c61236, 0xdbcb0cce, 0x74bef53d, 0xdbc0b0ce,
+ 0x74b7d63c, 0xdbb65634, 0x74b0b533, 0xdbabfd01,
+ 0x74a99221, 0xdba1a534, 0x74a26d08, 0xdb974ece,
+ 0x749b45e7, 0xdb8cf9cf, 0x74941cbf, 0xdb82a638,
+ 0x748cf190, 0xdb785409, 0x7485c45b, 0xdb6e0342,
+ 0x747e951f, 0xdb63b3e5, 0x747763dd, 0xdb5965f1,
+ 0x74703095, 0xdb4f1967, 0x7468fb47, 0xdb44ce46,
+ 0x7461c3f5, 0xdb3a8491, 0x745a8a9d, 0xdb303c46,
+ 0x74534f41, 0xdb25f566, 0x744c11e0, 0xdb1baff2,
+ 0x7444d27b, 0xdb116beb, 0x743d9112, 0xdb072950,
+ 0x74364da6, 0xdafce821, 0x742f0836, 0xdaf2a860,
+ 0x7427c0c3, 0xdae86a0d, 0x7420774d, 0xdade2d28,
+ 0x74192bd5, 0xdad3f1b1, 0x7411de5b, 0xdac9b7a9,
+ 0x740a8edf, 0xdabf7f11, 0x74033d61, 0xdab547e8,
+ 0x73fbe9e2, 0xdaab122f, 0x73f49462, 0xdaa0dde7,
+ 0x73ed3ce1, 0xda96ab0f, 0x73e5e360, 0xda8c79a9,
+ 0x73de87de, 0xda8249b4, 0x73d72a5d, 0xda781b31,
+ 0x73cfcadc, 0xda6dee21, 0x73c8695b, 0xda63c284,
+ 0x73c105db, 0xda599859, 0x73b9a05d, 0xda4f6fa3,
+ 0x73b238e0, 0xda454860, 0x73aacf65, 0xda3b2292,
+ 0x73a363ec, 0xda30fe38, 0x739bf675, 0xda26db54,
+ 0x73948701, 0xda1cb9e5, 0x738d1590, 0xda1299ec,
+ 0x7385a222, 0xda087b69, 0x737e2cb7, 0xd9fe5e5e,
+ 0x7376b551, 0xd9f442c9, 0x736f3bee, 0xd9ea28ac,
+ 0x7367c090, 0xd9e01006, 0x73604336, 0xd9d5f8d9,
+ 0x7358c3e2, 0xd9cbe325, 0x73514292, 0xd9c1cee9,
+ 0x7349bf48, 0xd9b7bc27, 0x73423a04, 0xd9adaadf,
+ 0x733ab2c6, 0xd9a39b11, 0x7333298f, 0xd9998cbe,
+ 0x732b9e5e, 0xd98f7fe6, 0x73241134, 0xd9857489,
+ 0x731c8211, 0xd97b6aa8, 0x7314f0f6, 0xd9716243,
+ 0x730d5de3, 0xd9675b5a, 0x7305c8d7, 0xd95d55ef,
+ 0x72fe31d5, 0xd9535201, 0x72f698db, 0xd9494f90,
+ 0x72eefdea, 0xd93f4e9e, 0x72e76102, 0xd9354f2a,
+ 0x72dfc224, 0xd92b5135, 0x72d82150, 0xd92154bf,
+ 0x72d07e85, 0xd91759c9, 0x72c8d9c6, 0xd90d6053,
+ 0x72c13311, 0xd903685d, 0x72b98a67, 0xd8f971e8,
+ 0x72b1dfc9, 0xd8ef7cf4, 0x72aa3336, 0xd8e58982,
+ 0x72a284b0, 0xd8db9792, 0x729ad435, 0xd8d1a724,
+ 0x729321c7, 0xd8c7b838, 0x728b6d66, 0xd8bdcad0,
+ 0x7283b712, 0xd8b3deeb, 0x727bfecc, 0xd8a9f48a,
+ 0x72744493, 0xd8a00bae, 0x726c8868, 0xd8962456,
+ 0x7264ca4c, 0xd88c3e83, 0x725d0a3e, 0xd8825a35,
+ 0x72554840, 0xd878776d, 0x724d8450, 0xd86e962b,
+ 0x7245be70, 0xd864b670, 0x723df6a0, 0xd85ad83c,
+ 0x72362ce0, 0xd850fb8e, 0x722e6130, 0xd8472069,
+ 0x72269391, 0xd83d46cc, 0x721ec403, 0xd8336eb7,
+ 0x7216f287, 0xd829982b, 0x720f1f1c, 0xd81fc328,
+ 0x720749c3, 0xd815efae, 0x71ff727c, 0xd80c1dbf,
+ 0x71f79948, 0xd8024d59, 0x71efbe27, 0xd7f87e7f,
+ 0x71e7e118, 0xd7eeb130, 0x71e0021e, 0xd7e4e56c,
+ 0x71d82137, 0xd7db1b34, 0x71d03e64, 0xd7d15288,
+ 0x71c859a5, 0xd7c78b68, 0x71c072fb, 0xd7bdc5d6,
+ 0x71b88a66, 0xd7b401d1, 0x71b09fe7, 0xd7aa3f5a,
+ 0x71a8b37c, 0xd7a07e70, 0x71a0c528, 0xd796bf16,
+ 0x7198d4ea, 0xd78d014a, 0x7190e2c3, 0xd783450d,
+ 0x7188eeb2, 0xd7798a60, 0x7180f8b8, 0xd76fd143,
+ 0x717900d6, 0xd76619b6, 0x7171070c, 0xd75c63ba,
+ 0x71690b59, 0xd752af4f, 0x71610dbf, 0xd748fc75,
+ 0x71590e3e, 0xd73f4b2e, 0x71510cd5, 0xd7359b78,
+ 0x71490986, 0xd72bed55, 0x71410450, 0xd72240c5,
+ 0x7138fd35, 0xd71895c9, 0x7130f433, 0xd70eec60,
+ 0x7128e94c, 0xd705448b, 0x7120dc80, 0xd6fb9e4b,
+ 0x7118cdcf, 0xd6f1f99f, 0x7110bd39, 0xd6e85689,
+ 0x7108aabf, 0xd6deb508, 0x71009661, 0xd6d5151d,
+ 0x70f8801f, 0xd6cb76c9, 0x70f067fb, 0xd6c1da0b,
+ 0x70e84df3, 0xd6b83ee4, 0x70e03208, 0xd6aea555,
+ 0x70d8143b, 0xd6a50d5d, 0x70cff48c, 0xd69b76fe,
+ 0x70c7d2fb, 0xd691e237, 0x70bfaf89, 0xd6884f09,
+ 0x70b78a36, 0xd67ebd74, 0x70af6302, 0xd6752d79,
+ 0x70a739ed, 0xd66b9f18, 0x709f0ef8, 0xd6621251,
+ 0x7096e223, 0xd6588725, 0x708eb36f, 0xd64efd94,
+ 0x708682dc, 0xd645759f, 0x707e5069, 0xd63bef46,
+ 0x70761c18, 0xd6326a88, 0x706de5e9, 0xd628e767,
+ 0x7065addb, 0xd61f65e4, 0x705d73f0, 0xd615e5fd,
+ 0x70553828, 0xd60c67b4, 0x704cfa83, 0xd602eb0a,
+ 0x7044bb00, 0xd5f96ffd, 0x703c79a2, 0xd5eff690,
+ 0x70343667, 0xd5e67ec1, 0x702bf151, 0xd5dd0892,
+ 0x7023aa5f, 0xd5d39403, 0x701b6193, 0xd5ca2115,
+ 0x701316eb, 0xd5c0afc6, 0x700aca69, 0xd5b74019,
+ 0x70027c0c, 0xd5add20d, 0x6ffa2bd6, 0xd5a465a3,
+ 0x6ff1d9c7, 0xd59afadb, 0x6fe985de, 0xd59191b5,
+ 0x6fe1301c, 0xd5882a32, 0x6fd8d882, 0xd57ec452,
+ 0x6fd07f0f, 0xd5756016, 0x6fc823c5, 0xd56bfd7d,
+ 0x6fbfc6a3, 0xd5629c89, 0x6fb767aa, 0xd5593d3a,
+ 0x6faf06da, 0xd54fdf8f, 0x6fa6a433, 0xd5468389,
+ 0x6f9e3fb6, 0xd53d292a, 0x6f95d963, 0xd533d070,
+ 0x6f8d713a, 0xd52a795d, 0x6f85073c, 0xd52123f0,
+ 0x6f7c9b69, 0xd517d02b, 0x6f742dc1, 0xd50e7e0d,
+ 0x6f6bbe45, 0xd5052d97, 0x6f634cf5, 0xd4fbdec9,
+ 0x6f5ad9d1, 0xd4f291a4, 0x6f5264da, 0xd4e94627,
+ 0x6f49ee0f, 0xd4dffc54, 0x6f417573, 0xd4d6b42b,
+ 0x6f38fb03, 0xd4cd6dab, 0x6f307ec2, 0xd4c428d6,
+ 0x6f2800af, 0xd4bae5ab, 0x6f1f80ca, 0xd4b1a42c,
+ 0x6f16ff14, 0xd4a86458, 0x6f0e7b8e, 0xd49f2630,
+ 0x6f05f637, 0xd495e9b3, 0x6efd6f10, 0xd48caee4,
+ 0x6ef4e619, 0xd48375c1, 0x6eec5b53, 0xd47a3e4b,
+ 0x6ee3cebe, 0xd4710883, 0x6edb405a, 0xd467d469,
+ 0x6ed2b027, 0xd45ea1fd, 0x6eca1e27, 0xd4557140,
+ 0x6ec18a58, 0xd44c4232, 0x6eb8f4bc, 0xd44314d3,
+ 0x6eb05d53, 0xd439e923, 0x6ea7c41e, 0xd430bf24,
+ 0x6e9f291b, 0xd42796d5, 0x6e968c4d, 0xd41e7037,
+ 0x6e8dedb3, 0xd4154b4a, 0x6e854d4d, 0xd40c280e,
+ 0x6e7cab1c, 0xd4030684, 0x6e740720, 0xd3f9e6ad,
+ 0x6e6b615a, 0xd3f0c887, 0x6e62b9ca, 0xd3e7ac15,
+ 0x6e5a1070, 0xd3de9156, 0x6e51654c, 0xd3d5784a,
+ 0x6e48b860, 0xd3cc60f2, 0x6e4009aa, 0xd3c34b4f,
+ 0x6e37592c, 0xd3ba3760, 0x6e2ea6e6, 0xd3b12526,
+ 0x6e25f2d8, 0xd3a814a2, 0x6e1d3d03, 0xd39f05d3,
+ 0x6e148566, 0xd395f8ba, 0x6e0bcc03, 0xd38ced57,
+ 0x6e0310d9, 0xd383e3ab, 0x6dfa53e9, 0xd37adbb6,
+ 0x6df19534, 0xd371d579, 0x6de8d4b8, 0xd368d0f3,
+ 0x6de01278, 0xd35fce26, 0x6dd74e73, 0xd356cd11,
+ 0x6dce88aa, 0xd34dcdb4, 0x6dc5c11c, 0xd344d011,
+ 0x6dbcf7cb, 0xd33bd427, 0x6db42cb6, 0xd332d9f7,
+ 0x6dab5fdf, 0xd329e181, 0x6da29144, 0xd320eac6,
+ 0x6d99c0e7, 0xd317f5c6, 0x6d90eec8, 0xd30f0280,
+ 0x6d881ae8, 0xd30610f7, 0x6d7f4545, 0xd2fd2129,
+ 0x6d766de2, 0xd2f43318, 0x6d6d94bf, 0xd2eb46c3,
+ 0x6d64b9da, 0xd2e25c2b, 0x6d5bdd36, 0xd2d97350,
+ 0x6d52fed2, 0xd2d08c33, 0x6d4a1eaf, 0xd2c7a6d4,
+ 0x6d413ccd, 0xd2bec333, 0x6d38592c, 0xd2b5e151,
+ 0x6d2f73cd, 0xd2ad012e, 0x6d268cb0, 0xd2a422ca,
+ 0x6d1da3d5, 0xd29b4626, 0x6d14b93d, 0xd2926b41,
+ 0x6d0bcce8, 0xd289921e, 0x6d02ded7, 0xd280babb,
+ 0x6cf9ef09, 0xd277e518, 0x6cf0fd80, 0xd26f1138,
+ 0x6ce80a3a, 0xd2663f19, 0x6cdf153a, 0xd25d6ebc,
+ 0x6cd61e7f, 0xd254a021, 0x6ccd2609, 0xd24bd34a,
+ 0x6cc42bd9, 0xd2430835, 0x6cbb2fef, 0xd23a3ee4,
+ 0x6cb2324c, 0xd2317756, 0x6ca932ef, 0xd228b18d,
+ 0x6ca031da, 0xd21fed88, 0x6c972f0d, 0xd2172b48,
+ 0x6c8e2a87, 0xd20e6acc, 0x6c85244a, 0xd205ac17,
+ 0x6c7c1c55, 0xd1fcef27, 0x6c7312a9, 0xd1f433fd,
+ 0x6c6a0746, 0xd1eb7a9a, 0x6c60fa2d, 0xd1e2c2fd,
+ 0x6c57eb5e, 0xd1da0d28, 0x6c4edada, 0xd1d1591a,
+ 0x6c45c8a0, 0xd1c8a6d4, 0x6c3cb4b1, 0xd1bff656,
+ 0x6c339f0e, 0xd1b747a0, 0x6c2a87b6, 0xd1ae9ab4,
+ 0x6c216eaa, 0xd1a5ef90, 0x6c1853eb, 0xd19d4636,
+ 0x6c0f3779, 0xd1949ea6, 0x6c061953, 0xd18bf8e0,
+ 0x6bfcf97c, 0xd18354e4, 0x6bf3d7f2, 0xd17ab2b3,
+ 0x6beab4b6, 0xd172124d, 0x6be18fc9, 0xd16973b3,
+ 0x6bd8692b, 0xd160d6e5, 0x6bcf40dc, 0xd1583be2,
+ 0x6bc616dd, 0xd14fa2ad, 0x6bbceb2d, 0xd1470b44,
+ 0x6bb3bdce, 0xd13e75a8, 0x6baa8ec0, 0xd135e1d9,
+ 0x6ba15e03, 0xd12d4fd9, 0x6b982b97, 0xd124bfa6,
+ 0x6b8ef77d, 0xd11c3142, 0x6b85c1b5, 0xd113a4ad,
+ 0x6b7c8a3f, 0xd10b19e7, 0x6b73511c, 0xd10290f0,
+ 0x6b6a164d, 0xd0fa09c9, 0x6b60d9d0, 0xd0f18472,
+ 0x6b579ba8, 0xd0e900ec, 0x6b4e5bd4, 0xd0e07f36,
+ 0x6b451a55, 0xd0d7ff51, 0x6b3bd72a, 0xd0cf813e,
+ 0x6b329255, 0xd0c704fd, 0x6b294bd5, 0xd0be8a8d,
+ 0x6b2003ac, 0xd0b611f1, 0x6b16b9d9, 0xd0ad9b26,
+ 0x6b0d6e5c, 0xd0a5262f, 0x6b042137, 0xd09cb30b,
+ 0x6afad269, 0xd09441bb, 0x6af181f3, 0xd08bd23f,
+ 0x6ae82fd5, 0xd0836497, 0x6adedc10, 0xd07af8c4,
+ 0x6ad586a3, 0xd0728ec6, 0x6acc2f90, 0xd06a269d,
+ 0x6ac2d6d6, 0xd061c04a, 0x6ab97c77, 0xd0595bcd,
+ 0x6ab02071, 0xd050f926, 0x6aa6c2c6, 0xd0489856,
+ 0x6a9d6377, 0xd040395d, 0x6a940283, 0xd037dc3b,
+ 0x6a8a9fea, 0xd02f80f1, 0x6a813bae, 0xd027277e,
+ 0x6a77d5ce, 0xd01ecfe4, 0x6a6e6e4b, 0xd0167a22,
+ 0x6a650525, 0xd00e2639, 0x6a5b9a5d, 0xd005d42a,
+ 0x6a522df3, 0xcffd83f4, 0x6a48bfe7, 0xcff53597,
+ 0x6a3f503a, 0xcfece915, 0x6a35deeb, 0xcfe49e6d,
+ 0x6a2c6bfd, 0xcfdc55a1, 0x6a22f76e, 0xcfd40eaf,
+ 0x6a19813f, 0xcfcbc999, 0x6a100970, 0xcfc3865e,
+ 0x6a069003, 0xcfbb4500, 0x69fd14f6, 0xcfb3057d,
+ 0x69f3984c, 0xcfaac7d8, 0x69ea1a03, 0xcfa28c10,
+ 0x69e09a1c, 0xcf9a5225, 0x69d71899, 0xcf921a17,
+ 0x69cd9578, 0xcf89e3e8, 0x69c410ba, 0xcf81af97,
+ 0x69ba8a61, 0xcf797d24, 0x69b1026c, 0xcf714c91,
+ 0x69a778db, 0xcf691ddd, 0x699dedaf, 0xcf60f108,
+ 0x699460e8, 0xcf58c613, 0x698ad287, 0xcf509cfe,
+ 0x6981428c, 0xcf4875ca, 0x6977b0f7, 0xcf405077,
+ 0x696e1dc9, 0xcf382d05, 0x69648902, 0xcf300b74,
+ 0x695af2a3, 0xcf27ebc5, 0x69515aab, 0xcf1fcdf8,
+ 0x6947c11c, 0xcf17b20d, 0x693e25f5, 0xcf0f9805,
+ 0x69348937, 0xcf077fe1, 0x692aeae3, 0xceff699f,
+ 0x69214af8, 0xcef75541, 0x6917a977, 0xceef42c7,
+ 0x690e0661, 0xcee73231, 0x690461b5, 0xcedf2380,
+ 0x68fabb75, 0xced716b4, 0x68f113a0, 0xcecf0bcd,
+ 0x68e76a37, 0xcec702cb, 0x68ddbf3b, 0xcebefbb0,
+ 0x68d412ab, 0xceb6f67a, 0x68ca6488, 0xceaef32b,
+ 0x68c0b4d2, 0xcea6f1c2, 0x68b7038b, 0xce9ef241,
+ 0x68ad50b1, 0xce96f4a7, 0x68a39c46, 0xce8ef8f4,
+ 0x6899e64a, 0xce86ff2a, 0x68902ebd, 0xce7f0748,
+ 0x688675a0, 0xce77114e, 0x687cbaf3, 0xce6f1d3d,
+ 0x6872feb6, 0xce672b16, 0x686940ea, 0xce5f3ad8,
+ 0x685f8190, 0xce574c84, 0x6855c0a6, 0xce4f6019,
+ 0x684bfe2f, 0xce47759a, 0x68423a2a, 0xce3f8d05,
+ 0x68387498, 0xce37a65b, 0x682ead78, 0xce2fc19c,
+ 0x6824e4cc, 0xce27dec9, 0x681b1a94, 0xce1ffde2,
+ 0x68114ed0, 0xce181ee8, 0x68078181, 0xce1041d9,
+ 0x67fdb2a7, 0xce0866b8, 0x67f3e241, 0xce008d84,
+ 0x67ea1052, 0xcdf8b63d, 0x67e03cd8, 0xcdf0e0e4,
+ 0x67d667d5, 0xcde90d79, 0x67cc9149, 0xcde13bfd,
+ 0x67c2b934, 0xcdd96c6f, 0x67b8df97, 0xcdd19ed0,
+ 0x67af0472, 0xcdc9d320, 0x67a527c4, 0xcdc20960,
+ 0x679b4990, 0xcdba4190, 0x679169d5, 0xcdb27bb0,
+ 0x67878893, 0xcdaab7c0, 0x677da5cb, 0xcda2f5c2,
+ 0x6773c17d, 0xcd9b35b4, 0x6769dbaa, 0xcd937798,
+ 0x675ff452, 0xcd8bbb6d, 0x67560b76, 0xcd840134,
+ 0x674c2115, 0xcd7c48ee, 0x67423530, 0xcd74929a,
+ 0x673847c8, 0xcd6cde39, 0x672e58dc, 0xcd652bcb,
+ 0x6724686e, 0xcd5d7b50, 0x671a767e, 0xcd55ccca,
+ 0x6710830c, 0xcd4e2037, 0x67068e18, 0xcd467599,
+ 0x66fc97a3, 0xcd3eccef, 0x66f29fad, 0xcd37263a,
+ 0x66e8a637, 0xcd2f817b, 0x66deab41, 0xcd27deb0,
+ 0x66d4aecb, 0xcd203ddc, 0x66cab0d6, 0xcd189efe,
+ 0x66c0b162, 0xcd110216, 0x66b6b070, 0xcd096725,
+ 0x66acadff, 0xcd01ce2b, 0x66a2aa11, 0xccfa3729,
+ 0x6698a4a6, 0xccf2a21d, 0x668e9dbd, 0xcceb0f0a,
+ 0x66849558, 0xcce37def, 0x667a8b77, 0xccdbeecc,
+ 0x6670801a, 0xccd461a2, 0x66667342, 0xccccd671,
+ 0x665c64ef, 0xccc54d3a, 0x66525521, 0xccbdc5fc,
+ 0x664843d9, 0xccb640b8, 0x663e3117, 0xccaebd6e,
+ 0x66341cdb, 0xcca73c1e, 0x662a0727, 0xcc9fbcca,
+ 0x661feffa, 0xcc983f70, 0x6615d754, 0xcc90c412,
+ 0x660bbd37, 0xcc894aaf, 0x6601a1a2, 0xcc81d349,
+ 0x65f78497, 0xcc7a5dde, 0x65ed6614, 0xcc72ea70,
+ 0x65e3461b, 0xcc6b78ff, 0x65d924ac, 0xcc64098b,
+ 0x65cf01c8, 0xcc5c9c14, 0x65c4dd6e, 0xcc55309b,
+ 0x65bab7a0, 0xcc4dc720, 0x65b0905d, 0xcc465fa3,
+ 0x65a667a7, 0xcc3efa25, 0x659c3d7c, 0xcc3796a5,
+ 0x659211df, 0xcc303524, 0x6587e4cf, 0xcc28d5a3,
+ 0x657db64c, 0xcc217822, 0x65738657, 0xcc1a1ca0,
+ 0x656954f1, 0xcc12c31f, 0x655f2219, 0xcc0b6b9e,
+ 0x6554edd1, 0xcc04161e, 0x654ab818, 0xcbfcc29f,
+ 0x654080ef, 0xcbf57121, 0x65364857, 0xcbee21a5,
+ 0x652c0e4f, 0xcbe6d42b, 0x6521d2d8, 0xcbdf88b3,
+ 0x651795f3, 0xcbd83f3d, 0x650d57a0, 0xcbd0f7ca,
+ 0x650317df, 0xcbc9b25a, 0x64f8d6b0, 0xcbc26eee,
+ 0x64ee9415, 0xcbbb2d85, 0x64e4500e, 0xcbb3ee20,
+ 0x64da0a9a, 0xcbacb0bf, 0x64cfc3ba, 0xcba57563,
+ 0x64c57b6f, 0xcb9e3c0b, 0x64bb31ba, 0xcb9704b9,
+ 0x64b0e699, 0xcb8fcf6b, 0x64a69a0f, 0xcb889c23,
+ 0x649c4c1b, 0xcb816ae1, 0x6491fcbe, 0xcb7a3ba5,
+ 0x6487abf7, 0xcb730e70, 0x647d59c8, 0xcb6be341,
+ 0x64730631, 0xcb64ba19, 0x6468b132, 0xcb5d92f8,
+ 0x645e5acc, 0xcb566ddf, 0x645402ff, 0xcb4f4acd,
+ 0x6449a9cc, 0xcb4829c4, 0x643f4f32, 0xcb410ac3,
+ 0x6434f332, 0xcb39edca, 0x642a95ce, 0xcb32d2da,
+ 0x64203704, 0xcb2bb9f4, 0x6415d6d5, 0xcb24a316,
+ 0x640b7543, 0xcb1d8e43, 0x6401124d, 0xcb167b79,
+ 0x63f6adf3, 0xcb0f6aba, 0x63ec4837, 0xcb085c05,
+ 0x63e1e117, 0xcb014f5b, 0x63d77896, 0xcafa44bc,
+ 0x63cd0eb3, 0xcaf33c28, 0x63c2a36f, 0xcaec35a0,
+ 0x63b836ca, 0xcae53123, 0x63adc8c4, 0xcade2eb3,
+ 0x63a3595e, 0xcad72e4f, 0x6398e898, 0xcad02ff8,
+ 0x638e7673, 0xcac933ae, 0x638402ef, 0xcac23971,
+ 0x63798e0d, 0xcabb4141, 0x636f17cc, 0xcab44b1f,
+ 0x6364a02e, 0xcaad570c, 0x635a2733, 0xcaa66506,
+ 0x634facda, 0xca9f750f, 0x63453125, 0xca988727,
+ 0x633ab414, 0xca919b4e, 0x633035a7, 0xca8ab184,
+ 0x6325b5df, 0xca83c9ca, 0x631b34bc, 0xca7ce420,
+ 0x6310b23e, 0xca760086, 0x63062e67, 0xca6f1efc,
+ 0x62fba936, 0xca683f83, 0x62f122ab, 0xca61621b,
+ 0x62e69ac8, 0xca5a86c4, 0x62dc118c, 0xca53ad7e,
+ 0x62d186f8, 0xca4cd64b, 0x62c6fb0c, 0xca460129,
+ 0x62bc6dca, 0xca3f2e19, 0x62b1df30, 0xca385d1d,
+ 0x62a74f40, 0xca318e32, 0x629cbdfa, 0xca2ac15b,
+ 0x62922b5e, 0xca23f698, 0x6287976e, 0xca1d2de7,
+ 0x627d0228, 0xca16674b, 0x62726b8e, 0xca0fa2c3,
+ 0x6267d3a0, 0xca08e04f, 0x625d3a5e, 0xca021fef,
+ 0x62529fca, 0xc9fb61a5, 0x624803e2, 0xc9f4a570,
+ 0x623d66a8, 0xc9edeb50, 0x6232c81c, 0xc9e73346,
+ 0x6228283f, 0xc9e07d51, 0x621d8711, 0xc9d9c973,
+ 0x6212e492, 0xc9d317ab, 0x620840c2, 0xc9cc67fa,
+ 0x61fd9ba3, 0xc9c5ba60, 0x61f2f534, 0xc9bf0edd,
+ 0x61e84d76, 0xc9b86572, 0x61dda46a, 0xc9b1be1e,
+ 0x61d2fa0f, 0xc9ab18e3, 0x61c84e67, 0xc9a475bf,
+ 0x61bda171, 0xc99dd4b4, 0x61b2f32e, 0xc99735c2,
+ 0x61a8439e, 0xc99098e9, 0x619d92c2, 0xc989fe29,
+ 0x6192e09b, 0xc9836582, 0x61882d28, 0xc97ccef5,
+ 0x617d786a, 0xc9763a83, 0x6172c262, 0xc96fa82a,
+ 0x61680b0f, 0xc96917ec, 0x615d5273, 0xc96289c9,
+ 0x6152988d, 0xc95bfdc1, 0x6147dd5f, 0xc95573d4,
+ 0x613d20e8, 0xc94eec03, 0x61326329, 0xc948664d,
+ 0x6127a423, 0xc941e2b4, 0x611ce3d5, 0xc93b6137,
+ 0x61122240, 0xc934e1d6, 0x61075f65, 0xc92e6492,
+ 0x60fc9b44, 0xc927e96b, 0x60f1d5de, 0xc9217062,
+ 0x60e70f32, 0xc91af976, 0x60dc4742, 0xc91484a8,
+ 0x60d17e0d, 0xc90e11f7, 0x60c6b395, 0xc907a166,
+ 0x60bbe7d8, 0xc90132f2, 0x60b11ad9, 0xc8fac69e,
+ 0x60a64c97, 0xc8f45c68, 0x609b7d13, 0xc8edf452,
+ 0x6090ac4d, 0xc8e78e5b, 0x6085da46, 0xc8e12a84,
+ 0x607b06fe, 0xc8dac8cd, 0x60703275, 0xc8d46936,
+ 0x60655cac, 0xc8ce0bc0, 0x605a85a3, 0xc8c7b06b,
+ 0x604fad5b, 0xc8c15736, 0x6044d3d4, 0xc8bb0023,
+ 0x6039f90f, 0xc8b4ab32, 0x602f1d0b, 0xc8ae5862,
+ 0x60243fca, 0xc8a807b4, 0x6019614c, 0xc8a1b928,
+ 0x600e8190, 0xc89b6cbf, 0x6003a099, 0xc8952278,
+ 0x5ff8be65, 0xc88eda54, 0x5feddaf6, 0xc8889454,
+ 0x5fe2f64c, 0xc8825077, 0x5fd81067, 0xc87c0ebd,
+ 0x5fcd2948, 0xc875cf28, 0x5fc240ef, 0xc86f91b7,
+ 0x5fb7575c, 0xc869566a, 0x5fac6c91, 0xc8631d42,
+ 0x5fa1808c, 0xc85ce63e, 0x5f969350, 0xc856b160,
+ 0x5f8ba4dc, 0xc8507ea7, 0x5f80b531, 0xc84a4e14,
+ 0x5f75c44e, 0xc8441fa6, 0x5f6ad235, 0xc83df35f,
+ 0x5f5fdee6, 0xc837c93e, 0x5f54ea62, 0xc831a143,
+ 0x5f49f4a8, 0xc82b7b70, 0x5f3efdb9, 0xc82557c3,
+ 0x5f340596, 0xc81f363d, 0x5f290c3f, 0xc81916df,
+ 0x5f1e11b5, 0xc812f9a9, 0x5f1315f7, 0xc80cde9b,
+ 0x5f081907, 0xc806c5b5, 0x5efd1ae4, 0xc800aef7,
+ 0x5ef21b90, 0xc7fa9a62, 0x5ee71b0a, 0xc7f487f6,
+ 0x5edc1953, 0xc7ee77b3, 0x5ed1166b, 0xc7e8699a,
+ 0x5ec61254, 0xc7e25daa, 0x5ebb0d0d, 0xc7dc53e3,
+ 0x5eb00696, 0xc7d64c47, 0x5ea4fef0, 0xc7d046d6,
+ 0x5e99f61d, 0xc7ca438f, 0x5e8eec1b, 0xc7c44272,
+ 0x5e83e0eb, 0xc7be4381, 0x5e78d48e, 0xc7b846ba,
+ 0x5e6dc705, 0xc7b24c20, 0x5e62b84f, 0xc7ac53b1,
+ 0x5e57a86d, 0xc7a65d6e, 0x5e4c9760, 0xc7a06957,
+ 0x5e418528, 0xc79a776c, 0x5e3671c5, 0xc79487ae,
+ 0x5e2b5d38, 0xc78e9a1d, 0x5e204781, 0xc788aeb9,
+ 0x5e1530a1, 0xc782c582, 0x5e0a1898, 0xc77cde79,
+ 0x5dfeff67, 0xc776f99d, 0x5df3e50d, 0xc77116f0,
+ 0x5de8c98c, 0xc76b3671, 0x5dddace4, 0xc7655820,
+ 0x5dd28f15, 0xc75f7bfe, 0x5dc7701f, 0xc759a20a,
+ 0x5dbc5004, 0xc753ca46, 0x5db12ec3, 0xc74df4b1,
+ 0x5da60c5d, 0xc748214c, 0x5d9ae8d2, 0xc7425016,
+ 0x5d8fc424, 0xc73c8111, 0x5d849e51, 0xc736b43c,
+ 0x5d79775c, 0xc730e997, 0x5d6e4f43, 0xc72b2123,
+ 0x5d632608, 0xc7255ae0, 0x5d57fbaa, 0xc71f96ce,
+ 0x5d4cd02c, 0xc719d4ed, 0x5d41a38c, 0xc714153e,
+ 0x5d3675cb, 0xc70e57c0, 0x5d2b46ea, 0xc7089c75,
+ 0x5d2016e9, 0xc702e35c, 0x5d14e5c9, 0xc6fd2c75,
+ 0x5d09b389, 0xc6f777c1, 0x5cfe802b, 0xc6f1c540,
+ 0x5cf34baf, 0xc6ec14f2, 0x5ce81615, 0xc6e666d7,
+ 0x5cdcdf5e, 0xc6e0baf0, 0x5cd1a78a, 0xc6db113d,
+ 0x5cc66e99, 0xc6d569be, 0x5cbb348d, 0xc6cfc472,
+ 0x5caff965, 0xc6ca215c, 0x5ca4bd21, 0xc6c4807a,
+ 0x5c997fc4, 0xc6bee1cd, 0x5c8e414b, 0xc6b94554,
+ 0x5c8301b9, 0xc6b3ab12, 0x5c77c10e, 0xc6ae1304,
+ 0x5c6c7f4a, 0xc6a87d2d, 0x5c613c6d, 0xc6a2e98b,
+ 0x5c55f878, 0xc69d5820, 0x5c4ab36b, 0xc697c8eb,
+ 0x5c3f6d47, 0xc6923bec, 0x5c34260c, 0xc68cb124,
+ 0x5c28ddbb, 0xc6872894, 0x5c1d9454, 0xc681a23a,
+ 0x5c1249d8, 0xc67c1e18, 0x5c06fe46, 0xc6769c2e,
+ 0x5bfbb1a0, 0xc6711c7b, 0x5bf063e6, 0xc66b9f01,
+ 0x5be51518, 0xc66623be, 0x5bd9c537, 0xc660aab5,
+ 0x5bce7442, 0xc65b33e4, 0x5bc3223c, 0xc655bf4c,
+ 0x5bb7cf23, 0xc6504ced, 0x5bac7af9, 0xc64adcc7,
+ 0x5ba125bd, 0xc6456edb, 0x5b95cf71, 0xc6400329,
+ 0x5b8a7815, 0xc63a99b1, 0x5b7f1fa9, 0xc6353273,
+ 0x5b73c62d, 0xc62fcd6f, 0x5b686ba3, 0xc62a6aa6,
+ 0x5b5d100a, 0xc6250a18, 0x5b51b363, 0xc61fabc4,
+ 0x5b4655ae, 0xc61a4fac, 0x5b3af6ec, 0xc614f5cf,
+ 0x5b2f971e, 0xc60f9e2e, 0x5b243643, 0xc60a48c9,
+ 0x5b18d45c, 0xc604f5a0, 0x5b0d716a, 0xc5ffa4b3,
+ 0x5b020d6c, 0xc5fa5603, 0x5af6a865, 0xc5f5098f,
+ 0x5aeb4253, 0xc5efbf58, 0x5adfdb37, 0xc5ea775e,
+ 0x5ad47312, 0xc5e531a1, 0x5ac909e5, 0xc5dfee22,
+ 0x5abd9faf, 0xc5daace1, 0x5ab23471, 0xc5d56ddd,
+ 0x5aa6c82b, 0xc5d03118, 0x5a9b5adf, 0xc5caf690,
+ 0x5a8fec8c, 0xc5c5be47, 0x5a847d33, 0xc5c0883d,
+ 0x5a790cd4, 0xc5bb5472, 0x5a6d9b70, 0xc5b622e6,
+ 0x5a622907, 0xc5b0f399, 0x5a56b599, 0xc5abc68c,
+ 0x5a4b4128, 0xc5a69bbe, 0x5a3fcbb3, 0xc5a17330,
+ 0x5a34553b, 0xc59c4ce3, 0x5a28ddc0, 0xc59728d5,
+ 0x5a1d6544, 0xc5920708, 0x5a11ebc5, 0xc58ce77c,
+ 0x5a067145, 0xc587ca31, 0x59faf5c5, 0xc582af26,
+ 0x59ef7944, 0xc57d965d, 0x59e3fbc3, 0xc5787fd6,
+ 0x59d87d42, 0xc5736b90, 0x59ccfdc2, 0xc56e598c,
+ 0x59c17d44, 0xc56949ca, 0x59b5fbc8, 0xc5643c4a,
+ 0x59aa794d, 0xc55f310d, 0x599ef5d6, 0xc55a2812,
+ 0x59937161, 0xc555215a, 0x5987ebf0, 0xc5501ce5,
+ 0x597c6584, 0xc54b1ab4, 0x5970de1b, 0xc5461ac6,
+ 0x596555b8, 0xc5411d1b, 0x5959cc5a, 0xc53c21b4,
+ 0x594e4201, 0xc5372891, 0x5942b6af, 0xc53231b3,
+ 0x59372a64, 0xc52d3d18, 0x592b9d1f, 0xc5284ac3,
+ 0x59200ee3, 0xc5235ab2, 0x59147fae, 0xc51e6ce6,
+ 0x5908ef82, 0xc519815f, 0x58fd5e5f, 0xc514981d,
+ 0x58f1cc45, 0xc50fb121, 0x58e63935, 0xc50acc6b,
+ 0x58daa52f, 0xc505e9fb, 0x58cf1034, 0xc50109d0,
+ 0x58c37a44, 0xc4fc2bec, 0x58b7e35f, 0xc4f7504e,
+ 0x58ac4b87, 0xc4f276f7, 0x58a0b2bb, 0xc4ed9fe7,
+ 0x589518fc, 0xc4e8cb1e, 0x58897e4a, 0xc4e3f89c,
+ 0x587de2a7, 0xc4df2862, 0x58724611, 0xc4da5a6f,
+ 0x5866a88a, 0xc4d58ec3, 0x585b0a13, 0xc4d0c560,
+ 0x584f6aab, 0xc4cbfe45, 0x5843ca53, 0xc4c73972,
+ 0x5838290c, 0xc4c276e8, 0x582c86d5, 0xc4bdb6a6,
+ 0x5820e3b0, 0xc4b8f8ad, 0x58153f9d, 0xc4b43cfd,
+ 0x58099a9c, 0xc4af8397, 0x57fdf4ae, 0xc4aacc7a,
+ 0x57f24dd3, 0xc4a617a6, 0x57e6a60c, 0xc4a1651c,
+ 0x57dafd59, 0xc49cb4dd, 0x57cf53bb, 0xc49806e7,
+ 0x57c3a931, 0xc4935b3c, 0x57b7fdbd, 0xc48eb1db,
+ 0x57ac515f, 0xc48a0ac4, 0x57a0a417, 0xc48565f9,
+ 0x5794f5e6, 0xc480c379, 0x578946cc, 0xc47c2344,
+ 0x577d96ca, 0xc477855a, 0x5771e5e0, 0xc472e9bc,
+ 0x5766340f, 0xc46e5069, 0x575a8157, 0xc469b963,
+ 0x574ecdb8, 0xc46524a9, 0x57431933, 0xc460923b,
+ 0x573763c9, 0xc45c0219, 0x572bad7a, 0xc4577444,
+ 0x571ff646, 0xc452e8bc, 0x57143e2d, 0xc44e5f80,
+ 0x57088531, 0xc449d892, 0x56fccb51, 0xc44553f2,
+ 0x56f1108f, 0xc440d19e, 0x56e554ea, 0xc43c5199,
+ 0x56d99864, 0xc437d3e1, 0x56cddafb, 0xc4335877,
+ 0x56c21cb2, 0xc42edf5c, 0x56b65d88, 0xc42a688f,
+ 0x56aa9d7e, 0xc425f410, 0x569edc94, 0xc42181e0,
+ 0x56931acb, 0xc41d11ff, 0x56875823, 0xc418a46d,
+ 0x567b949d, 0xc414392b, 0x566fd039, 0xc40fd037,
+ 0x56640af7, 0xc40b6994, 0x565844d8, 0xc4070540,
+ 0x564c7ddd, 0xc402a33c, 0x5640b606, 0xc3fe4388,
+ 0x5634ed53, 0xc3f9e624, 0x562923c5, 0xc3f58b10,
+ 0x561d595d, 0xc3f1324e, 0x56118e1a, 0xc3ecdbdc,
+ 0x5605c1fd, 0xc3e887bb, 0x55f9f507, 0xc3e435ea,
+ 0x55ee2738, 0xc3dfe66c, 0x55e25890, 0xc3db993e,
+ 0x55d68911, 0xc3d74e62, 0x55cab8ba, 0xc3d305d8,
+ 0x55bee78c, 0xc3cebfa0, 0x55b31587, 0xc3ca7bba,
+ 0x55a742ac, 0xc3c63a26, 0x559b6efb, 0xc3c1fae5,
+ 0x558f9a76, 0xc3bdbdf6, 0x5583c51b, 0xc3b9835a,
+ 0x5577eeec, 0xc3b54b11, 0x556c17e9, 0xc3b1151b,
+ 0x55604013, 0xc3ace178, 0x5554676a, 0xc3a8b028,
+ 0x55488dee, 0xc3a4812c, 0x553cb3a0, 0xc3a05484,
+ 0x5530d881, 0xc39c2a2f, 0x5524fc90, 0xc398022f,
+ 0x55191fcf, 0xc393dc82, 0x550d423d, 0xc38fb92a,
+ 0x550163dc, 0xc38b9827, 0x54f584ac, 0xc3877978,
+ 0x54e9a4ac, 0xc3835d1e, 0x54ddc3de, 0xc37f4319,
+ 0x54d1e242, 0xc37b2b6a, 0x54c5ffd9, 0xc377160f,
+ 0x54ba1ca3, 0xc373030a, 0x54ae38a0, 0xc36ef25b,
+ 0x54a253d1, 0xc36ae401, 0x54966e36, 0xc366d7fd,
+ 0x548a87d1, 0xc362ce50, 0x547ea0a0, 0xc35ec6f8,
+ 0x5472b8a5, 0xc35ac1f7, 0x5466cfe1, 0xc356bf4d,
+ 0x545ae653, 0xc352bef9, 0x544efbfc, 0xc34ec0fc,
+ 0x544310dd, 0xc34ac556, 0x543724f5, 0xc346cc07,
+ 0x542b3846, 0xc342d510, 0x541f4ad1, 0xc33ee070,
+ 0x54135c94, 0xc33aee27, 0x54076d91, 0xc336fe37,
+ 0x53fb7dc9, 0xc333109e, 0x53ef8d3c, 0xc32f255e,
+ 0x53e39be9, 0xc32b3c75, 0x53d7a9d3, 0xc32755e5,
+ 0x53cbb6f8, 0xc32371ae, 0x53bfc35b, 0xc31f8fcf,
+ 0x53b3cefa, 0xc31bb049, 0x53a7d9d7, 0xc317d31c,
+ 0x539be3f2, 0xc313f848, 0x538fed4b, 0xc3101fce,
+ 0x5383f5e3, 0xc30c49ad, 0x5377fdbb, 0xc30875e5,
+ 0x536c04d2, 0xc304a477, 0x53600b2a, 0xc300d563,
+ 0x535410c3, 0xc2fd08a9, 0x5348159d, 0xc2f93e4a,
+ 0x533c19b8, 0xc2f57644, 0x53301d16, 0xc2f1b099,
+ 0x53241fb6, 0xc2eded49, 0x5318219a, 0xc2ea2c53,
+ 0x530c22c1, 0xc2e66db8, 0x5300232c, 0xc2e2b178,
+ 0x52f422db, 0xc2def794, 0x52e821cf, 0xc2db400a,
+ 0x52dc2009, 0xc2d78add, 0x52d01d89, 0xc2d3d80a,
+ 0x52c41a4f, 0xc2d02794, 0x52b8165b, 0xc2cc7979,
+ 0x52ac11af, 0xc2c8cdbb, 0x52a00c4b, 0xc2c52459,
+ 0x5294062f, 0xc2c17d52, 0x5287ff5b, 0xc2bdd8a9,
+ 0x527bf7d1, 0xc2ba365c, 0x526fef90, 0xc2b6966c,
+ 0x5263e699, 0xc2b2f8d8, 0x5257dced, 0xc2af5da2,
+ 0x524bd28c, 0xc2abc4c9, 0x523fc776, 0xc2a82e4d,
+ 0x5233bbac, 0xc2a49a2e, 0x5227af2e, 0xc2a1086d,
+ 0x521ba1fd, 0xc29d790a, 0x520f941a, 0xc299ec05,
+ 0x52038584, 0xc296615d, 0x51f7763c, 0xc292d914,
+ 0x51eb6643, 0xc28f5329, 0x51df5599, 0xc28bcf9c,
+ 0x51d3443f, 0xc2884e6e, 0x51c73235, 0xc284cf9f,
+ 0x51bb1f7c, 0xc281532e, 0x51af0c13, 0xc27dd91c,
+ 0x51a2f7fc, 0xc27a616a, 0x5196e337, 0xc276ec16,
+ 0x518acdc4, 0xc2737922, 0x517eb7a4, 0xc270088e,
+ 0x5172a0d7, 0xc26c9a58, 0x5166895f, 0xc2692e83,
+ 0x515a713a, 0xc265c50e, 0x514e586a, 0xc2625df8,
+ 0x51423ef0, 0xc25ef943, 0x513624cb, 0xc25b96ee,
+ 0x512a09fc, 0xc25836f9, 0x511dee84, 0xc254d965,
+ 0x5111d263, 0xc2517e31, 0x5105b599, 0xc24e255e,
+ 0x50f99827, 0xc24aceed, 0x50ed7a0e, 0xc2477adc,
+ 0x50e15b4e, 0xc244292c, 0x50d53be7, 0xc240d9de,
+ 0x50c91bda, 0xc23d8cf1, 0x50bcfb28, 0xc23a4265,
+ 0x50b0d9d0, 0xc236fa3b, 0x50a4b7d3, 0xc233b473,
+ 0x50989532, 0xc230710d, 0x508c71ee, 0xc22d3009,
+ 0x50804e06, 0xc229f167, 0x5074297b, 0xc226b528,
+ 0x5068044e, 0xc2237b4b, 0x505bde7f, 0xc22043d0,
+ 0x504fb80e, 0xc21d0eb8, 0x504390fd, 0xc219dc03,
+ 0x5037694b, 0xc216abb1, 0x502b40f8, 0xc2137dc2,
+ 0x501f1807, 0xc2105236, 0x5012ee76, 0xc20d290d,
+ 0x5006c446, 0xc20a0248, 0x4ffa9979, 0xc206dde6,
+ 0x4fee6e0d, 0xc203bbe8, 0x4fe24205, 0xc2009c4e,
+ 0x4fd6155f, 0xc1fd7f17, 0x4fc9e81e, 0xc1fa6445,
+ 0x4fbdba40, 0xc1f74bd6, 0x4fb18bc8, 0xc1f435cc,
+ 0x4fa55cb4, 0xc1f12227, 0x4f992d06, 0xc1ee10e5,
+ 0x4f8cfcbe, 0xc1eb0209, 0x4f80cbdc, 0xc1e7f591,
+ 0x4f749a61, 0xc1e4eb7e, 0x4f68684e, 0xc1e1e3d0,
+ 0x4f5c35a3, 0xc1dede87, 0x4f500260, 0xc1dbdba3,
+ 0x4f43ce86, 0xc1d8db25, 0x4f379a16, 0xc1d5dd0c,
+ 0x4f2b650f, 0xc1d2e158, 0x4f1f2f73, 0xc1cfe80a,
+ 0x4f12f941, 0xc1ccf122, 0x4f06c27a, 0xc1c9fca0,
+ 0x4efa8b20, 0xc1c70a84, 0x4eee5331, 0xc1c41ace,
+ 0x4ee21aaf, 0xc1c12d7e, 0x4ed5e19a, 0xc1be4294,
+ 0x4ec9a7f3, 0xc1bb5a11, 0x4ebd6db9, 0xc1b873f5,
+ 0x4eb132ef, 0xc1b5903f, 0x4ea4f793, 0xc1b2aef0,
+ 0x4e98bba7, 0xc1afd007, 0x4e8c7f2a, 0xc1acf386,
+ 0x4e80421e, 0xc1aa196c, 0x4e740483, 0xc1a741b9,
+ 0x4e67c65a, 0xc1a46c6e, 0x4e5b87a2, 0xc1a1998a,
+ 0x4e4f485c, 0xc19ec90d, 0x4e430889, 0xc19bfaf9,
+ 0x4e36c82a, 0xc1992f4c, 0x4e2a873e, 0xc1966606,
+ 0x4e1e45c6, 0xc1939f29, 0x4e1203c3, 0xc190dab4,
+ 0x4e05c135, 0xc18e18a7, 0x4df97e1d, 0xc18b5903,
+ 0x4ded3a7b, 0xc1889bc6, 0x4de0f64f, 0xc185e0f3,
+ 0x4dd4b19a, 0xc1832888, 0x4dc86c5d, 0xc1807285,
+ 0x4dbc2698, 0xc17dbeec, 0x4dafe04b, 0xc17b0dbb,
+ 0x4da39978, 0xc1785ef4, 0x4d97521d, 0xc175b296,
+ 0x4d8b0a3d, 0xc17308a1, 0x4d7ec1d6, 0xc1706115,
+ 0x4d7278eb, 0xc16dbbf3, 0x4d662f7b, 0xc16b193a,
+ 0x4d59e586, 0xc16878eb, 0x4d4d9b0e, 0xc165db05,
+ 0x4d415013, 0xc1633f8a, 0x4d350495, 0xc160a678,
+ 0x4d28b894, 0xc15e0fd1, 0x4d1c6c11, 0xc15b7b94,
+ 0x4d101f0e, 0xc158e9c1, 0x4d03d189, 0xc1565a58,
+ 0x4cf78383, 0xc153cd5a, 0x4ceb34fe, 0xc15142c6,
+ 0x4cdee5f9, 0xc14eba9d, 0x4cd29676, 0xc14c34df,
+ 0x4cc64673, 0xc149b18b, 0x4cb9f5f3, 0xc14730a3,
+ 0x4cada4f5, 0xc144b225, 0x4ca1537a, 0xc1423613,
+ 0x4c950182, 0xc13fbc6c, 0x4c88af0e, 0xc13d4530,
+ 0x4c7c5c1e, 0xc13ad060, 0x4c7008b3, 0xc1385dfb,
+ 0x4c63b4ce, 0xc135ee02, 0x4c57606e, 0xc1338075,
+ 0x4c4b0b94, 0xc1311553, 0x4c3eb641, 0xc12eac9d,
+ 0x4c326075, 0xc12c4653, 0x4c260a31, 0xc129e276,
+ 0x4c19b374, 0xc1278104, 0x4c0d5c41, 0xc12521ff,
+ 0x4c010496, 0xc122c566, 0x4bf4ac75, 0xc1206b39,
+ 0x4be853de, 0xc11e1379, 0x4bdbfad1, 0xc11bbe26,
+ 0x4bcfa150, 0xc1196b3f, 0x4bc34759, 0xc1171ac6,
+ 0x4bb6ecef, 0xc114ccb9, 0x4baa9211, 0xc1128119,
+ 0x4b9e36c0, 0xc11037e6, 0x4b91dafc, 0xc10df120,
+ 0x4b857ec7, 0xc10bacc8, 0x4b79221f, 0xc1096add,
+ 0x4b6cc506, 0xc1072b5f, 0x4b60677c, 0xc104ee4f,
+ 0x4b540982, 0xc102b3ac, 0x4b47ab19, 0xc1007b77,
+ 0x4b3b4c40, 0xc0fe45b0, 0x4b2eecf8, 0xc0fc1257,
+ 0x4b228d42, 0xc0f9e16b, 0x4b162d1d, 0xc0f7b2ee,
+ 0x4b09cc8c, 0xc0f586df, 0x4afd6b8d, 0xc0f35d3e,
+ 0x4af10a22, 0xc0f1360b, 0x4ae4a84b, 0xc0ef1147,
+ 0x4ad84609, 0xc0eceef1, 0x4acbe35b, 0xc0eacf09,
+ 0x4abf8043, 0xc0e8b190, 0x4ab31cc1, 0xc0e69686,
+ 0x4aa6b8d5, 0xc0e47deb, 0x4a9a5480, 0xc0e267be,
+ 0x4a8defc3, 0xc0e05401, 0x4a818a9d, 0xc0de42b2,
+ 0x4a752510, 0xc0dc33d2, 0x4a68bf1b, 0xc0da2762,
+ 0x4a5c58c0, 0xc0d81d61, 0x4a4ff1fe, 0xc0d615cf,
+ 0x4a438ad7, 0xc0d410ad, 0x4a37234a, 0xc0d20dfa,
+ 0x4a2abb59, 0xc0d00db6, 0x4a1e5303, 0xc0ce0fe3,
+ 0x4a11ea49, 0xc0cc147f, 0x4a05812c, 0xc0ca1b8a,
+ 0x49f917ac, 0xc0c82506, 0x49ecadc9, 0xc0c630f2,
+ 0x49e04385, 0xc0c43f4d, 0x49d3d8df, 0xc0c25019,
+ 0x49c76dd8, 0xc0c06355, 0x49bb0271, 0xc0be7901,
+ 0x49ae96aa, 0xc0bc911d, 0x49a22a83, 0xc0baabaa,
+ 0x4995bdfd, 0xc0b8c8a7, 0x49895118, 0xc0b6e815,
+ 0x497ce3d5, 0xc0b509f3, 0x49707635, 0xc0b32e42,
+ 0x49640837, 0xc0b15502, 0x495799dd, 0xc0af7e33,
+ 0x494b2b27, 0xc0ada9d4, 0x493ebc14, 0xc0abd7e6,
+ 0x49324ca7, 0xc0aa086a, 0x4925dcdf, 0xc0a83b5e,
+ 0x49196cbc, 0xc0a670c4, 0x490cfc40, 0xc0a4a89b,
+ 0x49008b6a, 0xc0a2e2e3, 0x48f41a3c, 0xc0a11f9d,
+ 0x48e7a8b5, 0xc09f5ec8, 0x48db36d6, 0xc09da065,
+ 0x48cec4a0, 0xc09be473, 0x48c25213, 0xc09a2af3,
+ 0x48b5df30, 0xc09873e4, 0x48a96bf6, 0xc096bf48,
+ 0x489cf867, 0xc0950d1d, 0x48908483, 0xc0935d64,
+ 0x4884104b, 0xc091b01d, 0x48779bbe, 0xc0900548,
+ 0x486b26de, 0xc08e5ce5, 0x485eb1ab, 0xc08cb6f5,
+ 0x48523c25, 0xc08b1376, 0x4845c64d, 0xc089726a,
+ 0x48395024, 0xc087d3d0, 0x482cd9a9, 0xc08637a9,
+ 0x482062de, 0xc0849df4, 0x4813ebc2, 0xc08306b2,
+ 0x48077457, 0xc08171e2, 0x47fafc9c, 0xc07fdf85,
+ 0x47ee8493, 0xc07e4f9b, 0x47e20c3b, 0xc07cc223,
+ 0x47d59396, 0xc07b371e, 0x47c91aa3, 0xc079ae8c,
+ 0x47bca163, 0xc078286e, 0x47b027d7, 0xc076a4c2,
+ 0x47a3adff, 0xc0752389, 0x479733dc, 0xc073a4c3,
+ 0x478ab96e, 0xc0722871, 0x477e3eb5, 0xc070ae92,
+ 0x4771c3b3, 0xc06f3726, 0x47654867, 0xc06dc22e,
+ 0x4758ccd2, 0xc06c4fa8, 0x474c50f4, 0xc06adf97,
+ 0x473fd4cf, 0xc06971f9, 0x47335862, 0xc06806ce,
+ 0x4726dbae, 0xc0669e18, 0x471a5eb3, 0xc06537d4,
+ 0x470de172, 0xc063d405, 0x470163eb, 0xc06272aa,
+ 0x46f4e620, 0xc06113c2, 0x46e86810, 0xc05fb74e,
+ 0x46dbe9bb, 0xc05e5d4e, 0x46cf6b23, 0xc05d05c3,
+ 0x46c2ec48, 0xc05bb0ab, 0x46b66d29, 0xc05a5e07,
+ 0x46a9edc9, 0xc0590dd8, 0x469d6e27, 0xc057c01d,
+ 0x4690ee44, 0xc05674d6, 0x46846e1f, 0xc0552c03,
+ 0x4677edbb, 0xc053e5a5, 0x466b6d16, 0xc052a1bb,
+ 0x465eec33, 0xc0516045, 0x46526b10, 0xc0502145,
+ 0x4645e9af, 0xc04ee4b8, 0x46396810, 0xc04daaa1,
+ 0x462ce634, 0xc04c72fe, 0x4620641a, 0xc04b3dcf,
+ 0x4613e1c5, 0xc04a0b16, 0x46075f33, 0xc048dad1,
+ 0x45fadc66, 0xc047ad01, 0x45ee595d, 0xc04681a6,
+ 0x45e1d61b, 0xc04558c0, 0x45d5529e, 0xc044324f,
+ 0x45c8cee7, 0xc0430e53, 0x45bc4af8, 0xc041eccc,
+ 0x45afc6d0, 0xc040cdba, 0x45a3426f, 0xc03fb11d,
+ 0x4596bdd7, 0xc03e96f6, 0x458a3908, 0xc03d7f44,
+ 0x457db403, 0xc03c6a07, 0x45712ec7, 0xc03b573f,
+ 0x4564a955, 0xc03a46ed, 0x455823ae, 0xc0393910,
+ 0x454b9dd3, 0xc0382da8, 0x453f17c3, 0xc03724b6,
+ 0x4532917f, 0xc0361e3a, 0x45260b08, 0xc0351a33,
+ 0x4519845e, 0xc03418a2, 0x450cfd82, 0xc0331986,
+ 0x45007674, 0xc0321ce0, 0x44f3ef35, 0xc03122b0,
+ 0x44e767c5, 0xc0302af5, 0x44dae024, 0xc02f35b1,
+ 0x44ce5854, 0xc02e42e2, 0x44c1d054, 0xc02d5289,
+ 0x44b54825, 0xc02c64a6, 0x44a8bfc7, 0xc02b7939,
+ 0x449c373c, 0xc02a9042, 0x448fae83, 0xc029a9c1,
+ 0x4483259d, 0xc028c5b6, 0x44769c8b, 0xc027e421,
+ 0x446a134c, 0xc0270502, 0x445d89e2, 0xc0262859,
+ 0x4451004d, 0xc0254e27, 0x4444768d, 0xc024766a,
+ 0x4437eca4, 0xc023a124, 0x442b6290, 0xc022ce54,
+ 0x441ed854, 0xc021fdfb, 0x44124dee, 0xc0213018,
+ 0x4405c361, 0xc02064ab, 0x43f938ac, 0xc01f9bb5,
+ 0x43ecadcf, 0xc01ed535, 0x43e022cc, 0xc01e112b,
+ 0x43d397a3, 0xc01d4f99, 0x43c70c54, 0xc01c907c,
+ 0x43ba80df, 0xc01bd3d6, 0x43adf546, 0xc01b19a7,
+ 0x43a16988, 0xc01a61ee, 0x4394dda7, 0xc019acac,
+ 0x438851a2, 0xc018f9e1, 0x437bc57b, 0xc018498c,
+ 0x436f3931, 0xc0179bae, 0x4362acc5, 0xc016f047,
+ 0x43562038, 0xc0164757, 0x43499389, 0xc015a0dd,
+ 0x433d06bb, 0xc014fcda, 0x433079cc, 0xc0145b4e,
+ 0x4323ecbe, 0xc013bc39, 0x43175f91, 0xc0131f9b,
+ 0x430ad245, 0xc0128574, 0x42fe44dc, 0xc011edc3,
+ 0x42f1b755, 0xc011588a, 0x42e529b0, 0xc010c5c7,
+ 0x42d89bf0, 0xc010357c, 0x42cc0e13, 0xc00fa7a8,
+ 0x42bf801a, 0xc00f1c4a, 0x42b2f207, 0xc00e9364,
+ 0x42a663d8, 0xc00e0cf5, 0x4299d590, 0xc00d88fd,
+ 0x428d472e, 0xc00d077c, 0x4280b8b3, 0xc00c8872,
+ 0x42742a1f, 0xc00c0be0, 0x42679b73, 0xc00b91c4,
+ 0x425b0caf, 0xc00b1a20, 0x424e7dd4, 0xc00aa4f3,
+ 0x4241eee2, 0xc00a323d, 0x42355fd9, 0xc009c1ff,
+ 0x4228d0bb, 0xc0095438, 0x421c4188, 0xc008e8e8,
+ 0x420fb240, 0xc008800f, 0x420322e3, 0xc00819ae,
+ 0x41f69373, 0xc007b5c4, 0x41ea03ef, 0xc0075452,
+ 0x41dd7459, 0xc006f556, 0x41d0e4b0, 0xc00698d3,
+ 0x41c454f5, 0xc0063ec6, 0x41b7c528, 0xc005e731,
+ 0x41ab354b, 0xc0059214, 0x419ea55d, 0xc0053f6e,
+ 0x4192155f, 0xc004ef3f, 0x41858552, 0xc004a188,
+ 0x4178f536, 0xc0045648, 0x416c650b, 0xc0040d80,
+ 0x415fd4d2, 0xc003c72f, 0x4153448c, 0xc0038356,
+ 0x4146b438, 0xc00341f4, 0x413a23d8, 0xc003030a,
+ 0x412d936c, 0xc002c697, 0x412102f4, 0xc0028c9c,
+ 0x41147271, 0xc0025519, 0x4107e1e3, 0xc002200d,
+ 0x40fb514b, 0xc001ed78, 0x40eec0aa, 0xc001bd5c,
+ 0x40e22fff, 0xc0018fb6, 0x40d59f4c, 0xc0016489,
+ 0x40c90e90, 0xc0013bd3, 0x40bc7dcc, 0xc0011594,
+ 0x40afed02, 0xc000f1ce, 0x40a35c30, 0xc000d07e,
+ 0x4096cb58, 0xc000b1a7, 0x408a3a7b, 0xc0009547,
+ 0x407da998, 0xc0007b5f, 0x407118b0, 0xc00063ee,
+ 0x406487c4, 0xc0004ef5, 0x4057f6d4, 0xc0003c74,
+ 0x404b65e1, 0xc0002c6a, 0x403ed4ea, 0xc0001ed8,
+ 0x403243f1, 0xc00013bd, 0x4025b2f7, 0xc0000b1a,
+ 0x401921fb, 0xc00004ef, 0x400c90fe, 0xc000013c,
+};
+
+/**
+* @brief Initialization function for the Q31 RFFT/RIFFT.
+* @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure.
+* @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure.
+* @param[in] fftLenReal length of the FFT.
+* @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+* @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+* @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported value.
+*
+* \par Description:
+* \par
+* The parameter <code>fftLenReal</code> Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.
+* \par
+* The parameter <code>ifftFlagR</code> controls whether a forward or inverse transform is computed.
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.
+* \par
+* The parameter <code>bitReverseFlag</code> controls whether output is in normal order or bit reversed order.
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.
+* \par
+* This function also initializes Twiddle factor table.
+*/
+
+arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag)
+{
+ /* Initialise the default arm status */
+ arm_status status = ARM_MATH_SUCCESS;
+
+ /* Initialize the Real FFT length */
+ S->fftLenReal = (uint16_t) fftLenReal;
+
+ /* Initialize the Complex FFT length */
+ S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+ /* Initialize the Twiddle coefficientA pointer */
+ S->pTwiddleAReal = (q31_t *) realCoefAQ31;
+
+ /* Initialize the Twiddle coefficientB pointer */
+ S->pTwiddleBReal = (q31_t *) realCoefBQ31;
+
+ /* Initialize the Flag for selection of RFFT or RIFFT */
+ S->ifftFlagR = (uint8_t) ifftFlagR;
+
+ /* Initialize the Flag for calculation Bit reversal or not */
+ S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+ /* Initialization of coef modifier depending on the FFT length */
+ switch (S->fftLenReal)
+ {
+ case 8192:
+ S->twidCoefRModifier = 1u;
+ break;
+ case 2048u:
+ S->twidCoefRModifier = 4u;
+ break;
+ case 512u:
+ S->twidCoefRModifier = 16u;
+ break;
+ case 128u:
+ S->twidCoefRModifier = 64u;
+ break;
+ default:
+ /* Reporting argument error if rfftSize is not valid value */
+ status = ARM_MATH_ARGUMENT_ERROR;
+ break;
+ }
+
+ /* Init Complex FFT Instance */
+ S->pCfft = S_CFFT;
+
+ if(S->ifftFlagR)
+ {
+ /* Initializes the CIFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 1u, 1u);
+ }
+ else
+ {
+ /* Initializes the CFFT Module for fftLenreal/2 length */
+ arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 0u, 1u);
+ }
+
+ /* return the status of RFFT Init function */
+ return (status);
+
+}
+
+ /**
+ * @} end of RealFFT group
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_q15.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_q15.c
new file mode 100644
index 000000000..0b6613cde
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_q15.c
@@ -0,0 +1,482 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_q15.c
+*
+* Description: RFFT & RIFFT Q15 process function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix4_butterfly_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
+void arm_radix4_butterfly_inverse_q15(
+ q15_t * pSrc16,
+ uint32_t fftLen,
+ q15_t * pCoef16,
+ uint32_t twidCoefModifier);
+
+void arm_bitreversal_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ uint16_t bitRevFactor,
+ uint16_t * pBitRevTab);
+
+ /*--------------------------------------------------------------------
+* Internal functions prototypes
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pATable,
+ q15_t * pBTable,
+ q15_t * pDst,
+ uint32_t modifier);
+
+void arm_split_rifft_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pATable,
+ q15_t * pBTable,
+ q15_t * pDst,
+ uint32_t modifier);
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q15 RFFT/RIFFT.
+ * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ *
+ * \par Input an output formats:
+ * \par
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+ * Hence the output format is different for different RFFT sizes.
+ * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:
+ * \par
+ * \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT"
+ * \par
+ * \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT"
+ */
+
+void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst)
+{
+ const arm_cfft_radix4_instance_q15 *S_CFFT = S->pCfft;
+
+ /* Calculation of RIFFT of input */
+ if(S->ifftFlagR == 1u)
+ {
+ /* Real IFFT core process */
+ arm_split_rifft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+ /* Complex readix-4 IFFT process */
+ arm_radix4_butterfly_inverse_q15(pDst, S_CFFT->fftLen,
+ S_CFFT->pTwiddle,
+ S_CFFT->twidCoefModifier);
+
+ /* Bit reversal process */
+ if(S->bitReverseFlagR == 1u)
+ {
+ arm_bitreversal_q15(pDst, S_CFFT->fftLen,
+ S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+ }
+ else
+ {
+ /* Calculation of RFFT of input */
+
+ /* Complex readix-4 FFT process */
+ arm_radix4_butterfly_q15(pSrc, S_CFFT->fftLen,
+ S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+ /* Bit reversal process */
+ if(S->bitReverseFlagR == 1u)
+ {
+ arm_bitreversal_q15(pSrc, S_CFFT->fftLen,
+ S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+
+ arm_split_rfft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+ }
+
+}
+
+ /**
+ * @} end of RealFFT group
+ */
+
+/**
+ * @brief Core Real FFT process
+ * @param *pSrc points to the input buffer.
+ * @param fftLen length of FFT.
+ * @param *pATable points to the A twiddle Coef buffer.
+ * @param *pBTable points to the B twiddle Coef buffer.
+ * @param *pDst points to the output buffer.
+ * @param modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ * The function implements a Real FFT
+ */
+
+void arm_split_rfft_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pATable,
+ q15_t * pBTable,
+ q15_t * pDst,
+ uint32_t modifier)
+{
+ uint32_t i; /* Loop Counter */
+ q31_t outR, outI; /* Temporary variables for output */
+ q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ q15_t *pSrc1, *pSrc2;
+
+
+// pSrc[2u * fftLen] = pSrc[0];
+// pSrc[(2u * fftLen) + 1u] = pSrc[1];
+
+ pCoefA = &pATable[modifier * 2u];
+ pCoefB = &pBTable[modifier * 2u];
+
+ pSrc1 = &pSrc[2];
+ pSrc2 = &pSrc[(2u * fftLen) - 2u];
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ i = 1u;
+
+ while(i < fftLen)
+ {
+ /*
+ outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+ + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+ outR = __SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA));
+
+#else
+
+ /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */
+ outR = -(__SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA)));
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+ outR = __SMLAD(*__SIMD32(pSrc2), *__SIMD32(pCoefB), outR) >> 15u;
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ outI = __SMUSDX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+#else
+
+ outI = __SMUSDX(*__SIMD32(pCoefB), *__SIMD32(pSrc2)--);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */
+ outI = __SMLADX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), outI);
+
+ /* write output */
+ pDst[2u * i] = (q15_t) outR;
+ pDst[(2u * i) + 1u] = outI >> 15u;
+
+ /* write complex conjugate output */
+ pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
+ pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (2u * modifier);
+ pCoefA = pCoefA + (2u * modifier);
+
+ i++;
+
+ }
+
+ pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+ pDst[(2u * fftLen) + 1u] = 0;
+
+ pDst[0] = pSrc[0] + pSrc[1];
+ pDst[1] = 0;
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ i = 1u;
+
+ while(i < fftLen)
+ {
+ /*
+ outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+ + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ outR = *pSrc1 * *pCoefA;
+ outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1));
+ outR = outR + (*pSrc2 * *pCoefB);
+ outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 15;
+
+
+ /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+ */
+
+ outI = *pSrc2 * *(pCoefB + 1);
+ outI = outI - (*(pSrc2 + 1) * *pCoefB);
+ outI = outI + (*(pSrc1 + 1) * *pCoefA);
+ outI = outI + (*pSrc1 * *(pCoefA + 1));
+
+ /* update input pointers */
+ pSrc1 += 2u;
+ pSrc2 -= 2u;
+
+ /* write output */
+ pDst[2u * i] = (q15_t) outR;
+ pDst[(2u * i) + 1u] = outI >> 15u;
+
+ /* write complex conjugate output */
+ pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
+ pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (2u * modifier);
+ pCoefA = pCoefA + (2u * modifier);
+
+ i++;
+
+ }
+
+ pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+ pDst[(2u * fftLen) + 1u] = 0;
+
+ pDst[0] = pSrc[0] + pSrc[1];
+ pDst[1] = 0;
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
+
+
+/**
+ * @brief Core Real IFFT process
+ * @param[in] *pSrc points to the input buffer.
+ * @param[in] fftLen length of FFT.
+ * @param[in] *pATable points to the twiddle Coef A buffer.
+ * @param[in] *pBTable points to the twiddle Coef B buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ * The function implements a Real IFFT
+ */
+void arm_split_rifft_q15(
+ q15_t * pSrc,
+ uint32_t fftLen,
+ q15_t * pATable,
+ q15_t * pBTable,
+ q15_t * pDst,
+ uint32_t modifier)
+{
+ uint32_t i; /* Loop Counter */
+ q31_t outR, outI; /* Temporary variables for output */
+ q15_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ q15_t *pSrc1, *pSrc2;
+ q15_t *pDst1 = &pDst[0];
+
+ pCoefA = &pATable[0];
+ pCoefB = &pBTable[0];
+
+ pSrc1 = &pSrc[0];
+ pSrc2 = &pSrc[2u * fftLen];
+
+#ifndef ARM_MATH_CM0_FAMILY
+
+ /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+ i = fftLen;
+
+ while(i > 0u)
+ {
+
+ /*
+ outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+
+ outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+
+ */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+ outR = __SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB));
+
+#else
+
+ /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] +
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */
+ outR = -(__SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB)));
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] */
+ outR = __SMLAD(*__SIMD32(pSrc1), *__SIMD32(pCoefA), outR) >> 15u;
+
+ /*
+ -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+ outI = __SMUADX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+ /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ outI = __SMLSDX(*__SIMD32(pCoefA), *__SIMD32(pSrc1)++, -outI);
+
+#else
+
+ outI = __SMLSDX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), -outI);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+ /* write output */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+ *__SIMD32(pDst1)++ = __PKHBT(outR, (outI >> 15u), 16);
+
+#else
+
+ *__SIMD32(pDst1)++ = __PKHBT((outI >> 15u), outR, 16);
+
+#endif /* #ifndef ARM_MATH_BIG_ENDIAN */
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (2u * modifier);
+ pCoefA = pCoefA + (2u * modifier);
+
+ i--;
+
+ }
+
+
+#else
+
+ /* Run the below code for Cortex-M0 */
+
+ i = fftLen;
+
+ while(i > 0u)
+ {
+
+ /*
+ outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ outR = *pSrc2 * *pCoefB;
+ outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1));
+ outR = outR + (*pSrc1 * *pCoefA);
+ outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 15;
+
+ /*
+ outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+ */
+
+ outI = *(pSrc1 + 1) * *pCoefA;
+ outI = outI - (*pSrc1 * *(pCoefA + 1));
+ outI = outI - (*pSrc2 * *(pCoefB + 1));
+ outI = outI - (*(pSrc2 + 1) * *(pCoefB));
+
+ /* update input pointers */
+ pSrc1 += 2u;
+ pSrc2 -= 2u;
+
+ /* write output */
+ *pDst1++ = (q15_t) outR;
+ *pDst1++ = (q15_t) (outI >> 15);
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (2u * modifier);
+ pCoefA = pCoefA + (2u * modifier);
+
+ i--;
+
+ }
+
+#endif /* #ifndef ARM_MATH_CM0_FAMILY */
+
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_q31.c b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_q31.c
new file mode 100644
index 000000000..488cbd9a5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/TransformFunctions/arm_rfft_q31.c
@@ -0,0 +1,349 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_rfft_q31.c
+*
+* Description: RFFT & RIFFT Q31 process function
+*
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+void arm_radix4_butterfly_inverse_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint32_t twidCoefModifier);
+
+void arm_radix4_butterfly_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+q31_t * pCoef,
+uint32_t twidCoefModifier);
+
+void arm_bitreversal_q31(
+q31_t * pSrc,
+uint32_t fftLen,
+uint16_t bitRevFactor,
+uint16_t * pBitRevTab);
+
+/*--------------------------------------------------------------------
+* Internal functions prototypes
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pATable,
+ q31_t * pBTable,
+ q31_t * pDst,
+ uint32_t modifier);
+
+void arm_split_rifft_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pATable,
+ q31_t * pBTable,
+ q31_t * pDst,
+ uint32_t modifier);
+
+/**
+ * @addtogroup RealFFT
+ * @{
+ */
+
+/**
+ * @brief Processing function for the Q31 RFFT/RIFFT.
+ * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure.
+ * @param[in] *pSrc points to the input buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @return none.
+ *
+ * \par Input an output formats:
+ * \par
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.
+ * Hence the output format is different for different RFFT sizes.
+ * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:
+ * \par
+ * \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT"
+ *
+ * \par
+ * \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT"
+ */
+
+void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst)
+{
+ const arm_cfft_radix4_instance_q31 *S_CFFT = S->pCfft;
+
+ /* Calculation of RIFFT of input */
+ if(S->ifftFlagR == 1u)
+ {
+ /* Real IFFT core process */
+ arm_split_rifft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+ /* Complex readix-4 IFFT process */
+ arm_radix4_butterfly_inverse_q31(pDst, S_CFFT->fftLen,
+ S_CFFT->pTwiddle,
+ S_CFFT->twidCoefModifier);
+ /* Bit reversal process */
+ if(S->bitReverseFlagR == 1u)
+ {
+ arm_bitreversal_q31(pDst, S_CFFT->fftLen,
+ S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+ }
+ else
+ {
+ /* Calculation of RFFT of input */
+
+ /* Complex readix-4 FFT process */
+ arm_radix4_butterfly_q31(pSrc, S_CFFT->fftLen,
+ S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+ /* Bit reversal process */
+ if(S->bitReverseFlagR == 1u)
+ {
+ arm_bitreversal_q31(pSrc, S_CFFT->fftLen,
+ S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+ }
+
+ /* Real FFT core process */
+ arm_split_rfft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+ S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+ }
+
+}
+
+
+ /**
+ * @} end of RealFFT group
+ */
+
+/**
+ * @brief Core Real FFT process
+ * @param[in] *pSrc points to the input buffer.
+ * @param[in] fftLen length of FFT.
+ * @param[in] *pATable points to the twiddle Coef A buffer.
+ * @param[in] *pBTable points to the twiddle Coef B buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_split_rfft_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pATable,
+ q31_t * pBTable,
+ q31_t * pDst,
+ uint32_t modifier)
+{
+ uint32_t i; /* Loop Counter */
+ q31_t outR, outI; /* Temporary variables for output */
+ q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
+ q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[(4u * fftLen) - 1u];
+ q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[(2u * fftLen) - 1u];
+
+ /* Init coefficient pointers */
+ pCoefA = &pATable[modifier * 2u];
+ pCoefB = &pBTable[modifier * 2u];
+
+ i = fftLen - 1u;
+
+ while(i > 0u)
+ {
+ /*
+ outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]
+ + pSrc[2 * n - 2 * i] * pBTable[2 * i] +
+ pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+ */
+
+ /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+ CoefA1 = *pCoefA++;
+ CoefA2 = *pCoefA;
+
+ /* outR = (pSrc[2 * i] * pATable[2 * i] */
+ outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));
+
+ /* outI = pIn[2 * i] * pATable[2 * i + 1] */
+ outI = ((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));
+
+ /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+ outR =
+ (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (-CoefA2))) >> 32);
+
+ /* (pIn[2 * i + 1] * pATable[2 * i] */
+ outI =
+ (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);
+
+ /* pSrc[2 * n - 2 * i] * pBTable[2 * i] */
+ outR =
+ (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (-CoefA2))) >> 32);
+ CoefB1 = *pCoefB;
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+ outI =
+ (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefB1))) >> 32);
+
+ /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+ outR =
+ (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);
+
+ /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+ outI =
+ (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefA2))) >> 32);
+
+ /* write output */
+ *pOut1++ = (outR << 1u);
+ *pOut1++ = (outI << 1u);
+
+ /* write complex conjugate output */
+ *pOut2-- = -(outI << 1u);
+ *pOut2-- = (outR << 1u);
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (modifier * 2u);
+ pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+ i--;
+
+ }
+
+ pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+ pDst[(2u * fftLen) + 1u] = 0;
+
+ pDst[0] = pSrc[0] + pSrc[1];
+ pDst[1] = 0;
+
+}
+
+
+/**
+ * @brief Core Real IFFT process
+ * @param[in] *pSrc points to the input buffer.
+ * @param[in] fftLen length of FFT.
+ * @param[in] *pATable points to the twiddle Coef A buffer.
+ * @param[in] *pBTable points to the twiddle Coef B buffer.
+ * @param[out] *pDst points to the output buffer.
+ * @param[in] modifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+ * @return none.
+ */
+
+void arm_split_rifft_q31(
+ q31_t * pSrc,
+ uint32_t fftLen,
+ q31_t * pATable,
+ q31_t * pBTable,
+ q31_t * pDst,
+ uint32_t modifier)
+{
+ q31_t outR, outI; /* Temporary variables for output */
+ q31_t *pCoefA, *pCoefB; /* Temporary pointers for twiddle factors */
+ q31_t CoefA1, CoefA2, CoefB1; /* Temporary variables for twiddle coefficients */
+ q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[(2u * fftLen) + 1u];
+
+ pCoefA = &pATable[0];
+ pCoefB = &pBTable[0];
+
+ while(fftLen > 0u)
+ {
+ /*
+ outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +
+ pIn[2 * n - 2 * i] * pBTable[2 * i] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);
+
+ outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -
+ pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -
+ pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);
+
+ */
+ CoefA1 = *pCoefA++;
+ CoefA2 = *pCoefA;
+
+ /* outR = (pIn[2 * i] * pATable[2 * i] */
+ outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));
+
+ /* - pIn[2 * i] * pATable[2 * i + 1] */
+ outI = -((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));
+
+ /* pIn[2 * i + 1] * pATable[2 * i + 1] */
+ outR =
+ (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (CoefA2))) >> 32);
+
+ /* pIn[2 * i + 1] * pATable[2 * i] */
+ outI =
+ (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i] */
+ outR =
+ (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefA2))) >> 32);
+
+ CoefB1 = *pCoefB;
+
+ /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+ outI =
+ (q31_t) ((((q63_t) outI << 32) - ((q63_t) * pIn2-- * (CoefB1))) >> 32);
+
+ /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+ outR =
+ (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);
+
+ /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+ outI =
+ (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (CoefA2))) >> 32);
+
+ /* write output */
+ *pDst++ = (outR << 1u);
+ *pDst++ = (outI << 1u);
+
+ /* update coefficient pointer */
+ pCoefB = pCoefB + (modifier * 2u);
+ pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+ /* Decrement loop count */
+ fftLen--;
+
+ }
+
+
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/arm_common_tables.h b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/arm_common_tables.h
new file mode 100644
index 000000000..7a59b5923
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/arm_common_tables.h
@@ -0,0 +1,93 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_common_tables.h
+*
+* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoefQ31[6144];
+extern const q15_t twiddleCoefQ15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+#endif /* ARM_COMMON_TABLES_H */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/arm_math.h b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/arm_math.h
new file mode 100644
index 000000000..0b7c6902b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/arm_math.h
@@ -0,0 +1,7304 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.1
+*
+* Project: CMSIS DSP Library
+* Title: arm_math.h
+*
+* Description: Public header file for CMSIS DSP Library
+*
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+ * -------------------------------------------------------------------- */
+
+/**
+ \mainpage CMSIS DSP Software Library
+ *
+ * <b>Introduction</b>
+ *
+ * This user manual describes the CMSIS DSP software library,
+ * a suite of common signal processing functions for use on Cortex-M processor based devices.
+ *
+ * The library is divided into a number of functions each covering a specific category:
+ * - Basic math functions
+ * - Fast math functions
+ * - Complex math functions
+ * - Filters
+ * - Matrix functions
+ * - Transforms
+ * - Motor control functions
+ * - Statistical functions
+ * - Support functions
+ * - Interpolation functions
+ *
+ * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+ * 32-bit integer and 32-bit floating-point values.
+ *
+ * <b>Using the Library</b>
+ *
+ * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
+ * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+ * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+ * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+ * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+ * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+ *
+ * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
+ * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
+ * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
+ *
+ * <b>Examples</b>
+ *
+ * The library ships with a number of examples which demonstrate how to use the library functions.
+ *
+ * <b>Toolchain Support</b>
+ *
+ * The library has been developed and tested with MDK-ARM version 4.60.
+ * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+ *
+ * <b>Building the Library</b>
+ *
+ * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
+ * - arm_cortexM0b_math.uvproj
+ * - arm_cortexM0l_math.uvproj
+ * - arm_cortexM3b_math.uvproj
+ * - arm_cortexM3l_math.uvproj
+ * - arm_cortexM4b_math.uvproj
+ * - arm_cortexM4l_math.uvproj
+ * - arm_cortexM4bf_math.uvproj
+ * - arm_cortexM4lf_math.uvproj
+ *
+ *
+ * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
+ *
+ * <b>Pre-processor Macros</b>
+ *
+ * Each library project have differant pre-processor macros.
+ *
+ * - UNALIGNED_SUPPORT_DISABLE:
+ *
+ * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
+ *
+ * - ARM_MATH_BIG_ENDIAN:
+ *
+ * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+ *
+ * - ARM_MATH_MATRIX_CHECK:
+ *
+ * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
+ *
+ * - ARM_MATH_ROUNDING:
+ *
+ * Define macro ARM_MATH_ROUNDING for rounding on support functions
+ *
+ * - ARM_MATH_CMx:
+ *
+ * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+ * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+ *
+ * - __FPU_PRESENT:
+ *
+ * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
+ *
+ * <b>Copyright Notice</b>
+ *
+ * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+ */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures. For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows; // number of rows of the matrix.
+ * uint16_t numCols; // number of columns of the matrix.
+ * float32_t *pData; // points to the data of the matrix.
+ * } arm_matrix_instance_f32;
+ * </pre>
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data. The array is of size <code>numRows X numCols</code>
+ * and the values are arranged in row order. That is, the
+ * matrix element (i, j) is stored at:
+ * <pre>
+ * pData[i*numCols + j]
+ * </pre>
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
+ * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure. For example:
+ * <pre>
+ * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
+ * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
+ * </pre>
+ * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
+ * specifies the number of columns, and <code>pData</code> points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices. For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns. If the size check fails the functions return:
+ * <pre>
+ * ARM_MATH_SIZE_MISMATCH
+ * </pre>
+ * Otherwise the functions return
+ * <pre>
+ * ARM_MATH_SUCCESS
+ * </pre>
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the \#define
+ * <pre>
+ * ARM_MATH_MATRIX_CHECK
+ * </pre>
+ * within the library project settings. By default this macro is defined
+ * and size checking is enabled. By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster. With size checking disabled the functions always
+ * return <code>ARM_MATH_SUCCESS</code>.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+#include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+#include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+#include "core_cm0.h"
+#define ARM_MATH_CM0_FAMILY
+#elif defined (ARM_MATH_CM0PLUS)
+#include "core_cm0plus.h"
+#define ARM_MATH_CM0_FAMILY
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
+#include "string.h"
+#include "math.h"
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+ /**
+ * @brief Macros required for reciprocal calculation in Normalized LMS
+ */
+
+#define DELTA_Q31 (0x100)
+#define DELTA_Q15 0x5
+#define INDEX_MASK 0x0000003F
+#ifndef PI
+#define PI 3.14159265358979f
+#endif
+
+ /**
+ * @brief Macros required for SINE and COSINE Fast math approximations
+ */
+
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x800000
+#define TABLE_SPACING_Q15 0x80
+
+ /**
+ * @brief Macros required for SINE and COSINE Controller functions
+ */
+ /* 1.31(q31) Fixed value of 2/360 */
+ /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING 0xB60B61
+
+ /**
+ * @brief Macro for Unaligned Support
+ */
+#ifndef UNALIGNED_SUPPORT_DISABLE
+ #define ALIGN4
+#else
+ #if defined (__GNUC__)
+ #define ALIGN4 __attribute__((aligned(4)))
+ #else
+ #define ALIGN4 __align(4)
+ #endif
+#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
+
+ /**
+ * @brief Error status returned by some functions in the library.
+ */
+
+ typedef enum
+ {
+ ARM_MATH_SUCCESS = 0, /**< No error */
+ ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
+ ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
+ ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
+ ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
+ ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+ ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
+ } arm_status;
+
+ /**
+ * @brief 8-bit fractional data type in 1.7 format.
+ */
+ typedef int8_t q7_t;
+
+ /**
+ * @brief 16-bit fractional data type in 1.15 format.
+ */
+ typedef int16_t q15_t;
+
+ /**
+ * @brief 32-bit fractional data type in 1.31 format.
+ */
+ typedef int32_t q31_t;
+
+ /**
+ * @brief 64-bit fractional data type in 1.63 format.
+ */
+ typedef int64_t q63_t;
+
+ /**
+ * @brief 32-bit floating-point type definition.
+ */
+ typedef float float32_t;
+
+ /**
+ * @brief 64-bit floating-point type definition.
+ */
+ typedef double float64_t;
+
+ /**
+ * @brief definition to read/write two 16 bit values.
+ */
+#if defined __CC_ARM
+#define __SIMD32_TYPE int32_t __packed
+#define CMSIS_UNUSED __attribute__((unused))
+#elif defined __ICCARM__
+#define CMSIS_UNUSED
+#define __SIMD32_TYPE int32_t __packed
+#elif defined __GNUC__
+#define __SIMD32_TYPE int32_t
+#define CMSIS_UNUSED __attribute__((unused))
+#else
+#error Unknown compiler
+#endif
+
+#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
+#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
+
+#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
+
+#define __SIMD64(addr) (*(int64_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+ /**
+ * @brief definition to pack two 16 bit values.
+ */
+#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
+ (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
+#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
+ (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
+
+#endif
+
+
+ /**
+ * @brief definition to pack four 8 bit values.
+ */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
+#else
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
+ (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
+ (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
+ (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
+
+#endif
+
+
+ /**
+ * @brief Clips Q63 to Q31 values.
+ */
+ static __INLINE q31_t clip_q63_to_q31(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+ }
+
+ /**
+ * @brief Clips Q63 to Q15 values.
+ */
+ static __INLINE q15_t clip_q63_to_q15(
+ q63_t x)
+ {
+ return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+ }
+
+ /**
+ * @brief Clips Q31 to Q7 values.
+ */
+ static __INLINE q7_t clip_q31_to_q7(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+ ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+ }
+
+ /**
+ * @brief Clips Q31 to Q15 values.
+ */
+ static __INLINE q15_t clip_q31_to_q15(
+ q31_t x)
+ {
+ return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+ ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+ }
+
+ /**
+ * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+ */
+
+ static __INLINE q63_t mult32x64(
+ q63_t x,
+ q31_t y)
+ {
+ return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+ (((q63_t) (x >> 32) * y)));
+ }
+
+
+#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+#define __CLZ __clz
+#elif defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data);
+
+
+ static __INLINE uint32_t __CLZ(
+ q31_t data)
+ {
+ uint32_t count = 0;
+ uint32_t mask = 0x80000000;
+
+ while((data & mask) == 0)
+ {
+ count += 1u;
+ mask = mask >> 1u;
+ }
+
+ return (count);
+
+ }
+
+#endif
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
+ */
+
+ static __INLINE uint32_t arm_recip_q31(
+ q31_t in,
+ q31_t * dst,
+ q31_t * pRecipTable)
+ {
+
+ uint32_t out, tempVal;
+ uint32_t index, i;
+ uint32_t signBits;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 1;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 1;
+ }
+
+ /* Convert input sample to 1.31 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = (uint32_t) (in >> 24u);
+ index = (index & INDEX_MASK);
+
+ /* 1.31 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0u; i < 2u; i++)
+ {
+ tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+ tempVal = 0x7FFFFFFF - tempVal;
+ /* 1.31 with exp 1 */
+ //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+ out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1u);
+
+ }
+
+ /**
+ * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
+ */
+ static __INLINE uint32_t arm_recip_q15(
+ q15_t in,
+ q15_t * dst,
+ q15_t * pRecipTable)
+ {
+
+ uint32_t out = 0, tempVal = 0;
+ uint32_t index = 0, i = 0;
+ uint32_t signBits = 0;
+
+ if(in > 0)
+ {
+ signBits = __CLZ(in) - 17;
+ }
+ else
+ {
+ signBits = __CLZ(-in) - 17;
+ }
+
+ /* Convert input sample to 1.15 format */
+ in = in << signBits;
+
+ /* calculation of index for initial approximated Val */
+ index = in >> 8;
+ index = (index & INDEX_MASK);
+
+ /* 1.15 with exp 1 */
+ out = pRecipTable[index];
+
+ /* calculation of reciprocal value */
+ /* running approximation for two iterations */
+ for (i = 0; i < 2; i++)
+ {
+ tempVal = (q15_t) (((q31_t) in * out) >> 15);
+ tempVal = 0x7FFF - tempVal;
+ /* 1.15 with exp 1 */
+ out = (q15_t) (((q31_t) out * tempVal) >> 14);
+ }
+
+ /* write output */
+ *dst = out;
+
+ /* return num of signbits of out = 1/in value */
+ return (signBits + 1);
+
+ }
+
+
+ /*
+ * @brief C custom defined intrinisic function for only M0 processors
+ */
+#if defined(ARM_MATH_CM0_FAMILY)
+
+ static __INLINE q31_t __SSAT(
+ q31_t x,
+ uint32_t y)
+ {
+ int32_t posMax, negMin;
+ uint32_t i;
+
+ posMax = 1;
+ for (i = 0; i < (y - 1); i++)
+ {
+ posMax = posMax * 2;
+ }
+
+ if(x > 0)
+ {
+ posMax = (posMax - 1);
+
+ if(x > posMax)
+ {
+ x = posMax;
+ }
+ }
+ else
+ {
+ negMin = -posMax;
+
+ if(x < negMin)
+ {
+ x = negMin;
+ }
+ }
+ return (x);
+
+
+ }
+
+#endif /* end of ARM_MATH_CM0_FAMILY */
+
+
+
+ /*
+ * @brief C custom defined intrinsic function for M3 and M0 processors
+ */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
+
+ /*
+ * @brief C custom defined QADD8 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q7_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((q31_t) (r + s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+ t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+ u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+ sum =
+ (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+ (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB8 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB8(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s, t, u;
+
+ r = (q7_t) x;
+ s = (q7_t) y;
+
+ r = __SSAT((r - s), 8);
+ s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+ t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+ u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+ sum =
+ (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
+ 0x000000FF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+
+ /*
+ * @brief C custom defined QADD16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r + s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined SHADD16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHADD16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (s >> 1));
+ s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+
+ }
+
+ /*
+ * @brief C custom defined QSUB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = __SSAT(r - s, 16);
+ s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSUB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHSUB16(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t diff;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (s >> 1));
+ s = (((x >> 17) - (y >> 17)) << 16);
+
+ diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return diff;
+ }
+
+ /*
+ * @brief C custom defined QASX for M3 and M0 processors
+ */
+ static __INLINE q31_t __QASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHASX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHASX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) - (y >> 17));
+ s = (((x >> 17) + (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+
+ /*
+ * @brief C custom defined QSAX for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum = 0;
+
+ sum =
+ ((sum +
+ clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SHSAX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SHSAX(
+ q31_t x,
+ q31_t y)
+ {
+
+ q31_t sum;
+ q31_t r, s;
+
+ r = (short) x;
+ s = (short) y;
+
+ r = ((r >> 1) + (y >> 17));
+ s = (((x >> 17) - (s >> 1)) << 16);
+
+ sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+ return sum;
+ }
+
+ /*
+ * @brief C custom defined SMUSDX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUSDX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((short) x * (short) (y >> 16)) -
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined SMUADX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUADX(
+ q31_t x,
+ q31_t y)
+ {
+
+ return ((q31_t) (((short) x * (short) (y >> 16)) +
+ ((short) (x >> 16) * (short) y)));
+ }
+
+ /*
+ * @brief C custom defined QADD for M3 and M0 processors
+ */
+ static __INLINE q31_t __QADD(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x + y);
+ }
+
+ /*
+ * @brief C custom defined QSUB for M3 and M0 processors
+ */
+ static __INLINE q31_t __QSUB(
+ q31_t x,
+ q31_t y)
+ {
+ return clip_q63_to_q31((q63_t) x - y);
+ }
+
+ /*
+ * @brief C custom defined SMLAD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLAD(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLADX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLADX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLSDX for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMLSDX(
+ q31_t x,
+ q31_t y,
+ q31_t sum)
+ {
+
+ return (sum - ((short) (x >> 16) * (short) (y)) +
+ ((short) x * (short) (y >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMLALD for M3 and M0 processors
+ */
+ static __INLINE q63_t __SMLALD(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+ ((short) x * (short) y));
+ }
+
+ /*
+ * @brief C custom defined SMLALDX for M3 and M0 processors
+ */
+ static __INLINE q63_t __SMLALDX(
+ q31_t x,
+ q31_t y,
+ q63_t sum)
+ {
+
+ return (sum + ((short) (x >> 16) * (short) y)) +
+ ((short) x * (short) (y >> 16));
+ }
+
+ /*
+ * @brief C custom defined SMUAD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUAD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+ /*
+ * @brief C custom defined SMUSD for M3 and M0 processors
+ */
+ static __INLINE q31_t __SMUSD(
+ q31_t x,
+ q31_t y)
+ {
+
+ return (-((x >> 16) * (y >> 16)) +
+ (((x << 16) >> 16) * ((y << 16) >> 16)));
+ }
+
+
+ /*
+ * @brief C custom defined SXTB16 for M3 and M0 processors
+ */
+ static __INLINE q31_t __SXTB16(
+ q31_t x)
+ {
+
+ return ((((x << 24) >> 24) & 0x0000FFFF) |
+ (((x << 8) >> 8) & 0xFFFF0000));
+ }
+
+
+#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
+
+
+ /**
+ * @brief Instance structure for the Q7 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q7;
+
+ /**
+ * @brief Instance structure for the Q15 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ } arm_fir_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of filter coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ } arm_fir_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q7 FIR filter.
+ * @param[in] *S points to an instance of the Q7 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q7(
+ const arm_fir_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q7 FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed.
+ * @return none
+ */
+ void arm_fir_init_q7(
+ arm_fir_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR filter.
+ * @param[in] *S points to an instance of the Q15 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q15(
+ const arm_fir_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+ * <code>numTaps</code> is not a supported value.
+ */
+
+ arm_status arm_fir_init_q15(
+ arm_fir_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR filter.
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_fast_q31(
+ const arm_fir_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 FIR structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_q31(
+ arm_fir_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point FIR filter.
+ * @param[in] *S points to an instance of the floating-point FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_f32(
+ const arm_fir_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+ * @param[in] numTaps Number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of samples that are processed at a time.
+ * @return none.
+ */
+ void arm_fir_init_f32(
+ arm_fir_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q15 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q15;
+
+
+ /**
+ * @brief Instance structure for the Q31 Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_casd_df1_inst_q31;
+
+ /**
+ * @brief Instance structure for the floating-point Biquad cascade filter.
+ */
+ typedef struct
+ {
+ uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
+
+
+ } arm_biquad_casd_df1_inst_f32;
+
+
+
+ /**
+ * @brief Processing function for the Q15 Biquad cascade filter.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q15 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q15(
+ arm_biquad_casd_df1_inst_q15 * S,
+ uint8_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int8_t postShift);
+
+
+ /**
+ * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q15(
+ const arm_biquad_casd_df1_inst_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 Biquad cascade filter
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_fast_q31(
+ const arm_biquad_casd_df1_inst_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_q31(
+ arm_biquad_casd_df1_inst_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int8_t postShift);
+
+ /**
+ * @brief Processing function for the floating-point Biquad cascade filter.
+ * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df1_f32(
+ const arm_biquad_casd_df1_inst_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df1_init_f32(
+ arm_biquad_casd_df1_inst_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float32_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q15 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q15_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ q31_t *pData; /**< points to the data of the matrix. */
+
+ } arm_matrix_instance_q31;
+
+
+
+ /**
+ * @brief Floating-point matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix addition.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_add_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ arm_matrix_instance_f32 * pDst);
+
+
+ /**
+ * @brief Q15 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix transpose.
+ * @param[in] *pSrc points to the input matrix
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
+ * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_trans_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @param[in] *pState points to the array for storing intermediate results
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pState);
+
+ /**
+ * @brief Q31 matrix multiplication
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_mult_fast_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Floating-point matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix subtraction
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_sub_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
+ /**
+ * @brief Floating-point matrix scaling.
+ * @param[in] *pSrc points to the input matrix
+ * @param[in] scale scale factor
+ * @param[out] *pDst points to the output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_f32(
+ const arm_matrix_instance_f32 * pSrc,
+ float32_t scale,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q15(
+ const arm_matrix_instance_q15 * pSrc,
+ q15_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q15 * pDst);
+
+ /**
+ * @brief Q31 matrix scaling.
+ * @param[in] *pSrc points to input matrix
+ * @param[in] scaleFract fractional portion of the scale factor
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_scale_q31(
+ const arm_matrix_instance_q31 * pSrc,
+ q31_t scaleFract,
+ int32_t shift,
+ arm_matrix_instance_q31 * pDst);
+
+
+ /**
+ * @brief Q31 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q31(
+ arm_matrix_instance_q31 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q31_t * pData);
+
+ /**
+ * @brief Q15 matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_q15(
+ arm_matrix_instance_q15 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ q15_t * pData);
+
+ /**
+ * @brief Floating-point matrix initialization.
+ * @param[in,out] *S points to an instance of the floating-point matrix structure.
+ * @param[in] nRows number of rows in the matrix.
+ * @param[in] nColumns number of columns in the matrix.
+ * @param[in] *pData points to the matrix data array.
+ * @return none
+ */
+
+ void arm_mat_init_f32(
+ arm_matrix_instance_f32 * S,
+ uint16_t nRows,
+ uint16_t nColumns,
+ float32_t * pData);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 PID Control.
+ */
+ typedef struct
+ {
+ q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+#ifdef ARM_MATH_CM0_FAMILY
+ q15_t A1;
+ q15_t A2;
+#else
+ q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+#endif
+ q15_t state[3]; /**< The state array of length 3. */
+ q15_t Kp; /**< The proportional gain. */
+ q15_t Ki; /**< The integral gain. */
+ q15_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 PID Control.
+ */
+ typedef struct
+ {
+ q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ q31_t A2; /**< The derived gain, A2 = Kd . */
+ q31_t state[3]; /**< The state array of length 3. */
+ q31_t Kp; /**< The proportional gain. */
+ q31_t Ki; /**< The integral gain. */
+ q31_t Kd; /**< The derivative gain. */
+
+ } arm_pid_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point PID Control.
+ */
+ typedef struct
+ {
+ float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
+ float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
+ float32_t A2; /**< The derived gain, A2 = Kd . */
+ float32_t state[3]; /**< The state array of length 3. */
+ float32_t Kp; /**< The proportional gain. */
+ float32_t Ki; /**< The integral gain. */
+ float32_t Kd; /**< The derivative gain. */
+ } arm_pid_instance_f32;
+
+
+
+ /**
+ * @brief Initialization function for the floating-point PID Control.
+ * @param[in,out] *S points to an instance of the PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_f32(
+ arm_pid_instance_f32 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_f32(
+ arm_pid_instance_f32 * S);
+
+
+ /**
+ * @brief Initialization function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q31(
+ arm_pid_instance_q31 * S,
+ int32_t resetStateFlag);
+
+
+ /**
+ * @brief Reset function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @return none
+ */
+
+ void arm_pid_reset_q31(
+ arm_pid_instance_q31 * S);
+
+ /**
+ * @brief Initialization function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID structure.
+ * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
+ * @return none.
+ */
+ void arm_pid_init_q15(
+ arm_pid_instance_q15 * S,
+ int32_t resetStateFlag);
+
+ /**
+ * @brief Reset function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the q15 PID Control structure
+ * @return none
+ */
+ void arm_pid_reset_q15(
+ arm_pid_instance_q15 * S);
+
+
+ /**
+ * @brief Instance structure for the floating-point Linear Interpolate function.
+ */
+ typedef struct
+ {
+ uint32_t nValues; /**< nValues */
+ float32_t x1; /**< x1 */
+ float32_t xSpacing; /**< xSpacing */
+ float32_t *pYData; /**< pointer to the table of Y values */
+ } arm_linear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ float32_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q31_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q15_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q15 bilinear interpolation function.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows in the data table. */
+ uint16_t numCols; /**< number of columns in the data table. */
+ q7_t *pData; /**< points to the data table. */
+ } arm_bilinear_interp_instance_q7;
+
+
+ /**
+ * @brief Q7 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector multiplication.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_mult_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q15;
+
+ arm_status arm_cfft_radix2_init_q15(
+ arm_cfft_radix2_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ void arm_cfft_radix2_q15(
+ const arm_cfft_radix2_instance_q15 * S,
+ q15_t * pSrc);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q15;
+
+ arm_status arm_cfft_radix4_init_q15(
+ arm_cfft_radix4_instance_q15 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ void arm_cfft_radix4_q15(
+ const arm_cfft_radix4_instance_q15 * S,
+ q15_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix2_instance_q31;
+
+ arm_status arm_cfft_radix2_init_q31(
+ arm_cfft_radix2_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ void arm_cfft_radix2_q31(
+ const arm_cfft_radix2_instance_q31 * S,
+ q31_t * pSrc);
+
+ /**
+ * @brief Instance structure for the Q31 CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ } arm_cfft_radix4_instance_q31;
+
+
+ void arm_cfft_radix4_q31(
+ const arm_cfft_radix4_instance_q31 * S,
+ q31_t * pSrc);
+
+ arm_status arm_cfft_radix4_init_q31(
+ arm_cfft_radix4_instance_q31 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix2_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix2_init_f32(
+ arm_cfft_radix2_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix2_f32(
+ const arm_cfft_radix2_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+ uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+ float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+ float32_t onebyfftLen; /**< value of 1/fftLen. */
+ } arm_cfft_radix4_instance_f32;
+
+/* Deprecated */
+ arm_status arm_cfft_radix4_init_f32(
+ arm_cfft_radix4_instance_f32 * S,
+ uint16_t fftLen,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+/* Deprecated */
+ void arm_cfft_radix4_f32(
+ const arm_cfft_radix4_instance_f32 * S,
+ float32_t * pSrc);
+
+ /**
+ * @brief Instance structure for the floating-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_f32;
+
+ void arm_cfft_f32(
+ const arm_cfft_instance_f32 * S,
+ float32_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the Q15 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q15;
+
+ arm_status arm_rfft_init_q15(
+ arm_rfft_instance_q15 * S,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q15(
+ const arm_rfft_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst);
+
+ /**
+ * @brief Instance structure for the Q31 RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint32_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_q31;
+
+ arm_status arm_rfft_init_q31(
+ arm_rfft_instance_q31 * S,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_q31(
+ const arm_rfft_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+ typedef struct
+ {
+ uint32_t fftLenReal; /**< length of the real FFT. */
+ uint16_t fftLenBy2; /**< length of the complex FFT. */
+ uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+ float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
+ float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_rfft_instance_f32;
+
+ arm_status arm_rfft_init_f32(
+ arm_rfft_instance_f32 * S,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint32_t fftLenReal,
+ uint32_t ifftFlagR,
+ uint32_t bitReverseFlag);
+
+ void arm_rfft_f32(
+ const arm_rfft_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst);
+
+ /**
+ * @brief Instance structure for the floating-point RFFT/RIFFT function.
+ */
+
+typedef struct
+ {
+ arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
+ uint16_t fftLenRFFT; /**< length of the real sequence */
+ float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
+ } arm_rfft_fast_instance_f32 ;
+
+arm_status arm_rfft_fast_init_f32 (
+ arm_rfft_fast_instance_f32 * S,
+ uint16_t fftLen);
+
+void arm_rfft_fast_f32(
+ arm_rfft_fast_instance_f32 * S,
+ float32_t * p, float32_t * pOut,
+ uint8_t ifftFlag);
+
+ /**
+ * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ float32_t normalize; /**< normalizing factor. */
+ float32_t *pTwiddle; /**< points to the twiddle factor table. */
+ float32_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_f32;
+
+ /**
+ * @brief Initialization function for the floating-point DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_f32(
+ arm_dct4_instance_f32 * S,
+ arm_rfft_instance_f32 * S_RFFT,
+ arm_cfft_radix4_instance_f32 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ float32_t normalize);
+
+ /**
+ * @brief Processing function for the floating-point DCT4/IDCT4.
+ * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_f32(
+ const arm_dct4_instance_f32 * S,
+ float32_t * pState,
+ float32_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q31_t normalize; /**< normalizing factor. */
+ q31_t *pTwiddle; /**< points to the twiddle factor table. */
+ q31_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q31;
+
+ /**
+ * @brief Initialization function for the Q31 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
+ * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q31(
+ arm_dct4_instance_q31 * S,
+ arm_rfft_instance_q31 * S_RFFT,
+ arm_cfft_radix4_instance_q31 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q31_t normalize);
+
+ /**
+ * @brief Processing function for the Q31 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q31 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q31(
+ const arm_dct4_instance_q31 * S,
+ q31_t * pState,
+ q31_t * pInlineBuffer);
+
+ /**
+ * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+ */
+
+ typedef struct
+ {
+ uint16_t N; /**< length of the DCT4. */
+ uint16_t Nby2; /**< half of the length of the DCT4. */
+ q15_t normalize; /**< normalizing factor. */
+ q15_t *pTwiddle; /**< points to the twiddle factor table. */
+ q15_t *pCosFactor; /**< points to the cosFactor table. */
+ arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
+ arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ } arm_dct4_instance_q15;
+
+ /**
+ * @brief Initialization function for the Q15 DCT4/IDCT4.
+ * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
+ * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
+ * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
+ * @param[in] N length of the DCT4.
+ * @param[in] Nby2 half of the length of the DCT4.
+ * @param[in] normalize normalizing factor.
+ * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
+ */
+
+ arm_status arm_dct4_init_q15(
+ arm_dct4_instance_q15 * S,
+ arm_rfft_instance_q15 * S_RFFT,
+ arm_cfft_radix4_instance_q15 * S_CFFT,
+ uint16_t N,
+ uint16_t Nby2,
+ q15_t normalize);
+
+ /**
+ * @brief Processing function for the Q15 DCT4/IDCT4.
+ * @param[in] *S points to an instance of the Q15 DCT4 structure.
+ * @param[in] *pState points to state buffer.
+ * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
+ * @return none.
+ */
+
+ void arm_dct4_q15(
+ const arm_dct4_instance_q15 * S,
+ q15_t * pState,
+ q15_t * pInlineBuffer);
+
+ /**
+ * @brief Floating-point vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector addition.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_add_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector subtraction.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_sub_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a floating-point vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scale scale factor to be applied
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_f32(
+ float32_t * pSrc,
+ float32_t scale,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q7 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q7(
+ q7_t * pSrc,
+ q7_t scaleFract,
+ int8_t shift,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q15 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q15(
+ q15_t * pSrc,
+ q15_t scaleFract,
+ int8_t shift,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Multiplies a Q31 vector by a scalar.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] scaleFract fractional portion of the scale value
+ * @param[in] shift number of bits to shift the result by
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_scale_q31(
+ q31_t * pSrc,
+ q31_t scaleFract,
+ int8_t shift,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q7 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Floating-point vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q15 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Q31 vector absolute value.
+ * @param[in] *pSrc points to the input buffer
+ * @param[out] *pDst points to the output buffer
+ * @param[in] blockSize number of samples in each vector
+ * @return none.
+ */
+
+ void arm_abs_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Dot product of floating-point vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t blockSize,
+ float32_t * result);
+
+ /**
+ * @brief Dot product of Q7 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q7(
+ q7_t * pSrcA,
+ q7_t * pSrcB,
+ uint32_t blockSize,
+ q31_t * result);
+
+ /**
+ * @brief Dot product of Q15 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Dot product of Q31 vectors.
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] blockSize number of samples in each vector
+ * @param[out] *result output result returned here
+ * @return none.
+ */
+
+ void arm_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t blockSize,
+ q63_t * result);
+
+ /**
+ * @brief Shifts the elements of a Q7 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q7(
+ q7_t * pSrc,
+ int8_t shiftBits,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q15 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q15(
+ q15_t * pSrc,
+ int8_t shiftBits,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Shifts the elements of a Q31 vector a specified number of bits.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_shift_q31(
+ q31_t * pSrc,
+ int8_t shiftBits,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_f32(
+ float32_t * pSrc,
+ float32_t offset,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q7(
+ q7_t * pSrc,
+ q7_t offset,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q15(
+ q15_t * pSrc,
+ q15_t offset,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Adds a constant offset to a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[in] offset is the offset to be added
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_offset_q31(
+ q31_t * pSrc,
+ q31_t offset,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a floating-point vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q7 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q15 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Negates the elements of a Q31 vector.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] blockSize number of samples in the vector
+ * @return none.
+ */
+
+ void arm_negate_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Copies the elements of a floating-point vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q7 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q7(
+ q7_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Copies the elements of a Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_copy_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+ /**
+ * @brief Fills a constant value into a floating-point vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_f32(
+ float32_t value,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q7 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q7(
+ q7_t value,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q15 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q15(
+ q15_t value,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Fills a constant value into a Q31 vector.
+ * @param[in] value input value to be filled
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_fill_q31(
+ q31_t value,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+
+ void arm_conv_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_conv_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+
+ /**
+ * @brief Convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
+ * @return none.
+ */
+
+ void arm_conv_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Partial convolution of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+ /**
+ * @brief Partial convolution of Q7 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+/**
+ * @brief Partial convolution of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] firstIndex is the first output sample to start with.
+ * @param[in] numPoints is the number of output points to be computed.
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+ */
+
+ arm_status arm_conv_partial_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ uint32_t firstIndex,
+ uint32_t numPoints);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ } arm_fir_decimate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR decimator.
+ */
+
+ typedef struct
+ {
+ uint8_t M; /**< decimation factor. */
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+ } arm_fir_decimate_instance_f32;
+
+
+
+ /**
+ * @brief Processing function for the floating-point FIR decimator.
+ * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_f32(
+ const arm_fir_decimate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point FIR decimator.
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+ arm_status arm_fir_decimate_init_f32(
+ arm_fir_decimate_instance_f32 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q15(
+ const arm_fir_decimate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+ arm_status arm_fir_decimate_init_q15(
+ arm_fir_decimate_instance_q15 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_q31(
+ const arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none
+ */
+
+ void arm_fir_decimate_fast_q31(
+ arm_fir_decimate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 FIR decimator.
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+ * @param[in] numTaps number of coefficients in the filter.
+ * @param[in] M decimation factor.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * <code>blockSize</code> is not a multiple of <code>M</code>.
+ */
+
+ arm_status arm_fir_decimate_init_q31(
+ arm_fir_decimate_instance_q31 * S,
+ uint16_t numTaps,
+ uint8_t M,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+ } arm_fir_interpolate_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR interpolator.
+ */
+
+ typedef struct
+ {
+ uint8_t L; /**< upsample factor. */
+ uint16_t phaseLength; /**< length of each polyphase filter component. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
+ float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+ } arm_fir_interpolate_instance_f32;
+
+
+ /**
+ * @brief Processing function for the Q15 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q15(
+ const arm_fir_interpolate_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+ arm_status arm_fir_interpolate_init_q15(
+ arm_fir_interpolate_instance_q15 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 FIR interpolator.
+ * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_q31(
+ const arm_fir_interpolate_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR interpolator.
+ * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+ arm_status arm_fir_interpolate_init_q31(
+ arm_fir_interpolate_instance_q31 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the floating-point FIR interpolator.
+ * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_interpolate_f32(
+ const arm_fir_interpolate_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point FIR interpolator.
+ * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
+ * @param[in] L upsample factor.
+ * @param[in] numTaps number of filter coefficients in the filter.
+ * @param[in] *pCoeffs points to the filter coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+ * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
+ */
+
+ arm_status arm_fir_interpolate_init_f32(
+ arm_fir_interpolate_instance_f32 * S,
+ uint8_t L,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
+
+ } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+ /**
+ * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cas_df1_32x64_q31(
+ const arm_biquad_cas_df1_32x64_ins_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
+ * @return none
+ */
+
+ void arm_biquad_cas_df1_32x64_init_q31(
+ arm_biquad_cas_df1_32x64_ins_q31 * S,
+ uint8_t numStages,
+ q31_t * pCoeffs,
+ q63_t * pState,
+ uint8_t postShift);
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f32;
+
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df2T_f32(
+ const arm_biquad_cascade_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df2T_init_f32(
+ arm_biquad_cascade_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+
+ /**
+ * @brief Instance structure for the Q15 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point FIR lattice filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numStages; /**< number of filter stages. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
+ } arm_fir_lattice_instance_f32;
+
+ /**
+ * @brief Initialization function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q15(
+ arm_fir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pCoeffs,
+ q15_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q15 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+ void arm_fir_lattice_q15(
+ const arm_fir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_q31(
+ arm_fir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pCoeffs,
+ q31_t * pState);
+
+
+ /**
+ * @brief Processing function for the Q31 FIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_q31(
+ const arm_fir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
+ * @param[in] *pState points to the state buffer. The array is of length numStages.
+ * @return none.
+ */
+
+ void arm_fir_lattice_init_f32(
+ arm_fir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+ /**
+ * @brief Processing function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_fir_lattice_f32(
+ const arm_fir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q31 IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_q31;
+
+ /**
+ * @brief Instance structure for the floating-point IIR lattice filter.
+ */
+ typedef struct
+ {
+ uint16_t numStages; /**< number of stages in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
+ float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
+ float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
+ } arm_iir_lattice_instance_f32;
+
+ /**
+ * @brief Processing function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_f32(
+ const arm_iir_lattice_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point IIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_f32(
+ arm_iir_lattice_instance_f32 * S,
+ uint16_t numStages,
+ float32_t * pkCoeffs,
+ float32_t * pvCoeffs,
+ float32_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q31(
+ const arm_iir_lattice_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q31 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q31(
+ arm_iir_lattice_instance_q31 * S,
+ uint16_t numStages,
+ q31_t * pkCoeffs,
+ q31_t * pvCoeffs,
+ q31_t * pState,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Processing function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_iir_lattice_q15(
+ const arm_iir_lattice_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
+ * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+ void arm_iir_lattice_init_q15(
+ arm_iir_lattice_instance_q15 * S,
+ uint16_t numStages,
+ q15_t * pkCoeffs,
+ q15_t * pvCoeffs,
+ q15_t * pState,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the floating-point LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that controls filter coefficient updates. */
+ } arm_lms_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_f32(
+ const arm_lms_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_init_f32(
+ arm_lms_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+ /**
+ * @brief Instance structure for the Q15 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+ } arm_lms_instance_q15;
+
+
+ /**
+ * @brief Initialization function for the Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to the coefficient buffer.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q15(
+ arm_lms_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Processing function for Q15 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q15(
+ const arm_lms_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint32_t postShift; /**< bit shift applied to coefficients. */
+
+ } arm_lms_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_q31(
+ const arm_lms_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 LMS filter.
+ * @param[in] *S points to an instance of the Q31 LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_init_q31(
+ arm_lms_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint32_t postShift);
+
+ /**
+ * @brief Instance structure for the floating-point normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ float32_t mu; /**< step size that control filter coefficient updates. */
+ float32_t energy; /**< saves previous frame energy. */
+ float32_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_f32;
+
+ /**
+ * @brief Processing function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_f32(
+ arm_lms_norm_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pRef,
+ float32_t * pOut,
+ float32_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for floating-point normalized LMS filter.
+ * @param[in] *S points to an instance of the floating-point LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_f32(
+ arm_lms_norm_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ float32_t mu,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Instance structure for the Q31 normalized LMS filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q31_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q31_t *recipTable; /**< points to the reciprocal initial value table. */
+ q31_t energy; /**< saves previous frame energy. */
+ q31_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q31;
+
+ /**
+ * @brief Processing function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q31(
+ arm_lms_norm_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pRef,
+ q31_t * pOut,
+ q31_t * pErr,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for Q31 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q31(
+ arm_lms_norm_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ q31_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Instance structure for the Q15 normalized LMS filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< Number of coefficients in the filter. */
+ q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
+ q15_t mu; /**< step size that controls filter coefficient updates. */
+ uint8_t postShift; /**< bit shift applied to coefficients. */
+ q15_t *recipTable; /**< Points to the reciprocal initial value table. */
+ q15_t energy; /**< saves previous frame energy. */
+ q15_t x0; /**< saves previous input sample. */
+ } arm_lms_norm_instance_q15;
+
+ /**
+ * @brief Processing function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[in] *pRef points to the block of reference data.
+ * @param[out] *pOut points to the block of output data.
+ * @param[out] *pErr points to the block of error data.
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_lms_norm_q15(
+ arm_lms_norm_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pRef,
+ q15_t * pOut,
+ q15_t * pErr,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for Q15 normalized LMS filter.
+ * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+ * @param[in] numTaps number of filter coefficients.
+ * @param[in] *pCoeffs points to coefficient buffer.
+ * @param[in] *pState points to state buffer.
+ * @param[in] mu step size that controls filter coefficient updates.
+ * @param[in] blockSize number of samples to process.
+ * @param[in] postShift bit shift applied to coefficients.
+ * @return none.
+ */
+
+ void arm_lms_norm_init_q15(
+ arm_lms_norm_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ q15_t mu,
+ uint32_t blockSize,
+ uint8_t postShift);
+
+ /**
+ * @brief Correlation of floating-point sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_f32(
+ float32_t * pSrcA,
+ uint32_t srcALen,
+ float32_t * pSrcB,
+ uint32_t srcBLen,
+ float32_t * pDst);
+
+
+ /**
+ * @brief Correlation of Q15 sequences
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+ void arm_correlate_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+
+ /**
+ * @brief Correlation of Q15 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @return none.
+ */
+
+ void arm_correlate_fast_opt_q15(
+ q15_t * pSrcA,
+ uint32_t srcALen,
+ q15_t * pSrcB,
+ uint32_t srcBLen,
+ q15_t * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Correlation of Q31 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+ /**
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_fast_q31(
+ q31_t * pSrcA,
+ uint32_t srcALen,
+ q31_t * pSrcB,
+ uint32_t srcBLen,
+ q31_t * pDst);
+
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
+ * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
+ * @return none.
+ */
+
+ void arm_correlate_opt_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst,
+ q15_t * pScratch1,
+ q15_t * pScratch2);
+
+
+ /**
+ * @brief Correlation of Q7 sequences.
+ * @param[in] *pSrcA points to the first input sequence.
+ * @param[in] srcALen length of the first input sequence.
+ * @param[in] *pSrcB points to the second input sequence.
+ * @param[in] srcBLen length of the second input sequence.
+ * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
+ * @return none.
+ */
+
+ void arm_correlate_q7(
+ q7_t * pSrcA,
+ uint32_t srcALen,
+ q7_t * pSrcB,
+ uint32_t srcBLen,
+ q7_t * pDst);
+
+
+ /**
+ * @brief Instance structure for the floating-point sparse FIR filter.
+ */
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_f32;
+
+ /**
+ * @brief Instance structure for the Q31 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q31;
+
+ /**
+ * @brief Instance structure for the Q15 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q15;
+
+ /**
+ * @brief Instance structure for the Q7 sparse FIR filter.
+ */
+
+ typedef struct
+ {
+ uint16_t numTaps; /**< number of coefficients in the filter. */
+ uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
+ q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+ q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
+ uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
+ int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
+ } arm_fir_sparse_instance_q7;
+
+ /**
+ * @brief Processing function for the floating-point sparse FIR filter.
+ * @param[in] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_f32(
+ arm_fir_sparse_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ float32_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the floating-point sparse FIR filter.
+ * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_f32(
+ arm_fir_sparse_instance_f32 * S,
+ uint16_t numTaps,
+ float32_t * pCoeffs,
+ float32_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q31 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q31(
+ arm_fir_sparse_instance_q31 * S,
+ q31_t * pSrc,
+ q31_t * pDst,
+ q31_t * pScratchIn,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q31 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q31(
+ arm_fir_sparse_instance_q31 * S,
+ uint16_t numTaps,
+ q31_t * pCoeffs,
+ q31_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q15 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q15(
+ arm_fir_sparse_instance_q15 * S,
+ q15_t * pSrc,
+ q15_t * pDst,
+ q15_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Initialization function for the Q15 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q15(
+ arm_fir_sparse_instance_q15 * S,
+ uint16_t numTaps,
+ q15_t * pCoeffs,
+ q15_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the Q7 sparse FIR filter.
+ * @param[in] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
+ * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
+ * @param[in] blockSize number of input samples to process per call.
+ * @return none.
+ */
+
+ void arm_fir_sparse_q7(
+ arm_fir_sparse_instance_q7 * S,
+ q7_t * pSrc,
+ q7_t * pDst,
+ q7_t * pScratchIn,
+ q31_t * pScratchOut,
+ uint32_t blockSize);
+
+ /**
+ * @brief Initialization function for the Q7 sparse FIR filter.
+ * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
+ * @param[in] numTaps number of nonzero coefficients in the filter.
+ * @param[in] *pCoeffs points to the array of filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @param[in] *pTapDelay points to the array of offset times.
+ * @param[in] maxDelay maximum offset time supported.
+ * @param[in] blockSize number of samples that will be processed per block.
+ * @return none
+ */
+
+ void arm_fir_sparse_init_q7(
+ arm_fir_sparse_instance_q7 * S,
+ uint16_t numTaps,
+ q7_t * pCoeffs,
+ q7_t * pState,
+ int32_t * pTapDelay,
+ uint16_t maxDelay,
+ uint32_t blockSize);
+
+
+ /*
+ * @brief Floating-point sin_cos function.
+ * @param[in] theta input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cos output.
+ * @return none.
+ */
+
+ void arm_sin_cos_f32(
+ float32_t theta,
+ float32_t * pSinVal,
+ float32_t * pCcosVal);
+
+ /*
+ * @brief Q31 sin_cos function.
+ * @param[in] theta scaled input value in degrees
+ * @param[out] *pSinVal points to the processed sine output.
+ * @param[out] *pCosVal points to the processed cosine output.
+ * @return none.
+ */
+
+ void arm_sin_cos_q31(
+ q31_t theta,
+ q31_t * pSinVal,
+ q31_t * pCosVal);
+
+
+ /**
+ * @brief Floating-point complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex conjugate.
+ * @param[in] *pSrc points to the input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_conj_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+
+ /**
+ * @brief Floating-point complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude squared
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_squared_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup PID PID Motor Control
+ *
+ * A Proportional Integral Derivative (PID) controller is a generic feedback control
+ * loop mechanism widely used in industrial control systems.
+ * A PID controller is the most commonly used type of feedback controller.
+ *
+ * This set of functions implements (PID) controllers
+ * for Q15, Q31, and floating-point data types. The functions operate on a single sample
+ * of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
+ * is the input sample value. The functions return the output value.
+ *
+ * \par Algorithm:
+ * <pre>
+ * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+ * A0 = Kp + Ki + Kd
+ * A1 = (-Kp ) - (2 * Kd )
+ * A2 = Kd </pre>
+ *
+ * \par
+ * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+ *
+ * \par
+ * \image html PID.gif "Proportional Integral Derivative Controller"
+ *
+ * \par
+ * The PID controller calculates an "error" value as the difference between
+ * the measured output and the reference input.
+ * The controller attempts to minimize the error by adjusting the process control inputs.
+ * The proportional value determines the reaction to the current error,
+ * the integral value determines the reaction based on the sum of recent errors,
+ * and the derivative value determines the reaction based on the rate at which the error has been changing.
+ *
+ * \par Instance Structure
+ * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
+ * A separate instance structure must be defined for each PID Controller.
+ * There are separate instance structure declarations for each of the 3 supported data types.
+ *
+ * \par Reset Functions
+ * There is also an associated reset function for each data type which clears the state array.
+ *
+ * \par Initialization Functions
+ * There is also an associated initialization function for each data type.
+ * The initialization function performs the following operations:
+ * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+ * - Zeros out the values in the state buffer.
+ *
+ * \par
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
+ *
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the fixed-point versions of the PID Controller functions.
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup PID
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point PID Control.
+ * @param[in,out] *S is an instance of the floating-point PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ */
+
+
+ static __INLINE float32_t arm_pid_f32(
+ arm_pid_instance_f32 * S,
+ float32_t in)
+ {
+ float32_t out;
+
+ /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
+ out = (S->A0 * in) +
+ (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q31 PID Control.
+ * @param[in,out] *S points to an instance of the Q31 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 64-bit accumulator.
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
+ * Thus, if the accumulator result overflows it wraps around rather than clip.
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
+ */
+
+ static __INLINE q31_t arm_pid_q31(
+ arm_pid_instance_q31 * S,
+ q31_t in)
+ {
+ q63_t acc;
+ q31_t out;
+
+ /* acc = A0 * x[n] */
+ acc = (q63_t) S->A0 * in;
+
+ /* acc += A1 * x[n-1] */
+ acc += (q63_t) S->A1 * S->state[0];
+
+ /* acc += A2 * x[n-2] */
+ acc += (q63_t) S->A2 * S->state[1];
+
+ /* convert output to 1.31 format to add y[n-1] */
+ out = (q31_t) (acc >> 31u);
+
+ /* out += y[n-1] */
+ out += S->state[2];
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @brief Process function for the Q15 PID Control.
+ * @param[in,out] *S points to an instance of the Q15 PID Control structure
+ * @param[in] in input sample to process
+ * @return out processed output sample.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using a 64-bit internal accumulator.
+ * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+ */
+
+ static __INLINE q15_t arm_pid_q15(
+ arm_pid_instance_q15 * S,
+ q15_t in)
+ {
+ q63_t acc;
+ q15_t out;
+
+#ifndef ARM_MATH_CM0_FAMILY
+ __SIMD32_TYPE *vstate;
+
+ /* Implementation of PID controller */
+
+ /* acc = A0 * x[n] */
+ acc = (q31_t) __SMUAD(S->A0, in);
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ vstate = __SIMD32_CONST(S->state);
+ acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
+
+#else
+ /* acc = A0 * x[n] */
+ acc = ((q31_t) S->A0) * in;
+
+ /* acc += A1 * x[n-1] + A2 * x[n-2] */
+ acc += (q31_t) S->A1 * S->state[0];
+ acc += (q31_t) S->A2 * S->state[1];
+
+#endif
+
+ /* acc += y[n-1] */
+ acc += (q31_t) S->state[2] << 15;
+
+ /* saturate the output */
+ out = (q15_t) (__SSAT((acc >> 15), 16));
+
+ /* Update state */
+ S->state[1] = S->state[0];
+ S->state[0] = in;
+ S->state[2] = out;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ * @} end of PID group
+ */
+
+
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *src points to the instance of the input floating-point matrix structure.
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+
+ arm_status arm_mat_inverse_f32(
+ const arm_matrix_instance_f32 * src,
+ arm_matrix_instance_f32 * dst);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+
+ /**
+ * @defgroup clarke Vector Clarke Transform
+ * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+ * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
+ * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
+ * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
+ * \image html clarke.gif Stator current space vector and its components in (a,b).
+ * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
+ * can be calculated using only <code>Ia</code> and <code>Ib</code>.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeFormula.gif
+ * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
+ * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup clarke
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point Clarke transform
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ */
+
+ static __INLINE void arm_clarke_f32(
+ float32_t Ia,
+ float32_t Ib,
+ float32_t * pIalpha,
+ float32_t * pIbeta)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+ *pIbeta =
+ ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+ }
+
+ /**
+ * @brief Clarke transform for Q31 version
+ * @param[in] Ia input three-phase coordinate <code>a</code>
+ * @param[in] Ib input three-phase coordinate <code>b</code>
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+ static __INLINE void arm_clarke_q31(
+ q31_t Ia,
+ q31_t Ib,
+ q31_t * pIalpha,
+ q31_t * pIbeta)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+ *pIalpha = Ia;
+
+ /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+ /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+ product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+ /* pIbeta is calculated by adding the intermediate products */
+ *pIbeta = __QADD(product1, product2);
+ }
+
+ /**
+ * @} end of clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q31 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q31(
+ q7_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_clarke Vector Inverse Clarke Transform
+ * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html clarkeInvFormula.gif
+ * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
+ * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Clarke transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_clarke
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Clarke transform
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>
+ * @return none.
+ */
+
+
+ static __INLINE void arm_inv_clarke_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pIa,
+ float32_t * pIb)
+ {
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+ *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+ }
+
+ /**
+ * @brief Inverse Clarke transform for Q31 version
+ * @param[in] Ialpha input two-phase orthogonal vector axis alpha
+ * @param[in] Ibeta input two-phase orthogonal vector axis beta
+ * @param[out] *pIa points to output three-phase coordinate <code>a</code>
+ * @param[out] *pIb points to output three-phase coordinate <code>b</code>
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the subtraction, hence there is no risk of overflow.
+ */
+
+ static __INLINE void arm_inv_clarke_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pIa,
+ q31_t * pIb)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+
+ /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+ *pIa = Ialpha;
+
+ /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+ /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+ /* pIb is calculated by subtracting the products */
+ *pIb = __QSUB(product2, product1);
+
+ }
+
+ /**
+ * @} end of inv_clarke group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to Q15 vector.
+ * @param[in] *pSrc input pointer
+ * @param[out] *pDst output pointer
+ * @param[in] blockSize number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_q15(
+ q7_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup park Vector Park Transform
+ *
+ * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+ * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
+ * from the stationary to the moving reference frame and control the spatial relationship between
+ * the stator vector current and rotor flux vector.
+ * If we consider the d axis aligned with the rotor flux, the diagram below shows the
+ * current vector and the relationship from the two reference frames:
+ * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkFormula.gif
+ * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
+ * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Park transform
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * The function implements the forward Park transform.
+ *
+ */
+
+ static __INLINE void arm_park_f32(
+ float32_t Ialpha,
+ float32_t Ibeta,
+ float32_t * pId,
+ float32_t * pIq,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+ *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+ /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+ *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+ }
+
+ /**
+ * @brief Park transform for Q31 version
+ * @param[in] Ialpha input two-phase vector coordinate alpha
+ * @param[in] Ibeta input two-phase vector coordinate beta
+ * @param[out] *pId points to output rotor reference frame d
+ * @param[out] *pIq points to output rotor reference frame q
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+ */
+
+
+ static __INLINE void arm_park_q31(
+ q31_t Ialpha,
+ q31_t Ibeta,
+ q31_t * pId,
+ q31_t * pIq,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Ialpha * cosVal) */
+ product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * sinVal) */
+ product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Ialpha * sinVal) */
+ product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Ibeta * cosVal) */
+ product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+ /* Calculate pId by adding the two intermediate products 1 and 2 */
+ *pId = __QADD(product1, product2);
+
+ /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+ *pIq = __QSUB(product4, product3);
+ }
+
+ /**
+ * @} end of park group
+ */
+
+ /**
+ * @brief Converts the elements of the Q7 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q7_to_float(
+ q7_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupController
+ */
+
+ /**
+ * @defgroup inv_park Vector Inverse Park transform
+ * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+ *
+ * The function operates on a single sample of data and each call to the function returns the processed output.
+ * The library provides separate functions for Q31 and floating-point data types.
+ * \par Algorithm
+ * \image html parkInvFormula.gif
+ * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
+ * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
+ * cosine and sine values of theta (rotor flux position).
+ * \par Fixed-Point Behavior
+ * Care must be taken when using the Q31 version of the Park transform.
+ * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+ * Refer to the function specific documentation below for usage guidelines.
+ */
+
+ /**
+ * @addtogroup inv_park
+ * @{
+ */
+
+ /**
+ * @brief Floating-point Inverse Park transform
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ */
+
+ static __INLINE void arm_inv_park_f32(
+ float32_t Id,
+ float32_t Iq,
+ float32_t * pIalpha,
+ float32_t * pIbeta,
+ float32_t sinVal,
+ float32_t cosVal)
+ {
+ /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+ *pIalpha = Id * cosVal - Iq * sinVal;
+
+ /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+ *pIbeta = Id * sinVal + Iq * cosVal;
+
+ }
+
+
+ /**
+ * @brief Inverse Park transform for Q31 version
+ * @param[in] Id input coordinate of rotor reference frame d
+ * @param[in] Iq input coordinate of rotor reference frame q
+ * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
+ * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
+ * @param[in] sinVal sine value of rotation angle theta
+ * @param[in] cosVal cosine value of rotation angle theta
+ * @return none.
+ *
+ * <b>Scaling and Overflow Behavior:</b>
+ * \par
+ * The function is implemented using an internal 32-bit accumulator.
+ * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+ * There is saturation on the addition, hence there is no risk of overflow.
+ */
+
+
+ static __INLINE void arm_inv_park_q31(
+ q31_t Id,
+ q31_t Iq,
+ q31_t * pIalpha,
+ q31_t * pIbeta,
+ q31_t sinVal,
+ q31_t cosVal)
+ {
+ q31_t product1, product2; /* Temporary variables used to store intermediate results */
+ q31_t product3, product4; /* Temporary variables used to store intermediate results */
+
+ /* Intermediate product is calculated by (Id * cosVal) */
+ product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * sinVal) */
+ product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+ /* Intermediate product is calculated by (Id * sinVal) */
+ product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+ /* Intermediate product is calculated by (Iq * cosVal) */
+ product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+ /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+ *pIalpha = __QSUB(product1, product2);
+
+ /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+ *pIbeta = __QADD(product4, product3);
+
+ }
+
+ /**
+ * @} end of Inverse park group
+ */
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_float(
+ q31_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup LinearInterpolate Linear Interpolation
+ *
+ * Linear interpolation is a method of curve fitting using linear polynomials.
+ * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+ *
+ * \par
+ * \image html LinearInterp.gif "Linear interpolation"
+ *
+ * \par
+ * A Linear Interpolate function calculates an output value(y), for the input(x)
+ * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+ *
+ * \par Algorithm:
+ * <pre>
+ * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+ * where x0, x1 are nearest values of input x
+ * y0, y1 are nearest values to output y
+ * </pre>
+ *
+ * \par
+ * This set of functions implements Linear interpolation process
+ * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
+ * sample of data and each call to the function returns a single processed value.
+ * <code>S</code> points to an instance of the Linear Interpolate function data structure.
+ * <code>x</code> is the input sample value. The functions returns the output value.
+ *
+ * \par
+ * if x is outside of the table boundary, Linear interpolation returns first value of the table
+ * if x is below input range and returns last value of table if x is above range.
+ */
+
+ /**
+ * @addtogroup LinearInterpolate
+ * @{
+ */
+
+ /**
+ * @brief Process function for the floating-point Linear Interpolation Function.
+ * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+ * @param[in] x input sample to process
+ * @return y processed output sample.
+ *
+ */
+
+ static __INLINE float32_t arm_linear_interp_f32(
+ arm_linear_interp_instance_f32 * S,
+ float32_t x)
+ {
+
+ float32_t y;
+ float32_t x0, x1; /* Nearest input values */
+ float32_t y0, y1; /* Nearest output values */
+ float32_t xSpacing = S->xSpacing; /* spacing between input values */
+ int32_t i; /* Index variable */
+ float32_t *pYData = S->pYData; /* pointer to output table */
+
+ /* Calculation of index */
+ i = (int32_t) ((x - S->x1) / xSpacing);
+
+ if(i < 0)
+ {
+ /* Iniatilize output for below specified range as least output value of table */
+ y = pYData[0];
+ }
+ else if((uint32_t)i >= S->nValues)
+ {
+ /* Iniatilize output for above specified range as last output value of table */
+ y = pYData[S->nValues - 1];
+ }
+ else
+ {
+ /* Calculation of nearest input values */
+ x0 = S->x1 + i * xSpacing;
+ x1 = S->x1 + (i + 1) * xSpacing;
+
+ /* Read of nearest output values */
+ y0 = pYData[i];
+ y1 = pYData[i + 1];
+
+ /* Calculation of output */
+ y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
+
+ }
+
+ /* returns output value */
+ return (y);
+ }
+
+ /**
+ *
+ * @brief Process function for the Q31 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q31 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ static __INLINE q31_t arm_linear_interp_q31(
+ q31_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q31_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* shift left by 11 to keep fract in 1.31 format */
+ fract = (x & 0x000FFFFF) << 11;
+
+ /* Read two nearest output values from the index in 1.31(q31) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+ y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+
+ /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+ y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+
+ /* Convert y to 1.31 format */
+ return (y << 1u);
+
+ }
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q15 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q15 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ *
+ */
+
+
+ static __INLINE q15_t arm_linear_interp_q15(
+ q15_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q63_t y; /* output */
+ q15_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ int32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ index = ((x & 0xFFF00000) >> 20u);
+
+ if(index >= (int32_t)(nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else if(index < 0)
+ {
+ return (pYData[0]);
+ }
+ else
+ {
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+ y = ((q63_t) y0 * (0xFFFFF - fract));
+
+ /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+ y += ((q63_t) y1 * (fract));
+
+ /* convert y to 1.15 format */
+ return (y >> 20);
+ }
+
+
+ }
+
+ /**
+ *
+ * @brief Process function for the Q7 Linear Interpolation Function.
+ * @param[in] *pYData pointer to Q7 Linear Interpolation table
+ * @param[in] x input sample to process
+ * @param[in] nValues number of table values
+ * @return y processed output sample.
+ *
+ * \par
+ * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+ * This function can support maximum of table size 2^12.
+ */
+
+
+ static __INLINE q7_t arm_linear_interp_q7(
+ q7_t * pYData,
+ q31_t x,
+ uint32_t nValues)
+ {
+ q31_t y; /* output */
+ q7_t y0, y1; /* Nearest output values */
+ q31_t fract; /* fractional part */
+ uint32_t index; /* Index to read nearest output values */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ if (x < 0)
+ {
+ return (pYData[0]);
+ }
+ index = (x >> 20) & 0xfff;
+
+
+ if(index >= (nValues - 1))
+ {
+ return (pYData[nValues - 1]);
+ }
+ else
+ {
+
+ /* 20 bits for the fractional part */
+ /* fract is in 12.20 format */
+ fract = (x & 0x000FFFFF);
+
+ /* Read two nearest output values from the index and are in 1.7(q7) format */
+ y0 = pYData[index];
+ y1 = pYData[index + 1u];
+
+ /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+ y = ((y0 * (0xFFFFF - fract)));
+
+ /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+ y += (y1 * fract);
+
+ /* convert y to 1.7(q7) format */
+ return (y >> 20u);
+
+ }
+
+ }
+ /**
+ * @} end of LinearInterpolate group
+ */
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return sin(x).
+ */
+
+ float32_t arm_sin_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q31_t arm_sin_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return sin(x).
+ */
+
+ q15_t arm_sin_q15(
+ q15_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for floating-point data.
+ * @param[in] x input value in radians.
+ * @return cos(x).
+ */
+
+ float32_t arm_cos_f32(
+ float32_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q31_t arm_cos_q31(
+ q31_t x);
+
+ /**
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.
+ * @param[in] x Scaled input value in radians.
+ * @return cos(x).
+ */
+
+ q15_t arm_cos_q15(
+ q15_t x);
+
+
+ /**
+ * @ingroup groupFastMath
+ */
+
+
+ /**
+ * @defgroup SQRT Square Root
+ *
+ * Computes the square root of a number.
+ * There are separate functions for Q15, Q31, and floating-point data types.
+ * The square root function is computed using the Newton-Raphson algorithm.
+ * This is an iterative algorithm of the form:
+ * <pre>
+ * x1 = x0 - f(x0)/f'(x0)
+ * </pre>
+ * where <code>x1</code> is the current estimate,
+ * <code>x0</code> is the previous estimate, and
+ * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
+ * For the square root function, the algorithm reduces to:
+ * <pre>
+ * x0 = in/2 [initial guess]
+ * x1 = 1/2 * ( x0 + in / x0) [each iteration]
+ * </pre>
+ */
+
+
+ /**
+ * @addtogroup SQRT
+ * @{
+ */
+
+ /**
+ * @brief Floating-point square root function.
+ * @param[in] in input value.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+
+ static __INLINE arm_status arm_sqrt_f32(
+ float32_t in,
+ float32_t * pOut)
+ {
+ if(in > 0)
+ {
+
+// #if __FPU_USED
+#if (__FPU_USED == 1) && defined ( __CC_ARM )
+ *pOut = __sqrtf(in);
+#else
+ *pOut = sqrtf(in);
+#endif
+
+ return (ARM_MATH_SUCCESS);
+ }
+ else
+ {
+ *pOut = 0.0f;
+ return (ARM_MATH_ARGUMENT_ERROR);
+ }
+
+ }
+
+
+ /**
+ * @brief Q31 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q31(
+ q31_t in,
+ q31_t * pOut);
+
+ /**
+ * @brief Q15 square root function.
+ * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+ * @param[out] *pOut square root of input value.
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+ * <code>in</code> is negative value and returns zero output for negative values.
+ */
+ arm_status arm_sqrt_q15(
+ q15_t in,
+ q15_t * pOut);
+
+ /**
+ * @} end of SQRT group
+ */
+
+
+
+
+
+
+ /**
+ * @brief floating-point Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const int32_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief floating-point Circular Read function.
+ */
+ static __INLINE void arm_circularRead_f32(
+ int32_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ int32_t * dst,
+ int32_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (int32_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+ /**
+ * @brief Q15 Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q15_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q15 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q15(
+ q15_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q15_t * dst,
+ q15_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q15_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Q7 Circular write function.
+ */
+
+ static __INLINE void arm_circularWrite_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ uint16_t * writeOffset,
+ int32_t bufferInc,
+ const q7_t * src,
+ int32_t srcInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0u;
+ int32_t wOffset;
+
+ /* Copy the value of Index pointer that points
+ * to the current location where the input samples to be copied */
+ wOffset = *writeOffset;
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the input sample to the circular buffer */
+ circBuffer[wOffset] = *src;
+
+ /* Update the input pointer */
+ src += srcInc;
+
+ /* Circularly update wOffset. Watch out for positive and negative value */
+ wOffset += bufferInc;
+ if(wOffset >= L)
+ wOffset -= L;
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *writeOffset = wOffset;
+ }
+
+
+
+ /**
+ * @brief Q7 Circular Read function.
+ */
+ static __INLINE void arm_circularRead_q7(
+ q7_t * circBuffer,
+ int32_t L,
+ int32_t * readOffset,
+ int32_t bufferInc,
+ q7_t * dst,
+ q7_t * dst_base,
+ int32_t dst_length,
+ int32_t dstInc,
+ uint32_t blockSize)
+ {
+ uint32_t i = 0;
+ int32_t rOffset, dst_end;
+
+ /* Copy the value of Index pointer that points
+ * to the current location from where the input samples to be read */
+ rOffset = *readOffset;
+
+ dst_end = (int32_t) (dst_base + dst_length);
+
+ /* Loop over the blockSize */
+ i = blockSize;
+
+ while(i > 0u)
+ {
+ /* copy the sample from the circular buffer to the destination buffer */
+ *dst = circBuffer[rOffset];
+
+ /* Update the input pointer */
+ dst += dstInc;
+
+ if(dst == (q7_t *) dst_end)
+ {
+ dst = dst_base;
+ }
+
+ /* Circularly update rOffset. Watch out for positive and negative value */
+ rOffset += bufferInc;
+
+ if(rOffset >= L)
+ {
+ rOffset -= L;
+ }
+
+ /* Decrement the loop counter */
+ i--;
+ }
+
+ /* Update the index pointer */
+ *readOffset = rOffset;
+ }
+
+
+ /**
+ * @brief Sum of the squares of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Sum of the squares of the elements of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_power_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_mean_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult);
+
+ /**
+ * @brief Mean value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Mean value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Mean value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+ void arm_mean_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q63_t * pResult);
+
+ /**
+ * @brief Variance of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_var_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Root Mean Square of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_rms_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult);
+
+ /**
+ * @brief Standard deviation of the elements of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output value.
+ * @return none.
+ */
+
+ void arm_std_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult);
+
+ /**
+ * @brief Floating-point complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_f32(
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q31(
+ q31_t * pSrc,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex magnitude
+ * @param[in] *pSrc points to the complex input vector
+ * @param[out] *pDst points to the real output vector
+ * @param[in] numSamples number of complex samples in the input vector
+ * @return none.
+ */
+
+ void arm_cmplx_mag_q15(
+ q15_t * pSrc,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q15 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ uint32_t numSamples,
+ q31_t * realResult,
+ q31_t * imagResult);
+
+ /**
+ * @brief Q31 complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ uint32_t numSamples,
+ q63_t * realResult,
+ q63_t * imagResult);
+
+ /**
+ * @brief Floating-point complex dot product
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @param[out] *realResult real part of the result returned here
+ * @param[out] *imagResult imaginary part of the result returned here
+ * @return none.
+ */
+
+ void arm_cmplx_dot_prod_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ uint32_t numSamples,
+ float32_t * realResult,
+ float32_t * imagResult);
+
+ /**
+ * @brief Q15 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q15(
+ q15_t * pSrcCmplx,
+ q15_t * pSrcReal,
+ q15_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_q31(
+ q31_t * pSrcCmplx,
+ q31_t * pSrcReal,
+ q31_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-real multiplication
+ * @param[in] *pSrcCmplx points to the complex input vector
+ * @param[in] *pSrcReal points to the real input vector
+ * @param[out] *pCmplxDst points to the complex output vector
+ * @param[in] numSamples number of samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_real_f32(
+ float32_t * pSrcCmplx,
+ float32_t * pSrcReal,
+ float32_t * pCmplxDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Minimum value of a Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *result is output pointer
+ * @param[in] index is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * result,
+ uint32_t * index);
+
+ /**
+ * @brief Minimum value of a Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[in] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+ void arm_min_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Minimum value of a floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[in] blockSize is the number of samples to process
+ * @param[out] *pResult is output pointer
+ * @param[out] *pIndex is the array index of the minimum value in the input buffer.
+ * @return none.
+ */
+
+ void arm_min_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q7(
+ q7_t * pSrc,
+ uint32_t blockSize,
+ q7_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q15(
+ q15_t * pSrc,
+ uint32_t blockSize,
+ q15_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_q31(
+ q31_t * pSrc,
+ uint32_t blockSize,
+ q31_t * pResult,
+ uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in] *pSrc points to the input buffer
+ * @param[in] blockSize length of the input vector
+ * @param[out] *pResult maximum value returned here
+ * @param[out] *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+ void arm_max_f32(
+ float32_t * pSrc,
+ uint32_t blockSize,
+ float32_t * pResult,
+ uint32_t * pIndex);
+
+ /**
+ * @brief Q15 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q15(
+ q15_t * pSrcA,
+ q15_t * pSrcB,
+ q15_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Q31 complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_q31(
+ q31_t * pSrcA,
+ q31_t * pSrcB,
+ q31_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Floating-point complex-by-complex multiplication
+ * @param[in] *pSrcA points to the first input vector
+ * @param[in] *pSrcB points to the second input vector
+ * @param[out] *pDst points to the output vector
+ * @param[in] numSamples number of complex samples in each vector
+ * @return none.
+ */
+
+ void arm_cmplx_mult_cmplx_f32(
+ float32_t * pSrcA,
+ float32_t * pSrcB,
+ float32_t * pDst,
+ uint32_t numSamples);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q31 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q31 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none.
+ */
+ void arm_float_to_q31(
+ float32_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q15 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q15 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q15(
+ float32_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the floating-point vector to Q7 vector.
+ * @param[in] *pSrc points to the floating-point input vector
+ * @param[out] *pDst points to the Q7 output vector
+ * @param[in] blockSize length of the input vector
+ * @return none
+ */
+ void arm_float_to_q7(
+ float32_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q15 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q15(
+ q31_t * pSrc,
+ q15_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q31 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q31_to_q7(
+ q31_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Converts the elements of the Q15 vector to floating-point vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_float(
+ q15_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q31 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q31(
+ q15_t * pSrc,
+ q31_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @brief Converts the elements of the Q15 vector to Q7 vector.
+ * @param[in] *pSrc is input pointer
+ * @param[out] *pDst is output pointer
+ * @param[in] blockSize is the number of samples to process
+ * @return none.
+ */
+ void arm_q15_to_q7(
+ q15_t * pSrc,
+ q7_t * pDst,
+ uint32_t blockSize);
+
+
+ /**
+ * @ingroup groupInterpolation
+ */
+
+ /**
+ * @defgroup BilinearInterpolate Bilinear Interpolation
+ *
+ * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+ * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
+ * determines values between the grid points.
+ * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+ * Bilinear interpolation is often used in image processing to rescale images.
+ * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+ *
+ * <b>Algorithm</b>
+ * \par
+ * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+ * For floating-point, the instance structure is defined as:
+ * <pre>
+ * typedef struct
+ * {
+ * uint16_t numRows;
+ * uint16_t numCols;
+ * float32_t *pData;
+ * } arm_bilinear_interp_instance_f32;
+ * </pre>
+ *
+ * \par
+ * where <code>numRows</code> specifies the number of rows in the table;
+ * <code>numCols</code> specifies the number of columns in the table;
+ * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
+ * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
+ * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
+ *
+ * \par
+ * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
+ * <pre>
+ * XF = floor(x)
+ * YF = floor(y)
+ * </pre>
+ * \par
+ * The interpolated output point is computed as:
+ * <pre>
+ * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+ * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+ * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+ * + f(XF+1, YF+1) * (x-XF)*(y-YF)
+ * </pre>
+ * Note that the coordinates (x, y) contain integer and fractional components.
+ * The integer components specify which portion of the table to use while the
+ * fractional components control the interpolation processor.
+ *
+ * \par
+ * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
+ */
+
+ /**
+ * @addtogroup BilinearInterpolate
+ * @{
+ */
+
+ /**
+ *
+ * @brief Floating-point bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate.
+ * @param[in] Y interpolation coordinate.
+ * @return out interpolated value.
+ */
+
+
+ static __INLINE float32_t arm_bilinear_interp_f32(
+ const arm_bilinear_interp_instance_f32 * S,
+ float32_t X,
+ float32_t Y)
+ {
+ float32_t out;
+ float32_t f00, f01, f10, f11;
+ float32_t *pData = S->pData;
+ int32_t xIndex, yIndex, index;
+ float32_t xdiff, ydiff;
+ float32_t b1, b2, b3, b4;
+
+ xIndex = (int32_t) X;
+ yIndex = (int32_t) Y;
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
+ || yIndex > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* Calculation of index for two nearest points in X-direction */
+ index = (xIndex - 1) + (yIndex - 1) * S->numCols;
+
+
+ /* Read two nearest points in X-direction */
+ f00 = pData[index];
+ f01 = pData[index + 1];
+
+ /* Calculation of index for two nearest points in Y-direction */
+ index = (xIndex - 1) + (yIndex) * S->numCols;
+
+
+ /* Read two nearest points in Y-direction */
+ f10 = pData[index];
+ f11 = pData[index + 1];
+
+ /* Calculation of intermediate values */
+ b1 = f00;
+ b2 = f01 - f00;
+ b3 = f10 - f00;
+ b4 = f00 - f01 - f10 + f11;
+
+ /* Calculation of fractional part in X */
+ xdiff = X - xIndex;
+
+ /* Calculation of fractional part in Y */
+ ydiff = Y - yIndex;
+
+ /* Calculation of bi-linear interpolated output */
+ out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+ /* return to application */
+ return (out);
+
+ }
+
+ /**
+ *
+ * @brief Q31 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q31_t arm_bilinear_interp_q31(
+ arm_bilinear_interp_instance_q31 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q31_t out; /* Temporary output */
+ q31_t acc = 0; /* output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q31_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q31_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20u);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20u);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* shift left xfract by 11 to keep 1.31 format */
+ xfract = (X & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+ /* 20 bits for the fractional part */
+ /* shift left yfract by 11 to keep 1.31 format */
+ yfract = (Y & 0x000FFFFF) << 11u;
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+ out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+ acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+ /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+ /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
+ out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+ acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+ /* Convert acc to 1.31(q31) format */
+ return (acc << 2u);
+
+ }
+
+ /**
+ * @brief Q15 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q15_t arm_bilinear_interp_q15(
+ arm_bilinear_interp_instance_q15 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q15_t x1, x2, y1, y2; /* Nearest output values */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ int32_t rI, cI; /* Row and column indices */
+ q15_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+ /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+ /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
+ out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+ acc = ((q63_t) out * (0xFFFFF - yfract));
+
+ /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+ acc += ((q63_t) out * (xfract));
+
+ /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
+ out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+ acc += ((q63_t) out * (yfract));
+
+ /* acc is in 13.51 format and down shift acc by 36 times */
+ /* Convert out to 1.15 format */
+ return (acc >> 36);
+
+ }
+
+ /**
+ * @brief Q7 bilinear interpolation.
+ * @param[in,out] *S points to an instance of the interpolation structure.
+ * @param[in] X interpolation coordinate in 12.20 format.
+ * @param[in] Y interpolation coordinate in 12.20 format.
+ * @return out interpolated value.
+ */
+
+ static __INLINE q7_t arm_bilinear_interp_q7(
+ arm_bilinear_interp_instance_q7 * S,
+ q31_t X,
+ q31_t Y)
+ {
+ q63_t acc = 0; /* output */
+ q31_t out; /* Temporary output */
+ q31_t xfract, yfract; /* X, Y fractional parts */
+ q7_t x1, x2, y1, y2; /* Nearest output values */
+ int32_t rI, cI; /* Row and column indices */
+ q7_t *pYData = S->pData; /* pointer to output table values */
+ uint32_t nCols = S->numCols; /* num of rows */
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ rI = ((X & 0xFFF00000) >> 20);
+
+ /* Input is in 12.20 format */
+ /* 12 bits for the table index */
+ /* Index value calculation */
+ cI = ((Y & 0xFFF00000) >> 20);
+
+ /* Care taken for table outside boundary */
+ /* Returns zero output when values are outside table boundary */
+ if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
+ {
+ return (0);
+ }
+
+ /* 20 bits for the fractional part */
+ /* xfract should be in 12.20 format */
+ xfract = (X & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ x1 = pYData[(rI) + nCols * (cI)];
+ x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+ /* 20 bits for the fractional part */
+ /* yfract should be in 12.20 format */
+ yfract = (Y & 0x000FFFFF);
+
+ /* Read two nearest output values from the index */
+ y1 = pYData[(rI) + nCols * (cI + 1)];
+ y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+ /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+ out = ((x1 * (0xFFFFF - xfract)));
+ acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+ /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
+ out = ((x2 * (0xFFFFF - yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y1 * (0xFFFFF - xfract)));
+ acc += (((q63_t) out * (yfract)));
+
+ /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
+ out = ((y2 * (yfract)));
+ acc += (((q63_t) out * (xfract)));
+
+ /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+ return (acc >> 40);
+
+ }
+
+ /**
+ * @} end of BilinearInterpolate group
+ */
+
+
+#if defined ( __CC_ARM ) //Keil
+//SMMLAR
+ #define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMLSR
+ #define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+
+//SMMULR
+ #define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+
+//Exit low optimization region - place directly after end of function definition
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+
+//Enter low optimization region - place directly above function definition
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+//Exit low optimization region - place directly after end of function definition
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__ICCARM__) //IAR
+ //SMMLA
+ #define multAcc_32x32_keep32_R(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+ #define multSub_32x32_keep32_R(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+ #define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+//Enter low optimization region - place directly above function definition
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+ #define LOW_OPTIMIZATION_EXIT
+
+//Enter low optimization region - place directly above function definition
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+
+//Exit low optimization region - place directly after end of function definition
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__GNUC__)
+ //SMMLA
+ #define multAcc_32x32_keep32_R(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+ //SMMLS
+ #define multSub_32x32_keep32_R(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+ #define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+ #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
+
+ #define LOW_OPTIMIZATION_EXIT
+
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+
+ #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#endif
+
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/math_helper.h b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/math_helper.h
new file mode 100644
index 000000000..749f00d43
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/cmsis_dsp/math_helper.h
@@ -0,0 +1,73 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+*
+* $Date: 17. January 2013
+* $Revision: V1.4.0
+*
+* Project: CMSIS DSP Library
+*
+* Title: math_helper.h
+*
+* Description: Prototypes of all helper functions required.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+#ifndef MATH_HELPER_H
+#define MATH_HELPER_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+float arm_snr_f32(float *pRef, float *pTest, uint32_t buffSize);
+void arm_float_to_q12_20(float *pIn, q31_t * pOut, uint32_t numSamples);
+void arm_provide_guard_bits_q15(q15_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_provide_guard_bits_q31(q31_t *input_buf, uint32_t blockSize, uint32_t guard_bits);
+void arm_float_to_q14(float *pIn, q15_t *pOut, uint32_t numSamples);
+void arm_float_to_q29(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q28(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_float_to_q30(float *pIn, q31_t *pOut, uint32_t numSamples);
+void arm_clip_f32(float *pIn, uint32_t numSamples);
+uint32_t arm_calc_guard_bits(uint32_t num_adds);
+void arm_apply_guard_bits (float32_t * pIn, uint32_t numSamples, uint32_t guard_bits);
+uint32_t arm_compare_fixed_q15(q15_t *pIn, q15_t * pOut, uint32_t numSamples);
+uint32_t arm_compare_fixed_q31(q31_t *pIn, q31_t *pOut, uint32_t numSamples);
+uint32_t arm_calc_2pow(uint32_t guard_bits);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/dsp/FIR_f32.h b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/dsp/FIR_f32.h
new file mode 100644
index 000000000..bbb9f927f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/dsp/FIR_f32.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef FIR_F32_H
+#define FIR_F32_H
+
+#include <stdint.h>
+#include "arm_math.h"
+
+namespace dsp {
+
+template<uint16_t num_taps, uint32_t block_size=32>
+class FIR_f32 {
+public:
+ FIR_f32(const float32_t *coeff) {
+ arm_fir_init_f32(&fir, num_taps, (float32_t*)coeff, fir_state, block_size);
+ }
+
+ void process(float32_t *sgn_in, float32_t *sgn_out) {
+ arm_fir_f32(&fir, sgn_in, sgn_out, block_size);
+ }
+
+ void reset(void) {
+ memset(fir_state, 0, sizeof(fir_state));
+ }
+
+private:
+ arm_fir_instance_f32 fir;
+ float32_t fir_state[block_size + num_taps - 1];
+};
+
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/dsp/Sine_f32.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/dsp/Sine_f32.cpp
new file mode 100644
index 000000000..63163c858
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/dsp/Sine_f32.cpp
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "Sine_f32.h"
+#include "math_helper.h"
+
+#define RAD_2PI (2. * PI)
+
+namespace dsp {
+
+Sine_f32::Sine_f32(uint32_t frequency, uint32_t sample_rate, float32_t amplitude, float32_t phase, uint32_t block_size) {
+ _dx = RAD_2PI * ((float32_t)frequency / (float32_t)sample_rate);
+ _amplitude = amplitude;
+ _x = phase;
+ _block_size = block_size;
+}
+
+void Sine_f32::process(float32_t *sgn_in, float32_t *sgn_out) {
+ for (uint32_t i=0; i<_block_size; i++) {
+ *sgn_out = *sgn_in + (_amplitude * arm_sin_f32(_x));
+ sgn_in++; sgn_out++;
+ _x += _dx;
+ }
+}
+
+void Sine_f32::generate(float32_t *sgn) {
+ for (uint32_t i=0; i<_block_size; i++) {
+ *sgn = (_amplitude * arm_sin_f32(_x));
+ sgn++;
+ _x += _dx;
+ }
+}
+
+void Sine_f32::reset(void) {
+ _x = 0.0f;
+}
+
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/dsp/Sine_f32.h b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/dsp/Sine_f32.h
new file mode 100644
index 000000000..798778572
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/dsp/Sine_f32.h
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef SINE_F32_H
+#define SINE_F32_H
+
+#include <stdint.h>
+#include "arm_math.h"
+
+namespace dsp {
+
+class Sine_f32 {
+public:
+ Sine_f32(uint32_t frequency, uint32_t sample_rate=48000, float32_t amplitude=1.f, float32_t phase=0.0, uint32_t block_size=32);
+
+ void process(float32_t *sgn_in, float32_t *sgn_out);
+
+ void generate(float32_t *sgn);
+
+ void reset(void);
+
+private:
+ float32_t _dx;
+ float32_t _amplitude;
+ float32_t _x;
+ uint32_t _block_size;
+};
+
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/dsp/dsp.h b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/dsp/dsp.h
new file mode 100644
index 000000000..0ac5e8e0f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/dsp/dsp/dsp.h
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef DSP_H
+#define DSP_H
+
+#include "math_helper.h"
+#include "arm_math.h"
+
+#include "FIR_f32.h"
+#include "Sine_f32.h"
+
+using namespace dsp;
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ccsbcs.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ccsbcs.cpp
new file mode 100644
index 000000000..01d94428c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ccsbcs.cpp
@@ -0,0 +1,540 @@
+/*------------------------------------------------------------------------*/
+/* Unicode - Local code bidirectional converter (C)ChaN, 2009 */
+/* (SBCS code pages) */
+/*------------------------------------------------------------------------*/
+/* 437 U.S. (OEM)
+/ 720 Arabic (OEM)
+/ 1256 Arabic (Windows)
+/ 737 Greek (OEM)
+/ 1253 Greek (Windows)
+/ 1250 Central Europe (Windows)
+/ 775 Baltic (OEM)
+/ 1257 Baltic (Windows)
+/ 850 Multilingual Latin 1 (OEM)
+/ 852 Latin 2 (OEM)
+/ 1252 Latin 1 (Windows)
+/ 855 Cyrillic (OEM)
+/ 1251 Cyrillic (Windows)
+/ 866 Russian (OEM)
+/ 857 Turkish (OEM)
+/ 1254 Turkish (Windows)
+/ 858 Multilingual Latin 1 + Euro (OEM)
+/ 862 Hebrew (OEM)
+/ 1255 Hebrew (Windows)
+/ 874 Thai (OEM, Windows)
+/ 1258 Vietnam (OEM, Windows)
+*/
+
+#include "ff.h"
+
+
+#if _CODE_PAGE == 437
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+ 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+ 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+ 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+ 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+ 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4,
+ 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+ 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248,
+ 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 720
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP720(0x80-0xFF) to Unicode conversion table */
+ 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7,
+ 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9,
+ 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627,
+ 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F,
+ 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+ 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+ 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642,
+ 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A,
+ 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0xO650, 0x2248,
+ 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 737
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP737(0x80-0xFF) to Unicode conversion table */
+ 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398,
+ 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0,
+ 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9,
+ 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8,
+ 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0,
+ 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+ 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+ 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD,
+ 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E,
+ 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248,
+ 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 775
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP775(0x80-0xFF) to Unicode conversion table */
+ 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107,
+ 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A,
+ 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4,
+ 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6,
+ 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118,
+ 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D,
+ 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B,
+ 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144,
+ 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019,
+ 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E,
+ 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 850
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP850(0x80-0xFF) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+ 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+ 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+ 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
+ 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+ 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE,
+ 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+ 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE,
+ 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
+ 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
+ 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 852
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP852(0x80-0xFF) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7,
+ 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106,
+ 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A,
+ 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E,
+ 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A,
+ 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+ 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE,
+ 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580,
+ 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161,
+ 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4,
+ 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8,
+ 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 855
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP855(0x80-0xFF) to Unicode conversion table */
+ 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404,
+ 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408,
+ 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C,
+ 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A,
+ 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414,
+ 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438,
+ 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+ 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E,
+ 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580,
+ 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443,
+ 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116,
+ 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D,
+ 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 857
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP857(0x80-0xFF) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+ 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+ 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F,
+ 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
+ 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+ 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE,
+ 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
+ 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000,
+ 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4,
+ 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
+ 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 858
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP858(0x80-0xFF) to Unicode conversion table */
+ 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
+ 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
+ 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
+ 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+ 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
+ 0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
+ 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE,
+ 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580,
+ 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE,
+ 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
+ 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
+ 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 862
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP862(0x80-0xFF) to Unicode conversion table */
+ 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7,
+ 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
+ 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7,
+ 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
+ 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
+ 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+ 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+ 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4,
+ 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
+ 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248,
+ 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 866
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP866(0x80-0xFF) to Unicode conversion table */
+ 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
+ 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+ 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
+ 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+ 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
+ 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+ 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
+ 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
+ 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
+ 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
+ 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
+ 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
+ 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
+ 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
+ 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E,
+ 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0
+};
+
+#elif _CODE_PAGE == 874
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP874(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07,
+ 0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F,
+ 0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17,
+ 0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F,
+ 0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27,
+ 0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F,
+ 0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37,
+ 0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F,
+ 0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47,
+ 0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F,
+ 0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57,
+ 0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000
+};
+
+#elif _CODE_PAGE == 1250
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1250(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A,
+ 0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7,
+ 0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B,
+ 0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+ 0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C,
+ 0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7,
+ 0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E,
+ 0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7,
+ 0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF,
+ 0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7,
+ 0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F,
+ 0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7,
+ 0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9
+};
+
+#elif _CODE_PAGE == 1251
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1251(0x80-0xFF) to Unicode conversion table */
+ 0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F,
+ 0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F,
+ 0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7,
+ 0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407,
+ 0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7,
+ 0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457,
+ 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
+ 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
+ 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
+ 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
+ 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
+ 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
+ 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
+ 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F
+};
+
+#elif _CODE_PAGE == 1252
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1252(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178,
+ 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+ 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+ 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+ 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
+ 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF,
+ 0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7,
+ 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF,
+ 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
+ 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF,
+ 0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7,
+ 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF
+};
+
+#elif _CODE_PAGE == 1253
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1253(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+ 0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015,
+ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7,
+ 0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F,
+ 0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397,
+ 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F,
+ 0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7,
+ 0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF,
+ 0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7,
+ 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF,
+ 0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7,
+ 0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000
+};
+
+#elif _CODE_PAGE == 1254
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1254(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178,
+ 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+ 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+ 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+ 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
+ 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF,
+ 0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7,
+ 0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF,
+ 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
+ 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF,
+ 0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7,
+ 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF
+};
+
+#elif _CODE_PAGE == 1255
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1255(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+ 0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+ 0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+ 0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7,
+ 0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF,
+ 0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3,
+ 0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7,
+ 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
+ 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7,
+ 0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000
+};
+
+#elif _CODE_PAGE == 1256
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1256(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688,
+ 0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA,
+ 0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+ 0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+ 0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F,
+ 0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627,
+ 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F,
+ 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7,
+ 0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643,
+ 0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7,
+ 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF,
+ 0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7,
+ 0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2
+}
+
+#elif _CODE_PAGE == 1257
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1257(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000,
+ 0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7,
+ 0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+ 0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6,
+ 0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112,
+ 0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B,
+ 0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7,
+ 0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF,
+ 0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113,
+ 0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C,
+ 0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7,
+ 0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9
+};
+
+#elif _CODE_PAGE == 1258
+#define _TBLDEF 1
+static
+const WCHAR Tbl[] = { /* CP1258(0x80-0xFF) to Unicode conversion table */
+ 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+ 0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000,
+ 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+ 0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178,
+ 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
+ 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
+ 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
+ 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
+ 0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
+ 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF,
+ 0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7,
+ 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF,
+ 0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
+ 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF,
+ 0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7,
+ 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF
+};
+
+#endif
+
+
+#if !_TBLDEF || !_USE_LFN
+#error This file is not needed in current configuration. Remove from the project.
+#endif
+
+
+WCHAR ff_convert ( /* Converted character, Returns zero on error */
+ WCHAR src, /* Character code to be converted */
+ UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */
+)
+{
+ WCHAR c;
+
+
+ if (src < 0x80) { /* ASCII */
+ c = src;
+
+ } else {
+ if (dir) { /* OEMCP to Unicode */
+ c = (src >= 0x100) ? 0 : Tbl[src - 0x80];
+
+ } else { /* Unicode to OEMCP */
+ for (c = 0; c < 0x80; c++) {
+ if (src == Tbl[c]) break;
+ }
+ c = (c + 0x80) & 0xFF;
+ }
+ }
+
+ return c;
+}
+
+
+WCHAR ff_wtoupper ( /* Upper converted character */
+ WCHAR chr /* Input character */
+)
+{
+ static const WCHAR tbl_lower[] = { 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF, 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101, 0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F, 0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D, 0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B, 0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A, 0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148, 0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157, 0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165, 0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173, 0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1, 0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8, 0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF, 0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7, 0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A, 0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441, 0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448, 0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F, 0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457, 0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F, 0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177, 0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F, 0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48, 0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50, 0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58, 0xFF59, 0xFF5A, 0 };
+ static const WCHAR tbl_upper[] = { 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 };
+ int i;
+
+
+ for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ;
+
+ return tbl_lower[i] ? tbl_upper[i] : chr;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/diskio.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/diskio.cpp
new file mode 100644
index 000000000..1f719725e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/diskio.cpp
@@ -0,0 +1,94 @@
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2007 */
+/*-----------------------------------------------------------------------*/
+/* This is a stub disk I/O module that acts as front end of the existing */
+/* disk I/O modules and attach it to FatFs module with common interface. */
+/*-----------------------------------------------------------------------*/
+#include "ffconf.h"
+#include "diskio.h"
+
+#include "mbed_debug.h"
+#include "FATFileSystem.h"
+
+using namespace mbed;
+
+DSTATUS disk_initialize (
+ BYTE drv /* Physical drive nmuber (0..) */
+)
+{
+ debug_if(FFS_DBG, "disk_initialize on drv [%d]\n", drv);
+ return (DSTATUS)FATFileSystem::_ffs[drv]->disk_initialize();
+}
+
+DSTATUS disk_status (
+ BYTE drv /* Physical drive nmuber (0..) */
+)
+{
+ debug_if(FFS_DBG, "disk_status on drv [%d]\n", drv);
+ return (DSTATUS)FATFileSystem::_ffs[drv]->disk_status();
+}
+
+DRESULT disk_read (
+ BYTE drv, /* Physical drive nmuber (0..) */
+ BYTE *buff, /* Data buffer to store read data */
+ DWORD sector, /* Sector address (LBA) */
+ BYTE count /* Number of sectors to read (1..255) */
+)
+{
+ debug_if(FFS_DBG, "disk_read(sector %d, count %d) on drv [%d]\n", sector, count, drv);
+ if (FATFileSystem::_ffs[drv]->disk_read((uint8_t*)buff, sector, count))
+ return RES_PARERR;
+ else
+ return RES_OK;
+}
+
+#if _READONLY == 0
+DRESULT disk_write (
+ BYTE drv, /* Physical drive nmuber (0..) */
+ const BYTE *buff, /* Data to be written */
+ DWORD sector, /* Sector address (LBA) */
+ BYTE count /* Number of sectors to write (1..255) */
+)
+{
+ debug_if(FFS_DBG, "disk_write(sector %d, count %d) on drv [%d]\n", sector, count, drv);
+ if (FATFileSystem::_ffs[drv]->disk_write((uint8_t*)buff, sector, count))
+ return RES_PARERR;
+ else
+ return RES_OK;
+}
+#endif /* _READONLY */
+
+DRESULT disk_ioctl (
+ BYTE drv, /* Physical drive nmuber (0..) */
+ BYTE ctrl, /* Control code */
+ void *buff /* Buffer to send/receive control data */
+)
+{
+ debug_if(FFS_DBG, "disk_ioctl(%d)\n", ctrl);
+ switch(ctrl) {
+ case CTRL_SYNC:
+ if(FATFileSystem::_ffs[drv] == NULL) {
+ return RES_NOTRDY;
+ } else if(FATFileSystem::_ffs[drv]->disk_sync()) {
+ return RES_ERROR;
+ }
+ return RES_OK;
+ case GET_SECTOR_COUNT:
+ if(FATFileSystem::_ffs[drv] == NULL) {
+ return RES_NOTRDY;
+ } else {
+ DWORD res = FATFileSystem::_ffs[drv]->disk_sectors();
+ if(res > 0) {
+ *((DWORD*)buff) = res; // minimum allowed
+ return RES_OK;
+ } else {
+ return RES_ERROR;
+ }
+ }
+ case GET_BLOCK_SIZE:
+ *((DWORD*)buff) = 1; // default when not known
+ return RES_OK;
+
+ }
+ return RES_PARERR;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/diskio.h b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/diskio.h
new file mode 100644
index 000000000..a469ebb85
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/diskio.h
@@ -0,0 +1,76 @@
+//-----------------------------------------------------------------------
+// Low level disk interface modlue include file
+//-----------------------------------------------------------------------
+
+#ifndef _DISKIO
+
+#define _READONLY 0 // 1: Remove write functions
+#define _USE_IOCTL 1 // 1: Use disk_ioctl fucntion
+
+#include "integer.h"
+
+
+// Status of Disk Functions
+typedef BYTE DSTATUS;
+
+// Results of Disk Functions
+typedef enum {
+ RES_OK = 0, // 0: Successful
+ RES_ERROR, // 1: R/W Error
+ RES_WRPRT, // 2: Write Protected
+ RES_NOTRDY, // 3: Not Ready
+ RES_PARERR // 4: Invalid Parameter
+} DRESULT;
+
+
+// Prototypes for disk control functions
+
+int assign_drives (int, int);
+DSTATUS disk_initialize (BYTE);
+DSTATUS disk_status (BYTE);
+DRESULT disk_read (BYTE, BYTE*, DWORD, BYTE);
+#if _READONLY == 0
+DRESULT disk_write (BYTE, const BYTE*, DWORD, BYTE);
+#endif
+DRESULT disk_ioctl (BYTE, BYTE, void*);
+
+
+
+// Disk Status Bits (DSTATUS)
+#define STA_NOINIT 0x01 // Drive not initialized
+#define STA_NODISK 0x02 // No medium in the drive
+#define STA_PROTECT 0x04 // Write protected
+
+
+// Command code for disk_ioctrl fucntion
+
+// Generic command (defined for FatFs)
+#define CTRL_SYNC 0 // Flush disk cache (for write functions)
+#define GET_SECTOR_COUNT 1 // Get media size (for only f_mkfs())
+#define GET_SECTOR_SIZE 2 // Get sector size (for multiple sector size (_MAX_SS >= 1024))
+#define GET_BLOCK_SIZE 3 // Get erase block size (for only f_mkfs())
+#define CTRL_ERASE_SECTOR 4 // Force erased a block of sectors (for only _USE_ERASE)
+
+// Generic command
+#define CTRL_POWER 5 // Get/Set power status
+#define CTRL_LOCK 6 // Lock/Unlock media removal
+#define CTRL_EJECT 7 // Eject media
+
+// MMC/SDC specific ioctl command
+#define MMC_GET_TYPE 10 // Get card type
+#define MMC_GET_CSD 11 // Get CSD
+#define MMC_GET_CID 12 // Get CID
+#define MMC_GET_OCR 13 // Get OCR
+#define MMC_GET_SDSTAT 14 // Get SD status
+
+// ATA/CF specific ioctl command
+#define ATA_GET_REV 20 // Get F/W revision
+#define ATA_GET_MODEL 21 // Get model name
+#define ATA_GET_SN 22 // Get serial number
+
+// NAND specific ioctl command
+#define NAND_FORMAT 30 // Create physical format
+
+
+#define _DISKIO
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ff.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ff.cpp
new file mode 100644
index 000000000..fe786a747
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ff.cpp
@@ -0,0 +1,4153 @@
+/*----------------------------------------------------------------------------/
+/ FatFs - FAT file system module R0.09a (C)ChaN, 2012
+/-----------------------------------------------------------------------------/
+/ FatFs module is a generic FAT file system module for small embedded systems.
+/ This is a free software that opened for education, research and commercial
+/ developments under license policy of following terms.
+/
+/ Copyright (C) 2012, ChaN, all right reserved.
+/
+/ * The FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-----------------------------------------------------------------------------/
+/ Feb 26,'06 R0.00 Prototype.
+/
+/ Apr 29,'06 R0.01 First stable version.
+/
+/ Jun 01,'06 R0.02 Added FAT12 support.
+/ Removed unbuffered mode.
+/ Fixed a problem on small (<32M) partition.
+/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM).
+/
+/ Sep 22,'06 R0.03 Added f_rename().
+/ Changed option _FS_MINIMUM to _FS_MINIMIZE.
+/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast.
+/ Fixed f_mkdir() creates incorrect directory on FAT32.
+/
+/ Feb 04,'07 R0.04 Supported multiple drive system.
+/ Changed some interfaces for multiple drive system.
+/ Changed f_mountdrv() to f_mount().
+/ Added f_mkfs().
+/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive.
+/ Added a capability of extending file size to f_lseek().
+/ Added minimization level 3.
+/ Fixed an endian sensitive code in f_mkfs().
+/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG.
+/ Added FSInfo support.
+/ Fixed DBCS name can result FR_INVALID_NAME.
+/ Fixed short seek (<= csize) collapses the file object.
+/
+/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs().
+/ Fixed f_mkfs() on FAT32 creates incorrect FSInfo.
+/ Fixed f_mkdir() on FAT32 creates incorrect directory.
+/ Feb 03,'08 R0.05a Added f_truncate() and f_utime().
+/ Fixed off by one error at FAT sub-type determination.
+/ Fixed btr in f_read() can be mistruncated.
+/ Fixed cached sector is not flushed when create and close without write.
+/
+/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets().
+/ Improved performance of f_lseek() on moving to the same or following cluster.
+/
+/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a configuration option. (_FS_TINY)
+/ Added long file name feature.
+/ Added multiple code page feature.
+/ Added re-entrancy for multitask operation.
+/ Added auto cluster size selection to f_mkfs().
+/ Added rewind option to f_readdir().
+/ Changed result code of critical errors.
+/ Renamed string functions to avoid name collision.
+/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg.
+/ Added multiple sector size feature.
+/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error.
+/ Fixed wrong cache control in f_lseek().
+/ Added relative path feature.
+/ Added f_chdir() and f_chdrive().
+/ Added proper case conversion to extended char.
+/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h.
+/ Fixed f_unlink() fails to remove a sub-dir on _FS_RPATH.
+/ Fixed name matching error on the 13 char boundary.
+/ Added a configuration option, _LFN_UNICODE.
+/ Changed f_readdir() to return the SFN with always upper case on non-LFN cfg.
+/
+/ May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3)
+/ Added file lock feature. (_FS_SHARE)
+/ Added fast seek feature. (_USE_FASTSEEK)
+/ Changed some types on the API, XCHAR->TCHAR.
+/ Changed fname member in the FILINFO structure on Unicode cfg.
+/ String functions support UTF-8 encoding files on Unicode cfg.
+/ Aug 16,'10 R0.08a Added f_getcwd(). (_FS_RPATH = 2)
+/ Added sector erase feature. (_USE_ERASE)
+/ Moved file lock semaphore table from fs object to the bss.
+/ Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'.
+/ Fixed f_mkfs() creates wrong FAT32 volume.
+/ Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write().
+/ f_lseek() reports required table size on creating CLMP.
+/ Extended format syntax of f_printf function.
+/ Ignores duplicated directory separators in given path name.
+/
+/ Sep 06,'11 R0.09 f_mkfs() supports multiple partition to finish the multiple partition feature.
+/ Added f_fdisk(). (_MULTI_PARTITION = 2)
+/ Aug 27,'12 R0.09a Fixed assertion failure due to OS/2 EA on FAT12/16 volume.
+/ Changed f_open() and f_opendir reject null object pointer to avoid crash.
+/ Changed option name _FS_SHARE to _FS_LOCK.
+/---------------------------------------------------------------------------*/
+
+#include "ff.h" /* FatFs configurations and declarations */
+#include "diskio.h" /* Declarations of low level disk I/O functions */
+
+
+/*--------------------------------------------------------------------------
+
+ Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+#if _FATFS != 4004 /* Revision ID */
+#error Wrong include file (ff.h).
+#endif
+
+
+/* Definitions on sector size */
+#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096
+#error Wrong sector size.
+#endif
+#if _MAX_SS != 512
+#define SS(fs) ((fs)->ssize) /* Variable sector size */
+#else
+#define SS(fs) 512U /* Fixed sector size */
+#endif
+
+
+/* Reentrancy related */
+#if _FS_REENTRANT
+#if _USE_LFN == 1
+#error Static LFN work area must not be used in re-entrant configuration.
+#endif
+#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; }
+#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; }
+#else
+#define ENTER_FF(fs)
+#define LEAVE_FF(fs, res) return res
+#endif
+
+#define ABORT(fs, res) { fp->flag |= FA__ERROR; LEAVE_FF(fs, res); }
+
+
+/* File access control feature */
+#if _FS_LOCK
+#if _FS_READONLY
+#error _FS_LOCK must be 0 on read-only cfg.
+#endif
+typedef struct {
+ FATFS *fs; /* File ID 1, volume (NULL:blank entry) */
+ DWORD clu; /* File ID 2, directory */
+ WORD idx; /* File ID 3, directory index */
+ WORD ctr; /* File open counter, 0:none, 0x01..0xFF:read open count, 0x100:write mode */
+} FILESEM;
+#endif
+
+
+
+/* DBCS code ranges and SBCS extend char conversion table */
+
+#if _CODE_PAGE == 932 /* Japanese Shift-JIS */
+#define _DF1S 0x81 /* DBC 1st byte range 1 start */
+#define _DF1E 0x9F /* DBC 1st byte range 1 end */
+#define _DF2S 0xE0 /* DBC 1st byte range 2 start */
+#define _DF2E 0xFC /* DBC 1st byte range 2 end */
+#define _DS1S 0x40 /* DBC 2nd byte range 1 start */
+#define _DS1E 0x7E /* DBC 2nd byte range 1 end */
+#define _DS2S 0x80 /* DBC 2nd byte range 2 start */
+#define _DS2E 0xFC /* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */
+#define _DF1S 0x81
+#define _DF1E 0xFE
+#define _DS1S 0x40
+#define _DS1E 0x7E
+#define _DS2S 0x80
+#define _DS2E 0xFE
+
+#elif _CODE_PAGE == 949 /* Korean */
+#define _DF1S 0x81
+#define _DF1E 0xFE
+#define _DS1S 0x41
+#define _DS1E 0x5A
+#define _DS2S 0x61
+#define _DS2E 0x7A
+#define _DS3S 0x81
+#define _DS3E 0xFE
+
+#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */
+#define _DF1S 0x81
+#define _DF1E 0xFE
+#define _DS1S 0x40
+#define _DS1E 0x7E
+#define _DS2S 0xA1
+#define _DS2E 0xFE
+
+#elif _CODE_PAGE == 437 /* U.S. (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720 /* Arabic (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737 /* Greek (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+ 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775 /* Baltic (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
+ 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+ 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+ 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857 /* Turkish (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+ 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+ 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862 /* Hebrew (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866 /* Russian (OEM) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+ 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
+
+#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1253 /* Greek (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
+ 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
+
+#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+ 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
+#define _DF1S 0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
+ 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+ 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
+
+#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */
+#if _USE_LFN
+#error Cannot use LFN feature without valid code page.
+#endif
+#define _DF1S 0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+/* Character code support macros */
+#define IsUpper(c) (((c)>='A')&&((c)<='Z'))
+#define IsLower(c) (((c)>='a')&&((c)<='z'))
+#define IsDigit(c) (((c)>='0')&&((c)<='9'))
+
+#if _DF1S /* Code page is DBCS */
+
+#ifdef _DF2S /* Two 1st byte areas */
+#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else /* One 1st byte area */
+#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S /* Three 2nd byte areas */
+#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else /* Two 2nd byte areas */
+#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else /* Code page is SBCS */
+
+#define IsDBCS1(c) 0
+#define IsDBCS2(c) 0
+
+#endif /* _DF1S */
+
+
+/* Name status flags */
+#define NS 11 /* Index of name status byte in fn[] */
+#define NS_LOSS 0x01 /* Out of 8.3 format */
+#define NS_LFN 0x02 /* Force to create LFN entry */
+#define NS_LAST 0x04 /* Last segment */
+#define NS_BODY 0x08 /* Lower case flag (body) */
+#define NS_EXT 0x10 /* Lower case flag (ext) */
+#define NS_DOT 0x20 /* Dot entry */
+
+
+/* FAT sub-type boundaries */
+/* Note that the FAT spec by Microsoft says 4085 but Windows works with 4087! */
+#define MIN_FAT16 4086 /* Minimum number of clusters for FAT16 */
+#define MIN_FAT32 65526 /* Minimum number of clusters for FAT32 */
+
+
+/* FatFs refers the members in the FAT structures as byte array instead of
+/ structure member because the structure is not binary compatible between
+/ different platforms */
+
+#define BS_jmpBoot 0 /* Jump instruction (3) */
+#define BS_OEMName 3 /* OEM name (8) */
+#define BPB_BytsPerSec 11 /* Sector size [byte] (2) */
+#define BPB_SecPerClus 13 /* Cluster size [sector] (1) */
+#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (2) */
+#define BPB_NumFATs 16 /* Number of FAT copies (1) */
+#define BPB_RootEntCnt 17 /* Number of root dir entries for FAT12/16 (2) */
+#define BPB_TotSec16 19 /* Volume size [sector] (2) */
+#define BPB_Media 21 /* Media descriptor (1) */
+#define BPB_FATSz16 22 /* FAT size [sector] (2) */
+#define BPB_SecPerTrk 24 /* Track size [sector] (2) */
+#define BPB_NumHeads 26 /* Number of heads (2) */
+#define BPB_HiddSec 28 /* Number of special hidden sectors (4) */
+#define BPB_TotSec32 32 /* Volume size [sector] (4) */
+#define BS_DrvNum 36 /* Physical drive number (2) */
+#define BS_BootSig 38 /* Extended boot signature (1) */
+#define BS_VolID 39 /* Volume serial number (4) */
+#define BS_VolLab 43 /* Volume label (8) */
+#define BS_FilSysType 54 /* File system type (1) */
+#define BPB_FATSz32 36 /* FAT size [sector] (4) */
+#define BPB_ExtFlags 40 /* Extended flags (2) */
+#define BPB_FSVer 42 /* File system version (2) */
+#define BPB_RootClus 44 /* Root dir first cluster (4) */
+#define BPB_FSInfo 48 /* Offset of FSInfo sector (2) */
+#define BPB_BkBootSec 50 /* Offset of backup boot sector (2) */
+#define BS_DrvNum32 64 /* Physical drive number (2) */
+#define BS_BootSig32 66 /* Extended boot signature (1) */
+#define BS_VolID32 67 /* Volume serial number (4) */
+#define BS_VolLab32 71 /* Volume label (8) */
+#define BS_FilSysType32 82 /* File system type (1) */
+#define FSI_LeadSig 0 /* FSI: Leading signature (4) */
+#define FSI_StrucSig 484 /* FSI: Structure signature (4) */
+#define FSI_Free_Count 488 /* FSI: Number of free clusters (4) */
+#define FSI_Nxt_Free 492 /* FSI: Last allocated cluster (4) */
+#define MBR_Table 446 /* MBR: Partition table offset (2) */
+#define SZ_PTE 16 /* MBR: Size of a partition table entry */
+#define BS_55AA 510 /* Boot sector signature (2) */
+
+#define DIR_Name 0 /* Short file name (11) */
+#define DIR_Attr 11 /* Attribute (1) */
+#define DIR_NTres 12 /* NT flag (1) */
+#define DIR_CrtTimeTenth 13 /* Created time sub-second (1) */
+#define DIR_CrtTime 14 /* Created time (2) */
+#define DIR_CrtDate 16 /* Created date (2) */
+#define DIR_LstAccDate 18 /* Last accessed date (2) */
+#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (2) */
+#define DIR_WrtTime 22 /* Modified time (2) */
+#define DIR_WrtDate 24 /* Modified date (2) */
+#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (2) */
+#define DIR_FileSize 28 /* File size (4) */
+#define LDIR_Ord 0 /* LFN entry order and LLE flag (1) */
+#define LDIR_Attr 11 /* LFN attribute (1) */
+#define LDIR_Type 12 /* LFN type (1) */
+#define LDIR_Chksum 13 /* Sum of corresponding SFN entry */
+#define LDIR_FstClusLO 26 /* Filled by zero (0) */
+#define SZ_DIR 32 /* Size of a directory entry */
+#define LLE 0x40 /* Last long entry flag in LDIR_Ord */
+#define DDE 0xE5 /* Deleted directory entry mark in DIR_Name[0] */
+#define NDDE 0x05 /* Replacement of the character collides with DDE */
+
+
+/*------------------------------------------------------------*/
+/* Module private work area */
+/*------------------------------------------------------------*/
+/* Note that uninitialized variables with static duration are
+/ zeroed/nulled at start-up. If not, the compiler or start-up
+/ routine is out of ANSI-C standard.
+*/
+
+#if _VOLUMES
+static
+FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */
+#else
+#error Number of volumes must not be 0.
+#endif
+
+static
+WORD Fsid; /* File system mount ID */
+
+#if _FS_RPATH
+static
+BYTE CurrVol; /* Current drive */
+#endif
+
+#if _FS_LOCK
+static
+FILESEM Files[_FS_LOCK]; /* File lock semaphores */
+#endif
+
+#if _USE_LFN == 0 /* No LFN feature */
+#define DEF_NAMEBUF BYTE sfn[12]
+#define INIT_BUF(dobj) (dobj).fn = sfn
+#define FREE_BUF()
+
+#elif _USE_LFN == 1 /* LFN feature with static working buffer */
+static WCHAR LfnBuf[_MAX_LFN+1];
+#define DEF_NAMEBUF BYTE sfn[12]
+#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = LfnBuf; }
+#define FREE_BUF()
+
+#elif _USE_LFN == 2 /* LFN feature with dynamic working buffer on the stack */
+#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1]
+#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; }
+#define FREE_BUF()
+
+#elif _USE_LFN == 3 /* LFN feature with dynamic working buffer on the heap */
+#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn
+#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \
+ if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \
+ (dobj).lfn = lfn; (dobj).fn = sfn; }
+#define FREE_BUF() ff_memfree(lfn)
+
+#else
+#error Wrong LFN configuration.
+#endif
+
+
+
+
+/*--------------------------------------------------------------------------
+
+ Module Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------------------*/
+/* String functions */
+/*-----------------------------------------------------------------------*/
+
+/* Copy memory to memory */
+static
+void mem_cpy (void* dst, const void* src, UINT cnt) {
+ BYTE *d = (BYTE*)dst;
+ const BYTE *s = (const BYTE*)src;
+
+#if _WORD_ACCESS == 1
+ while (cnt >= sizeof (int)) {
+ *(int*)d = *(int*)s;
+ d += sizeof (int); s += sizeof (int);
+ cnt -= sizeof (int);
+ }
+#endif
+ while (cnt--)
+ *d++ = *s++;
+}
+
+/* Fill memory */
+static
+void mem_set (void* dst, int val, UINT cnt) {
+ BYTE *d = (BYTE*)dst;
+
+ while (cnt--)
+ *d++ = (BYTE)val;
+}
+
+/* Compare memory to memory */
+static
+int mem_cmp (const void* dst, const void* src, UINT cnt) {
+ const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src;
+ int r = 0;
+
+ while (cnt-- && (r = *d++ - *s++) == 0) ;
+ return r;
+}
+
+/* Check if chr is contained in the string */
+static
+int chk_chr (const char* str, int chr) {
+ while (*str && *str != chr) str++;
+ return *str;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Request/Release grant to access the volume */
+/*-----------------------------------------------------------------------*/
+#if _FS_REENTRANT
+
+static
+int lock_fs (
+ FATFS *fs /* File system object */
+)
+{
+ return ff_req_grant(fs->sobj);
+}
+
+
+static
+void unlock_fs (
+ FATFS *fs, /* File system object */
+ FRESULT res /* Result code to be returned */
+)
+{
+ if (fs &&
+ res != FR_NOT_ENABLED &&
+ res != FR_INVALID_DRIVE &&
+ res != FR_INVALID_OBJECT &&
+ res != FR_TIMEOUT) {
+ ff_rel_grant(fs->sobj);
+ }
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* File lock control functions */
+/*-----------------------------------------------------------------------*/
+#if _FS_LOCK
+
+static
+FRESULT chk_lock ( /* Check if the file can be accessed */
+ DIR* dj, /* Directory object pointing the file to be checked */
+ int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */
+)
+{
+ UINT i, be;
+
+ /* Search file semaphore table */
+ for (i = be = 0; i < _FS_LOCK; i++) {
+ if (Files[i].fs) { /* Existing entry */
+ if (Files[i].fs == dj->fs && /* Check if the file matched with an open file */
+ Files[i].clu == dj->sclust &&
+ Files[i].idx == dj->index) break;
+ } else { /* Blank entry */
+ be++;
+ }
+ }
+ if (i == _FS_LOCK) /* The file is not opened */
+ return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new file? */
+
+ /* The file has been opened. Reject any open against writing file and all write mode open */
+ return (acc || Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK;
+}
+
+
+static
+int enq_lock (void) /* Check if an entry is available for a new file */
+{
+ UINT i;
+
+ for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ return (i == _FS_LOCK) ? 0 : 1;
+}
+
+
+static
+UINT inc_lock ( /* Increment file open counter and returns its index (0:int error) */
+ DIR* dj, /* Directory object pointing the file to register or increment */
+ int acc /* Desired access mode (0:Read, !0:Write) */
+)
+{
+ UINT i;
+
+
+ for (i = 0; i < _FS_LOCK; i++) { /* Find the file */
+ if (Files[i].fs == dj->fs &&
+ Files[i].clu == dj->sclust &&
+ Files[i].idx == dj->index) break;
+ }
+
+ if (i == _FS_LOCK) { /* Not opened. Register it as new. */
+ for (i = 0; i < _FS_LOCK && Files[i].fs; i++) ;
+ if (i == _FS_LOCK) return 0; /* No space to register (int err) */
+ Files[i].fs = dj->fs;
+ Files[i].clu = dj->sclust;
+ Files[i].idx = dj->index;
+ Files[i].ctr = 0;
+ }
+
+ if (acc && Files[i].ctr) return 0; /* Access violation (int err) */
+
+ Files[i].ctr = acc ? 0x100 : Files[i].ctr + 1; /* Set semaphore value */
+
+ return i + 1;
+}
+
+
+static
+FRESULT dec_lock ( /* Decrement file open counter */
+ UINT i /* Semaphore index */
+)
+{
+ WORD n;
+ FRESULT res;
+
+
+ if (--i < _FS_LOCK) {
+ n = Files[i].ctr;
+ if (n == 0x100) n = 0;
+ if (n) n--;
+ Files[i].ctr = n;
+ if (!n) Files[i].fs = 0;
+ res = FR_OK;
+ } else {
+ res = FR_INT_ERR;
+ }
+ return res;
+}
+
+
+static
+void clear_lock ( /* Clear lock entries of the volume */
+ FATFS *fs
+)
+{
+ UINT i;
+
+ for (i = 0; i < _FS_LOCK; i++) {
+ if (Files[i].fs == fs) Files[i].fs = 0;
+ }
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change window offset */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT move_window (
+ FATFS *fs, /* File system object */
+ DWORD sector /* Sector number to make appearance in the fs->win[] */
+) /* Move to zero only writes back dirty window */
+{
+ DWORD wsect;
+
+
+ wsect = fs->winsect;
+ if (wsect != sector) { /* Changed current window */
+#if !_FS_READONLY
+ if (fs->wflag) { /* Write back dirty window if needed */
+ if (disk_write(fs->drv, fs->win, wsect, 1) != RES_OK)
+ return FR_DISK_ERR;
+ fs->wflag = 0;
+ if (wsect < (fs->fatbase + fs->fsize)) { /* In FAT area */
+ BYTE nf;
+ for (nf = fs->n_fats; nf > 1; nf--) { /* Reflect the change to all FAT copies */
+ wsect += fs->fsize;
+ disk_write(fs->drv, fs->win, wsect, 1);
+ }
+ }
+ }
+#endif
+ if (sector) {
+ if (disk_read(fs->drv, fs->win, sector, 1) != RES_OK)
+ return FR_DISK_ERR;
+ fs->winsect = sector;
+ }
+ }
+
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Clean-up cached data */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT sync ( /* FR_OK: successful, FR_DISK_ERR: failed */
+ FATFS *fs /* File system object */
+)
+{
+ FRESULT res;
+
+
+ res = move_window(fs, 0);
+ if (res == FR_OK) {
+ /* Update FSInfo sector if needed */
+ if (fs->fs_type == FS_FAT32 && fs->fsi_flag) {
+ fs->winsect = 0;
+ /* Create FSInfo structure */
+ mem_set(fs->win, 0, 512);
+ ST_WORD(fs->win+BS_55AA, 0xAA55);
+ ST_DWORD(fs->win+FSI_LeadSig, 0x41615252);
+ ST_DWORD(fs->win+FSI_StrucSig, 0x61417272);
+ ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust);
+ ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust);
+ /* Write it into the FSInfo sector */
+ disk_write(fs->drv, fs->win, fs->fsi_sector, 1);
+ fs->fsi_flag = 0;
+ }
+ /* Make sure that no pending write process in the physical drive */
+ if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK)
+ res = FR_DISK_ERR;
+ }
+
+ return res;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster# */
+/*-----------------------------------------------------------------------*/
+
+
+DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */
+ FATFS *fs, /* File system object */
+ DWORD clst /* Cluster# to be converted */
+)
+{
+ clst -= 2;
+ if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */
+ return clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry */
+/*-----------------------------------------------------------------------*/
+
+
+DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */
+ FATFS *fs, /* File system object */
+ DWORD clst /* Cluster# to get the link information */
+)
+{
+ UINT wc, bc;
+ BYTE *p;
+
+
+ if (clst < 2 || clst >= fs->n_fatent) /* Check range */
+ return 1;
+
+ switch (fs->fs_type) {
+ case FS_FAT12 :
+ bc = (UINT)clst; bc += bc / 2;
+ if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
+ wc = fs->win[bc % SS(fs)]; bc++;
+ if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break;
+ wc |= fs->win[bc % SS(fs)] << 8;
+ return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+
+ case FS_FAT16 :
+ if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break;
+ p = &fs->win[clst * 2 % SS(fs)];
+ return LD_WORD(p);
+
+ case FS_FAT32 :
+ if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break;
+ p = &fs->win[clst * 4 % SS(fs)];
+ return LD_DWORD(p) & 0x0FFFFFFF;
+ }
+
+ return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Change value of a FAT entry */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+
+FRESULT put_fat (
+ FATFS *fs, /* File system object */
+ DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */
+ DWORD val /* New value to mark the cluster */
+)
+{
+ UINT bc;
+ BYTE *p;
+ FRESULT res;
+
+
+ if (clst < 2 || clst >= fs->n_fatent) { /* Check range */
+ res = FR_INT_ERR;
+
+ } else {
+ switch (fs->fs_type) {
+ case FS_FAT12 :
+ bc = (UINT)clst; bc += bc / 2;
+ res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+ if (res != FR_OK) break;
+ p = &fs->win[bc % SS(fs)];
+ *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val;
+ bc++;
+ fs->wflag = 1;
+ res = move_window(fs, fs->fatbase + (bc / SS(fs)));
+ if (res != FR_OK) break;
+ p = &fs->win[bc % SS(fs)];
+ *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F));
+ break;
+
+ case FS_FAT16 :
+ res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)));
+ if (res != FR_OK) break;
+ p = &fs->win[clst * 2 % SS(fs)];
+ ST_WORD(p, (WORD)val);
+ break;
+
+ case FS_FAT32 :
+ res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)));
+ if (res != FR_OK) break;
+ p = &fs->win[clst * 4 % SS(fs)];
+ val |= LD_DWORD(p) & 0xF0000000;
+ ST_DWORD(p, val);
+ break;
+
+ default :
+ res = FR_INT_ERR;
+ }
+ fs->wflag = 1;
+ }
+
+ return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Remove a cluster chain */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT remove_chain (
+ FATFS *fs, /* File system object */
+ DWORD clst /* Cluster# to remove a chain from */
+)
+{
+ FRESULT res;
+ DWORD nxt;
+#if _USE_ERASE
+ DWORD scl = clst, ecl = clst, rt[2];
+#endif
+
+ if (clst < 2 || clst >= fs->n_fatent) { /* Check range */
+ res = FR_INT_ERR;
+
+ } else {
+ res = FR_OK;
+ while (clst < fs->n_fatent) { /* Not a last link? */
+ nxt = get_fat(fs, clst); /* Get cluster status */
+ if (nxt == 0) break; /* Empty cluster? */
+ if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */
+ if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */
+ res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */
+ if (res != FR_OK) break;
+ if (fs->free_clust != 0xFFFFFFFF) { /* Update FSInfo */
+ fs->free_clust++;
+ fs->fsi_flag = 1;
+ }
+#if _USE_ERASE
+ if (ecl + 1 == nxt) { /* Is next cluster contiguous? */
+ ecl = nxt;
+ } else { /* End of contiguous clusters */
+ rt[0] = clust2sect(fs, scl); /* Start sector */
+ rt[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */
+ disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, rt); /* Erase the block */
+ scl = ecl = nxt;
+ }
+#endif
+ clst = nxt; /* Next cluster */
+ }
+ }
+
+ return res;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Stretch or Create a cluster chain */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */
+ FATFS *fs, /* File system object */
+ DWORD clst /* Cluster# to stretch. 0 means create a new chain. */
+)
+{
+ DWORD cs, ncl, scl;
+ FRESULT res;
+
+
+ if (clst == 0) { /* Create a new chain */
+ scl = fs->last_clust; /* Get suggested start point */
+ if (!scl || scl >= fs->n_fatent) scl = 1;
+ }
+ else { /* Stretch the current chain */
+ cs = get_fat(fs, clst); /* Check the cluster status */
+ if (cs < 2) return 1; /* It is an invalid cluster */
+ if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */
+ scl = clst;
+ }
+
+ ncl = scl; /* Start cluster */
+ for (;;) {
+ ncl++; /* Next cluster */
+ if (ncl >= fs->n_fatent) { /* Wrap around */
+ ncl = 2;
+ if (ncl > scl) return 0; /* No free cluster */
+ }
+ cs = get_fat(fs, ncl); /* Get the cluster status */
+ if (cs == 0) break; /* Found a free cluster */
+ if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */
+ return cs;
+ if (ncl == scl) return 0; /* No free cluster */
+ }
+
+ res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */
+ if (res == FR_OK && clst != 0) {
+ res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */
+ }
+ if (res == FR_OK) {
+ fs->last_clust = ncl; /* Update FSINFO */
+ if (fs->free_clust != 0xFFFFFFFF) {
+ fs->free_clust--;
+ fs->fsi_flag = 1;
+ }
+ } else {
+ ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1;
+ }
+
+ return ncl; /* Return new cluster number or error code */
+}
+#endif /* !_FS_READONLY */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT handling - Convert offset into cluster with link map table */
+/*-----------------------------------------------------------------------*/
+
+#if _USE_FASTSEEK
+static
+DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */
+ FIL* fp, /* Pointer to the file object */
+ DWORD ofs /* File offset to be converted to cluster# */
+)
+{
+ DWORD cl, ncl, *tbl;
+
+
+ tbl = fp->cltbl + 1; /* Top of CLMT */
+ cl = ofs / SS(fp->fs) / fp->fs->csize; /* Cluster order from top of the file */
+ for (;;) {
+ ncl = *tbl++; /* Number of cluters in the fragment */
+ if (!ncl) return 0; /* End of table? (error) */
+ if (cl < ncl) break; /* In this fragment? */
+ cl -= ncl; tbl++; /* Next fragment */
+ }
+ return cl + *tbl; /* Return the cluster number */
+}
+#endif /* _USE_FASTSEEK */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Set directory index */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_sdi (
+ FATFS_DIR *dj, /* Pointer to directory object */
+ WORD idx /* Index of directory table */
+)
+{
+ DWORD clst;
+ WORD ic;
+
+
+ dj->index = idx;
+ clst = dj->sclust;
+ if (clst == 1 || clst >= dj->fs->n_fatent) /* Check start cluster range */
+ return FR_INT_ERR;
+ if (!clst && dj->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */
+ clst = dj->fs->dirbase;
+
+ if (clst == 0) { /* Static table (root-dir in FAT12/16) */
+ dj->clust = clst;
+ if (idx >= dj->fs->n_rootdir) /* Index is out of range */
+ return FR_INT_ERR;
+ dj->sect = dj->fs->dirbase + idx / (SS(dj->fs) / SZ_DIR); /* Sector# */
+ }
+ else { /* Dynamic table (sub-dirs or root-dir in FAT32) */
+ ic = SS(dj->fs) / SZ_DIR * dj->fs->csize; /* Entries per cluster */
+ while (idx >= ic) { /* Follow cluster chain */
+ clst = get_fat(dj->fs, clst); /* Get next cluster */
+ if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */
+ if (clst < 2 || clst >= dj->fs->n_fatent) /* Reached to end of table or int error */
+ return FR_INT_ERR;
+ idx -= ic;
+ }
+ dj->clust = clst;
+ dj->sect = clust2sect(dj->fs, clst) + idx / (SS(dj->fs) / SZ_DIR); /* Sector# */
+ }
+
+ dj->dir = dj->fs->win + (idx % (SS(dj->fs) / SZ_DIR)) * SZ_DIR; /* Ptr to the entry in the sector */
+
+ return FR_OK; /* Seek succeeded */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory table index next */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:EOT and could not stretch */
+ FATFS_DIR *dj, /* Pointer to directory object */
+ int stretch /* 0: Do not stretch table, 1: Stretch table if needed */
+)
+{
+ DWORD clst;
+ WORD i;
+
+
+ stretch = stretch; /* To suppress warning on read-only cfg. */
+ i = dj->index + 1;
+ if (!i || !dj->sect) /* Report EOT when index has reached 65535 */
+ return FR_NO_FILE;
+
+ if (!(i % (SS(dj->fs) / SZ_DIR))) { /* Sector changed? */
+ dj->sect++; /* Next sector */
+
+ if (dj->clust == 0) { /* Static table */
+ if (i >= dj->fs->n_rootdir) /* Report EOT when end of table */
+ return FR_NO_FILE;
+ }
+ else { /* Dynamic table */
+ if (((i / (SS(dj->fs) / SZ_DIR)) & (dj->fs->csize - 1)) == 0) { /* Cluster changed? */
+ clst = get_fat(dj->fs, dj->clust); /* Get next cluster */
+ if (clst <= 1) return FR_INT_ERR;
+ if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
+ if (clst >= dj->fs->n_fatent) { /* When it reached end of dynamic table */
+#if !_FS_READONLY
+ BYTE c;
+ if (!stretch) return FR_NO_FILE; /* When do not stretch, report EOT */
+ clst = create_chain(dj->fs, dj->clust); /* Stretch cluster chain */
+ if (clst == 0) return FR_DENIED; /* No free cluster */
+ if (clst == 1) return FR_INT_ERR;
+ if (clst == 0xFFFFFFFF) return FR_DISK_ERR;
+ /* Clean-up stretched table */
+ if (move_window(dj->fs, 0)) return FR_DISK_ERR; /* Flush active window */
+ mem_set(dj->fs->win, 0, SS(dj->fs)); /* Clear window buffer */
+ dj->fs->winsect = clust2sect(dj->fs, clst); /* Cluster start sector */
+ for (c = 0; c < dj->fs->csize; c++) { /* Fill the new cluster with 0 */
+ dj->fs->wflag = 1;
+ if (move_window(dj->fs, 0)) return FR_DISK_ERR;
+ dj->fs->winsect++;
+ }
+ dj->fs->winsect -= c; /* Rewind window address */
+#else
+ return FR_NO_FILE; /* Report EOT */
+#endif
+ }
+ dj->clust = clst; /* Initialize data for new cluster */
+ dj->sect = clust2sect(dj->fs, clst);
+ }
+ }
+ }
+
+ dj->index = i;
+ dj->dir = dj->fs->win + (i % (SS(dj->fs) / SZ_DIR)) * SZ_DIR;
+
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Load/Store start cluster number */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD ld_clust (
+ FATFS *fs, /* Pointer to the fs object */
+ BYTE *dir /* Pointer to the directory entry */
+)
+{
+ DWORD cl;
+
+ cl = LD_WORD(dir+DIR_FstClusLO);
+ if (fs->fs_type == FS_FAT32)
+ cl |= (DWORD)LD_WORD(dir+DIR_FstClusHI) << 16;
+
+ return cl;
+}
+
+
+#if !_FS_READONLY
+static
+void st_clust (
+ BYTE *dir, /* Pointer to the directory entry */
+ DWORD cl /* Value to be set */
+)
+{
+ ST_WORD(dir+DIR_FstClusLO, cl);
+ ST_WORD(dir+DIR_FstClusHI, cl >> 16);
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+static
+const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN chars in the directory entry */
+
+
+static
+int cmp_lfn ( /* 1:Matched, 0:Not matched */
+ WCHAR *lfnbuf, /* Pointer to the LFN to be compared */
+ BYTE *dir /* Pointer to the directory entry containing a part of LFN */
+)
+{
+ UINT i, s;
+ WCHAR wc, uc;
+
+
+ i = ((dir[LDIR_Ord] & ~LLE) - 1) * 13; /* Get offset in the LFN buffer */
+ s = 0; wc = 1;
+ do {
+ uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */
+ if (wc) { /* Last char has not been processed */
+ wc = ff_wtoupper(uc); /* Convert it to upper case */
+ if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */
+ return 0; /* Not matched */
+ } else {
+ if (uc != 0xFFFF) return 0; /* Check filler */
+ }
+ } while (++s < 13); /* Repeat until all chars in the entry are checked */
+
+ if ((dir[LDIR_Ord] & LLE) && wc && lfnbuf[i]) /* Last segment matched but different length */
+ return 0;
+
+ return 1; /* The part of LFN matched */
+}
+
+
+
+static
+int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */
+ WCHAR *lfnbuf, /* Pointer to the Unicode-LFN buffer */
+ BYTE *dir /* Pointer to the directory entry */
+)
+{
+ UINT i, s;
+ WCHAR wc, uc;
+
+
+ i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */
+
+ s = 0; wc = 1;
+ do {
+ uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */
+ if (wc) { /* Last char has not been processed */
+ if (i >= _MAX_LFN) return 0; /* Buffer overflow? */
+ lfnbuf[i++] = wc = uc; /* Store it */
+ } else {
+ if (uc != 0xFFFF) return 0; /* Check filler */
+ }
+ } while (++s < 13); /* Read all character in the entry */
+
+ if (dir[LDIR_Ord] & LLE) { /* Put terminator if it is the last LFN part */
+ if (i >= _MAX_LFN) return 0; /* Buffer overflow? */
+ lfnbuf[i] = 0;
+ }
+
+ return 1;
+}
+
+
+#if !_FS_READONLY
+static
+void fit_lfn (
+ const WCHAR *lfnbuf, /* Pointer to the LFN buffer */
+ BYTE *dir, /* Pointer to the directory entry */
+ BYTE ord, /* LFN order (1-20) */
+ BYTE sum /* SFN sum */
+)
+{
+ UINT i, s;
+ WCHAR wc;
+
+
+ dir[LDIR_Chksum] = sum; /* Set check sum */
+ dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */
+ dir[LDIR_Type] = 0;
+ ST_WORD(dir+LDIR_FstClusLO, 0);
+
+ i = (ord - 1) * 13; /* Get offset in the LFN buffer */
+ s = wc = 0;
+ do {
+ if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective char */
+ ST_WORD(dir+LfnOfs[s], wc); /* Put it */
+ if (!wc) wc = 0xFFFF; /* Padding chars following last char */
+ } while (++s < 13);
+ if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLE; /* Bottom LFN part is the start of LFN sequence */
+ dir[LDIR_Ord] = ord; /* Set the LFN order */
+}
+
+#endif
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create numbered name */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+void gen_numname (
+ BYTE *dst, /* Pointer to generated SFN */
+ const BYTE *src, /* Pointer to source SFN to be modified */
+ const WCHAR *lfn, /* Pointer to LFN */
+ WORD seq /* Sequence number */
+)
+{
+ BYTE ns[8], c;
+ UINT i, j;
+
+
+ mem_cpy(dst, src, 11);
+
+ if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */
+ do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn);
+ }
+
+ /* itoa (hexdecimal) */
+ i = 7;
+ do {
+ c = (seq % 16) + '0';
+ if (c > '9') c += 7;
+ ns[i--] = c;
+ seq /= 16;
+ } while (seq);
+ ns[i] = '~';
+
+ /* Append the number */
+ for (j = 0; j < i && dst[j] != ' '; j++) {
+ if (IsDBCS1(dst[j])) {
+ if (j == i - 1) break;
+ j++;
+ }
+ }
+ do {
+ dst[j++] = (i < 8) ? ns[i++] : ' ';
+ } while (j < 8);
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Calculate sum of an SFN */
+/*-----------------------------------------------------------------------*/
+#if _USE_LFN
+static
+BYTE sum_sfn (
+ const BYTE *dir /* Ptr to directory entry */
+)
+{
+ BYTE sum = 0;
+ UINT n = 11;
+
+ do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n);
+ return sum;
+}
+#endif
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+ FATFS_DIR *dj /* Pointer to the directory object linked to the file name */
+)
+{
+ FRESULT res;
+ BYTE c, *dir;
+#if _USE_LFN
+ BYTE a, ord, sum;
+#endif
+
+ res = dir_sdi(dj, 0); /* Rewind directory object */
+ if (res != FR_OK) return res;
+
+#if _USE_LFN
+ ord = sum = 0xFF;
+#endif
+ do {
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ dir = dj->dir; /* Ptr to the directory entry of current index */
+ c = dir[DIR_Name];
+ if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */
+#if _USE_LFN /* LFN configuration */
+ a = dir[DIR_Attr] & AM_MASK;
+ if (c == DDE || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */
+ ord = 0xFF;
+ } else {
+ if (a == AM_LFN) { /* An LFN entry is found */
+ if (dj->lfn) {
+ if (c & LLE) { /* Is it start of LFN sequence? */
+ sum = dir[LDIR_Chksum];
+ c &= ~LLE; ord = c; /* LFN start order */
+ dj->lfn_idx = dj->index;
+ }
+ /* Check validity of the LFN entry and compare it with given name */
+ ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF;
+ }
+ } else { /* An SFN entry is found */
+ if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */
+ ord = 0xFF; dj->lfn_idx = 0xFFFF; /* Reset LFN sequence */
+ if (!(dj->fn[NS] & NS_LOSS) && !mem_cmp(dir, dj->fn, 11)) break; /* SFN matched? */
+ }
+ }
+#else /* Non LFN configuration */
+ if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
+ break;
+#endif
+ res = dir_next(dj, 0); /* Next entry */
+ } while (res == FR_OK);
+
+ return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory */
+/*-----------------------------------------------------------------------*/
+#if _FS_MINIMIZE <= 1
+static
+FRESULT dir_read (
+ FATFS_DIR *dj /* Pointer to the directory object that pointing the entry to be read */
+)
+{
+ FRESULT res;
+ BYTE c, *dir;
+#if _USE_LFN
+ BYTE a, ord = 0xFF, sum = 0xFF;
+#endif
+
+ res = FR_NO_FILE;
+ while (dj->sect) {
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ dir = dj->dir; /* Ptr to the directory entry of current index */
+ c = dir[DIR_Name];
+ if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */
+#if _USE_LFN /* LFN configuration */
+ a = dir[DIR_Attr] & AM_MASK;
+ if (c == DDE || (!_FS_RPATH && c == '.') || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */
+ ord = 0xFF;
+ } else {
+ if (a == AM_LFN) { /* An LFN entry is found */
+ if (c & LLE) { /* Is it start of LFN sequence? */
+ sum = dir[LDIR_Chksum];
+ c &= ~LLE; ord = c;
+ dj->lfn_idx = dj->index;
+ }
+ /* Check LFN validity and capture it */
+ ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dj->lfn, dir)) ? ord - 1 : 0xFF;
+ } else { /* An SFN entry is found */
+ if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */
+ dj->lfn_idx = 0xFFFF; /* It has no LFN. */
+ break;
+ }
+ }
+#else /* Non LFN configuration */
+ if (c != DDE && (_FS_RPATH || c != '.') && !(dir[DIR_Attr] & AM_VOL)) /* Is it a valid entry? */
+ break;
+#endif
+ res = dir_next(dj, 0); /* Next entry */
+ if (res != FR_OK) break;
+ }
+
+ if (res != FR_OK) dj->sect = 0;
+
+ return res;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Register an object to the directory */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY
+static
+FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */
+ FATFS_DIR *dj /* Target directory with object name to be created */
+)
+{
+ FRESULT res;
+ BYTE c, *dir;
+#if _USE_LFN /* LFN configuration */
+ WORD n, ne, is;
+ BYTE sn[12], *fn, sum;
+ WCHAR *lfn;
+
+
+ fn = dj->fn; lfn = dj->lfn;
+ mem_cpy(sn, fn, 12);
+
+ if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */
+ return FR_INVALID_NAME;
+
+ if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */
+ fn[NS] = 0; dj->lfn = 0; /* Find only SFN */
+ for (n = 1; n < 100; n++) {
+ gen_numname(fn, sn, lfn, n); /* Generate a numbered name */
+ res = dir_find(dj); /* Check if the name collides with existing SFN */
+ if (res != FR_OK) break;
+ }
+ if (n == 100) return FR_DENIED; /* Abort if too many collisions */
+ if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */
+ fn[NS] = sn[NS]; dj->lfn = lfn;
+ }
+
+ if (sn[NS] & NS_LFN) { /* When LFN is to be created, reserve an SFN + LFN entries. */
+ for (ne = 0; lfn[ne]; ne++) ;
+ ne = (ne + 25) / 13;
+ } else { /* Otherwise reserve only an SFN entry. */
+ ne = 1;
+ }
+
+ /* Reserve contiguous entries */
+ res = dir_sdi(dj, 0);
+ if (res != FR_OK) return res;
+ n = is = 0;
+ do {
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ c = *dj->dir; /* Check the entry status */
+ if (c == DDE || c == 0) { /* Is it a blank entry? */
+ if (n == 0) is = dj->index; /* First index of the contiguous entry */
+ if (++n == ne) break; /* A contiguous entry that required count is found */
+ } else {
+ n = 0; /* Not a blank entry. Restart to search */
+ }
+ res = dir_next(dj, 1); /* Next entry with table stretch */
+ } while (res == FR_OK);
+
+ if (res == FR_OK && ne > 1) { /* Initialize LFN entry if needed */
+ res = dir_sdi(dj, is);
+ if (res == FR_OK) {
+ sum = sum_sfn(dj->fn); /* Sum of the SFN tied to the LFN */
+ ne--;
+ do { /* Store LFN entries in bottom first */
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ fit_lfn(dj->lfn, dj->dir, (BYTE)ne, sum);
+ dj->fs->wflag = 1;
+ res = dir_next(dj, 0); /* Next entry */
+ } while (res == FR_OK && --ne);
+ }
+ }
+
+#else /* Non LFN configuration */
+ res = dir_sdi(dj, 0);
+ if (res == FR_OK) {
+ do { /* Find a blank entry for the SFN */
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ c = *dj->dir;
+ if (c == DDE || c == 0) break; /* Is it a blank entry? */
+ res = dir_next(dj, 1); /* Next entry with table stretch */
+ } while (res == FR_OK);
+ }
+#endif
+
+ if (res == FR_OK) { /* Initialize the SFN entry */
+ res = move_window(dj->fs, dj->sect);
+ if (res == FR_OK) {
+ dir = dj->dir;
+ mem_set(dir, 0, SZ_DIR); /* Clean the entry */
+ mem_cpy(dir, dj->fn, 11); /* Put SFN */
+#if _USE_LFN
+ dir[DIR_NTres] = *(dj->fn+NS) & (NS_BODY | NS_EXT); /* Put NT flag */
+#endif
+ dj->fs->wflag = 1;
+ }
+ }
+
+ return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Remove an object from the directory */
+/*-----------------------------------------------------------------------*/
+#if !_FS_READONLY && !_FS_MINIMIZE
+static
+FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */
+ FATFS_DIR *dj /* Directory object pointing the entry to be removed */
+)
+{
+ FRESULT res;
+#if _USE_LFN /* LFN configuration */
+ WORD i;
+
+ i = dj->index; /* SFN index */
+ res = dir_sdi(dj, (WORD)((dj->lfn_idx == 0xFFFF) ? i : dj->lfn_idx)); /* Goto the SFN or top of the LFN entries */
+ if (res == FR_OK) {
+ do {
+ res = move_window(dj->fs, dj->sect);
+ if (res != FR_OK) break;
+ *dj->dir = DDE; /* Mark the entry "deleted" */
+ dj->fs->wflag = 1;
+ if (dj->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */
+ res = dir_next(dj, 0); /* Next entry */
+ } while (res == FR_OK);
+ if (res == FR_NO_FILE) res = FR_INT_ERR;
+ }
+
+#else /* Non LFN configuration */
+ res = dir_sdi(dj, dj->index);
+ if (res == FR_OK) {
+ res = move_window(dj->fs, dj->sect);
+ if (res == FR_OK) {
+ *dj->dir = DDE; /* Mark the entry "deleted" */
+ dj->fs->wflag = 1;
+ }
+ }
+#endif
+
+ return res;
+}
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT create_name (
+ FATFS_DIR *dj, /* Pointer to the directory object */
+ const TCHAR **path /* Pointer to pointer to the segment in the path string */
+)
+{
+#ifdef _EXCVT
+ static const BYTE excvt[] = _EXCVT; /* Upper conversion table for extended chars */
+#endif
+
+#if _USE_LFN /* LFN configuration */
+ BYTE b, cf;
+ WCHAR w, *lfn;
+ UINT i, ni, si, di;
+ const TCHAR *p;
+
+ /* Create LFN in Unicode */
+ for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */
+ lfn = dj->lfn;
+ si = di = 0;
+ for (;;) {
+ w = p[si++]; /* Get a character */
+ if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */
+ if (di >= _MAX_LFN) /* Reject too long name */
+ return FR_INVALID_NAME;
+#if !_LFN_UNICODE
+ w &= 0xFF;
+ if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+ b = (BYTE)p[si++]; /* Get 2nd byte */
+ if (!IsDBCS2(b))
+ return FR_INVALID_NAME; /* Reject invalid sequence */
+ w = (w << 8) + b; /* Create a DBC */
+ }
+ w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */
+ if (!w) return FR_INVALID_NAME; /* Reject invalid code */
+#endif
+ if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal chars for LFN */
+ return FR_INVALID_NAME;
+ lfn[di++] = w; /* Store the Unicode char */
+ }
+ *path = &p[si]; /* Return pointer to the next segment */
+ cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */
+#if _FS_RPATH
+ if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */
+ (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) {
+ lfn[di] = 0;
+ for (i = 0; i < 11; i++)
+ dj->fn[i] = (i < di) ? '.' : ' ';
+ dj->fn[i] = cf | NS_DOT; /* This is a dot entry */
+ return FR_OK;
+ }
+#endif
+ while (di) { /* Strip trailing spaces and dots */
+ w = lfn[di-1];
+ if (w != ' ' && w != '.') break;
+ di--;
+ }
+ if (!di) return FR_INVALID_NAME; /* Reject nul string */
+
+ lfn[di] = 0; /* LFN is created */
+
+ /* Create SFN in directory form */
+ mem_set(dj->fn, ' ', 11);
+ for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */
+ if (si) cf |= NS_LOSS | NS_LFN;
+ while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */
+
+ b = i = 0; ni = 8;
+ for (;;) {
+ w = lfn[si++]; /* Get an LFN char */
+ if (!w) break; /* Break on end of the LFN */
+ if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */
+ cf |= NS_LOSS | NS_LFN; continue;
+ }
+
+ if (i >= ni || si == di) { /* Extension or end of SFN */
+ if (ni == 11) { /* Long extension */
+ cf |= NS_LOSS | NS_LFN; break;
+ }
+ if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */
+ if (si > di) break; /* No extension */
+ si = di; i = 8; ni = 11; /* Enter extension section */
+ b <<= 2; continue;
+ }
+
+ if (w >= 0x80) { /* Non ASCII char */
+#ifdef _EXCVT
+ w = ff_convert(w, 0); /* Unicode -> OEM code */
+ if (w) w = excvt[w - 0x80]; /* Convert extended char to upper (SBCS) */
+#else
+ w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */
+#endif
+ cf |= NS_LFN; /* Force create LFN entry */
+ }
+
+ if (_DF1S && w >= 0x100) { /* Double byte char (always false on SBCS cfg) */
+ if (i >= ni - 1) {
+ cf |= NS_LOSS | NS_LFN; i = ni; continue;
+ }
+ dj->fn[i++] = (BYTE)(w >> 8);
+ } else { /* Single byte char */
+ if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal chars for SFN */
+ w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */
+ } else {
+ if (IsUpper(w)) { /* ASCII large capital */
+ b |= 2;
+ } else {
+ if (IsLower(w)) { /* ASCII small capital */
+ b |= 1; w -= 0x20;
+ }
+ }
+ }
+ }
+ dj->fn[i++] = (BYTE)w;
+ }
+
+ if (dj->fn[0] == DDE) dj->fn[0] = NDDE; /* If the first char collides with deleted mark, replace it with 0x05 */
+
+ if (ni == 8) b <<= 2;
+ if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */
+ cf |= NS_LFN;
+ if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended char, NT flags are created */
+ if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */
+ if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */
+ }
+
+ dj->fn[NS] = cf; /* SFN is created */
+
+ return FR_OK;
+
+
+#else /* Non-LFN configuration */
+ BYTE b, c, d, *sfn;
+ UINT ni, si, i;
+ const char *p;
+
+ /* Create file name in directory form */
+ for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */
+ sfn = dj->fn;
+ mem_set(sfn, ' ', 11);
+ si = i = b = 0; ni = 8;
+#if _FS_RPATH
+ if (p[si] == '.') { /* Is this a dot entry? */
+ for (;;) {
+ c = (BYTE)p[si++];
+ if (c != '.' || si >= 3) break;
+ sfn[i++] = c;
+ }
+ if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME;
+ *path = &p[si]; /* Return pointer to the next segment */
+ sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */
+ return FR_OK;
+ }
+#endif
+ for (;;) {
+ c = (BYTE)p[si++];
+ if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */
+ if (c == '.' || i >= ni) {
+ if (ni != 8 || c != '.') return FR_INVALID_NAME;
+ i = 8; ni = 11;
+ b <<= 2; continue;
+ }
+ if (c >= 0x80) { /* Extended char? */
+ b |= 3; /* Eliminate NT flag */
+#ifdef _EXCVT
+ c = excvt[c - 0x80]; /* Upper conversion (SBCS) */
+#else
+#if !_DF1S /* ASCII only cfg */
+ return FR_INVALID_NAME;
+#endif
+#endif
+ }
+ if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */
+ d = (BYTE)p[si++]; /* Get 2nd byte */
+ if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */
+ return FR_INVALID_NAME;
+ sfn[i++] = c;
+ sfn[i++] = d;
+ } else { /* Single byte code */
+ if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */
+ return FR_INVALID_NAME;
+ if (IsUpper(c)) { /* ASCII large capital? */
+ b |= 2;
+ } else {
+ if (IsLower(c)) { /* ASCII small capital? */
+ b |= 1; c -= 0x20;
+ }
+ }
+ sfn[i++] = c;
+ }
+ }
+ *path = &p[si]; /* Return pointer to the next segment */
+ c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */
+
+ if (!i) return FR_INVALID_NAME; /* Reject nul string */
+ if (sfn[0] == DDE) sfn[0] = NDDE; /* When first char collides with DDE, replace it with 0x05 */
+
+ if (ni == 8) b <<= 2;
+ if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */
+ if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */
+
+ sfn[NS] = c; /* Store NT flag, File name is created */
+
+ return FR_OK;
+#endif
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry */
+/*-----------------------------------------------------------------------*/
+#if _FS_MINIMIZE <= 1
+static
+void get_fileinfo ( /* No return code */
+ FATFS_DIR *dj, /* Pointer to the directory object */
+ FILINFO *fno /* Pointer to the file information to be filled */
+)
+{
+ UINT i;
+ BYTE nt, *dir;
+ TCHAR *p, c;
+
+
+ p = fno->fname;
+ if (dj->sect) {
+ dir = dj->dir;
+ nt = dir[DIR_NTres]; /* NT flag */
+ for (i = 0; i < 8; i++) { /* Copy name body */
+ c = dir[i];
+ if (c == ' ') break;
+ if (c == NDDE) c = (TCHAR)DDE;
+ if (_USE_LFN && (nt & NS_BODY) && IsUpper(c)) c += 0x20;
+#if _LFN_UNICODE
+ if (IsDBCS1(c) && i < 7 && IsDBCS2(dir[i+1]))
+ c = (c << 8) | dir[++i];
+ c = ff_convert(c, 1);
+ if (!c) c = '?';
+#endif
+ *p++ = c;
+ }
+ if (dir[8] != ' ') { /* Copy name extension */
+ *p++ = '.';
+ for (i = 8; i < 11; i++) {
+ c = dir[i];
+ if (c == ' ') break;
+ if (_USE_LFN && (nt & NS_EXT) && IsUpper(c)) c += 0x20;
+#if _LFN_UNICODE
+ if (IsDBCS1(c) && i < 10 && IsDBCS2(dir[i+1]))
+ c = (c << 8) | dir[++i];
+ c = ff_convert(c, 1);
+ if (!c) c = '?';
+#endif
+ *p++ = c;
+ }
+ }
+ fno->fattrib = dir[DIR_Attr]; /* Attribute */
+ fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */
+ fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */
+ fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */
+ }
+ *p = 0; /* Terminate SFN str by a \0 */
+
+#if _USE_LFN
+ if (fno->lfname && fno->lfsize) {
+ TCHAR *tp = fno->lfname;
+ WCHAR w, *lfn;
+
+ i = 0;
+ if (dj->sect && dj->lfn_idx != 0xFFFF) {/* Get LFN if available */
+ lfn = dj->lfn;
+ while ((w = *lfn++) != 0) { /* Get an LFN char */
+#if !_LFN_UNICODE
+ w = ff_convert(w, 0); /* Unicode -> OEM conversion */
+ if (!w) { i = 0; break; } /* Could not convert, no LFN */
+ if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */
+ tp[i++] = (TCHAR)(w >> 8);
+#endif
+ if (i >= fno->lfsize - 1) { i = 0; break; } /* Buffer overflow, no LFN */
+ tp[i++] = (TCHAR)w;
+ }
+ }
+ tp[i] = 0; /* Terminate the LFN str by a \0 */
+ }
+#endif
+}
+#endif /* _FS_MINIMIZE <= 1 */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */
+ FATFS_DIR *dj, /* Directory object to return last directory and found object */
+ const TCHAR *path /* Full-path string to find a file or directory */
+)
+{
+ FRESULT res;
+ BYTE *dir, ns;
+
+
+#if _FS_RPATH
+ if (*path == '/' || *path == '\\') { /* There is a heading separator */
+ path++; dj->sclust = 0; /* Strip it and start from the root dir */
+ } else { /* No heading separator */
+ dj->sclust = dj->fs->cdir; /* Start from the current dir */
+ }
+#else
+ if (*path == '/' || *path == '\\') /* Strip heading separator if exist */
+ path++;
+ dj->sclust = 0; /* Start from the root dir */
+#endif
+
+ if ((UINT)*path < ' ') { /* Nul path means the start directory itself */
+ res = dir_sdi(dj, 0);
+ dj->dir = 0;
+ } else { /* Follow path */
+ for (;;) {
+ res = create_name(dj, &path); /* Get a segment */
+ if (res != FR_OK) break;
+ res = dir_find(dj); /* Find it */
+ ns = *(dj->fn+NS);
+ if (res != FR_OK) { /* Failed to find the object */
+ if (res != FR_NO_FILE) break; /* Abort if any hard error occurred */
+ /* Object not found */
+ if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exit */
+ dj->sclust = 0; dj->dir = 0; /* It is the root dir */
+ res = FR_OK;
+ if (!(ns & NS_LAST)) continue;
+ } else { /* Could not find the object */
+ if (!(ns & NS_LAST)) res = FR_NO_PATH;
+ }
+ break;
+ }
+ if (ns & NS_LAST) break; /* Last segment match. Function completed. */
+ dir = dj->dir; /* There is next segment. Follow the sub directory */
+ if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
+ res = FR_NO_PATH; break;
+ }
+ dj->sclust = ld_clust(dj->fs, dir);
+ }
+ }
+
+ return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Load a sector and check if it is an FAT Volume Boot Record */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs ( /* 0:FAT-VBR, 1:Any BR but not FAT, 2:Not a BR, 3:Disk error */
+ FATFS *fs, /* File system object */
+ DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+ if (disk_read(fs->drv, fs->win, sect, 1) != RES_OK) /* Load boot record */
+ return 3;
+ if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check record signature (always placed at offset 510 even if the sector size is >512) */
+ return 2;
+
+ if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */
+ return 0;
+ if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146)
+ return 0;
+
+ return 1;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file system object is valid or not */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT chk_mounted ( /* FR_OK(0): successful, !=0: any error occurred */
+ const TCHAR **path, /* Pointer to pointer to the path name (drive number) */
+ FATFS **rfs, /* Pointer to pointer to the found file system object */
+ BYTE wmode /* !=0: Check write protection for write access */
+)
+{
+ BYTE fmt, b, pi, *tbl;
+ UINT vol;
+ DSTATUS stat;
+ DWORD bsect, fasize, tsect, sysect, nclst, szbfat;
+ WORD nrsv;
+ const TCHAR *p = *path;
+ FATFS *fs;
+
+
+ /* Get logical drive number from the path name */
+ vol = p[0] - '0'; /* Is there a drive number? */
+ if (vol <= 9 && p[1] == ':') { /* Found a drive number, get and strip it */
+ p += 2; *path = p; /* Return pointer to the path name */
+ } else { /* No drive number is given */
+#if _FS_RPATH
+ vol = CurrVol; /* Use current drive */
+#else
+ vol = 0; /* Use drive 0 */
+#endif
+ }
+
+ /* Check if the file system object is valid or not */
+ *rfs = 0;
+ if (vol >= _VOLUMES) /* Is the drive number valid? */
+ return FR_INVALID_DRIVE;
+ fs = FatFs[vol]; /* Get corresponding file system object */
+ if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */
+
+ ENTER_FF(fs); /* Lock file system */
+
+ *rfs = fs; /* Return pointer to the corresponding file system object */
+ if (fs->fs_type) { /* If the volume has been mounted */
+ stat = disk_status(fs->drv);
+ if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized (has not been changed), */
+ if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check write protection if needed */
+ return FR_WRITE_PROTECTED;
+ return FR_OK; /* The file system object is valid */
+ }
+ }
+
+ /* The file system object is not valid. */
+ /* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */
+
+ fs->fs_type = 0; /* Clear the file system object */
+ fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */
+ stat = disk_initialize(fs->drv); /* Initialize the physical drive */
+ if (stat & STA_NOINIT) /* Check if the initialization succeeded */
+ return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */
+ if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check disk write protection if needed */
+ return FR_WRITE_PROTECTED;
+#if _MAX_SS != 512 /* Get disk sector size (variable sector size cfg only) */
+ if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK)
+ return FR_DISK_ERR;
+#endif
+ /* Search FAT partition on the drive. Supports only generic partitions, FDISK and SFD. */
+ fmt = check_fs(fs, bsect = 0); /* Load sector 0 and check if it is an FAT-VBR (in SFD) */
+ if (LD2PT(vol) && !fmt) fmt = 1; /* Force non-SFD if the volume is forced partition */
+ if (fmt == 1) { /* Not an FAT-VBR, the physical drive can be partitioned */
+ /* Check the partition listed in the partition table */
+ pi = LD2PT(vol);
+ if (pi) pi--;
+ tbl = &fs->win[MBR_Table + pi * SZ_PTE];/* Partition table */
+ if (tbl[4]) { /* Is the partition existing? */
+ bsect = LD_DWORD(&tbl[8]); /* Partition offset in LBA */
+ fmt = check_fs(fs, bsect); /* Check the partition */
+ }
+ }
+ if (fmt == 3) return FR_DISK_ERR;
+ if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */
+
+ /* An FAT volume is found. Following code initializes the file system object */
+
+ if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* (BPB_BytsPerSec must be equal to the physical sector size) */
+ return FR_NO_FILESYSTEM;
+
+ fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */
+ if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32);
+ fs->fsize = fasize;
+
+ fs->n_fats = b = fs->win[BPB_NumFATs]; /* Number of FAT copies */
+ if (b != 1 && b != 2) return FR_NO_FILESYSTEM; /* (Must be 1 or 2) */
+ fasize *= b; /* Number of sectors for FAT area */
+
+ fs->csize = b = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */
+ if (!b || (b & (b - 1))) return FR_NO_FILESYSTEM; /* (Must be power of 2) */
+
+ fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */
+ if (fs->n_rootdir % (SS(fs) / SZ_DIR)) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be sector aligned) */
+
+ tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */
+ if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32);
+
+ nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */
+ if (!nrsv) return FR_NO_FILESYSTEM; /* (BPB_RsvdSecCnt must not be 0) */
+
+ /* Determine the FAT sub type */
+ sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIR); /* RSV+FAT+DIR */
+ if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */
+ nclst = (tsect - sysect) / fs->csize; /* Number of clusters */
+ if (!nclst) return FR_NO_FILESYSTEM; /* (Invalid volume size) */
+ fmt = FS_FAT12;
+ if (nclst >= MIN_FAT16) fmt = FS_FAT16;
+ if (nclst >= MIN_FAT32) fmt = FS_FAT32;
+
+ /* Boundaries and Limits */
+ fs->n_fatent = nclst + 2; /* Number of FAT entries */
+ fs->database = bsect + sysect; /* Data start sector */
+ fs->fatbase = bsect + nrsv; /* FAT start sector */
+ if (fmt == FS_FAT32) {
+ if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */
+ fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */
+ szbfat = fs->n_fatent * 4; /* (Required FAT size) */
+ } else {
+ if (!fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */
+ fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */
+ szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */
+ fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1);
+ }
+ if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (BPB_FATSz must not be less than required) */
+ return FR_NO_FILESYSTEM;
+
+#if !_FS_READONLY
+ /* Initialize cluster allocation information */
+ fs->free_clust = 0xFFFFFFFF;
+ fs->last_clust = 0;
+
+ /* Get fsinfo if available */
+ if (fmt == FS_FAT32) {
+ fs->fsi_flag = 0;
+ fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo);
+ if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK &&
+ LD_WORD(fs->win+BS_55AA) == 0xAA55 &&
+ LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 &&
+ LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) {
+ fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free);
+ fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count);
+ }
+ }
+#endif
+ fs->fs_type = fmt; /* FAT sub-type */
+ fs->id = ++Fsid; /* File system mount ID */
+ fs->winsect = 0; /* Invalidate sector cache */
+ fs->wflag = 0;
+#if _FS_RPATH
+ fs->cdir = 0; /* Current directory (root dir) */
+#endif
+#if _FS_LOCK /* Clear file lock semaphores */
+ clear_lock(fs);
+#endif
+
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check if the file/dir object is valid or not */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */
+ void* obj /* Pointer to the object FIL/DIR to check validity */
+)
+{
+ FIL *fil;
+
+
+ fil = (FIL*)obj; /* Assuming offset of fs and id in the FIL/DIR is identical */
+ if (!fil->fs || !fil->fs->fs_type || fil->fs->id != fil->id)
+ return FR_INVALID_OBJECT;
+
+ ENTER_FF(fil->fs); /* Lock file system */
+
+ if (disk_status(fil->fs->drv) & STA_NOINIT)
+ return FR_NOT_READY;
+
+ return FR_OK;
+}
+
+
+
+
+/*--------------------------------------------------------------------------
+
+ Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Logical Drive */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mount (
+ BYTE vol, /* Logical drive number to be mounted/unmounted */
+ FATFS *fs /* Pointer to new file system object (NULL for unmount)*/
+)
+{
+ FATFS *rfs;
+
+
+ if (vol >= _VOLUMES) /* Check if the drive number is valid */
+ return FR_INVALID_DRIVE;
+ rfs = FatFs[vol]; /* Get current fs object */
+
+ if (rfs) {
+#if _FS_LOCK
+ clear_lock(rfs);
+#endif
+#if _FS_REENTRANT /* Discard sync object of the current volume */
+ if (!ff_del_syncobj(rfs->sobj)) return FR_INT_ERR;
+#endif
+ rfs->fs_type = 0; /* Clear old fs object */
+ }
+
+ if (fs) {
+ fs->fs_type = 0; /* Clear new fs object */
+#if _FS_REENTRANT /* Create sync object for the new volume */
+ if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR;
+#endif
+ }
+ FatFs[vol] = fs; /* Register new fs object */
+
+ return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_open (
+ FIL *fp, /* Pointer to the blank file object */
+ const TCHAR *path, /* Pointer to the file name */
+ BYTE mode /* Access mode and file open mode flags */
+)
+{
+ FRESULT res;
+ FATFS_DIR dj;
+ BYTE *dir;
+ DEF_NAMEBUF;
+
+
+ if (!fp) return FR_INVALID_OBJECT;
+ fp->fs = 0; /* Clear file object */
+
+#if !_FS_READONLY
+ mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW;
+ res = chk_mounted(&path, &dj.fs, (BYTE)(mode & ~FA_READ));
+#else
+ mode &= FA_READ;
+ res = chk_mounted(&path, &dj.fs, 0);
+#endif
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ dir = dj.dir;
+#if !_FS_READONLY /* R/W configuration */
+ if (res == FR_OK) {
+ if (!dir) /* Current dir itself */
+ res = FR_INVALID_NAME;
+#if _FS_LOCK
+ else
+ res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+#endif
+ }
+ /* Create or Open a file */
+ if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) {
+ DWORD dw, cl;
+
+ if (res != FR_OK) { /* No file, create new */
+ if (res == FR_NO_FILE) /* There is no file to open, create a new entry */
+#if _FS_LOCK
+ res = enq_lock() ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES;
+#else
+ res = dir_register(&dj);
+#endif
+ mode |= FA_CREATE_ALWAYS; /* File is created */
+ dir = dj.dir; /* New entry */
+ }
+ else { /* Any object is already existing */
+ if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */
+ res = FR_DENIED;
+ } else {
+ if (mode & FA_CREATE_NEW) /* Cannot create as new file */
+ res = FR_EXIST;
+ }
+ }
+ if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */
+ dw = get_fattime(); /* Created time */
+ ST_DWORD(dir+DIR_CrtTime, dw);
+ dir[DIR_Attr] = 0; /* Reset attribute */
+ ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */
+ cl = ld_clust(dj.fs, dir); /* Get start cluster */
+ st_clust(dir, 0); /* cluster = 0 */
+ dj.fs->wflag = 1;
+ if (cl) { /* Remove the cluster chain if exist */
+ dw = dj.fs->winsect;
+ res = remove_chain(dj.fs, cl);
+ if (res == FR_OK) {
+ dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */
+ res = move_window(dj.fs, dw);
+ }
+ }
+ }
+ }
+ else { /* Open an existing file */
+ if (res == FR_OK) { /* Follow succeeded */
+ if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */
+ res = FR_NO_FILE;
+ } else {
+ if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */
+ res = FR_DENIED;
+ }
+ }
+ }
+ if (res == FR_OK) {
+ if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */
+ mode |= FA__WRITTEN;
+ fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */
+ fp->dir_ptr = dir;
+#if _FS_LOCK
+ fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0);
+ if (!fp->lockid) res = FR_INT_ERR;
+#endif
+ }
+
+#else /* R/O configuration */
+ if (res == FR_OK) { /* Follow succeeded */
+ dir = dj.dir;
+ if (!dir) { /* Current dir itself */
+ res = FR_INVALID_NAME;
+ } else {
+ if (dir[DIR_Attr] & AM_DIR) /* It is a directory */
+ res = FR_NO_FILE;
+ }
+ }
+#endif
+ FREE_BUF();
+
+ if (res == FR_OK) {
+ fp->flag = mode; /* File access mode */
+ fp->sclust = ld_clust(dj.fs, dir); /* File start cluster */
+ fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */
+ fp->fptr = 0; /* File pointer */
+ fp->dsect = 0;
+#if _USE_FASTSEEK
+ fp->cltbl = 0; /* Normal seek mode */
+#endif
+ fp->fs = dj.fs; fp->id = dj.fs->id; /* Validate file object */
+ }
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_read (
+ FIL *fp, /* Pointer to the file object */
+ void *buff, /* Pointer to data buffer */
+ UINT btr, /* Number of bytes to read */
+ UINT *br /* Pointer to number of bytes read */
+)
+{
+ FRESULT res;
+ DWORD clst, sect, remain;
+ UINT rcnt, cc;
+ BYTE csect, *rbuff = (BYTE *)buff;
+
+
+ *br = 0; /* Clear read byte counter */
+
+ res = validate(fp); /* Check validity */
+ if (res != FR_OK) LEAVE_FF(fp->fs, res);
+ if (fp->flag & FA__ERROR) /* Aborted file? */
+ LEAVE_FF(fp->fs, FR_INT_ERR);
+ if (!(fp->flag & FA_READ)) /* Check access mode */
+ LEAVE_FF(fp->fs, FR_DENIED);
+ remain = fp->fsize - fp->fptr;
+ if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */
+
+ for ( ; btr; /* Repeat until all data read */
+ rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) {
+ if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
+ csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
+ if (!csect) { /* On the cluster boundary? */
+ if (fp->fptr == 0) { /* On the top of the file? */
+ clst = fp->sclust; /* Follow from the origin */
+ } else { /* Middle or end of the file */
+#if _USE_FASTSEEK
+ if (fp->cltbl)
+ clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */
+ else
+#endif
+ clst = get_fat(fp->fs, fp->clust); /* Follow cluster chain on the FAT */
+ }
+ if (clst < 2) ABORT(fp->fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ fp->clust = clst; /* Update current cluster */
+ }
+ sect = clust2sect(fp->fs, fp->clust); /* Get current sector */
+ if (!sect) ABORT(fp->fs, FR_INT_ERR);
+ sect += csect;
+ cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */
+ if (cc) { /* Read maximum contiguous sectors directly */
+ if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */
+ cc = fp->fs->csize - csect;
+ if (disk_read(fp->fs->drv, rbuff, sect, (BYTE)cc) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */
+#if _FS_TINY
+ if (fp->fs->wflag && fp->fs->winsect - sect < cc)
+ mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs));
+#else
+ if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc)
+ mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs));
+#endif
+#endif
+ rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */
+ continue;
+ }
+#if !_FS_TINY
+ if (fp->dsect != sect) { /* Load data sector if not in cache */
+#if !_FS_READONLY
+ if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ if (disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK) /* Fill sector cache */
+ ABORT(fp->fs, FR_DISK_ERR);
+ }
+#endif
+ fp->dsect = sect;
+ }
+ rcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */
+ if (rcnt > btr) rcnt = btr;
+#if _FS_TINY
+ if (move_window(fp->fs, fp->dsect)) /* Move sector window */
+ ABORT(fp->fs, FR_DISK_ERR);
+ mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */
+#else
+ mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */
+#endif
+ }
+
+ LEAVE_FF(fp->fs, FR_OK);
+}
+
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Write File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_write (
+ FIL *fp, /* Pointer to the file object */
+ const void *buff, /* Pointer to the data to be written */
+ UINT btw, /* Number of bytes to write */
+ UINT *bw /* Pointer to number of bytes written */
+)
+{
+ FRESULT res;
+ DWORD clst, sect;
+ UINT wcnt, cc;
+ const BYTE *wbuff = (const BYTE *)buff;
+ BYTE csect;
+ bool need_sync = false;
+
+ *bw = 0; /* Clear write byte counter */
+
+ res = validate(fp); /* Check validity */
+ if (res != FR_OK) LEAVE_FF(fp->fs, res);
+ if (fp->flag & FA__ERROR) /* Aborted file? */
+ LEAVE_FF(fp->fs, FR_INT_ERR);
+ if (!(fp->flag & FA_WRITE)) /* Check access mode */
+ LEAVE_FF(fp->fs, FR_DENIED);
+ if ((DWORD)(fp->fsize + btw) < fp->fsize) btw = 0; /* File size cannot reach 4GB */
+
+ for ( ; btw; /* Repeat until all data written */
+ wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) {
+ if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
+ csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
+ if (!csect) { /* On the cluster boundary? */
+ if (fp->fptr == 0) { /* On the top of the file? */
+ clst = fp->sclust; /* Follow from the origin */
+ if (clst == 0) /* When no cluster is allocated, */
+ fp->sclust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */
+ } else { /* Middle or end of the file */
+#if _USE_FASTSEEK
+ if (fp->cltbl)
+ clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */
+ else
+#endif
+ clst = create_chain(fp->fs, fp->clust); /* Follow or stretch cluster chain on the FAT */
+ }
+ if (clst == 0) break; /* Could not allocate a new cluster (disk full) */
+ if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ fp->clust = clst; /* Update current cluster */
+
+#ifdef FLUSH_ON_NEW_CLUSTER
+ // We do not need to flush for the first cluster
+ if (fp->fptr != 0) {
+ need_sync = true;
+ }
+#endif
+ }
+#if _FS_TINY
+ if (fp->fs->winsect == fp->dsect && move_window(fp->fs, 0)) /* Write-back sector cache */
+ ABORT(fp->fs, FR_DISK_ERR);
+#else
+ if (fp->flag & FA__DIRTY) { /* Write-back sector cache */
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ sect = clust2sect(fp->fs, fp->clust); /* Get current sector */
+ if (!sect) ABORT(fp->fs, FR_INT_ERR);
+ sect += csect;
+ cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */
+ if (cc) { /* Write maximum contiguous sectors directly */
+ if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */
+ cc = fp->fs->csize - csect;
+ if (disk_write(fp->fs->drv, wbuff, sect, (BYTE)cc) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+#if _FS_TINY
+ if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+ mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs));
+ fp->fs->wflag = 0;
+ }
+#else
+ if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */
+ mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs));
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */
+#ifdef FLUSH_ON_NEW_SECTOR
+ need_sync = true;
+#endif
+ continue;
+ }
+#if _FS_TINY
+ if (fp->fptr >= fp->fsize) { /* Avoid silly cache filling at growing edge */
+ if (move_window(fp->fs, 0)) ABORT(fp->fs, FR_DISK_ERR);
+ fp->fs->winsect = sect;
+ }
+#else
+ if (fp->dsect != sect) { /* Fill sector cache with file data */
+ if (fp->fptr < fp->fsize &&
+ disk_read(fp->fs->drv, fp->buf, sect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ }
+#endif
+ fp->dsect = sect;
+ }
+ wcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */
+ if (wcnt > btw) wcnt = btw;
+#if _FS_TINY
+ if (move_window(fp->fs, fp->dsect)) /* Move sector window */
+ ABORT(fp->fs, FR_DISK_ERR);
+ mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */
+ fp->fs->wflag = 1;
+#else
+ mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */
+ fp->flag |= FA__DIRTY;
+#endif
+ }
+
+ if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */
+ fp->flag |= FA__WRITTEN; /* Set file change flag */
+
+ if (need_sync) {
+ f_sync (fp);
+ }
+
+ LEAVE_FF(fp->fs, FR_OK);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Synchronize the File Object */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_sync (
+ FIL *fp /* Pointer to the file object */
+)
+{
+ FRESULT res;
+ DWORD tim;
+ BYTE *dir;
+
+
+ res = validate(fp); /* Check validity of the object */
+ if (res == FR_OK) {
+ if (fp->flag & FA__WRITTEN) { /* Has the file been written? */
+#if !_FS_TINY /* Write-back dirty buffer */
+ if (fp->flag & FA__DIRTY) {
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ LEAVE_FF(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ /* Update the directory entry */
+ res = move_window(fp->fs, fp->dir_sect);
+ if (res == FR_OK) {
+ dir = fp->dir_ptr;
+ dir[DIR_Attr] |= AM_ARC; /* Set archive bit */
+ ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */
+ st_clust(dir, fp->sclust); /* Update start cluster */
+ tim = get_fattime(); /* Update updated time */
+ ST_DWORD(dir+DIR_WrtTime, tim);
+ ST_WORD(dir+DIR_LstAccDate, 0);
+ fp->flag &= ~FA__WRITTEN;
+ fp->fs->wflag = 1;
+ res = sync(fp->fs);
+ }
+ }
+ }
+
+ LEAVE_FF(fp->fs, res);
+}
+
+#endif /* !_FS_READONLY */
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Close File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_close (
+ FIL *fp /* Pointer to the file object to be closed */
+)
+{
+ FRESULT res;
+
+
+#if _FS_READONLY
+ res = validate(fp);
+ {
+#if _FS_REENTRANT
+ FATFS *fs = fp->fs;
+#endif
+ if (res == FR_OK) fp->fs = 0; /* Discard file object */
+ LEAVE_FF(fs, res);
+ }
+#else
+ res = f_sync(fp); /* Flush cached data */
+#if _FS_LOCK
+ if (res == FR_OK) { /* Decrement open counter */
+#if _FS_REENTRANT
+ FATFS *fs = fp->fs;;
+ res = validate(fp);
+ if (res == FR_OK) {
+ res = dec_lock(fp->lockid);
+ unlock_fs(fs, FR_OK);
+ }
+#else
+ res = dec_lock(fp->lockid);
+#endif
+ }
+#endif
+ if (res == FR_OK) fp->fs = 0; /* Discard file object */
+ return res;
+#endif
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Current Drive/Directory Handlings */
+/*-----------------------------------------------------------------------*/
+
+#if _FS_RPATH >= 1
+
+FRESULT f_chdrive (
+ BYTE drv /* Drive number */
+)
+{
+ if (drv >= _VOLUMES) return FR_INVALID_DRIVE;
+
+ CurrVol = drv;
+
+ return FR_OK;
+}
+
+
+
+FRESULT f_chdir (
+ const TCHAR *path /* Pointer to the directory path */
+)
+{
+ FRESULT res;
+ DIR dj;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 0);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the path */
+ FREE_BUF();
+ if (res == FR_OK) { /* Follow completed */
+ if (!dj.dir) {
+ dj.fs->cdir = dj.sclust; /* Start directory itself */
+ } else {
+ if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */
+ dj.fs->cdir = ld_clust(dj.fs, dj.dir);
+ else
+ res = FR_NO_PATH; /* Reached but a file */
+ }
+ }
+ if (res == FR_NO_FILE) res = FR_NO_PATH;
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+#if _FS_RPATH >= 2
+FRESULT f_getcwd (
+ TCHAR *path, /* Pointer to the directory path */
+ UINT sz_path /* Size of path */
+)
+{
+ FRESULT res;
+ DIR dj;
+ UINT i, n;
+ DWORD ccl;
+ TCHAR *tp;
+ FILINFO fno;
+ DEF_NAMEBUF;
+
+
+ *path = 0;
+ res = chk_mounted((const TCHAR**)&path, &dj.fs, 0); /* Get current volume */
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ i = sz_path; /* Bottom of buffer (dir stack base) */
+ dj.sclust = dj.fs->cdir; /* Start to follow upper dir from current dir */
+ while ((ccl = dj.sclust) != 0) { /* Repeat while current dir is a sub-dir */
+ res = dir_sdi(&dj, 1); /* Get parent dir */
+ if (res != FR_OK) break;
+ res = dir_read(&dj);
+ if (res != FR_OK) break;
+ dj.sclust = ld_clust(dj.fs, dj.dir); /* Goto parent dir */
+ res = dir_sdi(&dj, 0);
+ if (res != FR_OK) break;
+ do { /* Find the entry links to the child dir */
+ res = dir_read(&dj);
+ if (res != FR_OK) break;
+ if (ccl == ld_clust(dj.fs, dj.dir)) break; /* Found the entry */
+ res = dir_next(&dj, 0);
+ } while (res == FR_OK);
+ if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
+ if (res != FR_OK) break;
+#if _USE_LFN
+ fno.lfname = path;
+ fno.lfsize = i;
+#endif
+ get_fileinfo(&dj, &fno); /* Get the dir name and push it to the buffer */
+ tp = fno.fname;
+ if (_USE_LFN && *path) tp = path;
+ for (n = 0; tp[n]; n++) ;
+ if (i < n + 3) {
+ res = FR_NOT_ENOUGH_CORE; break;
+ }
+ while (n) path[--i] = tp[--n];
+ path[--i] = '/';
+ }
+ tp = path;
+ if (res == FR_OK) {
+ *tp++ = '0' + CurrVol; /* Put drive number */
+ *tp++ = ':';
+ if (i == sz_path) { /* Root-dir */
+ *tp++ = '/';
+ } else { /* Sub-dir */
+ do /* Add stacked path str */
+ *tp++ = path[i++];
+ while (i < sz_path);
+ }
+ }
+ *tp = 0;
+ FREE_BUF();
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+#endif /* _FS_RPATH >= 2 */
+#endif /* _FS_RPATH >= 1 */
+
+
+
+#if _FS_MINIMIZE <= 2
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_lseek (
+ FIL *fp, /* Pointer to the file object */
+ DWORD ofs /* File pointer from top of file */
+)
+{
+ FRESULT res;
+
+
+ res = validate(fp); /* Check validity of the object */
+ if (res != FR_OK) LEAVE_FF(fp->fs, res);
+ if (fp->flag & FA__ERROR) /* Check abort flag */
+ LEAVE_FF(fp->fs, FR_INT_ERR);
+
+#if _USE_FASTSEEK
+ if (fp->cltbl) { /* Fast seek */
+ DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl;
+
+ if (ofs == CREATE_LINKMAP) { /* Create CLMT */
+ tbl = fp->cltbl;
+ tlen = *tbl++; ulen = 2; /* Given table size and required table size */
+ cl = fp->sclust; /* Top of the chain */
+ if (cl) {
+ do {
+ /* Get a fragment */
+ tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */
+ do {
+ pcl = cl; ncl++;
+ cl = get_fat(fp->fs, cl);
+ if (cl <= 1) ABORT(fp->fs, FR_INT_ERR);
+ if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ } while (cl == pcl + 1);
+ if (ulen <= tlen) { /* Store the length and top of the fragment */
+ *tbl++ = ncl; *tbl++ = tcl;
+ }
+ } while (cl < fp->fs->n_fatent); /* Repeat until end of chain */
+ }
+ *fp->cltbl = ulen; /* Number of items used */
+ if (ulen <= tlen)
+ *tbl = 0; /* Terminate table */
+ else
+ res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */
+
+ } else { /* Fast seek */
+ if (ofs > fp->fsize) /* Clip offset at the file size */
+ ofs = fp->fsize;
+ fp->fptr = ofs; /* Set file pointer */
+ if (ofs) {
+ fp->clust = clmt_clust(fp, ofs - 1);
+ dsc = clust2sect(fp->fs, fp->clust);
+ if (!dsc) ABORT(fp->fs, FR_INT_ERR);
+ dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1);
+ if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) { /* Refill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+ if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ if (disk_read(fp->fs->drv, fp->buf, dsc, 1) != RES_OK) /* Load current sector */
+ ABORT(fp->fs, FR_DISK_ERR);
+#endif
+ fp->dsect = dsc;
+ }
+ }
+ }
+ } else
+#endif
+
+ /* Normal Seek */
+ {
+ DWORD clst, bcs, nsect, ifptr;
+
+ if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */
+#if !_FS_READONLY
+ && !(fp->flag & FA_WRITE)
+#endif
+ ) ofs = fp->fsize;
+
+ ifptr = fp->fptr;
+ fp->fptr = nsect = 0;
+ if (ofs) {
+ bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */
+ if (ifptr > 0 &&
+ (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */
+ fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */
+ ofs -= fp->fptr;
+ clst = fp->clust;
+ } else { /* When seek to back cluster, */
+ clst = fp->sclust; /* start from the first cluster */
+#if !_FS_READONLY
+ if (clst == 0) { /* If no cluster chain, create a new chain */
+ clst = create_chain(fp->fs, 0);
+ if (clst == 1) ABORT(fp->fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ fp->sclust = clst;
+ }
+#endif
+ fp->clust = clst;
+ }
+ if (clst != 0) {
+ while (ofs > bcs) { /* Cluster following loop */
+#if !_FS_READONLY
+ if (fp->flag & FA_WRITE) { /* Check if in write mode or not */
+ clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */
+ if (clst == 0) { /* When disk gets full, clip file size */
+ ofs = bcs; break;
+ }
+ } else
+#endif
+ clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR);
+ fp->clust = clst;
+ fp->fptr += bcs;
+ ofs -= bcs;
+ }
+ fp->fptr += ofs;
+ if (ofs % SS(fp->fs)) {
+ nsect = clust2sect(fp->fs, clst); /* Current sector */
+ if (!nsect) ABORT(fp->fs, FR_INT_ERR);
+ nsect += ofs / SS(fp->fs);
+ }
+ }
+ }
+ if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { /* Fill sector cache if needed */
+#if !_FS_TINY
+#if !_FS_READONLY
+ if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */
+ if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1) != RES_OK)
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->flag &= ~FA__DIRTY;
+ }
+#endif
+ if (disk_read(fp->fs->drv, fp->buf, nsect, 1) != RES_OK) /* Fill sector cache */
+ ABORT(fp->fs, FR_DISK_ERR);
+#endif
+ fp->dsect = nsect;
+ }
+#if !_FS_READONLY
+ if (fp->fptr > fp->fsize) { /* Set file change flag if the file size is extended */
+ fp->fsize = fp->fptr;
+ fp->flag |= FA__WRITTEN;
+ }
+#endif
+ }
+
+ LEAVE_FF(fp->fs, res);
+}
+
+
+
+#if _FS_MINIMIZE <= 1
+/*-----------------------------------------------------------------------*/
+/* Create a Directory Object */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_opendir (
+ FATFS_DIR *dj, /* Pointer to directory object to create */
+ const TCHAR *path /* Pointer to the directory path */
+)
+{
+ FRESULT res;
+ FATFS *fs;
+ DEF_NAMEBUF;
+
+
+ if (!dj) return FR_INVALID_OBJECT;
+
+ res = chk_mounted(&path, &dj->fs, 0);
+ fs = dj->fs;
+ if (res == FR_OK) {
+ INIT_BUF(*dj);
+ res = follow_path(dj, path); /* Follow the path to the directory */
+ FREE_BUF();
+ if (res == FR_OK) { /* Follow completed */
+ if (dj->dir) { /* It is not the root dir */
+ if (dj->dir[DIR_Attr] & AM_DIR) { /* The object is a directory */
+ dj->sclust = ld_clust(fs, dj->dir);
+ } else { /* The object is not a directory */
+ res = FR_NO_PATH;
+ }
+ }
+ if (res == FR_OK) {
+ dj->id = fs->id;
+ res = dir_sdi(dj, 0); /* Rewind dir */
+ }
+ }
+ if (res == FR_NO_FILE) res = FR_NO_PATH;
+ if (res != FR_OK) dj->fs = 0; /* Invalidate the dir object if function faild */
+ } else {
+ dj->fs = 0;
+ }
+
+ LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entry in Sequence */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_readdir (
+ FATFS_DIR *dj, /* Pointer to the open directory object */
+ FILINFO *fno /* Pointer to file information to return */
+)
+{
+ FRESULT res;
+ DEF_NAMEBUF;
+
+
+ res = validate(dj); /* Check validity of the object */
+ if (res == FR_OK) {
+ if (!fno) {
+ res = dir_sdi(dj, 0); /* Rewind the directory object */
+ } else {
+ INIT_BUF(*dj);
+ res = dir_read(dj); /* Read an directory item */
+ if (res == FR_NO_FILE) { /* Reached end of dir */
+ dj->sect = 0;
+ res = FR_OK;
+ }
+ if (res == FR_OK) { /* A valid entry is found */
+ get_fileinfo(dj, fno); /* Get the object information */
+ res = dir_next(dj, 0); /* Increment index for next */
+ if (res == FR_NO_FILE) {
+ dj->sect = 0;
+ res = FR_OK;
+ }
+ }
+ FREE_BUF();
+ }
+ }
+
+ LEAVE_FF(dj->fs, res);
+}
+
+
+
+#if _FS_MINIMIZE == 0
+/*-----------------------------------------------------------------------*/
+/* Get File Status */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_stat (
+ const TCHAR *path, /* Pointer to the file path */
+ FILINFO *fno /* Pointer to file information to return */
+)
+{
+ FRESULT res;
+ FATFS_DIR dj;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 0);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ if (res == FR_OK) { /* Follow completed */
+ if (dj.dir) /* Found an object */
+ get_fileinfo(&dj, fno);
+ else /* It is root dir */
+ res = FR_INVALID_NAME;
+ }
+ FREE_BUF();
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+#if !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Get Number of Free Clusters */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_getfree (
+ const TCHAR *path, /* Pointer to the logical drive number (root dir) */
+ DWORD *nclst, /* Pointer to the variable to return number of free clusters */
+ FATFS **fatfs /* Pointer to pointer to corresponding file system object to return */
+)
+{
+ FRESULT res;
+ FATFS *fs;
+ DWORD n, clst, sect, stat;
+ UINT i;
+ BYTE fat, *p;
+
+
+ /* Get drive number */
+ res = chk_mounted(&path, fatfs, 0);
+ fs = *fatfs;
+ if (res == FR_OK) {
+ /* If free_clust is valid, return it without full cluster scan */
+ if (fs->free_clust <= fs->n_fatent - 2) {
+ *nclst = fs->free_clust;
+ } else {
+ /* Get number of free clusters */
+ fat = fs->fs_type;
+ n = 0;
+ if (fat == FS_FAT12) {
+ clst = 2;
+ do {
+ stat = get_fat(fs, clst);
+ if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; }
+ if (stat == 1) { res = FR_INT_ERR; break; }
+ if (stat == 0) n++;
+ } while (++clst < fs->n_fatent);
+ } else {
+ clst = fs->n_fatent;
+ sect = fs->fatbase;
+ i = 0; p = 0;
+ do {
+ if (!i) {
+ res = move_window(fs, sect++);
+ if (res != FR_OK) break;
+ p = fs->win;
+ i = SS(fs);
+ }
+ if (fat == FS_FAT16) {
+ if (LD_WORD(p) == 0) n++;
+ p += 2; i -= 2;
+ } else {
+ if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++;
+ p += 4; i -= 4;
+ }
+ } while (--clst);
+ }
+ fs->free_clust = n;
+ if (fat == FS_FAT32) fs->fsi_flag = 1;
+ *nclst = n;
+ }
+ }
+ LEAVE_FF(fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Truncate File */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_truncate (
+ FIL *fp /* Pointer to the file object */
+)
+{
+ FRESULT res;
+ DWORD ncl;
+
+
+ if (!fp) return FR_INVALID_OBJECT;
+
+ res = validate(fp); /* Check validity of the object */
+ if (res == FR_OK) {
+ if (fp->flag & FA__ERROR) { /* Check abort flag */
+ res = FR_INT_ERR;
+ } else {
+ if (!(fp->flag & FA_WRITE)) /* Check access mode */
+ res = FR_DENIED;
+ }
+ }
+ if (res == FR_OK) {
+ if (fp->fsize > fp->fptr) {
+ fp->fsize = fp->fptr; /* Set file size to current R/W point */
+ fp->flag |= FA__WRITTEN;
+ if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */
+ res = remove_chain(fp->fs, fp->sclust);
+ fp->sclust = 0;
+ } else { /* When truncate a part of the file, remove remaining clusters */
+ ncl = get_fat(fp->fs, fp->clust);
+ res = FR_OK;
+ if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR;
+ if (ncl == 1) res = FR_INT_ERR;
+ if (res == FR_OK && ncl < fp->fs->n_fatent) {
+ res = put_fat(fp->fs, fp->clust, 0x0FFFFFFF);
+ if (res == FR_OK) res = remove_chain(fp->fs, ncl);
+ }
+ }
+ }
+ if (res != FR_OK) fp->flag |= FA__ERROR;
+ }
+
+ LEAVE_FF(fp->fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Delete a File or Directory */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_unlink (
+ const TCHAR *path /* Pointer to the file or directory path */
+)
+{
+ FRESULT res;
+ FATFS_DIR dj, sdj;
+ BYTE *dir;
+ DWORD dclst;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 1);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME; /* Cannot remove dot entry */
+#if _FS_LOCK
+ if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */
+#endif
+ if (res == FR_OK) { /* The object is accessible */
+ dir = dj.dir;
+ if (!dir) {
+ res = FR_INVALID_NAME; /* Cannot remove the start directory */
+ } else {
+ if (dir[DIR_Attr] & AM_RDO)
+ res = FR_DENIED; /* Cannot remove R/O object */
+ }
+ dclst = ld_clust(dj.fs, dir);
+ if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */
+ if (dclst < 2) {
+ res = FR_INT_ERR;
+ } else {
+ mem_cpy(&sdj, &dj, sizeof (FATFS_DIR)); /* Check if the sub-dir is empty or not */
+ sdj.sclust = dclst;
+ res = dir_sdi(&sdj, 2); /* Exclude dot entries */
+ if (res == FR_OK) {
+ res = dir_read(&sdj);
+ if (res == FR_OK /* Not empty dir */
+#if _FS_RPATH
+ || dclst == dj.fs->cdir /* Current dir */
+#endif
+ ) res = FR_DENIED;
+ if (res == FR_NO_FILE) res = FR_OK; /* Empty */
+ }
+ }
+ }
+ if (res == FR_OK) {
+ res = dir_remove(&dj); /* Remove the directory entry */
+ if (res == FR_OK) {
+ if (dclst) /* Remove the cluster chain if exist */
+ res = remove_chain(dj.fs, dclst);
+ if (res == FR_OK) res = sync(dj.fs);
+ }
+ }
+ }
+ FREE_BUF();
+ }
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directory */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_mkdir (
+ const TCHAR *path /* Pointer to the directory path */
+)
+{
+ FRESULT res;
+ FATFS_DIR dj;
+ BYTE *dir, n;
+ DWORD dsc, dcl, pcl, tim = get_fattime();
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 1);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */
+ if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME;
+ if (res == FR_NO_FILE) { /* Can create a new directory */
+ dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */
+ res = FR_OK;
+ if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */
+ if (dcl == 1) res = FR_INT_ERR;
+ if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR;
+ if (res == FR_OK) /* Flush FAT */
+ res = move_window(dj.fs, 0);
+ if (res == FR_OK) { /* Initialize the new directory table */
+ dsc = clust2sect(dj.fs, dcl);
+ dir = dj.fs->win;
+ mem_set(dir, 0, SS(dj.fs));
+ mem_set(dir+DIR_Name, ' ', 8+3); /* Create "." entry */
+ dir[DIR_Name] = '.';
+ dir[DIR_Attr] = AM_DIR;
+ ST_DWORD(dir+DIR_WrtTime, tim);
+ st_clust(dir, dcl);
+ mem_cpy(dir+SZ_DIR, dir, SZ_DIR); /* Create ".." entry */
+ dir[33] = '.'; pcl = dj.sclust;
+ if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase)
+ pcl = 0;
+ st_clust(dir+SZ_DIR, pcl);
+ for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */
+ dj.fs->winsect = dsc++;
+ dj.fs->wflag = 1;
+ res = move_window(dj.fs, 0);
+ if (res != FR_OK) break;
+ mem_set(dir, 0, SS(dj.fs));
+ }
+ }
+ if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */
+ if (res != FR_OK) {
+ remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */
+ } else {
+ dir = dj.dir;
+ dir[DIR_Attr] = AM_DIR; /* Attribute */
+ ST_DWORD(dir+DIR_WrtTime, tim); /* Created time */
+ st_clust(dir, dcl); /* Table start cluster */
+ dj.fs->wflag = 1;
+ res = sync(dj.fs);
+ }
+ }
+ FREE_BUF();
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Attribute */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_chmod (
+ const TCHAR *path, /* Pointer to the file path */
+ BYTE value, /* Attribute bits */
+ BYTE mask /* Attribute mask to change */
+)
+{
+ FRESULT res;
+ FATFS_DIR dj;
+ BYTE *dir;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 1);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ FREE_BUF();
+ if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME;
+ if (res == FR_OK) {
+ dir = dj.dir;
+ if (!dir) { /* Is it a root directory? */
+ res = FR_INVALID_NAME;
+ } else { /* File or sub directory */
+ mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */
+ dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */
+ dj.fs->wflag = 1;
+ res = sync(dj.fs);
+ }
+ }
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Change Timestamp */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_utime (
+ const TCHAR *path, /* Pointer to the file/directory name */
+ const FILINFO *fno /* Pointer to the time stamp to be set */
+)
+{
+ FRESULT res;
+ FATFS_DIR dj;
+ BYTE *dir;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path, &dj.fs, 1);
+ if (res == FR_OK) {
+ INIT_BUF(dj);
+ res = follow_path(&dj, path); /* Follow the file path */
+ FREE_BUF();
+ if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME;
+ if (res == FR_OK) {
+ dir = dj.dir;
+ if (!dir) { /* Root directory */
+ res = FR_INVALID_NAME;
+ } else { /* File or sub-directory */
+ ST_WORD(dir+DIR_WrtTime, fno->ftime);
+ ST_WORD(dir+DIR_WrtDate, fno->fdate);
+ dj.fs->wflag = 1;
+ res = sync(dj.fs);
+ }
+ }
+ }
+
+ LEAVE_FF(dj.fs, res);
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Rename File/Directory */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_rename (
+ const TCHAR *path_old, /* Pointer to the old name */
+ const TCHAR *path_new /* Pointer to the new name */
+)
+{
+ FRESULT res;
+ FATFS_DIR djo, djn;
+ BYTE buf[21], *dir;
+ DWORD dw;
+ DEF_NAMEBUF;
+
+
+ res = chk_mounted(&path_old, &djo.fs, 1);
+ if (res == FR_OK) {
+ djn.fs = djo.fs;
+ INIT_BUF(djo);
+ res = follow_path(&djo, path_old); /* Check old object */
+ if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT))
+ res = FR_INVALID_NAME;
+#if _FS_LOCK
+ if (res == FR_OK) res = chk_lock(&djo, 2);
+#endif
+ if (res == FR_OK) { /* Old object is found */
+ if (!djo.dir) { /* Is root dir? */
+ res = FR_NO_FILE;
+ } else {
+ mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except for name */
+ mem_cpy(&djn, &djo, sizeof (FATFS_DIR)); /* Check new object */
+ res = follow_path(&djn, path_new);
+ if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */
+ if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */
+/* Start critical section that an interruption or error can cause cross-link */
+ res = dir_register(&djn); /* Register the new entry */
+ if (res == FR_OK) {
+ dir = djn.dir; /* Copy object information except for name */
+ mem_cpy(dir+13, buf+2, 19);
+ dir[DIR_Attr] = buf[0] | AM_ARC;
+ djo.fs->wflag = 1;
+ if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */
+ dw = clust2sect(djo.fs, ld_clust(djo.fs, dir));
+ if (!dw) {
+ res = FR_INT_ERR;
+ } else {
+ res = move_window(djo.fs, dw);
+ dir = djo.fs->win+SZ_DIR; /* .. entry */
+ if (res == FR_OK && dir[1] == '.') {
+ dw = (djo.fs->fs_type == FS_FAT32 && djn.sclust == djo.fs->dirbase) ? 0 : djn.sclust;
+ st_clust(dir, dw);
+ djo.fs->wflag = 1;
+ }
+ }
+ }
+ if (res == FR_OK) {
+ res = dir_remove(&djo); /* Remove old entry */
+ if (res == FR_OK)
+ res = sync(djo.fs);
+ }
+ }
+/* End critical section */
+ }
+ }
+ }
+ FREE_BUF();
+ }
+ LEAVE_FF(djo.fs, res);
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _FS_MINIMIZE == 0 */
+#endif /* _FS_MINIMIZE <= 1 */
+#endif /* _FS_MINIMIZE <= 2 */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Forward data to the stream directly (available on only tiny cfg) */
+/*-----------------------------------------------------------------------*/
+#if _USE_FORWARD && _FS_TINY
+
+FRESULT f_forward (
+ FIL *fp, /* Pointer to the file object */
+ UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */
+ UINT btr, /* Number of bytes to forward */
+ UINT *bf /* Pointer to number of bytes forwarded */
+)
+{
+ FRESULT res;
+ DWORD remain, clst, sect;
+ UINT rcnt;
+ BYTE csect;
+
+
+ *bf = 0; /* Clear transfer byte counter */
+
+ if (!fp) return FR_INVALID_OBJECT;
+
+ res = validate(fp); /* Check validity of the object */
+ if (res != FR_OK) LEAVE_FF(fp->fs, res);
+ if (fp->flag & FA__ERROR) /* Check error flag */
+ LEAVE_FF(fp->fs, FR_INT_ERR);
+ if (!(fp->flag & FA_READ)) /* Check access mode */
+ LEAVE_FF(fp->fs, FR_DENIED);
+
+ remain = fp->fsize - fp->fptr;
+ if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */
+
+ for ( ; btr && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */
+ fp->fptr += rcnt, *bf += rcnt, btr -= rcnt) {
+ csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */
+ if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */
+ if (!csect) { /* On the cluster boundary? */
+ clst = (fp->fptr == 0) ? /* On the top of the file? */
+ fp->sclust : get_fat(fp->fs, fp->clust);
+ if (clst <= 1) ABORT(fp->fs, FR_INT_ERR);
+ if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR);
+ fp->clust = clst; /* Update current cluster */
+ }
+ }
+ sect = clust2sect(fp->fs, fp->clust); /* Get current data sector */
+ if (!sect) ABORT(fp->fs, FR_INT_ERR);
+ sect += csect;
+ if (move_window(fp->fs, sect)) /* Move sector window */
+ ABORT(fp->fs, FR_DISK_ERR);
+ fp->dsect = sect;
+ rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */
+ if (rcnt > btr) rcnt = btr;
+ rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt);
+ if (!rcnt) ABORT(fp->fs, FR_INT_ERR);
+ }
+
+ LEAVE_FF(fp->fs, FR_OK);
+}
+#endif /* _USE_FORWARD */
+
+
+
+#if _USE_MKFS && !_FS_READONLY
+/*-----------------------------------------------------------------------*/
+/* Create File System on the Drive */
+/*-----------------------------------------------------------------------*/
+#define N_ROOTDIR 512 /* Number of root dir entries for FAT12/16 */
+#define N_FATS 1 /* Number of FAT copies (1 or 2) */
+
+
+FRESULT f_mkfs (
+ BYTE drv, /* Logical drive number */
+ BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */
+ UINT au /* Allocation unit size [bytes] */
+)
+{
+ static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0};
+ static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512};
+ BYTE fmt, md, sys, *tbl, pdrv, part;
+ DWORD n_clst, vs, n, wsect;
+ UINT i;
+ DWORD b_vol, b_fat, b_dir, b_data; /* LBA */
+ DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */
+ FATFS *fs;
+ DSTATUS stat;
+
+
+ /* Check mounted drive and clear work area */
+ if (drv >= _VOLUMES) return FR_INVALID_DRIVE;
+ if (sfd > 1) return FR_INVALID_PARAMETER;
+ if (au & (au - 1)) return FR_INVALID_PARAMETER;
+ fs = FatFs[drv];
+ if (!fs) return FR_NOT_ENABLED;
+ fs->fs_type = 0;
+ pdrv = LD2PD(drv); /* Physical drive */
+ part = LD2PT(drv); /* Partition (0:auto detect, 1-4:get from partition table)*/
+
+ /* Get disk statics */
+ stat = disk_initialize(pdrv);
+ if (stat & STA_NOINIT) return FR_NOT_READY;
+ if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+#if _MAX_SS != 512 /* Get disk sector size */
+ if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS)
+ return FR_DISK_ERR;
+#endif
+ if (_MULTI_PARTITION && part) {
+ /* Get partition information from partition table in the MBR */
+ if (disk_read(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR;
+ if (LD_WORD(fs->win+BS_55AA) != 0xAA55) return FR_MKFS_ABORTED;
+ tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE];
+ if (!tbl[4]) return FR_MKFS_ABORTED; /* No partition? */
+ b_vol = LD_DWORD(tbl+8); /* Volume start sector */
+ n_vol = LD_DWORD(tbl+12); /* Volume size */
+ } else {
+ /* Create a partition in this function */
+ if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128)
+ return FR_DISK_ERR;
+ b_vol = (sfd) ? 0 : 63; /* Volume start sector */
+ n_vol -= b_vol; /* Volume size */
+ }
+
+ if (!au) { /* AU auto selection */
+ vs = n_vol / (2000 / (SS(fs) / 512));
+ for (i = 0; vs < vst[i]; i++) ;
+ au = cst[i];
+ }
+ au /= SS(fs); /* Number of sectors per cluster */
+ if (au == 0) au = 1;
+ if (au > 128) au = 128;
+
+ /* Pre-compute number of clusters and FAT sub-type */
+ n_clst = n_vol / au;
+ fmt = FS_FAT12;
+ if (n_clst >= MIN_FAT16) fmt = FS_FAT16;
+ if (n_clst >= MIN_FAT32) fmt = FS_FAT32;
+
+ /* Determine offset and size of FAT structure */
+ if (fmt == FS_FAT32) {
+ n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs);
+ n_rsv = 32;
+ n_dir = 0;
+ } else {
+ n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4;
+ n_fat = (n_fat + SS(fs) - 1) / SS(fs);
+ n_rsv = 1;
+ n_dir = (DWORD)N_ROOTDIR * SZ_DIR / SS(fs);
+ }
+ b_fat = b_vol + n_rsv; /* FAT area start sector */
+ b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */
+ b_data = b_dir + n_dir; /* Data area start sector */
+ if (n_vol < b_data + au - b_vol) return FR_MKFS_ABORTED; /* Too small volume */
+
+ /* Align data start sector to erase block boundary (for flash memory media) */
+ if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1;
+ n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */
+ n = (n - b_data) / N_FATS;
+ if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */
+ n_rsv += n;
+ b_fat += n;
+ } else { /* FAT12/16: Expand FAT size */
+ n_fat += n;
+ }
+
+ /* Determine number of clusters and final check of validity of the FAT sub-type */
+ n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au;
+ if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16)
+ || (fmt == FS_FAT32 && n_clst < MIN_FAT32))
+ return FR_MKFS_ABORTED;
+
+ switch (fmt) { /* Determine system ID for partition table */
+ case FS_FAT12: sys = 0x01; break;
+ case FS_FAT16: sys = (n_vol < 0x10000) ? 0x04 : 0x06; break;
+ default: sys = 0x0C;
+ }
+
+ if (_MULTI_PARTITION && part) {
+ /* Update system ID in the partition table */
+ tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE];
+ tbl[4] = sys;
+ if (disk_write(pdrv, fs->win, 0, 1) != RES_OK) return FR_DISK_ERR;
+ md = 0xF8;
+ } else {
+ if (sfd) { /* No partition table (SFD) */
+ md = 0xF0;
+ } else { /* Create partition table (FDISK) */
+ mem_set(fs->win, 0, SS(fs));
+ tbl = fs->win+MBR_Table; /* Create partition table for single partition in the drive */
+ tbl[1] = 1; /* Partition start head */
+ tbl[2] = 1; /* Partition start sector */
+ tbl[3] = 0; /* Partition start cylinder */
+ tbl[4] = sys; /* System type */
+ tbl[5] = 254; /* Partition end head */
+ n = (b_vol + n_vol) / 63 / 255;
+ tbl[6] = (BYTE)((n >> 2) | 63); /* Partition end sector */
+ tbl[7] = (BYTE)n; /* End cylinder */
+ ST_DWORD(tbl+8, 63); /* Partition start in LBA */
+ ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */
+ ST_WORD(fs->win+BS_55AA, 0xAA55); /* MBR signature */
+ if (disk_write(pdrv, fs->win, 0, 1) != RES_OK) /* Write it to the MBR sector */
+ return FR_DISK_ERR;
+ md = 0xF8;
+ }
+ }
+
+ /* Create BPB in the VBR */
+ tbl = fs->win; /* Clear sector */
+ mem_set(tbl, 0, SS(fs));
+ mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code, OEM name */
+ i = SS(fs); /* Sector size */
+ ST_WORD(tbl+BPB_BytsPerSec, i);
+ tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */
+ ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */
+ tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */
+ i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of rootdir entries */
+ ST_WORD(tbl+BPB_RootEntCnt, i);
+ if (n_vol < 0x10000) { /* Number of total sectors */
+ ST_WORD(tbl+BPB_TotSec16, n_vol);
+ } else {
+ ST_DWORD(tbl+BPB_TotSec32, n_vol);
+ }
+ tbl[BPB_Media] = md; /* Media descriptor */
+ ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */
+ ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */
+ ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */
+ n = get_fattime(); /* Use current time as VSN */
+ if (fmt == FS_FAT32) {
+ ST_DWORD(tbl+BS_VolID32, n); /* VSN */
+ ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */
+ ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */
+ ST_WORD(tbl+BPB_FSInfo, 1); /* FSInfo record offset (VBR+1) */
+ ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */
+ tbl[BS_DrvNum32] = 0x80; /* Drive number */
+ tbl[BS_BootSig32] = 0x29; /* Extended boot signature */
+ mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */
+ } else {
+ ST_DWORD(tbl+BS_VolID, n); /* VSN */
+ ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */
+ tbl[BS_DrvNum] = 0x80; /* Drive number */
+ tbl[BS_BootSig] = 0x29; /* Extended boot signature */
+ mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */
+ }
+ ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */
+ if (disk_write(pdrv, tbl, b_vol, 1) != RES_OK) /* Write it to the VBR sector */
+ return FR_DISK_ERR;
+ if (fmt == FS_FAT32) /* Write backup VBR if needed (VBR+6) */
+ disk_write(pdrv, tbl, b_vol + 6, 1);
+
+ /* Initialize FAT area */
+ wsect = b_fat;
+ for (i = 0; i < N_FATS; i++) { /* Initialize each FAT copy */
+ mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */
+ n = md; /* Media descriptor byte */
+ if (fmt != FS_FAT32) {
+ n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00;
+ ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */
+ } else {
+ n |= 0xFFFFFF00;
+ ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */
+ ST_DWORD(tbl+4, 0xFFFFFFFF);
+ ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root dir */
+ }
+ if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+ return FR_DISK_ERR;
+ mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */
+ for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector writes */
+ if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+ return FR_DISK_ERR;
+ }
+ }
+
+ /* Initialize root directory */
+ i = (fmt == FS_FAT32) ? au : n_dir;
+ do {
+ if (disk_write(pdrv, tbl, wsect++, 1) != RES_OK)
+ return FR_DISK_ERR;
+ } while (--i);
+
+#if _USE_ERASE /* Erase data area if needed */
+ {
+ DWORD eb[2];
+
+ eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1;
+ disk_ioctl(pdrv, CTRL_ERASE_SECTOR, eb);
+ }
+#endif
+
+ /* Create FSInfo if needed */
+ if (fmt == FS_FAT32) {
+ ST_DWORD(tbl+FSI_LeadSig, 0x41615252);
+ ST_DWORD(tbl+FSI_StrucSig, 0x61417272);
+ ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); /* Number of free clusters */
+ ST_DWORD(tbl+FSI_Nxt_Free, 2); /* Last allocated cluster# */
+ ST_WORD(tbl+BS_55AA, 0xAA55);
+ disk_write(pdrv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */
+ disk_write(pdrv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */
+ }
+
+ return (disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR;
+}
+
+
+#if _MULTI_PARTITION == 2
+/*-----------------------------------------------------------------------*/
+/* Divide Physical Drive */
+/*-----------------------------------------------------------------------*/
+
+FRESULT f_fdisk (
+ BYTE pdrv, /* Physical drive number */
+ const DWORD szt[], /* Pointer to the size table for each partitions */
+ void* work /* Pointer to the working buffer */
+)
+{
+ UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl;
+ BYTE s_hd, e_hd, *p, *buf = (BYTE*)work;
+ DSTATUS stat;
+ DWORD sz_disk, sz_part, s_part;
+
+
+ stat = disk_initialize(pdrv);
+ if (stat & STA_NOINIT) return FR_NOT_READY;
+ if (stat & STA_PROTECT) return FR_WRITE_PROTECTED;
+ if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR;
+
+ /* Determine CHS in the table regardless of the drive geometry */
+ for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ;
+ if (n == 256) n--;
+ e_hd = n - 1;
+ sz_cyl = 63 * n;
+ tot_cyl = sz_disk / sz_cyl;
+
+ /* Create partition table */
+ mem_set(buf, 0, _MAX_SS);
+ p = buf + MBR_Table; b_cyl = 0;
+ for (i = 0; i < 4; i++, p += SZ_PTE) {
+ p_cyl = (szt[i] <= 100) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl;
+ if (!p_cyl) continue;
+ s_part = (DWORD)sz_cyl * b_cyl;
+ sz_part = (DWORD)sz_cyl * p_cyl;
+ if (i == 0) { /* Exclude first track of cylinder 0 */
+ s_hd = 1;
+ s_part += 63; sz_part -= 63;
+ } else {
+ s_hd = 0;
+ }
+ e_cyl = b_cyl + p_cyl - 1;
+ if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER;
+
+ /* Set partition table */
+ p[1] = s_hd; /* Start head */
+ p[2] = (BYTE)((b_cyl >> 2) + 1); /* Start sector */
+ p[3] = (BYTE)b_cyl; /* Start cylinder */
+ p[4] = 0x06; /* System type (temporary setting) */
+ p[5] = e_hd; /* End head */
+ p[6] = (BYTE)((e_cyl >> 2) + 63); /* End sector */
+ p[7] = (BYTE)e_cyl; /* End cylinder */
+ ST_DWORD(p + 8, s_part); /* Start sector in LBA */
+ ST_DWORD(p + 12, sz_part); /* Partition size */
+
+ /* Next partition */
+ b_cyl += p_cyl;
+ }
+ ST_WORD(p, 0xAA55);
+
+ /* Write it to the MBR */
+ return (disk_write(pdrv, buf, 0, 1) || disk_ioctl(pdrv, CTRL_SYNC, 0)) ? FR_DISK_ERR : FR_OK;
+}
+
+
+#endif /* _MULTI_PARTITION == 2 */
+#endif /* _USE_MKFS && !_FS_READONLY */
+
+
+
+
+#if _USE_STRFUNC
+/*-----------------------------------------------------------------------*/
+/* Get a string from the file */
+/*-----------------------------------------------------------------------*/
+TCHAR* f_gets (
+ TCHAR* buff, /* Pointer to the string buffer to read */
+ int len, /* Size of string buffer (characters) */
+ FIL* fil /* Pointer to the file object */
+)
+{
+ int n = 0;
+ TCHAR c, *p = buff;
+ BYTE s[2];
+ UINT rc;
+
+
+ while (n < len - 1) { /* Read bytes until buffer gets filled */
+ f_read(fil, s, 1, &rc);
+ if (rc != 1) break; /* Break on EOF or error */
+ c = s[0];
+#if _LFN_UNICODE /* Read a character in UTF-8 encoding */
+ if (c >= 0x80) {
+ if (c < 0xC0) continue; /* Skip stray trailer */
+ if (c < 0xE0) { /* Two-byte sequence */
+ f_read(fil, s, 1, &rc);
+ if (rc != 1) break;
+ c = ((c & 0x1F) << 6) | (s[0] & 0x3F);
+ if (c < 0x80) c = '?';
+ } else {
+ if (c < 0xF0) { /* Three-byte sequence */
+ f_read(fil, s, 2, &rc);
+ if (rc != 2) break;
+ c = (c << 12) | ((s[0] & 0x3F) << 6) | (s[1] & 0x3F);
+ if (c < 0x800) c = '?';
+ } else { /* Reject four-byte sequence */
+ c = '?';
+ }
+ }
+ }
+#endif
+#if _USE_STRFUNC >= 2
+ if (c == '\r') continue; /* Strip '\r' */
+#endif
+ *p++ = c;
+ n++;
+ if (c == '\n') break; /* Break on EOL */
+ }
+ *p = 0;
+ return n ? buff : 0; /* When no data read (eof or error), return with error. */
+}
+
+
+
+#if !_FS_READONLY
+#include <stdarg.h>
+/*-----------------------------------------------------------------------*/
+/* Put a character to the file */
+/*-----------------------------------------------------------------------*/
+int f_putc (
+ TCHAR c, /* A character to be output */
+ FIL* fil /* Pointer to the file object */
+)
+{
+ UINT bw, btw;
+ BYTE s[3];
+
+
+#if _USE_STRFUNC >= 2
+ if (c == '\n') f_putc ('\r', fil); /* LF -> CRLF conversion */
+#endif
+
+#if _LFN_UNICODE /* Write the character in UTF-8 encoding */
+ if (c < 0x80) { /* 7-bit */
+ s[0] = (BYTE)c;
+ btw = 1;
+ } else {
+ if (c < 0x800) { /* 11-bit */
+ s[0] = (BYTE)(0xC0 | (c >> 6));
+ s[1] = (BYTE)(0x80 | (c & 0x3F));
+ btw = 2;
+ } else { /* 16-bit */
+ s[0] = (BYTE)(0xE0 | (c >> 12));
+ s[1] = (BYTE)(0x80 | ((c >> 6) & 0x3F));
+ s[2] = (BYTE)(0x80 | (c & 0x3F));
+ btw = 3;
+ }
+ }
+#else /* Write the character without conversion */
+ s[0] = (BYTE)c;
+ btw = 1;
+#endif
+ f_write(fil, s, btw, &bw); /* Write the char to the file */
+ return (bw == btw) ? 1 : EOF; /* Return the result */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a string to the file */
+/*-----------------------------------------------------------------------*/
+int f_puts (
+ const TCHAR* str, /* Pointer to the string to be output */
+ FIL* fil /* Pointer to the file object */
+)
+{
+ int n;
+
+
+ for (n = 0; *str; str++, n++) {
+ if (f_putc(*str, fil) == EOF) return EOF;
+ }
+ return n;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Put a formatted string to the file */
+/*-----------------------------------------------------------------------*/
+int f_printf (
+ FIL* fil, /* Pointer to the file object */
+ const TCHAR* str, /* Pointer to the format string */
+ ... /* Optional arguments... */
+)
+{
+ va_list arp;
+ BYTE f, r;
+ UINT i, j, w;
+ ULONG v;
+ TCHAR c, d, s[16], *p;
+ int res, chc, cc;
+
+
+ va_start(arp, str);
+
+ for (cc = res = 0; cc != EOF; res += cc) {
+ c = *str++;
+ if (c == 0) break; /* End of string */
+ if (c != '%') { /* Non escape character */
+ cc = f_putc(c, fil);
+ if (cc != EOF) cc = 1;
+ continue;
+ }
+ w = f = 0;
+ c = *str++;
+ if (c == '0') { /* Flag: '0' padding */
+ f = 1; c = *str++;
+ } else {
+ if (c == '-') { /* Flag: left justified */
+ f = 2; c = *str++;
+ }
+ }
+ while (IsDigit(c)) { /* Precision */
+ w = w * 10 + c - '0';
+ c = *str++;
+ }
+ if (c == 'l' || c == 'L') { /* Prefix: Size is long int */
+ f |= 4; c = *str++;
+ }
+ if (!c) break;
+ d = c;
+ if (IsLower(d)) d -= 0x20;
+ switch (d) { /* Type is... */
+ case 'S' : /* String */
+ p = va_arg(arp, TCHAR*);
+ for (j = 0; p[j]; j++) ;
+ chc = 0;
+ if (!(f & 2)) {
+ while (j++ < w) chc += (cc = f_putc(' ', fil));
+ }
+ chc += (cc = f_puts(p, fil));
+ while (j++ < w) chc += (cc = f_putc(' ', fil));
+ if (cc != EOF) cc = chc;
+ continue;
+ case 'C' : /* Character */
+ cc = f_putc((TCHAR)va_arg(arp, int), fil); continue;
+ case 'B' : /* Binary */
+ r = 2; break;
+ case 'O' : /* Octal */
+ r = 8; break;
+ case 'D' : /* Signed decimal */
+ case 'U' : /* Unsigned decimal */
+ r = 10; break;
+ case 'X' : /* Hexdecimal */
+ r = 16; break;
+ default: /* Unknown type (pass-through) */
+ cc = f_putc(c, fil); continue;
+ }
+
+ /* Get an argument and put it in numeral */
+ v = (f & 4) ? (ULONG)va_arg(arp, long) : ((d == 'D') ? (ULONG)(long)va_arg(arp, int) : (ULONG)va_arg(arp, unsigned int));
+ if (d == 'D' && (v & 0x80000000)) {
+ v = 0 - v;
+ f |= 8;
+ }
+ i = 0;
+ do {
+ d = (TCHAR)(v % r); v /= r;
+ if (d > 9) d += (c == 'x') ? 0x27 : 0x07;
+ s[i++] = d + '0';
+ } while (v && i < sizeof s / sizeof s[0]);
+ if (f & 8) s[i++] = '-';
+ j = i; d = (f & 1) ? '0' : ' ';
+ res = 0;
+ while (!(f & 2) && j++ < w) res += (cc = f_putc(d, fil));
+ do res += (cc = f_putc(s[--i], fil)); while(i);
+ while (j++ < w) res += (cc = f_putc(' ', fil));
+ if (cc != EOF) cc = res;
+ }
+
+ va_end(arp);
+ return (cc == EOF) ? cc : res;
+}
+
+#endif /* !_FS_READONLY */
+#endif /* _USE_STRFUNC */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ff.h b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ff.h
new file mode 100644
index 000000000..610ad0a68
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ff.h
@@ -0,0 +1,337 @@
+/*---------------------------------------------------------------------------/
+/ FatFs - FAT file system module include file R0.09a (C)ChaN, 2012
+/----------------------------------------------------------------------------/
+/ FatFs module is a generic FAT file system module for small embedded systems.
+/ This is a free software that opened for education, research and commercial
+/ developments under license policy of following terms.
+/
+/ Copyright (C) 2012, ChaN, all right reserved.
+/
+/ * The FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/----------------------------------------------------------------------------*/
+
+#ifndef _FATFS
+#define _FATFS 4004 /* Revision ID */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "integer.h" /* Basic integer types */
+#include "ffconf.h" /* FatFs configuration options */
+
+#if _FATFS != _FFCONF
+#error Wrong configuration file (ffconf.h).
+#endif
+
+
+
+/* Definitions of volume management */
+
+#if _MULTI_PARTITION /* Multiple partition configuration */
+typedef struct {
+ BYTE pd; /* Physical drive number */
+ BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
+} PARTITION;
+extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
+#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive number */
+#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition index */
+
+#else /* Single partition configuration */
+#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */
+#define LD2PT(vol) 0 /* Always mounts the 1st partition or in SFD */
+
+#endif
+
+
+
+/* Type of path name strings on FatFs API */
+
+#if _LFN_UNICODE /* Unicode string */
+#if !_USE_LFN
+#error _LFN_UNICODE must be 0 in non-LFN cfg.
+#endif
+#ifndef _INC_TCHAR
+typedef WCHAR TCHAR;
+#define _T(x) L ## x
+#define _TEXT(x) L ## x
+#endif
+
+#else /* ANSI/OEM string */
+#ifndef _INC_TCHAR
+typedef char TCHAR;
+#define _T(x) x
+#define _TEXT(x) x
+#endif
+
+#endif
+
+
+
+/* File system object structure (FATFS) */
+
+typedef struct {
+ BYTE fs_type; /* FAT sub-type (0:Not mounted) */
+ BYTE drv; /* Physical drive number */
+ BYTE csize; /* Sectors per cluster (1,2,4...128) */
+ BYTE n_fats; /* Number of FAT copies (1,2) */
+ BYTE wflag; /* win[] dirty flag (1:must be written back) */
+ BYTE fsi_flag; /* fsinfo dirty flag (1:must be written back) */
+ WORD id; /* File system mount ID */
+ WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
+#if _MAX_SS != 512
+ WORD ssize; /* Bytes per sector (512, 1024, 2048 or 4096) */
+#endif
+#if _FS_REENTRANT
+ _SYNC_t sobj; /* Identifier of sync object */
+#endif
+#if !_FS_READONLY
+ DWORD last_clust; /* Last allocated cluster */
+ DWORD free_clust; /* Number of free clusters */
+ DWORD fsi_sector; /* fsinfo sector (FAT32) */
+#endif
+#if _FS_RPATH
+ DWORD cdir; /* Current directory start cluster (0:root) */
+#endif
+ DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */
+ DWORD fsize; /* Sectors per FAT */
+ DWORD fatbase; /* FAT start sector */
+ DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */
+ DWORD database; /* Data start sector */
+ DWORD winsect; /* Current sector appearing in the win[] */
+ BYTE win[_MAX_SS]; /* Disk access window for Directory, FAT (and Data on tiny cfg) */
+} FATFS;
+
+
+
+/* File object structure (FIL) */
+
+typedef struct {
+ FATFS* fs; /* Pointer to the related file system object */
+ WORD id; /* File system mount ID of the related file system object */
+ BYTE flag; /* File status flags */
+ BYTE pad1;
+ DWORD fptr; /* File read/write pointer (0ed on file open) */
+ DWORD fsize; /* File size */
+ DWORD sclust; /* File data start cluster (0:no data cluster, always 0 when fsize is 0) */
+ DWORD clust; /* Current cluster of fpter */
+ DWORD dsect; /* Current data sector of fpter */
+#if !_FS_READONLY
+ DWORD dir_sect; /* Sector containing the directory entry */
+ BYTE* dir_ptr; /* Pointer to the directory entry in the window */
+#endif
+#if _USE_FASTSEEK
+ DWORD* cltbl; /* Pointer to the cluster link map table (null on file open) */
+#endif
+#if _FS_LOCK
+ UINT lockid; /* File lock ID (index of file semaphore table Files[]) */
+#endif
+#if !_FS_TINY
+ BYTE buf[_MAX_SS]; /* File data read/write buffer */
+#endif
+} FIL;
+
+
+
+/* Directory object structure (DIR) */
+
+typedef struct {
+ FATFS* fs; /* Pointer to the owner file system object */
+ WORD id; /* Owner file system mount ID */
+ WORD index; /* Current read/write index number */
+ DWORD sclust; /* Table start cluster (0:Root dir) */
+ DWORD clust; /* Current cluster */
+ DWORD sect; /* Current sector */
+ BYTE* dir; /* Pointer to the current SFN entry in the win[] */
+ BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+#if _USE_LFN
+ WCHAR* lfn; /* Pointer to the LFN working buffer */
+ WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */
+#endif
+} FATFS_DIR;
+
+
+
+/* File status structure (FILINFO) */
+
+typedef struct {
+ DWORD fsize; /* File size */
+ WORD fdate; /* Last modified date */
+ WORD ftime; /* Last modified time */
+ BYTE fattrib; /* Attribute */
+ TCHAR fname[13]; /* Short file name (8.3 format) */
+#if _USE_LFN
+ TCHAR* lfname; /* Pointer to the LFN buffer */
+ UINT lfsize; /* Size of LFN buffer in TCHAR */
+#endif
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+ FR_OK = 0, /* (0) Succeeded */
+ FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
+ FR_INT_ERR, /* (2) Assertion failed */
+ FR_NOT_READY, /* (3) The physical drive cannot work */
+ FR_NO_FILE, /* (4) Could not find the file */
+ FR_NO_PATH, /* (5) Could not find the path */
+ FR_INVALID_NAME, /* (6) The path name format is invalid */
+ FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
+ FR_EXIST, /* (8) Access denied due to prohibited access */
+ FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
+ FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
+ FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
+ FR_NOT_ENABLED, /* (12) The volume has no work area */
+ FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
+ FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */
+ FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
+ FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
+ FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
+ FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_SHARE */
+ FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* FatFs module application interface */
+
+FRESULT f_mount (BYTE, FATFS*); /* Mount/Unmount a logical drive */
+FRESULT f_open (FIL*, const TCHAR*, BYTE); /* Open or create a file */
+FRESULT f_read (FIL*, void*, UINT, UINT*); /* Read data from a file */
+FRESULT f_lseek (FIL*, DWORD); /* Move file pointer of a file object */
+FRESULT f_close (FIL*); /* Close an open file object */
+FRESULT f_opendir (FATFS_DIR*, const TCHAR*); /* Open an existing directory */
+FRESULT f_readdir (FATFS_DIR*, FILINFO*); /* Read a directory item */
+FRESULT f_stat (const TCHAR*, FILINFO*); /* Get file status */
+FRESULT f_write (FIL*, const void*, UINT, UINT*); /* Write data to a file */
+FRESULT f_getfree (const TCHAR*, DWORD*, FATFS**); /* Get number of free clusters on the drive */
+FRESULT f_truncate (FIL*); /* Truncate file */
+FRESULT f_sync (FIL*); /* Flush cached data of a writing file */
+FRESULT f_unlink (const TCHAR*); /* Delete an existing file or directory */
+FRESULT f_mkdir (const TCHAR*); /* Create a new directory */
+FRESULT f_chmod (const TCHAR*, BYTE, BYTE); /* Change attribute of the file/dir */
+FRESULT f_utime (const TCHAR*, const FILINFO*); /* Change times-tamp of the file/dir */
+FRESULT f_rename (const TCHAR*, const TCHAR*); /* Rename/Move a file or directory */
+FRESULT f_chdrive (BYTE); /* Change current drive */
+FRESULT f_chdir (const TCHAR*); /* Change current directory */
+FRESULT f_getcwd (TCHAR*, UINT); /* Get current directory */
+FRESULT f_forward (FIL*, UINT(*)(const BYTE*,UINT), UINT, UINT*); /* Forward data to the stream */
+FRESULT f_mkfs (BYTE, BYTE, UINT); /* Create a file system on the drive */
+FRESULT f_fdisk (BYTE, const DWORD[], void*); /* Divide a physical drive into some partitions */
+int f_putc (TCHAR, FIL*); /* Put a character to the file */
+int f_puts (const TCHAR*, FIL*); /* Put a string to the file */
+int f_printf (FIL*, const TCHAR*, ...); /* Put a formatted string to the file */
+TCHAR* f_gets (TCHAR*, int, FIL*); /* Get a string from the file */
+
+#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0)
+#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0)
+#define f_tell(fp) ((fp)->fptr)
+#define f_size(fp) ((fp)->fsize)
+
+#ifndef EOF
+#define EOF (-1)
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Additional user defined functions */
+
+/* RTC function */
+#if !_FS_READONLY
+DWORD get_fattime (void);
+#endif
+
+/* Unicode support functions */
+#if _USE_LFN /* Unicode - OEM code conversion */
+WCHAR ff_convert (WCHAR, UINT); /* OEM-Unicode bidirectional conversion */
+WCHAR ff_wtoupper (WCHAR); /* Unicode upper-case conversion */
+#if _USE_LFN == 3 /* Memory functions */
+void* ff_memalloc (UINT); /* Allocate memory block */
+void ff_memfree (void*); /* Free memory block */
+#endif
+#endif
+
+/* Sync functions */
+#if _FS_REENTRANT
+int ff_cre_syncobj (BYTE, _SYNC_t*);/* Create a sync object */
+int ff_req_grant (_SYNC_t); /* Lock sync object */
+void ff_rel_grant (_SYNC_t); /* Unlock sync object */
+int ff_del_syncobj (_SYNC_t); /* Delete a sync object */
+#endif
+
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address */
+
+
+/* File access control and file status flags (FIL.flag) */
+
+#define FA_READ 0x01
+#define FA_OPEN_EXISTING 0x00
+#define FA__ERROR 0x80
+
+#if !_FS_READONLY
+#define FA_WRITE 0x02
+#define FA_CREATE_NEW 0x04
+#define FA_CREATE_ALWAYS 0x08
+#define FA_OPEN_ALWAYS 0x10
+#define FA__WRITTEN 0x20
+#define FA__DIRTY 0x40
+#endif
+
+
+/* FAT sub type (FATFS.fs_type) */
+
+#define FS_FAT12 1
+#define FS_FAT16 2
+#define FS_FAT32 3
+
+
+/* File attribute bits for directory entry */
+
+#define AM_RDO 0x01 /* Read only */
+#define AM_HID 0x02 /* Hidden */
+#define AM_SYS 0x04 /* System */
+#define AM_VOL 0x08 /* Volume label */
+#define AM_LFN 0x0F /* LFN entry */
+#define AM_DIR 0x10 /* Directory */
+#define AM_ARC 0x20 /* Archive */
+#define AM_MASK 0x3F /* Mask of defined bits */
+
+
+/* Fast seek feature */
+#define CREATE_LINKMAP 0xFFFFFFFF
+
+
+
+/*--------------------------------*/
+/* Multi-byte word access macros */
+
+#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */
+#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr))
+#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr))
+#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val)
+#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
+#else /* Use byte-by-byte access to the FAT structure */
+#define LD_WORD(ptr) (WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
+#define LD_DWORD(ptr) (DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
+#define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
+#define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FATFS */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ffconf.h b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ffconf.h
new file mode 100644
index 000000000..959f98468
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/ffconf.h
@@ -0,0 +1,198 @@
+/*---------------------------------------------------------------------------/
+/ FatFs - FAT file system module configuration file R0.09a (C)ChaN, 2012
+/----------------------------------------------------------------------------/
+/
+/ CAUTION! Do not forget to make clean the project after any changes to
+/ the configuration options.
+/
+/----------------------------------------------------------------------------*/
+#ifndef _FFCONF
+#define _FFCONF 4004 /* Revision ID */
+
+#define FFS_DBG 0
+
+/*---------------------------------------------------------------------------/
+/ Functions and Buffer Configurations
+/----------------------------------------------------------------------------*/
+
+#define _FS_TINY 0 /* 0:Normal or 1:Tiny */
+/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
+/ object instead of the sector buffer in the individual file object for file
+/ data transfer. This reduces memory consumption 512 bytes each file object. */
+
+
+#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */
+/* Setting _FS_READONLY to 1 defines read only configuration. This removes
+/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename,
+/ f_truncate and useless f_getfree. */
+
+
+#define _FS_MINIMIZE 0 /* 0 to 3 */
+/* The _FS_MINIMIZE option defines minimization level to remove some functions.
+/
+/ 0: Full function.
+/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename
+/ are removed.
+/ 2: f_opendir and f_readdir are removed in addition to 1.
+/ 3: f_lseek is removed in addition to 2. */
+
+
+#define _USE_STRFUNC 0 /* 0:Disable or 1-2:Enable */
+/* To enable string functions, set _USE_STRFUNC to 1 or 2. */
+
+
+#define _USE_MKFS 1 /* 0:Disable or 1:Enable */
+/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */
+
+
+#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */
+/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
+
+
+#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */
+/* To enable fast seek feature, set _USE_FASTSEEK to 1. */
+
+
+
+/*---------------------------------------------------------------------------/
+/ Locale and Namespace Configurations
+/----------------------------------------------------------------------------*/
+
+#define _CODE_PAGE 858
+/* The _CODE_PAGE specifies the OEM code page to be used on the target system.
+/ Incorrect setting of the code page can cause a file open failure.
+/
+/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows)
+/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows)
+/ 949 - Korean (DBCS, OEM, Windows)
+/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows)
+/ 1250 - Central Europe (Windows)
+/ 1251 - Cyrillic (Windows)
+/ 1252 - Latin 1 (Windows)
+/ 1253 - Greek (Windows)
+/ 1254 - Turkish (Windows)
+/ 1255 - Hebrew (Windows)
+/ 1256 - Arabic (Windows)
+/ 1257 - Baltic (Windows)
+/ 1258 - Vietnam (OEM, Windows)
+/ 437 - U.S. (OEM)
+/ 720 - Arabic (OEM)
+/ 737 - Greek (OEM)
+/ 775 - Baltic (OEM)
+/ 850 - Multilingual Latin 1 (OEM)
+/ 858 - Multilingual Latin 1 + Euro (OEM)
+/ 852 - Latin 2 (OEM)
+/ 855 - Cyrillic (OEM)
+/ 866 - Russian (OEM)
+/ 857 - Turkish (OEM)
+/ 862 - Hebrew (OEM)
+/ 874 - Thai (OEM, Windows)
+/ 1 - ASCII only (Valid for non LFN cfg.)
+*/
+
+
+#define _USE_LFN 1 /* 0 to 3 */
+#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */
+/* The _USE_LFN option switches the LFN support.
+/
+/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect.
+/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant.
+/ 2: Enable LFN with dynamic working buffer on the STACK.
+/ 3: Enable LFN with dynamic working buffer on the HEAP.
+/
+/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN,
+/ Unicode handling functions ff_convert() and ff_wtoupper() must be added
+/ to the project. When enable to use heap, memory control functions
+/ ff_memalloc() and ff_memfree() must be added to the project. */
+
+
+#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */
+/* To switch the character code set on FatFs API to Unicode,
+/ enable LFN feature and set _LFN_UNICODE to 1. */
+
+
+#define _FS_RPATH 0 /* 0 to 2 */
+/* The _FS_RPATH option configures relative path feature.
+/
+/ 0: Disable relative path feature and remove related functions.
+/ 1: Enable relative path. f_chdrive() and f_chdir() are available.
+/ 2: f_getcwd() is available in addition to 1.
+/
+/ Note that output of the f_readdir fnction is affected by this option. */
+
+
+
+/*---------------------------------------------------------------------------/
+/ Physical Drive Configurations
+/----------------------------------------------------------------------------*/
+
+#define _VOLUMES 1
+/* Number of volumes (logical drives) to be used. */
+
+
+#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */
+/* Maximum sector size to be handled.
+/ Always set 512 for memory card and hard disk but a larger value may be
+/ required for on-board flash memory, floppy disk and optical disk.
+/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size
+/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */
+
+
+#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */
+/* When set to 0, each volume is bound to the same physical drive number and
+/ it can mount only first primaly partition. When it is set to 1, each volume
+/ is tied to the partitions listed in VolToPart[]. */
+
+
+#define _USE_ERASE 0 /* 0:Disable or 1:Enable */
+/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command
+/ should be added to the disk_ioctl functio. */
+
+
+
+/*---------------------------------------------------------------------------/
+/ System Configurations
+/----------------------------------------------------------------------------*/
+
+#define _WORD_ACCESS 0 /* 0 or 1 */
+/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS
+/ option defines which access method is used to the word data on the FAT volume.
+/
+/ 0: Byte-by-byte access.
+/ 1: Word access. Do not choose this unless following condition is met.
+/
+/ When the byte order on the memory is big-endian or address miss-aligned word
+/ access results incorrect behavior, the _WORD_ACCESS must be set to 0.
+/ If it is not the case, the value can also be set to 1 to improve the
+/ performance and code size.
+*/
+
+
+/* A header file that defines sync object types on the O/S, such as
+/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */
+
+#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */
+#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */
+#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */
+
+/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module.
+/
+/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect.
+/ 1: Enable reentrancy. Also user provided synchronization handlers,
+/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj
+/ function must be added to the project. */
+
+
+#define _FS_LOCK 0 /* 0:Disable or >=1:Enable */
+/* To enable file lock control feature, set _FS_LOCK to 1 or greater.
+ The value defines how many files can be opened simultaneously. */
+
+#define FLUSH_ON_NEW_CLUSTER 0 /* Sync the file on every new cluster */
+#define FLUSH_ON_NEW_SECTOR 1 /* Sync the file on every new sector */
+/* Only one of these two defines needs to be set to 1. If both are set to 0
+ the file is only sync when closed.
+ Clusters are group of sectors (eg: 8 sectors). Flushing on new cluster means
+ it would be less often than flushing on new sector. Sectors are generally
+ 512 Bytes long. */
+
+#endif /* _FFCONFIG */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/integer.h b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/integer.h
new file mode 100644
index 000000000..1b99b37f6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/ChaN/integer.h
@@ -0,0 +1,37 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _INTEGER
+#define _INTEGER
+
+#ifdef _WIN32 /* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+
+#else /* Embedded platform */
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef int INT;
+typedef unsigned int UINT;
+
+/* These types must be 8-bit integer */
+typedef char CHAR;
+typedef unsigned char UCHAR;
+typedef unsigned char BYTE;
+
+/* These types must be 16-bit integer */
+typedef short SHORT;
+typedef unsigned short USHORT;
+typedef unsigned short WORD;
+typedef unsigned short WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long LONG;
+typedef unsigned long ULONG;
+typedef unsigned long DWORD;
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATDirHandle.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATDirHandle.cpp
new file mode 100644
index 000000000..60a4e7b2b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATDirHandle.cpp
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include <string.h>
+#include "ff.h"
+#include "FATDirHandle.h"
+
+using namespace mbed;
+
+FATDirHandle::FATDirHandle(const FATFS_DIR &the_dir) {
+ dir = the_dir;
+}
+
+int FATDirHandle::closedir() {
+ delete this;
+ return 0;
+}
+
+struct dirent *FATDirHandle::readdir() {
+ FILINFO finfo;
+
+#if _USE_LFN
+ finfo.lfname = cur_entry.d_name;
+ finfo.lfsize = sizeof(cur_entry.d_name);
+#endif // _USE_LFN
+
+ FRESULT res = f_readdir(&dir, &finfo);
+
+#if _USE_LFN
+ if(res != 0 || finfo.fname[0]==0) {
+ return NULL;
+ } else {
+ if(cur_entry.d_name[0]==0) {
+ // No long filename so use short filename.
+ memcpy(cur_entry.d_name, finfo.fname, sizeof(finfo.fname));
+ }
+ return &cur_entry;
+ }
+#else
+ if(res != 0 || finfo.fname[0]==0) {
+ return NULL;
+ } else {
+ memcpy(cur_entry.d_name, finfo.fname, sizeof(finfo.fname));
+ return &cur_entry;
+ }
+#endif /* _USE_LFN */
+}
+
+void FATDirHandle::rewinddir() {
+ dir.index = 0;
+}
+
+off_t FATDirHandle::telldir() {
+ return dir.index;
+}
+
+void FATDirHandle::seekdir(off_t location) {
+ dir.index = location;
+}
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATDirHandle.h b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATDirHandle.h
new file mode 100644
index 000000000..25ececacf
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATDirHandle.h
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_FATDIRHANDLE_H
+#define MBED_FATDIRHANDLE_H
+
+#include "DirHandle.h"
+
+using namespace mbed;
+
+class FATDirHandle : public DirHandle {
+
+ public:
+ FATDirHandle(const FATFS_DIR &the_dir);
+ virtual int closedir();
+ virtual struct dirent *readdir();
+ virtual void rewinddir();
+ virtual off_t telldir();
+ virtual void seekdir(off_t location);
+
+ private:
+ FATFS_DIR dir;
+ struct dirent cur_entry;
+
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileHandle.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileHandle.cpp
new file mode 100644
index 000000000..8c2bf881e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileHandle.cpp
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "ff.h"
+#include "ffconf.h"
+#include "mbed_debug.h"
+
+#include "FATFileHandle.h"
+
+FATFileHandle::FATFileHandle(FIL fh) {
+ _fh = fh;
+}
+
+int FATFileHandle::close() {
+ int retval = f_close(&_fh);
+ delete this;
+ return retval;
+}
+
+ssize_t FATFileHandle::write(const void* buffer, size_t length) {
+ UINT n;
+ FRESULT res = f_write(&_fh, buffer, length, &n);
+ if (res) {
+ debug_if(FFS_DBG, "f_write() failed: %d", res);
+ return -1;
+ }
+ return n;
+}
+
+ssize_t FATFileHandle::read(void* buffer, size_t length) {
+ debug_if(FFS_DBG, "read(%d)\n", length);
+ UINT n;
+ FRESULT res = f_read(&_fh, buffer, length, &n);
+ if (res) {
+ debug_if(FFS_DBG, "f_read() failed: %d\n", res);
+ return -1;
+ }
+ return n;
+}
+
+int FATFileHandle::isatty() {
+ return 0;
+}
+
+off_t FATFileHandle::lseek(off_t position, int whence) {
+ if (whence == SEEK_END) {
+ position += _fh.fsize;
+ } else if(whence==SEEK_CUR) {
+ position += _fh.fptr;
+ }
+ FRESULT res = f_lseek(&_fh, position);
+ if (res) {
+ debug_if(FFS_DBG, "lseek failed: %d\n", res);
+ return -1;
+ } else {
+ debug_if(FFS_DBG, "lseek OK, returning %i\n", _fh.fptr);
+ return _fh.fptr;
+ }
+}
+
+int FATFileHandle::fsync() {
+ FRESULT res = f_sync(&_fh);
+ if (res) {
+ debug_if(FFS_DBG, "f_sync() failed: %d\n", res);
+ return -1;
+ }
+ return 0;
+}
+
+off_t FATFileHandle::flen() {
+ return _fh.fsize;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileHandle.h b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileHandle.h
new file mode 100644
index 000000000..d41592f9c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileHandle.h
@@ -0,0 +1,47 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_FATFILEHANDLE_H
+#define MBED_FATFILEHANDLE_H
+
+#include "FileHandle.h"
+
+using namespace mbed;
+
+class FATFileHandle : public FileHandle {
+public:
+
+ FATFileHandle(FIL fh);
+ virtual int close();
+ virtual ssize_t write(const void* buffer, size_t length);
+ virtual ssize_t read(void* buffer, size_t length);
+ virtual int isatty();
+ virtual off_t lseek(off_t position, int whence);
+ virtual int fsync();
+ virtual off_t flen();
+
+protected:
+
+ FIL _fh;
+
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileSystem.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileSystem.cpp
new file mode 100644
index 000000000..da7e8e086
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileSystem.cpp
@@ -0,0 +1,153 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "mbed.h"
+
+#include "ffconf.h"
+#include "mbed_debug.h"
+
+#include "FATFileSystem.h"
+#include "FATFileHandle.h"
+#include "FATDirHandle.h"
+
+DWORD get_fattime(void) {
+ time_t rawtime;
+ time(&rawtime);
+ struct tm *ptm = localtime(&rawtime);
+ return (DWORD)(ptm->tm_year - 80) << 25
+ | (DWORD)(ptm->tm_mon + 1 ) << 21
+ | (DWORD)(ptm->tm_mday ) << 16
+ | (DWORD)(ptm->tm_hour ) << 11
+ | (DWORD)(ptm->tm_min ) << 5
+ | (DWORD)(ptm->tm_sec/2 );
+}
+
+FATFileSystem *FATFileSystem::_ffs[_VOLUMES] = {0};
+
+FATFileSystem::FATFileSystem(const char* n) : FileSystemLike(n) {
+ debug_if(FFS_DBG, "FATFileSystem(%s)\n", n);
+ for(int i=0; i<_VOLUMES; i++) {
+ if(_ffs[i] == 0) {
+ _ffs[i] = this;
+ _fsid = i;
+ debug_if(FFS_DBG, "Mounting [%s] on ffs drive [%d]\n", _name, _fsid);
+ f_mount(i, &_fs);
+ return;
+ }
+ }
+ error("Couldn't create %s in FATFileSystem::FATFileSystem\n", n);
+}
+
+FATFileSystem::~FATFileSystem() {
+ for (int i=0; i<_VOLUMES; i++) {
+ if (_ffs[i] == this) {
+ _ffs[i] = 0;
+ f_mount(i, NULL);
+ }
+ }
+}
+
+FileHandle *FATFileSystem::open(const char* name, int flags) {
+ debug_if(FFS_DBG, "open(%s) on filesystem [%s], drv [%d]\n", name, _name, _fsid);
+ char n[64];
+ sprintf(n, "%d:/%s", _fsid, name);
+
+ /* POSIX flags -> FatFS open mode */
+ BYTE openmode;
+ if (flags & O_RDWR) {
+ openmode = FA_READ|FA_WRITE;
+ } else if(flags & O_WRONLY) {
+ openmode = FA_WRITE;
+ } else {
+ openmode = FA_READ;
+ }
+ if(flags & O_CREAT) {
+ if(flags & O_TRUNC) {
+ openmode |= FA_CREATE_ALWAYS;
+ } else {
+ openmode |= FA_OPEN_ALWAYS;
+ }
+ }
+
+ FIL fh;
+ FRESULT res = f_open(&fh, n, openmode);
+ if (res) {
+ debug_if(FFS_DBG, "f_open('w') failed: %d\n", res);
+ return NULL;
+ }
+ if (flags & O_APPEND) {
+ f_lseek(&fh, fh.fsize);
+ }
+ return new FATFileHandle(fh);
+}
+
+int FATFileSystem::remove(const char *filename) {
+ FRESULT res = f_unlink(filename);
+ if (res) {
+ debug_if(FFS_DBG, "f_unlink() failed: %d\n", res);
+ return -1;
+ }
+ return 0;
+}
+
+int FATFileSystem::rename(const char *oldname, const char *newname) {
+ FRESULT res = f_rename(oldname, newname);
+ if (res) {
+ debug_if(FFS_DBG, "f_rename() failed: %d\n", res);
+ return -1;
+ }
+ return 0;
+}
+
+int FATFileSystem::format() {
+ FRESULT res = f_mkfs(_fsid, 0, 512); // Logical drive number, Partitioning rule, Allocation unit size (bytes per cluster)
+ if (res) {
+ debug_if(FFS_DBG, "f_mkfs() failed: %d\n", res);
+ return -1;
+ }
+ return 0;
+}
+
+DirHandle *FATFileSystem::opendir(const char *name) {
+ FATFS_DIR dir;
+ FRESULT res = f_opendir(&dir, name);
+ if (res != 0) {
+ return NULL;
+ }
+ return new FATDirHandle(dir);
+}
+
+int FATFileSystem::mkdir(const char *name, mode_t mode) {
+ FRESULT res = f_mkdir(name);
+ return res == 0 ? 0 : -1;
+}
+
+int FATFileSystem::mount() {
+ FRESULT res = f_mount(_fsid, &_fs);
+ return res == 0 ? 0 : -1;
+}
+
+int FATFileSystem::unmount() {
+ if (disk_sync())
+ return -1;
+ FRESULT res = f_mount(_fsid, NULL);
+ return res == 0 ? 0 : -1;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileSystem.h b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileSystem.h
new file mode 100644
index 000000000..ff137fed9
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/FATFileSystem.h
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_FATFILESYSTEM_H
+#define MBED_FATFILESYSTEM_H
+
+#include "FileSystemLike.h"
+#include "FileHandle.h"
+#include "ff.h"
+#include <stdint.h>
+
+using namespace mbed;
+
+/**
+ * FATFileSystem based on ChaN's Fat Filesystem library v0.8
+ */
+class FATFileSystem : public FileSystemLike {
+public:
+
+ FATFileSystem(const char* n);
+ virtual ~FATFileSystem();
+
+ static FATFileSystem * _ffs[_VOLUMES]; // FATFileSystem objects, as parallel to FatFs drives array
+ FATFS _fs; // Work area (file system object) for logical drive
+ int _fsid;
+
+ /**
+ * Opens a file on the filesystem
+ */
+ virtual FileHandle *open(const char* name, int flags);
+
+ /**
+ * Removes a file path
+ */
+ virtual int remove(const char *filename);
+
+ /**
+ * Renames a file
+ */
+ virtual int rename(const char *oldname, const char *newname);
+
+ /**
+ * Formats a logical drive, FDISK artitioning rule, 512 bytes per cluster
+ */
+ virtual int format();
+
+ /**
+ * Opens a directory on the filesystem
+ */
+ virtual DirHandle *opendir(const char *name);
+
+ /**
+ * Creates a directory path
+ */
+ virtual int mkdir(const char *name, mode_t mode);
+
+ /**
+ * Mounts the filesystem
+ */
+ virtual int mount();
+
+ /**
+ * Unmounts the filesystem
+ */
+ virtual int unmount();
+
+ virtual int disk_initialize() { return 0; }
+ virtual int disk_status() { return 0; }
+ virtual int disk_read(uint8_t * buffer, uint64_t sector, uint8_t count) = 0;
+ virtual int disk_write(const uint8_t * buffer, uint64_t sector, uint8_t count) = 0;
+ virtual int disk_sync() { return 0; }
+ virtual uint64_t disk_sectors() = 0;
+
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/MemFileSystem.h b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/MemFileSystem.h
new file mode 100644
index 000000000..0bb415ebc
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/fat/MemFileSystem.h
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library - MemFileSystem
+ * Copyright (c) 2008, sford
+ */
+
+
+#ifndef MBED_MEMFILESYSTEM_H
+#define MBED_MEMFILESYSTEM_H
+
+#include "FATFileSystem.h"
+
+namespace mbed
+{
+
+ class MemFileSystem : public FATFileSystem
+ {
+ public:
+
+ // 2000 sectors, each 512 bytes (malloced as required)
+ char *sectors[2000];
+
+ MemFileSystem(const char* name) : FATFileSystem(name) {
+ memset(sectors, 0, sizeof(sectors));
+ }
+
+ virtual ~MemFileSystem() {
+ for(int i = 0; i < 2000; i++) {
+ if(sectors[i]) {
+ free(sectors[i]);
+ }
+ }
+ }
+
+ // read a sector in to the buffer, return 0 if ok
+ virtual int disk_read(char *buffer, int sector) {
+ if(sectors[sector] == 0) {
+ // nothing allocated means sector is empty
+ memset(buffer, 0, 512);
+ } else {
+ memcpy(buffer, sectors[sector], 512);
+ }
+ return 0;
+ }
+
+ // write a sector from the buffer, return 0 if ok
+ virtual int disk_write(const char *buffer, int sector) {
+ // if buffer is zero deallocate sector
+ char zero[512];
+ memset(zero, 0, 512);
+ if(memcmp(zero, buffer, 512)==0) {
+ if(sectors[sector] != 0) {
+ free(sectors[sector]);
+ sectors[sector] = 0;
+ }
+ return 0;
+ }
+ // else allocate a sector if needed, and write
+ if(sectors[sector] == 0) {
+ char *sec = (char*)malloc(512);
+ if(sec==0) {
+ return 1; // out of memory
+ }
+ sectors[sector] = sec;
+ }
+ memcpy(sectors[sector], buffer, 512);
+ return 0;
+ }
+
+ // return the number of sectors
+ virtual int disk_sectors() {
+ return sizeof(sectors)/sizeof(sectors[0]);
+ }
+
+ };
+
+}
+
+#endif \ No newline at end of file
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/sd/SDFileSystem.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/sd/SDFileSystem.cpp
new file mode 100644
index 000000000..054035553
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/sd/SDFileSystem.cpp
@@ -0,0 +1,498 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+/* Introduction
+ * ------------
+ * SD and MMC cards support a number of interfaces, but common to them all
+ * is one based on SPI. This is the one I'm implmenting because it means
+ * it is much more portable even though not so performant, and we already
+ * have the mbed SPI Interface!
+ *
+ * The main reference I'm using is Chapter 7, "SPI Mode" of:
+ * http://www.sdcard.org/developers/tech/sdcard/pls/Simplified_Physical_Layer_Spec.pdf
+ *
+ * SPI Startup
+ * -----------
+ * The SD card powers up in SD mode. The SPI interface mode is selected by
+ * asserting CS low and sending the reset command (CMD0). The card will
+ * respond with a (R1) response.
+ *
+ * CMD8 is optionally sent to determine the voltage range supported, and
+ * indirectly determine whether it is a version 1.x SD/non-SD card or
+ * version 2.x. I'll just ignore this for now.
+ *
+ * ACMD41 is repeatedly issued to initialise the card, until "in idle"
+ * (bit 0) of the R1 response goes to '0', indicating it is initialised.
+ *
+ * You should also indicate whether the host supports High Capicity cards,
+ * and check whether the card is high capacity - i'll also ignore this
+ *
+ * SPI Protocol
+ * ------------
+ * The SD SPI protocol is based on transactions made up of 8-bit words, with
+ * the host starting every bus transaction by asserting the CS signal low. The
+ * card always responds to commands, data blocks and errors.
+ *
+ * The protocol supports a CRC, but by default it is off (except for the
+ * first reset CMD0, where the CRC can just be pre-calculated, and CMD8)
+ * I'll leave the CRC off I think!
+ *
+ * Standard capacity cards have variable data block sizes, whereas High
+ * Capacity cards fix the size of data block to 512 bytes. I'll therefore
+ * just always use the Standard Capacity cards with a block size of 512 bytes.
+ * This is set with CMD16.
+ *
+ * You can read and write single blocks (CMD17, CMD25) or multiple blocks
+ * (CMD18, CMD25). For simplicity, I'll just use single block accesses. When
+ * the card gets a read command, it responds with a response token, and then
+ * a data token or an error.
+ *
+ * SPI Command Format
+ * ------------------
+ * Commands are 6-bytes long, containing the command, 32-bit argument, and CRC.
+ *
+ * +---------------+------------+------------+-----------+----------+--------------+
+ * | 01 | cmd[5:0] | arg[31:24] | arg[23:16] | arg[15:8] | arg[7:0] | crc[6:0] | 1 |
+ * +---------------+------------+------------+-----------+----------+--------------+
+ *
+ * As I'm not using CRC, I can fix that byte to what is needed for CMD0 (0x95)
+ *
+ * All Application Specific commands shall be preceded with APP_CMD (CMD55).
+ *
+ * SPI Response Format
+ * -------------------
+ * The main response format (R1) is a status byte (normally zero). Key flags:
+ * idle - 1 if the card is in an idle state/initialising
+ * cmd - 1 if an illegal command code was detected
+ *
+ * +-------------------------------------------------+
+ * R1 | 0 | arg | addr | seq | crc | cmd | erase | idle |
+ * +-------------------------------------------------+
+ *
+ * R1b is the same, except it is followed by a busy signal (zeros) until
+ * the first non-zero byte when it is ready again.
+ *
+ * Data Response Token
+ * -------------------
+ * Every data block written to the card is acknowledged by a byte
+ * response token
+ *
+ * +----------------------+
+ * | xxx | 0 | status | 1 |
+ * +----------------------+
+ * 010 - OK!
+ * 101 - CRC Error
+ * 110 - Write Error
+ *
+ * Single Block Read and Write
+ * ---------------------------
+ *
+ * Block transfers have a byte header, followed by the data, followed
+ * by a 16-bit CRC. In our case, the data will always be 512 bytes.
+ *
+ * +------+---------+---------+- - - -+---------+-----------+----------+
+ * | 0xFE | data[0] | data[1] | | data[n] | crc[15:8] | crc[7:0] |
+ * +------+---------+---------+- - - -+---------+-----------+----------+
+ */
+#include "SDFileSystem.h"
+#include "mbed_debug.h"
+
+#define SD_COMMAND_TIMEOUT 5000
+
+#define SD_DBG 0
+
+SDFileSystem::SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name) :
+ FATFileSystem(name), _spi(mosi, miso, sclk), _cs(cs), _is_initialized(0) {
+ _cs = 1;
+
+ // Set default to 100kHz for initialisation and 1MHz for data transfer
+ _init_sck = 100000;
+ _transfer_sck = 1000000;
+}
+
+#define R1_IDLE_STATE (1 << 0)
+#define R1_ERASE_RESET (1 << 1)
+#define R1_ILLEGAL_COMMAND (1 << 2)
+#define R1_COM_CRC_ERROR (1 << 3)
+#define R1_ERASE_SEQUENCE_ERROR (1 << 4)
+#define R1_ADDRESS_ERROR (1 << 5)
+#define R1_PARAMETER_ERROR (1 << 6)
+
+// Types
+// - v1.x Standard Capacity
+// - v2.x Standard Capacity
+// - v2.x High Capacity
+// - Not recognised as an SD Card
+#define SDCARD_FAIL 0
+#define SDCARD_V1 1
+#define SDCARD_V2 2
+#define SDCARD_V2HC 3
+
+int SDFileSystem::initialise_card() {
+ // Set to SCK for initialisation, and clock card with cs = 1
+ _spi.frequency(_init_sck);
+ _cs = 1;
+ for (int i = 0; i < 16; i++) {
+ _spi.write(0xFF);
+ }
+
+ // send CMD0, should return with all zeros except IDLE STATE set (bit 0)
+ if (_cmd(0, 0) != R1_IDLE_STATE) {
+ debug("No disk, or could not put SD card in to SPI idle state\n");
+ return SDCARD_FAIL;
+ }
+
+ // send CMD8 to determine whther it is ver 2.x
+ int r = _cmd8();
+ if (r == R1_IDLE_STATE) {
+ return initialise_card_v2();
+ } else if (r == (R1_IDLE_STATE | R1_ILLEGAL_COMMAND)) {
+ return initialise_card_v1();
+ } else {
+ debug("Not in idle state after sending CMD8 (not an SD card?)\n");
+ return SDCARD_FAIL;
+ }
+}
+
+int SDFileSystem::initialise_card_v1() {
+ for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+ _cmd(55, 0);
+ if (_cmd(41, 0) == 0) {
+ cdv = 512;
+ debug_if(SD_DBG, "\n\rInit: SEDCARD_V1\n\r");
+ return SDCARD_V1;
+ }
+ }
+
+ debug("Timeout waiting for v1.x card\n");
+ return SDCARD_FAIL;
+}
+
+int SDFileSystem::initialise_card_v2() {
+ for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+ wait_ms(50);
+ _cmd58();
+ _cmd(55, 0);
+ if (_cmd(41, 0x40000000) == 0) {
+ _cmd58();
+ debug_if(SD_DBG, "\n\rInit: SDCARD_V2\n\r");
+ cdv = 1;
+ return SDCARD_V2;
+ }
+ }
+
+ debug("Timeout waiting for v2.x card\n");
+ return SDCARD_FAIL;
+}
+
+int SDFileSystem::disk_initialize() {
+ _is_initialized = initialise_card();
+ if (_is_initialized == 0) {
+ debug("Fail to initialize card\n");
+ return 1;
+ }
+ debug_if(SD_DBG, "init card = %d\n", _is_initialized);
+ _sectors = _sd_sectors();
+
+ // Set block length to 512 (CMD16)
+ if (_cmd(16, 512) != 0) {
+ debug("Set 512-byte block timed out\n");
+ return 1;
+ }
+
+ // Set SCK for data transfer
+ _spi.frequency(_transfer_sck);
+ return 0;
+}
+
+int SDFileSystem::disk_write(const uint8_t* buffer, uint64_t block_number, uint8_t count) {
+ if (!_is_initialized) {
+ return -1;
+ }
+
+ for (uint64_t b = block_number; b < block_number + count; b++) {
+ // set write address for single block (CMD24)
+ if (_cmd(24, b * cdv) != 0) {
+ return 1;
+ }
+
+ // send the data block
+ _write(buffer, 512);
+ buffer += 512;
+ }
+
+ return 0;
+}
+
+int SDFileSystem::disk_read(uint8_t* buffer, uint64_t block_number, uint8_t count) {
+ if (!_is_initialized) {
+ return -1;
+ }
+
+ for (uint64_t b = block_number; b < block_number + count; b++) {
+ // set read address for single block (CMD17)
+ if (_cmd(17, b * cdv) != 0) {
+ return 1;
+ }
+
+ // receive the data
+ _read(buffer, 512);
+ buffer += 512;
+ }
+
+ return 0;
+}
+
+int SDFileSystem::disk_status() {
+ // FATFileSystem::disk_status() returns 0 when initialized
+ if (_is_initialized) {
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
+int SDFileSystem::disk_sync() { return 0; }
+uint64_t SDFileSystem::disk_sectors() { return _sectors; }
+
+
+// PRIVATE FUNCTIONS
+int SDFileSystem::_cmd(int cmd, int arg) {
+ _cs = 0;
+
+ // send a command
+ _spi.write(0x40 | cmd);
+ _spi.write(arg >> 24);
+ _spi.write(arg >> 16);
+ _spi.write(arg >> 8);
+ _spi.write(arg >> 0);
+ _spi.write(0x95);
+
+ // wait for the repsonse (response[7] == 0)
+ for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+ int response = _spi.write(0xFF);
+ if (!(response & 0x80)) {
+ _cs = 1;
+ _spi.write(0xFF);
+ return response;
+ }
+ }
+ _cs = 1;
+ _spi.write(0xFF);
+ return -1; // timeout
+}
+int SDFileSystem::_cmdx(int cmd, int arg) {
+ _cs = 0;
+
+ // send a command
+ _spi.write(0x40 | cmd);
+ _spi.write(arg >> 24);
+ _spi.write(arg >> 16);
+ _spi.write(arg >> 8);
+ _spi.write(arg >> 0);
+ _spi.write(0x95);
+
+ // wait for the repsonse (response[7] == 0)
+ for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+ int response = _spi.write(0xFF);
+ if (!(response & 0x80)) {
+ return response;
+ }
+ }
+ _cs = 1;
+ _spi.write(0xFF);
+ return -1; // timeout
+}
+
+
+int SDFileSystem::_cmd58() {
+ _cs = 0;
+ int arg = 0;
+
+ // send a command
+ _spi.write(0x40 | 58);
+ _spi.write(arg >> 24);
+ _spi.write(arg >> 16);
+ _spi.write(arg >> 8);
+ _spi.write(arg >> 0);
+ _spi.write(0x95);
+
+ // wait for the repsonse (response[7] == 0)
+ for (int i = 0; i < SD_COMMAND_TIMEOUT; i++) {
+ int response = _spi.write(0xFF);
+ if (!(response & 0x80)) {
+ int ocr = _spi.write(0xFF) << 24;
+ ocr |= _spi.write(0xFF) << 16;
+ ocr |= _spi.write(0xFF) << 8;
+ ocr |= _spi.write(0xFF) << 0;
+ _cs = 1;
+ _spi.write(0xFF);
+ return response;
+ }
+ }
+ _cs = 1;
+ _spi.write(0xFF);
+ return -1; // timeout
+}
+
+int SDFileSystem::_cmd8() {
+ _cs = 0;
+
+ // send a command
+ _spi.write(0x40 | 8); // CMD8
+ _spi.write(0x00); // reserved
+ _spi.write(0x00); // reserved
+ _spi.write(0x01); // 3.3v
+ _spi.write(0xAA); // check pattern
+ _spi.write(0x87); // crc
+
+ // wait for the repsonse (response[7] == 0)
+ for (int i = 0; i < SD_COMMAND_TIMEOUT * 1000; i++) {
+ char response[5];
+ response[0] = _spi.write(0xFF);
+ if (!(response[0] & 0x80)) {
+ for (int j = 1; j < 5; j++) {
+ response[i] = _spi.write(0xFF);
+ }
+ _cs = 1;
+ _spi.write(0xFF);
+ return response[0];
+ }
+ }
+ _cs = 1;
+ _spi.write(0xFF);
+ return -1; // timeout
+}
+
+int SDFileSystem::_read(uint8_t *buffer, uint32_t length) {
+ _cs = 0;
+
+ // read until start byte (0xFF)
+ while (_spi.write(0xFF) != 0xFE);
+
+ // read data
+ for (uint32_t i = 0; i < length; i++) {
+ buffer[i] = _spi.write(0xFF);
+ }
+ _spi.write(0xFF); // checksum
+ _spi.write(0xFF);
+
+ _cs = 1;
+ _spi.write(0xFF);
+ return 0;
+}
+
+int SDFileSystem::_write(const uint8_t*buffer, uint32_t length) {
+ _cs = 0;
+
+ // indicate start of block
+ _spi.write(0xFE);
+
+ // write the data
+ for (uint32_t i = 0; i < length; i++) {
+ _spi.write(buffer[i]);
+ }
+
+ // write the checksum
+ _spi.write(0xFF);
+ _spi.write(0xFF);
+
+ // check the response token
+ if ((_spi.write(0xFF) & 0x1F) != 0x05) {
+ _cs = 1;
+ _spi.write(0xFF);
+ return 1;
+ }
+
+ // wait for write to finish
+ while (_spi.write(0xFF) == 0);
+
+ _cs = 1;
+ _spi.write(0xFF);
+ return 0;
+}
+
+static uint32_t ext_bits(unsigned char *data, int msb, int lsb) {
+ uint32_t bits = 0;
+ uint32_t size = 1 + msb - lsb;
+ for (uint32_t i = 0; i < size; i++) {
+ uint32_t position = lsb + i;
+ uint32_t byte = 15 - (position >> 3);
+ uint32_t bit = position & 0x7;
+ uint32_t value = (data[byte] >> bit) & 1;
+ bits |= value << i;
+ }
+ return bits;
+}
+
+uint64_t SDFileSystem::_sd_sectors() {
+ uint32_t c_size, c_size_mult, read_bl_len;
+ uint32_t block_len, mult, blocknr, capacity;
+ uint32_t hc_c_size;
+ uint64_t blocks;
+
+ // CMD9, Response R2 (R1 byte + 16-byte block read)
+ if (_cmdx(9, 0) != 0) {
+ debug("Didn't get a response from the disk\n");
+ return 0;
+ }
+
+ uint8_t csd[16];
+ if (_read(csd, 16) != 0) {
+ debug("Couldn't read csd response from disk\n");
+ return 0;
+ }
+
+ // csd_structure : csd[127:126]
+ // c_size : csd[73:62]
+ // c_size_mult : csd[49:47]
+ // read_bl_len : csd[83:80] - the *maximum* read block length
+
+ int csd_structure = ext_bits(csd, 127, 126);
+
+ switch (csd_structure) {
+ case 0:
+ cdv = 512;
+ c_size = ext_bits(csd, 73, 62);
+ c_size_mult = ext_bits(csd, 49, 47);
+ read_bl_len = ext_bits(csd, 83, 80);
+
+ block_len = 1 << read_bl_len;
+ mult = 1 << (c_size_mult + 2);
+ blocknr = (c_size + 1) * mult;
+ capacity = blocknr * block_len;
+ blocks = capacity / 512;
+ debug_if(SD_DBG, "\n\rSDCard\n\rc_size: %d \n\rcapacity: %ld \n\rsectors: %lld\n\r", c_size, capacity, blocks);
+ break;
+
+ case 1:
+ cdv = 1;
+ hc_c_size = ext_bits(csd, 63, 48);
+ blocks = (hc_c_size+1)*1024;
+ debug_if(SD_DBG, "\n\rSDHC Card \n\rhc_c_size: %d\n\rcapacity: %lld \n\rsectors: %lld\n\r", hc_c_size, blocks*512, blocks);
+ break;
+
+ default:
+ debug("CSD struct unsupported\r\n");
+ return 0;
+ };
+ return blocks;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/fs/sd/SDFileSystem.h b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/sd/SDFileSystem.h
new file mode 100644
index 000000000..73aba494d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/fs/sd/SDFileSystem.h
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2012 ARM Limited
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef MBED_SDFILESYSTEM_H
+#define MBED_SDFILESYSTEM_H
+
+#include "mbed.h"
+#include "FATFileSystem.h"
+#include <stdint.h>
+
+/** Access the filesystem on an SD Card using SPI
+ *
+ * @code
+ * #include "mbed.h"
+ * #include "SDFileSystem.h"
+ *
+ * SDFileSystem sd(p5, p6, p7, p12, "sd"); // mosi, miso, sclk, cs
+ *
+ * int main() {
+ * FILE *fp = fopen("/sd/myfile.txt", "w");
+ * fprintf(fp, "Hello World!\n");
+ * fclose(fp);
+ * }
+ */
+class SDFileSystem : public FATFileSystem {
+public:
+
+ /** Create the File System for accessing an SD Card using SPI
+ *
+ * @param mosi SPI mosi pin connected to SD Card
+ * @param miso SPI miso pin conencted to SD Card
+ * @param sclk SPI sclk pin connected to SD Card
+ * @param cs DigitalOut pin used as SD Card chip select
+ * @param name The name used to access the virtual filesystem
+ */
+ SDFileSystem(PinName mosi, PinName miso, PinName sclk, PinName cs, const char* name);
+ virtual int disk_initialize();
+ virtual int disk_status();
+ virtual int disk_read(uint8_t* buffer, uint64_t block_number, uint8_t count);
+ virtual int disk_write(const uint8_t* buffer, uint64_t block_number, uint8_t count);
+ virtual int disk_sync();
+ virtual uint64_t disk_sectors();
+
+protected:
+
+ int _cmd(int cmd, int arg);
+ int _cmdx(int cmd, int arg);
+ int _cmd8();
+ int _cmd58();
+ int initialise_card();
+ int initialise_card_v1();
+ int initialise_card_v2();
+
+ int _read(uint8_t * buffer, uint32_t length);
+ int _write(const uint8_t *buffer, uint32_t length);
+ uint64_t _sd_sectors();
+ uint64_t _sectors;
+
+ void set_init_sck(uint32_t sck) { _init_sck = sck; }
+ // Note: The highest SPI clock rate is 20 MHz for MMC and 25 MHz for SD
+ void set_transfer_sck(uint32_t sck) { _transfer_sck = sck; }
+ uint32_t _init_sck;
+ uint32_t _transfer_sck;
+
+ SPI _spi;
+ DigitalOut _cs;
+ int cdv;
+ int _is_initialized;
+};
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogIn.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogIn.h
new file mode 100644
index 000000000..09437a256
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogIn.h
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_H
+#define MBED_ANALOGIN_H
+
+#include "platform.h"
+
+#if DEVICE_ANALOGIN
+
+#include "analogin_api.h"
+
+namespace mbed {
+
+/** An analog input, used for reading the voltage on a pin
+ *
+ * Example:
+ * @code
+ * // Print messages when the AnalogIn is greater than 50%
+ *
+ * #include "mbed.h"
+ *
+ * AnalogIn temperature(p20);
+ *
+ * int main() {
+ * while(1) {
+ * if(temperature > 0.5) {
+ * printf("Too hot! (%f)", temperature.read());
+ * }
+ * }
+ * }
+ * @endcode
+ */
+class AnalogIn {
+
+public:
+
+ /** Create an AnalogIn, connected to the specified pin
+ *
+ * @param pin AnalogIn pin to connect to
+ * @param name (optional) A string to identify the object
+ */
+ AnalogIn(PinName pin) {
+ analogin_init(&_adc, pin);
+ }
+
+ /** Read the input voltage, represented as a float in the range [0.0, 1.0]
+ *
+ * @returns A floating-point value representing the current input voltage, measured as a percentage
+ */
+ float read() {
+ return analogin_read(&_adc);
+ }
+
+ /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+ *
+ * @returns
+ * 16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
+ */
+ unsigned short read_u16() {
+ return analogin_read_u16(&_adc);
+ }
+
+#ifdef MBED_OPERATORS
+ /** An operator shorthand for read()
+ *
+ * The float() operator can be used as a shorthand for read() to simplify common code sequences
+ *
+ * Example:
+ * @code
+ * float x = volume.read();
+ * float x = volume;
+ *
+ * if(volume.read() > 0.25) { ... }
+ * if(volume > 0.25) { ... }
+ * @endcode
+ */
+ operator float() {
+ return read();
+ }
+#endif
+
+protected:
+ analogin_t _adc;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogOut.h
new file mode 100644
index 000000000..0b879a72b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/AnalogOut.h
@@ -0,0 +1,121 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_H
+#define MBED_ANALOGOUT_H
+
+#include "platform.h"
+
+#if DEVICE_ANALOGOUT
+
+#include "analogout_api.h"
+
+namespace mbed {
+
+/** An analog output, used for setting the voltage on a pin
+ *
+ * Example:
+ * @code
+ * // Make a sawtooth output
+ *
+ * #include "mbed.h"
+ *
+ * AnalogOut tri(p18);
+ * int main() {
+ * while(1) {
+ * tri = tri + 0.01;
+ * wait_us(1);
+ * if(tri == 1) {
+ * tri = 0;
+ * }
+ * }
+ * }
+ * @endcode
+ */
+class AnalogOut {
+
+public:
+
+ /** Create an AnalogOut connected to the specified pin
+ *
+ * @param AnalogOut pin to connect to (18)
+ */
+ AnalogOut(PinName pin) {
+ analogout_init(&_dac, pin);
+ }
+
+ /** Set the output voltage, specified as a percentage (float)
+ *
+ * @param value A floating-point value representing the output voltage,
+ * specified as a percentage. The value should lie between
+ * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+ * Values outside this range will be saturated to 0.0f or 1.0f.
+ */
+ void write(float value) {
+ analogout_write(&_dac, value);
+ }
+
+ /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+ *
+ * @param value 16-bit unsigned short representing the output voltage,
+ * normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
+ */
+ void write_u16(unsigned short value) {
+ analogout_write_u16(&_dac, value);
+ }
+
+ /** Return the current output voltage setting, measured as a percentage (float)
+ *
+ * @returns
+ * A floating-point value representing the current voltage being output on the pin,
+ * measured as a percentage. The returned value will lie between
+ * 0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+ *
+ * @note
+ * This value may not match exactly the value set by a previous write().
+ */
+ float read() {
+ return analogout_read(&_dac);
+ }
+
+#ifdef MBED_OPERATORS
+ /** An operator shorthand for write()
+ */
+ AnalogOut& operator= (float percent) {
+ write(percent);
+ return *this;
+ }
+
+ AnalogOut& operator= (AnalogOut& rhs) {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** An operator shorthand for read()
+ */
+ operator float() {
+ return read();
+ }
+#endif
+
+protected:
+ dac_t _dac;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusIn.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusIn.h
new file mode 100644
index 000000000..d1c9a9cd4
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusIn.h
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSIN_H
+#define MBED_BUSIN_H
+
+#include "platform.h"
+#include "DigitalIn.h"
+
+namespace mbed {
+
+/** A digital input bus, used for reading the state of a collection of pins
+ */
+class BusIn {
+
+public:
+ /* Group: Configuration Methods */
+
+ /** Create an BusIn, connected to the specified pins
+ *
+ * @param <n> DigitalIn pin to connect to bus bit <n> (p5-p30, NC)
+ *
+ * @note
+ * It is only required to specify as many pin variables as is required
+ * for the bus; the rest will default to NC (not connected)
+ */
+ BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+ PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+ PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+ PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+ BusIn(PinName pins[16]);
+
+ virtual ~BusIn();
+
+ /** Read the value of the input bus
+ *
+ * @returns
+ * An integer with each bit corresponding to the value read from the associated DigitalIn pin
+ */
+ int read();
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone
+ */
+ void mode(PinMode pull);
+
+ /** Binary mask of bus pins connected to actual pins (not NC pins)
+ * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+ *
+ * @returns
+ * Binary mask of connected pins
+ */
+ int mask() {
+ return _nc_mask;
+ }
+
+#ifdef MBED_OPERATORS
+ /** A shorthand for read()
+ */
+ operator int();
+
+ /** Access to particular bit in random-iterator fashion
+ */
+ DigitalIn & operator[] (int index);
+#endif
+
+protected:
+ DigitalIn* _pin[16];
+
+ /** Mask of bus's NC pins
+ * If bit[n] is set to 1 - pin is connected
+ * if bit[n] is cleared - pin is not connected (NC)
+ */
+ int _nc_mask;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ BusIn(const BusIn&);
+ BusIn & operator = (const BusIn&);
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusInOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusInOut.h
new file mode 100644
index 000000000..54328fb02
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusInOut.h
@@ -0,0 +1,117 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSINOUT_H
+#define MBED_BUSINOUT_H
+
+#include "DigitalInOut.h"
+
+namespace mbed {
+
+/** A digital input output bus, used for setting the state of a collection of pins
+ */
+class BusInOut {
+
+public:
+
+ /** Create an BusInOut, connected to the specified pins
+ *
+ * @param p<n> DigitalInOut pin to connect to bus bit p<n> (p5-p30, NC)
+ *
+ * @note
+ * It is only required to specify as many pin variables as is required
+ * for the bus; the rest will default to NC (not connected)
+ */
+ BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+ PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+ PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+ PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+ BusInOut(PinName pins[16]);
+
+ virtual ~BusInOut();
+
+ /* Group: Access Methods */
+
+ /** Write the value to the output bus
+ *
+ * @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
+ */
+ void write(int value);
+
+ /** Read the value currently output on the bus
+ *
+ * @returns
+ * An integer with each bit corresponding to associated DigitalInOut pin setting
+ */
+ int read();
+
+ /** Set as an output
+ */
+ void output();
+
+ /** Set as an input
+ */
+ void input();
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone
+ */
+ void mode(PinMode pull);
+
+ /** Binary mask of bus pins connected to actual pins (not NC pins)
+ * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+ *
+ * @returns
+ * Binary mask of connected pins
+ */
+ int mask() {
+ return _nc_mask;
+ }
+
+#ifdef MBED_OPERATORS
+ /** A shorthand for write()
+ */
+ BusInOut& operator= (int v);
+ BusInOut& operator= (BusInOut& rhs);
+
+ /** Access to particular bit in random-iterator fashion
+ */
+ DigitalInOut& operator[] (int index);
+
+ /** A shorthand for read()
+ */
+ operator int();
+#endif
+
+protected:
+ DigitalInOut* _pin[16];
+
+ /** Mask of bus's NC pins
+ * If bit[n] is set to 1 - pin is connected
+ * if bit[n] is cleared - pin is not connected (NC)
+ */
+ int _nc_mask;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ BusInOut(const BusInOut&);
+ BusInOut & operator = (const BusInOut&);
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusOut.h
new file mode 100644
index 000000000..1c55be07e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/BusOut.h
@@ -0,0 +1,101 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSOUT_H
+#define MBED_BUSOUT_H
+
+#include "DigitalOut.h"
+
+namespace mbed {
+
+/** A digital output bus, used for setting the state of a collection of pins
+ */
+class BusOut {
+
+public:
+
+ /** Create an BusOut, connected to the specified pins
+ *
+ * @param p<n> DigitalOut pin to connect to bus bit <n> (p5-p30, NC)
+ *
+ * @note
+ * It is only required to specify as many pin variables as is required
+ * for the bus; the rest will default to NC (not connected)
+ */
+ BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+ PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+ PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+ PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+ BusOut(PinName pins[16]);
+
+ virtual ~BusOut();
+
+ /** Write the value to the output bus
+ *
+ * @param value An integer specifying a bit to write for every corresponding DigitalOut pin
+ */
+ void write(int value);
+
+ /** Read the value currently output on the bus
+ *
+ * @returns
+ * An integer with each bit corresponding to associated DigitalOut pin setting
+ */
+ int read();
+
+ /** Binary mask of bus pins connected to actual pins (not NC pins)
+ * If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+ *
+ * @returns
+ * Binary mask of connected pins
+ */
+ int mask() {
+ return _nc_mask;
+ }
+
+#ifdef MBED_OPERATORS
+ /** A shorthand for write()
+ */
+ BusOut& operator= (int v);
+ BusOut& operator= (BusOut& rhs);
+
+ /** Access to particular bit in random-iterator fashion
+ */
+ DigitalOut& operator[] (int index);
+
+ /** A shorthand for read()
+ */
+ operator int();
+#endif
+
+protected:
+ DigitalOut* _pin[16];
+
+ /** Mask of bus's NC pins
+ * If bit[n] is set to 1 - pin is connected
+ * if bit[n] is cleared - pin is not connected (NC)
+ */
+ int _nc_mask;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ BusOut(const BusOut&);
+ BusOut & operator = (const BusOut&);
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/CAN.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/CAN.h
new file mode 100644
index 000000000..db613f661
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/CAN.h
@@ -0,0 +1,243 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_H
+#define MBED_CAN_H
+
+#include "platform.h"
+
+#if DEVICE_CAN
+
+#include "can_api.h"
+#include "can_helper.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** CANMessage class
+ */
+class CANMessage : public CAN_Message {
+
+public:
+ /** Creates empty CAN message.
+ */
+ CANMessage() : CAN_Message() {
+ len = 8;
+ type = CANData;
+ format = CANStandard;
+ id = 0;
+ memset(data, 0, 8);
+ }
+
+ /** Creates CAN message with specific content.
+ */
+ CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
+ len = _len & 0xF;
+ type = _type;
+ format = _format;
+ id = _id;
+ memcpy(data, _data, _len);
+ }
+
+ /** Creates CAN remote message.
+ */
+ CANMessage(int _id, CANFormat _format = CANStandard) {
+ len = 0;
+ type = CANRemote;
+ format = _format;
+ id = _id;
+ memset(data, 0, 8);
+ }
+};
+
+/** A can bus client, used for communicating with can devices
+ */
+class CAN {
+
+public:
+ /** Creates an CAN interface connected to specific pins.
+ *
+ * @param rd read from transmitter
+ * @param td transmit to transmitter
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * Ticker ticker;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ * CAN can1(p9, p10);
+ * CAN can2(p30, p29);
+ *
+ * char counter = 0;
+ *
+ * void send() {
+ * if(can1.write(CANMessage(1337, &counter, 1))) {
+ * printf("Message sent: %d\n", counter);
+ * counter++;
+ * }
+ * led1 = !led1;
+ * }
+ *
+ * int main() {
+ * ticker.attach(&send, 1);
+ * CANMessage msg;
+ * while(1) {
+ * if(can2.read(msg)) {
+ * printf("Message received: %d\n\n", msg.data[0]);
+ * led2 = !led2;
+ * }
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ */
+ CAN(PinName rd, PinName td);
+ virtual ~CAN();
+
+ /** Set the frequency of the CAN interface
+ *
+ * @param hz The bus frequency in hertz
+ *
+ * @returns
+ * 1 if successful,
+ * 0 otherwise
+ */
+ int frequency(int hz);
+
+ /** Write a CANMessage to the bus.
+ *
+ * @param msg The CANMessage to write.
+ *
+ * @returns
+ * 0 if write failed,
+ * 1 if write was successful
+ */
+ int write(CANMessage msg);
+
+ /** Read a CANMessage from the bus.
+ *
+ * @param msg A CANMessage to read to.
+ * @param handle message filter handle (0 for any message)
+ *
+ * @returns
+ * 0 if no message arrived,
+ * 1 if message arrived
+ */
+ int read(CANMessage &msg, int handle = 0);
+
+ /** Reset CAN interface.
+ *
+ * To use after error overflow.
+ */
+ void reset();
+
+ /** Puts or removes the CAN interface into silent monitoring mode
+ *
+ * @param silent boolean indicating whether to go into silent mode or not
+ */
+ void monitor(bool silent);
+
+ enum Mode {
+ Reset = 0,
+ Normal,
+ Silent,
+ LocalTest,
+ GlobalTest,
+ SilentTest
+ };
+
+ /** Change CAN operation to the specified mode
+ *
+ * @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
+ *
+ * @returns
+ * 0 if mode change failed or unsupported,
+ * 1 if mode change was successful
+ */
+ int mode(Mode mode);
+
+ /** Filter out incomming messages
+ *
+ * @param id the id to filter on
+ * @param mask the mask applied to the id
+ * @param format format to filter on (Default CANAny)
+ * @param handle message filter handle (Optional)
+ *
+ * @returns
+ * 0 if filter change failed or unsupported,
+ * new filter handle if successful
+ */
+ int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);
+
+ /** Returns number of read errors to detect read overflow errors.
+ */
+ unsigned char rderror();
+
+ /** Returns number of write errors to detect write overflow errors.
+ */
+ unsigned char tderror();
+
+ enum IrqType {
+ RxIrq = 0,
+ TxIrq,
+ EwIrq,
+ DoIrq,
+ WuIrq,
+ EpIrq,
+ AlIrq,
+ BeIrq,
+ IdIrq
+ };
+
+ /** Attach a function to call whenever a CAN frame received interrupt is
+ * generated.
+ *
+ * @param fptr A pointer to a void function, or 0 to set as none
+ * @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
+ */
+ void attach(void (*fptr)(void), IrqType type=RxIrq);
+
+ /** Attach a member function to call whenever a CAN frame received interrupt
+ * is generated.
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
+ */
+ template<typename T>
+ void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ _irq[type].attach(tptr, mptr);
+ can_irq_set(&_can, (CanIrqType)type, 1);
+ }
+ else {
+ can_irq_set(&_can, (CanIrqType)type, 0);
+ }
+ }
+
+ static void _irq_handler(uint32_t id, CanIrqType type);
+
+protected:
+ can_t _can;
+ FunctionPointer _irq[9];
+};
+
+} // namespace mbed
+
+#endif
+
+#endif // MBED_CAN_H
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/CallChain.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/CallChain.h
new file mode 100644
index 000000000..ebb796a3c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/CallChain.h
@@ -0,0 +1,181 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CALLCHAIN_H
+#define MBED_CALLCHAIN_H
+
+#include "FunctionPointer.h"
+#include <string.h>
+
+namespace mbed {
+
+/** Group one or more functions in an instance of a CallChain, then call them in
+ * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
+ * but can be used for other purposes.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * CallChain chain;
+ *
+ * void first(void) {
+ * printf("'first' function.\n");
+ * }
+ *
+ * void second(void) {
+ * printf("'second' function.\n");
+ * }
+ *
+ * class Test {
+ * public:
+ * void f(void) {
+ * printf("A::f (class member).\n");
+ * }
+ * };
+ *
+ * int main() {
+ * Test test;
+ *
+ * chain.add(second);
+ * chain.add_front(first);
+ * chain.add(&test, &Test::f);
+ * chain.call();
+ * }
+ * @endcode
+ */
+
+typedef FunctionPointer* pFunctionPointer_t;
+
+class CallChain {
+public:
+ /** Create an empty chain
+ *
+ * @param size (optional) Initial size of the chain
+ */
+ CallChain(int size = 4);
+ virtual ~CallChain();
+
+ /** Add a function at the end of the chain
+ *
+ * @param function A pointer to a void function
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add(void (*function)(void));
+
+ /** Add a function at the end of the chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add(T *tptr, void (T::*mptr)(void)) {
+ return common_add(new FunctionPointer(tptr, mptr));
+ }
+
+ /** Add a function at the beginning of the chain
+ *
+ * @param function A pointer to a void function
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add_front(void (*function)(void));
+
+ /** Add a function at the beginning of the chain
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_front(T *tptr, void (T::*mptr)(void)) {
+ return common_add_front(new FunctionPointer(tptr, mptr));
+ }
+
+ /** Get the number of functions in the chain
+ */
+ int size() const;
+
+ /** Get a function object from the chain
+ *
+ * @param i function object index
+ *
+ * @returns
+ * The function object at position 'i' in the chain
+ */
+ pFunctionPointer_t get(int i) const;
+
+ /** Look for a function object in the call chain
+ *
+ * @param f the function object to search
+ *
+ * @returns
+ * The index of the function object if found, -1 otherwise.
+ */
+ int find(pFunctionPointer_t f) const;
+
+ /** Clear the call chain (remove all functions in the chain).
+ */
+ void clear();
+
+ /** Remove a function object from the chain
+ *
+ * @arg f the function object to remove
+ *
+ * @returns
+ * true if the function object was found and removed, false otherwise.
+ */
+ bool remove(pFunctionPointer_t f);
+
+ /** Call all the functions in the chain in sequence
+ */
+ void call();
+
+#ifdef MBED_OPERATORS
+ void operator ()(void) {
+ call();
+ }
+ pFunctionPointer_t operator [](int i) const {
+ return get(i);
+ }
+#endif
+
+private:
+ void _check_size();
+ pFunctionPointer_t common_add(pFunctionPointer_t pf);
+ pFunctionPointer_t common_add_front(pFunctionPointer_t pf);
+
+ pFunctionPointer_t* _chain;
+ int _size;
+ int _elements;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ CallChain(const CallChain&);
+ CallChain & operator = (const CallChain&);
+};
+
+} // namespace mbed
+
+#endif
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalIn.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalIn.h
new file mode 100644
index 000000000..b089de9fa
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalIn.h
@@ -0,0 +1,107 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALIN_H
+#define MBED_DIGITALIN_H
+
+#include "platform.h"
+
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital input, used for reading the state of a pin
+ *
+ * Example:
+ * @code
+ * // Flash an LED while a DigitalIn is true
+ *
+ * #include "mbed.h"
+ *
+ * DigitalIn enable(p5);
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ * while(1) {
+ * if(enable) {
+ * led = !led;
+ * }
+ * wait(0.25);
+ * }
+ * }
+ * @endcode
+ */
+class DigitalIn {
+
+public:
+ /** Create a DigitalIn connected to the specified pin
+ *
+ * @param pin DigitalIn pin to connect to
+ */
+ DigitalIn(PinName pin) : gpio() {
+ gpio_init_in(&gpio, pin);
+ }
+
+ /** Create a DigitalIn connected to the specified pin
+ *
+ * @param pin DigitalIn pin to connect to
+ * @param mode the initial mode of the pin
+ */
+ DigitalIn(PinName pin, PinMode mode) : gpio() {
+ gpio_init_in_ex(&gpio, pin, mode);
+ }
+ /** Read the input, represented as 0 or 1 (int)
+ *
+ * @returns
+ * An integer representing the state of the input pin,
+ * 0 for logical 0, 1 for logical 1
+ */
+ int read() {
+ return gpio_read(&gpio);
+ }
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode pull) {
+ gpio_mode(&gpio, pull);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * Non zero value if pin is connected to uc GPIO
+ * 0 if gpio object was initialized with NC
+ */
+ int is_connected() {
+ return gpio_is_connected(&gpio);
+ }
+
+#ifdef MBED_OPERATORS
+ /** An operator shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+#endif
+
+protected:
+ gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalInOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalInOut.h
new file mode 100644
index 000000000..e30be0e63
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalInOut.h
@@ -0,0 +1,124 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALINOUT_H
+#define MBED_DIGITALINOUT_H
+
+#include "platform.h"
+
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital input/output, used for setting or reading a bi-directional pin
+ */
+class DigitalInOut {
+
+public:
+ /** Create a DigitalInOut connected to the specified pin
+ *
+ * @param pin DigitalInOut pin to connect to
+ */
+ DigitalInOut(PinName pin) : gpio() {
+ gpio_init_in(&gpio, pin);
+ }
+
+ /** Create a DigitalInOut connected to the specified pin
+ *
+ * @param pin DigitalInOut pin to connect to
+ * @param direction the initial direction of the pin
+ * @param mode the initial mode of the pin
+ * @param value the initial value of the pin if is an output
+ */
+ DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio() {
+ gpio_init_inout(&gpio, pin, direction, mode, value);
+ }
+
+ /** Set the output, specified as 0 or 1 (int)
+ *
+ * @param value An integer specifying the pin output value,
+ * 0 for logical 0, 1 (or any other non-zero value) for logical 1
+ */
+ void write(int value) {
+ gpio_write(&gpio, value);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * an integer representing the output setting of the pin if it is an output,
+ * or read the input if set as an input
+ */
+ int read() {
+ return gpio_read(&gpio);
+ }
+
+ /** Set as an output
+ */
+ void output() {
+ gpio_dir(&gpio, PIN_OUTPUT);
+ }
+
+ /** Set as an input
+ */
+ void input() {
+ gpio_dir(&gpio, PIN_INPUT);
+ }
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode pull) {
+ gpio_mode(&gpio, pull);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * Non zero value if pin is connected to uc GPIO
+ * 0 if gpio object was initialized with NC
+ */
+ int is_connected() {
+ return gpio_is_connected(&gpio);
+ }
+
+#ifdef MBED_OPERATORS
+ /** A shorthand for write()
+ */
+ DigitalInOut& operator= (int value) {
+ write(value);
+ return *this;
+ }
+
+ DigitalInOut& operator= (DigitalInOut& rhs) {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+#endif
+
+protected:
+ gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalOut.h
new file mode 100644
index 000000000..0d66f907b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DigitalOut.h
@@ -0,0 +1,116 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALOUT_H
+#define MBED_DIGITALOUT_H
+
+#include "platform.h"
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital output, used for setting the state of a pin
+ *
+ * Example:
+ * @code
+ * // Toggle a LED
+ * #include "mbed.h"
+ *
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ * while(1) {
+ * led = !led;
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ */
+class DigitalOut {
+
+public:
+ /** Create a DigitalOut connected to the specified pin
+ *
+ * @param pin DigitalOut pin to connect to
+ */
+ DigitalOut(PinName pin) : gpio() {
+ gpio_init_out(&gpio, pin);
+ }
+
+ /** Create a DigitalOut connected to the specified pin
+ *
+ * @param pin DigitalOut pin to connect to
+ * @param value the initial pin value
+ */
+ DigitalOut(PinName pin, int value) : gpio() {
+ gpio_init_out_ex(&gpio, pin, value);
+ }
+
+ /** Set the output, specified as 0 or 1 (int)
+ *
+ * @param value An integer specifying the pin output value,
+ * 0 for logical 0, 1 (or any other non-zero value) for logical 1
+ */
+ void write(int value) {
+ gpio_write(&gpio, value);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * an integer representing the output setting of the pin,
+ * 0 for logical 0, 1 for logical 1
+ */
+ int read() {
+ return gpio_read(&gpio);
+ }
+
+ /** Return the output setting, represented as 0 or 1 (int)
+ *
+ * @returns
+ * Non zero value if pin is connected to uc GPIO
+ * 0 if gpio object was initialized with NC
+ */
+ int is_connected() {
+ return gpio_is_connected(&gpio);
+ }
+
+#ifdef MBED_OPERATORS
+ /** A shorthand for write()
+ */
+ DigitalOut& operator= (int value) {
+ write(value);
+ return *this;
+ }
+
+ DigitalOut& operator= (DigitalOut& rhs) {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+#endif
+
+protected:
+ gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DirHandle.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DirHandle.h
new file mode 100644
index 000000000..329f4d1c7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/DirHandle.h
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIRHANDLE_H
+#define MBED_DIRHANDLE_H
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+# define NAME_MAX 255
+typedef int mode_t;
+
+#else
+# include <sys/syslimits.h>
+#endif
+
+#include "FileHandle.h"
+
+struct dirent {
+ char d_name[NAME_MAX+1];
+};
+
+namespace mbed {
+
+/** Represents a directory stream. Objects of this type are returned
+ * by a FileSystemLike's opendir method. Implementations must define
+ * at least closedir, readdir and rewinddir.
+ *
+ * If a FileSystemLike class defines the opendir method, then the
+ * directories of an object of that type can be accessed by
+ * DIR *d = opendir("/example/directory") (or opendir("/example")
+ * to open the root of the filesystem), and then using readdir(d) etc.
+ *
+ * The root directory is considered to contain all FileLike and
+ * FileSystemLike objects, so the DIR* returned by opendir("/") will
+ * reflect this.
+ */
+class DirHandle {
+
+public:
+ /** Closes the directory.
+ *
+ * @returns
+ * 0 on success,
+ * -1 on error.
+ */
+ virtual int closedir()=0;
+
+ /** Return the directory entry at the current position, and
+ * advances the position to the next entry.
+ *
+ * @returns
+ * A pointer to a dirent structure representing the
+ * directory entry at the current position, or NULL on reaching
+ * end of directory or error.
+ */
+ virtual struct dirent *readdir()=0;
+
+ /** Resets the position to the beginning of the directory.
+ */
+ virtual void rewinddir()=0;
+
+ /** Returns the current position of the DirHandle.
+ *
+ * @returns
+ * the current position,
+ * -1 on error.
+ */
+ virtual off_t telldir() { return -1; }
+
+ /** Sets the position of the DirHandle.
+ *
+ * @param location The location to seek to. Must be a value returned by telldir.
+ */
+ virtual void seekdir(off_t location) { }
+
+ virtual ~DirHandle() {}
+};
+
+} // namespace mbed
+
+typedef mbed::DirHandle DIR;
+
+extern "C" {
+ DIR *opendir(const char*);
+ struct dirent *readdir(DIR *);
+ int closedir(DIR*);
+ void rewinddir(DIR*);
+ long telldir(DIR*);
+ void seekdir(DIR*, long);
+ int mkdir(const char *name, mode_t n);
+};
+
+#endif /* MBED_DIRHANDLE_H */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Ethernet.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Ethernet.h
new file mode 100644
index 000000000..d0e59a5cf
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Ethernet.h
@@ -0,0 +1,170 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_H
+#define MBED_ETHERNET_H
+
+#include "platform.h"
+
+#if DEVICE_ETHERNET
+
+namespace mbed {
+
+/** An ethernet interface, to use with the ethernet pins.
+ *
+ * Example:
+ * @code
+ * // Read destination and source from every ethernet packet
+ *
+ * #include "mbed.h"
+ *
+ * Ethernet eth;
+ *
+ * int main() {
+ * char buf[0x600];
+ *
+ * while(1) {
+ * int size = eth.receive();
+ * if(size > 0) {
+ * eth.read(buf, size);
+ * printf("Destination: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ * buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ * printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ * buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
+ * }
+ *
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ */
+class Ethernet {
+
+public:
+
+ /** Initialise the ethernet interface.
+ */
+ Ethernet();
+
+ /** Powers the hardware down.
+ */
+ virtual ~Ethernet();
+
+ enum Mode {
+ AutoNegotiate,
+ HalfDuplex10,
+ FullDuplex10,
+ HalfDuplex100,
+ FullDuplex100
+ };
+
+ /** Writes into an outgoing ethernet packet.
+ *
+ * It will append size bytes of data to the previously written bytes.
+ *
+ * @param data An array to write.
+ * @param size The size of data.
+ *
+ * @returns
+ * The number of written bytes.
+ */
+ int write(const char *data, int size);
+
+ /** Send an outgoing ethernet packet.
+ *
+ * After filling in the data in an ethernet packet it must be send.
+ * Send will provide a new packet to write to.
+ *
+ * @returns
+ * 0 if the sending was failed,
+ * or the size of the packet successfully sent.
+ */
+ int send();
+
+ /** Recevies an arrived ethernet packet.
+ *
+ * Receiving an ethernet packet will drop the last received ethernet packet
+ * and make a new ethernet packet ready to read.
+ * If no ethernet packet is arrived it will return 0.
+ *
+ * @returns
+ * 0 if no ethernet packet is arrived,
+ * or the size of the arrived packet.
+ */
+ int receive();
+
+ /** Read from an recevied ethernet packet.
+ *
+ * After receive returnd a number bigger than 0it is
+ * possible to read bytes from this packet.
+ * Read will write up to size bytes into data.
+ *
+ * It is possible to use read multible times.
+ * Each time read will start reading after the last read byte before.
+ *
+ * @returns
+ * The number of byte read.
+ */
+ int read(char *data, int size);
+
+ /** Gives the ethernet address of the mbed.
+ *
+ * @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
+ */
+ void address(char *mac);
+
+ /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
+ *
+ * @returns
+ * 0 if no ethernet link is pressent,
+ * 1 if an ethernet link is pressent.
+ *
+ * Example:
+ * @code
+ * // Using the Ethernet link function
+ * #include "mbed.h"
+ *
+ * Ethernet eth;
+ *
+ * int main() {
+ * wait(1); // Needed after startup.
+ * if (eth.link()) {
+ * printf("online\n");
+ * } else {
+ * printf("offline\n");
+ * }
+ * }
+ * @endcode
+ */
+ int link();
+
+ /** Sets the speed and duplex parameters of an ethernet link
+ *
+ * - AutoNegotiate Auto negotiate speed and duplex
+ * - HalfDuplex10 10 Mbit, half duplex
+ * - FullDuplex10 10 Mbit, full duplex
+ * - HalfDuplex100 100 Mbit, half duplex
+ * - FullDuplex100 100 Mbit, full duplex
+ *
+ * @param mode the speed and duplex mode to set the link to:
+ */
+ void set_link(Mode mode);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileBase.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileBase.h
new file mode 100644
index 000000000..88f87842c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileBase.h
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEBASE_H
+#define MBED_FILEBASE_H
+
+typedef int FILEHANDLE;
+
+#include <stdio.h>
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+# define O_RDONLY 0
+# define O_WRONLY 1
+# define O_RDWR 2
+# define O_CREAT 0x0200
+# define O_TRUNC 0x0400
+# define O_APPEND 0x0008
+
+# define NAME_MAX 255
+
+typedef int mode_t;
+typedef int ssize_t;
+typedef long off_t;
+
+#else
+# include <sys/fcntl.h>
+# include <sys/types.h>
+# include <sys/syslimits.h>
+#endif
+
+#include "platform.h"
+
+namespace mbed {
+
+typedef enum {
+ FilePathType,
+ FileSystemPathType
+} PathType;
+
+class FileBase {
+public:
+ FileBase(const char *name, PathType t);
+
+ virtual ~FileBase();
+
+ const char* getName(void);
+ PathType getPathType(void);
+
+ static FileBase *lookup(const char *name, unsigned int len);
+
+ static FileBase *get(int n);
+
+protected:
+ static FileBase *_head;
+
+ FileBase *_next;
+ const char *_name;
+ PathType _path_type;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ FileBase(const FileBase&);
+ FileBase & operator = (const FileBase&);
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileHandle.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileHandle.h
new file mode 100644
index 000000000..0a98a827c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileHandle.h
@@ -0,0 +1,119 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEHANDLE_H
+#define MBED_FILEHANDLE_H
+
+typedef int FILEHANDLE;
+
+#include <stdio.h>
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+typedef int ssize_t;
+typedef long off_t;
+
+#else
+# include <sys/types.h>
+#endif
+
+namespace mbed {
+
+/** An OO equivalent of the internal FILEHANDLE variable
+ * and associated _sys_* functions.
+ *
+ * FileHandle is an abstract class, needing at least sys_write and
+ * sys_read to be implmented for a simple interactive device.
+ *
+ * No one ever directly tals to/instanciates a FileHandle - it gets
+ * created by FileSystem, and wrapped up by stdio.
+ */
+class FileHandle {
+
+public:
+ /** Write the contents of a buffer to the file
+ *
+ * @param buffer the buffer to write from
+ * @param length the number of characters to write
+ *
+ * @returns
+ * The number of characters written (possibly 0) on success, -1 on error.
+ */
+ virtual ssize_t write(const void* buffer, size_t length) = 0;
+
+ /** Close the file
+ *
+ * @returns
+ * Zero on success, -1 on error.
+ */
+ virtual int close() = 0;
+
+ /** Function read
+ * Reads the contents of the file into a buffer
+ *
+ * @param buffer the buffer to read in to
+ * @param length the number of characters to read
+ *
+ * @returns
+ * The number of characters read (zero at end of file) on success, -1 on error.
+ */
+ virtual ssize_t read(void* buffer, size_t length) = 0;
+
+ /** Check if the handle is for a interactive terminal device.
+ * If so, line buffered behaviour is used by default
+ *
+ * @returns
+ * 1 if it is a terminal,
+ * 0 otherwise
+ */
+ virtual int isatty() = 0;
+
+ /** Move the file position to a given offset from a given location.
+ *
+ * @param offset The offset from whence to move to
+ * @param whence SEEK_SET for the start of the file, SEEK_CUR for the
+ * current file position, or SEEK_END for the end of the file.
+ *
+ * @returns
+ * new file position on success,
+ * -1 on failure or unsupported
+ */
+ virtual off_t lseek(off_t offset, int whence) = 0;
+
+ /** Flush any buffers associated with the FileHandle, ensuring it
+ * is up to date on disk
+ *
+ * @returns
+ * 0 on success or un-needed,
+ * -1 on error
+ */
+ virtual int fsync() = 0;
+
+ virtual off_t flen() {
+ /* remember our current position */
+ off_t pos = lseek(0, SEEK_CUR);
+ if(pos == -1) return -1;
+ /* seek to the end to get the file length */
+ off_t res = lseek(0, SEEK_END);
+ /* return to our old position */
+ lseek(pos, SEEK_SET);
+ return res;
+ }
+
+ virtual ~FileHandle();
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileLike.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileLike.h
new file mode 100644
index 000000000..666575c90
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileLike.h
@@ -0,0 +1,44 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILELIKE_H
+#define MBED_FILELIKE_H
+
+#include "FileBase.h"
+#include "FileHandle.h"
+
+namespace mbed {
+
+/* Class FileLike
+ * A file-like object is one that can be opened with fopen by
+ * fopen("/name", mode). It is intersection of the classes Base and
+ * FileHandle.
+ */
+class FileLike : public FileHandle, public FileBase {
+
+public:
+ /* Constructor FileLike
+ *
+ * Variables
+ * name - The name to use to open the file.
+ */
+ FileLike(const char *name);
+
+ virtual ~FileLike();
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FilePath.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FilePath.h
new file mode 100644
index 000000000..3de120504
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FilePath.h
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEPATH_H
+#define MBED_FILEPATH_H
+
+#include "platform.h"
+
+#include "FileSystemLike.h"
+#include "FileLike.h"
+
+namespace mbed {
+
+class FilePath {
+public:
+ FilePath(const char* file_path);
+
+ const char* fileName(void);
+
+ bool isFileSystem(void);
+ FileSystemLike* fileSystem(void);
+
+ bool isFile(void);
+ FileLike* file(void);
+ bool exists(void);
+
+private:
+ const char* file_name;
+ FileBase* fb;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileSystemLike.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileSystemLike.h
new file mode 100644
index 000000000..6680c4cb0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FileSystemLike.h
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILESYSTEMLIKE_H
+#define MBED_FILESYSTEMLIKE_H
+
+#include "platform.h"
+
+#include "FileBase.h"
+#include "FileHandle.h"
+#include "DirHandle.h"
+
+namespace mbed {
+
+/** A filesystem-like object is one that can be used to open files
+ * though it by fopen("/name/filename", mode)
+ *
+ * Implementations must define at least open (the default definitions
+ * of the rest of the functions just return error values).
+ */
+class FileSystemLike : public FileBase {
+
+public:
+ /** FileSystemLike constructor
+ *
+ * @param name The name to use for the filesystem.
+ */
+ FileSystemLike(const char *name);
+
+ virtual ~FileSystemLike();
+
+ static DirHandle *opendir();
+ friend class BaseDirHandle;
+
+ /** Opens a file from the filesystem
+ *
+ * @param filename The name of the file to open.
+ * @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with
+ * zero or more of O_CREAT, O_TRUNC, or O_APPEND.
+ *
+ * @returns
+ * A pointer to a FileHandle object representing the
+ * file on success, or NULL on failure.
+ */
+ virtual FileHandle *open(const char *filename, int flags) = 0;
+
+ /** Remove a file from the filesystem.
+ *
+ * @param filename the name of the file to remove.
+ * @param returns 0 on success, -1 on failure.
+ */
+ virtual int remove(const char *filename) { return -1; };
+
+ /** Rename a file in the filesystem.
+ *
+ * @param oldname the name of the file to rename.
+ * @param newname the name to rename it to.
+ *
+ * @returns
+ * 0 on success,
+ * -1 on failure.
+ */
+ virtual int rename(const char *oldname, const char *newname) { return -1; };
+
+ /** Opens a directory in the filesystem and returns a DirHandle
+ * representing the directory stream.
+ *
+ * @param name The name of the directory to open.
+ *
+ * @returns
+ * A DirHandle representing the directory stream, or
+ * NULL on failure.
+ */
+ virtual DirHandle *opendir(const char *name) { return NULL; };
+
+ /** Creates a directory in the filesystem.
+ *
+ * @param name The name of the directory to create.
+ * @param mode The permissions to create the directory with.
+ *
+ * @returns
+ * 0 on success,
+ * -1 on failure.
+ */
+ virtual int mkdir(const char *name, mode_t mode) { return -1; }
+
+ // TODO other filesystem functions (mkdir, rm, rn, ls etc)
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FunctionPointer.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FunctionPointer.h
new file mode 100644
index 000000000..1ae492283
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/FunctionPointer.h
@@ -0,0 +1,94 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FUNCTIONPOINTER_H
+#define MBED_FUNCTIONPOINTER_H
+
+#include <string.h>
+
+namespace mbed {
+
+typedef void (*pvoidf_t)(void);
+
+/** A class for storing and calling a pointer to a static or member void function
+ */
+class FunctionPointer {
+public:
+
+ /** Create a FunctionPointer, attaching a static function
+ *
+ * @param function The void static function to attach (default is none)
+ */
+ FunctionPointer(void (*function)(void) = 0);
+
+ /** Create a FunctionPointer, attaching a member function
+ *
+ * @param object The object pointer to invoke the member function on (i.e. the this pointer)
+ * @param function The address of the void member function to attach
+ */
+ template<typename T>
+ FunctionPointer(T *object, void (T::*member)(void)) {
+ attach(object, member);
+ }
+
+ /** Attach a static function
+ *
+ * @param function The void static function to attach (default is none)
+ */
+ void attach(void (*function)(void) = 0);
+
+ /** Attach a member function
+ *
+ * @param object The object pointer to invoke the member function on (i.e. the this pointer)
+ * @param function The address of the void member function to attach
+ */
+ template<typename T>
+ void attach(T *object, void (T::*member)(void)) {
+ _object = static_cast<void*>(object);
+ memcpy(_member, (char*)&member, sizeof(member));
+ _membercaller = &FunctionPointer::membercaller<T>;
+ _function = 0;
+ }
+
+ /** Call the attached static or member function
+ */
+ void call();
+
+ pvoidf_t get_function() const {
+ return (pvoidf_t)_function;
+ }
+
+#ifdef MBED_OPERATORS
+ void operator ()(void);
+#endif
+
+private:
+ template<typename T>
+ static void membercaller(void *object, char *member) {
+ T* o = static_cast<T*>(object);
+ void (T::*m)(void);
+ memcpy((char*)&m, member, sizeof(m));
+ (o->*m)();
+ }
+
+ void (*_function)(void); // static function pointer - 0 if none attached
+ void *_object; // object this pointer - 0 if none attached
+ char _member[16]; // raw member function pointer storage - converted back by registered _membercaller
+ void (*_membercaller)(void*, char*); // registered membercaller function to convert back and call _member on _object
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/I2C.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/I2C.h
new file mode 100644
index 000000000..bd7cf1223
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/I2C.h
@@ -0,0 +1,144 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_H
+#define MBED_I2C_H
+
+#include "platform.h"
+
+#if DEVICE_I2C
+
+#include "i2c_api.h"
+
+namespace mbed {
+
+/** An I2C Master, used for communicating with I2C slave devices
+ *
+ * Example:
+ * @code
+ * // Read from I2C slave at address 0x62
+ *
+ * #include "mbed.h"
+ *
+ * I2C i2c(p28, p27);
+ *
+ * int main() {
+ * int address = 0x62;
+ * char data[2];
+ * i2c.read(address, data, 2);
+ * }
+ * @endcode
+ */
+class I2C {
+
+public:
+ enum RxStatus {
+ NoData,
+ MasterGeneralCall,
+ MasterWrite,
+ MasterRead
+ };
+
+ enum Acknowledge {
+ NoACK = 0,
+ ACK = 1
+ };
+
+ /** Create an I2C Master interface, connected to the specified pins
+ *
+ * @param sda I2C data line pin
+ * @param scl I2C clock line pin
+ */
+ I2C(PinName sda, PinName scl);
+
+ /** Set the frequency of the I2C interface
+ *
+ * @param hz The bus frequency in hertz
+ */
+ void frequency(int hz);
+
+ /** Read from an I2C slave
+ *
+ * Performs a complete read transaction. The bottom bit of
+ * the address is forced to 1 to indicate a read.
+ *
+ * @param address 8-bit I2C slave address [ addr | 1 ]
+ * @param data Pointer to the byte-array to read data in to
+ * @param length Number of bytes to read
+ * @param repeated Repeated start, true - don't send stop at end
+ *
+ * @returns
+ * 0 on success (ack),
+ * non-0 on failure (nack)
+ */
+ int read(int address, char *data, int length, bool repeated = false);
+
+ /** Read a single byte from the I2C bus
+ *
+ * @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
+ *
+ * @returns
+ * the byte read
+ */
+ int read(int ack);
+
+ /** Write to an I2C slave
+ *
+ * Performs a complete write transaction. The bottom bit of
+ * the address is forced to 0 to indicate a write.
+ *
+ * @param address 8-bit I2C slave address [ addr | 0 ]
+ * @param data Pointer to the byte-array data to send
+ * @param length Number of bytes to send
+ * @param repeated Repeated start, true - do not send stop at end
+ *
+ * @returns
+ * 0 on success (ack),
+ * non-0 on failure (nack)
+ */
+ int write(int address, const char *data, int length, bool repeated = false);
+
+ /** Write single byte out on the I2C bus
+ *
+ * @param data data to write out on bus
+ *
+ * @returns
+ * '1' if an ACK was received,
+ * '0' otherwise
+ */
+ int write(int data);
+
+ /** Creates a start condition on the I2C bus
+ */
+
+ void start(void);
+
+ /** Creates a stop condition on the I2C bus
+ */
+ void stop(void);
+
+protected:
+ void aquire();
+
+ i2c_t _i2c;
+ static I2C *_owner;
+ int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/I2CSlave.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/I2CSlave.h
new file mode 100644
index 000000000..738faea27
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/I2CSlave.h
@@ -0,0 +1,154 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_SLAVE_H
+#define MBED_I2C_SLAVE_H
+
+#include "platform.h"
+
+#if DEVICE_I2CSLAVE
+
+#include "i2c_api.h"
+
+namespace mbed {
+
+/** An I2C Slave, used for communicating with an I2C Master device
+ *
+ * Example:
+ * @code
+ * // Simple I2C responder
+ * #include <mbed.h>
+ *
+ * I2CSlave slave(p9, p10);
+ *
+ * int main() {
+ * char buf[10];
+ * char msg[] = "Slave!";
+ *
+ * slave.address(0xA0);
+ * while (1) {
+ * int i = slave.receive();
+ * switch (i) {
+ * case I2CSlave::ReadAddressed:
+ * slave.write(msg, strlen(msg) + 1); // Includes null char
+ * break;
+ * case I2CSlave::WriteGeneral:
+ * slave.read(buf, 10);
+ * printf("Read G: %s\n", buf);
+ * break;
+ * case I2CSlave::WriteAddressed:
+ * slave.read(buf, 10);
+ * printf("Read A: %s\n", buf);
+ * break;
+ * }
+ * for(int i = 0; i < 10; i++) buf[i] = 0; // Clear buffer
+ * }
+ * }
+ * @endcode
+ */
+class I2CSlave {
+
+public:
+ enum RxStatus {
+ NoData = 0,
+ ReadAddressed = 1,
+ WriteGeneral = 2,
+ WriteAddressed = 3
+ };
+
+ /** Create an I2C Slave interface, connected to the specified pins.
+ *
+ * @param sda I2C data line pin
+ * @param scl I2C clock line pin
+ */
+ I2CSlave(PinName sda, PinName scl);
+
+ /** Set the frequency of the I2C interface
+ *
+ * @param hz The bus frequency in hertz
+ */
+ void frequency(int hz);
+
+ /** Checks to see if this I2C Slave has been addressed.
+ *
+ * @returns
+ * A status indicating if the device has been addressed, and how
+ * - NoData - the slave has not been addressed
+ * - ReadAddressed - the master has requested a read from this slave
+ * - WriteAddressed - the master is writing to this slave
+ * - WriteGeneral - the master is writing to all slave
+ */
+ int receive(void);
+
+ /** Read from an I2C master.
+ *
+ * @param data pointer to the byte array to read data in to
+ * @param length maximum number of bytes to read
+ *
+ * @returns
+ * 0 on success,
+ * non-0 otherwise
+ */
+ int read(char *data, int length);
+
+ /** Read a single byte from an I2C master.
+ *
+ * @returns
+ * the byte read
+ */
+ int read(void);
+
+ /** Write to an I2C master.
+ *
+ * @param data pointer to the byte array to be transmitted
+ * @param length the number of bytes to transmite
+ *
+ * @returns
+ * 0 on success,
+ * non-0 otherwise
+ */
+ int write(const char *data, int length);
+
+ /** Write a single byte to an I2C master.
+ *
+ * @data the byte to write
+ *
+ * @returns
+ * '1' if an ACK was received,
+ * '0' otherwise
+ */
+ int write(int data);
+
+ /** Sets the I2C slave address.
+ *
+ * @param address The address to set for the slave (ignoring the least
+ * signifcant bit). If set to 0, the slave will only respond to the
+ * general call address.
+ */
+ void address(int address);
+
+ /** Reset the I2C slave back into the known ready receiving state.
+ */
+ void stop(void);
+
+protected:
+ i2c_t _i2c;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptIn.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptIn.h
new file mode 100644
index 000000000..88bc4308e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptIn.h
@@ -0,0 +1,135 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERRUPTIN_H
+#define MBED_INTERRUPTIN_H
+
+#include "platform.h"
+
+#if DEVICE_INTERRUPTIN
+
+#include "gpio_api.h"
+#include "gpio_irq_api.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** A digital interrupt input, used to call a function on a rising or falling edge
+ *
+ * Example:
+ * @code
+ * // Flash an LED while waiting for events
+ *
+ * #include "mbed.h"
+ *
+ * InterruptIn event(p16);
+ * DigitalOut led(LED1);
+ *
+ * void trigger() {
+ * printf("triggered!\n");
+ * }
+ *
+ * int main() {
+ * event.rise(&trigger);
+ * while(1) {
+ * led = !led;
+ * wait(0.25);
+ * }
+ * }
+ * @endcode
+ */
+class InterruptIn {
+
+public:
+
+ /** Create an InterruptIn connected to the specified pin
+ *
+ * @param pin InterruptIn pin to connect to
+ * @param name (optional) A string to identify the object
+ */
+ InterruptIn(PinName pin);
+ virtual ~InterruptIn();
+
+ int read();
+#ifdef MBED_OPERATORS
+ operator int();
+
+#endif
+
+ /** Attach a function to call when a rising edge occurs on the input
+ *
+ * @param fptr A pointer to a void function, or 0 to set as none
+ */
+ void rise(void (*fptr)(void));
+
+ /** Attach a member function to call when a rising edge occurs on the input
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ */
+ template<typename T>
+ void rise(T* tptr, void (T::*mptr)(void)) {
+ _rise.attach(tptr, mptr);
+ gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+ }
+
+ /** Attach a function to call when a falling edge occurs on the input
+ *
+ * @param fptr A pointer to a void function, or 0 to set as none
+ */
+ void fall(void (*fptr)(void));
+
+ /** Attach a member function to call when a falling edge occurs on the input
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ */
+ template<typename T>
+ void fall(T* tptr, void (T::*mptr)(void)) {
+ _fall.attach(tptr, mptr);
+ gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+ }
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone
+ */
+ void mode(PinMode pull);
+
+ /** Enable IRQ. This method depends on hw implementation, might enable one
+ * port interrupts. For further information, check gpio_irq_enable().
+ */
+ void enable_irq();
+
+ /** Disable IRQ. This method depends on hw implementation, might disable one
+ * port interrupts. For further information, check gpio_irq_disable().
+ */
+ void disable_irq();
+
+ static void _irq_handler(uint32_t id, gpio_irq_event event);
+
+protected:
+ gpio_t gpio;
+ gpio_irq_t gpio_irq;
+
+ FunctionPointer _rise;
+ FunctionPointer _fall;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptManager.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptManager.h
new file mode 100644
index 000000000..4959a6469
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/InterruptManager.h
@@ -0,0 +1,143 @@
+#ifndef MBED_INTERRUPTMANAGER_H
+#define MBED_INTERRUPTMANAGER_H
+
+#include "cmsis.h"
+#include "CallChain.h"
+#include <string.h>
+
+namespace mbed {
+
+/** Use this singleton if you need to chain interrupt handlers.
+ *
+ * Example (for LPC1768):
+ * @code
+ * #include "InterruptManager.h"
+ * #include "mbed.h"
+ *
+ * Ticker flipper;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * void flip(void) {
+ * led1 = !led1;
+ * }
+ *
+ * void handler(void) {
+ * led2 = !led1;
+ * }
+ *
+ * int main() {
+ * led1 = led2 = 0;
+ * flipper.attach(&flip, 1.0);
+ * InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
+ * }
+ * @endcode
+ */
+class InterruptManager {
+public:
+ /** Return the only instance of this class
+ */
+ static InterruptManager* get();
+
+ /** Destroy the current instance of the interrupt manager
+ */
+ static void destroy();
+
+ /** Add a handler for an interrupt at the end of the handler list
+ *
+ * @param function the handler to add
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
+ return add_common(function, irq);
+ }
+
+ /** Add a handler for an interrupt at the beginning of the handler list
+ *
+ * @param function the handler to add
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'function'
+ */
+ pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
+ return add_common(function, irq, true);
+ }
+
+ /** Add a handler for an interrupt at the end of the handler list
+ *
+ * @param tptr pointer to the object that has the handler function
+ * @param mptr pointer to the actual handler function
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+ return add_common(tptr, mptr, irq);
+ }
+
+ /** Add a handler for an interrupt at the beginning of the handler list
+ *
+ * @param tptr pointer to the object that has the handler function
+ * @param mptr pointer to the actual handler function
+ * @param irq interrupt number
+ *
+ * @returns
+ * The function object created for 'tptr' and 'mptr'
+ */
+ template<typename T>
+ pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+ return add_common(tptr, mptr, irq, true);
+ }
+
+ /** Remove a handler from an interrupt
+ *
+ * @param handler the function object for the handler to remove
+ * @param irq the interrupt number
+ *
+ * @returns
+ * true if the handler was found and removed, false otherwise
+ */
+ bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
+
+private:
+ InterruptManager();
+ ~InterruptManager();
+
+ // We declare the copy contructor and the assignment operator, but we don't
+ // implement them. This way, if someone tries to copy/assign our instance,
+ // he will get an error at compile time.
+ InterruptManager(const InterruptManager&);
+ InterruptManager& operator =(const InterruptManager&);
+
+ template<typename T>
+ pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {
+ int irq_pos = get_irq_index(irq);
+ bool change = must_replace_vector(irq);
+
+ pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
+ if (change)
+ NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+ return pf;
+ }
+
+ pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);
+ bool must_replace_vector(IRQn_Type irq);
+ int get_irq_index(IRQn_Type irq);
+ void irq_helper();
+ void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);
+ static void static_irq_helper();
+
+ CallChain* _chains[NVIC_NUM_VECTORS];
+ static InterruptManager* _instance;
+};
+
+} // namespace mbed
+
+#endif
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/LocalFileSystem.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/LocalFileSystem.h
new file mode 100644
index 000000000..9eb61a4b9
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/LocalFileSystem.h
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOCALFILESYSTEM_H
+#define MBED_LOCALFILESYSTEM_H
+
+#include "platform.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "FileSystemLike.h"
+
+namespace mbed {
+
+FILEHANDLE local_file_open(const char* name, int flags);
+
+class LocalFileHandle : public FileHandle {
+
+public:
+ LocalFileHandle(FILEHANDLE fh);
+
+ virtual int close();
+
+ virtual ssize_t write(const void *buffer, size_t length);
+
+ virtual ssize_t read(void *buffer, size_t length);
+
+ virtual int isatty();
+
+ virtual off_t lseek(off_t position, int whence);
+
+ virtual int fsync();
+
+ virtual off_t flen();
+
+protected:
+ FILEHANDLE _fh;
+ int pos;
+};
+
+/** A filesystem for accessing the local mbed Microcontroller USB disk drive
+ *
+ * This allows programs to read and write files on the same disk drive that is used to program the
+ * mbed Microcontroller. Once created, the standard C file access functions are used to open,
+ * read and write files.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * LocalFileSystem local("local"); // Create the local filesystem under the name "local"
+ *
+ * int main() {
+ * FILE *fp = fopen("/local/out.txt", "w"); // Open "out.txt" on the local file system for writing
+ * fprintf(fp, "Hello World!");
+ * fclose(fp);
+ * remove("/local/out.txt"); // Removes the file "out.txt" from the local file system
+ *
+ * DIR *d = opendir("/local"); // Opens the root directory of the local file system
+ * struct dirent *p;
+ * while((p = readdir(d)) != NULL) { // Print the names of the files in the local file system
+ * printf("%s\n", p->d_name); // to stdout.
+ * }
+ * closedir(d);
+ * }
+ * @endcode
+ *
+ * @note
+ * If the microcontroller program makes an access to the local drive, it will be marked as "removed"
+ * on the Host computer. This means it is no longer accessible from the Host Computer.
+ *
+ * The drive will only re-appear when the microcontroller program exists. Note that if the program does
+ * not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!
+ */
+class LocalFileSystem : public FileSystemLike {
+
+public:
+ LocalFileSystem(const char* n) : FileSystemLike(n) {
+
+ }
+
+ virtual FileHandle *open(const char* name, int flags);
+ virtual int remove(const char *filename);
+ virtual DirHandle *opendir(const char *name);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortIn.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortIn.h
new file mode 100644
index 000000000..44686325c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortIn.h
@@ -0,0 +1,93 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTIN_H
+#define MBED_PORTIN_H
+
+#include "platform.h"
+
+#if DEVICE_PORTIN
+
+#include "port_api.h"
+
+namespace mbed {
+
+/** A multiple pin digital input
+ *
+ * Example:
+ * @code
+ * // Switch on an LED if any of mbed pins 21-26 is high
+ *
+ * #include "mbed.h"
+ *
+ * PortIn p(Port2, 0x0000003F); // p21-p26
+ * DigitalOut ind(LED4);
+ *
+ * int main() {
+ * while(1) {
+ * int pins = p.read();
+ * if(pins) {
+ * ind = 1;
+ * } else {
+ * ind = 0;
+ * }
+ * }
+ * }
+ * @endcode
+ */
+class PortIn {
+public:
+
+ /** Create an PortIn, connected to the specified port
+ *
+ * @param port Port to connect to (Port0-Port5)
+ * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+ */
+ PortIn(PortName port, int mask = 0xFFFFFFFF) {
+ port_init(&_port, port, mask, PIN_INPUT);
+ }
+
+ /** Read the value currently output on the port
+ *
+ * @returns
+ * An integer with each bit corresponding to associated port pin setting
+ */
+ int read() {
+ return port_read(&_port);
+ }
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode mode) {
+ port_mode(&_port, mode);
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+
+private:
+ port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortInOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortInOut.h
new file mode 100644
index 000000000..cca755126
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortInOut.h
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTINOUT_H
+#define MBED_PORTINOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PORTINOUT
+
+#include "port_api.h"
+
+namespace mbed {
+
+/** A multiple pin digital in/out used to set/read multiple bi-directional pins
+ */
+class PortInOut {
+public:
+
+ /** Create an PortInOut, connected to the specified port
+ *
+ * @param port Port to connect to (Port0-Port5)
+ * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+ */
+ PortInOut(PortName port, int mask = 0xFFFFFFFF) {
+ port_init(&_port, port, mask, PIN_INPUT);
+ }
+
+ /** Write the value to the output port
+ *
+ * @param value An integer specifying a bit to write for every corresponding port pin
+ */
+ void write(int value) {
+ port_write(&_port, value);
+ }
+
+ /** Read the value currently output on the port
+ *
+ * @returns
+ * An integer with each bit corresponding to associated port pin setting
+ */
+ int read() {
+ return port_read(&_port);
+ }
+
+ /** Set as an output
+ */
+ void output() {
+ port_dir(&_port, PIN_OUTPUT);
+ }
+
+ /** Set as an input
+ */
+ void input() {
+ port_dir(&_port, PIN_INPUT);
+ }
+
+ /** Set the input pin mode
+ *
+ * @param mode PullUp, PullDown, PullNone, OpenDrain
+ */
+ void mode(PinMode mode) {
+ port_mode(&_port, mode);
+ }
+
+ /** A shorthand for write()
+ */
+ PortInOut& operator= (int value) {
+ write(value);
+ return *this;
+ }
+
+ PortInOut& operator= (PortInOut& rhs) {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+
+private:
+ port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortOut.h
new file mode 100644
index 000000000..bab5fe0c6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PortOut.h
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTOUT_H
+#define MBED_PORTOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PORTOUT
+
+#include "port_api.h"
+
+namespace mbed {
+/** A multiple pin digital out
+ *
+ * Example:
+ * @code
+ * // Toggle all four LEDs
+ *
+ * #include "mbed.h"
+ *
+ * // LED1 = P1.18 LED2 = P1.20 LED3 = P1.21 LED4 = P1.23
+ * #define LED_MASK 0x00B40000
+ *
+ * PortOut ledport(Port1, LED_MASK);
+ *
+ * int main() {
+ * while(1) {
+ * ledport = LED_MASK;
+ * wait(1);
+ * ledport = 0;
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ */
+class PortOut {
+public:
+
+ /** Create an PortOut, connected to the specified port
+ *
+ * @param port Port to connect to (Port0-Port5)
+ * @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+ */
+ PortOut(PortName port, int mask = 0xFFFFFFFF) {
+ port_init(&_port, port, mask, PIN_OUTPUT);
+ }
+
+ /** Write the value to the output port
+ *
+ * @param value An integer specifying a bit to write for every corresponding PortOut pin
+ */
+ void write(int value) {
+ port_write(&_port, value);
+ }
+
+ /** Read the value currently output on the port
+ *
+ * @returns
+ * An integer with each bit corresponding to associated PortOut pin setting
+ */
+ int read() {
+ return port_read(&_port);
+ }
+
+ /** A shorthand for write()
+ */
+ PortOut& operator= (int value) {
+ write(value);
+ return *this;
+ }
+
+ PortOut& operator= (PortOut& rhs) {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** A shorthand for read()
+ */
+ operator int() {
+ return read();
+ }
+
+private:
+ port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PwmOut.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PwmOut.h
new file mode 100644
index 000000000..9e8c0bdf2
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/PwmOut.h
@@ -0,0 +1,158 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_H
+#define MBED_PWMOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PWMOUT
+#include "pwmout_api.h"
+
+namespace mbed {
+
+/** A pulse-width modulation digital output
+ *
+ * Example
+ * @code
+ * // Fade a led on.
+ * #include "mbed.h"
+ *
+ * PwmOut led(LED1);
+ *
+ * int main() {
+ * while(1) {
+ * led = led + 0.01;
+ * wait(0.2);
+ * if(led == 1.0) {
+ * led = 0;
+ * }
+ * }
+ * }
+ * @endcode
+ *
+ * @note
+ * On the LPC1768 and LPC2368, the PWMs all share the same
+ * period - if you change the period for one, you change it for all.
+ * Although routines that change the period maintain the duty cycle
+ * for its PWM, all other PWMs will require their duty cycle to be
+ * refreshed.
+ */
+class PwmOut {
+
+public:
+
+ /** Create a PwmOut connected to the specified pin
+ *
+ * @param pin PwmOut pin to connect to
+ */
+ PwmOut(PinName pin) {
+ pwmout_init(&_pwm, pin);
+ }
+
+ /** Set the ouput duty-cycle, specified as a percentage (float)
+ *
+ * @param value A floating-point value representing the output duty-cycle,
+ * specified as a percentage. The value should lie between
+ * 0.0f (representing on 0%) and 1.0f (representing on 100%).
+ * Values outside this range will be saturated to 0.0f or 1.0f.
+ */
+ void write(float value) {
+ pwmout_write(&_pwm, value);
+ }
+
+ /** Return the current output duty-cycle setting, measured as a percentage (float)
+ *
+ * @returns
+ * A floating-point value representing the current duty-cycle being output on the pin,
+ * measured as a percentage. The returned value will lie between
+ * 0.0f (representing on 0%) and 1.0f (representing on 100%).
+ *
+ * @note
+ * This value may not match exactly the value set by a previous <write>.
+ */
+ float read() {
+ return pwmout_read(&_pwm);
+ }
+
+ /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
+ *
+ * @note
+ * The resolution is currently in microseconds; periods smaller than this
+ * will be set to zero.
+ */
+ void period(float seconds) {
+ pwmout_period(&_pwm, seconds);
+ }
+
+ /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
+ */
+ void period_ms(int ms) {
+ pwmout_period_ms(&_pwm, ms);
+ }
+
+ /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
+ */
+ void period_us(int us) {
+ pwmout_period_us(&_pwm, us);
+ }
+
+ /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
+ */
+ void pulsewidth(float seconds) {
+ pwmout_pulsewidth(&_pwm, seconds);
+ }
+
+ /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
+ */
+ void pulsewidth_ms(int ms) {
+ pwmout_pulsewidth_ms(&_pwm, ms);
+ }
+
+ /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
+ */
+ void pulsewidth_us(int us) {
+ pwmout_pulsewidth_us(&_pwm, us);
+ }
+
+#ifdef MBED_OPERATORS
+ /** A operator shorthand for write()
+ */
+ PwmOut& operator= (float value) {
+ write(value);
+ return *this;
+ }
+
+ PwmOut& operator= (PwmOut& rhs) {
+ write(rhs.read());
+ return *this;
+ }
+
+ /** An operator shorthand for read()
+ */
+ operator float() {
+ return read();
+ }
+#endif
+
+protected:
+ pwmout_t _pwm;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/RawSerial.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/RawSerial.h
new file mode 100644
index 000000000..a5182bb64
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/RawSerial.h
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RAW_SERIAL_H
+#define MBED_RAW_SERIAL_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "SerialBase.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A serial port (UART) for communication with other serial devices
+ * This is a variation of the Serial class that doesn't use streams,
+ * thus making it safe to use in interrupt handlers with the RTOS.
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * Example:
+ * @code
+ * // Send a char to the PC
+ *
+ * #include "mbed.h"
+ *
+ * RawSerial pc(USBTX, USBRX);
+ *
+ * int main() {
+ * pc.putc('A');
+ * }
+ * @endcode
+ */
+class RawSerial: public SerialBase {
+
+public:
+ /** Create a RawSerial port, connected to the specified transmit and receive pins
+ *
+ * @param tx Transmit pin
+ * @param rx Receive pin
+ *
+ * @note
+ * Either tx or rx may be specified as NC if unused
+ */
+ RawSerial(PinName tx, PinName rx);
+
+ /** Write a char to the serial port
+ *
+ * @param c The char to write
+ *
+ * @returns The written char or -1 if an error occured
+ */
+ int putc(int c);
+
+ /** Read a char from the serial port
+ *
+ * @returns The char read from the serial port
+ */
+ int getc();
+
+ /** Write a string to the serial port
+ *
+ * @param str The string to write
+ *
+ * @returns 0 if the write succeeds, EOF for error
+ */
+ int puts(const char *str);
+
+ int printf(const char *format, ...);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SPI.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SPI.h
new file mode 100644
index 000000000..7fa1a6be8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SPI.h
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_H
+#define MBED_SPI_H
+
+#include "platform.h"
+
+#if DEVICE_SPI
+
+#include "spi_api.h"
+
+namespace mbed {
+
+/** A SPI Master, used for communicating with SPI slave devices
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * Most SPI devices will also require Chip Select and Reset signals. These
+ * can be controlled using <DigitalOut> pins
+ *
+ * Example:
+ * @code
+ * // Send a byte to a SPI slave, and record the response
+ *
+ * #include "mbed.h"
+ *
+ * SPI device(p5, p6, p7); // mosi, miso, sclk
+ *
+ * int main() {
+ * int response = device.write(0xFF);
+ * }
+ * @endcode
+ */
+class SPI {
+
+public:
+
+ /** Create a SPI master connected to the specified pins
+ *
+ * Pin Options:
+ * (5, 6, 7) or (11, 12, 13)
+ *
+ * mosi or miso can be specfied as NC if not used
+ *
+ * @param mosi SPI Master Out, Slave In pin
+ * @param miso SPI Master In, Slave Out pin
+ * @param sclk SPI Clock pin
+ */
+ SPI(PinName mosi, PinName miso, PinName sclk, PinName _unused=NC);
+
+ /** Configure the data transmission format
+ *
+ * @param bits Number of bits per SPI frame (4 - 16)
+ * @param mode Clock polarity and phase mode (0 - 3)
+ *
+ * @code
+ * mode | POL PHA
+ * -----+--------
+ * 0 | 0 0
+ * 1 | 0 1
+ * 2 | 1 0
+ * 3 | 1 1
+ * @endcode
+ */
+ void format(int bits, int mode = 0);
+
+ /** Set the spi bus clock frequency
+ *
+ * @param hz SCLK frequency in hz (default = 1MHz)
+ */
+ void frequency(int hz = 1000000);
+
+ /** Write to the SPI Slave and return the response
+ *
+ * @param value Data to be sent to the SPI slave
+ *
+ * @returns
+ * Response from the SPI slave
+ */
+ virtual int write(int value);
+
+public:
+ virtual ~SPI() {
+ }
+
+protected:
+ spi_t _spi;
+
+ void aquire(void);
+ static SPI *_owner;
+ int _bits;
+ int _mode;
+ int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SPISlave.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SPISlave.h
new file mode 100644
index 000000000..d06c7e1b4
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SPISlave.h
@@ -0,0 +1,126 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPISLAVE_H
+#define MBED_SPISLAVE_H
+
+#include "platform.h"
+
+#if DEVICE_SPISLAVE
+
+#include "spi_api.h"
+
+namespace mbed {
+
+/** A SPI slave, used for communicating with a SPI Master device
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * Example:
+ * @code
+ * // Reply to a SPI master as slave
+ *
+ * #include "mbed.h"
+ *
+ * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ *
+ * int main() {
+ * device.reply(0x00); // Prime SPI with first reply
+ * while(1) {
+ * if(device.receive()) {
+ * int v = device.read(); // Read byte from master
+ * v = (v + 1) % 0x100; // Add one to it, modulo 256
+ * device.reply(v); // Make this the next reply
+ * }
+ * }
+ * }
+ * @endcode
+ */
+class SPISlave {
+
+public:
+
+ /** Create a SPI slave connected to the specified pins
+ *
+ * Pin Options:
+ * (5, 6, 7i, 8) or (11, 12, 13, 14)
+ *
+ * mosi or miso can be specfied as NC if not used
+ *
+ * @param mosi SPI Master Out, Slave In pin
+ * @param miso SPI Master In, Slave Out pin
+ * @param sclk SPI Clock pin
+ * @param ssel SPI chip select pin
+ * @param name (optional) A string to identify the object
+ */
+ SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
+
+ /** Configure the data transmission format
+ *
+ * @param bits Number of bits per SPI frame (4 - 16)
+ * @param mode Clock polarity and phase mode (0 - 3)
+ *
+ * @code
+ * mode | POL PHA
+ * -----+--------
+ * 0 | 0 0
+ * 1 | 0 1
+ * 2 | 1 0
+ * 3 | 1 1
+ * @endcode
+ */
+ void format(int bits, int mode = 0);
+
+ /** Set the spi bus clock frequency
+ *
+ * @param hz SCLK frequency in hz (default = 1MHz)
+ */
+ void frequency(int hz = 1000000);
+
+ /** Polls the SPI to see if data has been received
+ *
+ * @returns
+ * 0 if no data,
+ * 1 otherwise
+ */
+ int receive(void);
+
+ /** Retrieve data from receive buffer as slave
+ *
+ * @returns
+ * the data in the receive buffer
+ */
+ int read(void);
+
+ /** Fill the transmission buffer with the value to be written out
+ * as slave on the next received message from the master.
+ *
+ * @param value the data to be transmitted next
+ */
+ void reply(int value);
+
+protected:
+ spi_t _spi;
+
+ int _bits;
+ int _mode;
+ int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Serial.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Serial.h
new file mode 100644
index 000000000..edd762d01
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Serial.h
@@ -0,0 +1,69 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_H
+#define MBED_SERIAL_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "Stream.h"
+#include "SerialBase.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A serial port (UART) for communication with other serial devices
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * Example:
+ * @code
+ * // Print "Hello World" to the PC
+ *
+ * #include "mbed.h"
+ *
+ * Serial pc(USBTX, USBRX);
+ *
+ * int main() {
+ * pc.printf("Hello World\n");
+ * }
+ * @endcode
+ */
+class Serial : public SerialBase, public Stream {
+
+public:
+ /** Create a Serial port, connected to the specified transmit and receive pins
+ *
+ * @param tx Transmit pin
+ * @param rx Receive pin
+ *
+ * @note
+ * Either tx or rx may be specified as NC if unused
+ */
+ Serial(PinName tx, PinName rx, const char *name=NULL);
+
+protected:
+ virtual int _getc();
+ virtual int _putc(int c);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SerialBase.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SerialBase.h
new file mode 100644
index 000000000..07bc4b463
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/SerialBase.h
@@ -0,0 +1,139 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIALBASE_H
+#define MBED_SERIALBASE_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "Stream.h"
+#include "FunctionPointer.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A base class for serial port implementations
+ * Can't be instantiated directly (use Serial or RawSerial)
+ */
+class SerialBase {
+
+public:
+ /** Set the baud rate of the serial port
+ *
+ * @param baudrate The baudrate of the serial port (default = 9600).
+ */
+ void baud(int baudrate);
+
+ enum Parity {
+ None = 0,
+ Odd,
+ Even,
+ Forced1,
+ Forced0
+ };
+
+ enum IrqType {
+ RxIrq = 0,
+ TxIrq
+ };
+
+ enum Flow {
+ Disabled = 0,
+ RTS,
+ CTS,
+ RTSCTS
+ };
+
+ /** Set the transmission format used by the serial port
+ *
+ * @param bits The number of bits in a word (5-8; default = 8)
+ * @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None)
+ * @param stop The number of stop bits (1 or 2; default = 1)
+ */
+ void format(int bits=8, Parity parity=SerialBase::None, int stop_bits=1);
+
+ /** Determine if there is a character available to read
+ *
+ * @returns
+ * 1 if there is a character available to read,
+ * 0 otherwise
+ */
+ int readable();
+
+ /** Determine if there is space available to write a character
+ *
+ * @returns
+ * 1 if there is space to write a character,
+ * 0 otherwise
+ */
+ int writeable();
+
+ /** Attach a function to call whenever a serial interrupt is generated
+ *
+ * @param fptr A pointer to a void function, or 0 to set as none
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ */
+ void attach(void (*fptr)(void), IrqType type=RxIrq);
+
+ /** Attach a member function to call whenever a serial interrupt is generated
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+ */
+ template<typename T>
+ void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+ if((mptr != NULL) && (tptr != NULL)) {
+ _irq[type].attach(tptr, mptr);
+ serial_irq_set(&_serial, (SerialIrq)type, 1);
+ }
+ }
+
+ /** Generate a break condition on the serial line
+ */
+ void send_break();
+
+#if DEVICE_SERIAL_FC
+ /** Set the flow control type on the serial port
+ *
+ * @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
+ * @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
+ * @param flow2 the second flow control pin (CTS for RTSCTS)
+ */
+ void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
+#endif
+
+ static void _irq_handler(uint32_t id, SerialIrq irq_type);
+
+protected:
+ SerialBase(PinName tx, PinName rx);
+ virtual ~SerialBase() {
+ }
+
+ int _base_getc();
+ int _base_putc(int c);
+
+ serial_t _serial;
+ FunctionPointer _irq[2];
+ int _baud;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Stream.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Stream.h
new file mode 100644
index 000000000..a57053e67
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Stream.h
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_STREAM_H
+#define MBED_STREAM_H
+
+#include "platform.h"
+#include "FileLike.h"
+
+namespace mbed {
+
+extern void mbed_set_unbuffered_stream(FILE *_file);
+extern int mbed_getc(FILE *_file);
+extern char* mbed_gets(char *s, int size, FILE *_file);
+
+class Stream : public FileLike {
+
+public:
+ Stream(const char *name=NULL);
+ virtual ~Stream();
+
+ int putc(int c);
+ int puts(const char *s);
+ int getc();
+ char *gets(char *s, int size);
+ int printf(const char* format, ...);
+ int scanf(const char* format, ...);
+
+ operator std::FILE*() {return _file;}
+
+protected:
+ virtual int close();
+ virtual ssize_t write(const void* buffer, size_t length);
+ virtual ssize_t read(void* buffer, size_t length);
+ virtual off_t lseek(off_t offset, int whence);
+ virtual int isatty();
+ virtual int fsync();
+ virtual off_t flen();
+
+ virtual int _putc(int c) = 0;
+ virtual int _getc() = 0;
+
+ std::FILE *_file;
+
+ /* disallow copy constructor and assignment operators */
+private:
+ Stream(const Stream&);
+ Stream & operator = (const Stream&);
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Ticker.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Ticker.h
new file mode 100644
index 000000000..43b70cbfc
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Ticker.h
@@ -0,0 +1,122 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_H
+#define MBED_TICKER_H
+
+#include "TimerEvent.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** A Ticker is used to call a function at a recurring interval
+ *
+ * You can use as many seperate Ticker objects as you require.
+ *
+ * Example:
+ * @code
+ * // Toggle the blinking led after 5 seconds
+ *
+ * #include "mbed.h"
+ *
+ * Ticker timer;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * int flip = 0;
+ *
+ * void attime() {
+ * flip = !flip;
+ * }
+ *
+ * int main() {
+ * timer.attach(&attime, 5);
+ * while(1) {
+ * if(flip == 0) {
+ * led1 = !led1;
+ * } else {
+ * led2 = !led2;
+ * }
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ */
+class Ticker : public TimerEvent {
+
+public:
+
+ /** Attach a function to be called by the Ticker, specifiying the interval in seconds
+ *
+ * @param fptr pointer to the function to be called
+ * @param t the time between calls in seconds
+ */
+ void attach(void (*fptr)(void), float t) {
+ attach_us(fptr, t * 1000000.0f);
+ }
+
+ /** Attach a member function to be called by the Ticker, specifiying the interval in seconds
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param t the time between calls in seconds
+ */
+ template<typename T>
+ void attach(T* tptr, void (T::*mptr)(void), float t) {
+ attach_us(tptr, mptr, t * 1000000.0f);
+ }
+
+ /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
+ *
+ * @param fptr pointer to the function to be called
+ * @param t the time between calls in micro-seconds
+ */
+ void attach_us(void (*fptr)(void), timestamp_t t) {
+ _function.attach(fptr);
+ setup(t);
+ }
+
+ /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
+ *
+ * @param tptr pointer to the object to call the member function on
+ * @param mptr pointer to the member function to be called
+ * @param t the time between calls in micro-seconds
+ */
+ template<typename T>
+ void attach_us(T* tptr, void (T::*mptr)(void), timestamp_t t) {
+ _function.attach(tptr, mptr);
+ setup(t);
+ }
+
+ virtual ~Ticker() {
+ detach();
+ }
+
+ /** Detach the function
+ */
+ void detach();
+
+protected:
+ void setup(timestamp_t t);
+ virtual void handler();
+
+protected:
+ timestamp_t _delay; /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
+ FunctionPointer _function; /**< Callback. */
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Timeout.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Timeout.h
new file mode 100644
index 000000000..e145d9a77
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Timeout.h
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEOUT_H
+#define MBED_TIMEOUT_H
+
+#include "Ticker.h"
+
+namespace mbed {
+
+/** A Timeout is used to call a function at a point in the future
+ *
+ * You can use as many seperate Timeout objects as you require.
+ *
+ * Example:
+ * @code
+ * // Blink until timeout.
+ *
+ * #include "mbed.h"
+ *
+ * Timeout timeout;
+ * DigitalOut led(LED1);
+ *
+ * int on = 1;
+ *
+ * void attimeout() {
+ * on = 0;
+ * }
+ *
+ * int main() {
+ * timeout.attach(&attimeout, 5);
+ * while(on) {
+ * led = !led;
+ * wait(0.2);
+ * }
+ * }
+ * @endcode
+ */
+class Timeout : public Ticker {
+
+protected:
+ virtual void handler();
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Timer.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Timer.h
new file mode 100644
index 000000000..aedf0377e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/Timer.h
@@ -0,0 +1,88 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMER_H
+#define MBED_TIMER_H
+
+#include "platform.h"
+
+namespace mbed {
+
+/** A general purpose timer
+ *
+ * Example:
+ * @code
+ * // Count the time to toggle a LED
+ *
+ * #include "mbed.h"
+ *
+ * Timer timer;
+ * DigitalOut led(LED1);
+ * int begin, end;
+ *
+ * int main() {
+ * timer.start();
+ * begin = timer.read_us();
+ * led = !led;
+ * end = timer.read_us();
+ * printf("Toggle the led takes %d us", end - begin);
+ * }
+ * @endcode
+ */
+class Timer {
+
+public:
+ Timer();
+
+ /** Start the timer
+ */
+ void start();
+
+ /** Stop the timer
+ */
+ void stop();
+
+ /** Reset the timer to 0.
+ *
+ * If it was already counting, it will continue
+ */
+ void reset();
+
+ /** Get the time passed in seconds
+ */
+ float read();
+
+ /** Get the time passed in mili-seconds
+ */
+ int read_ms();
+
+ /** Get the time passed in micro-seconds
+ */
+ int read_us();
+
+#ifdef MBED_OPERATORS
+ operator float();
+#endif
+
+protected:
+ int slicetime();
+ int _running; // whether the timer is running
+ unsigned int _start; // the start time of the latest slice
+ int _time; // any accumulated time from previous slices
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/TimerEvent.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/TimerEvent.h
new file mode 100644
index 000000000..4ec7056a7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/TimerEvent.h
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEREVENT_H
+#define MBED_TIMEREVENT_H
+
+#include "us_ticker_api.h"
+
+namespace mbed {
+
+/** Base abstraction for timer interrupts
+*/
+class TimerEvent {
+public:
+ TimerEvent();
+
+ /** The handler registered with the underlying timer interrupt
+ */
+ static void irq(uint32_t id);
+
+ /** Destruction removes it...
+ */
+ virtual ~TimerEvent();
+
+protected:
+ // The handler called to service the timer event of the derived class
+ virtual void handler() = 0;
+
+ // insert in to linked list
+ void insert(timestamp_t timestamp);
+
+ // remove from linked list, if in it
+ void remove();
+
+ ticker_event_t event;
+};
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/can_helper.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/can_helper.h
new file mode 100644
index 000000000..e427250e0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/can_helper.h
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_HELPER_H
+#define MBED_CAN_HELPER_H
+
+#if DEVICE_CAN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum CANFormat {
+ CANStandard = 0,
+ CANExtended = 1,
+ CANAny = 2
+};
+typedef enum CANFormat CANFormat;
+
+enum CANType {
+ CANData = 0,
+ CANRemote = 1
+};
+typedef enum CANType CANType;
+
+struct CAN_Message {
+ unsigned int id; // 29 bit identifier
+ unsigned char data[8]; // Data field
+ unsigned char len; // Length of data field in bytes
+ CANFormat format; // 0 - STANDARD, 1- EXTENDED IDENTIFIER
+ CANType type; // 0 - DATA FRAME, 1 - REMOTE FRAME
+};
+typedef struct CAN_Message CAN_Message;
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
+
+#endif // MBED_CAN_HELPER_H
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed.h
new file mode 100644
index 000000000..51b044d11
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed.h
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_H
+#define MBED_H
+
+#define MBED_LIBRARY_VERSION 97
+
+#include "platform.h"
+
+// Useful C libraries
+#include <math.h>
+#include <time.h>
+
+// mbed Debug libraries
+#include "mbed_error.h"
+#include "mbed_interface.h"
+
+// mbed Peripheral components
+#include "DigitalIn.h"
+#include "DigitalOut.h"
+#include "DigitalInOut.h"
+#include "BusIn.h"
+#include "BusOut.h"
+#include "BusInOut.h"
+#include "PortIn.h"
+#include "PortInOut.h"
+#include "PortOut.h"
+#include "AnalogIn.h"
+#include "AnalogOut.h"
+#include "PwmOut.h"
+#include "Serial.h"
+#include "SPI.h"
+#include "SPISlave.h"
+#include "I2C.h"
+#include "I2CSlave.h"
+#include "Ethernet.h"
+#include "CAN.h"
+#include "RawSerial.h"
+
+// mbed Internal components
+#include "Timer.h"
+#include "Ticker.h"
+#include "Timeout.h"
+#include "LocalFileSystem.h"
+#include "InterruptIn.h"
+#include "wait_api.h"
+#include "sleep_api.h"
+#include "rtc_time.h"
+
+using namespace mbed;
+using namespace std;
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_assert.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_assert.h
new file mode 100644
index 000000000..1bcfb092b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_assert.h
@@ -0,0 +1,50 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ASSERT_H
+#define MBED_ASSERT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.
+ * This function is active only if NDEBUG is not defined prior to including this
+ * assert header file.
+ * In case of MBED_ASSERT failing condition, the assertation message is printed
+ * to stderr and mbed_die() is called.
+ * @param expr Expresion to be checked.
+ * @param file File where assertation failed.
+ * @param line Failing assertation line number.
+ */
+void mbed_assert_internal(const char *expr, const char *file, int line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifdef NDEBUG
+#define MBED_ASSERT(expr) ((void)0)
+
+#else
+#define MBED_ASSERT(expr) \
+do { \
+ if (!(expr)) { \
+ mbed_assert_internal(#expr, __FILE__, __LINE__); \
+ } \
+} while (0)
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_debug.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_debug.h
new file mode 100644
index 000000000..2c8a34673
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_debug.h
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEBUG_H
+#define MBED_DEBUG_H
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#include <stdarg.h>
+
+/** Output a debug message
+ *
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug(const char *format, ...) {
+ va_list args;
+ va_start(args, format);
+ vfprintf(stderr, format, args);
+ va_end(args);
+}
+
+/** Conditionally output a debug message
+ *
+ * NOTE: If the condition is constant false (!= 1) and the compiler optimization
+ * level is greater than 0, then the whole function will be compiled away.
+ *
+ * @param condition output only if condition is true (== 1)
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug_if(int condition, const char *format, ...) {
+ if (condition == 1) {
+ va_list args;
+ va_start(args, format);
+ vfprintf(stderr, format, args);
+ va_end(args);
+ }
+}
+
+#else
+static inline void debug(const char *format, ...) {}
+static inline void debug_if(int condition, const char *format, ...) {}
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_error.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_error.h
new file mode 100644
index 000000000..3a403586d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_error.h
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ERROR_H
+#define MBED_ERROR_H
+
+/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
+ *
+ * @code
+ * #error "That shouldn't have happened!"
+ * @endcode
+ *
+ * If the compiler evaluates this line, it will report the error and stop the compile.
+ *
+ * For example, you could use this to check some user-defined compile-time variables:
+ *
+ * @code
+ * #define NUM_PORTS 7
+ * #if (NUM_PORTS > 4)
+ * #error "NUM_PORTS must be less than 4"
+ * #endif
+ * @endcode
+ *
+ * Reporting Run-Time Errors:
+ * To generate a fatal run-time error, you can use the mbed error() function.
+ *
+ * @code
+ * error("That shouldn't have happened!");
+ * @endcode
+ *
+ * If the mbed running the program executes this function, it will print the
+ * message via the USB serial port, and then die with the blue lights of death!
+ *
+ * The message can use printf-style formatting, so you can report variables in the
+ * message too. For example, you could use this to check a run-time condition:
+ *
+ * @code
+ * if(x >= 5) {
+ * error("expected x to be less than 5, but got %d", x);
+ * }
+ * #endcode
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void error(const char* format, ...);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_interface.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_interface.h
new file mode 100644
index 000000000..a93a4d33d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/mbed_interface.h
@@ -0,0 +1,114 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERFACE_H
+#define MBED_INTERFACE_H
+
+#include "device.h"
+
+/* Mbed interface mac address
+ * if MBED_MAC_ADD_x are zero, interface uid sets mac address,
+ * otherwise MAC_ADD_x are used.
+ */
+#define MBED_MAC_ADDR_INTERFACE 0x00
+#define MBED_MAC_ADDR_0 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_1 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_2 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_3 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_4 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_5 MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+/** Functions to control the mbed interface
+ *
+ * mbed Microcontrollers have a built-in interface to provide functionality such as
+ * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
+ * system. These functions provide means to control the interface suing semihost
+ * calls it supports.
+ */
+
+/** Determine whether the mbed interface is connected, based on whether debug is enabled
+ *
+ * @returns
+ * 1 if interface is connected,
+ * 0 otherwise
+ */
+int mbed_interface_connected(void);
+
+/** Instruct the mbed interface to reset, as if the reset button had been pressed
+ *
+ * @returns
+ * 1 if successful,
+ * 0 otherwise (e.g. interface not present)
+ */
+int mbed_interface_reset(void);
+
+/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
+ * The interface will still support the USB serial aspect
+ *
+ * @returns
+ * 0 if successful,
+ * -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_disconnect(void);
+
+/** This will disconnect the debug aspect of the interface, and if the USB cable is not
+ * connected, also power down the interface. If the USB cable is connected, the interface
+ * will remain powered up and visible to the host
+ *
+ * @returns
+ * 0 if successful,
+ * -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_powerdown(void);
+
+/** This returns a string containing the 32-character UID of the mbed interface
+ * This is a weak function that can be overwritten if required
+ *
+ * @param uid A 33-byte array to write the null terminated 32-byte string
+ *
+ * @returns
+ * 0 if successful,
+ * -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_uid(char *uid);
+
+#endif
+
+/** This returns a unique 6-byte MAC address, based on the interface UID
+ * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
+ *
+ * This is a weak function that can be overwritten if you want to provide your own mechanism to
+ * provide a MAC address.
+ *
+ * @param mac A 6-byte array to write the MAC address
+ */
+void mbed_mac_address(char *mac);
+
+/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
+ */
+void mbed_die(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/platform.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/platform.h
new file mode 100644
index 000000000..85e44e57b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/platform.h
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PLATFORM_H
+#define MBED_PLATFORM_H
+
+#define MBED_OPERATORS 1
+
+#include "device.h"
+#include "PinNames.h"
+#include "PeripheralNames.h"
+
+#include <cstddef>
+#include <cstdlib>
+#include <cstdio>
+#include <cstring>
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/rtc_time.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/rtc_time.h
new file mode 100644
index 000000000..565897366
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/rtc_time.h
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Implementation of the C time.h functions
+ *
+ * Provides mechanisms to set and read the current time, based
+ * on the microcontroller Real-Time Clock (RTC), plus some
+ * standard C manipulation and formating functions.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ * set_time(1256729737); // Set RTC time to Wed, 28 Oct 2009 11:35:37
+ *
+ * while(1) {
+ * time_t seconds = time(NULL);
+ *
+ * printf("Time as seconds since January 1, 1970 = %d\n", seconds);
+ *
+ * printf("Time as a basic string = %s", ctime(&seconds));
+ *
+ * char buffer[32];
+ * strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));
+ * printf("Time as a custom formatted string = %s", buffer);
+ *
+ * wait(1);
+ * }
+ * }
+ * @endcode
+ */
+
+/** Set the current time
+ *
+ * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)
+ * to the time represented by the number of seconds since January 1, 1970
+ * (the UNIX timestamp).
+ *
+ * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ * set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37
+ * }
+ * @endcode
+ */
+void set_time(time_t t);
+
+/** Attach an external RTC to be used for the C time functions
+ *
+ * Do not call this function from an interrupt while an RTC read/write operation may be occurring
+ *
+ * @param read_rtc pointer to function which returns current UNIX timestamp
+ * @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL
+ * @param init_rtc pointer to funtion which initializes RTC, can be NULL
+ * @param isenabled_rtc pointer to function wich returns if the rtc is enabled, can be NULL
+ */
+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void));
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/semihost_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/semihost_api.h
new file mode 100644
index 000000000..279f67160
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/semihost_api.h
@@ -0,0 +1,93 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SEMIHOST_H
+#define MBED_SEMIHOST_H
+
+#include "device.h"
+#include "toolchain.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+#ifndef __CC_ARM
+
+#if defined(__ICCARM__)
+inline int __semihost(int reason, const void *arg) {
+ return __semihosting(reason, (void*)arg);
+}
+#else
+
+#ifdef __thumb__
+# define AngelSWI 0xAB
+# define AngelSWIInsn "bkpt"
+# define AngelSWIAsm bkpt
+#else
+# define AngelSWI 0x123456
+# define AngelSWIInsn "swi"
+# define AngelSWIAsm swi
+#endif
+
+static inline int __semihost(int reason, const void *arg) {
+ int value;
+
+ asm volatile (
+ "mov r0, %1" "\n\t"
+ "mov r1, %2" "\n\t"
+ AngelSWIInsn " %a3" "\n\t"
+ "mov %0, r0"
+ : "=r" (value) /* output operands */
+ : "r" (reason), "r" (arg), "i" (AngelSWI) /* input operands */
+ : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" /* list of clobbered registers */
+ );
+
+ return value;
+}
+#endif
+#endif
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode);
+int semihost_close (FILEHANDLE fh);
+int semihost_read (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode);
+int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode);
+int semihost_ensure(FILEHANDLE fh);
+long semihost_flen (FILEHANDLE fh);
+int semihost_seek (FILEHANDLE fh, long position);
+int semihost_istty (FILEHANDLE fh);
+
+int semihost_remove(const char *name);
+int semihost_rename(const char *old_name, const char *new_name);
+#endif
+
+int semihost_uid(char *uid);
+int semihost_reset(void);
+int semihost_vbus(void);
+int semihost_powerdown(void);
+int semihost_exit(void);
+
+int semihost_connected(void);
+int semihost_disabledebug(void);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/toolchain.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/toolchain.h
new file mode 100644
index 000000000..b140643b3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/toolchain.h
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TOOLCHAIN_H
+#define MBED_TOOLCHAIN_H
+
+#if defined(TOOLCHAIN_ARM)
+#include <rt_sys.h>
+#endif
+
+#ifndef FILEHANDLE
+typedef int FILEHANDLE;
+#endif
+
+#if defined (__ICCARM__)
+# define WEAK __weak
+# define PACKED __packed
+#else
+# define WEAK __attribute__((weak))
+# define PACKED __attribute__((packed))
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/wait_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/wait_api.h
new file mode 100644
index 000000000..03c27141e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/api/wait_api.h
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_WAIT_API_H
+#define MBED_WAIT_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Generic wait functions.
+ *
+ * These provide simple NOP type wait capabilities.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * DigitalOut heartbeat(LED1);
+ *
+ * int main() {
+ * while (1) {
+ * heartbeat = 1;
+ * wait(0.5);
+ * heartbeat = 0;
+ * wait(0.5);
+ * }
+ * }
+ */
+
+/** Waits for a number of seconds, with microsecond resolution (within
+ * the accuracy of single precision floating point).
+ *
+ * @param s number of seconds to wait
+ */
+void wait(float s);
+
+/** Waits a number of milliseconds.
+ *
+ * @param ms the whole number of milliseconds to wait
+ */
+void wait_ms(int ms);
+
+/** Waits a number of microseconds.
+ *
+ * @param us the whole number of microseconds to wait
+ */
+void wait_us(int us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusIn.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusIn.cpp
new file mode 100644
index 000000000..ea67cbcb8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusIn.cpp
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusIn.h"
+#include "mbed_assert.h"
+
+namespace mbed {
+
+BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+ PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusIn::BusIn(PinName pins[16]) {
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusIn::~BusIn() {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ delete _pin[i];
+ }
+ }
+}
+
+int BusIn::read() {
+ int v = 0;
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ v |= _pin[i]->read() << i;
+ }
+ }
+ return v;
+}
+
+void BusIn::mode(PinMode pull) {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->mode(pull);
+ }
+ }
+}
+
+#ifdef MBED_OPERATORS
+BusIn::operator int() {
+ return read();
+}
+
+DigitalIn& BusIn::operator[] (int index) {
+ MBED_ASSERT(index >= 0 && index <= 16);
+ MBED_ASSERT(_pin[index]);
+ return *_pin[index];
+}
+
+#endif
+
+} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusInOut.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusInOut.cpp
new file mode 100644
index 000000000..5575f90d4
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusInOut.cpp
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusInOut.h"
+#include "mbed_assert.h"
+
+namespace mbed {
+
+BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+ PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusInOut::BusInOut(PinName pins[16]) {
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusInOut::~BusInOut() {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ delete _pin[i];
+ }
+ }
+}
+
+void BusInOut::write(int value) {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->write((value >> i) & 1);
+ }
+ }
+}
+
+int BusInOut::read() {
+ int v = 0;
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ v |= _pin[i]->read() << i;
+ }
+ }
+ return v;
+}
+
+void BusInOut::output() {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->output();
+ }
+ }
+}
+
+void BusInOut::input() {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->input();
+ }
+ }
+}
+
+void BusInOut::mode(PinMode pull) {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->mode(pull);
+ }
+ }
+}
+
+#ifdef MBED_OPERATORS
+BusInOut& BusInOut::operator= (int v) {
+ write(v);
+ return *this;
+}
+
+BusInOut& BusInOut::operator= (BusInOut& rhs) {
+ write(rhs.read());
+ return *this;
+}
+
+DigitalInOut& BusInOut::operator[] (int index) {
+ MBED_ASSERT(index >= 0 && index <= 16);
+ MBED_ASSERT(_pin[index]);
+ return *_pin[index];
+}
+
+BusInOut::operator int() {
+ return read();
+}
+#endif
+
+} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusOut.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusOut.cpp
new file mode 100644
index 000000000..4277c5727
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/BusOut.cpp
@@ -0,0 +1,91 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusOut.h"
+#include "mbed_assert.h"
+
+namespace mbed {
+
+BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+ PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusOut::BusOut(PinName pins[16]) {
+ _nc_mask = 0;
+ for (int i=0; i<16; i++) {
+ _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+ if (pins[i] != NC) {
+ _nc_mask |= (1 << i);
+ }
+ }
+}
+
+BusOut::~BusOut() {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ delete _pin[i];
+ }
+ }
+}
+
+void BusOut::write(int value) {
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ _pin[i]->write((value >> i) & 1);
+ }
+ }
+}
+
+int BusOut::read() {
+ int v = 0;
+ for (int i=0; i<16; i++) {
+ if (_pin[i] != 0) {
+ v |= _pin[i]->read() << i;
+ }
+ }
+ return v;
+}
+
+#ifdef MBED_OPERATORS
+BusOut& BusOut::operator= (int v) {
+ write(v);
+ return *this;
+}
+
+BusOut& BusOut::operator= (BusOut& rhs) {
+ write(rhs.read());
+ return *this;
+}
+
+DigitalOut& BusOut::operator[] (int index) {
+ MBED_ASSERT(index >= 0 && index <= 16);
+ MBED_ASSERT(_pin[index]);
+ return *_pin[index];
+}
+
+BusOut::operator int() {
+ return read();
+}
+#endif
+
+} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/CAN.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/CAN.cpp
new file mode 100644
index 000000000..407e00bf1
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/CAN.cpp
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "CAN.h"
+
+#if DEVICE_CAN
+
+#include "cmsis.h"
+
+namespace mbed {
+
+CAN::CAN(PinName rd, PinName td) : _can(), _irq() {
+ can_init(&_can, rd, td);
+ can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
+}
+
+CAN::~CAN() {
+ can_irq_free(&_can);
+ can_free(&_can);
+}
+
+int CAN::frequency(int f) {
+ return can_frequency(&_can, f);
+}
+
+int CAN::write(CANMessage msg) {
+ return can_write(&_can, msg, 0);
+}
+
+int CAN::read(CANMessage &msg, int handle) {
+ return can_read(&_can, &msg, handle);
+}
+
+void CAN::reset() {
+ can_reset(&_can);
+}
+
+unsigned char CAN::rderror() {
+ return can_rderror(&_can);
+}
+
+unsigned char CAN::tderror() {
+ return can_tderror(&_can);
+}
+
+void CAN::monitor(bool silent) {
+ can_monitor(&_can, (silent) ? 1 : 0);
+}
+
+int CAN::mode(Mode mode) {
+ return can_mode(&_can, (CanMode)mode);
+}
+
+int CAN::filter(unsigned int id, unsigned int mask, CANFormat format, int handle) {
+ return can_filter(&_can, id, mask, format, handle);
+}
+
+void CAN::attach(void (*fptr)(void), IrqType type) {
+ if (fptr) {
+ _irq[(CanIrqType)type].attach(fptr);
+ can_irq_set(&_can, (CanIrqType)type, 1);
+ } else {
+ can_irq_set(&_can, (CanIrqType)type, 0);
+ }
+}
+
+void CAN::_irq_handler(uint32_t id, CanIrqType type) {
+ CAN *handler = (CAN*)id;
+ handler->_irq[type].call();
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/CallChain.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/CallChain.cpp
new file mode 100644
index 000000000..e95090305
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/CallChain.cpp
@@ -0,0 +1,90 @@
+#include "CallChain.h"
+#include "cmsis.h"
+
+namespace mbed {
+
+CallChain::CallChain(int size) : _chain(), _size(size), _elements(0) {
+ _chain = new pFunctionPointer_t[size]();
+}
+
+CallChain::~CallChain() {
+ clear();
+ delete _chain;
+}
+
+pFunctionPointer_t CallChain::add(void (*function)(void)) {
+ return common_add(new FunctionPointer(function));
+}
+
+pFunctionPointer_t CallChain::add_front(void (*function)(void)) {
+ return common_add_front(new FunctionPointer(function));
+}
+
+int CallChain::size() const {
+ return _elements;
+}
+
+pFunctionPointer_t CallChain::get(int i) const {
+ if (i < 0 || i >= _elements)
+ return NULL;
+ return _chain[i];
+}
+
+int CallChain::find(pFunctionPointer_t f) const {
+ for (int i = 0; i < _elements; i++)
+ if (f == _chain[i])
+ return i;
+ return -1;
+}
+
+void CallChain::clear() {
+ for(int i = 0; i < _elements; i ++) {
+ delete _chain[i];
+ _chain[i] = NULL;
+ }
+ _elements = 0;
+}
+
+bool CallChain::remove(pFunctionPointer_t f) {
+ int i;
+
+ if ((i = find(f)) == -1)
+ return false;
+ if (i != _elements - 1)
+ memmove(_chain + i, _chain + i + 1, (_elements - i - 1) * sizeof(pFunctionPointer_t));
+ delete f;
+ _elements --;
+ return true;
+}
+
+void CallChain::call() {
+ for(int i = 0; i < _elements; i++)
+ _chain[i]->call();
+}
+
+void CallChain::_check_size() {
+ if (_elements < _size)
+ return;
+ _size = (_size < 4) ? 4 : _size + 4;
+ pFunctionPointer_t* new_chain = new pFunctionPointer_t[_size]();
+ memcpy(new_chain, _chain, _elements * sizeof(pFunctionPointer_t));
+ delete _chain;
+ _chain = new_chain;
+}
+
+pFunctionPointer_t CallChain::common_add(pFunctionPointer_t pf) {
+ _check_size();
+ _chain[_elements] = pf;
+ _elements ++;
+ return pf;
+}
+
+pFunctionPointer_t CallChain::common_add_front(pFunctionPointer_t pf) {
+ _check_size();
+ memmove(_chain + 1, _chain, _elements * sizeof(pFunctionPointer_t));
+ _chain[0] = pf;
+ _elements ++;
+ return pf;
+}
+
+} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Ethernet.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Ethernet.cpp
new file mode 100644
index 000000000..279a88b8f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Ethernet.cpp
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Ethernet.h"
+
+#if DEVICE_ETHERNET
+
+#include "ethernet_api.h"
+
+namespace mbed {
+
+Ethernet::Ethernet() {
+ ethernet_init();
+}
+
+Ethernet::~Ethernet() {
+ ethernet_free();
+}
+
+int Ethernet::write(const char *data, int size) {
+ return ethernet_write(data, size);
+}
+
+int Ethernet::send() {
+ return ethernet_send();
+}
+
+int Ethernet::receive() {
+ return ethernet_receive();
+}
+
+int Ethernet::read(char *data, int size) {
+ return ethernet_read(data, size);
+}
+
+void Ethernet::address(char *mac) {
+ return ethernet_address(mac);
+}
+
+int Ethernet::link() {
+ return ethernet_link();
+}
+
+void Ethernet::set_link(Mode mode) {
+ int speed = -1;
+ int duplex = 0;
+
+ switch(mode) {
+ case AutoNegotiate : speed = -1; duplex = 0; break;
+ case HalfDuplex10 : speed = 0; duplex = 0; break;
+ case FullDuplex10 : speed = 0; duplex = 1; break;
+ case HalfDuplex100 : speed = 1; duplex = 0; break;
+ case FullDuplex100 : speed = 1; duplex = 1; break;
+ }
+
+ ethernet_set_link(speed, duplex);
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileBase.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileBase.cpp
new file mode 100644
index 000000000..fce113d88
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileBase.cpp
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileBase.h"
+
+namespace mbed {
+
+FileBase *FileBase::_head = NULL;
+
+FileBase::FileBase(const char *name, PathType t) : _next(NULL),
+ _name(name),
+ _path_type(t) {
+ if (name != NULL) {
+ // put this object at head of the list
+ _next = _head;
+ _head = this;
+ } else {
+ _next = NULL;
+ }
+}
+
+FileBase::~FileBase() {
+ if (_name != NULL) {
+ // remove this object from the list
+ if (_head == this) { // first in the list, so just drop me
+ _head = _next;
+ } else { // find the object before me, then drop me
+ FileBase *p = _head;
+ while (p->_next != this) {
+ p = p->_next;
+ }
+ p->_next = _next;
+ }
+ }
+}
+
+FileBase *FileBase::lookup(const char *name, unsigned int len) {
+ FileBase *p = _head;
+ while (p != NULL) {
+ /* Check that p->_name matches name and is the correct length */
+ if (p->_name != NULL && std::strncmp(p->_name, name, len) == 0 && std::strlen(p->_name) == len) {
+ return p;
+ }
+ p = p->_next;
+ }
+ return NULL;
+}
+
+FileBase *FileBase::get(int n) {
+ FileBase *p = _head;
+ int m = 0;
+ while (p != NULL) {
+ if (m == n) return p;
+
+ m++;
+ p = p->_next;
+ }
+ return NULL;
+}
+
+const char* FileBase::getName(void) {
+ return _name;
+}
+
+PathType FileBase::getPathType(void) {
+ return _path_type;
+}
+
+} // namespace mbed
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileLike.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileLike.cpp
new file mode 100644
index 000000000..da13ead14
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileLike.cpp
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileLike.h"
+
+namespace mbed {
+
+FileLike::FileLike(const char *name) : FileHandle(), FileBase(name, FilePathType) {
+
+}
+
+FileLike::~FileLike() {
+
+}
+
+} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FilePath.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FilePath.cpp
new file mode 100644
index 000000000..09147a269
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FilePath.cpp
@@ -0,0 +1,76 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FilePath.h"
+
+namespace mbed {
+
+FilePath::FilePath(const char* file_path) : file_name(NULL), fb(NULL) {
+ if ((file_path[0] != '/') || (file_path[1] == 0)) return;
+
+ const char* file_system = &file_path[1];
+ file_name = file_system;
+ int len = 0;
+ while (true) {
+ char c = *file_name;
+ if (c == '/') { // end of object name
+ file_name++; // point to one char after the '/'
+ break;
+ }
+ if (c == 0) { // end of object name, with no filename
+ break;
+ }
+ len++;
+ file_name++;
+ }
+
+ fb = FileBase::lookup(file_system, len);
+}
+
+const char* FilePath::fileName(void) {
+ return file_name;
+}
+
+bool FilePath::isFileSystem(void) {
+ if (NULL == fb)
+ return false;
+ return (fb->getPathType() == FileSystemPathType);
+}
+
+FileSystemLike* FilePath::fileSystem(void) {
+ if (isFileSystem()) {
+ return (FileSystemLike*)fb;
+ }
+ return NULL;
+}
+
+bool FilePath::isFile(void) {
+ if (NULL == fb)
+ return false;
+ return (fb->getPathType() == FilePathType);
+}
+
+FileLike* FilePath::file(void) {
+ if (isFile()) {
+ return (FileLike*)fb;
+ }
+ return NULL;
+}
+
+bool FilePath::exists(void) {
+ return fb != NULL;
+}
+
+} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileSystemLike.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileSystemLike.cpp
new file mode 100644
index 000000000..df5d86da8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FileSystemLike.cpp
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileSystemLike.h"
+
+namespace mbed {
+
+class BaseDirHandle : public DirHandle {
+public:
+ /*
+ We keep track of our current location as the n'th object in the
+ FileSystemLike list. Using a Base* instead would cause problems if that
+ object were to be destroyed between readdirs.
+ Using this method does mean though that destroying/creating objects can
+ give unusual results from readdir.
+ */
+ off_t n;
+ struct dirent cur_entry;
+
+ BaseDirHandle() : n(0), cur_entry() {
+ }
+
+ virtual int closedir() {
+ delete this;
+ return 0;
+ }
+
+ virtual struct dirent *readdir() {
+ FileBase *ptr = FileBase::get(n);
+ if (ptr == NULL) return NULL;
+
+ /* Increment n, so next readdir gets the next item */
+ n++;
+
+ /* Setup cur entry and return a pointer to it */
+ std::strncpy(cur_entry.d_name, ptr->getName(), NAME_MAX);
+ return &cur_entry;
+ }
+
+ virtual off_t telldir() {
+ return n;
+ }
+
+ virtual void seekdir(off_t offset) {
+ n = offset;
+ }
+
+ virtual void rewinddir() {
+ n = 0;
+ }
+};
+
+FileSystemLike::FileSystemLike(const char *name) : FileBase(name, FileSystemPathType) {
+
+}
+
+FileSystemLike::~FileSystemLike() {
+
+}
+
+DirHandle *FileSystemLike::opendir() {
+ return new BaseDirHandle();
+}
+
+} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FunctionPointer.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FunctionPointer.cpp
new file mode 100644
index 000000000..7c43916c7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/FunctionPointer.cpp
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+FunctionPointer::FunctionPointer(void (*function)(void)): _function(),
+ _object(),
+ _membercaller() {
+ attach(function);
+}
+
+void FunctionPointer::attach(void (*function)(void)) {
+ _function = function;
+ _object = 0;
+}
+
+void FunctionPointer::call(void) {
+ if (_function) {
+ _function();
+ } else if (_object) {
+ _membercaller(_object, _member);
+ }
+}
+
+#ifdef MBED_OPERATORS
+void FunctionPointer::operator ()(void) {
+ call();
+}
+#endif
+
+} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/I2C.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/I2C.cpp
new file mode 100644
index 000000000..fb1d03048
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/I2C.cpp
@@ -0,0 +1,91 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "I2C.h"
+
+#if DEVICE_I2C
+
+namespace mbed {
+
+I2C *I2C::_owner = NULL;
+
+I2C::I2C(PinName sda, PinName scl) : _i2c(), _hz(100000) {
+ // The init function also set the frequency to 100000
+ i2c_init(&_i2c, sda, scl);
+
+ // Used to avoid unnecessary frequency updates
+ _owner = this;
+}
+
+void I2C::frequency(int hz) {
+ _hz = hz;
+
+ // We want to update the frequency even if we are already the bus owners
+ i2c_frequency(&_i2c, _hz);
+
+ // Updating the frequency of the bus we become the owners of it
+ _owner = this;
+}
+
+void I2C::aquire() {
+ if (_owner != this) {
+ i2c_frequency(&_i2c, _hz);
+ _owner = this;
+ }
+}
+
+// write - Master Transmitter Mode
+int I2C::write(int address, const char* data, int length, bool repeated) {
+ aquire();
+
+ int stop = (repeated) ? 0 : 1;
+ int written = i2c_write(&_i2c, address, data, length, stop);
+
+ return length != written;
+}
+
+int I2C::write(int data) {
+ return i2c_byte_write(&_i2c, data);
+}
+
+// read - Master Reciever Mode
+int I2C::read(int address, char* data, int length, bool repeated) {
+ aquire();
+
+ int stop = (repeated) ? 0 : 1;
+ int read = i2c_read(&_i2c, address, data, length, stop);
+
+ return length != read;
+}
+
+int I2C::read(int ack) {
+ if (ack) {
+ return i2c_byte_read(&_i2c, 0);
+ } else {
+ return i2c_byte_read(&_i2c, 1);
+ }
+}
+
+void I2C::start(void) {
+ i2c_start(&_i2c);
+}
+
+void I2C::stop(void) {
+ i2c_stop(&_i2c);
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/I2CSlave.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/I2CSlave.cpp
new file mode 100644
index 000000000..43940939c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/I2CSlave.cpp
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "I2CSlave.h"
+
+#if DEVICE_I2CSLAVE
+
+namespace mbed {
+
+I2CSlave::I2CSlave(PinName sda, PinName scl) : _i2c() {
+ i2c_init(&_i2c, sda, scl);
+ i2c_frequency(&_i2c, 100000);
+ i2c_slave_mode(&_i2c, 1);
+}
+
+void I2CSlave::frequency(int hz) {
+ i2c_frequency(&_i2c, hz);
+}
+
+void I2CSlave::address(int address) {
+ int addr = (address & 0xFF) | 1;
+ i2c_slave_address(&_i2c, 0, addr, 0);
+}
+
+int I2CSlave::receive(void) {
+ return i2c_slave_receive(&_i2c);
+}
+
+int I2CSlave::read(char *data, int length) {
+ return i2c_slave_read(&_i2c, data, length) != length;
+}
+
+int I2CSlave::read(void) {
+ return i2c_byte_read(&_i2c, 0);
+}
+
+int I2CSlave::write(const char *data, int length) {
+ return i2c_slave_write(&_i2c, data, length) != length;
+}
+
+int I2CSlave::write(int data) {
+ return i2c_byte_write(&_i2c, data);
+}
+
+void I2CSlave::stop(void) {
+ i2c_stop(&_i2c);
+}
+
+}
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptIn.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptIn.cpp
new file mode 100644
index 000000000..8692124c1
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptIn.cpp
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "InterruptIn.h"
+
+#if DEVICE_INTERRUPTIN
+
+namespace mbed {
+
+InterruptIn::InterruptIn(PinName pin) : gpio(),
+ gpio_irq(),
+ _rise(),
+ _fall() {
+ gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
+ gpio_init_in(&gpio, pin);
+}
+
+InterruptIn::~InterruptIn() {
+ gpio_irq_free(&gpio_irq);
+}
+
+int InterruptIn::read() {
+ return gpio_read(&gpio);
+}
+
+void InterruptIn::mode(PinMode pull) {
+ gpio_mode(&gpio, pull);
+}
+
+void InterruptIn::rise(void (*fptr)(void)) {
+ if (fptr) {
+ _rise.attach(fptr);
+ gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+ } else {
+ gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
+ }
+}
+
+void InterruptIn::fall(void (*fptr)(void)) {
+ if (fptr) {
+ _fall.attach(fptr);
+ gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+ } else {
+ gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
+ }
+}
+
+void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
+ InterruptIn *handler = (InterruptIn*)id;
+ switch (event) {
+ case IRQ_RISE: handler->_rise.call(); break;
+ case IRQ_FALL: handler->_fall.call(); break;
+ case IRQ_NONE: break;
+ }
+}
+
+void InterruptIn::enable_irq() {
+ gpio_irq_enable(&gpio_irq);
+}
+
+void InterruptIn::disable_irq() {
+ gpio_irq_disable(&gpio_irq);
+}
+
+#ifdef MBED_OPERATORS
+InterruptIn::operator int() {
+ return read();
+}
+#endif
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptManager.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptManager.cpp
new file mode 100644
index 000000000..e92fb68d4
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/InterruptManager.cpp
@@ -0,0 +1,93 @@
+#include "cmsis.h"
+#if defined(NVIC_NUM_VECTORS)
+
+#include "InterruptManager.h"
+#include <string.h>
+
+#define CHAIN_INITIAL_SIZE 4
+
+namespace mbed {
+
+typedef void (*pvoidf)(void);
+
+InterruptManager* InterruptManager::_instance = (InterruptManager*)NULL;
+
+InterruptManager* InterruptManager::get() {
+ if (NULL == _instance)
+ _instance = new InterruptManager();
+ return _instance;
+}
+
+InterruptManager::InterruptManager() {
+ memset(_chains, 0, NVIC_NUM_VECTORS * sizeof(CallChain*));
+}
+
+void InterruptManager::destroy() {
+ // Not a good idea to call this unless NO interrupt at all
+ // is under the control of the handler; otherwise, a system crash
+ // is very likely to occur
+ if (NULL != _instance) {
+ delete _instance;
+ _instance = (InterruptManager*)NULL;
+ }
+}
+
+InterruptManager::~InterruptManager() {
+ for(int i = 0; i < NVIC_NUM_VECTORS; i++)
+ if (NULL != _chains[i])
+ delete _chains[i];
+}
+
+bool InterruptManager::must_replace_vector(IRQn_Type irq) {
+ int irq_pos = get_irq_index(irq);
+
+ if (NULL == _chains[irq_pos]) {
+ _chains[irq_pos] = new CallChain(CHAIN_INITIAL_SIZE);
+ _chains[irq_pos]->add((pvoidf)NVIC_GetVector(irq));
+ return true;
+ }
+ return false;
+}
+
+pFunctionPointer_t InterruptManager::add_common(void (*function)(void), IRQn_Type irq, bool front) {
+ int irq_pos = get_irq_index(irq);
+ bool change = must_replace_vector(irq);
+
+ pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(function) : _chains[irq_pos]->add(function);
+ if (change)
+ NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+ return pf;
+}
+
+bool InterruptManager::remove_handler(pFunctionPointer_t handler, IRQn_Type irq) {
+ int irq_pos = get_irq_index(irq);
+
+ if (NULL == _chains[irq_pos])
+ return false;
+ if (!_chains[irq_pos]->remove(handler))
+ return false;
+ // If there's a single function left in the chain, swith the interrupt vector
+ // to call that function directly. This way we save both time and space.
+ if (_chains[irq_pos]->size() == 1 && NULL != _chains[irq_pos]->get(0)->get_function()) {
+ NVIC_SetVector(irq, (uint32_t)_chains[irq_pos]->get(0)->get_function());
+ delete _chains[irq_pos];
+ _chains[irq_pos] = (CallChain*) NULL;
+ }
+ return true;
+}
+
+void InterruptManager::irq_helper() {
+ _chains[__get_IPSR()]->call();
+}
+
+int InterruptManager::get_irq_index(IRQn_Type irq) {
+ return (int)irq + NVIC_USER_IRQ_OFFSET;
+}
+
+void InterruptManager::static_irq_helper() {
+ InterruptManager::get()->irq_helper();
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/LocalFileSystem.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/LocalFileSystem.cpp
new file mode 100644
index 000000000..9505d91a9
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/LocalFileSystem.cpp
@@ -0,0 +1,223 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "LocalFileSystem.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "semihost_api.h"
+#include <string.h>
+#include <stdio.h>
+
+namespace mbed {
+
+/* Extension to FINFO type defined in RTL.h (in Keil RL) - adds 'create time'. */
+typedef struct {
+ unsigned char hr; /* Hours [0..23] */
+ unsigned char min; /* Minutes [0..59] */
+ unsigned char sec; /* Seconds [0..59] */
+ unsigned char day; /* Day [1..31] */
+ unsigned char mon; /* Month [1..12] */
+ unsigned short year; /* Year [1980..2107] */
+} FTIME;
+
+typedef struct { /* File Search info record */
+ char name[32]; /* File name */
+ long size; /* File size in bytes */
+ int fileID; /* System File Identification */
+ FTIME create_time; /* Date & time file was created */
+ FTIME write_time; /* Date & time of last write */
+} XFINFO;
+
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) /* 0x100 - 0x1ff */
+#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
+
+static int xffind (const char *pattern, XFINFO *info) {
+ unsigned param[4];
+
+ param[0] = (unsigned long)pattern;
+ param[1] = (unsigned long)strlen(pattern);
+ param[2] = (unsigned long)info;
+ param[3] = (unsigned long)sizeof(XFINFO);
+
+ return __semihost(USR_XFFIND, param);
+}
+
+#define OPEN_R 0
+#define OPEN_B 1
+#define OPEN_PLUS 2
+#define OPEN_W 4
+#define OPEN_A 8
+#define OPEN_INVALID -1
+
+int posix_to_semihost_open_flags(int flags) {
+ /* POSIX flags -> semihosting open mode */
+ int openmode;
+ if (flags & O_RDWR) {
+ /* a plus mode */
+ openmode = OPEN_PLUS;
+ if (flags & O_APPEND) {
+ openmode |= OPEN_A;
+ } else if (flags & O_TRUNC) {
+ openmode |= OPEN_W;
+ } else {
+ openmode |= OPEN_R;
+ }
+ } else if (flags & O_WRONLY) {
+ /* write or append */
+ if (flags & O_APPEND) {
+ openmode = OPEN_A;
+ } else {
+ openmode = OPEN_W;
+ }
+ } else if (flags == O_RDONLY) {
+ /* read mode */
+ openmode = OPEN_R;
+ } else {
+ /* invalid flags */
+ openmode = OPEN_INVALID;
+ }
+
+ return openmode;
+}
+
+FILEHANDLE local_file_open(const char* name, int flags) {
+ int openmode = posix_to_semihost_open_flags(flags);
+ if (openmode == OPEN_INVALID) {
+ return (FILEHANDLE)NULL;
+ }
+
+ FILEHANDLE fh = semihost_open(name, openmode);
+ if (fh == -1) {
+ return (FILEHANDLE)NULL;
+ }
+
+ return fh;
+}
+
+LocalFileHandle::LocalFileHandle(FILEHANDLE fh) : _fh(fh), pos(0) {
+}
+
+int LocalFileHandle::close() {
+ int retval = semihost_close(_fh);
+ delete this;
+ return retval;
+}
+
+ssize_t LocalFileHandle::write(const void *buffer, size_t length) {
+ ssize_t n = semihost_write(_fh, (const unsigned char*)buffer, length, 0); // number of characters not written
+ n = length - n; // number of characters written
+ pos += n;
+ return n;
+}
+
+ssize_t LocalFileHandle::read(void *buffer, size_t length) {
+ ssize_t n = semihost_read(_fh, (unsigned char*)buffer, length, 0); // number of characters not read
+ n = length - n; // number of characters read
+ pos += n;
+ return n;
+}
+
+int LocalFileHandle::isatty() {
+ return semihost_istty(_fh);
+}
+
+off_t LocalFileHandle::lseek(off_t position, int whence) {
+ if (whence == SEEK_CUR) {
+ position += pos;
+ } else if (whence == SEEK_END) {
+ position += semihost_flen(_fh);
+ } /* otherwise SEEK_SET, so position is fine */
+
+ /* Always seems to return -1, so just ignore for now. */
+ semihost_seek(_fh, position);
+ pos = position;
+ return position;
+}
+
+int LocalFileHandle::fsync() {
+ return semihost_ensure(_fh);
+}
+
+off_t LocalFileHandle::flen() {
+ return semihost_flen(_fh);
+}
+
+class LocalDirHandle : public DirHandle {
+
+public:
+ struct dirent cur_entry;
+ XFINFO info;
+
+ LocalDirHandle() : cur_entry(), info() {
+ }
+
+ virtual int closedir() {
+ delete this;
+ return 0;
+ }
+
+ virtual struct dirent *readdir() {
+ if (xffind("*", &info)!=0) {
+ return NULL;
+ }
+ memcpy(cur_entry.d_name, info.name, sizeof(info.name));
+ return &cur_entry;
+ }
+
+ virtual void rewinddir() {
+ info.fileID = 0;
+ }
+
+ virtual off_t telldir() {
+ return info.fileID;
+ }
+
+ virtual void seekdir(off_t offset) {
+ info.fileID = offset;
+ }
+};
+
+FileHandle *LocalFileSystem::open(const char* name, int flags) {
+ /* reject filenames with / in them */
+ for (const char *tmp = name; *tmp; tmp++) {
+ if (*tmp == '/') {
+ return NULL;
+ }
+ }
+
+ int openmode = posix_to_semihost_open_flags(flags);
+ if (openmode == OPEN_INVALID) {
+ return NULL;
+ }
+
+ FILEHANDLE fh = semihost_open(name, openmode);
+ if (fh == -1) {
+ return NULL;
+ }
+ return new LocalFileHandle(fh);
+}
+
+int LocalFileSystem::remove(const char *filename) {
+ return semihost_remove(filename);
+}
+
+DirHandle *LocalFileSystem::opendir(const char *name) {
+ return new LocalDirHandle();
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/RawSerial.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/RawSerial.cpp
new file mode 100644
index 000000000..dc5db7a3f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/RawSerial.cpp
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "RawSerial.h"
+#include "wait_api.h"
+#include <cstdarg>
+
+#if DEVICE_SERIAL
+
+#define STRING_STACK_LIMIT 120
+
+namespace mbed {
+
+RawSerial::RawSerial(PinName tx, PinName rx) : SerialBase(tx, rx) {
+}
+
+int RawSerial::getc() {
+ return _base_getc();
+}
+
+int RawSerial::putc(int c) {
+ return _base_putc(c);
+}
+
+int RawSerial::puts(const char *str) {
+ while (*str)
+ putc(*str ++);
+ return 0;
+}
+
+// Experimental support for printf in RawSerial. No Stream inheritance
+// means we can't call printf() directly, so we use sprintf() instead.
+// We only call malloc() for the sprintf() buffer if the buffer
+// length is above a certain threshold, otherwise we use just the stack.
+int RawSerial::printf(const char *format, ...) {
+ std::va_list arg;
+ va_start(arg, format);
+ int len = vsnprintf(NULL, 0, format, arg);
+ if (len < STRING_STACK_LIMIT) {
+ char temp[STRING_STACK_LIMIT];
+ vsprintf(temp, format, arg);
+ puts(temp);
+ } else {
+ char *temp = new char[len + 1];
+ vsprintf(temp, format, arg);
+ puts(temp);
+ delete[] temp;
+ }
+ va_end(arg);
+ return len;
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SPI.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SPI.cpp
new file mode 100644
index 000000000..4bca2b69c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SPI.cpp
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SPI.h"
+
+#if DEVICE_SPI
+
+namespace mbed {
+
+SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName _unused) :
+ _spi(),
+ _bits(8),
+ _mode(0),
+ _hz(1000000) {
+ spi_init(&_spi, mosi, miso, sclk, NC);
+ spi_format(&_spi, _bits, _mode, 0);
+ spi_frequency(&_spi, _hz);
+}
+
+void SPI::format(int bits, int mode) {
+ _bits = bits;
+ _mode = mode;
+ SPI::_owner = NULL; // Not that elegant, but works. rmeyer
+ aquire();
+}
+
+void SPI::frequency(int hz) {
+ _hz = hz;
+ SPI::_owner = NULL; // Not that elegant, but works. rmeyer
+ aquire();
+}
+
+SPI* SPI::_owner = NULL;
+
+// ignore the fact there are multiple physical spis, and always update if it wasnt us last
+void SPI::aquire() {
+ if (_owner != this) {
+ spi_format(&_spi, _bits, _mode, 0);
+ spi_frequency(&_spi, _hz);
+ _owner = this;
+ }
+}
+
+int SPI::write(int value) {
+ aquire();
+ return spi_master_write(&_spi, value);
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SPISlave.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SPISlave.cpp
new file mode 100644
index 000000000..5e503165b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SPISlave.cpp
@@ -0,0 +1,58 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SPISlave.h"
+
+#if DEVICE_SPISLAVE
+
+namespace mbed {
+
+SPISlave::SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
+ _spi(),
+ _bits(8),
+ _mode(0),
+ _hz(1000000)
+ {
+ spi_init(&_spi, mosi, miso, sclk, ssel);
+ spi_format(&_spi, _bits, _mode, 1);
+ spi_frequency(&_spi, _hz);
+}
+
+void SPISlave::format(int bits, int mode) {
+ _bits = bits;
+ _mode = mode;
+ spi_format(&_spi, _bits, _mode, 1);
+}
+
+void SPISlave::frequency(int hz) {
+ _hz = hz;
+ spi_frequency(&_spi, _hz);
+}
+
+int SPISlave::receive(void) {
+ return(spi_slave_receive(&_spi));
+}
+
+int SPISlave::read(void) {
+ return(spi_slave_read(&_spi));
+}
+
+void SPISlave::reply(int value) {
+ spi_slave_write(&_spi, value);
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Serial.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Serial.cpp
new file mode 100644
index 000000000..602c87a0a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Serial.cpp
@@ -0,0 +1,36 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Serial.h"
+#include "wait_api.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+Serial::Serial(PinName tx, PinName rx, const char *name) : SerialBase(tx, rx), Stream(name) {
+}
+
+int Serial::_getc() {
+ return _base_getc();
+}
+
+int Serial::_putc(int c) {
+ return _base_putc(c);
+}
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SerialBase.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SerialBase.cpp
new file mode 100644
index 000000000..68cf7c381
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/SerialBase.cpp
@@ -0,0 +1,108 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SerialBase.h"
+#include "wait_api.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+SerialBase::SerialBase(PinName tx, PinName rx) : _serial(), _baud(9600) {
+ serial_init(&_serial, tx, rx);
+ serial_irq_handler(&_serial, SerialBase::_irq_handler, (uint32_t)this);
+}
+
+void SerialBase::baud(int baudrate) {
+ serial_baud(&_serial, baudrate);
+ _baud = baudrate;
+}
+
+void SerialBase::format(int bits, Parity parity, int stop_bits) {
+ serial_format(&_serial, bits, (SerialParity)parity, stop_bits);
+}
+
+int SerialBase::readable() {
+ return serial_readable(&_serial);
+}
+
+
+int SerialBase::writeable() {
+ return serial_writable(&_serial);
+}
+
+void SerialBase::attach(void (*fptr)(void), IrqType type) {
+ if (fptr) {
+ _irq[type].attach(fptr);
+ serial_irq_set(&_serial, (SerialIrq)type, 1);
+ } else {
+ serial_irq_set(&_serial, (SerialIrq)type, 0);
+ }
+}
+
+void SerialBase::_irq_handler(uint32_t id, SerialIrq irq_type) {
+ SerialBase *handler = (SerialBase*)id;
+ handler->_irq[irq_type].call();
+}
+
+int SerialBase::_base_getc() {
+ return serial_getc(&_serial);
+}
+
+int SerialBase::_base_putc(int c) {
+ serial_putc(&_serial, c);
+ return c;
+}
+
+void SerialBase::send_break() {
+ // Wait for 1.5 frames before clearing the break condition
+ // This will have different effects on our platforms, but should
+ // ensure that we keep the break active for at least one frame.
+ // We consider a full frame (1 start bit + 8 data bits bits +
+ // 1 parity bit + 2 stop bits = 12 bits) for computation.
+ // One bit time (in us) = 1000000/_baud
+ // Twelve bits: 12000000/baud delay
+ // 1.5 frames: 18000000/baud delay
+ serial_break_set(&_serial);
+ wait_us(18000000/_baud);
+ serial_break_clear(&_serial);
+}
+
+#if DEVICE_SERIAL_FC
+void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) {
+ FlowControl flow_type = (FlowControl)type;
+ switch(type) {
+ case RTS:
+ serial_set_flow_control(&_serial, flow_type, flow1, NC);
+ break;
+
+ case CTS:
+ serial_set_flow_control(&_serial, flow_type, NC, flow1);
+ break;
+
+ case RTSCTS:
+ case Disabled:
+ serial_set_flow_control(&_serial, flow_type, flow1, flow2);
+ break;
+
+ default:
+ break;
+ }
+}
+#endif
+
+} // namespace mbed
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Stream.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Stream.cpp
new file mode 100644
index 000000000..6d3a33526
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Stream.cpp
@@ -0,0 +1,111 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Stream.h"
+
+#include <cstdarg>
+
+namespace mbed {
+
+Stream::Stream(const char *name) : FileLike(name), _file(NULL) {
+ /* open ourselves */
+ char buf[12]; /* :0x12345678 + null byte */
+ std::sprintf(buf, ":%p", this);
+ _file = std::fopen(buf, "w+");
+ mbed_set_unbuffered_stream(_file);
+}
+
+Stream::~Stream() {
+ fclose(_file);
+}
+
+int Stream::putc(int c) {
+ fflush(_file);
+ return std::fputc(c, _file);
+}
+int Stream::puts(const char *s) {
+ fflush(_file);
+ return std::fputs(s, _file);
+}
+int Stream::getc() {
+ fflush(_file);
+ return mbed_getc(_file);
+}
+char* Stream::gets(char *s, int size) {
+ fflush(_file);
+ return mbed_gets(s,size,_file);
+}
+
+int Stream::close() {
+ return 0;
+}
+
+ssize_t Stream::write(const void* buffer, size_t length) {
+ const char* ptr = (const char*)buffer;
+ const char* end = ptr + length;
+ while (ptr != end) {
+ if (_putc(*ptr++) == EOF) {
+ break;
+ }
+ }
+ return ptr - (const char*)buffer;
+}
+
+ssize_t Stream::read(void* buffer, size_t length) {
+ char* ptr = (char*)buffer;
+ char* end = ptr + length;
+ while (ptr != end) {
+ int c = _getc();
+ if (c==EOF) break;
+ *ptr++ = c;
+ }
+ return ptr - (const char*)buffer;
+}
+
+off_t Stream::lseek(off_t offset, int whence) {
+ return 0;
+}
+
+int Stream::isatty() {
+ return 0;
+}
+
+int Stream::fsync() {
+ return 0;
+}
+
+off_t Stream::flen() {
+ return 0;
+}
+
+int Stream::printf(const char* format, ...) {
+ std::va_list arg;
+ va_start(arg, format);
+ fflush(_file);
+ int r = vfprintf(_file, format, arg);
+ va_end(arg);
+ return r;
+}
+
+int Stream::scanf(const char* format, ...) {
+ std::va_list arg;
+ va_start(arg, format);
+ fflush(_file);
+ int r = vfscanf(_file, format, arg);
+ va_end(arg);
+ return r;
+}
+
+} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Ticker.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Ticker.cpp
new file mode 100644
index 000000000..577950b85
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Ticker.cpp
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Ticker.h"
+
+#include "TimerEvent.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+void Ticker::detach() {
+ remove();
+ _function.attach(0);
+}
+
+void Ticker::setup(timestamp_t t) {
+ remove();
+ _delay = t;
+ insert(_delay + us_ticker_read());
+}
+
+void Ticker::handler() {
+ insert(event.timestamp + _delay);
+ _function.call();
+}
+
+} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Timeout.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Timeout.cpp
new file mode 100644
index 000000000..ed7950212
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Timeout.cpp
@@ -0,0 +1,24 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Timeout.h"
+
+namespace mbed {
+
+void Timeout::handler() {
+ _function.call();
+}
+
+} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Timer.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Timer.cpp
new file mode 100644
index 000000000..e00eaaf54
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/Timer.cpp
@@ -0,0 +1,68 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Timer.h"
+#include "us_ticker_api.h"
+
+namespace mbed {
+
+Timer::Timer() : _running(), _start(), _time() {
+ reset();
+}
+
+void Timer::start() {
+ if (!_running) {
+ _start = us_ticker_read();
+ _running = 1;
+ }
+}
+
+void Timer::stop() {
+ _time += slicetime();
+ _running = 0;
+}
+
+int Timer::read_us() {
+ return _time + slicetime();
+}
+
+float Timer::read() {
+ return (float)read_us() / 1000000.0f;
+}
+
+int Timer::read_ms() {
+ return read_us() / 1000;
+}
+
+int Timer::slicetime() {
+ if (_running) {
+ return us_ticker_read() - _start;
+ } else {
+ return 0;
+ }
+}
+
+void Timer::reset() {
+ _start = us_ticker_read();
+ _time = 0;
+}
+
+#ifdef MBED_OPERATORS
+Timer::operator float() {
+ return read();
+}
+#endif
+
+} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/TimerEvent.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/TimerEvent.cpp
new file mode 100644
index 000000000..272adf51f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/TimerEvent.cpp
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "TimerEvent.h"
+#include "cmsis.h"
+
+#include <stddef.h>
+
+namespace mbed {
+
+TimerEvent::TimerEvent() : event() {
+ us_ticker_set_handler((&TimerEvent::irq));
+}
+
+void TimerEvent::irq(uint32_t id) {
+ TimerEvent *timer_event = (TimerEvent*)id;
+ timer_event->handler();
+}
+
+TimerEvent::~TimerEvent() {
+ remove();
+}
+
+// insert in to linked list
+void TimerEvent::insert(timestamp_t timestamp) {
+ us_ticker_insert_event(&event, timestamp, (uint32_t)this);
+}
+
+void TimerEvent::remove() {
+ us_ticker_remove_event(&event);
+}
+
+} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/assert.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/assert.c
new file mode 100644
index 000000000..51394707b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/assert.c
@@ -0,0 +1,32 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "device.h"
+
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+
+#include <stdlib.h>
+#include "mbed_interface.h"
+
+void mbed_assert_internal(const char *expr, const char *file, int line)
+{
+#if DEVICE_STDIO_MESSAGES
+ fprintf(stderr, "mbed assertation failed: %s, file: %s, line %d \n", expr, file, line);
+#endif
+ mbed_die();
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/board.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/board.c
new file mode 100644
index 000000000..910323645
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/board.c
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "wait_api.h"
+#include "toolchain.h"
+#include "mbed_interface.h"
+
+WEAK void mbed_die(void) {
+#ifndef NRF51_H
+ __disable_irq(); // dont allow interrupts to disturb the flash pattern
+#endif
+#if (DEVICE_ERROR_RED == 1)
+ gpio_t led_red; gpio_init_out(&led_red, LED_RED);
+#elif (DEVICE_ERROR_PATTERN == 1)
+ gpio_t led_1; gpio_init_out(&led_1, LED1);
+ gpio_t led_2; gpio_init_out(&led_2, LED2);
+ gpio_t led_3; gpio_init_out(&led_3, LED3);
+ gpio_t led_4; gpio_init_out(&led_4, LED4);
+#endif
+
+ while (1) {
+#if (DEVICE_ERROR_RED == 1)
+ gpio_write(&led_red, 1);
+
+#elif (DEVICE_ERROR_PATTERN == 1)
+ gpio_write(&led_1, 1);
+ gpio_write(&led_2, 0);
+ gpio_write(&led_3, 0);
+ gpio_write(&led_4, 1);
+#endif
+
+ wait_ms(150);
+
+#if (DEVICE_ERROR_RED == 1)
+ gpio_write(&led_red, 0);
+
+#elif (DEVICE_ERROR_PATTERN == 1)
+ gpio_write(&led_1, 0);
+ gpio_write(&led_2, 1);
+ gpio_write(&led_3, 1);
+ gpio_write(&led_4, 0);
+#endif
+
+ wait_ms(150);
+ }
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/error.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/error.c
new file mode 100644
index 000000000..b307d8756
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/error.c
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdlib.h>
+#include <stdarg.h>
+#include "device.h"
+#include "toolchain.h"
+#include "mbed_error.h"
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+
+WEAK void error(const char* format, ...) {
+#if DEVICE_STDIO_MESSAGES
+ va_list arg;
+ va_start(arg, format);
+ vfprintf(stderr, format, arg);
+ va_end(arg);
+#endif
+ exit(1);
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/gpio.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/gpio.c
new file mode 100644
index 000000000..3839e8bb2
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/gpio.c
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+
+static inline void _gpio_init_in(gpio_t* gpio, PinName pin, PinMode mode)
+{
+ gpio_init(gpio, pin);
+ if (pin != NC) {
+ gpio_dir(gpio, PIN_INPUT);
+ gpio_mode(gpio, mode);
+ }
+}
+
+static inline void _gpio_init_out(gpio_t* gpio, PinName pin, PinMode mode, int value)
+{
+ gpio_init(gpio, pin);
+ if (pin != NC) {
+ gpio_write(gpio, value);
+ gpio_dir(gpio, PIN_OUTPUT);
+ gpio_mode(gpio, mode);
+ }
+}
+
+void gpio_init_in(gpio_t* gpio, PinName pin) {
+ gpio_init_in_ex(gpio, pin, PullDefault);
+}
+
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode) {
+ _gpio_init_in(gpio, pin, mode);
+}
+
+void gpio_init_out(gpio_t* gpio, PinName pin) {
+ gpio_init_out_ex(gpio, pin, 0);
+}
+
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value) {
+ _gpio_init_out(gpio, pin, PullNone, value);
+}
+
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value) {
+ if (direction == PIN_INPUT) {
+ _gpio_init_in(gpio, pin, mode);
+ if (pin != NC)
+ gpio_write(gpio, value); // we prepare the value in case it is switched later
+ } else {
+ _gpio_init_out(gpio, pin, mode, value);
+ }
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/mbed_interface.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/mbed_interface.c
new file mode 100644
index 000000000..5b27b3087
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/mbed_interface.c
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include "mbed_interface.h"
+
+#include "gpio_api.h"
+#include "wait_api.h"
+#include "semihost_api.h"
+#include "mbed_error.h"
+#include "toolchain.h"
+
+#if DEVICE_SEMIHOST
+
+// return true if a debugger is attached, indicating mbed interface is connected
+int mbed_interface_connected(void) {
+ return semihost_connected();
+}
+
+int mbed_interface_reset(void) {
+ if (mbed_interface_connected()) {
+ semihost_reset();
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+WEAK int mbed_interface_uid(char *uid) {
+ if (mbed_interface_connected()) {
+ return semihost_uid(uid); // Returns 0 if successful, -1 on failure
+ } else {
+ uid[0] = 0;
+ return -1;
+ }
+}
+
+int mbed_interface_disconnect(void) {
+ int res;
+ if (mbed_interface_connected()) {
+ if ((res = semihost_disabledebug()) != 0)
+ return res;
+ while (mbed_interface_connected());
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+int mbed_interface_powerdown(void) {
+ int res;
+ if (mbed_interface_connected()) {
+ if ((res = semihost_powerdown()) != 0)
+ return res;
+ while (mbed_interface_connected());
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+// for backward compatibility
+void mbed_reset(void) {
+ mbed_interface_reset();
+}
+
+WEAK int mbed_uid(char *uid) {
+ return mbed_interface_uid(uid);
+}
+#endif
+
+WEAK void mbed_mac_address(char *mac) {
+#if DEVICE_SEMIHOST
+ char uid[DEVICE_ID_LENGTH + 1];
+ int i;
+
+ // if we have a UID, extract the MAC
+ if (mbed_interface_uid(uid) == 0) {
+ char *p = uid;
+#if defined(DEVICE_MAC_OFFSET)
+ p += DEVICE_MAC_OFFSET;
+#endif
+ for (i=0; i<6; i++) {
+ int byte;
+ sscanf(p, "%2x", &byte);
+ mac[i] = byte;
+ p += 2;
+ }
+ mac[0] &= ~0x01; // reset the IG bit in the address; see IEE 802.3-2002, Section 3.2.3(b)
+ } else { // else return a default MAC
+#endif
+ mac[0] = 0x00;
+ mac[1] = 0x02;
+ mac[2] = 0xF7;
+ mac[3] = 0xF0;
+ mac[4] = 0x00;
+ mac[5] = 0x00;
+#if DEVICE_SEMIHOST
+ }
+#endif
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/pinmap_common.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/pinmap_common.c
new file mode 100644
index 000000000..5aab0e617
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/pinmap_common.c
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "mbed_error.h"
+
+void pinmap_pinout(PinName pin, const PinMap *map) {
+ if (pin == NC)
+ return;
+
+ while (map->pin != NC) {
+ if (map->pin == pin) {
+ pin_function(pin, map->function);
+
+ pin_mode(pin, PullNone);
+ return;
+ }
+ map++;
+ }
+ error("could not pinout");
+}
+
+uint32_t pinmap_merge(uint32_t a, uint32_t b) {
+ // both are the same (inc both NC)
+ if (a == b)
+ return a;
+
+ // one (or both) is not connected
+ if (a == (uint32_t)NC)
+ return b;
+ if (b == (uint32_t)NC)
+ return a;
+
+ // mis-match error case
+ error("pinmap mis-match");
+ return (uint32_t)NC;
+}
+
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map) {
+ while (map->pin != NC) {
+ if (map->pin == pin)
+ return map->peripheral;
+ map++;
+ }
+ return (uint32_t)NC;
+}
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
+ uint32_t peripheral = (uint32_t)NC;
+
+ if (pin == (PinName)NC)
+ return (uint32_t)NC;
+ peripheral = pinmap_find_peripheral(pin, map);
+ if ((uint32_t)NC == peripheral) // no mapping available
+ error("pinmap not found for peripheral");
+ return peripheral;
+}
+
+uint32_t pinmap_find_function(PinName pin, const PinMap* map) {
+ while (map->pin != NC) {
+ if (map->pin == pin)
+ return map->function;
+ map++;
+ }
+ return (uint32_t)NC;
+}
+
+uint32_t pinmap_function(PinName pin, const PinMap* map) {
+ uint32_t function = (uint32_t)NC;
+
+ if (pin == (PinName)NC)
+ return (uint32_t)NC;
+ function = pinmap_find_function(pin, map);
+ if ((uint32_t)NC == function) // no mapping available
+ error("pinmap not found for function");
+ return function;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/retarget.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/retarget.cpp
new file mode 100644
index 000000000..82411abd2
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/retarget.cpp
@@ -0,0 +1,569 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform.h"
+#include "FileHandle.h"
+#include "FileSystemLike.h"
+#include "FilePath.h"
+#include "serial_api.h"
+#include "toolchain.h"
+#include "semihost_api.h"
+#include "mbed_interface.h"
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+#include <errno.h>
+
+#if defined(__ARMCC_VERSION)
+# include <rt_sys.h>
+# define PREFIX(x) _sys##x
+# define OPEN_MAX _SYS_OPEN
+# ifdef __MICROLIB
+# pragma import(__use_full_stdio)
+# endif
+
+#elif defined(__ICCARM__)
+# include <yfuns.h>
+# define PREFIX(x) _##x
+# define OPEN_MAX 16
+
+# define STDIN_FILENO 0
+# define STDOUT_FILENO 1
+# define STDERR_FILENO 2
+
+#else
+# include <sys/stat.h>
+# include <sys/unistd.h>
+# include <sys/syslimits.h>
+# define PREFIX(x) x
+#endif
+
+using namespace mbed;
+
+#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+// Before version 5.03, we were using a patched version of microlib with proper names
+extern const char __stdin_name[] = ":tt";
+extern const char __stdout_name[] = ":tt";
+extern const char __stderr_name[] = ":tt";
+
+#else
+extern const char __stdin_name[] = "/stdin";
+extern const char __stdout_name[] = "/stdout";
+extern const char __stderr_name[] = "/stderr";
+#endif
+
+/* newlib has the filehandle field in the FILE struct as a short, so
+ * we can't just return a Filehandle* from _open and instead have to
+ * put it in a filehandles array and return the index into that array
+ * (or rather index+3, as filehandles 0-2 are stdin/out/err).
+ */
+static FileHandle *filehandles[OPEN_MAX];
+
+FileHandle::~FileHandle() {
+ /* Remove all open filehandles for this */
+ for (unsigned int fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+ if (filehandles[fh_i] == this) {
+ filehandles[fh_i] = NULL;
+ }
+ }
+}
+
+#if DEVICE_SERIAL
+extern int stdio_uart_inited;
+extern serial_t stdio_uart;
+#endif
+
+static void init_serial() {
+#if DEVICE_SERIAL
+ if (stdio_uart_inited) return;
+ serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
+#endif
+}
+
+static inline int openmode_to_posix(int openmode) {
+ int posix = openmode;
+#ifdef __ARMCC_VERSION
+ if (openmode & OPEN_PLUS) {
+ posix = O_RDWR;
+ } else if(openmode & OPEN_W) {
+ posix = O_WRONLY;
+ } else if(openmode & OPEN_A) {
+ posix = O_WRONLY|O_APPEND;
+ } else {
+ posix = O_RDONLY;
+ }
+ /* a, w, a+, w+ all create if file does not already exist */
+ if (openmode & (OPEN_A|OPEN_W)) {
+ posix |= O_CREAT;
+ }
+ /* w and w+ truncate */
+ if (openmode & OPEN_W) {
+ posix |= O_TRUNC;
+ }
+#elif defined(__ICCARM__)
+ switch (openmode & _LLIO_RDWRMASK) {
+ case _LLIO_RDONLY: posix = O_RDONLY; break;
+ case _LLIO_WRONLY: posix = O_WRONLY; break;
+ case _LLIO_RDWR : posix = O_RDWR ; break;
+ }
+ if (openmode & _LLIO_CREAT ) posix |= O_CREAT;
+ if (openmode & _LLIO_APPEND) posix |= O_APPEND;
+ if (openmode & _LLIO_TRUNC ) posix |= O_TRUNC;
+#endif
+ return posix;
+}
+
+extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) {
+ #if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+ // Before version 5.03, we were using a patched version of microlib with proper names
+ // This is the workaround that the microlib author suggested us
+ static int n = 0;
+ if (!std::strcmp(name, ":tt")) return n++;
+
+ #else
+ /* Use the posix convention that stdin,out,err are filehandles 0,1,2.
+ */
+ if (std::strcmp(name, __stdin_name) == 0) {
+ init_serial();
+ return 0;
+ } else if (std::strcmp(name, __stdout_name) == 0) {
+ init_serial();
+ return 1;
+ } else if (std::strcmp(name, __stderr_name) == 0) {
+ init_serial();
+ return 2;
+ }
+ #endif
+
+ // find the first empty slot in filehandles
+ unsigned int fh_i;
+ for (fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+ if (filehandles[fh_i] == NULL) break;
+ }
+ if (fh_i >= sizeof(filehandles)/sizeof(*filehandles)) {
+ return -1;
+ }
+
+ FileHandle *res;
+
+ /* FILENAME: ":0x12345678" describes a FileLike* */
+ if (name[0] == ':') {
+ void *p;
+ sscanf(name, ":%p", &p);
+ res = (FileHandle*)p;
+
+ /* FILENAME: "/file_system/file_name" */
+ } else {
+ FilePath path(name);
+
+ if (!path.exists())
+ return -1;
+ else if (path.isFile()) {
+ res = path.file();
+ } else {
+ FileSystemLike *fs = path.fileSystem();
+ if (fs == NULL) return -1;
+ int posix_mode = openmode_to_posix(openmode);
+ res = fs->open(path.fileName(), posix_mode); /* NULL if fails */
+ }
+ }
+
+ if (res == NULL) return -1;
+ filehandles[fh_i] = res;
+
+ return fh_i + 3; // +3 as filehandles 0-2 are stdin/out/err
+}
+
+extern "C" int PREFIX(_close)(FILEHANDLE fh) {
+ if (fh < 3) return 0;
+
+ FileHandle* fhc = filehandles[fh-3];
+ filehandles[fh-3] = NULL;
+ if (fhc == NULL) return -1;
+
+ return fhc->close();
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t __write (int fh, const unsigned char *buffer, size_t length) {
+#else
+extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode) {
+#endif
+ int n; // n is the number of bytes written
+ if (fh < 3) {
+#if DEVICE_SERIAL
+ if (!stdio_uart_inited) init_serial();
+ for (unsigned int i = 0; i < length; i++) {
+ serial_putc(&stdio_uart, buffer[i]);
+ }
+#endif
+ n = length;
+ } else {
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) return -1;
+
+ n = fhc->write(buffer, length);
+ }
+#ifdef __ARMCC_VERSION
+ return length-n;
+#else
+ return n;
+#endif
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t __read (int fh, unsigned char *buffer, size_t length) {
+#else
+extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode) {
+#endif
+ int n; // n is the number of bytes read
+ if (fh < 3) {
+ // only read a character at a time from stdin
+#if DEVICE_SERIAL
+ if (!stdio_uart_inited) init_serial();
+ *buffer = serial_getc(&stdio_uart);
+#endif
+ n = 1;
+ } else {
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) return -1;
+
+ n = fhc->read(buffer, length);
+ }
+#ifdef __ARMCC_VERSION
+ return length-n;
+#else
+ return n;
+#endif
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_istty)(FILEHANDLE fh)
+#else
+extern "C" int _isatty(FILEHANDLE fh)
+#endif
+{
+ /* stdin, stdout and stderr should be tty */
+ if (fh < 3) return 1;
+
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) return -1;
+
+ return fhc->isatty();
+}
+
+extern "C"
+#if defined(__ARMCC_VERSION)
+int _sys_seek(FILEHANDLE fh, long position)
+#elif defined(__ICCARM__)
+long __lseek(int fh, long offset, int whence)
+#else
+int _lseek(FILEHANDLE fh, int offset, int whence)
+#endif
+{
+ if (fh < 3) return 0;
+
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) return -1;
+
+#if defined(__ARMCC_VERSION)
+ return fhc->lseek(position, SEEK_SET);
+#else
+ return fhc->lseek(offset, whence);
+#endif
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_ensure)(FILEHANDLE fh) {
+ if (fh < 3) return 0;
+
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) return -1;
+
+ return fhc->fsync();
+}
+
+extern "C" long PREFIX(_flen)(FILEHANDLE fh) {
+ if (fh < 3) return 0;
+
+ FileHandle* fhc = filehandles[fh-3];
+ if (fhc == NULL) return -1;
+
+ return fhc->flen();
+}
+#endif
+
+
+#if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
+extern "C" int _fstat(int fd, struct stat *st) {
+ if ((STDOUT_FILENO == fd) || (STDERR_FILENO == fd) || (STDIN_FILENO == fd)) {
+ st->st_mode = S_IFCHR;
+ return 0;
+ }
+
+ errno = EBADF;
+ return -1;
+}
+#endif
+
+namespace std {
+extern "C" int remove(const char *path) {
+ FilePath fp(path);
+ FileSystemLike *fs = fp.fileSystem();
+ if (fs == NULL) return -1;
+
+ return fs->remove(fp.fileName());
+}
+
+extern "C" int rename(const char *oldname, const char *newname) {
+ FilePath fpOld(oldname);
+ FilePath fpNew(newname);
+ FileSystemLike *fsOld = fpOld.fileSystem();
+ FileSystemLike *fsNew = fpNew.fileSystem();
+
+ /* rename only if both files are on the same FS */
+ if (fsOld != fsNew || fsOld == NULL) return -1;
+
+ return fsOld->rename(fpOld.fileName(), fpNew.fileName());
+}
+
+extern "C" char *tmpnam(char *s) {
+ return NULL;
+}
+
+extern "C" FILE *tmpfile() {
+ return NULL;
+}
+} // namespace std
+
+#ifdef __ARMCC_VERSION
+extern "C" char *_sys_command_string(char *cmd, int len) {
+ return NULL;
+}
+#endif
+
+extern "C" DIR *opendir(const char *path) {
+ /* root dir is FileSystemLike */
+ if (path[0] == '/' && path[1] == 0) {
+ return FileSystemLike::opendir();
+ }
+
+ FilePath fp(path);
+ FileSystemLike* fs = fp.fileSystem();
+ if (fs == NULL) return NULL;
+
+ return fs->opendir(fp.fileName());
+}
+
+extern "C" struct dirent *readdir(DIR *dir) {
+ return dir->readdir();
+}
+
+extern "C" int closedir(DIR *dir) {
+ return dir->closedir();
+}
+
+extern "C" void rewinddir(DIR *dir) {
+ dir->rewinddir();
+}
+
+extern "C" off_t telldir(DIR *dir) {
+ return dir->telldir();
+}
+
+extern "C" void seekdir(DIR *dir, off_t off) {
+ dir->seekdir(off);
+}
+
+extern "C" int mkdir(const char *path, mode_t mode) {
+ FilePath fp(path);
+ FileSystemLike *fs = fp.fileSystem();
+ if (fs == NULL) return -1;
+
+ return fs->mkdir(fp.fileName(), mode);
+}
+
+#if defined(TOOLCHAIN_GCC)
+/* prevents the exception handling name demangling code getting pulled in */
+#include "mbed_error.h"
+namespace __gnu_cxx {
+ void __verbose_terminate_handler() {
+ error("Exception");
+ }
+}
+extern "C" WEAK void __cxa_pure_virtual(void);
+extern "C" WEAK void __cxa_pure_virtual(void) {
+ exit(1);
+}
+
+#endif
+
+// ****************************************************************************
+// mbed_main is a function that is called before main()
+// mbed_sdk_init() is also a function that is called before main(), but unlike
+// mbed_main(), it is not meant for user code, but for the SDK itself to perform
+// initializations before main() is called.
+
+extern "C" WEAK void mbed_main(void);
+extern "C" WEAK void mbed_main(void) {
+}
+
+extern "C" WEAK void mbed_sdk_init(void);
+extern "C" WEAK void mbed_sdk_init(void) {
+}
+
+#if defined(TOOLCHAIN_ARM)
+extern "C" int $Super$$main(void);
+
+extern "C" int $Sub$$main(void) {
+ mbed_sdk_init();
+ mbed_main();
+ return $Super$$main();
+}
+#elif defined(TOOLCHAIN_GCC)
+extern "C" int __real_main(void);
+
+extern "C" int __wrap_main(void) {
+ mbed_sdk_init();
+ mbed_main();
+ return __real_main();
+}
+#elif defined(TOOLCHAIN_IAR)
+// IAR doesn't have the $Super/$Sub mechanism of armcc, nor something equivalent
+// to ld's --wrap. It does have a --redirect, but that doesn't help, since redirecting
+// 'main' to another symbol looses the original 'main' symbol. However, its startup
+// code will call a function to setup argc and argv (__iar_argc_argv) if it is defined.
+// Since mbed doesn't use argc/argv, we use this function to call our mbed_main.
+extern "C" void __iar_argc_argv() {
+ mbed_sdk_init();
+ mbed_main();
+}
+#endif
+
+// Provide implementation of _sbrk (low-level dynamic memory allocation
+// routine) for GCC_ARM which compares new heap pointer with MSP instead of
+// SP. This make it compatible with RTX RTOS thread stacks.
+#if defined(TOOLCHAIN_GCC_ARM)
+// Linker defined symbol used by _sbrk to indicate where heap should start.
+extern "C" int __end__;
+
+#if defined(TARGET_CORTEX_A)
+extern "C" uint32_t __HeapLimit;
+#endif
+
+// Turn off the errno macro and use actual global variable instead.
+#undef errno
+extern "C" int errno;
+
+// For ARM7 only
+register unsigned char * stack_ptr __asm ("sp");
+
+// Dynamic memory allocation related syscall.
+extern "C" caddr_t _sbrk(int incr) {
+ static unsigned char* heap = (unsigned char*)&__end__;
+ unsigned char* prev_heap = heap;
+ unsigned char* new_heap = heap + incr;
+
+#if defined(TARGET_ARM7)
+ if (new_heap >= stack_ptr) {
+#elif defined(TARGET_CORTEX_A)
+ if (new_heap >= (unsigned char*)&__HeapLimit) { /* __HeapLimit is end of heap section */
+#else
+ if (new_heap >= (unsigned char*)__get_MSP()) {
+#endif
+ errno = ENOMEM;
+ return (caddr_t)-1;
+ }
+
+ heap = new_heap;
+ return (caddr_t) prev_heap;
+}
+#endif
+
+
+#ifdef TOOLCHAIN_GCC_CW
+// TODO: Ideally, we would like to define directly "_ExitProcess"
+extern "C" void mbed_exit(int return_code) {
+#elif defined TOOLCHAIN_GCC_ARM
+extern "C" void _exit(int return_code) {
+#else
+namespace std {
+extern "C" void exit(int return_code) {
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+ fflush(stdout);
+ fflush(stderr);
+#endif
+
+#if DEVICE_SEMIHOST
+ if (mbed_interface_connected()) {
+ semihost_exit();
+ }
+#endif
+ if (return_code) {
+ mbed_die();
+ }
+
+ while (1);
+}
+
+#if !defined(TOOLCHAIN_GCC_ARM) && !defined(TOOLCHAIN_GCC_CW)
+} //namespace std
+#endif
+
+
+namespace mbed {
+
+void mbed_set_unbuffered_stream(FILE *_file) {
+#if defined (__ICCARM__)
+ char buf[2];
+ std::setvbuf(_file,buf,_IONBF,NULL);
+#else
+ setbuf(_file, NULL);
+#endif
+}
+
+int mbed_getc(FILE *_file){
+#if defined (__ICCARM__)
+ /*This is only valid for unbuffered streams*/
+ int res = std::fgetc(_file);
+ if (res>=0){
+ _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
+ _file->_Rend = _file->_Wend;
+ _file->_Next = _file->_Wend;
+ }
+ return res;
+#else
+ return std::fgetc(_file);
+#endif
+}
+
+char* mbed_gets(char*s, int size, FILE *_file){
+#if defined (__ICCARM__)
+ /*This is only valid for unbuffered streams*/
+ char *str = fgets(s,size,_file);
+ if (str!=NULL){
+ _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
+ _file->_Rend = _file->_Wend;
+ _file->_Next = _file->_Wend;
+ }
+ return str;
+#else
+ return std::fgets(s,size,_file);
+#endif
+}
+
+} // namespace mbed
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/rtc_time.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/rtc_time.c
new file mode 100644
index 000000000..982279746
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/rtc_time.c
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "rtc_api.h"
+
+#include <time.h>
+#include "rtc_time.h"
+#include "us_ticker_api.h"
+
+#if DEVICE_RTC
+static void (*_rtc_init)(void) = rtc_init;
+static int (*_rtc_isenabled)(void) = rtc_isenabled;
+static time_t (*_rtc_read)(void) = rtc_read;
+static void (*_rtc_write)(time_t t) = rtc_write;
+#else
+static void (*_rtc_init)(void) = NULL;
+static int (*_rtc_isenabled)(void) = NULL;
+static time_t (*_rtc_read)(void) = NULL;
+static void (*_rtc_write)(time_t t) = NULL;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if defined (__ICCARM__)
+time_t __time32(time_t *timer)
+#else
+time_t time(time_t *timer)
+#endif
+
+{
+ if (_rtc_isenabled != NULL) {
+ if (!(_rtc_isenabled())) {
+ set_time(0);
+ }
+ }
+
+ time_t t = 0;
+ if (_rtc_read != NULL) {
+ t = _rtc_read();
+ }
+
+ if (timer != NULL) {
+ *timer = t;
+ }
+ return t;
+}
+
+void set_time(time_t t) {
+ if (_rtc_init != NULL) {
+ _rtc_init();
+ }
+ if (_rtc_write != NULL) {
+ _rtc_write(t);
+ }
+}
+
+clock_t clock() {
+ clock_t t = us_ticker_read();
+ t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
+ return t;
+}
+
+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void)) {
+ __disable_irq();
+ _rtc_read = read_rtc;
+ _rtc_write = write_rtc;
+ _rtc_init = init_rtc;
+ _rtc_isenabled = isenabled_rtc;
+ __enable_irq();
+}
+
+
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/semihost_api.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/semihost_api.c
new file mode 100644
index 000000000..e4e136eca
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/semihost_api.c
@@ -0,0 +1,162 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis.h"
+#include "semihost_api.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#if DEVICE_SEMIHOST
+
+// ARM Semihosting Commands
+#define SYS_OPEN (0x1)
+#define SYS_CLOSE (0x2)
+#define SYS_WRITE (0x5)
+#define SYS_READ (0x6)
+#define SYS_ISTTY (0x9)
+#define SYS_SEEK (0xa)
+#define SYS_ENSURE (0xb)
+#define SYS_FLEN (0xc)
+#define SYS_REMOVE (0xe)
+#define SYS_RENAME (0xf)
+#define SYS_EXIT (0x18)
+
+// mbed Semihosting Commands
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) // 0x100 - 0x1ff
+#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
+#define USR_UID (RESERVED_FOR_USER_APPLICATIONS + 1)
+#define USR_RESET (RESERVED_FOR_USER_APPLICATIONS + 2)
+#define USR_VBUS (RESERVED_FOR_USER_APPLICATIONS + 3)
+#define USR_POWERDOWN (RESERVED_FOR_USER_APPLICATIONS + 4)
+#define USR_DISABLEDEBUG (RESERVED_FOR_USER_APPLICATIONS + 5)
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode) {
+ uint32_t args[3];
+ args[0] = (uint32_t)name;
+ args[1] = (uint32_t)openmode;
+ args[2] = (uint32_t)strlen(name);
+ return __semihost(SYS_OPEN, args);
+}
+
+int semihost_close(FILEHANDLE fh) {
+ return __semihost(SYS_CLOSE, &fh);
+}
+
+int semihost_write(FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode) {
+ if (length == 0) return 0;
+
+ uint32_t args[3];
+ args[0] = (uint32_t)fh;
+ args[1] = (uint32_t)buffer;
+ args[2] = (uint32_t)length;
+ return __semihost(SYS_WRITE, args);
+}
+
+int semihost_read(FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode) {
+ uint32_t args[3];
+ args[0] = (uint32_t)fh;
+ args[1] = (uint32_t)buffer;
+ args[2] = (uint32_t)length;
+ return __semihost(SYS_READ, args);
+}
+
+int semihost_istty(FILEHANDLE fh) {
+ return __semihost(SYS_ISTTY, &fh);
+}
+
+int semihost_seek(FILEHANDLE fh, long position) {
+ uint32_t args[2];
+ args[0] = (uint32_t)fh;
+ args[1] = (uint32_t)position;
+ return __semihost(SYS_SEEK, args);
+}
+
+int semihost_ensure(FILEHANDLE fh) {
+ return __semihost(SYS_ENSURE, &fh);
+}
+
+long semihost_flen(FILEHANDLE fh) {
+ return __semihost(SYS_FLEN, &fh);
+}
+
+int semihost_remove(const char *name) {
+ uint32_t args[2];
+ args[0] = (uint32_t)name;
+ args[1] = (uint32_t)strlen(name);
+ return __semihost(SYS_REMOVE, args);
+}
+
+int semihost_rename(const char *old_name, const char *new_name) {
+ uint32_t args[4];
+ args[0] = (uint32_t)old_name;
+ args[1] = (uint32_t)strlen(old_name);
+ args[0] = (uint32_t)new_name;
+ args[1] = (uint32_t)strlen(new_name);
+ return __semihost(SYS_RENAME, args);
+}
+#endif
+
+int semihost_exit(void) {
+ uint32_t args[4];
+ return __semihost(SYS_EXIT, args);
+}
+
+int semihost_uid(char *uid) {
+ uint32_t args[2];
+ args[0] = (uint32_t)uid;
+ args[1] = DEVICE_ID_LENGTH + 1;
+ return __semihost(USR_UID, &args);
+}
+
+int semihost_reset(void) {
+ // Does not normally return, however if used with older firmware versions
+ // that do not support this call it will return -1.
+ return __semihost(USR_RESET, NULL);
+}
+
+int semihost_vbus(void) {
+ return __semihost(USR_VBUS, NULL);
+}
+
+int semihost_powerdown(void) {
+ return __semihost(USR_POWERDOWN, NULL);
+}
+
+#if DEVICE_DEBUG_AWARENESS
+
+int semihost_connected(void) {
+ return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? 1 : 0;
+}
+
+#else
+// These processors cannot know if the interface is connect, assume so:
+static int is_debugger_attached = 1;
+
+int semihost_connected(void) {
+ return is_debugger_attached;
+}
+#endif
+
+int semihost_disabledebug(void) {
+#if !(DEVICE_DEBUG_AWARENESS)
+ is_debugger_attached = 0;
+#endif
+ return __semihost(USR_DISABLEDEBUG, NULL);
+}
+
+#endif
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/us_ticker_api.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/us_ticker_api.c
new file mode 100644
index 000000000..659a04f48
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/us_ticker_api.c
@@ -0,0 +1,134 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "cmsis.h"
+
+static ticker_event_handler event_handler;
+static ticker_event_t *head = NULL;
+
+void us_ticker_set_handler(ticker_event_handler handler) {
+ us_ticker_init();
+
+ event_handler = handler;
+}
+
+void us_ticker_irq_handler(void) {
+ us_ticker_clear_interrupt();
+
+ /* Go through all the pending TimerEvents */
+ while (1) {
+ if (head == NULL) {
+ // There are no more TimerEvents left, so disable matches.
+ us_ticker_disable_interrupt();
+ return;
+ }
+
+ if ((int)(head->timestamp - us_ticker_read()) <= 0) {
+ // This event was in the past:
+ // point to the following one and execute its handler
+ ticker_event_t *p = head;
+ head = head->next;
+ if (event_handler != NULL) {
+ event_handler(p->id); // NOTE: the handler can set new events
+ }
+ /* Note: We continue back to examining the head because calling the
+ * event handler may have altered the chain of pending events. */
+ } else {
+ // This event and the following ones in the list are in the future:
+ // set it as next interrupt and return
+ us_ticker_set_interrupt(head->timestamp);
+ return;
+ }
+ }
+}
+
+void us_ticker_insert_event(ticker_event_t *obj, timestamp_t timestamp, uint32_t id) {
+ /* disable interrupts for the duration of the function */
+ __disable_irq();
+
+ // initialise our data
+ obj->timestamp = timestamp;
+ obj->id = id;
+
+ /* Go through the list until we either reach the end, or find
+ an element this should come before (which is possibly the
+ head). */
+ ticker_event_t *prev = NULL, *p = head;
+ while (p != NULL) {
+ /* check if we come before p */
+ if ((int)(timestamp - p->timestamp) < 0) {
+ break;
+ }
+ /* go to the next element */
+ prev = p;
+ p = p->next;
+ }
+
+ /* if we're at the end p will be NULL, which is correct */
+ obj->next = p;
+
+ /* if prev is NULL we're at the head */
+ if (prev == NULL) {
+ head = obj;
+ us_ticker_set_interrupt(timestamp);
+ } else {
+ prev->next = obj;
+ }
+
+ __enable_irq();
+}
+
+void us_ticker_remove_event(ticker_event_t *obj) {
+ __disable_irq();
+
+ // remove this object from the list
+ if (head == obj) {
+ // first in the list, so just drop me
+ head = obj->next;
+ if (head == NULL) {
+ us_ticker_disable_interrupt();
+ } else {
+ us_ticker_set_interrupt(head->timestamp);
+ }
+ } else {
+ // find the object before me, then drop me
+ ticker_event_t* p = head;
+ while (p != NULL) {
+ if (p->next == obj) {
+ p->next = obj->next;
+ break;
+ }
+ p = p->next;
+ }
+ }
+
+ __enable_irq();
+}
+
+int us_ticker_get_next_timestamp(timestamp_t *timestamp) {
+ int ret = 0;
+
+ /* if head is NULL, there are no pending events */
+ __disable_irq();
+ if (head != NULL) {
+ *timestamp = head->timestamp;
+ ret = 1;
+ }
+ __enable_irq();
+
+ return ret;
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/wait_api.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/wait_api.c
new file mode 100644
index 000000000..b276614ca
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/common/wait_api.c
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "wait_api.h"
+#include "us_ticker_api.h"
+
+void wait(float s) {
+ wait_us(s * 1000000.0f);
+}
+
+void wait_ms(int ms) {
+ wait_us(ms * 1000);
+}
+
+void wait_us(int us) {
+ uint32_t start = us_ticker_read();
+ while ((us_ticker_read() - start) < (uint32_t)us);
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/analogin_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/analogin_api.h
new file mode 100644
index 000000000..98d02c1b8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/analogin_api.h
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_API_H
+#define MBED_ANALOGIN_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct analogin_s analogin_t;
+
+void analogin_init (analogin_t *obj, PinName pin);
+float analogin_read (analogin_t *obj);
+uint16_t analogin_read_u16(analogin_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/analogout_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/analogout_api.h
new file mode 100644
index 000000000..97a201376
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/analogout_api.h
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_API_H
+#define MBED_ANALOGOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct dac_s dac_t;
+
+void analogout_init (dac_t *obj, PinName pin);
+void analogout_free (dac_t *obj);
+void analogout_write (dac_t *obj, float value);
+void analogout_write_u16(dac_t *obj, uint16_t value);
+float analogout_read (dac_t *obj);
+uint16_t analogout_read_u16 (dac_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/can_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/can_api.h
new file mode 100644
index 000000000..48bc10469
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/can_api.h
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_API_H
+#define MBED_CAN_API_H
+
+#include "device.h"
+
+#if DEVICE_CAN
+
+#include "PinNames.h"
+#include "PeripheralNames.h"
+#include "can_helper.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ IRQ_RX,
+ IRQ_TX,
+ IRQ_ERROR,
+ IRQ_OVERRUN,
+ IRQ_WAKEUP,
+ IRQ_PASSIVE,
+ IRQ_ARB,
+ IRQ_BUS,
+ IRQ_READY
+} CanIrqType;
+
+
+typedef enum {
+ MODE_RESET,
+ MODE_NORMAL,
+ MODE_SILENT,
+ MODE_TEST_GLOBAL,
+ MODE_TEST_LOCAL,
+ MODE_TEST_SILENT
+} CanMode;
+
+typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
+
+typedef struct can_s can_t;
+
+void can_init (can_t *obj, PinName rd, PinName td);
+void can_free (can_t *obj);
+int can_frequency(can_t *obj, int hz);
+
+void can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id);
+void can_irq_free (can_t *obj);
+void can_irq_set (can_t *obj, CanIrqType irq, uint32_t enable);
+
+int can_write (can_t *obj, CAN_Message, int cc);
+int can_read (can_t *obj, CAN_Message *msg, int handle);
+int can_mode (can_t *obj, CanMode mode);
+int can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle);
+void can_reset (can_t *obj);
+unsigned char can_rderror (can_t *obj);
+unsigned char can_tderror (can_t *obj);
+void can_monitor (can_t *obj, int silent);
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif // MBED_CAN_API_H
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/ethernet_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/ethernet_api.h
new file mode 100644
index 000000000..4cae77e13
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/ethernet_api.h
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_API_H
+#define MBED_ETHERNET_API_H
+
+#include "device.h"
+
+#if DEVICE_ETHERNET
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Connection constants
+
+int ethernet_init(void);
+void ethernet_free(void);
+
+// write size bytes from data to ethernet buffer
+// return num bytes written
+// or -1 if size is too big
+int ethernet_write(const char *data, int size);
+
+// send ethernet write buffer, returning the packet size sent
+int ethernet_send(void);
+
+// recieve from ethernet buffer, returning packet size, or 0 if no packet
+int ethernet_receive(void);
+
+// read size bytes in to data, return actual num bytes read (0..size)
+// if data == NULL, throw the bytes away
+int ethernet_read(char *data, int size);
+
+// get the ethernet address
+void ethernet_address(char *mac);
+
+// see if the link is up
+int ethernet_link(void);
+
+// force link settings
+void ethernet_set_link(int speed, int duplex);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_api.h
new file mode 100644
index 000000000..872b547ea
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_api.h
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_API_H
+#define MBED_GPIO_API_H
+
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Set the given pin as GPIO
+ * @param pin The pin to be set as GPIO
+ * @return The GPIO port mask for this pin
+ **/
+uint32_t gpio_set(PinName pin);
+
+/* Checks if gpio object is connected (pin was not initialized with NC)
+ * @param pin The pin to be set as GPIO
+ * @return 0 if port is initialized with NC
+ **/
+int gpio_is_connected(const gpio_t *obj);
+
+/* GPIO object */
+void gpio_init(gpio_t *obj, PinName pin);
+
+void gpio_mode (gpio_t *obj, PinMode mode);
+void gpio_dir (gpio_t *obj, PinDirection direction);
+
+void gpio_write(gpio_t *obj, int value);
+int gpio_read (gpio_t *obj);
+
+// the following set of functions are generic and are implemented in the common gpio.c file
+void gpio_init_in(gpio_t* gpio, PinName pin);
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode);
+void gpio_init_out(gpio_t* gpio, PinName pin);
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value);
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_irq_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_irq_api.h
new file mode 100644
index 000000000..76c7e927e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/gpio_irq_api.h
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_IRQ_API_H
+#define MBED_GPIO_IRQ_API_H
+
+#include "device.h"
+
+#if DEVICE_INTERRUPTIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ IRQ_NONE,
+ IRQ_RISE,
+ IRQ_FALL
+} gpio_irq_event;
+
+typedef struct gpio_irq_s gpio_irq_t;
+
+typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
+void gpio_irq_free(gpio_irq_t *obj);
+void gpio_irq_set (gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
+void gpio_irq_enable(gpio_irq_t *obj);
+void gpio_irq_disable(gpio_irq_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/i2c_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/i2c_api.h
new file mode 100644
index 000000000..c4da824e7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/i2c_api.h
@@ -0,0 +1,60 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_API_H
+#define MBED_I2C_API_H
+
+#include "device.h"
+
+#if DEVICE_I2C
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct i2c_s i2c_t;
+
+enum {
+ I2C_ERROR_NO_SLAVE = -1,
+ I2C_ERROR_BUS_BUSY = -2
+};
+
+void i2c_init (i2c_t *obj, PinName sda, PinName scl);
+void i2c_frequency (i2c_t *obj, int hz);
+int i2c_start (i2c_t *obj);
+int i2c_stop (i2c_t *obj);
+int i2c_read (i2c_t *obj, int address, char *data, int length, int stop);
+int i2c_write (i2c_t *obj, int address, const char *data, int length, int stop);
+void i2c_reset (i2c_t *obj);
+int i2c_byte_read (i2c_t *obj, int last);
+int i2c_byte_write (i2c_t *obj, int data);
+
+#if DEVICE_I2CSLAVE
+void i2c_slave_mode (i2c_t *obj, int enable_slave);
+int i2c_slave_receive(i2c_t *obj);
+int i2c_slave_read (i2c_t *obj, char *data, int length);
+int i2c_slave_write (i2c_t *obj, const char *data, int length);
+int i2c_slave_byte_read(i2c_t *obj, int last);
+int i2c_slave_byte_write(i2c_t *obj, int data);
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/pinmap.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/pinmap.h
new file mode 100644
index 000000000..a9cc92186
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/pinmap.h
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINMAP_H
+#define MBED_PINMAP_H
+
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ PinName pin;
+ int peripheral;
+ int function;
+} PinMap;
+
+void pin_function(PinName pin, int function);
+void pin_mode (PinName pin, PinMode mode);
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
+uint32_t pinmap_function(PinName pin, const PinMap* map);
+uint32_t pinmap_merge (uint32_t a, uint32_t b);
+void pinmap_pinout (PinName pin, const PinMap *map);
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);
+uint32_t pinmap_find_function(PinName pin, const PinMap* map);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/port_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/port_api.h
new file mode 100644
index 000000000..f687cfe89
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/port_api.h
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTMAP_H
+#define MBED_PORTMAP_H
+
+#include "device.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct port_s port_t;
+
+PinName port_pin(PortName port, int pin_n);
+
+void port_init (port_t *obj, PortName port, int mask, PinDirection dir);
+void port_mode (port_t *obj, PinMode mode);
+void port_dir (port_t *obj, PinDirection dir);
+void port_write(port_t *obj, int value);
+int port_read (port_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/pwmout_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/pwmout_api.h
new file mode 100644
index 000000000..6557fcdc4
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/pwmout_api.h
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_API_H
+#define MBED_PWMOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_PWMOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct pwmout_s pwmout_t;
+
+void pwmout_init (pwmout_t* obj, PinName pin);
+void pwmout_free (pwmout_t* obj);
+
+void pwmout_write (pwmout_t* obj, float percent);
+float pwmout_read (pwmout_t* obj);
+
+void pwmout_period (pwmout_t* obj, float seconds);
+void pwmout_period_ms (pwmout_t* obj, int ms);
+void pwmout_period_us (pwmout_t* obj, int us);
+
+void pwmout_pulsewidth (pwmout_t* obj, float seconds);
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms);
+void pwmout_pulsewidth_us(pwmout_t* obj, int us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/rtc_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/rtc_api.h
new file mode 100644
index 000000000..663f8884f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/rtc_api.h
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RTC_API_H
+#define MBED_RTC_API_H
+
+#include "device.h"
+
+#if DEVICE_RTC
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void rtc_init(void);
+void rtc_free(void);
+int rtc_isenabled(void);
+
+time_t rtc_read(void);
+void rtc_write(time_t t);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/serial_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/serial_api.h
new file mode 100644
index 000000000..2b0f0c4ab
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/serial_api.h
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_API_H
+#define MBED_SERIAL_API_H
+
+#include "device.h"
+
+#if DEVICE_SERIAL
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ParityNone = 0,
+ ParityOdd = 1,
+ ParityEven = 2,
+ ParityForced1 = 3,
+ ParityForced0 = 4
+} SerialParity;
+
+typedef enum {
+ RxIrq,
+ TxIrq
+} SerialIrq;
+
+typedef enum {
+ FlowControlNone,
+ FlowControlRTS,
+ FlowControlCTS,
+ FlowControlRTSCTS
+} FlowControl;
+
+typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
+
+typedef struct serial_s serial_t;
+
+void serial_init (serial_t *obj, PinName tx, PinName rx);
+void serial_free (serial_t *obj);
+void serial_baud (serial_t *obj, int baudrate);
+void serial_format (serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
+void serial_irq_set (serial_t *obj, SerialIrq irq, uint32_t enable);
+
+int serial_getc (serial_t *obj);
+void serial_putc (serial_t *obj, int c);
+int serial_readable (serial_t *obj);
+int serial_writable (serial_t *obj);
+void serial_clear (serial_t *obj);
+
+void serial_break_set (serial_t *obj);
+void serial_break_clear(serial_t *obj);
+
+void serial_pinout_tx(PinName tx);
+
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/sleep_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/sleep_api.h
new file mode 100644
index 000000000..c8cf3b6f8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/sleep_api.h
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SLEEP_API_H
+#define MBED_SLEEP_API_H
+
+#include "device.h"
+
+#if DEVICE_SLEEP
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Send the microcontroller to sleep
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void sleep(void);
+
+/** Send the microcontroller to deep sleep
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ * The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void deepsleep(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/spi_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/spi_api.h
new file mode 100644
index 000000000..7553dc1e3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/spi_api.h
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_API_H
+#define MBED_SPI_API_H
+
+#include "device.h"
+
+#if DEVICE_SPI
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct spi_s spi_t;
+
+void spi_init (spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
+void spi_free (spi_t *obj);
+void spi_format (spi_t *obj, int bits, int mode, int slave);
+void spi_frequency (spi_t *obj, int hz);
+int spi_master_write (spi_t *obj, int value);
+int spi_slave_receive(spi_t *obj);
+int spi_slave_read (spi_t *obj);
+void spi_slave_write (spi_t *obj, int value);
+int spi_busy (spi_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/us_ticker_api.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/us_ticker_api.h
new file mode 100644
index 000000000..1fa93170e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/hal/us_ticker_api.h
@@ -0,0 +1,52 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_US_TICKER_API_H
+#define MBED_US_TICKER_API_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef uint32_t timestamp_t;
+
+uint32_t us_ticker_read(void);
+
+typedef void (*ticker_event_handler)(uint32_t id);
+void us_ticker_set_handler(ticker_event_handler handler);
+
+typedef struct ticker_event_s {
+ timestamp_t timestamp;
+ uint32_t id;
+ struct ticker_event_s *next;
+} ticker_event_t;
+
+void us_ticker_init(void);
+void us_ticker_set_interrupt(timestamp_t timestamp);
+void us_ticker_disable_interrupt(void);
+void us_ticker_clear_interrupt(void);
+void us_ticker_irq_handler(void);
+
+void us_ticker_insert_event(ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
+void us_ticker_remove_event(ticker_event_t *obj);
+int us_ticker_get_next_timestamp(timestamp_t *timestamp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/MK20D5.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/MK20D5.h
new file mode 100644
index 000000000..b979eb7db
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/MK20D5.h
@@ -0,0 +1,5836 @@
+/*
+** ###################################################################
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
+** K20P32M50SF0RM Rev. 1, Oct 2011
+** K20P48M50SF0RM Rev. 1, Oct 2011
+**
+** Version: rev. 2.0, 2012-03-19
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MK20D5
+**
+** Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2011-12-15)
+** Initial version
+** - rev. 2.0 (2012-03-19)
+** PDB Peripheral register structure updated.
+** DMA Registers and bits for unsupported DMA channels removed.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK20D5.h
+ * @version 2.0
+ * @date 2012-03-19
+ * @brief CMSIS Peripheral Access Layer for MK20D5
+ *
+ * CMSIS Peripheral Access Layer for MK20D5
+ */
+
+#if !defined(MK20D5_H_)
+#define MK20D5_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000u
+
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
+ DMA_Error_IRQn = 4, /**< DMA error interrupt */
+ Reserved21_IRQn = 5, /**< Reserved interrupt 21 */
+ FTFL_IRQn = 6, /**< FTFL interrupt */
+ Read_Collision_IRQn = 7, /**< Read collision interrupt */
+ LVD_LVW_IRQn = 8, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 9, /**< Low Leakage Wakeup */
+ Watchdog_IRQn = 10, /**< WDOG interrupt */
+ I2C0_IRQn = 11, /**< I2C0 interrupt */
+ SPI0_IRQn = 12, /**< SPI0 interrupt */
+ I2S0_Tx_IRQn = 13, /**< I2S0 transmit interrupt */
+ I2S0_Rx_IRQn = 14, /**< I2S0 receive interrupt */
+ UART0_LON_IRQn = 15, /**< UART0 LON interrupt */
+ UART0_RX_TX_IRQn = 16, /**< UART0 receive/transmit interrupt */
+ UART0_ERR_IRQn = 17, /**< UART0 error interrupt */
+ UART1_RX_TX_IRQn = 18, /**< UART1 receive/transmit interrupt */
+ UART1_ERR_IRQn = 19, /**< UART1 error interrupt */
+ UART2_RX_TX_IRQn = 20, /**< UART2 receive/transmit interrupt */
+ UART2_ERR_IRQn = 21, /**< UART2 error interrupt */
+ ADC0_IRQn = 22, /**< ADC0 interrupt */
+ CMP0_IRQn = 23, /**< CMP0 interrupt */
+ CMP1_IRQn = 24, /**< CMP1 interrupt */
+ FTM0_IRQn = 25, /**< FTM0 fault, overflow and channels interrupt */
+ FTM1_IRQn = 26, /**< FTM1 fault, overflow and channels interrupt */
+ CMT_IRQn = 27, /**< CMT interrupt */
+ RTC_IRQn = 28, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 29, /**< RTC seconds interrupt */
+ PIT0_IRQn = 30, /**< PIT timer channel 0 interrupt */
+ PIT1_IRQn = 31, /**< PIT timer channel 1 interrupt */
+ PIT2_IRQn = 32, /**< PIT timer channel 2 interrupt */
+ PIT3_IRQn = 33, /**< PIT timer channel 3 interrupt */
+ PDB0_IRQn = 34, /**< PDB0 interrupt */
+ USB0_IRQn = 35, /**< USB0 interrupt */
+ USBDCD_IRQn = 36, /**< USBDCD interrupt */
+ TSI0_IRQn = 37, /**< TSI0 interrupt */
+ MCG_IRQn = 38, /**< MCG interrupt */
+ LPTimer_IRQn = 39, /**< LPTimer interrupt */
+ PORTA_IRQn = 40, /**< Port A interrupt */
+ PORTB_IRQn = 41, /**< Port B interrupt */
+ PORTC_IRQn = 42, /**< Port C interrupt */
+ PORTD_IRQn = 43, /**< Port D interrupt */
+ PORTE_IRQn = 44, /**< Port E interrupt */
+ SWI_IRQn = 45 /**< Software interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M4 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm4.h" /* Core Peripheral Access Layer */
+#include "system_MK20D5.h" /* Device specific configuration file */
+
+/**
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/**
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+
+/**
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1 ((CMP_Type *)CMP1_BASE)
+
+/**
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+ __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+ __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+ __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+ __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
+ __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
+ __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+ __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+ __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
+ __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+ __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
+ __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
+} CMT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK 0xFFu
+#define CMT_CGH1_PH_SHIFT 0
+#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
+/* CGL1 Bit Fields */
+#define CMT_CGL1_PL_MASK 0xFFu
+#define CMT_CGL1_PL_SHIFT 0
+#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
+/* CGH2 Bit Fields */
+#define CMT_CGH2_SH_MASK 0xFFu
+#define CMT_CGH2_SH_SHIFT 0
+#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
+/* CGL2 Bit Fields */
+#define CMT_CGL2_SL_MASK 0xFFu
+#define CMT_CGL2_SL_SHIFT 0
+#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
+/* OC Bit Fields */
+#define CMT_OC_IROPEN_MASK 0x20u
+#define CMT_OC_IROPEN_SHIFT 5
+#define CMT_OC_CMTPOL_MASK 0x40u
+#define CMT_OC_CMTPOL_SHIFT 6
+#define CMT_OC_IROL_MASK 0x80u
+#define CMT_OC_IROL_SHIFT 7
+/* MSC Bit Fields */
+#define CMT_MSC_MCGEN_MASK 0x1u
+#define CMT_MSC_MCGEN_SHIFT 0
+#define CMT_MSC_EOCIE_MASK 0x2u
+#define CMT_MSC_EOCIE_SHIFT 1
+#define CMT_MSC_FSK_MASK 0x4u
+#define CMT_MSC_FSK_SHIFT 2
+#define CMT_MSC_BASE_MASK 0x8u
+#define CMT_MSC_BASE_SHIFT 3
+#define CMT_MSC_EXSPC_MASK 0x10u
+#define CMT_MSC_EXSPC_SHIFT 4
+#define CMT_MSC_CMTDIV_MASK 0x60u
+#define CMT_MSC_CMTDIV_SHIFT 5
+#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK 0x80u
+#define CMT_MSC_EOCF_SHIFT 7
+/* CMD1 Bit Fields */
+#define CMT_CMD1_MB_MASK 0xFFu
+#define CMT_CMD1_MB_SHIFT 0
+#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
+/* CMD2 Bit Fields */
+#define CMT_CMD2_MB_MASK 0xFFu
+#define CMT_CMD2_MB_SHIFT 0
+#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
+/* CMD3 Bit Fields */
+#define CMT_CMD3_SB_MASK 0xFFu
+#define CMT_CMD3_SB_SHIFT 0
+#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
+/* CMD4 Bit Fields */
+#define CMT_CMD4_SB_MASK 0xFFu
+#define CMT_CMD4_SB_SHIFT 0
+#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
+/* PPS Bit Fields */
+#define CMT_PPS_PPSDIV_MASK 0xFu
+#define CMT_PPS_PPSDIV_SHIFT 0
+#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
+/* DMA Bit Fields */
+#define CMT_DMA_DMA_MASK 0x1u
+#define CMT_DMA_DMA_SHIFT 0
+
+/**
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT ((CMT_Type *)CMT_BASE)
+
+/**
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
+ __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
+ } ACCESS16BIT;
+ __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
+ __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
+ __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
+ __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
+ } ACCESS8BIT;
+ };
+ union { /* offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
+ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
+ } GPOLY_ACCESS16BIT;
+ __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
+ __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
+ __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
+ __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
+ } GPOLY_ACCESS8BIT;
+ };
+ union { /* offset: 0x8 */
+ __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
+ struct { /* offset: 0x8 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
+ } CTRL_ACCESS8BIT;
+ };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* CRCL Bit Fields */
+#define CRC_CRCL_CRCL_MASK 0xFFFFu
+#define CRC_CRCL_CRCL_SHIFT 0
+#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
+/* CRCH Bit Fields */
+#define CRC_CRCH_CRCH_MASK 0xFFFFu
+#define CRC_CRCH_CRCH_SHIFT 0
+#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
+/* CRC Bit Fields */
+#define CRC_CRC_LL_MASK 0xFFu
+#define CRC_CRC_LL_SHIFT 0
+#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
+#define CRC_CRC_LU_MASK 0xFF00u
+#define CRC_CRC_LU_SHIFT 8
+#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
+#define CRC_CRC_HL_MASK 0xFF0000u
+#define CRC_CRC_HL_SHIFT 16
+#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
+#define CRC_CRC_HU_MASK 0xFF000000u
+#define CRC_CRC_HU_SHIFT 24
+#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
+/* CRCLL Bit Fields */
+#define CRC_CRCLL_CRCLL_MASK 0xFFu
+#define CRC_CRCLL_CRCLL_SHIFT 0
+#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
+/* CRCLU Bit Fields */
+#define CRC_CRCLU_CRCLU_MASK 0xFFu
+#define CRC_CRCLU_CRCLU_SHIFT 0
+#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
+/* CRCHL Bit Fields */
+#define CRC_CRCHL_CRCHL_MASK 0xFFu
+#define CRC_CRCHL_CRCHL_SHIFT 0
+#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
+/* CRCHU Bit Fields */
+#define CRC_CRCHU_CRCHU_MASK 0xFFu
+#define CRC_CRCHU_CRCHU_SHIFT 0
+#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT 0
+#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT 0
+#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK 0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT 0
+#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT 16
+#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
+#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
+#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
+#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
+#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK 0x1000000u
+#define CRC_CTRL_TCRC_SHIFT 24
+#define CRC_CTRL_WAS_MASK 0x2000000u
+#define CRC_CTRL_WAS_SHIFT 25
+#define CRC_CTRL_FXOR_MASK 0x4000000u
+#define CRC_CTRL_FXOR_SHIFT 26
+#define CRC_CTRL_TOTR_MASK 0x30000000u
+#define CRC_CTRL_TOTR_SHIFT 28
+#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK 0xC0000000u
+#define CRC_CTRL_TOT_SHIFT 30
+#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK 0x1u
+#define CRC_CTRLHU_TCRC_SHIFT 0
+#define CRC_CTRLHU_WAS_MASK 0x2u
+#define CRC_CTRLHU_WAS_SHIFT 1
+#define CRC_CTRLHU_FXOR_MASK 0x4u
+#define CRC_CTRLHU_FXOR_SHIFT 2
+#define CRC_CTRLHU_TOTR_MASK 0x30u
+#define CRC_CTRLHU_TOTR_SHIFT 4
+#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK 0xC0u
+#define CRC_CTRLHU_TOT_SHIFT 6
+#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/**
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0 ((CRC_Type *)CRC_BASE)
+
+/**
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< Control Register, offset: 0x0 */
+ __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
+ __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+ __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
+ __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
+ __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
+ __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
+ __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
+ __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
+ __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
+ uint8_t RESERVED_5[200];
+ __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
+ __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
+ __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
+ __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
+ uint8_t RESERVED_6[3836];
+ struct { /* offset: 0x1000, array step: 0x20 */
+ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+ union { /* offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+ };
+ __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+ union { /* offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+ };
+ __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+ __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+ union { /* offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+ };
+ } TCD[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK 0x2u
+#define DMA_CR_EDBG_SHIFT 1
+#define DMA_CR_ERCA_MASK 0x4u
+#define DMA_CR_ERCA_SHIFT 2
+#define DMA_CR_HOE_MASK 0x10u
+#define DMA_CR_HOE_SHIFT 4
+#define DMA_CR_HALT_MASK 0x20u
+#define DMA_CR_HALT_SHIFT 5
+#define DMA_CR_CLM_MASK 0x40u
+#define DMA_CR_CLM_SHIFT 6
+#define DMA_CR_EMLM_MASK 0x80u
+#define DMA_CR_EMLM_SHIFT 7
+#define DMA_CR_ECX_MASK 0x10000u
+#define DMA_CR_ECX_SHIFT 16
+#define DMA_CR_CX_MASK 0x20000u
+#define DMA_CR_CX_SHIFT 17
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK 0x1u
+#define DMA_ES_DBE_SHIFT 0
+#define DMA_ES_SBE_MASK 0x2u
+#define DMA_ES_SBE_SHIFT 1
+#define DMA_ES_SGE_MASK 0x4u
+#define DMA_ES_SGE_SHIFT 2
+#define DMA_ES_NCE_MASK 0x8u
+#define DMA_ES_NCE_SHIFT 3
+#define DMA_ES_DOE_MASK 0x10u
+#define DMA_ES_DOE_SHIFT 4
+#define DMA_ES_DAE_MASK 0x20u
+#define DMA_ES_DAE_SHIFT 5
+#define DMA_ES_SOE_MASK 0x40u
+#define DMA_ES_SOE_SHIFT 6
+#define DMA_ES_SAE_MASK 0x80u
+#define DMA_ES_SAE_SHIFT 7
+#define DMA_ES_ERRCHN_MASK 0xF00u
+#define DMA_ES_ERRCHN_SHIFT 8
+#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK 0x4000u
+#define DMA_ES_CPE_SHIFT 14
+#define DMA_ES_ECX_MASK 0x10000u
+#define DMA_ES_ECX_SHIFT 16
+#define DMA_ES_VLD_MASK 0x80000000u
+#define DMA_ES_VLD_SHIFT 31
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK 0x1u
+#define DMA_ERQ_ERQ0_SHIFT 0
+#define DMA_ERQ_ERQ1_MASK 0x2u
+#define DMA_ERQ_ERQ1_SHIFT 1
+#define DMA_ERQ_ERQ2_MASK 0x4u
+#define DMA_ERQ_ERQ2_SHIFT 2
+#define DMA_ERQ_ERQ3_MASK 0x8u
+#define DMA_ERQ_ERQ3_SHIFT 3
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK 0x1u
+#define DMA_EEI_EEI0_SHIFT 0
+#define DMA_EEI_EEI1_MASK 0x2u
+#define DMA_EEI_EEI1_SHIFT 1
+#define DMA_EEI_EEI2_MASK 0x4u
+#define DMA_EEI_EEI2_SHIFT 2
+#define DMA_EEI_EEI3_MASK 0x8u
+#define DMA_EEI_EEI3_SHIFT 3
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK 0xFu
+#define DMA_CEEI_CEEI_SHIFT 0
+#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK 0x40u
+#define DMA_CEEI_CAEE_SHIFT 6
+#define DMA_CEEI_NOP_MASK 0x80u
+#define DMA_CEEI_NOP_SHIFT 7
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK 0xFu
+#define DMA_SEEI_SEEI_SHIFT 0
+#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK 0x40u
+#define DMA_SEEI_SAEE_SHIFT 6
+#define DMA_SEEI_NOP_MASK 0x80u
+#define DMA_SEEI_NOP_SHIFT 7
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK 0xFu
+#define DMA_CERQ_CERQ_SHIFT 0
+#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK 0x40u
+#define DMA_CERQ_CAER_SHIFT 6
+#define DMA_CERQ_NOP_MASK 0x80u
+#define DMA_CERQ_NOP_SHIFT 7
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK 0xFu
+#define DMA_SERQ_SERQ_SHIFT 0
+#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK 0x40u
+#define DMA_SERQ_SAER_SHIFT 6
+#define DMA_SERQ_NOP_MASK 0x80u
+#define DMA_SERQ_NOP_SHIFT 7
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK 0xFu
+#define DMA_CDNE_CDNE_SHIFT 0
+#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK 0x40u
+#define DMA_CDNE_CADN_SHIFT 6
+#define DMA_CDNE_NOP_MASK 0x80u
+#define DMA_CDNE_NOP_SHIFT 7
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK 0xFu
+#define DMA_SSRT_SSRT_SHIFT 0
+#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK 0x40u
+#define DMA_SSRT_SAST_SHIFT 6
+#define DMA_SSRT_NOP_MASK 0x80u
+#define DMA_SSRT_NOP_SHIFT 7
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK 0xFu
+#define DMA_CERR_CERR_SHIFT 0
+#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK 0x40u
+#define DMA_CERR_CAEI_SHIFT 6
+#define DMA_CERR_NOP_MASK 0x80u
+#define DMA_CERR_NOP_SHIFT 7
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK 0xFu
+#define DMA_CINT_CINT_SHIFT 0
+#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK 0x40u
+#define DMA_CINT_CAIR_SHIFT 6
+#define DMA_CINT_NOP_MASK 0x80u
+#define DMA_CINT_NOP_SHIFT 7
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK 0x1u
+#define DMA_INT_INT0_SHIFT 0
+#define DMA_INT_INT1_MASK 0x2u
+#define DMA_INT_INT1_SHIFT 1
+#define DMA_INT_INT2_MASK 0x4u
+#define DMA_INT_INT2_SHIFT 2
+#define DMA_INT_INT3_MASK 0x8u
+#define DMA_INT_INT3_SHIFT 3
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK 0x1u
+#define DMA_ERR_ERR0_SHIFT 0
+#define DMA_ERR_ERR1_MASK 0x2u
+#define DMA_ERR_ERR1_SHIFT 1
+#define DMA_ERR_ERR2_MASK 0x4u
+#define DMA_ERR_ERR2_SHIFT 2
+#define DMA_ERR_ERR3_MASK 0x8u
+#define DMA_ERR_ERR3_SHIFT 3
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK 0x1u
+#define DMA_HRS_HRS0_SHIFT 0
+#define DMA_HRS_HRS1_MASK 0x2u
+#define DMA_HRS_HRS1_SHIFT 1
+#define DMA_HRS_HRS2_MASK 0x4u
+#define DMA_HRS_HRS2_SHIFT 2
+#define DMA_HRS_HRS3_MASK 0x8u
+#define DMA_HRS_HRS3_SHIFT 3
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK 0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT 0
+#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK 0x40u
+#define DMA_DCHPRI3_DPA_SHIFT 6
+#define DMA_DCHPRI3_ECP_MASK 0x80u
+#define DMA_DCHPRI3_ECP_SHIFT 7
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK 0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT 0
+#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK 0x40u
+#define DMA_DCHPRI2_DPA_SHIFT 6
+#define DMA_DCHPRI2_ECP_MASK 0x80u
+#define DMA_DCHPRI2_ECP_SHIFT 7
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK 0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT 0
+#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK 0x40u
+#define DMA_DCHPRI1_DPA_SHIFT 6
+#define DMA_DCHPRI1_ECP_MASK 0x80u
+#define DMA_DCHPRI1_ECP_SHIFT 7
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK 0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT 0
+#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK 0x40u
+#define DMA_DCHPRI0_DPA_SHIFT 6
+#define DMA_DCHPRI0_ECP_MASK 0x80u
+#define DMA_DCHPRI0_ECP_SHIFT 7
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT 0
+#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK 0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT 0
+#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK 0x7u
+#define DMA_ATTR_DSIZE_SHIFT 0
+#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK 0xF8u
+#define DMA_ATTR_DMOD_SHIFT 3
+#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK 0x700u
+#define DMA_ATTR_SSIZE_SHIFT 8
+#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK 0xF800u
+#define DMA_ATTR_SMOD_SHIFT 11
+#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
+#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT 0
+#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT 0
+#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK 0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT 0
+#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT 0
+#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT 0
+#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
+#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK 0x1u
+#define DMA_CSR_START_SHIFT 0
+#define DMA_CSR_INTMAJOR_MASK 0x2u
+#define DMA_CSR_INTMAJOR_SHIFT 1
+#define DMA_CSR_INTHALF_MASK 0x4u
+#define DMA_CSR_INTHALF_SHIFT 2
+#define DMA_CSR_DREQ_MASK 0x8u
+#define DMA_CSR_DREQ_SHIFT 3
+#define DMA_CSR_ESG_MASK 0x10u
+#define DMA_CSR_ESG_SHIFT 4
+#define DMA_CSR_MAJORELINK_MASK 0x20u
+#define DMA_CSR_MAJORELINK_SHIFT 5
+#define DMA_CSR_ACTIVE_MASK 0x40u
+#define DMA_CSR_ACTIVE_SHIFT 6
+#define DMA_CSR_DONE_MASK 0x80u
+#define DMA_CSR_DONE_SHIFT 7
+#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT 8
+#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK 0xC000u
+#define DMA_CSR_BWC_SHIFT 14
+#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT 0
+#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT 0
+#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
+
+/**
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+
+/**
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
+ __O uint8_t SERV; /**< Service Register, offset: 0x1 */
+ __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
+ __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
+} EWM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- EWM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK 0x1u
+#define EWM_CTRL_EWMEN_SHIFT 0
+#define EWM_CTRL_ASSIN_MASK 0x2u
+#define EWM_CTRL_ASSIN_SHIFT 1
+#define EWM_CTRL_INEN_MASK 0x4u
+#define EWM_CTRL_INEN_SHIFT 2
+#define EWM_CTRL_INTEN_MASK 0x8u
+#define EWM_CTRL_INTEN_SHIFT 3
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK 0xFFu
+#define EWM_SERV_SERVICE_SHIFT 0
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK 0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT 0
+#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK 0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT 0
+#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+
+/**
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM ((EWM_Type *)EWM_BASE)
+
+/**
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
+ __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */
+ uint8_t RESERVED_0[248];
+ struct { /* offset: 0x100, array step: 0x20 */
+ __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
+ uint8_t RESERVED_0[24];
+ } TAG_WAY[4];
+ uint8_t RESERVED_1[132];
+ struct { /* offset: 0x204, array step: 0x8 */
+ __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW0S[2];
+ uint8_t RESERVED_2[48];
+ struct { /* offset: 0x244, array step: 0x8 */
+ __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW1S[2];
+ uint8_t RESERVED_3[48];
+ struct { /* offset: 0x284, array step: 0x8 */
+ __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW2S[2];
+ uint8_t RESERVED_4[48];
+ struct { /* offset: 0x2C4, array step: 0x8 */
+ __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW3S[2];
+} FMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK 0x3u
+#define FMC_PFAPR_M0AP_SHIFT 0
+#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK 0xCu
+#define FMC_PFAPR_M1AP_SHIFT 2
+#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK 0x30u
+#define FMC_PFAPR_M2AP_SHIFT 4
+#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK 0xC0u
+#define FMC_PFAPR_M3AP_SHIFT 6
+#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK 0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT 16
+#define FMC_PFAPR_M1PFD_MASK 0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT 17
+#define FMC_PFAPR_M2PFD_MASK 0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT 18
+#define FMC_PFAPR_M3PFD_MASK 0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT 19
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK 0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT 0
+#define FMC_PFB0CR_B0IPE_MASK 0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT 1
+#define FMC_PFB0CR_B0DPE_MASK 0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT 2
+#define FMC_PFB0CR_B0ICE_MASK 0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT 3
+#define FMC_PFB0CR_B0DCE_MASK 0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT 4
+#define FMC_PFB0CR_CRC_MASK 0xE0u
+#define FMC_PFB0CR_CRC_SHIFT 5
+#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK 0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT 17
+#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT 19
+#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT 20
+#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
+#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT 28
+#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* TAGVD Bit Fields */
+#define FMC_TAGVD_valid_MASK 0x1u
+#define FMC_TAGVD_valid_SHIFT 0
+#define FMC_TAGVD_tag_MASK 0x7FFC0u
+#define FMC_TAGVD_tag_SHIFT 6
+#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
+/* DATAW0S Bit Fields */
+#define FMC_DATAW0S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW0S_data_SHIFT 0
+#define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK)
+/* DATAW1S Bit Fields */
+#define FMC_DATAW1S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW1S_data_SHIFT 0
+#define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK)
+/* DATAW2S Bit Fields */
+#define FMC_DATAW2S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW2S_data_SHIFT 0
+#define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK)
+/* DATAW3S Bit Fields */
+#define FMC_DATAW3S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW3S_data_SHIFT 0
+#define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK)
+
+/**
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC ((FMC_Type *)FMC_BASE)
+
+/**
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFL Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
+ * @{
+ */
+
+/** FTFL - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
+ __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
+} FTFL_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFL Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFL_Register_Masks FTFL Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFL_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFL_FSTAT_MGSTAT0_SHIFT 0
+#define FTFL_FSTAT_FPVIOL_MASK 0x10u
+#define FTFL_FSTAT_FPVIOL_SHIFT 4
+#define FTFL_FSTAT_ACCERR_MASK 0x20u
+#define FTFL_FSTAT_ACCERR_SHIFT 5
+#define FTFL_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFL_FSTAT_RDCOLERR_SHIFT 6
+#define FTFL_FSTAT_CCIF_MASK 0x80u
+#define FTFL_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFL_FCNFG_EEERDY_MASK 0x1u
+#define FTFL_FCNFG_EEERDY_SHIFT 0
+#define FTFL_FCNFG_RAMRDY_MASK 0x2u
+#define FTFL_FCNFG_RAMRDY_SHIFT 1
+#define FTFL_FCNFG_PFLSH_MASK 0x4u
+#define FTFL_FCNFG_PFLSH_SHIFT 2
+#define FTFL_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFL_FCNFG_ERSSUSP_SHIFT 4
+#define FTFL_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFL_FCNFG_ERSAREQ_SHIFT 5
+#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFL_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFL_FCNFG_CCIE_MASK 0x80u
+#define FTFL_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFL_FSEC_SEC_MASK 0x3u
+#define FTFL_FSEC_SEC_SHIFT 0
+#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
+#define FTFL_FSEC_FSLACC_MASK 0xCu
+#define FTFL_FSEC_FSLACC_SHIFT 2
+#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
+#define FTFL_FSEC_MEEN_MASK 0x30u
+#define FTFL_FSEC_MEEN_SHIFT 4
+#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
+#define FTFL_FSEC_KEYEN_MASK 0xC0u
+#define FTFL_FSEC_KEYEN_SHIFT 6
+#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFL_FOPT_OPT_MASK 0xFFu
+#define FTFL_FOPT_OPT_SHIFT 0
+#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFL_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB3_CCOBn_SHIFT 0
+#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFL_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB2_CCOBn_SHIFT 0
+#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFL_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB1_CCOBn_SHIFT 0
+#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFL_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB0_CCOBn_SHIFT 0
+#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFL_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB7_CCOBn_SHIFT 0
+#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFL_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB6_CCOBn_SHIFT 0
+#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFL_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB5_CCOBn_SHIFT 0
+#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFL_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB4_CCOBn_SHIFT 0
+#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFL_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFL_FCCOBB_CCOBn_SHIFT 0
+#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFL_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFL_FCCOBA_CCOBn_SHIFT 0
+#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFL_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB9_CCOBn_SHIFT 0
+#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFL_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB8_CCOBn_SHIFT 0
+#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFL_FPROT3_PROT_MASK 0xFFu
+#define FTFL_FPROT3_PROT_SHIFT 0
+#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFL_FPROT2_PROT_MASK 0xFFu
+#define FTFL_FPROT2_PROT_SHIFT 0
+#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFL_FPROT1_PROT_MASK 0xFFu
+#define FTFL_FPROT1_PROT_SHIFT 0
+#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFL_FPROT0_PROT_MASK 0xFFu
+#define FTFL_FPROT0_PROT_SHIFT 0
+#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFL_FEPROT_EPROT_MASK 0xFFu
+#define FTFL_FEPROT_EPROT_SHIFT 0
+#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFL_FDPROT_DPROT_MASK 0xFFu
+#define FTFL_FDPROT_DPROT_SHIFT 0
+#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
+
+/**
+ * @}
+ */ /* end of group FTFL_Register_Masks */
+
+
+/* FTFL - Peripheral instance base addresses */
+/** Peripheral FTFL base address */
+#define FTFL_BASE (0x40020000u)
+/** Peripheral FTFL base pointer */
+#define FTFL ((FTFL_Type *)FTFL_BASE)
+
+/**
+ * @}
+ */ /* end of group FTFL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[8];
+ __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
+ __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
+ __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
+ __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */
+ __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
+ __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */
+ __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
+ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
+ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
+ __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
+ __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
+ __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
+ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+ __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
+ __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
+ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
+ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
+ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK 0x7u
+#define FTM_SC_PS_SHIFT 0
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK 0x18u
+#define FTM_SC_CLKS_SHIFT 3
+#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK 0x20u
+#define FTM_SC_CPWMS_SHIFT 5
+#define FTM_SC_TOIE_MASK 0x40u
+#define FTM_SC_TOIE_SHIFT 6
+#define FTM_SC_TOF_MASK 0x80u
+#define FTM_SC_TOF_SHIFT 7
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK 0xFFFFu
+#define FTM_CNT_COUNT_SHIFT 0
+#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK 0xFFFFu
+#define FTM_MOD_MOD_SHIFT 0
+#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK 0x1u
+#define FTM_CnSC_DMA_SHIFT 0
+#define FTM_CnSC_ELSA_MASK 0x4u
+#define FTM_CnSC_ELSA_SHIFT 2
+#define FTM_CnSC_ELSB_MASK 0x8u
+#define FTM_CnSC_ELSB_SHIFT 3
+#define FTM_CnSC_MSA_MASK 0x10u
+#define FTM_CnSC_MSA_SHIFT 4
+#define FTM_CnSC_MSB_MASK 0x20u
+#define FTM_CnSC_MSB_SHIFT 5
+#define FTM_CnSC_CHIE_MASK 0x40u
+#define FTM_CnSC_CHIE_SHIFT 6
+#define FTM_CnSC_CHF_MASK 0x80u
+#define FTM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK 0xFFFFu
+#define FTM_CnV_VAL_SHIFT 0
+#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK 0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT 0
+#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK 0x1u
+#define FTM_STATUS_CH0F_SHIFT 0
+#define FTM_STATUS_CH1F_MASK 0x2u
+#define FTM_STATUS_CH1F_SHIFT 1
+#define FTM_STATUS_CH2F_MASK 0x4u
+#define FTM_STATUS_CH2F_SHIFT 2
+#define FTM_STATUS_CH3F_MASK 0x8u
+#define FTM_STATUS_CH3F_SHIFT 3
+#define FTM_STATUS_CH4F_MASK 0x10u
+#define FTM_STATUS_CH4F_SHIFT 4
+#define FTM_STATUS_CH5F_MASK 0x20u
+#define FTM_STATUS_CH5F_SHIFT 5
+#define FTM_STATUS_CH6F_MASK 0x40u
+#define FTM_STATUS_CH6F_SHIFT 6
+#define FTM_STATUS_CH7F_MASK 0x80u
+#define FTM_STATUS_CH7F_SHIFT 7
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK 0x1u
+#define FTM_MODE_FTMEN_SHIFT 0
+#define FTM_MODE_INIT_MASK 0x2u
+#define FTM_MODE_INIT_SHIFT 1
+#define FTM_MODE_WPDIS_MASK 0x4u
+#define FTM_MODE_WPDIS_SHIFT 2
+#define FTM_MODE_PWMSYNC_MASK 0x8u
+#define FTM_MODE_PWMSYNC_SHIFT 3
+#define FTM_MODE_CAPTEST_MASK 0x10u
+#define FTM_MODE_CAPTEST_SHIFT 4
+#define FTM_MODE_FAULTM_MASK 0x60u
+#define FTM_MODE_FAULTM_SHIFT 5
+#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK 0x80u
+#define FTM_MODE_FAULTIE_SHIFT 7
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK 0x1u
+#define FTM_SYNC_CNTMIN_SHIFT 0
+#define FTM_SYNC_CNTMAX_MASK 0x2u
+#define FTM_SYNC_CNTMAX_SHIFT 1
+#define FTM_SYNC_REINIT_MASK 0x4u
+#define FTM_SYNC_REINIT_SHIFT 2
+#define FTM_SYNC_SYNCHOM_MASK 0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT 3
+#define FTM_SYNC_TRIG0_MASK 0x10u
+#define FTM_SYNC_TRIG0_SHIFT 4
+#define FTM_SYNC_TRIG1_MASK 0x20u
+#define FTM_SYNC_TRIG1_SHIFT 5
+#define FTM_SYNC_TRIG2_MASK 0x40u
+#define FTM_SYNC_TRIG2_SHIFT 6
+#define FTM_SYNC_SWSYNC_MASK 0x80u
+#define FTM_SYNC_SWSYNC_SHIFT 7
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK 0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT 0
+#define FTM_OUTINIT_CH1OI_MASK 0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT 1
+#define FTM_OUTINIT_CH2OI_MASK 0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT 2
+#define FTM_OUTINIT_CH3OI_MASK 0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT 3
+#define FTM_OUTINIT_CH4OI_MASK 0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT 4
+#define FTM_OUTINIT_CH5OI_MASK 0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT 5
+#define FTM_OUTINIT_CH6OI_MASK 0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT 6
+#define FTM_OUTINIT_CH7OI_MASK 0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT 7
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK 0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT 0
+#define FTM_OUTMASK_CH1OM_MASK 0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT 1
+#define FTM_OUTMASK_CH2OM_MASK 0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT 2
+#define FTM_OUTMASK_CH3OM_MASK 0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT 3
+#define FTM_OUTMASK_CH4OM_MASK 0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT 4
+#define FTM_OUTMASK_CH5OM_MASK 0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT 5
+#define FTM_OUTMASK_CH6OM_MASK 0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT 6
+#define FTM_OUTMASK_CH7OM_MASK 0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT 7
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK 0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT 0
+#define FTM_COMBINE_COMP0_MASK 0x2u
+#define FTM_COMBINE_COMP0_SHIFT 1
+#define FTM_COMBINE_DECAPEN0_MASK 0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT 2
+#define FTM_COMBINE_DECAP0_MASK 0x8u
+#define FTM_COMBINE_DECAP0_SHIFT 3
+#define FTM_COMBINE_DTEN0_MASK 0x10u
+#define FTM_COMBINE_DTEN0_SHIFT 4
+#define FTM_COMBINE_SYNCEN0_MASK 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT 5
+#define FTM_COMBINE_FAULTEN0_MASK 0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT 6
+#define FTM_COMBINE_COMBINE1_MASK 0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT 8
+#define FTM_COMBINE_COMP1_MASK 0x200u
+#define FTM_COMBINE_COMP1_SHIFT 9
+#define FTM_COMBINE_DECAPEN1_MASK 0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT 10
+#define FTM_COMBINE_DECAP1_MASK 0x800u
+#define FTM_COMBINE_DECAP1_SHIFT 11
+#define FTM_COMBINE_DTEN1_MASK 0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT 12
+#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT 13
+#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT 14
+#define FTM_COMBINE_COMBINE2_MASK 0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT 16
+#define FTM_COMBINE_COMP2_MASK 0x20000u
+#define FTM_COMBINE_COMP2_SHIFT 17
+#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT 18
+#define FTM_COMBINE_DECAP2_MASK 0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT 19
+#define FTM_COMBINE_DTEN2_MASK 0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT 20
+#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT 21
+#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT 22
+#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT 24
+#define FTM_COMBINE_COMP3_MASK 0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT 25
+#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT 26
+#define FTM_COMBINE_DECAP3_MASK 0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT 27
+#define FTM_COMBINE_DTEN3_MASK 0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT 28
+#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT 29
+#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT 30
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT 0
+#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK 0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT 6
+#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
+#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
+#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
+#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
+#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
+#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
+#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
+#define FTM_EXTTRIG_TRIGF_MASK 0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT 7
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK 0x1u
+#define FTM_POL_POL0_SHIFT 0
+#define FTM_POL_POL1_MASK 0x2u
+#define FTM_POL_POL1_SHIFT 1
+#define FTM_POL_POL2_MASK 0x4u
+#define FTM_POL_POL2_SHIFT 2
+#define FTM_POL_POL3_MASK 0x8u
+#define FTM_POL_POL3_SHIFT 3
+#define FTM_POL_POL4_MASK 0x10u
+#define FTM_POL_POL4_SHIFT 4
+#define FTM_POL_POL5_MASK 0x20u
+#define FTM_POL_POL5_SHIFT 5
+#define FTM_POL_POL6_MASK 0x40u
+#define FTM_POL_POL6_SHIFT 6
+#define FTM_POL_POL7_MASK 0x80u
+#define FTM_POL_POL7_SHIFT 7
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK 0x1u
+#define FTM_FMS_FAULTF0_SHIFT 0
+#define FTM_FMS_FAULTF1_MASK 0x2u
+#define FTM_FMS_FAULTF1_SHIFT 1
+#define FTM_FMS_FAULTF2_MASK 0x4u
+#define FTM_FMS_FAULTF2_SHIFT 2
+#define FTM_FMS_FAULTF3_MASK 0x8u
+#define FTM_FMS_FAULTF3_SHIFT 3
+#define FTM_FMS_FAULTIN_MASK 0x20u
+#define FTM_FMS_FAULTIN_SHIFT 5
+#define FTM_FMS_WPEN_MASK 0x40u
+#define FTM_FMS_WPEN_SHIFT 6
+#define FTM_FMS_FAULTF_MASK 0x80u
+#define FTM_FMS_FAULTF_SHIFT 7
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK 0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT 0
+#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK 0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT 4
+#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK 0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT 8
+#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK 0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT 12
+#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
+#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
+#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
+#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
+#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
+#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
+#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
+#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
+#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT 8
+#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK 0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT 0
+#define FTM_QDCTRL_TOFDIR_MASK 0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT 1
+#define FTM_QDCTRL_QUADIR_MASK 0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT 2
+#define FTM_QDCTRL_QUADMODE_MASK 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT 3
+#define FTM_QDCTRL_PHBPOL_MASK 0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT 4
+#define FTM_QDCTRL_PHAPOL_MASK 0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT 5
+#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
+#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK 0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT 0
+#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK 0xC0u
+#define FTM_CONF_BDMMODE_SHIFT 6
+#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK 0x200u
+#define FTM_CONF_GTBEEN_SHIFT 9
+#define FTM_CONF_GTBEOUT_MASK 0x400u
+#define FTM_CONF_GTBEOUT_SHIFT 10
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK 0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT 0
+#define FTM_FLTPOL_FLT1POL_MASK 0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT 1
+#define FTM_FLTPOL_FLT2POL_MASK 0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT 2
+#define FTM_FLTPOL_FLT3POL_MASK 0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT 3
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
+#define FTM_SYNCONF_CNTINC_MASK 0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT 2
+#define FTM_SYNCONF_INVC_MASK 0x10u
+#define FTM_SYNCONF_INVC_SHIFT 4
+#define FTM_SYNCONF_SWOC_MASK 0x20u
+#define FTM_SYNCONF_SWOC_SHIFT 5
+#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT 7
+#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
+#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT 9
+#define FTM_SYNCONF_SWOM_MASK 0x400u
+#define FTM_SYNCONF_SWOM_SHIFT 10
+#define FTM_SYNCONF_SWINVC_MASK 0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT 11
+#define FTM_SYNCONF_SWSOC_MASK 0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT 12
+#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
+#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT 17
+#define FTM_SYNCONF_HWOM_MASK 0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT 18
+#define FTM_SYNCONF_HWINVC_MASK 0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT 19
+#define FTM_SYNCONF_HWSOC_MASK 0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT 20
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK 0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT 0
+#define FTM_INVCTRL_INV1EN_MASK 0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT 1
+#define FTM_INVCTRL_INV2EN_MASK 0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT 2
+#define FTM_INVCTRL_INV3EN_MASK 0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT 3
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK 0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT 0
+#define FTM_SWOCTRL_CH1OC_MASK 0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT 1
+#define FTM_SWOCTRL_CH2OC_MASK 0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT 2
+#define FTM_SWOCTRL_CH3OC_MASK 0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT 3
+#define FTM_SWOCTRL_CH4OC_MASK 0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT 4
+#define FTM_SWOCTRL_CH5OC_MASK 0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT 5
+#define FTM_SWOCTRL_CH6OC_MASK 0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT 6
+#define FTM_SWOCTRL_CH7OC_MASK 0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT 7
+#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT 8
+#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT 9
+#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT 10
+#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT 11
+#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT 12
+#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT 13
+#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT 14
+#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT 15
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT 0
+#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT 1
+#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT 2
+#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT 3
+#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT 4
+#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT 5
+#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT 6
+#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT 7
+#define FTM_PWMLOAD_LDOK_MASK 0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT 9
+
+/**
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0 ((FTM_Type *)FTM0_BASE)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1 ((FTM_Type *)FTM1_BASE)
+
+/**
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+
+/**
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0x1Fu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+
+/**
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[24];
+ __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_2[24];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_4[8];
+ __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_5[24];
+ __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_6[24];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+ __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK 0x1u
+#define I2S_TCSR_FRDE_SHIFT 0
+#define I2S_TCSR_FWDE_MASK 0x2u
+#define I2S_TCSR_FWDE_SHIFT 1
+#define I2S_TCSR_FRIE_MASK 0x100u
+#define I2S_TCSR_FRIE_SHIFT 8
+#define I2S_TCSR_FWIE_MASK 0x200u
+#define I2S_TCSR_FWIE_SHIFT 9
+#define I2S_TCSR_FEIE_MASK 0x400u
+#define I2S_TCSR_FEIE_SHIFT 10
+#define I2S_TCSR_SEIE_MASK 0x800u
+#define I2S_TCSR_SEIE_SHIFT 11
+#define I2S_TCSR_WSIE_MASK 0x1000u
+#define I2S_TCSR_WSIE_SHIFT 12
+#define I2S_TCSR_FRF_MASK 0x10000u
+#define I2S_TCSR_FRF_SHIFT 16
+#define I2S_TCSR_FWF_MASK 0x20000u
+#define I2S_TCSR_FWF_SHIFT 17
+#define I2S_TCSR_FEF_MASK 0x40000u
+#define I2S_TCSR_FEF_SHIFT 18
+#define I2S_TCSR_SEF_MASK 0x80000u
+#define I2S_TCSR_SEF_SHIFT 19
+#define I2S_TCSR_WSF_MASK 0x100000u
+#define I2S_TCSR_WSF_SHIFT 20
+#define I2S_TCSR_SR_MASK 0x1000000u
+#define I2S_TCSR_SR_SHIFT 24
+#define I2S_TCSR_FR_MASK 0x2000000u
+#define I2S_TCSR_FR_SHIFT 25
+#define I2S_TCSR_BCE_MASK 0x10000000u
+#define I2S_TCSR_BCE_SHIFT 28
+#define I2S_TCSR_DBGE_MASK 0x20000000u
+#define I2S_TCSR_DBGE_SHIFT 29
+#define I2S_TCSR_STOPE_MASK 0x40000000u
+#define I2S_TCSR_STOPE_SHIFT 30
+#define I2S_TCSR_TE_MASK 0x80000000u
+#define I2S_TCSR_TE_SHIFT 31
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK 0x7u
+#define I2S_TCR1_TFW_SHIFT 0
+#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK 0xFFu
+#define I2S_TCR2_DIV_SHIFT 0
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK 0x1000000u
+#define I2S_TCR2_BCD_SHIFT 24
+#define I2S_TCR2_BCP_MASK 0x2000000u
+#define I2S_TCR2_BCP_SHIFT 25
+#define I2S_TCR2_MSEL_MASK 0xC000000u
+#define I2S_TCR2_MSEL_SHIFT 26
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK 0x10000000u
+#define I2S_TCR2_BCI_SHIFT 28
+#define I2S_TCR2_BCS_MASK 0x20000000u
+#define I2S_TCR2_BCS_SHIFT 29
+#define I2S_TCR2_SYNC_MASK 0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT 30
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK 0x1Fu
+#define I2S_TCR3_WDFL_SHIFT 0
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK 0x30000u
+#define I2S_TCR3_TCE_SHIFT 16
+#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK 0x1u
+#define I2S_TCR4_FSD_SHIFT 0
+#define I2S_TCR4_FSP_MASK 0x2u
+#define I2S_TCR4_FSP_SHIFT 1
+#define I2S_TCR4_FSE_MASK 0x8u
+#define I2S_TCR4_FSE_SHIFT 3
+#define I2S_TCR4_MF_MASK 0x10u
+#define I2S_TCR4_MF_SHIFT 4
+#define I2S_TCR4_SYWD_MASK 0x1F00u
+#define I2S_TCR4_SYWD_SHIFT 8
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK 0x1F0000u
+#define I2S_TCR4_FRSZ_SHIFT 16
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK 0x1F00u
+#define I2S_TCR5_FBT_SHIFT 8
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK 0x1F0000u
+#define I2S_TCR5_W0W_SHIFT 16
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK 0x1F000000u
+#define I2S_TCR5_WNW_SHIFT 24
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT 0
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK 0xFu
+#define I2S_TFR_RFP_SHIFT 0
+#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK 0xF0000u
+#define I2S_TFR_WFP_SHIFT 16
+#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK 0xFFFFFFFFu
+#define I2S_TMR_TWM_SHIFT 0
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK 0x1u
+#define I2S_RCSR_FRDE_SHIFT 0
+#define I2S_RCSR_FWDE_MASK 0x2u
+#define I2S_RCSR_FWDE_SHIFT 1
+#define I2S_RCSR_FRIE_MASK 0x100u
+#define I2S_RCSR_FRIE_SHIFT 8
+#define I2S_RCSR_FWIE_MASK 0x200u
+#define I2S_RCSR_FWIE_SHIFT 9
+#define I2S_RCSR_FEIE_MASK 0x400u
+#define I2S_RCSR_FEIE_SHIFT 10
+#define I2S_RCSR_SEIE_MASK 0x800u
+#define I2S_RCSR_SEIE_SHIFT 11
+#define I2S_RCSR_WSIE_MASK 0x1000u
+#define I2S_RCSR_WSIE_SHIFT 12
+#define I2S_RCSR_FRF_MASK 0x10000u
+#define I2S_RCSR_FRF_SHIFT 16
+#define I2S_RCSR_FWF_MASK 0x20000u
+#define I2S_RCSR_FWF_SHIFT 17
+#define I2S_RCSR_FEF_MASK 0x40000u
+#define I2S_RCSR_FEF_SHIFT 18
+#define I2S_RCSR_SEF_MASK 0x80000u
+#define I2S_RCSR_SEF_SHIFT 19
+#define I2S_RCSR_WSF_MASK 0x100000u
+#define I2S_RCSR_WSF_SHIFT 20
+#define I2S_RCSR_SR_MASK 0x1000000u
+#define I2S_RCSR_SR_SHIFT 24
+#define I2S_RCSR_FR_MASK 0x2000000u
+#define I2S_RCSR_FR_SHIFT 25
+#define I2S_RCSR_BCE_MASK 0x10000000u
+#define I2S_RCSR_BCE_SHIFT 28
+#define I2S_RCSR_DBGE_MASK 0x20000000u
+#define I2S_RCSR_DBGE_SHIFT 29
+#define I2S_RCSR_STOPE_MASK 0x40000000u
+#define I2S_RCSR_STOPE_SHIFT 30
+#define I2S_RCSR_RE_MASK 0x80000000u
+#define I2S_RCSR_RE_SHIFT 31
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK 0x7u
+#define I2S_RCR1_RFW_SHIFT 0
+#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK 0xFFu
+#define I2S_RCR2_DIV_SHIFT 0
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK 0x1000000u
+#define I2S_RCR2_BCD_SHIFT 24
+#define I2S_RCR2_BCP_MASK 0x2000000u
+#define I2S_RCR2_BCP_SHIFT 25
+#define I2S_RCR2_MSEL_MASK 0xC000000u
+#define I2S_RCR2_MSEL_SHIFT 26
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK 0x10000000u
+#define I2S_RCR2_BCI_SHIFT 28
+#define I2S_RCR2_BCS_MASK 0x20000000u
+#define I2S_RCR2_BCS_SHIFT 29
+#define I2S_RCR2_SYNC_MASK 0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT 30
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK 0x1Fu
+#define I2S_RCR3_WDFL_SHIFT 0
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK 0x30000u
+#define I2S_RCR3_RCE_SHIFT 16
+#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK 0x1u
+#define I2S_RCR4_FSD_SHIFT 0
+#define I2S_RCR4_FSP_MASK 0x2u
+#define I2S_RCR4_FSP_SHIFT 1
+#define I2S_RCR4_FSE_MASK 0x8u
+#define I2S_RCR4_FSE_SHIFT 3
+#define I2S_RCR4_MF_MASK 0x10u
+#define I2S_RCR4_MF_SHIFT 4
+#define I2S_RCR4_SYWD_MASK 0x1F00u
+#define I2S_RCR4_SYWD_SHIFT 8
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK 0x1F0000u
+#define I2S_RCR4_FRSZ_SHIFT 16
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK 0x1F00u
+#define I2S_RCR5_FBT_SHIFT 8
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK 0x1F0000u
+#define I2S_RCR5_W0W_SHIFT 16
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK 0x1F000000u
+#define I2S_RCR5_WNW_SHIFT 24
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT 0
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK 0xFu
+#define I2S_RFR_RFP_SHIFT 0
+#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK 0xF0000u
+#define I2S_RFR_WFP_SHIFT 16
+#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK 0xFFFFFFFFu
+#define I2S_RMR_RWM_SHIFT 0
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK 0x3000000u
+#define I2S_MCR_MICS_SHIFT 24
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK 0x40000000u
+#define I2S_MCR_MOE_SHIFT 30
+#define I2S_MCR_DUF_MASK 0x80000000u
+#define I2S_MCR_DUF_SHIFT 31
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK 0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT 0
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK 0xFF000u
+#define I2S_MDR_FRACT_SHIFT 12
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+
+/**
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */
+ __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+/* RST Bit Fields */
+#define LLWU_RST_RSTFILT_MASK 0x1u
+#define LLWU_RST_RSTFILT_SHIFT 0
+#define LLWU_RST_LLRSTE_MASK 0x2u
+#define LLWU_RST_LLRSTE_SHIFT 1
+
+/**
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+
+/**
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/**
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+
+/**
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS0_MASK 0x4u
+#define MCG_C2_EREFS0_SHIFT 2
+#define MCG_C2_HGO0_MASK 0x8u
+#define MCG_C2_HGO0_SHIFT 3
+#define MCG_C2_RANGE0_MASK 0x30u
+#define MCG_C2_RANGE0_SHIFT 4
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK 0x1Fu
+#define MCG_C5_PRDIV0_SHIFT 0
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK 0x20u
+#define MCG_C5_PLLSTEN0_SHIFT 5
+#define MCG_C5_PLLCLKEN0_MASK 0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT 6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK 0x1Fu
+#define MCG_C6_VDIV0_SHIFT 0
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK 0x20u
+#define MCG_C6_CME0_SHIFT 5
+#define MCG_C6_PLLS_MASK 0x40u
+#define MCG_C6_PLLS_SHIFT 6
+#define MCG_C6_LOLIE0_MASK 0x80u
+#define MCG_C6_LOLIE0_SHIFT 7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+#define MCG_S_PLLST_MASK 0x20u
+#define MCG_S_PLLST_SHIFT 5
+#define MCG_S_LOCK0_MASK 0x40u
+#define MCG_S_LOCK0_SHIFT 6
+#define MCG_S_LOLS0_MASK 0x80u
+#define MCG_S_LOLS0_SHIFT 7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK 0x1u
+#define MCG_C7_OSCSEL_SHIFT 0
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK 0x1u
+#define MCG_C8_LOCS1_SHIFT 0
+#define MCG_C8_CME1_MASK 0x20u
+#define MCG_C8_CME1_SHIFT 5
+#define MCG_C8_LOLRE_MASK 0x40u
+#define MCG_C8_LOLRE_SHIFT 6
+#define MCG_C8_LOCRE1_MASK 0x80u
+#define MCG_C8_LOCRE1_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+
+/**
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+ __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
+ __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK 0x1u
+#define NV_FOPT_LPBOOT_SHIFT 0
+#define NV_FOPT_EZPORT_DIS_MASK 0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT 1
+/* FEPROT Bit Fields */
+#define NV_FEPROT_EPROT_MASK 0xFFu
+#define NV_FEPROT_EPROT_SHIFT 0
+#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define NV_FDPROT_DPROT_MASK 0xFFu
+#define NV_FDPROT_DPROT_SHIFT 0
+#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+
+/**
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFL_FlashConfig base address */
+#define FTFL_FlashConfig_BASE (0x400u)
+/** Peripheral FTFL_FlashConfig base pointer */
+#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
+
+/**
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+
+/**
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
+ __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
+ __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
+ __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
+ struct { /* offset: 0x10, array step: 0x10 */
+ __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */
+ __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */
+ __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */
+ } CH[1];
+ uint8_t RESERVED_0[368];
+ __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
+ __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
+} PDB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PDB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK 0x1u
+#define PDB_SC_LDOK_SHIFT 0
+#define PDB_SC_CONT_MASK 0x2u
+#define PDB_SC_CONT_SHIFT 1
+#define PDB_SC_MULT_MASK 0xCu
+#define PDB_SC_MULT_SHIFT 2
+#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK 0x20u
+#define PDB_SC_PDBIE_SHIFT 5
+#define PDB_SC_PDBIF_MASK 0x40u
+#define PDB_SC_PDBIF_SHIFT 6
+#define PDB_SC_PDBEN_MASK 0x80u
+#define PDB_SC_PDBEN_SHIFT 7
+#define PDB_SC_TRGSEL_MASK 0xF00u
+#define PDB_SC_TRGSEL_SHIFT 8
+#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK 0x7000u
+#define PDB_SC_PRESCALER_SHIFT 12
+#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK 0x8000u
+#define PDB_SC_DMAEN_SHIFT 15
+#define PDB_SC_SWTRIG_MASK 0x10000u
+#define PDB_SC_SWTRIG_SHIFT 16
+#define PDB_SC_PDBEIE_MASK 0x20000u
+#define PDB_SC_PDBEIE_SHIFT 17
+#define PDB_SC_LDMOD_MASK 0xC0000u
+#define PDB_SC_LDMOD_SHIFT 18
+#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK 0xFFFFu
+#define PDB_MOD_MOD_SHIFT 0
+#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK 0xFFFFu
+#define PDB_CNT_CNT_SHIFT 0
+#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK 0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT 0
+#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK 0xFFu
+#define PDB_C1_EN_SHIFT 0
+#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK 0xFF00u
+#define PDB_C1_TOS_SHIFT 8
+#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK 0xFF0000u
+#define PDB_C1_BB_SHIFT 16
+#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK 0xFFu
+#define PDB_S_ERR_SHIFT 0
+#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK 0xFF0000u
+#define PDB_S_CF_SHIFT 16
+#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK 0xFFFFu
+#define PDB_DLY_DLY_SHIFT 0
+#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK 0xFFu
+#define PDB_POEN_POEN_SHIFT 0
+#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK 0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT 0
+#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT 16
+#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/**
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0 ((PDB_Type *)PDB0_BASE)
+
+/**
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[252];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[4];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/**
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+
+/**
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+
+/**
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+
+/**
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
+ __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
+ __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_ODE_MASK 0x20u
+#define PORT_PCR_ODE_SHIFT 5
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK 0x8000u
+#define PORT_PCR_LK_SHIFT 15
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT 0
+#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK 0x1u
+#define PORT_DFCR_CS_SHIFT 0
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK 0x1Fu
+#define PORT_DFWR_FILT_SHIFT 0
+#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/**
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+
+/**
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __I uint8_t MR; /**< Mode Register, offset: 0x7 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_LOL_MASK 0x8u
+#define RCM_SRS0_LOL_SHIFT 3
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK 0x1u
+#define RCM_SRS1_JTAG_SHIFT 0
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_EZPT_MASK 0x10u
+#define RCM_SRS1_EZPT_SHIFT 4
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK 0x2u
+#define RCM_MR_EZP_MS_SHIFT 1
+
+/**
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+
+/**
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK 0xFFu
+#define RFSYS_REG_LL_SHIFT 0
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK 0xFF00u
+#define RFSYS_REG_LH_SHIFT 8
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK 0xFF0000u
+#define RFSYS_REG_HL_SHIFT 16
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK 0xFF000000u
+#define RFSYS_REG_HH_SHIFT 24
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/**
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
+
+/**
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK 0xFFu
+#define RFVBAT_REG_LL_SHIFT 0
+#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK 0xFF00u
+#define RFVBAT_REG_LH_SHIFT 8
+#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK 0xFF0000u
+#define RFVBAT_REG_HL_SHIFT 16
+#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK 0xFF000000u
+#define RFVBAT_REG_HH_SHIFT 24
+#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/**
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
+
+/**
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+ uint8_t RESERVED_0[2016];
+ __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
+ __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK 0x1u
+#define RTC_WAR_TSRW_SHIFT 0
+#define RTC_WAR_TPRW_MASK 0x2u
+#define RTC_WAR_TPRW_SHIFT 1
+#define RTC_WAR_TARW_MASK 0x4u
+#define RTC_WAR_TARW_SHIFT 2
+#define RTC_WAR_TCRW_MASK 0x8u
+#define RTC_WAR_TCRW_SHIFT 3
+#define RTC_WAR_CRW_MASK 0x10u
+#define RTC_WAR_CRW_SHIFT 4
+#define RTC_WAR_SRW_MASK 0x20u
+#define RTC_WAR_SRW_SHIFT 5
+#define RTC_WAR_LRW_MASK 0x40u
+#define RTC_WAR_LRW_SHIFT 6
+#define RTC_WAR_IERW_MASK 0x80u
+#define RTC_WAR_IERW_SHIFT 7
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK 0x1u
+#define RTC_RAR_TSRR_SHIFT 0
+#define RTC_RAR_TPRR_MASK 0x2u
+#define RTC_RAR_TPRR_SHIFT 1
+#define RTC_RAR_TARR_MASK 0x4u
+#define RTC_RAR_TARR_SHIFT 2
+#define RTC_RAR_TCRR_MASK 0x8u
+#define RTC_RAR_TCRR_SHIFT 3
+#define RTC_RAR_CRR_MASK 0x10u
+#define RTC_RAR_CRR_SHIFT 4
+#define RTC_RAR_SRR_MASK 0x20u
+#define RTC_RAR_SRR_SHIFT 5
+#define RTC_RAR_LRR_MASK 0x40u
+#define RTC_RAR_LRR_SHIFT 6
+#define RTC_RAR_IERR_MASK 0x80u
+#define RTC_RAR_IERR_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+
+/**
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT 12
+#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK 0x800u
+#define SIM_SOPT2_PTD7PAD_SHIFT 11
+#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
+#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT 0
+#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT 1
+#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT 4
+#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x1u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK 0x10u
+#define SIM_SOPT5_UART1TXSRC_SHIFT 4
+#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT 6
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK 0x70u
+#define SIM_SDID_FAMID_SHIFT 4
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK 0x2u
+#define SIM_SCGC4_EWM_SHIFT 1
+#define SIM_SCGC4_CMT_MASK 0x4u
+#define SIM_SCGC4_CMT_SHIFT 2
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_UART1_MASK 0x800u
+#define SIM_SCGC4_UART1_SHIFT 11
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_USBOTG_MASK 0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT 18
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_VREF_MASK 0x100000u
+#define SIM_SCGC4_VREF_SHIFT 20
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTIMER_MASK 0x1u
+#define SIM_SCGC5_LPTIMER_SHIFT 0
+#define SIM_SCGC5_TSI_MASK 0x20u
+#define SIM_SCGC5_TSI_SHIFT 5
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTFL_MASK 0x1u
+#define SIM_SCGC6_FTFL_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_SPI0_MASK 0x1000u
+#define SIM_SCGC6_SPI0_SHIFT 12
+#define SIM_SCGC6_I2S_MASK 0x8000u
+#define SIM_SCGC6_I2S_SHIFT 15
+#define SIM_SCGC6_CRC_MASK 0x40000u
+#define SIM_SCGC6_CRC_SHIFT 18
+#define SIM_SCGC6_USBDCD_MASK 0x200000u
+#define SIM_SCGC6_USBDCD_SHIFT 21
+#define SIM_SCGC6_PDB_MASK 0x400000u
+#define SIM_SCGC6_PDB_SHIFT 22
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_FTM0_MASK 0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT 24
+#define SIM_SCGC6_FTM1_MASK 0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT 25
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK 0x2u
+#define SIM_SCGC7_DMA_SHIFT 1
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
+#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT 0
+#define SIM_CLKDIV2_USBDIV_MASK 0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT 1
+#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_DEPART_MASK 0xF00u
+#define SIM_FCFG1_DEPART_SHIFT 8
+#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK 0xF0000u
+#define SIM_FCFG1_EESIZE_SHIFT 16
+#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
+#define SIM_FCFG1_NVMSIZE_SHIFT 28
+#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT 16
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK 0x800000u
+#define SIM_FCFG2_PFLSH_SHIFT 23
+#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT 24
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT 0
+#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/**
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+
+/**
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */
+ __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK 0x80u
+#define SMC_PMCTRL_LPWUI_SHIFT 7
+/* VLLSCTRL Bit Fields */
+#define SMC_VLLSCTRL_VLLSM_MASK 0x7u
+#define SMC_VLLSCTRL_VLLSM_SHIFT 0
+#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK 0x20u
+#define SMC_VLLSCTRL_PORPO_SHIFT 5
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/**
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+
+/**
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
+ union { /* offset: 0xC */
+ __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+ __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+ };
+ uint8_t RESERVED_1[24];
+ __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
+ __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+ union { /* offset: 0x34 */
+ __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+ __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+ };
+ __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
+ __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
+ __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
+ __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
+ __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
+ uint8_t RESERVED_2[48];
+ __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
+ __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
+ __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
+ __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK 0x1u
+#define SPI_MCR_HALT_SHIFT 0
+#define SPI_MCR_SMPL_PT_MASK 0x300u
+#define SPI_MCR_SMPL_PT_SHIFT 8
+#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK 0x400u
+#define SPI_MCR_CLR_RXF_SHIFT 10
+#define SPI_MCR_CLR_TXF_MASK 0x800u
+#define SPI_MCR_CLR_TXF_SHIFT 11
+#define SPI_MCR_DIS_RXF_MASK 0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT 12
+#define SPI_MCR_DIS_TXF_MASK 0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT 13
+#define SPI_MCR_MDIS_MASK 0x4000u
+#define SPI_MCR_MDIS_SHIFT 14
+#define SPI_MCR_DOZE_MASK 0x8000u
+#define SPI_MCR_DOZE_SHIFT 15
+#define SPI_MCR_PCSIS_MASK 0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT 16
+#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK 0x1000000u
+#define SPI_MCR_ROOE_SHIFT 24
+#define SPI_MCR_PCSSE_MASK 0x2000000u
+#define SPI_MCR_PCSSE_SHIFT 25
+#define SPI_MCR_MTFE_MASK 0x4000000u
+#define SPI_MCR_MTFE_SHIFT 26
+#define SPI_MCR_FRZ_MASK 0x8000000u
+#define SPI_MCR_FRZ_SHIFT 27
+#define SPI_MCR_DCONF_MASK 0x30000000u
+#define SPI_MCR_DCONF_SHIFT 28
+#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT 30
+#define SPI_MCR_MSTR_MASK 0x80000000u
+#define SPI_MCR_MSTR_SHIFT 31
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT 16
+#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK 0xFu
+#define SPI_CTAR_BR_SHIFT 0
+#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK 0xF0u
+#define SPI_CTAR_DT_SHIFT 4
+#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK 0xF00u
+#define SPI_CTAR_ASC_SHIFT 8
+#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK 0xF000u
+#define SPI_CTAR_CSSCK_SHIFT 12
+#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK 0x30000u
+#define SPI_CTAR_PBR_SHIFT 16
+#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK 0xC0000u
+#define SPI_CTAR_PDT_SHIFT 18
+#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK 0x300000u
+#define SPI_CTAR_PASC_SHIFT 20
+#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK 0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT 22
+#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK 0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT 24
+#define SPI_CTAR_CPHA_MASK 0x2000000u
+#define SPI_CTAR_CPHA_SHIFT 25
+#define SPI_CTAR_CPOL_MASK 0x4000000u
+#define SPI_CTAR_CPOL_SHIFT 26
+#define SPI_CTAR_FMSZ_MASK 0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT 27
+#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK 0x80000000u
+#define SPI_CTAR_DBR_SHIFT 31
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
+#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
+#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
+#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK 0xFu
+#define SPI_SR_POPNXTPTR_SHIFT 0
+#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK 0xF0u
+#define SPI_SR_RXCTR_SHIFT 4
+#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK 0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT 8
+#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK 0xF000u
+#define SPI_SR_TXCTR_SHIFT 12
+#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK 0x20000u
+#define SPI_SR_RFDF_SHIFT 17
+#define SPI_SR_RFOF_MASK 0x80000u
+#define SPI_SR_RFOF_SHIFT 19
+#define SPI_SR_TFFF_MASK 0x2000000u
+#define SPI_SR_TFFF_SHIFT 25
+#define SPI_SR_TFUF_MASK 0x8000000u
+#define SPI_SR_TFUF_SHIFT 27
+#define SPI_SR_EOQF_MASK 0x10000000u
+#define SPI_SR_EOQF_SHIFT 28
+#define SPI_SR_TXRXS_MASK 0x40000000u
+#define SPI_SR_TXRXS_SHIFT 30
+#define SPI_SR_TCF_MASK 0x80000000u
+#define SPI_SR_TCF_SHIFT 31
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT 16
+#define SPI_RSER_RFDF_RE_MASK 0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT 17
+#define SPI_RSER_RFOF_RE_MASK 0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT 19
+#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT 24
+#define SPI_RSER_TFFF_RE_MASK 0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT 25
+#define SPI_RSER_TFUF_RE_MASK 0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT 27
+#define SPI_RSER_EOQF_RE_MASK 0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT 28
+#define SPI_RSER_TCF_RE_MASK 0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT 31
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT 0
+#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK 0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT 16
+#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK 0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT 26
+#define SPI_PUSHR_EOQ_MASK 0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT 27
+#define SPI_PUSHR_CTAS_MASK 0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT 28
+#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK 0x80000000u
+#define SPI_PUSHR_CONT_SHIFT 31
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
+#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT 0
+#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT 0
+#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT 0
+#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT 0
+#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT 0
+#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT 0
+#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT 0
+#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT 0
+#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT 0
+#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/**
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+
+/**
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
+ __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */
+ __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */
+ __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */
+ uint8_t RESERVED_0[240];
+ __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
+ __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
+ __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
+ __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
+ __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
+ __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
+ __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
+ __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
+ __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/* GENCS Bit Fields */
+#define TSI_GENCS_STPE_MASK 0x1u
+#define TSI_GENCS_STPE_SHIFT 0
+#define TSI_GENCS_STM_MASK 0x2u
+#define TSI_GENCS_STM_SHIFT 1
+#define TSI_GENCS_ESOR_MASK 0x10u
+#define TSI_GENCS_ESOR_SHIFT 4
+#define TSI_GENCS_ERIE_MASK 0x20u
+#define TSI_GENCS_ERIE_SHIFT 5
+#define TSI_GENCS_TSIIE_MASK 0x40u
+#define TSI_GENCS_TSIIE_SHIFT 6
+#define TSI_GENCS_TSIEN_MASK 0x80u
+#define TSI_GENCS_TSIEN_SHIFT 7
+#define TSI_GENCS_SWTS_MASK 0x100u
+#define TSI_GENCS_SWTS_SHIFT 8
+#define TSI_GENCS_SCNIP_MASK 0x200u
+#define TSI_GENCS_SCNIP_SHIFT 9
+#define TSI_GENCS_OVRF_MASK 0x1000u
+#define TSI_GENCS_OVRF_SHIFT 12
+#define TSI_GENCS_EXTERF_MASK 0x2000u
+#define TSI_GENCS_EXTERF_SHIFT 13
+#define TSI_GENCS_OUTRGF_MASK 0x4000u
+#define TSI_GENCS_OUTRGF_SHIFT 14
+#define TSI_GENCS_EOSF_MASK 0x8000u
+#define TSI_GENCS_EOSF_SHIFT 15
+#define TSI_GENCS_PS_MASK 0x70000u
+#define TSI_GENCS_PS_SHIFT 16
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
+#define TSI_GENCS_NSCN_MASK 0xF80000u
+#define TSI_GENCS_NSCN_SHIFT 19
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_LPSCNITV_MASK 0xF000000u
+#define TSI_GENCS_LPSCNITV_SHIFT 24
+#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
+#define TSI_GENCS_LPCLKS_MASK 0x10000000u
+#define TSI_GENCS_LPCLKS_SHIFT 28
+/* SCANC Bit Fields */
+#define TSI_SCANC_AMPSC_MASK 0x7u
+#define TSI_SCANC_AMPSC_SHIFT 0
+#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
+#define TSI_SCANC_AMCLKS_MASK 0x18u
+#define TSI_SCANC_AMCLKS_SHIFT 3
+#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
+#define TSI_SCANC_SMOD_MASK 0xFF00u
+#define TSI_SCANC_SMOD_SHIFT 8
+#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
+#define TSI_SCANC_EXTCHRG_MASK 0xF0000u
+#define TSI_SCANC_EXTCHRG_SHIFT 16
+#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
+#define TSI_SCANC_REFCHRG_MASK 0xF000000u
+#define TSI_SCANC_REFCHRG_SHIFT 24
+#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
+/* PEN Bit Fields */
+#define TSI_PEN_PEN0_MASK 0x1u
+#define TSI_PEN_PEN0_SHIFT 0
+#define TSI_PEN_PEN1_MASK 0x2u
+#define TSI_PEN_PEN1_SHIFT 1
+#define TSI_PEN_PEN2_MASK 0x4u
+#define TSI_PEN_PEN2_SHIFT 2
+#define TSI_PEN_PEN3_MASK 0x8u
+#define TSI_PEN_PEN3_SHIFT 3
+#define TSI_PEN_PEN4_MASK 0x10u
+#define TSI_PEN_PEN4_SHIFT 4
+#define TSI_PEN_PEN5_MASK 0x20u
+#define TSI_PEN_PEN5_SHIFT 5
+#define TSI_PEN_PEN6_MASK 0x40u
+#define TSI_PEN_PEN6_SHIFT 6
+#define TSI_PEN_PEN7_MASK 0x80u
+#define TSI_PEN_PEN7_SHIFT 7
+#define TSI_PEN_PEN8_MASK 0x100u
+#define TSI_PEN_PEN8_SHIFT 8
+#define TSI_PEN_PEN9_MASK 0x200u
+#define TSI_PEN_PEN9_SHIFT 9
+#define TSI_PEN_PEN10_MASK 0x400u
+#define TSI_PEN_PEN10_SHIFT 10
+#define TSI_PEN_PEN11_MASK 0x800u
+#define TSI_PEN_PEN11_SHIFT 11
+#define TSI_PEN_PEN12_MASK 0x1000u
+#define TSI_PEN_PEN12_SHIFT 12
+#define TSI_PEN_PEN13_MASK 0x2000u
+#define TSI_PEN_PEN13_SHIFT 13
+#define TSI_PEN_PEN14_MASK 0x4000u
+#define TSI_PEN_PEN14_SHIFT 14
+#define TSI_PEN_PEN15_MASK 0x8000u
+#define TSI_PEN_PEN15_SHIFT 15
+#define TSI_PEN_LPSP_MASK 0xF0000u
+#define TSI_PEN_LPSP_SHIFT 16
+#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
+/* WUCNTR Bit Fields */
+#define TSI_WUCNTR_WUCNT_MASK 0xFFFFu
+#define TSI_WUCNTR_WUCNT_SHIFT 0
+#define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
+/* CNTR1 Bit Fields */
+#define TSI_CNTR1_CTN1_MASK 0xFFFFu
+#define TSI_CNTR1_CTN1_SHIFT 0
+#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
+#define TSI_CNTR1_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR1_CTN_SHIFT 16
+#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
+/* CNTR3 Bit Fields */
+#define TSI_CNTR3_CTN1_MASK 0xFFFFu
+#define TSI_CNTR3_CTN1_SHIFT 0
+#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
+#define TSI_CNTR3_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR3_CTN_SHIFT 16
+#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
+/* CNTR5 Bit Fields */
+#define TSI_CNTR5_CTN1_MASK 0xFFFFu
+#define TSI_CNTR5_CTN1_SHIFT 0
+#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
+#define TSI_CNTR5_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR5_CTN_SHIFT 16
+#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
+/* CNTR7 Bit Fields */
+#define TSI_CNTR7_CTN1_MASK 0xFFFFu
+#define TSI_CNTR7_CTN1_SHIFT 0
+#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
+#define TSI_CNTR7_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR7_CTN_SHIFT 16
+#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
+/* CNTR9 Bit Fields */
+#define TSI_CNTR9_CTN1_MASK 0xFFFFu
+#define TSI_CNTR9_CTN1_SHIFT 0
+#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
+#define TSI_CNTR9_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR9_CTN_SHIFT 16
+#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
+/* CNTR11 Bit Fields */
+#define TSI_CNTR11_CTN1_MASK 0xFFFFu
+#define TSI_CNTR11_CTN1_SHIFT 0
+#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
+#define TSI_CNTR11_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR11_CTN_SHIFT 16
+#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
+/* CNTR13 Bit Fields */
+#define TSI_CNTR13_CTN1_MASK 0xFFFFu
+#define TSI_CNTR13_CTN1_SHIFT 0
+#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
+#define TSI_CNTR13_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR13_CTN_SHIFT 16
+#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
+/* CNTR15 Bit Fields */
+#define TSI_CNTR15_CTN1_MASK 0xFFFFu
+#define TSI_CNTR15_CTN1_SHIFT 0
+#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
+#define TSI_CNTR15_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR15_CTN_SHIFT 16
+#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
+/* THRESHOLD Bit Fields */
+#define TSI_THRESHOLD_HTHH_MASK 0xFFFFu
+#define TSI_THRESHOLD_HTHH_SHIFT 0
+#define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
+#define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u
+#define TSI_THRESHOLD_LTHH_SHIFT 16
+#define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
+
+/**
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+
+/**
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+ __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
+ __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
+ __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
+ __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
+ __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
+ __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
+ __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
+ __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
+ __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
+ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+ union { /* offset: 0x1B */
+ __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ };
+ __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
+ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
+ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
+ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
+ uint8_t RESERVED_2[1];
+ __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
+ __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
+ __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
+ __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */
+ __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
+ __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
+ __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */
+ __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
+ __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
+ __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */
+ __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */
+ __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */
+ __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
+ __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
+ __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
+ __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
+ __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+#define UART_BDH_LBKDIE_MASK 0x80u
+#define UART_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_UARTSWAI_MASK 0x40u
+#define UART_C1_UARTSWAI_SHIFT 6
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_LBKDE_MASK 0x2u
+#define UART_S2_LBKDE_SHIFT 1
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_MSBF_MASK 0x20u
+#define UART_S2_MSBF_SHIFT 5
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+#define UART_S2_LBKDIF_MASK 0x80u
+#define UART_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_RT_MASK 0xFFu
+#define UART_D_RT_SHIFT 0
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK 0xFFu
+#define UART_MA1_MA_SHIFT 0
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK 0xFFu
+#define UART_MA2_MA_SHIFT 0
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK 0x1Fu
+#define UART_C4_BRFA_SHIFT 0
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK 0x20u
+#define UART_C4_M10_SHIFT 5
+#define UART_C4_MAEN2_MASK 0x40u
+#define UART_C4_MAEN2_SHIFT 6
+#define UART_C4_MAEN1_MASK 0x80u
+#define UART_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UART_C5_RDMAS_MASK 0x20u
+#define UART_C5_RDMAS_SHIFT 5
+#define UART_C5_TDMAS_MASK 0x80u
+#define UART_C5_TDMAS_SHIFT 7
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK 0x40u
+#define UART_ED_PARITYE_SHIFT 6
+#define UART_ED_NOISY_MASK 0x80u
+#define UART_ED_NOISY_SHIFT 7
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK 0x1u
+#define UART_MODEM_TXCTSE_SHIFT 0
+#define UART_MODEM_TXRTSE_MASK 0x2u
+#define UART_MODEM_TXRTSE_SHIFT 1
+#define UART_MODEM_TXRTSPOL_MASK 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT 2
+#define UART_MODEM_RXRTSE_MASK 0x8u
+#define UART_MODEM_RXRTSE_SHIFT 3
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK 0x3u
+#define UART_IR_TNP_SHIFT 0
+#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK 0x4u
+#define UART_IR_IREN_SHIFT 2
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
+#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK 0x8u
+#define UART_PFIFO_RXFE_SHIFT 3
+#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
+#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK 0x80u
+#define UART_PFIFO_TXFE_SHIFT 7
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK 0x1u
+#define UART_CFIFO_RXUFE_SHIFT 0
+#define UART_CFIFO_TXOFE_MASK 0x2u
+#define UART_CFIFO_TXOFE_SHIFT 1
+#define UART_CFIFO_RXFLUSH_MASK 0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT 6
+#define UART_CFIFO_TXFLUSH_MASK 0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT 7
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK 0x1u
+#define UART_SFIFO_RXUF_SHIFT 0
+#define UART_SFIFO_TXOF_MASK 0x2u
+#define UART_SFIFO_TXOF_SHIFT 1
+#define UART_SFIFO_RXEMPT_MASK 0x40u
+#define UART_SFIFO_RXEMPT_SHIFT 6
+#define UART_SFIFO_TXEMPT_MASK 0x80u
+#define UART_SFIFO_TXEMPT_SHIFT 7
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT 0
+#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT 0
+#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT 0
+#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT 0
+#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK 0x1u
+#define UART_C7816_ISO_7816E_SHIFT 0
+#define UART_C7816_TTYPE_MASK 0x2u
+#define UART_C7816_TTYPE_SHIFT 1
+#define UART_C7816_INIT_MASK 0x4u
+#define UART_C7816_INIT_SHIFT 2
+#define UART_C7816_ANACK_MASK 0x8u
+#define UART_C7816_ANACK_SHIFT 3
+#define UART_C7816_ONACK_MASK 0x10u
+#define UART_C7816_ONACK_SHIFT 4
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK 0x1u
+#define UART_IE7816_RXTE_SHIFT 0
+#define UART_IE7816_TXTE_MASK 0x2u
+#define UART_IE7816_TXTE_SHIFT 1
+#define UART_IE7816_GTVE_MASK 0x4u
+#define UART_IE7816_GTVE_SHIFT 2
+#define UART_IE7816_INITDE_MASK 0x10u
+#define UART_IE7816_INITDE_SHIFT 4
+#define UART_IE7816_BWTE_MASK 0x20u
+#define UART_IE7816_BWTE_SHIFT 5
+#define UART_IE7816_CWTE_MASK 0x40u
+#define UART_IE7816_CWTE_SHIFT 6
+#define UART_IE7816_WTE_MASK 0x80u
+#define UART_IE7816_WTE_SHIFT 7
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK 0x1u
+#define UART_IS7816_RXT_SHIFT 0
+#define UART_IS7816_TXT_MASK 0x2u
+#define UART_IS7816_TXT_SHIFT 1
+#define UART_IS7816_GTV_MASK 0x4u
+#define UART_IS7816_GTV_SHIFT 2
+#define UART_IS7816_INITD_MASK 0x10u
+#define UART_IS7816_INITD_SHIFT 4
+#define UART_IS7816_BWT_MASK 0x20u
+#define UART_IS7816_BWT_SHIFT 5
+#define UART_IS7816_CWT_MASK 0x40u
+#define UART_IS7816_CWT_SHIFT 6
+#define UART_IS7816_WT_MASK 0x80u
+#define UART_IS7816_WT_SHIFT 7
+/* WP7816_T_TYPE0 Bit Fields */
+#define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
+#define UART_WP7816_T_TYPE0_WI_SHIFT 0
+#define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
+/* WP7816_T_TYPE1 Bit Fields */
+#define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
+#define UART_WP7816_T_TYPE1_BWI_SHIFT 0
+#define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
+#define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
+#define UART_WP7816_T_TYPE1_CWI_SHIFT 4
+#define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK 0xFFu
+#define UART_WN7816_GTN_SHIFT 0
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK 0xFFu
+#define UART_WF7816_GTFD_SHIFT 0
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT 0
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT 4
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK 0xFFu
+#define UART_TL7816_TLEN_SHIFT 0
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+/* C6 Bit Fields */
+#define UART_C6_CP_MASK 0x10u
+#define UART_C6_CP_SHIFT 4
+#define UART_C6_CE_MASK 0x20u
+#define UART_C6_CE_SHIFT 5
+#define UART_C6_TX709_MASK 0x40u
+#define UART_C6_TX709_SHIFT 6
+#define UART_C6_EN709_MASK 0x80u
+#define UART_C6_EN709_SHIFT 7
+/* PCTH Bit Fields */
+#define UART_PCTH_PCTH_MASK 0xFFu
+#define UART_PCTH_PCTH_SHIFT 0
+#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
+/* PCTL Bit Fields */
+#define UART_PCTL_PCTL_MASK 0xFFu
+#define UART_PCTL_PCTL_SHIFT 0
+#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
+/* B1T Bit Fields */
+#define UART_B1T_B1T_MASK 0xFFu
+#define UART_B1T_B1T_SHIFT 0
+#define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
+/* SDTH Bit Fields */
+#define UART_SDTH_SDTH_MASK 0xFFu
+#define UART_SDTH_SDTH_SHIFT 0
+#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
+/* SDTL Bit Fields */
+#define UART_SDTL_SDTL_MASK 0xFFu
+#define UART_SDTL_SDTL_SHIFT 0
+#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
+/* PRE Bit Fields */
+#define UART_PRE_PREAMBLE_MASK 0xFFu
+#define UART_PRE_PREAMBLE_SHIFT 0
+#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
+/* TPL Bit Fields */
+#define UART_TPL_TPL_MASK 0xFFu
+#define UART_TPL_TPL_SHIFT 0
+#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
+/* IE Bit Fields */
+#define UART_IE_TXFIE_MASK 0x1u
+#define UART_IE_TXFIE_SHIFT 0
+#define UART_IE_PSIE_MASK 0x2u
+#define UART_IE_PSIE_SHIFT 1
+#define UART_IE_PCTEIE_MASK 0x4u
+#define UART_IE_PCTEIE_SHIFT 2
+#define UART_IE_PTXIE_MASK 0x8u
+#define UART_IE_PTXIE_SHIFT 3
+#define UART_IE_PRXIE_MASK 0x10u
+#define UART_IE_PRXIE_SHIFT 4
+#define UART_IE_ISDIE_MASK 0x20u
+#define UART_IE_ISDIE_SHIFT 5
+#define UART_IE_WBEIE_MASK 0x40u
+#define UART_IE_WBEIE_SHIFT 6
+/* WB Bit Fields */
+#define UART_WB_WBASE_MASK 0xFFu
+#define UART_WB_WBASE_SHIFT 0
+#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
+/* S3 Bit Fields */
+#define UART_S3_TXFF_MASK 0x1u
+#define UART_S3_TXFF_SHIFT 0
+#define UART_S3_PSF_MASK 0x2u
+#define UART_S3_PSF_SHIFT 1
+#define UART_S3_PCTEF_MASK 0x4u
+#define UART_S3_PCTEF_SHIFT 2
+#define UART_S3_PTXF_MASK 0x8u
+#define UART_S3_PTXF_SHIFT 3
+#define UART_S3_PRXF_MASK 0x10u
+#define UART_S3_PRXF_SHIFT 4
+#define UART_S3_ISD_MASK 0x20u
+#define UART_S3_ISD_SHIFT 5
+#define UART_S3_WBEF_MASK 0x40u
+#define UART_S3_WBEF_SHIFT 6
+#define UART_S3_PEF_MASK 0x80u
+#define UART_S3_PEF_SHIFT 7
+/* S4 Bit Fields */
+#define UART_S4_FE_MASK 0x1u
+#define UART_S4_FE_SHIFT 0
+#define UART_S4_ILCV_MASK 0x2u
+#define UART_S4_ILCV_SHIFT 1
+#define UART_S4_CDET_MASK 0xCu
+#define UART_S4_CDET_SHIFT 2
+#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
+#define UART_S4_INITF_MASK 0x10u
+#define UART_S4_INITF_SHIFT 4
+/* RPL Bit Fields */
+#define UART_RPL_RPL_MASK 0xFFu
+#define UART_RPL_RPL_SHIFT 0
+#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
+/* RPREL Bit Fields */
+#define UART_RPREL_RPREL_MASK 0xFFu
+#define UART_RPREL_RPREL_SHIFT 0
+#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
+/* CPW Bit Fields */
+#define UART_CPW_CPW_MASK 0xFFu
+#define UART_CPW_CPW_SHIFT 0
+#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
+/* RIDT Bit Fields */
+#define UART_RIDT_RIDT_MASK 0xFFu
+#define UART_RIDT_RIDT_SHIFT 0
+#define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
+/* TIDT Bit Fields */
+#define UART_TIDT_TIDT_MASK 0xFFu
+#define UART_TIDT_TIDT_SHIFT 0
+#define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
+
+/**
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART_Type *)UART0_BASE)
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+
+/**
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status Register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control Register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
+ uint8_t RESERVED_25[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+#define USB_ADDINFO_IRQNUM_MASK 0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT 3
+#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
+#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
+#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
+#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT 6
+#define USB_OTGISTAT_IDCHG_MASK 0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK 0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT 0
+#define USB_OTGICR_BSESSEN_MASK 0x4u
+#define USB_OTGICR_BSESSEN_SHIFT 2
+#define USB_OTGICR_SESSVLDEN_MASK 0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT 3
+#define USB_OTGICR_LINESTATEEN_MASK 0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT 5
+#define USB_OTGICR_ONEMSECEN_MASK 0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT 6
+#define USB_OTGICR_IDEN_MASK 0x80u
+#define USB_OTGICR_IDEN_SHIFT 7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
+#define USB_OTGSTAT_BSESSEND_MASK 0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT 2
+#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT 3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
+#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
+#define USB_OTGSTAT_ID_MASK 0x80u
+#define USB_OTGSTAT_ID_SHIFT 7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK 0x4u
+#define USB_OTGCTL_OTGEN_SHIFT 2
+#define USB_OTGCTL_DMLOW_MASK 0x10u
+#define USB_OTGCTL_DMLOW_SHIFT 4
+#define USB_OTGCTL_DPLOW_MASK 0x20u
+#define USB_OTGCTL_DPLOW_SHIFT 5
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_ATTACH_MASK 0x40u
+#define USB_ISTAT_ATTACH_SHIFT 6
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_ATTACHEN_MASK 0x40u
+#define USB_INTEN_ATTACHEN_SHIFT 6
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_RESUME_MASK 0x4u
+#define USB_CTL_RESUME_SHIFT 2
+#define USB_CTL_HOSTMODEEN_MASK 0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT 3
+#define USB_CTL_RESET_MASK 0x10u
+#define USB_CTL_RESET_SHIFT 4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK 0x80u
+#define USB_ADDR_LSEN_SHIFT 7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK 0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT 0
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK 0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT 4
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK 0xFFu
+#define USB_SOFTHLD_CNT_SHIFT 0
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+#define USB_ENDPT_RETRYDIS_MASK 0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT 6
+#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT 7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT 0
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+
+/**
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+
+/**
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */
+ __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */
+ __I uint32_t STATUS; /**< Status Register, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */
+ __IO uint32_t TIMER1; /**< , offset: 0x14 */
+ __IO uint32_t TIMER2; /**< , offset: 0x18 */
+} USBDCD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT 0
+#define USBDCD_CONTROL_IF_MASK 0x100u
+#define USBDCD_CONTROL_IF_SHIFT 8
+#define USBDCD_CONTROL_IE_MASK 0x10000u
+#define USBDCD_CONTROL_IE_SHIFT 16
+#define USBDCD_CONTROL_START_MASK 0x1000000u
+#define USBDCD_CONTROL_START_SHIFT 24
+#define USBDCD_CONTROL_SR_MASK 0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT 25
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
+#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/* STATUS Bit Fields */
+#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
+#define USBDCD_STATUS_SEQ_RES_SHIFT 16
+#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
+#define USBDCD_STATUS_SEQ_STAT_SHIFT 18
+#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK 0x100000u
+#define USBDCD_STATUS_ERR_SHIFT 20
+#define USBDCD_STATUS_TO_MASK 0x200000u
+#define USBDCD_STATUS_TO_SHIFT 21
+#define USBDCD_STATUS_ACTIVE_MASK 0x400000u
+#define USBDCD_STATUS_ACTIVE_SHIFT 22
+/* TIMER0 Bit Fields */
+#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
+#define USBDCD_TIMER0_TUNITCON_SHIFT 0
+#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
+#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
+/* TIMER1 Bit Fields */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
+#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
+#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
+/* TIMER2 Bit Fields */
+#define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
+#define USBDCD_TIMER2_CHECK_DM_SHIFT 0
+#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
+#define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
+#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
+#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
+
+/**
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
+
+/**
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
+ __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type;
+
+/* ----------------------------------------------------------------------------
+ -- VREF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK 0x3Fu
+#define VREF_TRM_TRIM_SHIFT 0
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK 0x40u
+#define VREF_TRM_CHOPEN_SHIFT 6
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK 0x3u
+#define VREF_SC_MODE_LV_SHIFT 0
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK 0x4u
+#define VREF_SC_VREFST_SHIFT 2
+#define VREF_SC_REGEN_MASK 0x40u
+#define VREF_SC_REGEN_SHIFT 6
+#define VREF_SC_VREFEN_MASK 0x80u
+#define VREF_SC_VREFEN_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF ((VREF_Type *)VREF_BASE)
+
+/**
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+ __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
+ __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
+ __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
+ __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+ __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
+ __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
+ __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */
+ __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */
+ __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
+ __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
+ __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */
+ __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */
+} WDOG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT 0
+#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT 1
+#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
+#define WDOG_STCTRLH_WINEN_MASK 0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT 3
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
+#define WDOG_STCTRLH_DBGEN_MASK 0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT 5
+#define WDOG_STCTRLH_STOPEN_MASK 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT 6
+#define WDOG_STCTRLH_WAITEN_MASK 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT 7
+#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
+#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT 11
+#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT 12
+#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT 15
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
+#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT 0
+#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT 0
+#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK 0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT 0
+#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
+#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
+#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
+#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
+#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT 0
+#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT 8
+#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/**
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG ((WDOG_Type *)WDOG_BASE)
+
+/**
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/**
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+/* No backward compatibility issues. */
+
+/**
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#endif /* #if !defined(MK20D5_H_) */
+
+/* MK20D5.h, eof. */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct
new file mode 100644
index 000000000..9a661627b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/MK20D5.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x20000 { ; load region size_region (132k)
+ ER_IROM1 0x00000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0xF8) = 0xF8
+ ; 0x4000 - 0xF8 = 0x3F08
+ RW_IRAM1 0x1FFFE0F8 0x3F08 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s
new file mode 100644
index 000000000..24de2c250
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/startup_MK20D5.s
@@ -0,0 +1,412 @@
+;/*****************************************************************************
+; * @file: startup_MK20D5.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
+; * MK20D5
+; * @version: 1.0
+; * @date: 2011-12-15
+; *
+; * Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20002000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
+ DCD DMA_Error_IRQHandler ; DMA error interrupt
+ DCD Reserved21_IRQHandler ; Reserved interrupt 21
+ DCD FTFL_IRQHandler ; FTFL interrupt
+ DCD Read_Collision_IRQHandler ; Read collision interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD Watchdog_IRQHandler ; WDOG interrupt
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
+ DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
+ DCD UART0_LON_IRQHandler ; UART0 LON interrupt
+ DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt
+ DCD UART0_ERR_IRQHandler ; UART0 error interrupt
+ DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt
+ DCD UART1_ERR_IRQHandler ; UART1 error interrupt
+ DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt
+ DCD UART2_ERR_IRQHandler ; UART2 error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD CMP1_IRQHandler ; CMP1 interrupt
+ DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
+ DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
+ DCD CMT_IRQHandler ; CMT interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
+ DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
+ DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
+ DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
+ DCD PDB0_IRQHandler ; PDB0 interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD USBDCD_IRQHandler ; USBDCD interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTB_IRQHandler ; Port B interrupt
+ DCD PORTC_IRQHandler ; Port C interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+ DCD PORTE_IRQHandler ; Port E interrupt
+ DCD SWI_IRQHandler ; Software interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; <h> Data flash protection byte (FDPROT)
+; <i> Each bit protects a 1/8 region of the data flash memory.
+; <i> (Program flash only devices: Reserved)
+; <o.0> FDPROT.0
+; <o.1> FDPROT.1
+; <o.2> FDPROT.2
+; <o.3> FDPROT.3
+; <o.4> FDPROT.4
+; <o.5> FDPROT.5
+; <o.6> FDPROT.6
+; <o.7> FDPROT.7
+nFDPROT EQU 0x00
+FDPROT EQU nFDPROT:EOR:0xFF
+; </h>
+; <h> EEPROM protection byte (FEPROT)
+; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
+; <i> (Program flash only devices: Reserved)
+; <o.0> FEPROT.0
+; <o.1> FEPROT.1
+; <o.2> FEPROT.2
+; <o.3> FEPROT.3
+; <o.4> FEPROT.4
+; <o.5> FEPROT.5
+; <o.6> FEPROT.6
+; <o.7> FEPROT.7
+nFEPROT EQU 0x00
+FEPROT EQU nFEPROT:EOR:0xFF
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT
+; <0=> Low-power boot
+; <1=> normal boot
+; <o.1> EZPORT_DIS
+; <0=> EzPort operation is enabled
+; <1=> EzPort operation is disabled
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+; </h>
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, FEPROT, FDPROT
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT DMA_Error_IRQHandler [WEAK]
+ EXPORT Reserved21_IRQHandler [WEAK]
+ EXPORT FTFL_IRQHandler [WEAK]
+ EXPORT Read_Collision_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT Watchdog_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT I2S0_Tx_IRQHandler [WEAK]
+ EXPORT I2S0_Rx_IRQHandler [WEAK]
+ EXPORT UART0_LON_IRQHandler [WEAK]
+ EXPORT UART0_RX_TX_IRQHandler [WEAK]
+ EXPORT UART0_ERR_IRQHandler [WEAK]
+ EXPORT UART1_RX_TX_IRQHandler [WEAK]
+ EXPORT UART1_ERR_IRQHandler [WEAK]
+ EXPORT UART2_RX_TX_IRQHandler [WEAK]
+ EXPORT UART2_ERR_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT CMP1_IRQHandler [WEAK]
+ EXPORT FTM0_IRQHandler [WEAK]
+ EXPORT FTM1_IRQHandler [WEAK]
+ EXPORT CMT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT0_IRQHandler [WEAK]
+ EXPORT PIT1_IRQHandler [WEAK]
+ EXPORT PIT2_IRQHandler [WEAK]
+ EXPORT PIT3_IRQHandler [WEAK]
+ EXPORT PDB0_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT USBDCD_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTB_IRQHandler [WEAK]
+ EXPORT PORTC_IRQHandler [WEAK]
+ EXPORT PORTD_IRQHandler [WEAK]
+ EXPORT PORTE_IRQHandler [WEAK]
+ EXPORT SWI_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+DMA_Error_IRQHandler
+Reserved21_IRQHandler
+FTFL_IRQHandler
+Read_Collision_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+Watchdog_IRQHandler
+I2C0_IRQHandler
+SPI0_IRQHandler
+I2S0_Tx_IRQHandler
+I2S0_Rx_IRQHandler
+UART0_LON_IRQHandler
+UART0_RX_TX_IRQHandler
+UART0_ERR_IRQHandler
+UART1_RX_TX_IRQHandler
+UART1_ERR_IRQHandler
+UART2_RX_TX_IRQHandler
+UART2_ERR_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+FTM0_IRQHandler
+FTM1_IRQHandler
+CMT_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT0_IRQHandler
+PIT1_IRQHandler
+PIT2_IRQHandler
+PIT3_IRQHandler
+PDB0_IRQHandler
+USB0_IRQHandler
+USBDCD_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+SWI_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..3296df192
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld
new file mode 100644
index 000000000..600751ca0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/MK20D5.ld
@@ -0,0 +1,163 @@
+/*
+ * K20 ARM GCC linker script file
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFFE0F8, LENGTH = 16K - 0xF8
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ *(.text.Reset_Handler)
+ *(.text.System_Init)
+ . = ALIGN(4);
+ } > VECTORS
+
+ .flash_protect :
+ {
+ KEEP(*(.kinetis_flash_config_field))
+ . = ALIGN(4);
+ } > FLASH_PROTECTION
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s
new file mode 100644
index 000000000..ffa33181f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_GCC_ARM/startup_MK20D5.s
@@ -0,0 +1,259 @@
+/* File: startup_MK20D5.s
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.3
+ * Date: 08 Feb 2012
+ *
+ * Copyright (c) 2015, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0xC00
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DMA0_IRQHandler /* 0: Watchdog Timer */
+ .long DMA1_IRQHandler /* 1: Real Time Clock */
+ .long DMA2_IRQHandler /* 2: Timer0 / Timer1 */
+ .long DMA3_IRQHandler /* 3: Timer2 / Timer3 */
+ .long DMA_Error_IRQHandler /* 4: MCIa */
+ .long 0 /* 5: MCIb */
+ .long FTFL_IRQHandler /* 6: UART0 - DUT FPGA */
+ .long Read_Collision_IRQHandler /* 7: UART1 - DUT FPGA */
+ .long LVD_LVW_IRQHandler /* 8: UART2 - DUT FPGA */
+ .long LLW_IRQHandler /* 9: UART4 - not connected */
+ .long Watchdog_IRQHandler /* 10: AACI / AC97 */
+ .long I2C0_IRQHandler /* 11: CLCD Combined Interrupt */
+ .long SPI0_IRQHandler /* 12: Ethernet */
+ .long I2S0_Tx_IRQHandler /* 13: USB Device */
+ .long I2S0_Rx_IRQHandler /* 14: USB Host Controller */
+ .long UART0_LON_IRQHandler /* 15: Character LCD */
+ .long UART0_RX_TX_IRQHandler /* 16: Flexray */
+ .long UART0_ERR_IRQHandler /* 17: CAN */
+ .long UART1_RX_TX_IRQHandler /* 18: LIN */
+ .long UART1_ERR_IRQHandler /* 19: I2C ADC/DAC */
+ .long UART2_RX_TX_IRQHandler /* 20: Reserved */
+ .long UART2_ERR_IRQHandler /* 21: Reserved */
+ .long ADC0_IRQHandler /* 22: Reserved */
+ .long CMP0_IRQHandler /* 23: Reserved */
+ .long CMP1_IRQHandler /* 24: Reserved */
+ .long FTM0_IRQHandler /* 25: Reserved */
+ .long FTM1_IRQHandler /* 26: Reserved */
+ .long CMT_IRQHandler /* 27: Reserved */
+ .long RTC_IRQHandler /* 28: Reserved - CPU FPGA CLCD */
+ .long RTC_Seconds_IRQHandler /* 29: Reserved - CPU FPGA */
+ .long PIT0_IRQHandler /* 30: UART3 - CPU FPGA */
+ .long PIT1_IRQHandler /* 31: SPI Touchscreen - CPU FPGA */
+ .long PIT2_IRQHandler
+ .long PIT3_IRQHandler
+ .long PDB0_IRQHandler
+ .long USB0_IRQHandler
+ .long USBDCD_IRQHandler
+ .long TSI0_IRQHandler
+ .long MCG_IRQHandler
+ .long LPTimer_IRQHandler
+ .long PORTA_IRQHandler
+ .long PORTB_IRQHandler
+ .long PORTC_IRQHandler
+ .long PORTD_IRQHandler
+ .long PORTE_IRQHandler
+ .long SWI_IRQHandler
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.Lflash_to_ram_loop:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .Lflash_to_ram_loop
+
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler DMA0_IRQHandler
+ def_irq_default_handler DMA1_IRQHandler
+ def_irq_default_handler DMA2_IRQHandler
+ def_irq_default_handler DMA3_IRQHandler
+ def_irq_default_handler DMA_Error_IRQHandler
+ def_irq_default_handler FTFL_IRQHandler
+ def_irq_default_handler Read_Collision_IRQHandler
+ def_irq_default_handler LVD_LVW_IRQHandler
+ def_irq_default_handler LLW_IRQHandler
+ def_irq_default_handler Watchdog_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler I2S0_Tx_IRQHandler
+ def_irq_default_handler I2S0_Rx_IRQHandler
+ def_irq_default_handler UART0_LON_IRQHandler
+ def_irq_default_handler UART0_RX_TX_IRQHandler
+ def_irq_default_handler UART0_ERR_IRQHandler
+ def_irq_default_handler UART1_RX_TX_IRQHandler
+ def_irq_default_handler UART1_ERR_IRQHandler
+ def_irq_default_handler UART2_RX_TX_IRQHandler
+ def_irq_default_handler UART2_ERR_IRQHandler
+ def_irq_default_handler ADC0_IRQHandler
+ def_irq_default_handler CMP0_IRQHandler
+ def_irq_default_handler CMP1_IRQHandler
+ def_irq_default_handler FTM0_IRQHandler
+ def_irq_default_handler FTM1_IRQHandler
+ def_irq_default_handler CMT_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler RTC_Seconds_IRQHandler
+ def_irq_default_handler PIT0_IRQHandler
+ def_irq_default_handler PIT1_IRQHandler
+ def_irq_default_handler PIT2_IRQHandler
+ def_irq_default_handler PIT3_IRQHandler
+ def_irq_default_handler PDB0_IRQHandler
+ def_irq_default_handler USB0_IRQHandler
+ def_irq_default_handler USBDCD_IRQHandler
+ def_irq_default_handler TSI0_IRQHandler
+ def_irq_default_handler MCG_IRQHandler
+ def_irq_default_handler LPTimer_IRQHandler
+ def_irq_default_handler PORTA_IRQHandler
+ def_irq_default_handler PORTB_IRQHandler
+ def_irq_default_handler PORTC_IRQHandler
+ def_irq_default_handler PORTD_IRQHandler
+ def_irq_default_handler PORTE_IRQHandler
+ def_irq_default_handler SWI_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+/* Flash protection region, placed at 0x400 */
+ .text
+ .thumb
+ .align 2
+ .section .kinetis_flash_config_field,"a",%progbits
+kinetis_flash_config:
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xfffffffe
+
+ .end
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf
new file mode 100644
index 000000000..e73c38a0c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/MK20D5.icf
@@ -0,0 +1,52 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0001ffff;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x1fffe000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x1fffe0f7;
+define symbol __ICFEDIT_region_RAM_start__ = 0x1fffe0f8;
+define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x600;
+define symbol __ICFEDIT_size_heap__ = 0xC00;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM2_start__ = 0x20000000;
+define symbol __region_RAM2_end__ = 0x20001fff;
+
+define symbol __FlashConfig_start__ = 0x00000400;
+define symbol __FlashConfig_end__ = 0x0000040f;
+
+define symbol __region_FlexNVM_start__ = 0x10000000;
+define symbol __region_FlexNVM_end__ = 0x10007fff;
+
+define symbol __region_FlexRAM_start__ = 0x14000000;
+define symbol __region_FlexRAM_end__ = 0x140007ff;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__] | mem:[from __region_FlexNVM_start__ to __region_FlexNVM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
+define region FlexRAM_region = mem:[from __region_FlexRAM_start__ to __region_FlexRAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in FlashConfig_region {section FlashConfig};
+
+place in ROM_region { readonly };
+
+place in RAM_region { readwrite, block HEAP, block CSTACK };
+
+place in FlexRAM_region { section .flex_ram };
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s
new file mode 100644
index 000000000..cee394eaf
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/TOOLCHAIN_IAR/startup_MK20D5.s
@@ -0,0 +1,271 @@
+/**************************************************
+ *
+ * Copyright 2010 IAR Systems. All rights reserved.
+ *
+ * $Revision: 16 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:ROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete
+ DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete
+ DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete
+ DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete
+ DCD DMA_ERR_IRQHandler ; 4: DMA Error Interrupt Channels 0-15
+ DCD 0 ; 5: Reserved
+ DCD FLASH_CC_IRQHandler ; 6: Flash memory command complete
+ DCD FLASH_RC_IRQHandler ; 7: Flash memory read collision
+ DCD VLD_IRQHandler ; 8: Low Voltage Detect, Low Voltage Warning
+ DCD LLWU_IRQHandler ; 9: Low Leakage Wakeup
+ DCD WDOG_IRQHandler ;10: WDOG interrupt
+ DCD I2C0_IRQHandler ;11: I2C0 interrupt
+ DCD SPI0_IRQHandler ;12: SPI 0 interrupt
+ DCD I2S0_IRQHandler ;13: I2S 0 interrupt
+ DCD I2S1_IRQHandler ;14: I2S 1 interrupt
+ DCD UART0_LON_IRQHandler ;15: UART 0 LON intertrupt
+ DCD UART0_IRQHandler ;16: UART 0 intertrupt
+ DCD UART0_ERR_IRQHandler ;17: UART 0 error intertrupt
+ DCD UART1_IRQHandler ;18: UART 1 intertrupt
+ DCD UART1_ERR_IRQHandler ;19: UART 1 error intertrupt
+ DCD UART2_IRQHandler ;20: UART 2 intertrupt
+ DCD UART2_ERR_IRQHandler ;21: UART 2 error intertrupt
+ DCD ADC0_IRQHandler ;22: ADC 0 interrupt
+ DCD CMP0_IRQHandler ;23: CMP 0 High-speed comparator interrupt
+ DCD CMP1_IRQHandler ;24: CMP 1 interrupt
+ DCD FTM0_IRQHandler ;25: FTM 0 interrupt
+ DCD FTM1_IRQHandler ;26: FTM 1 interrupt
+ DCD CMT_IRQHandler ;27: CMT intrrupt
+ DCD RTC_ALRM_IRQHandler ;28: RTC Alarm interrupt
+ DCD RTC_SEC_IRQHandler ;29: RTC Sec interrupt
+ DCD PIT0_IRQHandler ;30: PIT 0 interrupt
+ DCD PIT1_IRQHandler ;31: PIT 1 interrupt
+ DCD PIT2_IRQHandler ;32: PIT 2 interrupt
+ DCD PIT3_IRQHandler ;33: PIT 3 interrupt
+ DCD PDB_IRQHandler ;34: PDB interrupt
+ DCD USB_OTG_IRQHandler ;35: USB OTG interrupt
+ DCD USB_CD_IRQHandler ;36: USB Charger Detect interrupt
+ DCD TSI_IRQHandler ;37: TSI interrupt
+ DCD MCG_IRQHandler ;38: MCG interrupt
+ DCD LPT_IRQHandler ;39: LPT interrupt
+ DCD PORTA_IRQHandler ;40: PORT A interrupt
+ DCD PORTB_IRQHandler ;41: PORT B interrupt
+ DCD PORTC_IRQHandler ;42: PORT C interrupt
+ DCD PORTD_IRQHandler ;43: PORT D interrupt
+ DCD PORTE_IRQHandler ;44: PORT E interrupt
+ DCD SW_IRQHandler ;45: Software initiated interrupt
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;Flash Configuration
+;;16-byte flash configuration field that stores default protection settings (loaded on reset)
+;;and security information that allows the MCU to restrict acces to the FTFL module.
+
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0^0xFF
+
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1^0xFF
+
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2^0xFF
+
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3^0xFF
+
+nFEPROT EQU 0x00
+FEPROT EQU nFEPROT^0xFF
+
+nFDPROT EQU 0x00
+FDPROT EQU nFDPROT^0xFF
+
+FOPT EQU 0xFF
+
+FSEC EQU 0xFE
+ SECTION FlashConfig:CONST:REORDER:ROOT(2)
+Config:
+ DATA
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, FEPROT, FDPROT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK DMA0_IRQHandler
+ PUBWEAK DMA1_IRQHandler
+ PUBWEAK DMA2_IRQHandler
+ PUBWEAK DMA3_IRQHandler
+ PUBWEAK DMA_ERR_IRQHandler
+ PUBWEAK FLASH_CC_IRQHandler
+ PUBWEAK FLASH_RC_IRQHandler
+ PUBWEAK VLD_IRQHandler
+ PUBWEAK LLWU_IRQHandler
+ PUBWEAK WDOG_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK I2S0_IRQHandler
+ PUBWEAK I2S1_IRQHandler
+ PUBWEAK UART0_LON_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART0_ERR_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK UART1_ERR_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK UART2_ERR_IRQHandler
+ PUBWEAK ADC0_IRQHandler
+ PUBWEAK CMP0_IRQHandler
+ PUBWEAK CMP1_IRQHandler
+ PUBWEAK FTM0_IRQHandler
+ PUBWEAK FTM1_IRQHandler
+ PUBWEAK CMT_IRQHandler
+ PUBWEAK RTC_ALRM_IRQHandler
+ PUBWEAK RTC_SEC_IRQHandler
+ PUBWEAK PIT0_IRQHandler
+ PUBWEAK PIT1_IRQHandler
+ PUBWEAK PIT2_IRQHandler
+ PUBWEAK PIT3_IRQHandler
+ PUBWEAK PDB_IRQHandler
+ PUBWEAK USB_OTG_IRQHandler
+ PUBWEAK USB_CD_IRQHandler
+ PUBWEAK TSI_IRQHandler
+ PUBWEAK MCG_IRQHandler
+ PUBWEAK LPT_IRQHandler
+ PUBWEAK PORTA_IRQHandler
+ PUBWEAK PORTB_IRQHandler
+ PUBWEAK PORTC_IRQHandler
+ PUBWEAK PORTD_IRQHandler
+ PUBWEAK PORTE_IRQHandler
+ PUBWEAK SW_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+SVC_Handler
+DebugMon_Handler
+PendSV_Handler
+SysTick_Handler
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+DMA_ERR_IRQHandler
+FLASH_CC_IRQHandler
+FLASH_RC_IRQHandler
+VLD_IRQHandler
+LLWU_IRQHandler
+WDOG_IRQHandler
+I2C0_IRQHandler
+SPI0_IRQHandler
+I2S0_IRQHandler
+I2S1_IRQHandler
+UART0_LON_IRQHandler
+UART0_IRQHandler
+UART0_ERR_IRQHandler
+UART1_IRQHandler
+UART1_ERR_IRQHandler
+UART2_IRQHandler
+UART2_ERR_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+FTM0_IRQHandler
+FTM1_IRQHandler
+CMT_IRQHandler
+RTC_ALRM_IRQHandler
+RTC_SEC_IRQHandler
+PIT0_IRQHandler
+PIT1_IRQHandler
+PIT2_IRQHandler
+PIT3_IRQHandler
+PDB_IRQHandler
+USB_OTG_IRQHandler
+USB_CD_IRQHandler
+TSI_IRQHandler
+MCG_IRQHandler
+LPT_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+SW_IRQHandler
+Default_Handler
+
+ B Default_Handler
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis.h
new file mode 100644
index 000000000..099017c7f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MK20D5.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c
new file mode 100644
index 000000000..16d1b1f7e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h
new file mode 100644
index 000000000..04cf15b21
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 46) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c
new file mode 100644
index 000000000..9cd3c16b0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c
@@ -0,0 +1,278 @@
+/*
+** ###################################################################
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
+** K20P32M50SF0RM Rev. 1, Oct 2011
+** K20P48M50SF0RM Rev. 1, Oct 2011
+**
+** Version: rev. 1.0, 2011-12-15
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2011-12-15)
+** Initial version
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK20D5
+ * @version 1.0
+ * @date 2011-12-15
+ * @brief Device specific configuration file for MK20D5 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MK20D5.h"
+
+#define DISABLE_WDOG 1
+
+#define CLOCK_SETUP 1
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+ Reference clock source for MCG module is the slow internal clock source 32.768kHz
+ Core clock = 41.94MHz, BusClock = 41.94MHz
+ 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+ Reference clock source for MCG module is an external crystal 8MHz
+ Core clock = 48MHz, BusClock = 48MHz
+ 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+ Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
+ Core clock = 8MHz, BusClock = 8MHz
+*/
+
+/*----------------------------------------------------------------------------
+ Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+ /* Disable the WDOG module */
+ /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
+ WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
+ /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
+ WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
+ /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+ WDOG->STCTRLH = (uint16_t)0x01D2u;
+#endif /* (DISABLE_WDOG) */
+#if (CLOCK_SETUP == 0)
+ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
+ /* Switch to FEI Mode */
+ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x06u;
+ /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x00u;
+ /* MCG_C4: DMX32=0,DRST_DRS=1 */
+ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
+ /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00u;
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */
+ }
+#elif (CLOCK_SETUP == 1)
+ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
+ /* Switch to FBE Mode */
+ /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x00u;
+ /* MCG->C7: OSCSEL=0 */
+ MCG->C7 = (uint8_t)0x00u;
+ /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24u;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9Au;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
+ /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
+ MCG->C5 = (uint8_t)0x03u;
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
+ }
+#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
+ while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+#endif
+ while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to PBE Mode */
+ /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
+ MCG->C5 = (uint8_t)0x03u;
+ /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x40u;
+ while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */
+ }
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
+ }
+ /* Switch to PEE Mode */
+ /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x1Au;
+ while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */
+ }
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
+ }
+#elif (CLOCK_SETUP == 2)
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
+ /* Switch to FBE Mode */
+ /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x00u;
+ /* MCG->C7: OSCSEL=0 */
+ MCG->C7 = (uint8_t)0x00u;
+ /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24u;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9Au;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
+ /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00u;
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
+ }
+#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
+ while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+#endif
+ while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to BLPE Mode */
+ /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24u;
+#endif /* (CLOCK_SETUP == 2) */
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint8_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+ /* Output of FLL or PLL is selected */
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
+ /* FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+ /* External reference clock is selected */
+ if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
+ MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
+ } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x0u:
+ MCGOUTClock *= 640u;
+ break;
+ case 0x20u:
+ MCGOUTClock *= 1280u;
+ break;
+ case 0x40u:
+ MCGOUTClock *= 1920u;
+ break;
+ case 0x60u:
+ MCGOUTClock *= 2560u;
+ break;
+ case 0x80u:
+ MCGOUTClock *= 732u;
+ break;
+ case 0xA0u:
+ MCGOUTClock *= 1464u;
+ break;
+ case 0xC0u:
+ MCGOUTClock *= 2197u;
+ break;
+ case 0xE0u:
+ MCGOUTClock *= 2929u;
+ break;
+ default:
+ break;
+ }
+ } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ /* PLL is selected */
+ Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+ MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+ Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+ MCGOUTClock *= Divider; /* Calculate the MCG output clock */
+ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+ /* External reference clock is selected */
+ if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.h
new file mode 100644
index 000000000..738791790
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.h
@@ -0,0 +1,87 @@
+/*
+** ###################################################################
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manuals: K20P64M50SF0RM Rev. 1, Oct 2011
+** K20P32M50SF0RM Rev. 1, Oct 2011
+** K20P48M50SF0RM Rev. 1, Oct 2011
+**
+** Version: rev. 2.0, 2012-03-19
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2011-12-15)
+** Initial version
+** - rev. 2.0 (2012-03-19)
+** PDB Peripheral register structure updated.
+** DMA Registers and bits for unsupported DMA channels removed.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK20D5
+ * @version 2.0
+ * @date 2012-03-19
+ * @brief Device specific configuration file for MK20D5 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK20D5_H_
+#define SYSTEM_MK20D5_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MK20D5_H_) */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h
new file mode 100644
index 000000000..041f99782
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/MK20DX256.h
@@ -0,0 +1,6032 @@
+/*
+** ###################################################################
+** Processors: MK20DX64VLH7
+** MK20DX128VLH7
+** MK20DX256VLH7
+** MK20DX64VLK7
+** MK20DX128VLK7
+** MK20DX256VLK7
+** MK20DX128VLL7
+** MK20DX256VLL7
+** MK20DX64VMB7
+** MK20DX128VMB7
+** MK20DX256VMB7
+** MK20DX128VML7
+** MK20DX256VML7
+**
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: Kxx (P1 silicon) Sub-Family Reference Manual Rev. 0, draft A Oct 2011
+** Version: rev. 1.0, 2012-01-15
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-01-15)
+** Initial public version.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK20DX256.h
+ * @version 2.0
+ * @date 2012-03-19
+ * @brief CMSIS Peripheral Access Layer for MK20DX256
+ *
+ * CMSIS Peripheral Access Layer for MK20DX256
+ */
+
+#if !defined(MK20DX256_H_)
+#define MK20DX256_H_ /**< Symbol preventing repeated inclusion */
+#define MCU_MK20DX256
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000u
+
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
+ DMA4_IRQn = 4,
+ DMA5_IRQn = 5,
+ DMA6_IRQn = 6,
+ DMA7_IRQn = 7,
+ DMA8_IRQn = 8,
+ DMA9_IRQn = 9,
+ DMA10_IRQn = 10,
+ DMA11_IRQn = 11,
+ DMA12_IRQn = 12,
+ DMA13_IRQn = 13,
+ DMA14_IRQn = 14,
+ DMA15_IRQn = 15,
+ DMA_Error_IRQn = 16, /**< DMA error interrupt */
+ Reserved33_IRQn = 17,
+ FTFL_IRQn = 18, /**< FTFL interrupt */
+ Read_Collision_IRQn = 19, /**< Read collision interrupt */
+ LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 21, /**< Low Leakage Wakeup */
+ Watchdog_IRQn = 22, /**< WDOG interrupt */
+ Reserved39_IRQn = 23,
+ I2C0_IRQn = 24, /**< I2C0 interrupt */
+ I2C1_IRQn = 25,
+ SPI0_IRQn = 26, /**< SPI0 interrupt */
+ SPI1_IRQn = 27,
+ Reserved44_IRQn = 28,
+ CAN0_ORed_Message_buffer_IRQn = 29, /**< CAN0 OR'd message buffers interrupt */
+ CAN0_Bus_Off_IRQn = 30, /**< CAN0 bus off interrupt */
+ CAN0_Error_IRQn = 31, /**< CAN0 error interrupt */
+ CAN0_Tx_Warning_IRQn = 32, /**< CAN0 Tx warning interrupt */
+ CAN0_Rx_Warning_IRQn = 33, /**< CAN0 Rx warning interrupt */
+ CAN0_Wake_Up_IRQn = 34, /**< CAN0 wake up interrupt */
+ I2S0_Tx_IRQn = 35, /**< I2S0 transmit interrupt */
+ I2S0_Rx_IRQn = 36, /**< I2S0 receive interrupt */
+ Reserved53_IRQn = 37,
+ Reserved54_IRQn = 38,
+ Reserved55_IRQn = 39,
+ Reserved56_IRQn = 40,
+ Reserved57_IRQn = 41,
+ Reserved58_IRQn = 42,
+ Reserved59_IRQn = 43,
+ UART0_LON_IRQn = 44, /**< UART0 LON interrupt */
+ UART0_RX_TX_IRQn = 45, /**< UART0 receive/transmit interrupt */
+ UART0_ERR_IRQn = 46, /**< UART0 error interrupt */
+ UART1_RX_TX_IRQn = 47, /**< UART1 receive/transmit interrupt */
+ UART1_ERR_IRQn = 48, /**< UART1 error interrupt */
+ UART2_RX_TX_IRQn = 49, /**< UART2 receive/transmit interrupt */
+ UART2_ERR_IRQn = 50, /**< UART2 error interrupt */
+ Reserved67_IRQn = 51,
+ Reserved68_IRQn = 52,
+ Reserved69_IRQn = 53,
+ Reserved70_IRQn = 54,
+ Reserved71_IRQn = 55,
+ Reserved72_IRQn = 56,
+ ADC0_IRQn = 57, /**< ADC0 interrupt */
+ ADC1_IRQn = 58,
+ CMP0_IRQn = 59, /**< CMP0 interrupt */
+ CMP1_IRQn = 60, /**< CMP1 interrupt */
+ CMP2_IRQn = 61,
+ FTM0_IRQn = 62, /**< FTM0 fault, overflow and channels interrupt */
+ FTM1_IRQn = 63, /**< FTM1 fault, overflow and channels interrupt */
+ FTM2_IRQn = 64,
+ CMT_IRQn = 65, /**< CMT interrupt */
+ RTC_IRQn = 66, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 67, /**< RTC seconds interrupt */
+ PIT0_IRQn = 68, /**< PIT timer channel 0 interrupt */
+ PIT1_IRQn = 69, /**< PIT timer channel 1 interrupt */
+ PIT2_IRQn = 70, /**< PIT timer channel 2 interrupt */
+ PIT3_IRQn = 71, /**< PIT timer channel 3 interrupt */
+ PDB0_IRQn = 72, /**< PDB0 interrupt */
+ USB0_IRQn = 73, /**< USB0 interrupt */
+ USBDCD_IRQn = 74, /**< USBDCD interrupt */
+ Reserved91_IRQn = 75,
+ Reserved92_IRQn = 76,
+ Reserved93_IRQn = 77,
+ Reserved94_IRQn = 78,
+ Reserved95_IRQn = 79,
+ Reserved96_IRQn = 80,
+ DAC0_IRQn = 81,
+ Reserved98_IRQn = 82,
+ TSI0_IRQn = 83, /**< TSI0 interrupt */
+ MCG_IRQn = 84, /**< MCG interrupt */
+ LPTimer_IRQn = 85, /**< LPTimer interrupt */
+ Reserved102_IRQn = 86,
+ PORTA_IRQn = 87, /**< Port A interrupt */
+ PORTB_IRQn = 88, /**< Port B interrupt */
+ PORTC_IRQn = 89, /**< Port C interrupt */
+ PORTD_IRQn = 90, /**< Port D interrupt */
+ PORTE_IRQn = 91, /**< Port E interrupt */
+ Reserved108_IRQn = 92,
+ Reserved109_IRQn = 93,
+ SWI_IRQn = 94 /**< Software interrupt */
+
+} IRQn_Type;
+
+/**
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M4 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm4.h" /* Core Peripheral Access Layer */
+#include "system_MK20DX256.h" /* Device specific configuration file */
+
+/**
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC configuration register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< Configuration register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC data result register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare value registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare value registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and control register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and control register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC offset correction register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC plus-side gain register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC minus-side gain register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC plus-side general calibration value register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC plus-side general calibration value register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC plus-side general calibration value register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC plus-side general calibration value register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC plus-side general calibration value register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC plus-side general calibration value register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC plus-side general calibration value register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC minus-side general calibration value register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC minus-side general calibration value register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC minus-side general calibration value register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC minus-side general calibration value register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC minus-side general calibration value register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC minus-side general calibration value register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC minus-side general calibration value register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/**
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+
+/**
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1 ((CMP_Type *)CMP1_BASE)
+
+/**
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+ __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+ __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+ __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+ __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
+ __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
+ __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+ __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+ __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
+ __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+ __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
+ __IO uint8_t DMA; /**< CMT Direct Memory Access, offset: 0xB */
+} CMT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK 0xFFu
+#define CMT_CGH1_PH_SHIFT 0
+#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
+/* CGL1 Bit Fields */
+#define CMT_CGL1_PL_MASK 0xFFu
+#define CMT_CGL1_PL_SHIFT 0
+#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
+/* CGH2 Bit Fields */
+#define CMT_CGH2_SH_MASK 0xFFu
+#define CMT_CGH2_SH_SHIFT 0
+#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
+/* CGL2 Bit Fields */
+#define CMT_CGL2_SL_MASK 0xFFu
+#define CMT_CGL2_SL_SHIFT 0
+#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
+/* OC Bit Fields */
+#define CMT_OC_IROPEN_MASK 0x20u
+#define CMT_OC_IROPEN_SHIFT 5
+#define CMT_OC_CMTPOL_MASK 0x40u
+#define CMT_OC_CMTPOL_SHIFT 6
+#define CMT_OC_IROL_MASK 0x80u
+#define CMT_OC_IROL_SHIFT 7
+/* MSC Bit Fields */
+#define CMT_MSC_MCGEN_MASK 0x1u
+#define CMT_MSC_MCGEN_SHIFT 0
+#define CMT_MSC_EOCIE_MASK 0x2u
+#define CMT_MSC_EOCIE_SHIFT 1
+#define CMT_MSC_FSK_MASK 0x4u
+#define CMT_MSC_FSK_SHIFT 2
+#define CMT_MSC_BASE_MASK 0x8u
+#define CMT_MSC_BASE_SHIFT 3
+#define CMT_MSC_EXSPC_MASK 0x10u
+#define CMT_MSC_EXSPC_SHIFT 4
+#define CMT_MSC_CMTDIV_MASK 0x60u
+#define CMT_MSC_CMTDIV_SHIFT 5
+#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK 0x80u
+#define CMT_MSC_EOCF_SHIFT 7
+/* CMD1 Bit Fields */
+#define CMT_CMD1_MB_MASK 0xFFu
+#define CMT_CMD1_MB_SHIFT 0
+#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
+/* CMD2 Bit Fields */
+#define CMT_CMD2_MB_MASK 0xFFu
+#define CMT_CMD2_MB_SHIFT 0
+#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
+/* CMD3 Bit Fields */
+#define CMT_CMD3_SB_MASK 0xFFu
+#define CMT_CMD3_SB_SHIFT 0
+#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
+/* CMD4 Bit Fields */
+#define CMT_CMD4_SB_MASK 0xFFu
+#define CMT_CMD4_SB_SHIFT 0
+#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
+/* PPS Bit Fields */
+#define CMT_PPS_PPSDIV_MASK 0xFu
+#define CMT_PPS_PPSDIV_SHIFT 0
+#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
+/* DMA Bit Fields */
+#define CMT_DMA_DMA_MASK 0x1u
+#define CMT_DMA_DMA_SHIFT 0
+
+/**
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT ((CMT_Type *)CMT_BASE)
+
+/**
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */
+ __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */
+ } ACCESS16BIT;
+ __IO uint32_t CRC; /**< CRC Data Register, offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */
+ __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */
+ __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */
+ __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */
+ } ACCESS8BIT;
+ };
+ union { /* offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
+ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
+ } GPOLY_ACCESS16BIT;
+ __IO uint32_t GPOLY; /**< CRC Polynomial Register, offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
+ __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
+ __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
+ __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
+ } GPOLY_ACCESS8BIT;
+ };
+ union { /* offset: 0x8 */
+ __IO uint32_t CTRL; /**< CRC Control Register, offset: 0x8 */
+ struct { /* offset: 0x8 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
+ } CTRL_ACCESS8BIT;
+ };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* CRCL Bit Fields */
+#define CRC_CRCL_CRCL_MASK 0xFFFFu
+#define CRC_CRCL_CRCL_SHIFT 0
+#define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
+/* CRCH Bit Fields */
+#define CRC_CRCH_CRCH_MASK 0xFFFFu
+#define CRC_CRCH_CRCH_SHIFT 0
+#define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
+/* CRC Bit Fields */
+#define CRC_CRC_LL_MASK 0xFFu
+#define CRC_CRC_LL_SHIFT 0
+#define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
+#define CRC_CRC_LU_MASK 0xFF00u
+#define CRC_CRC_LU_SHIFT 8
+#define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
+#define CRC_CRC_HL_MASK 0xFF0000u
+#define CRC_CRC_HL_SHIFT 16
+#define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
+#define CRC_CRC_HU_MASK 0xFF000000u
+#define CRC_CRC_HU_SHIFT 24
+#define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
+/* CRCLL Bit Fields */
+#define CRC_CRCLL_CRCLL_MASK 0xFFu
+#define CRC_CRCLL_CRCLL_SHIFT 0
+#define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
+/* CRCLU Bit Fields */
+#define CRC_CRCLU_CRCLU_MASK 0xFFu
+#define CRC_CRCLU_CRCLU_SHIFT 0
+#define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
+/* CRCHL Bit Fields */
+#define CRC_CRCHL_CRCHL_MASK 0xFFu
+#define CRC_CRCHL_CRCHL_SHIFT 0
+#define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
+/* CRCHU Bit Fields */
+#define CRC_CRCHU_CRCHU_MASK 0xFFu
+#define CRC_CRCHU_CRCHU_SHIFT 0
+#define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT 0
+#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT 0
+#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK 0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT 0
+#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT 16
+#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
+#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
+#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
+#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
+#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK 0x1000000u
+#define CRC_CTRL_TCRC_SHIFT 24
+#define CRC_CTRL_WAS_MASK 0x2000000u
+#define CRC_CTRL_WAS_SHIFT 25
+#define CRC_CTRL_FXOR_MASK 0x4000000u
+#define CRC_CTRL_FXOR_SHIFT 26
+#define CRC_CTRL_TOTR_MASK 0x30000000u
+#define CRC_CTRL_TOTR_SHIFT 28
+#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK 0xC0000000u
+#define CRC_CTRL_TOT_SHIFT 30
+#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK 0x1u
+#define CRC_CTRLHU_TCRC_SHIFT 0
+#define CRC_CTRLHU_WAS_MASK 0x2u
+#define CRC_CTRLHU_WAS_SHIFT 1
+#define CRC_CTRLHU_FXOR_MASK 0x4u
+#define CRC_CTRLHU_FXOR_SHIFT 2
+#define CRC_CTRLHU_TOTR_MASK 0x30u
+#define CRC_CTRLHU_TOTR_SHIFT 4
+#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK 0xC0u
+#define CRC_CTRLHU_TOT_SHIFT 6
+#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/**
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0 ((CRC_Type *)CRC_BASE)
+
+/**
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[16];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+#define DAC_SR_DACBFWMF_MASK 0x4u
+#define DAC_SR_DACBFWMF_SHIFT 2
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_DACBWIEN_MASK 0x4u
+#define DAC_C0_DACBWIEN_SHIFT 2
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x6u
+#define DAC_C1_DACBFMD_SHIFT 1
+#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK 0x18u
+#define DAC_C1_DACBFWM_SHIFT 3
+#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0xFu
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK 0xF0u
+#define DAC_C2_DACBFRP_SHIFT 4
+#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/**
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x400CC000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASES { DAC0 }
+
+/**
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< Control Register, offset: 0x0 */
+ __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
+ __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+ __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
+ __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
+ __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
+ __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
+ __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
+ __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
+ __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
+ uint8_t RESERVED_5[200];
+ __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
+ __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
+ __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
+ __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
+ uint8_t RESERVED_6[3836];
+ struct { /* offset: 0x1000, array step: 0x20 */
+ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+ union { /* offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+ };
+ __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+ union { /* offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+ };
+ __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+ __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+ union { /* offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+ };
+ } TCD[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK 0x2u
+#define DMA_CR_EDBG_SHIFT 1
+#define DMA_CR_ERCA_MASK 0x4u
+#define DMA_CR_ERCA_SHIFT 2
+#define DMA_CR_HOE_MASK 0x10u
+#define DMA_CR_HOE_SHIFT 4
+#define DMA_CR_HALT_MASK 0x20u
+#define DMA_CR_HALT_SHIFT 5
+#define DMA_CR_CLM_MASK 0x40u
+#define DMA_CR_CLM_SHIFT 6
+#define DMA_CR_EMLM_MASK 0x80u
+#define DMA_CR_EMLM_SHIFT 7
+#define DMA_CR_ECX_MASK 0x10000u
+#define DMA_CR_ECX_SHIFT 16
+#define DMA_CR_CX_MASK 0x20000u
+#define DMA_CR_CX_SHIFT 17
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK 0x1u
+#define DMA_ES_DBE_SHIFT 0
+#define DMA_ES_SBE_MASK 0x2u
+#define DMA_ES_SBE_SHIFT 1
+#define DMA_ES_SGE_MASK 0x4u
+#define DMA_ES_SGE_SHIFT 2
+#define DMA_ES_NCE_MASK 0x8u
+#define DMA_ES_NCE_SHIFT 3
+#define DMA_ES_DOE_MASK 0x10u
+#define DMA_ES_DOE_SHIFT 4
+#define DMA_ES_DAE_MASK 0x20u
+#define DMA_ES_DAE_SHIFT 5
+#define DMA_ES_SOE_MASK 0x40u
+#define DMA_ES_SOE_SHIFT 6
+#define DMA_ES_SAE_MASK 0x80u
+#define DMA_ES_SAE_SHIFT 7
+#define DMA_ES_ERRCHN_MASK 0xF00u
+#define DMA_ES_ERRCHN_SHIFT 8
+#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK 0x4000u
+#define DMA_ES_CPE_SHIFT 14
+#define DMA_ES_ECX_MASK 0x10000u
+#define DMA_ES_ECX_SHIFT 16
+#define DMA_ES_VLD_MASK 0x80000000u
+#define DMA_ES_VLD_SHIFT 31
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK 0x1u
+#define DMA_ERQ_ERQ0_SHIFT 0
+#define DMA_ERQ_ERQ1_MASK 0x2u
+#define DMA_ERQ_ERQ1_SHIFT 1
+#define DMA_ERQ_ERQ2_MASK 0x4u
+#define DMA_ERQ_ERQ2_SHIFT 2
+#define DMA_ERQ_ERQ3_MASK 0x8u
+#define DMA_ERQ_ERQ3_SHIFT 3
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK 0x1u
+#define DMA_EEI_EEI0_SHIFT 0
+#define DMA_EEI_EEI1_MASK 0x2u
+#define DMA_EEI_EEI1_SHIFT 1
+#define DMA_EEI_EEI2_MASK 0x4u
+#define DMA_EEI_EEI2_SHIFT 2
+#define DMA_EEI_EEI3_MASK 0x8u
+#define DMA_EEI_EEI3_SHIFT 3
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK 0xFu
+#define DMA_CEEI_CEEI_SHIFT 0
+#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK 0x40u
+#define DMA_CEEI_CAEE_SHIFT 6
+#define DMA_CEEI_NOP_MASK 0x80u
+#define DMA_CEEI_NOP_SHIFT 7
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK 0xFu
+#define DMA_SEEI_SEEI_SHIFT 0
+#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK 0x40u
+#define DMA_SEEI_SAEE_SHIFT 6
+#define DMA_SEEI_NOP_MASK 0x80u
+#define DMA_SEEI_NOP_SHIFT 7
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK 0xFu
+#define DMA_CERQ_CERQ_SHIFT 0
+#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK 0x40u
+#define DMA_CERQ_CAER_SHIFT 6
+#define DMA_CERQ_NOP_MASK 0x80u
+#define DMA_CERQ_NOP_SHIFT 7
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK 0xFu
+#define DMA_SERQ_SERQ_SHIFT 0
+#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK 0x40u
+#define DMA_SERQ_SAER_SHIFT 6
+#define DMA_SERQ_NOP_MASK 0x80u
+#define DMA_SERQ_NOP_SHIFT 7
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK 0xFu
+#define DMA_CDNE_CDNE_SHIFT 0
+#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK 0x40u
+#define DMA_CDNE_CADN_SHIFT 6
+#define DMA_CDNE_NOP_MASK 0x80u
+#define DMA_CDNE_NOP_SHIFT 7
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK 0xFu
+#define DMA_SSRT_SSRT_SHIFT 0
+#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK 0x40u
+#define DMA_SSRT_SAST_SHIFT 6
+#define DMA_SSRT_NOP_MASK 0x80u
+#define DMA_SSRT_NOP_SHIFT 7
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK 0xFu
+#define DMA_CERR_CERR_SHIFT 0
+#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK 0x40u
+#define DMA_CERR_CAEI_SHIFT 6
+#define DMA_CERR_NOP_MASK 0x80u
+#define DMA_CERR_NOP_SHIFT 7
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK 0xFu
+#define DMA_CINT_CINT_SHIFT 0
+#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK 0x40u
+#define DMA_CINT_CAIR_SHIFT 6
+#define DMA_CINT_NOP_MASK 0x80u
+#define DMA_CINT_NOP_SHIFT 7
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK 0x1u
+#define DMA_INT_INT0_SHIFT 0
+#define DMA_INT_INT1_MASK 0x2u
+#define DMA_INT_INT1_SHIFT 1
+#define DMA_INT_INT2_MASK 0x4u
+#define DMA_INT_INT2_SHIFT 2
+#define DMA_INT_INT3_MASK 0x8u
+#define DMA_INT_INT3_SHIFT 3
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK 0x1u
+#define DMA_ERR_ERR0_SHIFT 0
+#define DMA_ERR_ERR1_MASK 0x2u
+#define DMA_ERR_ERR1_SHIFT 1
+#define DMA_ERR_ERR2_MASK 0x4u
+#define DMA_ERR_ERR2_SHIFT 2
+#define DMA_ERR_ERR3_MASK 0x8u
+#define DMA_ERR_ERR3_SHIFT 3
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK 0x1u
+#define DMA_HRS_HRS0_SHIFT 0
+#define DMA_HRS_HRS1_MASK 0x2u
+#define DMA_HRS_HRS1_SHIFT 1
+#define DMA_HRS_HRS2_MASK 0x4u
+#define DMA_HRS_HRS2_SHIFT 2
+#define DMA_HRS_HRS3_MASK 0x8u
+#define DMA_HRS_HRS3_SHIFT 3
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK 0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT 0
+#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK 0x40u
+#define DMA_DCHPRI3_DPA_SHIFT 6
+#define DMA_DCHPRI3_ECP_MASK 0x80u
+#define DMA_DCHPRI3_ECP_SHIFT 7
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK 0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT 0
+#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK 0x40u
+#define DMA_DCHPRI2_DPA_SHIFT 6
+#define DMA_DCHPRI2_ECP_MASK 0x80u
+#define DMA_DCHPRI2_ECP_SHIFT 7
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK 0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT 0
+#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK 0x40u
+#define DMA_DCHPRI1_DPA_SHIFT 6
+#define DMA_DCHPRI1_ECP_MASK 0x80u
+#define DMA_DCHPRI1_ECP_SHIFT 7
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK 0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT 0
+#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK 0x40u
+#define DMA_DCHPRI0_DPA_SHIFT 6
+#define DMA_DCHPRI0_ECP_MASK 0x80u
+#define DMA_DCHPRI0_ECP_SHIFT 7
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT 0
+#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK 0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT 0
+#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK 0x7u
+#define DMA_ATTR_DSIZE_SHIFT 0
+#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK 0xF8u
+#define DMA_ATTR_DMOD_SHIFT 3
+#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK 0x700u
+#define DMA_ATTR_SSIZE_SHIFT 8
+#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK 0xF800u
+#define DMA_ATTR_SMOD_SHIFT 11
+#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
+#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT 0
+#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT 0
+#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK 0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT 0
+#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT 0
+#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT 0
+#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
+#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK 0x1u
+#define DMA_CSR_START_SHIFT 0
+#define DMA_CSR_INTMAJOR_MASK 0x2u
+#define DMA_CSR_INTMAJOR_SHIFT 1
+#define DMA_CSR_INTHALF_MASK 0x4u
+#define DMA_CSR_INTHALF_SHIFT 2
+#define DMA_CSR_DREQ_MASK 0x8u
+#define DMA_CSR_DREQ_SHIFT 3
+#define DMA_CSR_ESG_MASK 0x10u
+#define DMA_CSR_ESG_SHIFT 4
+#define DMA_CSR_MAJORELINK_MASK 0x20u
+#define DMA_CSR_MAJORELINK_SHIFT 5
+#define DMA_CSR_ACTIVE_MASK 0x40u
+#define DMA_CSR_ACTIVE_SHIFT 6
+#define DMA_CSR_DONE_MASK 0x80u
+#define DMA_CSR_DONE_SHIFT 7
+#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT 8
+#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK 0xC000u
+#define DMA_CSR_BWC_SHIFT 14
+#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT 0
+#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT 0
+#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
+
+/**
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+
+/**
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[16]; /**< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
+ __O uint8_t SERV; /**< Service Register, offset: 0x1 */
+ __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
+ __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
+} EWM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- EWM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK 0x1u
+#define EWM_CTRL_EWMEN_SHIFT 0
+#define EWM_CTRL_ASSIN_MASK 0x2u
+#define EWM_CTRL_ASSIN_SHIFT 1
+#define EWM_CTRL_INEN_MASK 0x4u
+#define EWM_CTRL_INEN_SHIFT 2
+#define EWM_CTRL_INTEN_MASK 0x8u
+#define EWM_CTRL_INTEN_SHIFT 3
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK 0xFFu
+#define EWM_SERV_SERVICE_SHIFT 0
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK 0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT 0
+#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK 0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT 0
+#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+
+/**
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM ((EWM_Type *)EWM_BASE)
+
+/**
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
+ __IO uint32_t PFB0CR; /**< Flash Control Register, offset: 0x4 */
+ uint8_t RESERVED_0[248];
+ struct { /* offset: 0x100, array step: 0x20 */
+ __IO uint32_t TAGVD[2]; /**< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
+ uint8_t RESERVED_0[24];
+ } TAG_WAY[4];
+ uint8_t RESERVED_1[132];
+ struct { /* offset: 0x204, array step: 0x8 */
+ __IO uint32_t DATAW0S; /**< Cache Data Storage, array offset: 0x204, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW0S[2];
+ uint8_t RESERVED_2[48];
+ struct { /* offset: 0x244, array step: 0x8 */
+ __IO uint32_t DATAW1S; /**< Cache Data Storage, array offset: 0x244, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW1S[2];
+ uint8_t RESERVED_3[48];
+ struct { /* offset: 0x284, array step: 0x8 */
+ __IO uint32_t DATAW2S; /**< Cache Data Storage, array offset: 0x284, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW2S[2];
+ uint8_t RESERVED_4[48];
+ struct { /* offset: 0x2C4, array step: 0x8 */
+ __IO uint32_t DATAW3S; /**< Cache Data Storage, array offset: 0x2C4, array step: 0x8 */
+ uint8_t RESERVED_0[4];
+ } DATAW3S[2];
+} FMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK 0x3u
+#define FMC_PFAPR_M0AP_SHIFT 0
+#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK 0xCu
+#define FMC_PFAPR_M1AP_SHIFT 2
+#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK 0x30u
+#define FMC_PFAPR_M2AP_SHIFT 4
+#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK 0xC0u
+#define FMC_PFAPR_M3AP_SHIFT 6
+#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK 0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT 16
+#define FMC_PFAPR_M1PFD_MASK 0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT 17
+#define FMC_PFAPR_M2PFD_MASK 0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT 18
+#define FMC_PFAPR_M3PFD_MASK 0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT 19
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK 0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT 0
+#define FMC_PFB0CR_B0IPE_MASK 0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT 1
+#define FMC_PFB0CR_B0DPE_MASK 0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT 2
+#define FMC_PFB0CR_B0ICE_MASK 0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT 3
+#define FMC_PFB0CR_B0DCE_MASK 0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT 4
+#define FMC_PFB0CR_CRC_MASK 0xE0u
+#define FMC_PFB0CR_CRC_SHIFT 5
+#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK 0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT 17
+#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT 19
+#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT 20
+#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
+#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT 28
+#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* TAGVD Bit Fields */
+#define FMC_TAGVD_valid_MASK 0x1u
+#define FMC_TAGVD_valid_SHIFT 0
+#define FMC_TAGVD_tag_MASK 0x7FFC0u
+#define FMC_TAGVD_tag_SHIFT 6
+#define FMC_TAGVD_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
+/* DATAW0S Bit Fields */
+#define FMC_DATAW0S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW0S_data_SHIFT 0
+#define FMC_DATAW0S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW0S_data_SHIFT))&FMC_DATAW0S_data_MASK)
+/* DATAW1S Bit Fields */
+#define FMC_DATAW1S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW1S_data_SHIFT 0
+#define FMC_DATAW1S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW1S_data_SHIFT))&FMC_DATAW1S_data_MASK)
+/* DATAW2S Bit Fields */
+#define FMC_DATAW2S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW2S_data_SHIFT 0
+#define FMC_DATAW2S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW2S_data_SHIFT))&FMC_DATAW2S_data_MASK)
+/* DATAW3S Bit Fields */
+#define FMC_DATAW3S_data_MASK 0xFFFFFFFFu
+#define FMC_DATAW3S_data_SHIFT 0
+#define FMC_DATAW3S_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATAW3S_data_SHIFT))&FMC_DATAW3S_data_MASK)
+
+/**
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC ((FMC_Type *)FMC_BASE)
+
+/**
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFL Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer
+ * @{
+ */
+
+/** FTFL - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
+ __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
+} FTFL_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFL Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFL_Register_Masks FTFL Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFL_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFL_FSTAT_MGSTAT0_SHIFT 0
+#define FTFL_FSTAT_FPVIOL_MASK 0x10u
+#define FTFL_FSTAT_FPVIOL_SHIFT 4
+#define FTFL_FSTAT_ACCERR_MASK 0x20u
+#define FTFL_FSTAT_ACCERR_SHIFT 5
+#define FTFL_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFL_FSTAT_RDCOLERR_SHIFT 6
+#define FTFL_FSTAT_CCIF_MASK 0x80u
+#define FTFL_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFL_FCNFG_EEERDY_MASK 0x1u
+#define FTFL_FCNFG_EEERDY_SHIFT 0
+#define FTFL_FCNFG_RAMRDY_MASK 0x2u
+#define FTFL_FCNFG_RAMRDY_SHIFT 1
+#define FTFL_FCNFG_PFLSH_MASK 0x4u
+#define FTFL_FCNFG_PFLSH_SHIFT 2
+#define FTFL_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFL_FCNFG_ERSSUSP_SHIFT 4
+#define FTFL_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFL_FCNFG_ERSAREQ_SHIFT 5
+#define FTFL_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFL_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFL_FCNFG_CCIE_MASK 0x80u
+#define FTFL_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFL_FSEC_SEC_MASK 0x3u
+#define FTFL_FSEC_SEC_SHIFT 0
+#define FTFL_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
+#define FTFL_FSEC_FSLACC_MASK 0xCu
+#define FTFL_FSEC_FSLACC_SHIFT 2
+#define FTFL_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
+#define FTFL_FSEC_MEEN_MASK 0x30u
+#define FTFL_FSEC_MEEN_SHIFT 4
+#define FTFL_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
+#define FTFL_FSEC_KEYEN_MASK 0xC0u
+#define FTFL_FSEC_KEYEN_SHIFT 6
+#define FTFL_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFL_FOPT_OPT_MASK 0xFFu
+#define FTFL_FOPT_OPT_SHIFT 0
+#define FTFL_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFL_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB3_CCOBn_SHIFT 0
+#define FTFL_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFL_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB2_CCOBn_SHIFT 0
+#define FTFL_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFL_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB1_CCOBn_SHIFT 0
+#define FTFL_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFL_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB0_CCOBn_SHIFT 0
+#define FTFL_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFL_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB7_CCOBn_SHIFT 0
+#define FTFL_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFL_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB6_CCOBn_SHIFT 0
+#define FTFL_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFL_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB5_CCOBn_SHIFT 0
+#define FTFL_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFL_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB4_CCOBn_SHIFT 0
+#define FTFL_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFL_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFL_FCCOBB_CCOBn_SHIFT 0
+#define FTFL_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFL_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFL_FCCOBA_CCOBn_SHIFT 0
+#define FTFL_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFL_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB9_CCOBn_SHIFT 0
+#define FTFL_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFL_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFL_FCCOB8_CCOBn_SHIFT 0
+#define FTFL_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFL_FPROT3_PROT_MASK 0xFFu
+#define FTFL_FPROT3_PROT_SHIFT 0
+#define FTFL_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFL_FPROT2_PROT_MASK 0xFFu
+#define FTFL_FPROT2_PROT_SHIFT 0
+#define FTFL_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFL_FPROT1_PROT_MASK 0xFFu
+#define FTFL_FPROT1_PROT_SHIFT 0
+#define FTFL_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFL_FPROT0_PROT_MASK 0xFFu
+#define FTFL_FPROT0_PROT_SHIFT 0
+#define FTFL_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFL_FEPROT_EPROT_MASK 0xFFu
+#define FTFL_FEPROT_EPROT_SHIFT 0
+#define FTFL_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFL_FDPROT_DPROT_MASK 0xFFu
+#define FTFL_FDPROT_DPROT_SHIFT 0
+#define FTFL_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
+
+/**
+ * @}
+ */ /* end of group FTFL_Register_Masks */
+
+
+/* FTFL - Peripheral instance base addresses */
+/** Peripheral FTFL base address */
+#define FTFL_BASE (0x40020000u)
+/** Peripheral FTFL base pointer */
+#define FTFL ((FTFL_Type *)FTFL_BASE)
+
+/**
+ * @}
+ */ /* end of group FTFL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[8];
+ __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
+ __I uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
+ __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
+ __IO uint32_t OUTINIT; /**< Initial State for Channels Output, offset: 0x5C */
+ __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
+ __IO uint32_t COMBINE; /**< Function for Linked Channels, offset: 0x64 */
+ __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
+ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
+ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
+ __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
+ __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
+ __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
+ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+ __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
+ __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
+ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
+ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
+ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK 0x7u
+#define FTM_SC_PS_SHIFT 0
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK 0x18u
+#define FTM_SC_CLKS_SHIFT 3
+#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK 0x20u
+#define FTM_SC_CPWMS_SHIFT 5
+#define FTM_SC_TOIE_MASK 0x40u
+#define FTM_SC_TOIE_SHIFT 6
+#define FTM_SC_TOF_MASK 0x80u
+#define FTM_SC_TOF_SHIFT 7
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK 0xFFFFu
+#define FTM_CNT_COUNT_SHIFT 0
+#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK 0xFFFFu
+#define FTM_MOD_MOD_SHIFT 0
+#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK 0x1u
+#define FTM_CnSC_DMA_SHIFT 0
+#define FTM_CnSC_ELSA_MASK 0x4u
+#define FTM_CnSC_ELSA_SHIFT 2
+#define FTM_CnSC_ELSB_MASK 0x8u
+#define FTM_CnSC_ELSB_SHIFT 3
+#define FTM_CnSC_MSA_MASK 0x10u
+#define FTM_CnSC_MSA_SHIFT 4
+#define FTM_CnSC_MSB_MASK 0x20u
+#define FTM_CnSC_MSB_SHIFT 5
+#define FTM_CnSC_CHIE_MASK 0x40u
+#define FTM_CnSC_CHIE_SHIFT 6
+#define FTM_CnSC_CHF_MASK 0x80u
+#define FTM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK 0xFFFFu
+#define FTM_CnV_VAL_SHIFT 0
+#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK 0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT 0
+#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK 0x1u
+#define FTM_STATUS_CH0F_SHIFT 0
+#define FTM_STATUS_CH1F_MASK 0x2u
+#define FTM_STATUS_CH1F_SHIFT 1
+#define FTM_STATUS_CH2F_MASK 0x4u
+#define FTM_STATUS_CH2F_SHIFT 2
+#define FTM_STATUS_CH3F_MASK 0x8u
+#define FTM_STATUS_CH3F_SHIFT 3
+#define FTM_STATUS_CH4F_MASK 0x10u
+#define FTM_STATUS_CH4F_SHIFT 4
+#define FTM_STATUS_CH5F_MASK 0x20u
+#define FTM_STATUS_CH5F_SHIFT 5
+#define FTM_STATUS_CH6F_MASK 0x40u
+#define FTM_STATUS_CH6F_SHIFT 6
+#define FTM_STATUS_CH7F_MASK 0x80u
+#define FTM_STATUS_CH7F_SHIFT 7
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK 0x1u
+#define FTM_MODE_FTMEN_SHIFT 0
+#define FTM_MODE_INIT_MASK 0x2u
+#define FTM_MODE_INIT_SHIFT 1
+#define FTM_MODE_WPDIS_MASK 0x4u
+#define FTM_MODE_WPDIS_SHIFT 2
+#define FTM_MODE_PWMSYNC_MASK 0x8u
+#define FTM_MODE_PWMSYNC_SHIFT 3
+#define FTM_MODE_CAPTEST_MASK 0x10u
+#define FTM_MODE_CAPTEST_SHIFT 4
+#define FTM_MODE_FAULTM_MASK 0x60u
+#define FTM_MODE_FAULTM_SHIFT 5
+#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK 0x80u
+#define FTM_MODE_FAULTIE_SHIFT 7
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK 0x1u
+#define FTM_SYNC_CNTMIN_SHIFT 0
+#define FTM_SYNC_CNTMAX_MASK 0x2u
+#define FTM_SYNC_CNTMAX_SHIFT 1
+#define FTM_SYNC_REINIT_MASK 0x4u
+#define FTM_SYNC_REINIT_SHIFT 2
+#define FTM_SYNC_SYNCHOM_MASK 0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT 3
+#define FTM_SYNC_TRIG0_MASK 0x10u
+#define FTM_SYNC_TRIG0_SHIFT 4
+#define FTM_SYNC_TRIG1_MASK 0x20u
+#define FTM_SYNC_TRIG1_SHIFT 5
+#define FTM_SYNC_TRIG2_MASK 0x40u
+#define FTM_SYNC_TRIG2_SHIFT 6
+#define FTM_SYNC_SWSYNC_MASK 0x80u
+#define FTM_SYNC_SWSYNC_SHIFT 7
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK 0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT 0
+#define FTM_OUTINIT_CH1OI_MASK 0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT 1
+#define FTM_OUTINIT_CH2OI_MASK 0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT 2
+#define FTM_OUTINIT_CH3OI_MASK 0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT 3
+#define FTM_OUTINIT_CH4OI_MASK 0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT 4
+#define FTM_OUTINIT_CH5OI_MASK 0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT 5
+#define FTM_OUTINIT_CH6OI_MASK 0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT 6
+#define FTM_OUTINIT_CH7OI_MASK 0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT 7
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK 0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT 0
+#define FTM_OUTMASK_CH1OM_MASK 0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT 1
+#define FTM_OUTMASK_CH2OM_MASK 0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT 2
+#define FTM_OUTMASK_CH3OM_MASK 0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT 3
+#define FTM_OUTMASK_CH4OM_MASK 0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT 4
+#define FTM_OUTMASK_CH5OM_MASK 0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT 5
+#define FTM_OUTMASK_CH6OM_MASK 0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT 6
+#define FTM_OUTMASK_CH7OM_MASK 0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT 7
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK 0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT 0
+#define FTM_COMBINE_COMP0_MASK 0x2u
+#define FTM_COMBINE_COMP0_SHIFT 1
+#define FTM_COMBINE_DECAPEN0_MASK 0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT 2
+#define FTM_COMBINE_DECAP0_MASK 0x8u
+#define FTM_COMBINE_DECAP0_SHIFT 3
+#define FTM_COMBINE_DTEN0_MASK 0x10u
+#define FTM_COMBINE_DTEN0_SHIFT 4
+#define FTM_COMBINE_SYNCEN0_MASK 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT 5
+#define FTM_COMBINE_FAULTEN0_MASK 0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT 6
+#define FTM_COMBINE_COMBINE1_MASK 0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT 8
+#define FTM_COMBINE_COMP1_MASK 0x200u
+#define FTM_COMBINE_COMP1_SHIFT 9
+#define FTM_COMBINE_DECAPEN1_MASK 0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT 10
+#define FTM_COMBINE_DECAP1_MASK 0x800u
+#define FTM_COMBINE_DECAP1_SHIFT 11
+#define FTM_COMBINE_DTEN1_MASK 0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT 12
+#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT 13
+#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT 14
+#define FTM_COMBINE_COMBINE2_MASK 0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT 16
+#define FTM_COMBINE_COMP2_MASK 0x20000u
+#define FTM_COMBINE_COMP2_SHIFT 17
+#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT 18
+#define FTM_COMBINE_DECAP2_MASK 0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT 19
+#define FTM_COMBINE_DTEN2_MASK 0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT 20
+#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT 21
+#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT 22
+#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT 24
+#define FTM_COMBINE_COMP3_MASK 0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT 25
+#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT 26
+#define FTM_COMBINE_DECAP3_MASK 0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT 27
+#define FTM_COMBINE_DTEN3_MASK 0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT 28
+#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT 29
+#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT 30
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT 0
+#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK 0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT 6
+#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
+#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
+#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
+#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
+#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
+#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
+#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
+#define FTM_EXTTRIG_TRIGF_MASK 0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT 7
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK 0x1u
+#define FTM_POL_POL0_SHIFT 0
+#define FTM_POL_POL1_MASK 0x2u
+#define FTM_POL_POL1_SHIFT 1
+#define FTM_POL_POL2_MASK 0x4u
+#define FTM_POL_POL2_SHIFT 2
+#define FTM_POL_POL3_MASK 0x8u
+#define FTM_POL_POL3_SHIFT 3
+#define FTM_POL_POL4_MASK 0x10u
+#define FTM_POL_POL4_SHIFT 4
+#define FTM_POL_POL5_MASK 0x20u
+#define FTM_POL_POL5_SHIFT 5
+#define FTM_POL_POL6_MASK 0x40u
+#define FTM_POL_POL6_SHIFT 6
+#define FTM_POL_POL7_MASK 0x80u
+#define FTM_POL_POL7_SHIFT 7
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK 0x1u
+#define FTM_FMS_FAULTF0_SHIFT 0
+#define FTM_FMS_FAULTF1_MASK 0x2u
+#define FTM_FMS_FAULTF1_SHIFT 1
+#define FTM_FMS_FAULTF2_MASK 0x4u
+#define FTM_FMS_FAULTF2_SHIFT 2
+#define FTM_FMS_FAULTF3_MASK 0x8u
+#define FTM_FMS_FAULTF3_SHIFT 3
+#define FTM_FMS_FAULTIN_MASK 0x20u
+#define FTM_FMS_FAULTIN_SHIFT 5
+#define FTM_FMS_WPEN_MASK 0x40u
+#define FTM_FMS_WPEN_SHIFT 6
+#define FTM_FMS_FAULTF_MASK 0x80u
+#define FTM_FMS_FAULTF_SHIFT 7
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK 0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT 0
+#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK 0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT 4
+#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK 0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT 8
+#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK 0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT 12
+#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
+#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
+#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
+#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
+#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
+#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
+#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
+#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
+#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT 8
+#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK 0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT 0
+#define FTM_QDCTRL_TOFDIR_MASK 0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT 1
+#define FTM_QDCTRL_QUADIR_MASK 0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT 2
+#define FTM_QDCTRL_QUADMODE_MASK 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT 3
+#define FTM_QDCTRL_PHBPOL_MASK 0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT 4
+#define FTM_QDCTRL_PHAPOL_MASK 0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT 5
+#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
+#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK 0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT 0
+#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK 0xC0u
+#define FTM_CONF_BDMMODE_SHIFT 6
+#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK 0x200u
+#define FTM_CONF_GTBEEN_SHIFT 9
+#define FTM_CONF_GTBEOUT_MASK 0x400u
+#define FTM_CONF_GTBEOUT_SHIFT 10
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK 0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT 0
+#define FTM_FLTPOL_FLT1POL_MASK 0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT 1
+#define FTM_FLTPOL_FLT2POL_MASK 0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT 2
+#define FTM_FLTPOL_FLT3POL_MASK 0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT 3
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
+#define FTM_SYNCONF_CNTINC_MASK 0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT 2
+#define FTM_SYNCONF_INVC_MASK 0x10u
+#define FTM_SYNCONF_INVC_SHIFT 4
+#define FTM_SYNCONF_SWOC_MASK 0x20u
+#define FTM_SYNCONF_SWOC_SHIFT 5
+#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT 7
+#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
+#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT 9
+#define FTM_SYNCONF_SWOM_MASK 0x400u
+#define FTM_SYNCONF_SWOM_SHIFT 10
+#define FTM_SYNCONF_SWINVC_MASK 0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT 11
+#define FTM_SYNCONF_SWSOC_MASK 0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT 12
+#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
+#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT 17
+#define FTM_SYNCONF_HWOM_MASK 0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT 18
+#define FTM_SYNCONF_HWINVC_MASK 0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT 19
+#define FTM_SYNCONF_HWSOC_MASK 0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT 20
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK 0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT 0
+#define FTM_INVCTRL_INV1EN_MASK 0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT 1
+#define FTM_INVCTRL_INV2EN_MASK 0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT 2
+#define FTM_INVCTRL_INV3EN_MASK 0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT 3
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK 0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT 0
+#define FTM_SWOCTRL_CH1OC_MASK 0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT 1
+#define FTM_SWOCTRL_CH2OC_MASK 0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT 2
+#define FTM_SWOCTRL_CH3OC_MASK 0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT 3
+#define FTM_SWOCTRL_CH4OC_MASK 0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT 4
+#define FTM_SWOCTRL_CH5OC_MASK 0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT 5
+#define FTM_SWOCTRL_CH6OC_MASK 0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT 6
+#define FTM_SWOCTRL_CH7OC_MASK 0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT 7
+#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT 8
+#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT 9
+#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT 10
+#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT 11
+#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT 12
+#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT 13
+#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT 14
+#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT 15
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT 0
+#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT 1
+#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT 2
+#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT 3
+#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT 4
+#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT 5
+#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT 6
+#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT 7
+#define FTM_PWMLOAD_LDOK_MASK 0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT 9
+
+/**
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0 ((FTM_Type *)FTM0_BASE)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1 ((FTM_Type *)FTM1_BASE)
+
+/**
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+
+/**
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status Register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0x1Fu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+/**
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[24];
+ __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_2[24];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_4[8];
+ __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_5[24];
+ __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_6[24];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+ __IO uint32_t MDR; /**< MCLK Divide Register, offset: 0x104 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK 0x1u
+#define I2S_TCSR_FRDE_SHIFT 0
+#define I2S_TCSR_FWDE_MASK 0x2u
+#define I2S_TCSR_FWDE_SHIFT 1
+#define I2S_TCSR_FRIE_MASK 0x100u
+#define I2S_TCSR_FRIE_SHIFT 8
+#define I2S_TCSR_FWIE_MASK 0x200u
+#define I2S_TCSR_FWIE_SHIFT 9
+#define I2S_TCSR_FEIE_MASK 0x400u
+#define I2S_TCSR_FEIE_SHIFT 10
+#define I2S_TCSR_SEIE_MASK 0x800u
+#define I2S_TCSR_SEIE_SHIFT 11
+#define I2S_TCSR_WSIE_MASK 0x1000u
+#define I2S_TCSR_WSIE_SHIFT 12
+#define I2S_TCSR_FRF_MASK 0x10000u
+#define I2S_TCSR_FRF_SHIFT 16
+#define I2S_TCSR_FWF_MASK 0x20000u
+#define I2S_TCSR_FWF_SHIFT 17
+#define I2S_TCSR_FEF_MASK 0x40000u
+#define I2S_TCSR_FEF_SHIFT 18
+#define I2S_TCSR_SEF_MASK 0x80000u
+#define I2S_TCSR_SEF_SHIFT 19
+#define I2S_TCSR_WSF_MASK 0x100000u
+#define I2S_TCSR_WSF_SHIFT 20
+#define I2S_TCSR_SR_MASK 0x1000000u
+#define I2S_TCSR_SR_SHIFT 24
+#define I2S_TCSR_FR_MASK 0x2000000u
+#define I2S_TCSR_FR_SHIFT 25
+#define I2S_TCSR_BCE_MASK 0x10000000u
+#define I2S_TCSR_BCE_SHIFT 28
+#define I2S_TCSR_DBGE_MASK 0x20000000u
+#define I2S_TCSR_DBGE_SHIFT 29
+#define I2S_TCSR_STOPE_MASK 0x40000000u
+#define I2S_TCSR_STOPE_SHIFT 30
+#define I2S_TCSR_TE_MASK 0x80000000u
+#define I2S_TCSR_TE_SHIFT 31
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK 0x7u
+#define I2S_TCR1_TFW_SHIFT 0
+#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK 0xFFu
+#define I2S_TCR2_DIV_SHIFT 0
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK 0x1000000u
+#define I2S_TCR2_BCD_SHIFT 24
+#define I2S_TCR2_BCP_MASK 0x2000000u
+#define I2S_TCR2_BCP_SHIFT 25
+#define I2S_TCR2_MSEL_MASK 0xC000000u
+#define I2S_TCR2_MSEL_SHIFT 26
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK 0x10000000u
+#define I2S_TCR2_BCI_SHIFT 28
+#define I2S_TCR2_BCS_MASK 0x20000000u
+#define I2S_TCR2_BCS_SHIFT 29
+#define I2S_TCR2_SYNC_MASK 0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT 30
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK 0x1Fu
+#define I2S_TCR3_WDFL_SHIFT 0
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK 0x30000u
+#define I2S_TCR3_TCE_SHIFT 16
+#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK 0x1u
+#define I2S_TCR4_FSD_SHIFT 0
+#define I2S_TCR4_FSP_MASK 0x2u
+#define I2S_TCR4_FSP_SHIFT 1
+#define I2S_TCR4_FSE_MASK 0x8u
+#define I2S_TCR4_FSE_SHIFT 3
+#define I2S_TCR4_MF_MASK 0x10u
+#define I2S_TCR4_MF_SHIFT 4
+#define I2S_TCR4_SYWD_MASK 0x1F00u
+#define I2S_TCR4_SYWD_SHIFT 8
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK 0x1F0000u
+#define I2S_TCR4_FRSZ_SHIFT 16
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK 0x1F00u
+#define I2S_TCR5_FBT_SHIFT 8
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK 0x1F0000u
+#define I2S_TCR5_W0W_SHIFT 16
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK 0x1F000000u
+#define I2S_TCR5_WNW_SHIFT 24
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT 0
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK 0xFu
+#define I2S_TFR_RFP_SHIFT 0
+#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK 0xF0000u
+#define I2S_TFR_WFP_SHIFT 16
+#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK 0xFFFFFFFFu
+#define I2S_TMR_TWM_SHIFT 0
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK 0x1u
+#define I2S_RCSR_FRDE_SHIFT 0
+#define I2S_RCSR_FWDE_MASK 0x2u
+#define I2S_RCSR_FWDE_SHIFT 1
+#define I2S_RCSR_FRIE_MASK 0x100u
+#define I2S_RCSR_FRIE_SHIFT 8
+#define I2S_RCSR_FWIE_MASK 0x200u
+#define I2S_RCSR_FWIE_SHIFT 9
+#define I2S_RCSR_FEIE_MASK 0x400u
+#define I2S_RCSR_FEIE_SHIFT 10
+#define I2S_RCSR_SEIE_MASK 0x800u
+#define I2S_RCSR_SEIE_SHIFT 11
+#define I2S_RCSR_WSIE_MASK 0x1000u
+#define I2S_RCSR_WSIE_SHIFT 12
+#define I2S_RCSR_FRF_MASK 0x10000u
+#define I2S_RCSR_FRF_SHIFT 16
+#define I2S_RCSR_FWF_MASK 0x20000u
+#define I2S_RCSR_FWF_SHIFT 17
+#define I2S_RCSR_FEF_MASK 0x40000u
+#define I2S_RCSR_FEF_SHIFT 18
+#define I2S_RCSR_SEF_MASK 0x80000u
+#define I2S_RCSR_SEF_SHIFT 19
+#define I2S_RCSR_WSF_MASK 0x100000u
+#define I2S_RCSR_WSF_SHIFT 20
+#define I2S_RCSR_SR_MASK 0x1000000u
+#define I2S_RCSR_SR_SHIFT 24
+#define I2S_RCSR_FR_MASK 0x2000000u
+#define I2S_RCSR_FR_SHIFT 25
+#define I2S_RCSR_BCE_MASK 0x10000000u
+#define I2S_RCSR_BCE_SHIFT 28
+#define I2S_RCSR_DBGE_MASK 0x20000000u
+#define I2S_RCSR_DBGE_SHIFT 29
+#define I2S_RCSR_STOPE_MASK 0x40000000u
+#define I2S_RCSR_STOPE_SHIFT 30
+#define I2S_RCSR_RE_MASK 0x80000000u
+#define I2S_RCSR_RE_SHIFT 31
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK 0x7u
+#define I2S_RCR1_RFW_SHIFT 0
+#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK 0xFFu
+#define I2S_RCR2_DIV_SHIFT 0
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK 0x1000000u
+#define I2S_RCR2_BCD_SHIFT 24
+#define I2S_RCR2_BCP_MASK 0x2000000u
+#define I2S_RCR2_BCP_SHIFT 25
+#define I2S_RCR2_MSEL_MASK 0xC000000u
+#define I2S_RCR2_MSEL_SHIFT 26
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK 0x10000000u
+#define I2S_RCR2_BCI_SHIFT 28
+#define I2S_RCR2_BCS_MASK 0x20000000u
+#define I2S_RCR2_BCS_SHIFT 29
+#define I2S_RCR2_SYNC_MASK 0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT 30
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK 0x1Fu
+#define I2S_RCR3_WDFL_SHIFT 0
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK 0x30000u
+#define I2S_RCR3_RCE_SHIFT 16
+#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK 0x1u
+#define I2S_RCR4_FSD_SHIFT 0
+#define I2S_RCR4_FSP_MASK 0x2u
+#define I2S_RCR4_FSP_SHIFT 1
+#define I2S_RCR4_FSE_MASK 0x8u
+#define I2S_RCR4_FSE_SHIFT 3
+#define I2S_RCR4_MF_MASK 0x10u
+#define I2S_RCR4_MF_SHIFT 4
+#define I2S_RCR4_SYWD_MASK 0x1F00u
+#define I2S_RCR4_SYWD_SHIFT 8
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK 0x1F0000u
+#define I2S_RCR4_FRSZ_SHIFT 16
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK 0x1F00u
+#define I2S_RCR5_FBT_SHIFT 8
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK 0x1F0000u
+#define I2S_RCR5_W0W_SHIFT 16
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK 0x1F000000u
+#define I2S_RCR5_WNW_SHIFT 24
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT 0
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK 0xFu
+#define I2S_RFR_RFP_SHIFT 0
+#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK 0xF0000u
+#define I2S_RFR_WFP_SHIFT 16
+#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK 0xFFFFFFFFu
+#define I2S_RMR_RWM_SHIFT 0
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK 0x3000000u
+#define I2S_MCR_MICS_SHIFT 24
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK 0x40000000u
+#define I2S_MCR_MOE_SHIFT 30
+#define I2S_MCR_DUF_MASK 0x80000000u
+#define I2S_MCR_DUF_SHIFT 31
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK 0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT 0
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK 0xFF000u
+#define I2S_MDR_FRACT_SHIFT 12
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+
+/**
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 Register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 Register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 Register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 Register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable Register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 Register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 Register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 Register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 Register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 Register, offset: 0x9 */
+ __IO uint8_t RST; /**< LLWU Reset Enable Register, offset: 0xA */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+/* RST Bit Fields */
+#define LLWU_RST_RSTFILT_MASK 0x1u
+#define LLWU_RST_RSTFILT_SHIFT 0
+#define LLWU_RST_LLRSTE_MASK 0x2u
+#define LLWU_RST_LLRSTE_SHIFT 1
+
+/**
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+
+/**
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/**
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+
+/**
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS0_MASK 0x4u
+#define MCG_C2_EREFS0_SHIFT 2
+#define MCG_C2_HGO0_MASK 0x8u
+#define MCG_C2_HGO0_SHIFT 3
+#define MCG_C2_RANGE0_MASK 0x30u
+#define MCG_C2_RANGE0_SHIFT 4
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK 0x1Fu
+#define MCG_C5_PRDIV0_SHIFT 0
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK 0x20u
+#define MCG_C5_PLLSTEN0_SHIFT 5
+#define MCG_C5_PLLCLKEN0_MASK 0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT 6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK 0x1Fu
+#define MCG_C6_VDIV0_SHIFT 0
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK 0x20u
+#define MCG_C6_CME0_SHIFT 5
+#define MCG_C6_PLLS_MASK 0x40u
+#define MCG_C6_PLLS_SHIFT 6
+#define MCG_C6_LOLIE0_MASK 0x80u
+#define MCG_C6_LOLIE0_SHIFT 7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+#define MCG_S_PLLST_MASK 0x20u
+#define MCG_S_PLLST_SHIFT 5
+#define MCG_S_LOCK0_MASK 0x40u
+#define MCG_S_LOCK0_SHIFT 6
+#define MCG_S_LOLS0_MASK 0x80u
+#define MCG_S_LOLS0_SHIFT 7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK 0x1u
+#define MCG_C7_OSCSEL_SHIFT 0
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK 0x1u
+#define MCG_C8_LOCS1_SHIFT 0
+#define MCG_C8_CME1_MASK 0x20u
+#define MCG_C8_CME1_SHIFT 5
+#define MCG_C8_LOLRE_MASK 0x40u
+#define MCG_C8_LOLRE_SHIFT 6
+#define MCG_C8_LOCRE1_MASK 0x80u
+#define MCG_C8_LOCRE1_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+
+/**
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+ __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
+ __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK 0x1u
+#define NV_FOPT_LPBOOT_SHIFT 0
+#define NV_FOPT_EZPORT_DIS_MASK 0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT 1
+/* FEPROT Bit Fields */
+#define NV_FEPROT_EPROT_MASK 0xFFu
+#define NV_FEPROT_EPROT_SHIFT 0
+#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define NV_FDPROT_DPROT_MASK 0xFFu
+#define NV_FDPROT_DPROT_SHIFT 0
+#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+
+/**
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFL_FlashConfig base address */
+#define FTFL_FlashConfig_BASE (0x400u)
+/** Peripheral FTFL_FlashConfig base pointer */
+#define FTFL_FlashConfig ((NV_Type *)FTFL_FlashConfig_BASE)
+
+/**
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+
+/**
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control Register, offset: 0x0 */
+ __IO uint32_t MOD; /**< Modulus Register, offset: 0x4 */
+ __I uint32_t CNT; /**< Counter Register, offset: 0x8 */
+ __IO uint32_t IDLY; /**< Interrupt Delay Register, offset: 0xC */
+ struct { /* offset: 0x10, array step: 0x10 */
+ __IO uint32_t C1; /**< Channel n Control Register 1, array offset: 0x10, array step: 0x10 */
+ __IO uint32_t S; /**< Channel n Status Register, array offset: 0x14, array step: 0x10 */
+ __IO uint32_t DLY[2]; /**< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x10, index2*0x4 */
+ } CH[1];
+ uint8_t RESERVED_0[368];
+ __IO uint32_t POEN; /**< Pulse-Out n Enable Register, offset: 0x190 */
+ __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 */
+} PDB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PDB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK 0x1u
+#define PDB_SC_LDOK_SHIFT 0
+#define PDB_SC_CONT_MASK 0x2u
+#define PDB_SC_CONT_SHIFT 1
+#define PDB_SC_MULT_MASK 0xCu
+#define PDB_SC_MULT_SHIFT 2
+#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK 0x20u
+#define PDB_SC_PDBIE_SHIFT 5
+#define PDB_SC_PDBIF_MASK 0x40u
+#define PDB_SC_PDBIF_SHIFT 6
+#define PDB_SC_PDBEN_MASK 0x80u
+#define PDB_SC_PDBEN_SHIFT 7
+#define PDB_SC_TRGSEL_MASK 0xF00u
+#define PDB_SC_TRGSEL_SHIFT 8
+#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK 0x7000u
+#define PDB_SC_PRESCALER_SHIFT 12
+#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK 0x8000u
+#define PDB_SC_DMAEN_SHIFT 15
+#define PDB_SC_SWTRIG_MASK 0x10000u
+#define PDB_SC_SWTRIG_SHIFT 16
+#define PDB_SC_PDBEIE_MASK 0x20000u
+#define PDB_SC_PDBEIE_SHIFT 17
+#define PDB_SC_LDMOD_MASK 0xC0000u
+#define PDB_SC_LDMOD_SHIFT 18
+#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK 0xFFFFu
+#define PDB_MOD_MOD_SHIFT 0
+#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK 0xFFFFu
+#define PDB_CNT_CNT_SHIFT 0
+#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK 0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT 0
+#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK 0xFFu
+#define PDB_C1_EN_SHIFT 0
+#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK 0xFF00u
+#define PDB_C1_TOS_SHIFT 8
+#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK 0xFF0000u
+#define PDB_C1_BB_SHIFT 16
+#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK 0xFFu
+#define PDB_S_ERR_SHIFT 0
+#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK 0xFF0000u
+#define PDB_S_CF_SHIFT 16
+#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK 0xFFFFu
+#define PDB_DLY_DLY_SHIFT 0
+#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK 0xFFu
+#define PDB_POEN_POEN_SHIFT 0
+#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK 0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT 0
+#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT 16
+#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/**
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0 ((PDB_Type *)PDB0_BASE)
+
+/**
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[252];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[4];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/**
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+
+/**
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status and Control Register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+
+/**
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+
+/**
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
+ __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
+ __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_ODE_MASK 0x20u
+#define PORT_PCR_ODE_SHIFT 5
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK 0x8000u
+#define PORT_PCR_LK_SHIFT 15
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT 0
+#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK 0x1u
+#define PORT_DFCR_CS_SHIFT 0
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK 0x1Fu
+#define PORT_DFWR_FILT_SHIFT 0
+#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/**
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+
+/**
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control Register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width Register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __I uint8_t MR; /**< Mode Register, offset: 0x7 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_LOL_MASK 0x8u
+#define RCM_SRS0_LOL_SHIFT 3
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK 0x1u
+#define RCM_SRS1_JTAG_SHIFT 0
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_EZPT_MASK 0x10u
+#define RCM_SRS1_EZPT_SHIFT 4
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK 0x2u
+#define RCM_MR_EZP_MS_SHIFT 1
+
+/**
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+
+/**
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK 0xFFu
+#define RFSYS_REG_LL_SHIFT 0
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK 0xFF00u
+#define RFSYS_REG_LH_SHIFT 8
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK 0xFF0000u
+#define RFSYS_REG_HL_SHIFT 16
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK 0xFF000000u
+#define RFSYS_REG_HH_SHIFT 24
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/**
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
+
+/**
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK 0xFFu
+#define RFVBAT_REG_LL_SHIFT 0
+#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK 0xFF00u
+#define RFVBAT_REG_LH_SHIFT 8
+#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK 0xFF0000u
+#define RFVBAT_REG_HL_SHIFT 16
+#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK 0xFF000000u
+#define RFVBAT_REG_HH_SHIFT 24
+#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/**
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
+
+/**
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+ uint8_t RESERVED_0[2016];
+ __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
+ __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK 0x1u
+#define RTC_WAR_TSRW_SHIFT 0
+#define RTC_WAR_TPRW_MASK 0x2u
+#define RTC_WAR_TPRW_SHIFT 1
+#define RTC_WAR_TARW_MASK 0x4u
+#define RTC_WAR_TARW_SHIFT 2
+#define RTC_WAR_TCRW_MASK 0x8u
+#define RTC_WAR_TCRW_SHIFT 3
+#define RTC_WAR_CRW_MASK 0x10u
+#define RTC_WAR_CRW_SHIFT 4
+#define RTC_WAR_SRW_MASK 0x20u
+#define RTC_WAR_SRW_SHIFT 5
+#define RTC_WAR_LRW_MASK 0x40u
+#define RTC_WAR_LRW_SHIFT 6
+#define RTC_WAR_IERW_MASK 0x80u
+#define RTC_WAR_IERW_SHIFT 7
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK 0x1u
+#define RTC_RAR_TSRR_SHIFT 0
+#define RTC_RAR_TPRR_MASK 0x2u
+#define RTC_RAR_TPRR_SHIFT 1
+#define RTC_RAR_TARR_MASK 0x4u
+#define RTC_RAR_TARR_SHIFT 2
+#define RTC_RAR_TCRR_MASK 0x8u
+#define RTC_RAR_TCRR_SHIFT 3
+#define RTC_RAR_CRR_MASK 0x10u
+#define RTC_RAR_CRR_SHIFT 4
+#define RTC_RAR_SRR_MASK 0x20u
+#define RTC_RAR_SRR_SHIFT 5
+#define RTC_RAR_LRR_MASK 0x40u
+#define RTC_RAR_LRR_SHIFT 6
+#define RTC_RAR_IERR_MASK 0x80u
+#define RTC_RAR_IERR_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+
+/**
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
+ __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
+ __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT 12
+#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_PTD7PAD_MASK 0x800u
+#define SIM_SOPT2_PTD7PAD_SHIFT 11
+#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
+#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT 0
+#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT 1
+#define SIM_SOPT4_FTM0FLT2_MASK 0x4u
+#define SIM_SOPT4_FTM0FLT2_SHIFT 2
+#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT 4
+#define SIM_SOPT4_FTM2FLT0_MASK 0x100u
+#define SIM_SOPT4_FTM2FLT0_SHIFT 8
+#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
+#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
+#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
+#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x1u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK 0x10u
+#define SIM_SOPT5_UART1TXSRC_SHIFT 4
+#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT 6
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
+#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK 0x70u
+#define SIM_SDID_FAMID_SHIFT 4
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+/* SCGC2 Bit Fields */
+#define SIM_SCGC2_DAC0_MASK 0x1000u
+#define SIM_SCGC2_DAC0_SHIFT 12
+/* SCGC3 Bit Fields */
+#define SIM_SCGC3_FTM2_MASK 0x1000000u
+#define SIM_SCGC3_FTM2_SHIFT 24
+#define SIM_SCGC3_ADC1_MASK 0x8000000u
+#define SIM_SCGC3_ADC1_SHIFT 27
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK 0x2u
+#define SIM_SCGC4_EWM_SHIFT 1
+#define SIM_SCGC4_CMT_MASK 0x4u
+#define SIM_SCGC4_CMT_SHIFT 2
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_I2C1_MASK 0x80u
+#define SIM_SCGC4_I2C1_SHIFT 7
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_UART1_MASK 0x800u
+#define SIM_SCGC4_UART1_SHIFT 11
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_USBOTG_MASK 0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT 18
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_VREF_MASK 0x100000u
+#define SIM_SCGC4_VREF_SHIFT 20
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTIMER_MASK 0x1u
+#define SIM_SCGC5_LPTIMER_SHIFT 0
+#define SIM_SCGC5_TSI_MASK 0x20u
+#define SIM_SCGC5_TSI_SHIFT 5
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTFL_MASK 0x1u
+#define SIM_SCGC6_FTFL_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_FLEXCAN0_MASK 0x10u
+#define SIM_SCGC6_FLEXCAN0_SHIFT 4
+#define SIM_SCGC6_SPI0_MASK 0x1000u
+#define SIM_SCGC6_SPI0_SHIFT 12
+#define SIM_SCGC6_SPI1_MASK 0x2000u
+#define SIM_SCGC6_SPI1_SHIFT 13
+#define SIM_SCGC6_I2S_MASK 0x8000u
+#define SIM_SCGC6_I2S_SHIFT 15
+#define SIM_SCGC6_CRC_MASK 0x40000u
+#define SIM_SCGC6_CRC_SHIFT 18
+#define SIM_SCGC6_USBDCD_MASK 0x200000u
+#define SIM_SCGC6_USBDCD_SHIFT 21
+#define SIM_SCGC6_PDB_MASK 0x400000u
+#define SIM_SCGC6_PDB_SHIFT 22
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_FTM0_MASK 0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT 24
+#define SIM_SCGC6_FTM1_MASK 0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT 25
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK 0x2u
+#define SIM_SCGC7_DMA_SHIFT 1
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
+#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT 0
+#define SIM_CLKDIV2_USBDIV_MASK 0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT 1
+#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_DEPART_MASK 0xF00u
+#define SIM_FCFG1_DEPART_SHIFT 8
+#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK 0xF0000u
+#define SIM_FCFG1_EESIZE_SHIFT 16
+#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
+#define SIM_FCFG1_NVMSIZE_SHIFT 28
+#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT 16
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK 0x800000u
+#define SIM_FCFG2_PFLSH_SHIFT 23
+#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT 24
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT 0
+#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/**
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+
+/**
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection Register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control Register, offset: 0x1 */
+ __IO uint8_t VLLSCTRL; /**< VLLS Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status Register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI_MASK 0x80u
+#define SMC_PMCTRL_LPWUI_SHIFT 7
+/* VLLSCTRL Bit Fields */
+#define SMC_VLLSCTRL_VLLSM_MASK 0x7u
+#define SMC_VLLSCTRL_VLLSM_SHIFT 0
+#define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO_MASK 0x20u
+#define SMC_VLLSCTRL_PORPO_SHIFT 5
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/**
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+
+/**
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */
+ union { /* offset: 0xC */
+ __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+ __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+ };
+ uint8_t RESERVED_1[24];
+ __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */
+ __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+ union { /* offset: 0x34 */
+ __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+ __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+ };
+ __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */
+ __I uint32_t TXFR0; /**< DSPI Transmit FIFO Registers, offset: 0x3C */
+ __I uint32_t TXFR1; /**< DSPI Transmit FIFO Registers, offset: 0x40 */
+ __I uint32_t TXFR2; /**< DSPI Transmit FIFO Registers, offset: 0x44 */
+ __I uint32_t TXFR3; /**< DSPI Transmit FIFO Registers, offset: 0x48 */
+ uint8_t RESERVED_2[48];
+ __I uint32_t RXFR0; /**< DSPI Receive FIFO Registers, offset: 0x7C */
+ __I uint32_t RXFR1; /**< DSPI Receive FIFO Registers, offset: 0x80 */
+ __I uint32_t RXFR2; /**< DSPI Receive FIFO Registers, offset: 0x84 */
+ __I uint32_t RXFR3; /**< DSPI Receive FIFO Registers, offset: 0x88 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK 0x1u
+#define SPI_MCR_HALT_SHIFT 0
+#define SPI_MCR_SMPL_PT_MASK 0x300u
+#define SPI_MCR_SMPL_PT_SHIFT 8
+#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK 0x400u
+#define SPI_MCR_CLR_RXF_SHIFT 10
+#define SPI_MCR_CLR_TXF_MASK 0x800u
+#define SPI_MCR_CLR_TXF_SHIFT 11
+#define SPI_MCR_DIS_RXF_MASK 0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT 12
+#define SPI_MCR_DIS_TXF_MASK 0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT 13
+#define SPI_MCR_MDIS_MASK 0x4000u
+#define SPI_MCR_MDIS_SHIFT 14
+#define SPI_MCR_DOZE_MASK 0x8000u
+#define SPI_MCR_DOZE_SHIFT 15
+#define SPI_MCR_PCSIS_MASK 0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT 16
+#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK 0x1000000u
+#define SPI_MCR_ROOE_SHIFT 24
+#define SPI_MCR_PCSSE_MASK 0x2000000u
+#define SPI_MCR_PCSSE_SHIFT 25
+#define SPI_MCR_MTFE_MASK 0x4000000u
+#define SPI_MCR_MTFE_SHIFT 26
+#define SPI_MCR_FRZ_MASK 0x8000000u
+#define SPI_MCR_FRZ_SHIFT 27
+#define SPI_MCR_DCONF_MASK 0x30000000u
+#define SPI_MCR_DCONF_SHIFT 28
+#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT 30
+#define SPI_MCR_MSTR_MASK 0x80000000u
+#define SPI_MCR_MSTR_SHIFT 31
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT 16
+#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK 0xFu
+#define SPI_CTAR_BR_SHIFT 0
+#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK 0xF0u
+#define SPI_CTAR_DT_SHIFT 4
+#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK 0xF00u
+#define SPI_CTAR_ASC_SHIFT 8
+#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK 0xF000u
+#define SPI_CTAR_CSSCK_SHIFT 12
+#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK 0x30000u
+#define SPI_CTAR_PBR_SHIFT 16
+#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK 0xC0000u
+#define SPI_CTAR_PDT_SHIFT 18
+#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK 0x300000u
+#define SPI_CTAR_PASC_SHIFT 20
+#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK 0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT 22
+#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK 0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT 24
+#define SPI_CTAR_CPHA_MASK 0x2000000u
+#define SPI_CTAR_CPHA_SHIFT 25
+#define SPI_CTAR_CPOL_MASK 0x4000000u
+#define SPI_CTAR_CPOL_SHIFT 26
+#define SPI_CTAR_FMSZ_MASK 0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT 27
+#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK 0x80000000u
+#define SPI_CTAR_DBR_SHIFT 31
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
+#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
+#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
+#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK 0xFu
+#define SPI_SR_POPNXTPTR_SHIFT 0
+#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK 0xF0u
+#define SPI_SR_RXCTR_SHIFT 4
+#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK 0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT 8
+#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK 0xF000u
+#define SPI_SR_TXCTR_SHIFT 12
+#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK 0x20000u
+#define SPI_SR_RFDF_SHIFT 17
+#define SPI_SR_RFOF_MASK 0x80000u
+#define SPI_SR_RFOF_SHIFT 19
+#define SPI_SR_TFFF_MASK 0x2000000u
+#define SPI_SR_TFFF_SHIFT 25
+#define SPI_SR_TFUF_MASK 0x8000000u
+#define SPI_SR_TFUF_SHIFT 27
+#define SPI_SR_EOQF_MASK 0x10000000u
+#define SPI_SR_EOQF_SHIFT 28
+#define SPI_SR_TXRXS_MASK 0x40000000u
+#define SPI_SR_TXRXS_SHIFT 30
+#define SPI_SR_TCF_MASK 0x80000000u
+#define SPI_SR_TCF_SHIFT 31
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT 16
+#define SPI_RSER_RFDF_RE_MASK 0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT 17
+#define SPI_RSER_RFOF_RE_MASK 0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT 19
+#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT 24
+#define SPI_RSER_TFFF_RE_MASK 0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT 25
+#define SPI_RSER_TFUF_RE_MASK 0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT 27
+#define SPI_RSER_EOQF_RE_MASK 0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT 28
+#define SPI_RSER_TCF_RE_MASK 0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT 31
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT 0
+#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK 0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT 16
+#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK 0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT 26
+#define SPI_PUSHR_EOQ_MASK 0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT 27
+#define SPI_PUSHR_CTAS_MASK 0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT 28
+#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK 0x80000000u
+#define SPI_PUSHR_CONT_SHIFT 31
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
+#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT 0
+#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT 0
+#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT 0
+#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT 0
+#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT 0
+#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT 0
+#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT 0
+#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT 0
+#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT 0
+#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/**
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+
+/**
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< General Control and Status Register, offset: 0x0 */
+ __IO uint32_t SCANC; /**< SCAN Control Register, offset: 0x4 */
+ __IO uint32_t PEN; /**< Pin Enable Register, offset: 0x8 */
+ __I uint32_t WUCNTR; /**< Wake-Up Channel Counter Register, offset: 0xC */
+ uint8_t RESERVED_0[240];
+ __I uint32_t CNTR1; /**< Counter Register, offset: 0x100 */
+ __I uint32_t CNTR3; /**< Counter Register, offset: 0x104 */
+ __I uint32_t CNTR5; /**< Counter Register, offset: 0x108 */
+ __I uint32_t CNTR7; /**< Counter Register, offset: 0x10C */
+ __I uint32_t CNTR9; /**< Counter Register, offset: 0x110 */
+ __I uint32_t CNTR11; /**< Counter Register, offset: 0x114 */
+ __I uint32_t CNTR13; /**< Counter Register, offset: 0x118 */
+ __I uint32_t CNTR15; /**< Counter Register, offset: 0x11C */
+ __IO uint32_t THRESHOLD; /**< Low Power Channel Threshold Register, offset: 0x120 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/* GENCS Bit Fields */
+#define TSI_GENCS_STPE_MASK 0x1u
+#define TSI_GENCS_STPE_SHIFT 0
+#define TSI_GENCS_STM_MASK 0x2u
+#define TSI_GENCS_STM_SHIFT 1
+#define TSI_GENCS_ESOR_MASK 0x10u
+#define TSI_GENCS_ESOR_SHIFT 4
+#define TSI_GENCS_ERIE_MASK 0x20u
+#define TSI_GENCS_ERIE_SHIFT 5
+#define TSI_GENCS_TSIIE_MASK 0x40u
+#define TSI_GENCS_TSIIE_SHIFT 6
+#define TSI_GENCS_TSIEN_MASK 0x80u
+#define TSI_GENCS_TSIEN_SHIFT 7
+#define TSI_GENCS_SWTS_MASK 0x100u
+#define TSI_GENCS_SWTS_SHIFT 8
+#define TSI_GENCS_SCNIP_MASK 0x200u
+#define TSI_GENCS_SCNIP_SHIFT 9
+#define TSI_GENCS_OVRF_MASK 0x1000u
+#define TSI_GENCS_OVRF_SHIFT 12
+#define TSI_GENCS_EXTERF_MASK 0x2000u
+#define TSI_GENCS_EXTERF_SHIFT 13
+#define TSI_GENCS_OUTRGF_MASK 0x4000u
+#define TSI_GENCS_OUTRGF_SHIFT 14
+#define TSI_GENCS_EOSF_MASK 0x8000u
+#define TSI_GENCS_EOSF_SHIFT 15
+#define TSI_GENCS_PS_MASK 0x70000u
+#define TSI_GENCS_PS_SHIFT 16
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
+#define TSI_GENCS_NSCN_MASK 0xF80000u
+#define TSI_GENCS_NSCN_SHIFT 19
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_LPSCNITV_MASK 0xF000000u
+#define TSI_GENCS_LPSCNITV_SHIFT 24
+#define TSI_GENCS_LPSCNITV(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
+#define TSI_GENCS_LPCLKS_MASK 0x10000000u
+#define TSI_GENCS_LPCLKS_SHIFT 28
+/* SCANC Bit Fields */
+#define TSI_SCANC_AMPSC_MASK 0x7u
+#define TSI_SCANC_AMPSC_SHIFT 0
+#define TSI_SCANC_AMPSC(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
+#define TSI_SCANC_AMCLKS_MASK 0x18u
+#define TSI_SCANC_AMCLKS_SHIFT 3
+#define TSI_SCANC_AMCLKS(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
+#define TSI_SCANC_SMOD_MASK 0xFF00u
+#define TSI_SCANC_SMOD_SHIFT 8
+#define TSI_SCANC_SMOD(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
+#define TSI_SCANC_EXTCHRG_MASK 0xF0000u
+#define TSI_SCANC_EXTCHRG_SHIFT 16
+#define TSI_SCANC_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
+#define TSI_SCANC_REFCHRG_MASK 0xF000000u
+#define TSI_SCANC_REFCHRG_SHIFT 24
+#define TSI_SCANC_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
+/* PEN Bit Fields */
+#define TSI_PEN_PEN0_MASK 0x1u
+#define TSI_PEN_PEN0_SHIFT 0
+#define TSI_PEN_PEN1_MASK 0x2u
+#define TSI_PEN_PEN1_SHIFT 1
+#define TSI_PEN_PEN2_MASK 0x4u
+#define TSI_PEN_PEN2_SHIFT 2
+#define TSI_PEN_PEN3_MASK 0x8u
+#define TSI_PEN_PEN3_SHIFT 3
+#define TSI_PEN_PEN4_MASK 0x10u
+#define TSI_PEN_PEN4_SHIFT 4
+#define TSI_PEN_PEN5_MASK 0x20u
+#define TSI_PEN_PEN5_SHIFT 5
+#define TSI_PEN_PEN6_MASK 0x40u
+#define TSI_PEN_PEN6_SHIFT 6
+#define TSI_PEN_PEN7_MASK 0x80u
+#define TSI_PEN_PEN7_SHIFT 7
+#define TSI_PEN_PEN8_MASK 0x100u
+#define TSI_PEN_PEN8_SHIFT 8
+#define TSI_PEN_PEN9_MASK 0x200u
+#define TSI_PEN_PEN9_SHIFT 9
+#define TSI_PEN_PEN10_MASK 0x400u
+#define TSI_PEN_PEN10_SHIFT 10
+#define TSI_PEN_PEN11_MASK 0x800u
+#define TSI_PEN_PEN11_SHIFT 11
+#define TSI_PEN_PEN12_MASK 0x1000u
+#define TSI_PEN_PEN12_SHIFT 12
+#define TSI_PEN_PEN13_MASK 0x2000u
+#define TSI_PEN_PEN13_SHIFT 13
+#define TSI_PEN_PEN14_MASK 0x4000u
+#define TSI_PEN_PEN14_SHIFT 14
+#define TSI_PEN_PEN15_MASK 0x8000u
+#define TSI_PEN_PEN15_SHIFT 15
+#define TSI_PEN_LPSP_MASK 0xF0000u
+#define TSI_PEN_LPSP_SHIFT 16
+#define TSI_PEN_LPSP(x) (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
+/* WUCNTR Bit Fields */
+#define TSI_WUCNTR_WUCNT_MASK 0xFFFFu
+#define TSI_WUCNTR_WUCNT_SHIFT 0
+#define TSI_WUCNTR_WUCNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_WUCNTR_WUCNT_SHIFT))&TSI_WUCNTR_WUCNT_MASK)
+/* CNTR1 Bit Fields */
+#define TSI_CNTR1_CTN1_MASK 0xFFFFu
+#define TSI_CNTR1_CTN1_SHIFT 0
+#define TSI_CNTR1_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN1_SHIFT))&TSI_CNTR1_CTN1_MASK)
+#define TSI_CNTR1_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR1_CTN_SHIFT 16
+#define TSI_CNTR1_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CTN_SHIFT))&TSI_CNTR1_CTN_MASK)
+/* CNTR3 Bit Fields */
+#define TSI_CNTR3_CTN1_MASK 0xFFFFu
+#define TSI_CNTR3_CTN1_SHIFT 0
+#define TSI_CNTR3_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN1_SHIFT))&TSI_CNTR3_CTN1_MASK)
+#define TSI_CNTR3_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR3_CTN_SHIFT 16
+#define TSI_CNTR3_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CTN_SHIFT))&TSI_CNTR3_CTN_MASK)
+/* CNTR5 Bit Fields */
+#define TSI_CNTR5_CTN1_MASK 0xFFFFu
+#define TSI_CNTR5_CTN1_SHIFT 0
+#define TSI_CNTR5_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN1_SHIFT))&TSI_CNTR5_CTN1_MASK)
+#define TSI_CNTR5_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR5_CTN_SHIFT 16
+#define TSI_CNTR5_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CTN_SHIFT))&TSI_CNTR5_CTN_MASK)
+/* CNTR7 Bit Fields */
+#define TSI_CNTR7_CTN1_MASK 0xFFFFu
+#define TSI_CNTR7_CTN1_SHIFT 0
+#define TSI_CNTR7_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN1_SHIFT))&TSI_CNTR7_CTN1_MASK)
+#define TSI_CNTR7_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR7_CTN_SHIFT 16
+#define TSI_CNTR7_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CTN_SHIFT))&TSI_CNTR7_CTN_MASK)
+/* CNTR9 Bit Fields */
+#define TSI_CNTR9_CTN1_MASK 0xFFFFu
+#define TSI_CNTR9_CTN1_SHIFT 0
+#define TSI_CNTR9_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN1_SHIFT))&TSI_CNTR9_CTN1_MASK)
+#define TSI_CNTR9_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR9_CTN_SHIFT 16
+#define TSI_CNTR9_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CTN_SHIFT))&TSI_CNTR9_CTN_MASK)
+/* CNTR11 Bit Fields */
+#define TSI_CNTR11_CTN1_MASK 0xFFFFu
+#define TSI_CNTR11_CTN1_SHIFT 0
+#define TSI_CNTR11_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN1_SHIFT))&TSI_CNTR11_CTN1_MASK)
+#define TSI_CNTR11_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR11_CTN_SHIFT 16
+#define TSI_CNTR11_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CTN_SHIFT))&TSI_CNTR11_CTN_MASK)
+/* CNTR13 Bit Fields */
+#define TSI_CNTR13_CTN1_MASK 0xFFFFu
+#define TSI_CNTR13_CTN1_SHIFT 0
+#define TSI_CNTR13_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN1_SHIFT))&TSI_CNTR13_CTN1_MASK)
+#define TSI_CNTR13_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR13_CTN_SHIFT 16
+#define TSI_CNTR13_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CTN_SHIFT))&TSI_CNTR13_CTN_MASK)
+/* CNTR15 Bit Fields */
+#define TSI_CNTR15_CTN1_MASK 0xFFFFu
+#define TSI_CNTR15_CTN1_SHIFT 0
+#define TSI_CNTR15_CTN1(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN1_SHIFT))&TSI_CNTR15_CTN1_MASK)
+#define TSI_CNTR15_CTN_MASK 0xFFFF0000u
+#define TSI_CNTR15_CTN_SHIFT 16
+#define TSI_CNTR15_CTN(x) (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CTN_SHIFT))&TSI_CNTR15_CTN_MASK)
+/* THRESHOLD Bit Fields */
+#define TSI_THRESHOLD_HTHH_MASK 0xFFFFu
+#define TSI_THRESHOLD_HTHH_SHIFT 0
+#define TSI_THRESHOLD_HTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_HTHH_SHIFT))&TSI_THRESHOLD_HTHH_MASK)
+#define TSI_THRESHOLD_LTHH_MASK 0xFFFF0000u
+#define TSI_THRESHOLD_LTHH_SHIFT 16
+#define TSI_THRESHOLD_LTHH(x) (((uint32_t)(((uint32_t)(x))<<TSI_THRESHOLD_LTHH_SHIFT))&TSI_THRESHOLD_LTHH_MASK)
+
+/**
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+
+/**
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Registers:High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+ __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
+ __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
+ __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
+ __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
+ __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
+ __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
+ __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
+ __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
+ __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
+ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+ union { /* offset: 0x1B */
+ __IO uint8_t WP7816_T_TYPE0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ __IO uint8_t WP7816_T_TYPE1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ };
+ __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
+ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
+ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
+ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
+ uint8_t RESERVED_2[1];
+ __IO uint8_t C6; /**< UART CEA709.1-B Control Register 6, offset: 0x21 */
+ __IO uint8_t PCTH; /**< UART CEA709.1-B Packet Cycle Time Counter High, offset: 0x22 */
+ __IO uint8_t PCTL; /**< UART CEA709.1-B Packet Cycle Time Counter Low, offset: 0x23 */
+ __IO uint8_t B1T; /**< UART CEA709.1-B Beta1 Timer, offset: 0x24 */
+ __IO uint8_t SDTH; /**< UART CEA709.1-B Secondary Delay Timer High, offset: 0x25 */
+ __IO uint8_t SDTL; /**< UART CEA709.1-B Secondary Delay Timer Low, offset: 0x26 */
+ __IO uint8_t PRE; /**< UART CEA709.1-B Preamble, offset: 0x27 */
+ __IO uint8_t TPL; /**< UART CEA709.1-B Transmit Packet Length, offset: 0x28 */
+ __IO uint8_t IE; /**< UART CEA709.1-B Interrupt Enable Register, offset: 0x29 */
+ __IO uint8_t WB; /**< UART CEA709.1-B WBASE, offset: 0x2A */
+ __IO uint8_t S3; /**< UART CEA709.1-B Status Register, offset: 0x2B */
+ __IO uint8_t S4; /**< UART CEA709.1-B Status Register, offset: 0x2C */
+ __I uint8_t RPL; /**< UART CEA709.1-B Received Packet Length, offset: 0x2D */
+ __I uint8_t RPREL; /**< UART CEA709.1-B Received Preamble Length, offset: 0x2E */
+ __IO uint8_t CPW; /**< UART CEA709.1-B Collision Pulse Width, offset: 0x2F */
+ __IO uint8_t RIDT; /**< UART CEA709.1-B Receive Indeterminate Time, offset: 0x30 */
+ __IO uint8_t TIDT; /**< UART CEA709.1-B Transmit Indeterminate Time, offset: 0x31 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+#define UART_BDH_LBKDIE_MASK 0x80u
+#define UART_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_UARTSWAI_MASK 0x40u
+#define UART_C1_UARTSWAI_SHIFT 6
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_LBKDE_MASK 0x2u
+#define UART_S2_LBKDE_SHIFT 1
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_MSBF_MASK 0x20u
+#define UART_S2_MSBF_SHIFT 5
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+#define UART_S2_LBKDIF_MASK 0x80u
+#define UART_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_RT_MASK 0xFFu
+#define UART_D_RT_SHIFT 0
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK 0xFFu
+#define UART_MA1_MA_SHIFT 0
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK 0xFFu
+#define UART_MA2_MA_SHIFT 0
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK 0x1Fu
+#define UART_C4_BRFA_SHIFT 0
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK 0x20u
+#define UART_C4_M10_SHIFT 5
+#define UART_C4_MAEN2_MASK 0x40u
+#define UART_C4_MAEN2_SHIFT 6
+#define UART_C4_MAEN1_MASK 0x80u
+#define UART_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UART_C5_RDMAS_MASK 0x20u
+#define UART_C5_RDMAS_SHIFT 5
+#define UART_C5_TDMAS_MASK 0x80u
+#define UART_C5_TDMAS_SHIFT 7
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK 0x40u
+#define UART_ED_PARITYE_SHIFT 6
+#define UART_ED_NOISY_MASK 0x80u
+#define UART_ED_NOISY_SHIFT 7
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK 0x1u
+#define UART_MODEM_TXCTSE_SHIFT 0
+#define UART_MODEM_TXRTSE_MASK 0x2u
+#define UART_MODEM_TXRTSE_SHIFT 1
+#define UART_MODEM_TXRTSPOL_MASK 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT 2
+#define UART_MODEM_RXRTSE_MASK 0x8u
+#define UART_MODEM_RXRTSE_SHIFT 3
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK 0x3u
+#define UART_IR_TNP_SHIFT 0
+#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK 0x4u
+#define UART_IR_IREN_SHIFT 2
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
+#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK 0x8u
+#define UART_PFIFO_RXFE_SHIFT 3
+#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
+#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK 0x80u
+#define UART_PFIFO_TXFE_SHIFT 7
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK 0x1u
+#define UART_CFIFO_RXUFE_SHIFT 0
+#define UART_CFIFO_TXOFE_MASK 0x2u
+#define UART_CFIFO_TXOFE_SHIFT 1
+#define UART_CFIFO_RXFLUSH_MASK 0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT 6
+#define UART_CFIFO_TXFLUSH_MASK 0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT 7
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK 0x1u
+#define UART_SFIFO_RXUF_SHIFT 0
+#define UART_SFIFO_TXOF_MASK 0x2u
+#define UART_SFIFO_TXOF_SHIFT 1
+#define UART_SFIFO_RXEMPT_MASK 0x40u
+#define UART_SFIFO_RXEMPT_SHIFT 6
+#define UART_SFIFO_TXEMPT_MASK 0x80u
+#define UART_SFIFO_TXEMPT_SHIFT 7
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT 0
+#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT 0
+#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT 0
+#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT 0
+#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK 0x1u
+#define UART_C7816_ISO_7816E_SHIFT 0
+#define UART_C7816_TTYPE_MASK 0x2u
+#define UART_C7816_TTYPE_SHIFT 1
+#define UART_C7816_INIT_MASK 0x4u
+#define UART_C7816_INIT_SHIFT 2
+#define UART_C7816_ANACK_MASK 0x8u
+#define UART_C7816_ANACK_SHIFT 3
+#define UART_C7816_ONACK_MASK 0x10u
+#define UART_C7816_ONACK_SHIFT 4
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK 0x1u
+#define UART_IE7816_RXTE_SHIFT 0
+#define UART_IE7816_TXTE_MASK 0x2u
+#define UART_IE7816_TXTE_SHIFT 1
+#define UART_IE7816_GTVE_MASK 0x4u
+#define UART_IE7816_GTVE_SHIFT 2
+#define UART_IE7816_INITDE_MASK 0x10u
+#define UART_IE7816_INITDE_SHIFT 4
+#define UART_IE7816_BWTE_MASK 0x20u
+#define UART_IE7816_BWTE_SHIFT 5
+#define UART_IE7816_CWTE_MASK 0x40u
+#define UART_IE7816_CWTE_SHIFT 6
+#define UART_IE7816_WTE_MASK 0x80u
+#define UART_IE7816_WTE_SHIFT 7
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK 0x1u
+#define UART_IS7816_RXT_SHIFT 0
+#define UART_IS7816_TXT_MASK 0x2u
+#define UART_IS7816_TXT_SHIFT 1
+#define UART_IS7816_GTV_MASK 0x4u
+#define UART_IS7816_GTV_SHIFT 2
+#define UART_IS7816_INITD_MASK 0x10u
+#define UART_IS7816_INITD_SHIFT 4
+#define UART_IS7816_BWT_MASK 0x20u
+#define UART_IS7816_BWT_SHIFT 5
+#define UART_IS7816_CWT_MASK 0x40u
+#define UART_IS7816_CWT_SHIFT 6
+#define UART_IS7816_WT_MASK 0x80u
+#define UART_IS7816_WT_SHIFT 7
+/* WP7816_T_TYPE0 Bit Fields */
+#define UART_WP7816_T_TYPE0_WI_MASK 0xFFu
+#define UART_WP7816_T_TYPE0_WI_SHIFT 0
+#define UART_WP7816_T_TYPE0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
+/* WP7816_T_TYPE1 Bit Fields */
+#define UART_WP7816_T_TYPE1_BWI_MASK 0xFu
+#define UART_WP7816_T_TYPE1_BWI_SHIFT 0
+#define UART_WP7816_T_TYPE1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
+#define UART_WP7816_T_TYPE1_CWI_MASK 0xF0u
+#define UART_WP7816_T_TYPE1_CWI_SHIFT 4
+#define UART_WP7816_T_TYPE1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK 0xFFu
+#define UART_WN7816_GTN_SHIFT 0
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK 0xFFu
+#define UART_WF7816_GTFD_SHIFT 0
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT 0
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT 4
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK 0xFFu
+#define UART_TL7816_TLEN_SHIFT 0
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+/* C6 Bit Fields */
+#define UART_C6_CP_MASK 0x10u
+#define UART_C6_CP_SHIFT 4
+#define UART_C6_CE_MASK 0x20u
+#define UART_C6_CE_SHIFT 5
+#define UART_C6_TX709_MASK 0x40u
+#define UART_C6_TX709_SHIFT 6
+#define UART_C6_EN709_MASK 0x80u
+#define UART_C6_EN709_SHIFT 7
+/* PCTH Bit Fields */
+#define UART_PCTH_PCTH_MASK 0xFFu
+#define UART_PCTH_PCTH_SHIFT 0
+#define UART_PCTH_PCTH(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTH_PCTH_SHIFT))&UART_PCTH_PCTH_MASK)
+/* PCTL Bit Fields */
+#define UART_PCTL_PCTL_MASK 0xFFu
+#define UART_PCTL_PCTL_SHIFT 0
+#define UART_PCTL_PCTL(x) (((uint8_t)(((uint8_t)(x))<<UART_PCTL_PCTL_SHIFT))&UART_PCTL_PCTL_MASK)
+/* B1T Bit Fields */
+#define UART_B1T_B1T_MASK 0xFFu
+#define UART_B1T_B1T_SHIFT 0
+#define UART_B1T_B1T(x) (((uint8_t)(((uint8_t)(x))<<UART_B1T_B1T_SHIFT))&UART_B1T_B1T_MASK)
+/* SDTH Bit Fields */
+#define UART_SDTH_SDTH_MASK 0xFFu
+#define UART_SDTH_SDTH_SHIFT 0
+#define UART_SDTH_SDTH(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTH_SDTH_SHIFT))&UART_SDTH_SDTH_MASK)
+/* SDTL Bit Fields */
+#define UART_SDTL_SDTL_MASK 0xFFu
+#define UART_SDTL_SDTL_SHIFT 0
+#define UART_SDTL_SDTL(x) (((uint8_t)(((uint8_t)(x))<<UART_SDTL_SDTL_SHIFT))&UART_SDTL_SDTL_MASK)
+/* PRE Bit Fields */
+#define UART_PRE_PREAMBLE_MASK 0xFFu
+#define UART_PRE_PREAMBLE_SHIFT 0
+#define UART_PRE_PREAMBLE(x) (((uint8_t)(((uint8_t)(x))<<UART_PRE_PREAMBLE_SHIFT))&UART_PRE_PREAMBLE_MASK)
+/* TPL Bit Fields */
+#define UART_TPL_TPL_MASK 0xFFu
+#define UART_TPL_TPL_SHIFT 0
+#define UART_TPL_TPL(x) (((uint8_t)(((uint8_t)(x))<<UART_TPL_TPL_SHIFT))&UART_TPL_TPL_MASK)
+/* IE Bit Fields */
+#define UART_IE_TXFIE_MASK 0x1u
+#define UART_IE_TXFIE_SHIFT 0
+#define UART_IE_PSIE_MASK 0x2u
+#define UART_IE_PSIE_SHIFT 1
+#define UART_IE_PCTEIE_MASK 0x4u
+#define UART_IE_PCTEIE_SHIFT 2
+#define UART_IE_PTXIE_MASK 0x8u
+#define UART_IE_PTXIE_SHIFT 3
+#define UART_IE_PRXIE_MASK 0x10u
+#define UART_IE_PRXIE_SHIFT 4
+#define UART_IE_ISDIE_MASK 0x20u
+#define UART_IE_ISDIE_SHIFT 5
+#define UART_IE_WBEIE_MASK 0x40u
+#define UART_IE_WBEIE_SHIFT 6
+/* WB Bit Fields */
+#define UART_WB_WBASE_MASK 0xFFu
+#define UART_WB_WBASE_SHIFT 0
+#define UART_WB_WBASE(x) (((uint8_t)(((uint8_t)(x))<<UART_WB_WBASE_SHIFT))&UART_WB_WBASE_MASK)
+/* S3 Bit Fields */
+#define UART_S3_TXFF_MASK 0x1u
+#define UART_S3_TXFF_SHIFT 0
+#define UART_S3_PSF_MASK 0x2u
+#define UART_S3_PSF_SHIFT 1
+#define UART_S3_PCTEF_MASK 0x4u
+#define UART_S3_PCTEF_SHIFT 2
+#define UART_S3_PTXF_MASK 0x8u
+#define UART_S3_PTXF_SHIFT 3
+#define UART_S3_PRXF_MASK 0x10u
+#define UART_S3_PRXF_SHIFT 4
+#define UART_S3_ISD_MASK 0x20u
+#define UART_S3_ISD_SHIFT 5
+#define UART_S3_WBEF_MASK 0x40u
+#define UART_S3_WBEF_SHIFT 6
+#define UART_S3_PEF_MASK 0x80u
+#define UART_S3_PEF_SHIFT 7
+/* S4 Bit Fields */
+#define UART_S4_FE_MASK 0x1u
+#define UART_S4_FE_SHIFT 0
+#define UART_S4_ILCV_MASK 0x2u
+#define UART_S4_ILCV_SHIFT 1
+#define UART_S4_CDET_MASK 0xCu
+#define UART_S4_CDET_SHIFT 2
+#define UART_S4_CDET(x) (((uint8_t)(((uint8_t)(x))<<UART_S4_CDET_SHIFT))&UART_S4_CDET_MASK)
+#define UART_S4_INITF_MASK 0x10u
+#define UART_S4_INITF_SHIFT 4
+/* RPL Bit Fields */
+#define UART_RPL_RPL_MASK 0xFFu
+#define UART_RPL_RPL_SHIFT 0
+#define UART_RPL_RPL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPL_RPL_SHIFT))&UART_RPL_RPL_MASK)
+/* RPREL Bit Fields */
+#define UART_RPREL_RPREL_MASK 0xFFu
+#define UART_RPREL_RPREL_SHIFT 0
+#define UART_RPREL_RPREL(x) (((uint8_t)(((uint8_t)(x))<<UART_RPREL_RPREL_SHIFT))&UART_RPREL_RPREL_MASK)
+/* CPW Bit Fields */
+#define UART_CPW_CPW_MASK 0xFFu
+#define UART_CPW_CPW_SHIFT 0
+#define UART_CPW_CPW(x) (((uint8_t)(((uint8_t)(x))<<UART_CPW_CPW_SHIFT))&UART_CPW_CPW_MASK)
+/* RIDT Bit Fields */
+#define UART_RIDT_RIDT_MASK 0xFFu
+#define UART_RIDT_RIDT_SHIFT 0
+#define UART_RIDT_RIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_RIDT_RIDT_SHIFT))&UART_RIDT_RIDT_MASK)
+/* TIDT Bit Fields */
+#define UART_TIDT_TIDT_MASK 0xFFu
+#define UART_TIDT_TIDT_SHIFT 0
+#define UART_TIDT_TIDT(x) (((uint8_t)(((uint8_t)(x))<<UART_TIDT_TIDT_SHIFT))&UART_TIDT_TIDT_MASK)
+
+/**
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART_Type *)UART0_BASE)
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+
+/**
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID Register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement Register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision Register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info Register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status Register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status Register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control Register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status Register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable Register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status Register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable Register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status Register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control Register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address Register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token Register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control Register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe Register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control Register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
+ uint8_t RESERVED_25[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+#define USB_ADDINFO_IRQNUM_MASK 0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT 3
+#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
+#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
+#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
+#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT 6
+#define USB_OTGISTAT_IDCHG_MASK 0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK 0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT 0
+#define USB_OTGICR_BSESSEN_MASK 0x4u
+#define USB_OTGICR_BSESSEN_SHIFT 2
+#define USB_OTGICR_SESSVLDEN_MASK 0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT 3
+#define USB_OTGICR_LINESTATEEN_MASK 0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT 5
+#define USB_OTGICR_ONEMSECEN_MASK 0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT 6
+#define USB_OTGICR_IDEN_MASK 0x80u
+#define USB_OTGICR_IDEN_SHIFT 7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
+#define USB_OTGSTAT_BSESSEND_MASK 0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT 2
+#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT 3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
+#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
+#define USB_OTGSTAT_ID_MASK 0x80u
+#define USB_OTGSTAT_ID_SHIFT 7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK 0x4u
+#define USB_OTGCTL_OTGEN_SHIFT 2
+#define USB_OTGCTL_DMLOW_MASK 0x10u
+#define USB_OTGCTL_DMLOW_SHIFT 4
+#define USB_OTGCTL_DPLOW_MASK 0x20u
+#define USB_OTGCTL_DPLOW_SHIFT 5
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_ATTACH_MASK 0x40u
+#define USB_ISTAT_ATTACH_SHIFT 6
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_ATTACHEN_MASK 0x40u
+#define USB_INTEN_ATTACHEN_SHIFT 6
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_RESUME_MASK 0x4u
+#define USB_CTL_RESUME_SHIFT 2
+#define USB_CTL_HOSTMODEEN_MASK 0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT 3
+#define USB_CTL_RESET_MASK 0x10u
+#define USB_CTL_RESET_SHIFT 4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK 0x80u
+#define USB_ADDR_LSEN_SHIFT 7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK 0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT 0
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK 0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT 4
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK 0xFFu
+#define USB_SOFTHLD_CNT_SHIFT 0
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+#define USB_ENDPT_RETRYDIS_MASK 0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT 6
+#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT 7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT 0
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+
+/**
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+
+/**
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONTROL; /**< Control Register, offset: 0x0 */
+ __IO uint32_t CLOCK; /**< Clock Register, offset: 0x4 */
+ __I uint32_t STATUS; /**< Status Register, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TIMER0; /**< TIMER0 Register, offset: 0x10 */
+ __IO uint32_t TIMER1; /**< , offset: 0x14 */
+ __IO uint32_t TIMER2; /**< , offset: 0x18 */
+} USBDCD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBDCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT 0
+#define USBDCD_CONTROL_IF_MASK 0x100u
+#define USBDCD_CONTROL_IF_SHIFT 8
+#define USBDCD_CONTROL_IE_MASK 0x10000u
+#define USBDCD_CONTROL_IE_SHIFT 16
+#define USBDCD_CONTROL_START_MASK 0x1000000u
+#define USBDCD_CONTROL_START_SHIFT 24
+#define USBDCD_CONTROL_SR_MASK 0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT 25
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
+#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/* STATUS Bit Fields */
+#define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
+#define USBDCD_STATUS_SEQ_RES_SHIFT 16
+#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
+#define USBDCD_STATUS_SEQ_STAT_SHIFT 18
+#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK 0x100000u
+#define USBDCD_STATUS_ERR_SHIFT 20
+#define USBDCD_STATUS_TO_MASK 0x200000u
+#define USBDCD_STATUS_TO_SHIFT 21
+#define USBDCD_STATUS_ACTIVE_MASK 0x400000u
+#define USBDCD_STATUS_ACTIVE_SHIFT 22
+/* TIMER0 Bit Fields */
+#define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
+#define USBDCD_TIMER0_TUNITCON_SHIFT 0
+#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
+#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
+/* TIMER1 Bit Fields */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
+#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
+#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
+/* TIMER2 Bit Fields */
+#define USBDCD_TIMER2_CHECK_DM_MASK 0xFu
+#define USBDCD_TIMER2_CHECK_DM_SHIFT 0
+#define USBDCD_TIMER2_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
+#define USBDCD_TIMER2_TVDPSRC_CON_MASK 0x3FF0000u
+#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT 16
+#define USBDCD_TIMER2_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
+
+/**
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
+
+/**
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
+ __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type;
+
+/* ----------------------------------------------------------------------------
+ -- VREF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK 0x3Fu
+#define VREF_TRM_TRIM_SHIFT 0
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK 0x40u
+#define VREF_TRM_CHOPEN_SHIFT 6
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK 0x3u
+#define VREF_SC_MODE_LV_SHIFT 0
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK 0x4u
+#define VREF_SC_VREFST_SHIFT 2
+#define VREF_SC_REGEN_MASK 0x40u
+#define VREF_SC_REGEN_SHIFT 6
+#define VREF_SC_VREFEN_MASK 0x80u
+#define VREF_SC_VREFEN_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF ((VREF_Type *)VREF_BASE)
+
+/**
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+ __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
+ __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
+ __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
+ __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+ __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
+ __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
+ __IO uint16_t REFRESH; /**< Watchdog Refresh Register, offset: 0xC */
+ __IO uint16_t UNLOCK; /**< Watchdog Unlock Register, offset: 0xE */
+ __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
+ __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
+ __IO uint16_t RSTCNT; /**< Watchdog Reset Count Register, offset: 0x14 */
+ __IO uint16_t PRESC; /**< Watchdog Prescaler Register, offset: 0x16 */
+} WDOG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT 0
+#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT 1
+#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
+#define WDOG_STCTRLH_WINEN_MASK 0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT 3
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
+#define WDOG_STCTRLH_DBGEN_MASK 0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT 5
+#define WDOG_STCTRLH_STOPEN_MASK 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT 6
+#define WDOG_STCTRLH_WAITEN_MASK 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT 7
+#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
+#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT 11
+#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT 12
+#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT 15
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
+#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT 0
+#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT 0
+#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK 0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT 0
+#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
+#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
+#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
+#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
+#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT 0
+#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT 8
+#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/**
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG ((WDOG_Type *)WDOG_BASE)
+
+/**
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/**
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+/* No backward compatibility issues. */
+
+/**
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#endif /* #if !defined(MK20D5_H_) */
+
+/* MK20D5.h, eof. */
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/MK20DX256.sct b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/MK20DX256.sct
new file mode 100644
index 000000000..8e8908c28
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/MK20DX256.sct
@@ -0,0 +1,13 @@
+
+LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
+ ER_IROM1 0x00000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(112 vect * 4 bytes) = 8_byte_aligned(0x1C0) = 0x1C0
+ ; 0x10000 - 0x1C0 = 0xFE40
+ RW_IRAM1 0x1FFF81C0 0xFE40 {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/startup_MK20DX256.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/startup_MK20DX256.s
new file mode 100644
index 000000000..cbbc94aaa
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/startup_MK20DX256.s
@@ -0,0 +1,559 @@
+;/*****************************************************************************
+; * @file: startup_MK20DX256.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
+; * MK20DX256
+; * @version: 1.0
+; * @date: 2011-12-15
+; *
+; * Copyright: 1997 - 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20008000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
+ DCD DMA4_IRQHandler ; DMA channel 4 transfer complete interrupt
+ DCD DMA5_IRQHandler ; DMA channel 5 transfer complete interrupt
+ DCD DMA6_IRQHandler ; DMA channel 6 transfer complete interrupt
+ DCD DMA7_IRQHandler ; DMA channel 7 transfer complete interrupt
+ DCD DMA8_IRQHandler ; DMA channel 8 transfer complete interrupt
+ DCD DMA9_IRQHandler ; DMA channel 9 transfer complete interrupt
+ DCD DMA10_IRQHandler ; DMA channel 10 transfer complete interrupt
+ DCD DMA11_IRQHandler ; DMA channel 11 transfer complete interrupt
+ DCD DMA12_IRQHandler ; DMA channel 12 transfer complete interrupt
+ DCD DMA13_IRQHandler ; DMA channel 13 transfer complete interrupt
+ DCD DMA14_IRQHandler ; DMA channel 14 transfer complete interrupt
+ DCD DMA15_IRQHandler ; DMA channel 15 transfer complete interrupt
+ DCD DMA_Error_IRQHandler ; DMA error interrupt
+ DCD Reserved33_IRQHandler ; Reserved interrupt 33
+ DCD FTFL_IRQHandler ; FTFL interrupt
+ DCD Read_Collision_IRQHandler ; Read collision interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD Watchdog_IRQHandler ; WDOG interrupt
+ DCD Reserved39_IRQHandler ; Reserved interrupt 39
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C1 interrupt
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD SPI1_IRQHandler ; SPI1 interrupt
+ DCD Reserved44_IRQHandler ; Reserved interrupt 44
+ DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
+ DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
+ DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
+ DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
+ DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
+ DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
+ DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
+ DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
+ DCD Reserved53_IRQHandler ; Reserved interrupt 53
+ DCD Reserved54_IRQHandler ; Reserved interrupt 54
+ DCD Reserved55_IRQHandler ; Reserved interrupt 55
+ DCD Reserved56_IRQHandler ; Reserved interrupt 56
+ DCD Reserved57_IRQHandler ; Reserved interrupt 57
+ DCD Reserved58_IRQHandler ; Reserved interrupt 58
+ DCD Reserved59_IRQHandler ; Reserved interrupt 59
+ DCD UART0_LON_IRQHandler ; UART0 LON interrupt
+ DCD UART0_RX_TX_IRQHandler ; UART0 receive/transmit interrupt
+ DCD UART0_ERR_IRQHandler ; UART0 error interrupt
+ DCD UART1_RX_TX_IRQHandler ; UART1 receive/transmit interrupt
+ DCD UART1_ERR_IRQHandler ; UART1 error interrupt
+ DCD UART2_RX_TX_IRQHandler ; UART2 receive/transmit interrupt
+ DCD UART2_ERR_IRQHandler ; UART2 error interrupt
+ DCD Reserved67_IRQHandler ; Reserved interrupt 67
+ DCD Reserved68_IRQHandler ; Reserved interrupt 68
+ DCD Reserved69_IRQHandler ; Reserved interrupt 69
+ DCD Reserved70_IRQHandler ; Reserved interrupt 70
+ DCD Reserved71_IRQHandler ; Reserved interrupt 71
+ DCD Reserved72_IRQHandler ; Reserved interrupt 72
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD ADC1_IRQHandler ; ADC1 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD CMP1_IRQHandler ; CMP1 interrupt
+ DCD CMP2_IRQHandler ; CMP2 interrupt
+ DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
+ DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
+ DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
+ DCD CMT_IRQHandler ; CMT interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
+ DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
+ DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
+ DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
+ DCD PDB0_IRQHandler ; PDB0 interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD USBDCD_IRQHandler ; USBDCD interrupt
+ DCD Reserved91_IRQHandler ; Reserved interrupt 91
+ DCD Reserved92_IRQHandler ; Reserved interrupt 92
+ DCD Reserved93_IRQHandler ; Reserved interrupt 93
+ DCD Reserved94_IRQHandler ; Reserved interrupt 94
+ DCD Reserved95_IRQHandler ; Reserved interrupt 95
+ DCD Reserved96_IRQHandler ; Reserved interrupt 96
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD Reserved98_IRQHandler ; Reserved interrupt 98
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD Reserved102_IRQHandler ; Reserved interrupt 102
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTB_IRQHandler ; Port B interrupt
+ DCD PORTC_IRQHandler ; Port C interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+ DCD PORTE_IRQHandler ; Port E interrupt
+ DCD Reserved108_IRQHandler ; Reserved interrupt 108
+ DCD Reserved109_IRQHandler ; Reserved interrupt 109
+ DCD SWI_IRQHandler ; Software interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; <h> Data flash protection byte (FDPROT)
+; <i> Each bit protects a 1/8 region of the data flash memory.
+; <i> (Program flash only devices: Reserved)
+; <o.0> FDPROT.0
+; <o.1> FDPROT.1
+; <o.2> FDPROT.2
+; <o.3> FDPROT.3
+; <o.4> FDPROT.4
+; <o.5> FDPROT.5
+; <o.6> FDPROT.6
+; <o.7> FDPROT.7
+nFDPROT EQU 0x00
+FDPROT EQU nFDPROT:EOR:0xFF
+; </h>
+; <h> EEPROM protection byte (FEPROT)
+; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
+; <i> (Program flash only devices: Reserved)
+; <o.0> FEPROT.0
+; <o.1> FEPROT.1
+; <o.2> FEPROT.2
+; <o.3> FEPROT.3
+; <o.4> FEPROT.4
+; <o.5> FEPROT.5
+; <o.6> FEPROT.6
+; <o.7> FEPROT.7
+nFEPROT EQU 0x00
+FEPROT EQU nFEPROT:EOR:0xFF
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT
+; <0=> Low-power boot
+; <1=> normal boot
+; <o.1> EZPORT_DIS
+; <0=> EzPort operation is enabled
+; <1=> EzPort operation is disabled
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+; </h>
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, FEPROT, FDPROT
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT DMA4_IRQHandler [WEAK]
+ EXPORT DMA5_IRQHandler [WEAK]
+ EXPORT DMA6_IRQHandler [WEAK]
+ EXPORT DMA7_IRQHandler [WEAK]
+ EXPORT DMA8_IRQHandler [WEAK]
+ EXPORT DMA9_IRQHandler [WEAK]
+ EXPORT DMA10_IRQHandler [WEAK]
+ EXPORT DMA11_IRQHandler [WEAK]
+ EXPORT DMA12_IRQHandler [WEAK]
+ EXPORT DMA13_IRQHandler [WEAK]
+ EXPORT DMA14_IRQHandler [WEAK]
+ EXPORT DMA15_IRQHandler [WEAK]
+ EXPORT DMA_Error_IRQHandler [WEAK]
+ EXPORT Reserved33_IRQHandler [WEAK]
+ EXPORT FTFL_IRQHandler [WEAK]
+ EXPORT Read_Collision_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT Watchdog_IRQHandler [WEAK]
+ EXPORT Reserved39_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT Reserved44_IRQHandler [WEAK]
+ EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
+ EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
+ EXPORT CAN0_Error_IRQHandler [WEAK]
+ EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
+ EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
+ EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
+ EXPORT I2S0_Tx_IRQHandler [WEAK]
+ EXPORT I2S0_Rx_IRQHandler [WEAK]
+ EXPORT Reserved53_IRQHandler [WEAK]
+ EXPORT Reserved54_IRQHandler [WEAK]
+ EXPORT Reserved55_IRQHandler [WEAK]
+ EXPORT Reserved56_IRQHandler [WEAK]
+ EXPORT Reserved57_IRQHandler [WEAK]
+ EXPORT Reserved58_IRQHandler [WEAK]
+ EXPORT Reserved59_IRQHandler [WEAK]
+ EXPORT UART0_LON_IRQHandler [WEAK]
+ EXPORT UART0_RX_TX_IRQHandler [WEAK]
+ EXPORT UART0_ERR_IRQHandler [WEAK]
+ EXPORT UART1_RX_TX_IRQHandler [WEAK]
+ EXPORT UART1_ERR_IRQHandler [WEAK]
+ EXPORT UART2_RX_TX_IRQHandler [WEAK]
+ EXPORT UART2_ERR_IRQHandler [WEAK]
+ EXPORT Reserved67_IRQHandler [WEAK]
+ EXPORT Reserved68_IRQHandler [WEAK]
+ EXPORT Reserved69_IRQHandler [WEAK]
+ EXPORT Reserved70_IRQHandler [WEAK]
+ EXPORT Reserved71_IRQHandler [WEAK]
+ EXPORT Reserved72_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT CMP1_IRQHandler [WEAK]
+ EXPORT CMP2_IRQHandler [WEAK]
+ EXPORT FTM0_IRQHandler [WEAK]
+ EXPORT FTM1_IRQHandler [WEAK]
+ EXPORT FTM2_IRQHandler [WEAK]
+ EXPORT CMT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT0_IRQHandler [WEAK]
+ EXPORT PIT1_IRQHandler [WEAK]
+ EXPORT PIT2_IRQHandler [WEAK]
+ EXPORT PIT3_IRQHandler [WEAK]
+ EXPORT PDB0_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT USBDCD_IRQHandler [WEAK]
+ EXPORT Reserved91_IRQHandler [WEAK]
+ EXPORT Reserved92_IRQHandler [WEAK]
+ EXPORT Reserved93_IRQHandler [WEAK]
+ EXPORT Reserved94_IRQHandler [WEAK]
+ EXPORT Reserved95_IRQHandler [WEAK]
+ EXPORT Reserved96_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT Reserved98_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT Reserved102_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTB_IRQHandler [WEAK]
+ EXPORT PORTC_IRQHandler [WEAK]
+ EXPORT PORTD_IRQHandler [WEAK]
+ EXPORT PORTE_IRQHandler [WEAK]
+ EXPORT Reserved108_IRQHandler [WEAK]
+ EXPORT Reserved109_IRQHandler [WEAK]
+ EXPORT SWI_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+DMA8_IRQHandler
+DMA9_IRQHandler
+DMA10_IRQHandler
+DMA11_IRQHandler
+DMA12_IRQHandler
+DMA13_IRQHandler
+DMA14_IRQHandler
+DMA15_IRQHandler
+DMA_Error_IRQHandler
+Reserved33_IRQHandler
+FTFL_IRQHandler
+Read_Collision_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+Watchdog_IRQHandler
+Reserved39_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+Reserved44_IRQHandler
+CAN0_ORed_Message_buffer_IRQHandler
+CAN0_Bus_Off_IRQHandler
+CAN0_Error_IRQHandler
+CAN0_Tx_Warning_IRQHandler
+CAN0_Rx_Warning_IRQHandler
+CAN0_Wake_Up_IRQHandler
+I2S0_Tx_IRQHandler
+I2S0_Rx_IRQHandler
+Reserved53_IRQHandler
+Reserved54_IRQHandler
+Reserved55_IRQHandler
+Reserved56_IRQHandler
+Reserved57_IRQHandler
+Reserved58_IRQHandler
+Reserved59_IRQHandler
+UART0_LON_IRQHandler
+UART0_RX_TX_IRQHandler
+UART0_ERR_IRQHandler
+UART1_RX_TX_IRQHandler
+UART1_ERR_IRQHandler
+UART2_RX_TX_IRQHandler
+UART2_ERR_IRQHandler
+Reserved67_IRQHandler
+Reserved68_IRQHandler
+Reserved69_IRQHandler
+Reserved70_IRQHandler
+Reserved71_IRQHandler
+Reserved72_IRQHandler
+ADC0_IRQHandler
+ADC1_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+CMP2_IRQHandler
+FTM0_IRQHandler
+FTM1_IRQHandler
+FTM2_IRQHandler
+CMT_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT0_IRQHandler
+PIT1_IRQHandler
+PIT2_IRQHandler
+PIT3_IRQHandler
+PDB0_IRQHandler
+USB0_IRQHandler
+USBDCD_IRQHandler
+Reserved91_IRQHandler
+Reserved92_IRQHandler
+Reserved93_IRQHandler
+Reserved94_IRQHandler
+Reserved95_IRQHandler
+Reserved96_IRQHandler
+DAC0_IRQHandler
+Reserved98_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+Reserved102_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+Reserved108_IRQHandler
+Reserved109_IRQHandler
+SWI_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..3296df192
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld
new file mode 100644
index 000000000..3a40be864
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/MK20DX256.ld
@@ -0,0 +1,164 @@
+/*
+ * K20DX256 ARM GCC linker script file
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFF81C0, LENGTH = 64K - 0x1C0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ . = 0;
+ __isr_vector = .;
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+ *(.text.SystemInit)
+ . = ALIGN(4);
+ } > VECTORS
+
+ .flash_protect :
+ {
+ KEEP(*(.kinetis_flash_config_field))
+ . = ALIGN(4);
+ } > FLASH_PROTECTION
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s
new file mode 100644
index 000000000..e54559a4d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/TOOLCHAIN_GCC_ARM/startup_MK20DX256.s
@@ -0,0 +1,366 @@
+/* File: startup_MK20DX256.s
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.3
+ * Date: 08 Feb 2012
+ *
+ * Copyright (c) 2015, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv7-m
+
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0xC00
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .if Heap_Size
+ .space Heap_Size
+ .endif
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DMA0_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA1_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA2_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA3_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA4_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA5_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA6_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA7_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA8_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA9_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA10_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA11_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA12_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA13_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA14_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA15_IRQHandler // DMA channel 0 transfer complete interrupt
+ .long DMA_Error_IRQHandler // DMA error interrupt
+ .long Reserved33_IRQHandler // Reserved interrupt 33
+ .long FTFL_IRQHandler // FTFL interrupt
+ .long Read_Collision_IRQHandler // Read collision interrupt
+ .long LVD_LVW_IRQHandler // Low Voltage Detect, Low Voltage Warning
+ .long LLW_IRQHandler // Low Leakage Wakeup
+ .long Watchdog_IRQHandler // WDOG interrupt
+ .long Reserved39_IRQHandler // Reserved interrupt 39
+ .long I2C0_IRQHandler // I2C0 interrupt
+ .long I2C1_IRQHandler // I2C1 interrupt
+ .long SPI0_IRQHandler // SPI0 interrupt
+ .long SPI1_IRQHandler // SPI1 interrupt
+ .long Reserved44_IRQHandler // Reserved interrupt 44
+ .long CAN0_ORed_Message_buffer_IRQHandler // CAN0 OR'd message buffers interrupt
+ .long CAN0_Bus_Off_IRQHandler // CAN0 bus off interrupt
+ .long CAN0_Error_IRQHandler // CAN0 error interrupt
+ .long CAN0_Tx_Warning_IRQHandler // CAN0 Tx warning interrupt
+ .long CAN0_Rx_Warning_IRQHandler // CAN0 Rx warning interrupt
+ .long CAN0_Wake_Up_IRQHandler // CAN0 wake up interrupt
+ .long I2S0_Tx_IRQHandler // I2S0 transmit interrupt
+ .long I2S0_Rx_IRQHandler // I2S0 receive interrupt
+ .long Reserved53_IRQHandler // Reserved interrupt 53
+ .long Reserved54_IRQHandler // Reserved interrupt 54
+ .long Reserved55_IRQHandler // Reserved interrupt 55
+ .long Reserved56_IRQHandler // Reserved interrupt 56
+ .long Reserved57_IRQHandler // Reserved interrupt 57
+ .long Reserved58_IRQHandler // Reserved interrupt 58
+ .long Reserved59_IRQHandler // Reserved interrupt 59
+ .long UART0_LON_IRQHandler // UART0 LON interrupt
+ .long UART0_RX_TX_IRQHandler // UART0 receive/transmit interrupt
+ .long UART0_ERR_IRQHandler // UART0 error interrupt
+ .long UART1_RX_TX_IRQHandler // UART1 receive/transmit interrupt
+ .long UART1_ERR_IRQHandler // UART1 error interrupt
+ .long UART2_RX_TX_IRQHandler // UART2 receive/transmit interrupt
+ .long UART2_ERR_IRQHandler // UART2 error interrupt
+ .long Reserved67_IRQHandler // Reserved interrupt 67
+ .long Reserved68_IRQHandler // Reserved interrupt 68
+ .long Reserved69_IRQHandler // Reserved interrupt 69
+ .long Reserved70_IRQHandler // Reserved interrupt 70
+ .long Reserved71_IRQHandler // Reserved interrupt 71
+ .long Reserved72_IRQHandler // Reserved interrupt 72
+ .long ADC0_IRQHandler // ADC0 interrupt
+ .long ADC1_IRQHandler // ADC1 interrupt
+ .long CMP0_IRQHandler // CMP0 interrupt
+ .long CMP1_IRQHandler // CMP1 interrupt
+ .long CMP2_IRQHandler // CMP2 interrupt
+ .long FTM0_IRQHandler // FTM0 fault, overflow and channels interrupt
+ .long FTM1_IRQHandler // FTM1 fault, overflow and channels interrupt
+ .long FTM2_IRQHandler // FTM2 fault, overflow and channels interrupt
+ .long CMT_IRQHandler // CMT interrupt
+ .long RTC_IRQHandler // RTC interrupt
+ .long RTC_Seconds_IRQHandler // RTC seconds interrupt
+ .long PIT0_IRQHandler // PIT timer channel 0 interrupt
+ .long PIT1_IRQHandler // PIT timer channel 1 interrupt
+ .long PIT2_IRQHandler // PIT timer channel 2 interrupt
+ .long PIT3_IRQHandler // PIT timer channel 3 interrupt
+ .long PDB0_IRQHandler // PDB0 interrupt
+ .long USB0_IRQHandler // USB0 interrupt
+ .long USBDCD_IRQHandler // USBDCD interrupt
+ .long Reserved91_IRQHandler // Reserved interrupt 91
+ .long Reserved92_IRQHandler // Reserved interrupt 92
+ .long Reserved93_IRQHandler // Reserved interrupt 93
+ .long Reserved94_IRQHandler // Reserved interrupt 94
+ .long Reserved95_IRQHandler // Reserved interrupt 95
+ .long Reserved96_IRQHandler // Reserved interrupt 96
+ .long DAC0_IRQHandler // DAC0 interrupt
+ .long Reserved98_IRQHandler // Reserved interrupt 98
+ .long TSI0_IRQHandler // TSI0 interrupt
+ .long MCG_IRQHandler // MCG interrupt
+ .long LPTimer_IRQHandler // LPTimer interrupt
+ .long Reserved102_IRQHandler // Reserved interrupt 102
+ .long PORTA_IRQHandler // Port A interrupt
+ .long PORTB_IRQHandler // Port B interrupt
+ .long PORTC_IRQHandler // Port C interrupt
+ .long PORTD_IRQHandler // Port D interrupt
+ .long PORTE_IRQHandler // Port E interrupt
+ .long Reserved108_IRQHandler // Reserved interrupt 108
+ .long Reserved109_IRQHandler // Reserved interrupt 109
+ .long SWI_IRQHandler // Software interrupt
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/*
+ * Call SystemInit before loading the .data section to prevent the watchdog
+ * from resetting the board.
+ */
+ ldr r0, =SystemInit
+ blx r0
+
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+.Lflash_to_ram_loop:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .Lflash_to_ram_loop
+
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+
+ def_irq_default_handler DMA0_IRQHandler
+ def_irq_default_handler DMA1_IRQHandler
+ def_irq_default_handler DMA2_IRQHandler
+ def_irq_default_handler DMA3_IRQHandler
+ def_irq_default_handler DMA4_IRQHandler
+ def_irq_default_handler DMA5_IRQHandler
+ def_irq_default_handler DMA6_IRQHandler
+ def_irq_default_handler DMA7_IRQHandler
+ def_irq_default_handler DMA8_IRQHandler
+ def_irq_default_handler DMA9_IRQHandler
+ def_irq_default_handler DMA10_IRQHandler
+ def_irq_default_handler DMA11_IRQHandler
+ def_irq_default_handler DMA12_IRQHandler
+ def_irq_default_handler DMA13_IRQHandler
+ def_irq_default_handler DMA14_IRQHandler
+ def_irq_default_handler DMA15_IRQHandler
+ def_irq_default_handler DMA_Error_IRQHandler
+ def_irq_default_handler Reserved33_IRQHandler
+ def_irq_default_handler FTFL_IRQHandler
+ def_irq_default_handler Read_Collision_IRQHandler
+ def_irq_default_handler LVD_LVW_IRQHandler
+ def_irq_default_handler LLW_IRQHandler
+ def_irq_default_handler Watchdog_IRQHandler
+ def_irq_default_handler Reserved39_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler Reserved44_IRQHandler
+ def_irq_default_handler CAN0_ORed_Message_buffer_IRQHandler
+ def_irq_default_handler CAN0_Bus_Off_IRQHandler
+ def_irq_default_handler CAN0_Error_IRQHandler
+ def_irq_default_handler CAN0_Tx_Warning_IRQHandler
+ def_irq_default_handler CAN0_Rx_Warning_IRQHandler
+ def_irq_default_handler CAN0_Wake_Up_IRQHandler
+ def_irq_default_handler I2S0_Tx_IRQHandler
+ def_irq_default_handler I2S0_Rx_IRQHandler
+ def_irq_default_handler Reserved53_IRQHandler
+ def_irq_default_handler Reserved54_IRQHandler
+ def_irq_default_handler Reserved55_IRQHandler
+ def_irq_default_handler Reserved56_IRQHandler
+ def_irq_default_handler Reserved57_IRQHandler
+ def_irq_default_handler Reserved58_IRQHandler
+ def_irq_default_handler Reserved59_IRQHandler
+ def_irq_default_handler UART0_LON_IRQHandler
+ def_irq_default_handler UART0_RX_TX_IRQHandler
+ def_irq_default_handler UART0_ERR_IRQHandler
+ def_irq_default_handler UART1_RX_TX_IRQHandler
+ def_irq_default_handler UART1_ERR_IRQHandler
+ def_irq_default_handler UART2_RX_TX_IRQHandler
+ def_irq_default_handler UART2_ERR_IRQHandler
+ def_irq_default_handler Reserved67_IRQHandler
+ def_irq_default_handler Reserved68_IRQHandler
+ def_irq_default_handler Reserved69_IRQHandler
+ def_irq_default_handler Reserved70_IRQHandler
+ def_irq_default_handler Reserved71_IRQHandler
+ def_irq_default_handler Reserved72_IRQHandler
+ def_irq_default_handler ADC0_IRQHandler
+ def_irq_default_handler ADC1_IRQHandler
+ def_irq_default_handler CMP0_IRQHandler
+ def_irq_default_handler CMP1_IRQHandler
+ def_irq_default_handler CMP2_IRQHandler
+ def_irq_default_handler FTM0_IRQHandler
+ def_irq_default_handler FTM1_IRQHandler
+ def_irq_default_handler FTM2_IRQHandler
+ def_irq_default_handler CMT_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler RTC_Seconds_IRQHandler
+ def_irq_default_handler PIT0_IRQHandler
+ def_irq_default_handler PIT1_IRQHandler
+ def_irq_default_handler PIT2_IRQHandler
+ def_irq_default_handler PIT3_IRQHandler
+ def_irq_default_handler PDB0_IRQHandler
+ def_irq_default_handler USB0_IRQHandler
+ def_irq_default_handler USBDCD_IRQHandler
+ def_irq_default_handler Reserved91_IRQHandler
+ def_irq_default_handler Reserved92_IRQHandler
+ def_irq_default_handler Reserved93_IRQHandler
+ def_irq_default_handler Reserved94_IRQHandler
+ def_irq_default_handler Reserved95_IRQHandler
+ def_irq_default_handler Reserved96_IRQHandler
+ def_irq_default_handler DAC0_IRQHandler
+ def_irq_default_handler Reserved98_IRQHandler
+ def_irq_default_handler TSI0_IRQHandler
+ def_irq_default_handler MCG_IRQHandler
+ def_irq_default_handler LPTimer_IRQHandler
+ def_irq_default_handler Reserved102_IRQHandler
+ def_irq_default_handler PORTA_IRQHandler
+ def_irq_default_handler PORTB_IRQHandler
+ def_irq_default_handler PORTC_IRQHandler
+ def_irq_default_handler PORTD_IRQHandler
+ def_irq_default_handler PORTE_IRQHandler
+ def_irq_default_handler Reserved108_IRQHandler
+ def_irq_default_handler Reserved109_IRQHandler
+ def_irq_default_handler SWI_IRQHandler
+ def_irq_default_handler DefaultISR
+
+/* Flash protection region, placed at 0x400 */
+ .text
+ .thumb
+ .align 2
+ .section .kinetis_flash_config_field,"a",%progbits
+kinetis_flash_config:
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xfffffffe
+
+ .end
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h
new file mode 100644
index 000000000..86440692b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2015 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MK20DX256.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c
new file mode 100644
index 000000000..8148ba87f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2012 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF8000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h
new file mode 100644
index 000000000..ce9de13c9
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2015 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 95) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c
new file mode 100644
index 000000000..4f34cc76c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c
@@ -0,0 +1,309 @@
+/*
+** ###################################################################
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+**
+**
+** Version: rev. 1.0, 2011-12-15
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2011-12-15)
+** Initial version
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK20DX256
+ * @version 1.0
+ * @date 2011-12-15
+ * @brief Device specific configuration file for MK20DX256 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MK20DX256.h"
+
+#define DISABLE_WDOG 1
+
+#define CLOCK_SETUP 3
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+ Reference clock source for MCG module is the slow internal clock source 32.768kHz
+ Core clock = 41.94MHz, BusClock = 41.94MHz
+ This works on Teensy3.1
+ 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+ Reference clock source for MCG module is an external crystal 8MHz
+ Core clock = 48MHz, BusClock = 48MHz
+ 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+ Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
+ Core clock = 8MHz, BusClock = 8MHz
+ 3 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+ Reference clock source for MCG module is an external crystal 16MHz
+ Core clock = 72MHz, BusClock = 48MHz
+ This is the default Teensy3.1 72Mhz set up
+*/
+
+/*----------------------------------------------------------------------------
+ Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 3)
+ #define CPU_XTAL_CLK_HZ 16000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 72000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+void SystemInit (void) {
+ /* SystemInit MUST NOT use any variables from the .data section, as this section is not loaded yet! */
+
+#if (DISABLE_WDOG)
+ /* Disable the WDOG module */
+ /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
+ WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */
+ /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
+ WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */
+ /* WDOG_STCTRLH: DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+ WDOG->STCTRLH = (uint16_t)0x01D2u;
+#endif /* (DISABLE_WDOG) */
+
+#if (CLOCK_SETUP == 0)
+ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 41.94MHz cpu, 41.94MHz system, 20.97MHz flash*/
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
+ /* Switch to FEI Mode */
+ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK;
+ /* MCG->C2: LOCKRE0=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x00u;
+ /* MCG_C4: DMX32=0,DRST_DRS=1 */
+ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
+ /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00u;
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_IREFST_MASK) == 0u) { } /* Check that the source of the FLL reference clock is the internal reference clock. */
+ while((MCG->S & 0x0Cu) != 0x00u) { } /* Wait until output of the FLL is selected */
+
+#elif (CLOCK_SETUP == 1)
+ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 48MHz cpu, 48MHz system, 24MHz flash*/
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
+ /* Switch to FBE Mode */
+ /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x00u;
+ /* MCG->C7: OSCSEL=0 */
+ MCG->C7 = (uint8_t)0x00u;
+ /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = MCG_C2_RANGE0(2);
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
+ /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
+ MCG->C5 = MCG_C5_PRDIV0(3);
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
+ while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
+ /* Switch to PBE Mode */
+ /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
+ MCG->C5 = MCG_C5_PRDIV0(3);
+ /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
+ MCG->C6 = MCG_C6_PLLS_MASK;
+ while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
+ /* Switch to PEE Mode */
+ /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
+ while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
+
+#elif (CLOCK_SETUP == 2)
+ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 8MHz cpu, 8MHz system, 8MHz flash*/
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
+ /* Switch to FBE Mode */
+ /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x00u;
+ /* MCG->C7: OSCSEL=0 */
+ MCG->C7 = (uint8_t)0x00u;
+ /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
+ /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00u;
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
+ while((MCG->S & 0x0CU) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
+ /* Switch to BLPE Mode */
+ /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
+
+#elif (CLOCK_SETUP == 3)
+ /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 72MHz system, 36MHz flash*/
+ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1);
+ /* SIM->CLKDIV2: USBDIV=2,USBFRAC=1 Divide 72MHz system clock for USB 48MHz */
+ SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK;
+ /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/
+ OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK;
+ /* Switch to FBE Mode */
+ /* MCG->C7: OSCSEL=0 */
+ MCG->C7 = (uint8_t)0x00u;
+ /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK;
+ //MCG->C2 = (uint8_t)0x24u;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
+ /* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
+ /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */
+ MCG->C5 = MCG_C5_PRDIV0(7);
+ /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00u;
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */
+ while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */
+ /* Switch to PBE Mode */
+ /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */
+ MCG->C5 = MCG_C5_PRDIV0(5);
+ /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */
+ MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
+ while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
+ /* Switch to PEE Mode */
+ /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;
+ while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */
+#endif /* (CLOCK_SETUP) */
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint8_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+ /* Output of FLL or PLL is selected */
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
+ /* FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+ /* External reference clock is selected */
+ if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
+ MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
+ } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x0u:
+ MCGOUTClock *= 640u;
+ break;
+ case 0x20u:
+ MCGOUTClock *= 1280u;
+ break;
+ case 0x40u:
+ MCGOUTClock *= 1920u;
+ break;
+ case 0x60u:
+ MCGOUTClock *= 2560u;
+ break;
+ case 0x80u:
+ MCGOUTClock *= 732u;
+ break;
+ case 0xA0u:
+ MCGOUTClock *= 1464u;
+ break;
+ case 0xC0u:
+ MCGOUTClock *= 2197u;
+ break;
+ case 0xE0u:
+ MCGOUTClock *= 2929u;
+ break;
+ default:
+ break;
+ }
+ } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ /* PLL is selected */
+ Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+ MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+ Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+ MCGOUTClock *= Divider; /* Calculate the MCG output clock */
+ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+ /* External reference clock is selected */
+ if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h
new file mode 100644
index 000000000..3c916d038
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.h
@@ -0,0 +1,85 @@
+/*
+** ###################################################################
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+**
+**
+** Version: rev. 2.0, 2012-03-19
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2011-12-15)
+** Initial version
+** - rev. 2.0 (2012-03-19)
+** PDB Peripheral register structure updated.
+** DMA Registers and bits for unsupported DMA channels removed.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MK20DX256
+ * @version 2.0
+ * @date 2012-03-19
+ * @brief Device specific configuration file for MK20DX256 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK20DX256_H_
+#define SYSTEM_MK20DX256_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MK20DX256_H_) */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h
new file mode 100644
index 000000000..fd48b0f8c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/MK22F51212.h
@@ -0,0 +1,10137 @@
+/*
+** ###################################################################
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
+** Version: rev. 2.5, 2014-05-06
+** Build: b140604
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MK22F51212
+**
+** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2013-07-23)
+** Initial version.
+** - rev. 1.1 (2013-09-17)
+** RM rev. 0.4 update.
+** - rev. 2.0 (2013-10-29)
+** Register accessor macros added to the memory map.
+** Symbols for Processor Expert memory map compatibility added to the memory map.
+** Startup file for gcc has been updated according to CMSIS 3.2.
+** System initialization updated.
+** - rev. 2.1 (2013-10-30)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+** - rev. 2.2 (2013-12-20)
+** Update according to reference manual rev. 0.6,
+** - rev. 2.3 (2014-01-13)
+** Update according to reference manual rev. 0.61,
+** - rev. 2.4 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
+** - rev. 2.5 (2014-05-06)
+** Update according to reference manual rev. 1.0,
+** Update of system and startup files.
+** Module access macro module_BASES replaced by module_BASE_PTRS.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK22F51212.h
+ * @version 2.5
+ * @date 2014-05-06
+ * @brief CMSIS Peripheral Access Layer for MK22F51212
+ *
+ * CMSIS Peripheral Access Layer for MK22F51212
+ */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCU activation
+ ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MK22F51212_H_) /* Check if memory map has not been already included */
+#define MK22F51212_H_
+#define MCU_MK22F51212
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+ #error MK22F51212 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0005u
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ * bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ * 0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
+ DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
+ DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
+ DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
+ DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
+ DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
+ DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
+ DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
+ DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
+ DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
+ DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
+ DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
+ DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
+ DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
+ DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
+ DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
+ DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
+ MCM_IRQn = 17, /**< Normal Interrupt */
+ FTF_IRQn = 18, /**< FTFA Command complete interrupt */
+ Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
+ LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 21, /**< Low Leakage Wakeup */
+ Watchdog_IRQn = 22, /**< WDOG Interrupt */
+ RNG_IRQn = 23, /**< RNG Interrupt */
+ I2C0_IRQn = 24, /**< I2C0 interrupt */
+ I2C1_IRQn = 25, /**< I2C1 interrupt */
+ SPI0_IRQn = 26, /**< SPI0 Interrupt */
+ SPI1_IRQn = 27, /**< SPI1 Interrupt */
+ I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
+ I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
+ LPUART0_IRQn = 30, /**< LPUART0 status/error interrupt */
+ UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
+ UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
+ UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
+ UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
+ UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
+ UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
+ Reserved53_IRQn = 37, /**< Reserved interrupt 53 */
+ Reserved54_IRQn = 38, /**< Reserved interrupt 54 */
+ ADC0_IRQn = 39, /**< ADC0 interrupt */
+ CMP0_IRQn = 40, /**< CMP0 interrupt */
+ CMP1_IRQn = 41, /**< CMP1 interrupt */
+ FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
+ FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
+ FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
+ Reserved61_IRQn = 45, /**< Reserved interrupt 61 */
+ RTC_IRQn = 46, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
+ PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
+ PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
+ PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
+ PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
+ PDB0_IRQn = 52, /**< PDB0 Interrupt */
+ USB0_IRQn = 53, /**< USB0 interrupt */
+ Reserved70_IRQn = 54, /**< Reserved interrupt 70 */
+ Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
+ DAC0_IRQn = 56, /**< DAC0 interrupt */
+ MCG_IRQn = 57, /**< MCG Interrupt */
+ LPTimer_IRQn = 58, /**< LPTimer interrupt */
+ PORTA_IRQn = 59, /**< Port A interrupt */
+ PORTB_IRQn = 60, /**< Port B interrupt */
+ PORTC_IRQn = 61, /**< Port C interrupt */
+ PORTD_IRQn = 62, /**< Port D interrupt */
+ PORTE_IRQn = 63, /**< Port E interrupt */
+ SWI_IRQn = 64, /**< Software interrupt */
+ Reserved81_IRQn = 65, /**< Reserved interrupt 81 */
+ Reserved82_IRQn = 66, /**< Reserved interrupt 82 */
+ Reserved83_IRQn = 67, /**< Reserved interrupt 83 */
+ Reserved84_IRQn = 68, /**< Reserved interrupt 84 */
+ Reserved85_IRQn = 69, /**< Reserved interrupt 85 */
+ Reserved86_IRQn = 70, /**< Reserved interrupt 86 */
+ FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
+ DAC1_IRQn = 72, /**< DAC1 interrupt */
+ ADC1_IRQn = 73, /**< ADC1 interrupt */
+ Reserved90_IRQn = 74, /**< Reserved Interrupt 90 */
+ Reserved91_IRQn = 75, /**< Reserved Interrupt 91 */
+ Reserved92_IRQn = 76, /**< Reserved Interrupt 92 */
+ Reserved93_IRQn = 77, /**< Reserved Interrupt 93 */
+ Reserved94_IRQn = 78, /**< Reserved Interrupt 94 */
+ Reserved95_IRQn = 79, /**< Reserved Interrupt 95 */
+ Reserved96_IRQn = 80, /**< Reserved Interrupt 96 */
+ Reserved97_IRQn = 81, /**< Reserved Interrupt 97 */
+ Reserved98_IRQn = 82, /**< Reserved Interrupt 98 */
+ Reserved99_IRQn = 83, /**< Reserved Interrupt 99 */
+ Reserved100_IRQn = 84, /**< Reserved Interrupt 100 */
+ Reserved101_IRQn = 85 /**< Reserved Interrupt 101 */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M4 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h" /* Core Peripheral Access Layer */
+#include "system_MK22F51212.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index) ((base)->SC1[index])
+#define ADC_CFG1_REG(base) ((base)->CFG1)
+#define ADC_CFG2_REG(base) ((base)->CFG2)
+#define ADC_R_REG(base,index) ((base)->R[index])
+#define ADC_CV1_REG(base) ((base)->CV1)
+#define ADC_CV2_REG(base) ((base)->CV2)
+#define ADC_SC2_REG(base) ((base)->SC2)
+#define ADC_SC3_REG(base) ((base)->SC3)
+#define ADC_OFS_REG(base) ((base)->OFS)
+#define ADC_PG_REG(base) ((base)->PG)
+#define ADC_MG_REG(base) ((base)->MG)
+#define ADC_CLPD_REG(base) ((base)->CLPD)
+#define ADC_CLPS_REG(base) ((base)->CLPS)
+#define ADC_CLP4_REG(base) ((base)->CLP4)
+#define ADC_CLP3_REG(base) ((base)->CLP3)
+#define ADC_CLP2_REG(base) ((base)->CLP2)
+#define ADC_CLP1_REG(base) ((base)->CLP1)
+#define ADC_CLP0_REG(base) ((base)->CLP0)
+#define ADC_CLMD_REG(base) ((base)->CLMD)
+#define ADC_CLMS_REG(base) ((base)->CLMS)
+#define ADC_CLM4_REG(base) ((base)->CLM4)
+#define ADC_CLM3_REG(base) ((base)->CLM3)
+#define ADC_CLM2_REG(base) ((base)->CLM2)
+#define ADC_CLM1_REG(base) ((base)->CLM1)
+#define ADC_CLM0_REG(base) ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR (ADC0)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE (0x40027000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1 ((ADC_Type *)ADC1_BASE)
+#define ADC1_BASE_PTR (ADC1)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
+#define ADC0_RA ADC_R_REG(ADC0,0)
+#define ADC0_RB ADC_R_REG(ADC0,1)
+#define ADC0_CV1 ADC_CV1_REG(ADC0)
+#define ADC0_CV2 ADC_CV2_REG(ADC0)
+#define ADC0_SC2 ADC_SC2_REG(ADC0)
+#define ADC0_SC3 ADC_SC3_REG(ADC0)
+#define ADC0_OFS ADC_OFS_REG(ADC0)
+#define ADC0_PG ADC_PG_REG(ADC0)
+#define ADC0_MG ADC_MG_REG(ADC0)
+#define ADC0_CLPD ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
+/* ADC1 */
+#define ADC1_SC1A ADC_SC1_REG(ADC1,0)
+#define ADC1_SC1B ADC_SC1_REG(ADC1,1)
+#define ADC1_CFG1 ADC_CFG1_REG(ADC1)
+#define ADC1_CFG2 ADC_CFG2_REG(ADC1)
+#define ADC1_RA ADC_R_REG(ADC1,0)
+#define ADC1_RB ADC_R_REG(ADC1,1)
+#define ADC1_CV1 ADC_CV1_REG(ADC1)
+#define ADC1_CV2 ADC_CV2_REG(ADC1)
+#define ADC1_SC2 ADC_SC2_REG(ADC1)
+#define ADC1_SC3 ADC_SC3_REG(ADC1)
+#define ADC1_OFS ADC_OFS_REG(ADC1)
+#define ADC1_PG ADC_PG_REG(ADC1)
+#define ADC1_MG ADC_MG_REG(ADC1)
+#define ADC1_CLPD ADC_CLPD_REG(ADC1)
+#define ADC1_CLPS ADC_CLPS_REG(ADC1)
+#define ADC1_CLP4 ADC_CLP4_REG(ADC1)
+#define ADC1_CLP3 ADC_CLP3_REG(ADC1)
+#define ADC1_CLP2 ADC_CLP2_REG(ADC1)
+#define ADC1_CLP1 ADC_CLP1_REG(ADC1)
+#define ADC1_CLP0 ADC_CLP0_REG(ADC1)
+#define ADC1_CLMD ADC_CLMD_REG(ADC1)
+#define ADC1_CLMS ADC_CLMS_REG(ADC1)
+#define ADC1_CLM4 ADC_CLM4_REG(ADC1)
+#define ADC1_CLM3 ADC_CLM3_REG(ADC1)
+#define ADC1_CLM2 ADC_CLM2_REG(ADC1)
+#define ADC1_CLM1 ADC_CLM1_REG(ADC1)
+#define ADC1_CLM0 ADC_CLM0_REG(ADC1)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
+#define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
+#define ADC0_R(index) ADC_R_REG(ADC0,index)
+#define ADC1_R(index) ADC_R_REG(ADC1,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type, *CMP_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CMP - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register accessors */
+#define CMP_CR0_REG(base) ((base)->CR0)
+#define CMP_CR1_REG(base) ((base)->CR1)
+#define CMP_FPR_REG(base) ((base)->FPR)
+#define CMP_SCR_REG(base) ((base)->SCR)
+#define CMP_DACCR_REG(base) ((base)->DACCR)
+#define CMP_MUXCR_REG(base) ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_TRIGM_MASK 0x20u
+#define CMP_CR1_TRIGM_SHIFT 5
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+#define CMP0_BASE_PTR (CMP0)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1 ((CMP_Type *)CMP1_BASE)
+#define CMP1_BASE_PTR (CMP1)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS { CMP0, CMP1 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- CMP - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register instance definitions */
+/* CMP0 */
+#define CMP0_CR0 CMP_CR0_REG(CMP0)
+#define CMP0_CR1 CMP_CR1_REG(CMP0)
+#define CMP0_FPR CMP_FPR_REG(CMP0)
+#define CMP0_SCR CMP_SCR_REG(CMP0)
+#define CMP0_DACCR CMP_DACCR_REG(CMP0)
+#define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
+/* CMP1 */
+#define CMP1_CR0 CMP_CR0_REG(CMP1)
+#define CMP1_CR1 CMP_CR1_REG(CMP1)
+#define CMP1_FPR CMP_FPR_REG(CMP1)
+#define CMP1_SCR CMP_SCR_REG(CMP1)
+#define CMP1_DACCR CMP_DACCR_REG(CMP1)
+#define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
+ __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
+ } ACCESS16BIT;
+ __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
+ struct { /* offset: 0x0 */
+ __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
+ __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
+ __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
+ __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
+ } ACCESS8BIT;
+ };
+ union { /* offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
+ __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
+ } GPOLY_ACCESS16BIT;
+ __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
+ struct { /* offset: 0x4 */
+ __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
+ __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
+ __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
+ __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
+ } GPOLY_ACCESS8BIT;
+ };
+ union { /* offset: 0x8 */
+ __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
+ struct { /* offset: 0x8 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
+ } CTRL_ACCESS8BIT;
+ };
+} CRC_Type, *CRC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CRC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register accessors */
+#define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
+#define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
+#define CRC_DATA_REG(base) ((base)->DATA)
+#define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
+#define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
+#define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
+#define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
+#define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
+#define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
+#define CRC_GPOLY_REG(base) ((base)->GPOLY)
+#define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
+#define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
+#define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
+#define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
+#define CRC_CTRL_REG(base) ((base)->CTRL)
+#define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/* DATAL Bit Fields */
+#define CRC_DATAL_DATAL_MASK 0xFFFFu
+#define CRC_DATAL_DATAL_SHIFT 0
+#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
+/* DATAH Bit Fields */
+#define CRC_DATAH_DATAH_MASK 0xFFFFu
+#define CRC_DATAH_DATAH_SHIFT 0
+#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
+/* DATA Bit Fields */
+#define CRC_DATA_LL_MASK 0xFFu
+#define CRC_DATA_LL_SHIFT 0
+#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK 0xFF00u
+#define CRC_DATA_LU_SHIFT 8
+#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK 0xFF0000u
+#define CRC_DATA_HL_SHIFT 16
+#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK 0xFF000000u
+#define CRC_DATA_HU_SHIFT 24
+#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
+/* DATALL Bit Fields */
+#define CRC_DATALL_DATALL_MASK 0xFFu
+#define CRC_DATALL_DATALL_SHIFT 0
+#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
+/* DATALU Bit Fields */
+#define CRC_DATALU_DATALU_MASK 0xFFu
+#define CRC_DATALU_DATALU_SHIFT 0
+#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
+/* DATAHL Bit Fields */
+#define CRC_DATAHL_DATAHL_MASK 0xFFu
+#define CRC_DATAHL_DATAHL_SHIFT 0
+#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
+/* DATAHU Bit Fields */
+#define CRC_DATAHU_DATAHU_MASK 0xFFu
+#define CRC_DATAHU_DATAHU_SHIFT 0
+#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT 0
+#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT 0
+#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK 0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT 0
+#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT 16
+#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT 0
+#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT 0
+#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT 0
+#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT 0
+#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK 0x1000000u
+#define CRC_CTRL_TCRC_SHIFT 24
+#define CRC_CTRL_WAS_MASK 0x2000000u
+#define CRC_CTRL_WAS_SHIFT 25
+#define CRC_CTRL_FXOR_MASK 0x4000000u
+#define CRC_CTRL_FXOR_SHIFT 26
+#define CRC_CTRL_TOTR_MASK 0x30000000u
+#define CRC_CTRL_TOTR_SHIFT 28
+#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK 0xC0000000u
+#define CRC_CTRL_TOT_SHIFT 30
+#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+/* CTRLHU Bit Fields */
+#define CRC_CTRLHU_TCRC_MASK 0x1u
+#define CRC_CTRLHU_TCRC_SHIFT 0
+#define CRC_CTRLHU_WAS_MASK 0x2u
+#define CRC_CTRLHU_WAS_SHIFT 1
+#define CRC_CTRLHU_FXOR_MASK 0x4u
+#define CRC_CTRLHU_FXOR_SHIFT 2
+#define CRC_CTRLHU_TOTR_MASK 0x30u
+#define CRC_CTRLHU_TOTR_SHIFT 4
+#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK 0xC0u
+#define CRC_CTRLHU_TOT_SHIFT 6
+#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0 ((CRC_Type *)CRC_BASE)
+#define CRC_BASE_PTR (CRC0)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS { CRC0 }
+
+/* ----------------------------------------------------------------------------
+ -- CRC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
+ * @{
+ */
+
+
+/* CRC - Register instance definitions */
+/* CRC */
+#define CRC_DATA CRC_DATA_REG(CRC0)
+#define CRC_DATAL CRC_DATAL_REG(CRC0)
+#define CRC_DATALL CRC_DATALL_REG(CRC0)
+#define CRC_DATALU CRC_DATALU_REG(CRC0)
+#define CRC_DATAH CRC_DATAH_REG(CRC0)
+#define CRC_DATAHL CRC_DATAHL_REG(CRC0)
+#define CRC_DATAHU CRC_DATAHU_REG(CRC0)
+#define CRC_GPOLY CRC_GPOLY_REG(CRC0)
+#define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
+#define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
+#define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
+#define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
+#define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
+#define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
+#define CRC_CTRL CRC_CTRL_REG(CRC0)
+#define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[16];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DAC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
+#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
+#define DAC_SR_REG(base) ((base)->SR)
+#define DAC_C0_REG(base) ((base)->C0)
+#define DAC_C1_REG(base) ((base)->C1)
+#define DAC_C2_REG(base) ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+#define DAC_SR_DACBFWMF_MASK 0x4u
+#define DAC_SR_DACBFWMF_SHIFT 2
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_DACBWIEN_MASK 0x4u
+#define DAC_C0_DACBWIEN_SHIFT 2
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x6u
+#define DAC_C1_DACBFMD_SHIFT 1
+#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK 0x18u
+#define DAC_C1_DACBFWM_SHIFT 3
+#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0xFu
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK 0xF0u
+#define DAC_C2_DACBFRP_SHIFT 4
+#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+#define DAC0_BASE_PTR (DAC0)
+/** Peripheral DAC1 base address */
+#define DAC1_BASE (0x40028000u)
+/** Peripheral DAC1 base pointer */
+#define DAC1 ((DAC_Type *)DAC1_BASE)
+#define DAC1_BASE_PTR (DAC1)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS { DAC0, DAC1 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- DAC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register instance definitions */
+/* DAC0 */
+#define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
+#define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
+#define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
+#define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
+#define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
+#define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
+#define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
+#define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
+#define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
+#define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
+#define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
+#define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
+#define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
+#define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
+#define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
+#define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
+#define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
+#define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
+#define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
+#define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
+#define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
+#define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
+#define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
+#define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
+#define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
+#define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
+#define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
+#define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
+#define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
+#define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
+#define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
+#define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
+#define DAC0_SR DAC_SR_REG(DAC0)
+#define DAC0_C0 DAC_C0_REG(DAC0)
+#define DAC0_C1 DAC_C1_REG(DAC0)
+#define DAC0_C2 DAC_C2_REG(DAC0)
+/* DAC1 */
+#define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
+#define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
+#define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
+#define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
+#define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
+#define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
+#define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
+#define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
+#define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
+#define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
+#define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
+#define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
+#define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
+#define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
+#define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
+#define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
+#define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
+#define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
+#define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
+#define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
+#define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
+#define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
+#define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
+#define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
+#define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
+#define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
+#define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
+#define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
+#define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
+#define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
+#define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
+#define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
+#define DAC1_SR DAC_SR_REG(DAC1)
+#define DAC1_C0 DAC_C0_REG(DAC1)
+#define DAC1_C1 DAC_C1_REG(DAC1)
+#define DAC1_C2 DAC_C2_REG(DAC1)
+
+/* DAC - Register array accessors */
+#define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
+#define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
+#define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
+#define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< Control Register, offset: 0x0 */
+ __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
+ __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+ __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
+ __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
+ __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
+ __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
+ __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
+ __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
+ __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
+ uint8_t RESERVED_4[4];
+ __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
+ uint8_t RESERVED_5[12];
+ __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
+ uint8_t RESERVED_6[184];
+ __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
+ __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
+ __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
+ __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
+ __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
+ __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
+ __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
+ __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
+ __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
+ __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
+ __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
+ __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
+ __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
+ __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
+ __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
+ __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
+ uint8_t RESERVED_7[3824];
+ struct { /* offset: 0x1000, array step: 0x20 */
+ __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+ __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+ __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+ union { /* offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+ __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+ };
+ __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+ __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+ __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+ union { /* offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+ __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+ };
+ __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+ __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+ union { /* offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+ __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+ };
+ } TCD[16];
+} DMA_Type, *DMA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DMA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register accessors */
+#define DMA_CR_REG(base) ((base)->CR)
+#define DMA_ES_REG(base) ((base)->ES)
+#define DMA_ERQ_REG(base) ((base)->ERQ)
+#define DMA_EEI_REG(base) ((base)->EEI)
+#define DMA_CEEI_REG(base) ((base)->CEEI)
+#define DMA_SEEI_REG(base) ((base)->SEEI)
+#define DMA_CERQ_REG(base) ((base)->CERQ)
+#define DMA_SERQ_REG(base) ((base)->SERQ)
+#define DMA_CDNE_REG(base) ((base)->CDNE)
+#define DMA_SSRT_REG(base) ((base)->SSRT)
+#define DMA_CERR_REG(base) ((base)->CERR)
+#define DMA_CINT_REG(base) ((base)->CINT)
+#define DMA_INT_REG(base) ((base)->INT)
+#define DMA_ERR_REG(base) ((base)->ERR)
+#define DMA_HRS_REG(base) ((base)->HRS)
+#define DMA_EARS_REG(base) ((base)->EARS)
+#define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
+#define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
+#define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
+#define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
+#define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
+#define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
+#define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
+#define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
+#define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
+#define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
+#define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
+#define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
+#define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
+#define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
+#define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
+#define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
+#define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
+#define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
+#define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
+#define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
+#define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
+#define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
+#define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
+#define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
+#define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
+#define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
+#define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
+#define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
+#define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
+#define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
+#define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK 0x2u
+#define DMA_CR_EDBG_SHIFT 1
+#define DMA_CR_ERCA_MASK 0x4u
+#define DMA_CR_ERCA_SHIFT 2
+#define DMA_CR_HOE_MASK 0x10u
+#define DMA_CR_HOE_SHIFT 4
+#define DMA_CR_HALT_MASK 0x20u
+#define DMA_CR_HALT_SHIFT 5
+#define DMA_CR_CLM_MASK 0x40u
+#define DMA_CR_CLM_SHIFT 6
+#define DMA_CR_EMLM_MASK 0x80u
+#define DMA_CR_EMLM_SHIFT 7
+#define DMA_CR_ECX_MASK 0x10000u
+#define DMA_CR_ECX_SHIFT 16
+#define DMA_CR_CX_MASK 0x20000u
+#define DMA_CR_CX_SHIFT 17
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK 0x1u
+#define DMA_ES_DBE_SHIFT 0
+#define DMA_ES_SBE_MASK 0x2u
+#define DMA_ES_SBE_SHIFT 1
+#define DMA_ES_SGE_MASK 0x4u
+#define DMA_ES_SGE_SHIFT 2
+#define DMA_ES_NCE_MASK 0x8u
+#define DMA_ES_NCE_SHIFT 3
+#define DMA_ES_DOE_MASK 0x10u
+#define DMA_ES_DOE_SHIFT 4
+#define DMA_ES_DAE_MASK 0x20u
+#define DMA_ES_DAE_SHIFT 5
+#define DMA_ES_SOE_MASK 0x40u
+#define DMA_ES_SOE_SHIFT 6
+#define DMA_ES_SAE_MASK 0x80u
+#define DMA_ES_SAE_SHIFT 7
+#define DMA_ES_ERRCHN_MASK 0xF00u
+#define DMA_ES_ERRCHN_SHIFT 8
+#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK 0x4000u
+#define DMA_ES_CPE_SHIFT 14
+#define DMA_ES_ECX_MASK 0x10000u
+#define DMA_ES_ECX_SHIFT 16
+#define DMA_ES_VLD_MASK 0x80000000u
+#define DMA_ES_VLD_SHIFT 31
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK 0x1u
+#define DMA_ERQ_ERQ0_SHIFT 0
+#define DMA_ERQ_ERQ1_MASK 0x2u
+#define DMA_ERQ_ERQ1_SHIFT 1
+#define DMA_ERQ_ERQ2_MASK 0x4u
+#define DMA_ERQ_ERQ2_SHIFT 2
+#define DMA_ERQ_ERQ3_MASK 0x8u
+#define DMA_ERQ_ERQ3_SHIFT 3
+#define DMA_ERQ_ERQ4_MASK 0x10u
+#define DMA_ERQ_ERQ4_SHIFT 4
+#define DMA_ERQ_ERQ5_MASK 0x20u
+#define DMA_ERQ_ERQ5_SHIFT 5
+#define DMA_ERQ_ERQ6_MASK 0x40u
+#define DMA_ERQ_ERQ6_SHIFT 6
+#define DMA_ERQ_ERQ7_MASK 0x80u
+#define DMA_ERQ_ERQ7_SHIFT 7
+#define DMA_ERQ_ERQ8_MASK 0x100u
+#define DMA_ERQ_ERQ8_SHIFT 8
+#define DMA_ERQ_ERQ9_MASK 0x200u
+#define DMA_ERQ_ERQ9_SHIFT 9
+#define DMA_ERQ_ERQ10_MASK 0x400u
+#define DMA_ERQ_ERQ10_SHIFT 10
+#define DMA_ERQ_ERQ11_MASK 0x800u
+#define DMA_ERQ_ERQ11_SHIFT 11
+#define DMA_ERQ_ERQ12_MASK 0x1000u
+#define DMA_ERQ_ERQ12_SHIFT 12
+#define DMA_ERQ_ERQ13_MASK 0x2000u
+#define DMA_ERQ_ERQ13_SHIFT 13
+#define DMA_ERQ_ERQ14_MASK 0x4000u
+#define DMA_ERQ_ERQ14_SHIFT 14
+#define DMA_ERQ_ERQ15_MASK 0x8000u
+#define DMA_ERQ_ERQ15_SHIFT 15
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK 0x1u
+#define DMA_EEI_EEI0_SHIFT 0
+#define DMA_EEI_EEI1_MASK 0x2u
+#define DMA_EEI_EEI1_SHIFT 1
+#define DMA_EEI_EEI2_MASK 0x4u
+#define DMA_EEI_EEI2_SHIFT 2
+#define DMA_EEI_EEI3_MASK 0x8u
+#define DMA_EEI_EEI3_SHIFT 3
+#define DMA_EEI_EEI4_MASK 0x10u
+#define DMA_EEI_EEI4_SHIFT 4
+#define DMA_EEI_EEI5_MASK 0x20u
+#define DMA_EEI_EEI5_SHIFT 5
+#define DMA_EEI_EEI6_MASK 0x40u
+#define DMA_EEI_EEI6_SHIFT 6
+#define DMA_EEI_EEI7_MASK 0x80u
+#define DMA_EEI_EEI7_SHIFT 7
+#define DMA_EEI_EEI8_MASK 0x100u
+#define DMA_EEI_EEI8_SHIFT 8
+#define DMA_EEI_EEI9_MASK 0x200u
+#define DMA_EEI_EEI9_SHIFT 9
+#define DMA_EEI_EEI10_MASK 0x400u
+#define DMA_EEI_EEI10_SHIFT 10
+#define DMA_EEI_EEI11_MASK 0x800u
+#define DMA_EEI_EEI11_SHIFT 11
+#define DMA_EEI_EEI12_MASK 0x1000u
+#define DMA_EEI_EEI12_SHIFT 12
+#define DMA_EEI_EEI13_MASK 0x2000u
+#define DMA_EEI_EEI13_SHIFT 13
+#define DMA_EEI_EEI14_MASK 0x4000u
+#define DMA_EEI_EEI14_SHIFT 14
+#define DMA_EEI_EEI15_MASK 0x8000u
+#define DMA_EEI_EEI15_SHIFT 15
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK 0xFu
+#define DMA_CEEI_CEEI_SHIFT 0
+#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK 0x40u
+#define DMA_CEEI_CAEE_SHIFT 6
+#define DMA_CEEI_NOP_MASK 0x80u
+#define DMA_CEEI_NOP_SHIFT 7
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK 0xFu
+#define DMA_SEEI_SEEI_SHIFT 0
+#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK 0x40u
+#define DMA_SEEI_SAEE_SHIFT 6
+#define DMA_SEEI_NOP_MASK 0x80u
+#define DMA_SEEI_NOP_SHIFT 7
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK 0xFu
+#define DMA_CERQ_CERQ_SHIFT 0
+#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK 0x40u
+#define DMA_CERQ_CAER_SHIFT 6
+#define DMA_CERQ_NOP_MASK 0x80u
+#define DMA_CERQ_NOP_SHIFT 7
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK 0xFu
+#define DMA_SERQ_SERQ_SHIFT 0
+#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK 0x40u
+#define DMA_SERQ_SAER_SHIFT 6
+#define DMA_SERQ_NOP_MASK 0x80u
+#define DMA_SERQ_NOP_SHIFT 7
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK 0xFu
+#define DMA_CDNE_CDNE_SHIFT 0
+#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK 0x40u
+#define DMA_CDNE_CADN_SHIFT 6
+#define DMA_CDNE_NOP_MASK 0x80u
+#define DMA_CDNE_NOP_SHIFT 7
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK 0xFu
+#define DMA_SSRT_SSRT_SHIFT 0
+#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK 0x40u
+#define DMA_SSRT_SAST_SHIFT 6
+#define DMA_SSRT_NOP_MASK 0x80u
+#define DMA_SSRT_NOP_SHIFT 7
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK 0xFu
+#define DMA_CERR_CERR_SHIFT 0
+#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK 0x40u
+#define DMA_CERR_CAEI_SHIFT 6
+#define DMA_CERR_NOP_MASK 0x80u
+#define DMA_CERR_NOP_SHIFT 7
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK 0xFu
+#define DMA_CINT_CINT_SHIFT 0
+#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK 0x40u
+#define DMA_CINT_CAIR_SHIFT 6
+#define DMA_CINT_NOP_MASK 0x80u
+#define DMA_CINT_NOP_SHIFT 7
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK 0x1u
+#define DMA_INT_INT0_SHIFT 0
+#define DMA_INT_INT1_MASK 0x2u
+#define DMA_INT_INT1_SHIFT 1
+#define DMA_INT_INT2_MASK 0x4u
+#define DMA_INT_INT2_SHIFT 2
+#define DMA_INT_INT3_MASK 0x8u
+#define DMA_INT_INT3_SHIFT 3
+#define DMA_INT_INT4_MASK 0x10u
+#define DMA_INT_INT4_SHIFT 4
+#define DMA_INT_INT5_MASK 0x20u
+#define DMA_INT_INT5_SHIFT 5
+#define DMA_INT_INT6_MASK 0x40u
+#define DMA_INT_INT6_SHIFT 6
+#define DMA_INT_INT7_MASK 0x80u
+#define DMA_INT_INT7_SHIFT 7
+#define DMA_INT_INT8_MASK 0x100u
+#define DMA_INT_INT8_SHIFT 8
+#define DMA_INT_INT9_MASK 0x200u
+#define DMA_INT_INT9_SHIFT 9
+#define DMA_INT_INT10_MASK 0x400u
+#define DMA_INT_INT10_SHIFT 10
+#define DMA_INT_INT11_MASK 0x800u
+#define DMA_INT_INT11_SHIFT 11
+#define DMA_INT_INT12_MASK 0x1000u
+#define DMA_INT_INT12_SHIFT 12
+#define DMA_INT_INT13_MASK 0x2000u
+#define DMA_INT_INT13_SHIFT 13
+#define DMA_INT_INT14_MASK 0x4000u
+#define DMA_INT_INT14_SHIFT 14
+#define DMA_INT_INT15_MASK 0x8000u
+#define DMA_INT_INT15_SHIFT 15
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK 0x1u
+#define DMA_ERR_ERR0_SHIFT 0
+#define DMA_ERR_ERR1_MASK 0x2u
+#define DMA_ERR_ERR1_SHIFT 1
+#define DMA_ERR_ERR2_MASK 0x4u
+#define DMA_ERR_ERR2_SHIFT 2
+#define DMA_ERR_ERR3_MASK 0x8u
+#define DMA_ERR_ERR3_SHIFT 3
+#define DMA_ERR_ERR4_MASK 0x10u
+#define DMA_ERR_ERR4_SHIFT 4
+#define DMA_ERR_ERR5_MASK 0x20u
+#define DMA_ERR_ERR5_SHIFT 5
+#define DMA_ERR_ERR6_MASK 0x40u
+#define DMA_ERR_ERR6_SHIFT 6
+#define DMA_ERR_ERR7_MASK 0x80u
+#define DMA_ERR_ERR7_SHIFT 7
+#define DMA_ERR_ERR8_MASK 0x100u
+#define DMA_ERR_ERR8_SHIFT 8
+#define DMA_ERR_ERR9_MASK 0x200u
+#define DMA_ERR_ERR9_SHIFT 9
+#define DMA_ERR_ERR10_MASK 0x400u
+#define DMA_ERR_ERR10_SHIFT 10
+#define DMA_ERR_ERR11_MASK 0x800u
+#define DMA_ERR_ERR11_SHIFT 11
+#define DMA_ERR_ERR12_MASK 0x1000u
+#define DMA_ERR_ERR12_SHIFT 12
+#define DMA_ERR_ERR13_MASK 0x2000u
+#define DMA_ERR_ERR13_SHIFT 13
+#define DMA_ERR_ERR14_MASK 0x4000u
+#define DMA_ERR_ERR14_SHIFT 14
+#define DMA_ERR_ERR15_MASK 0x8000u
+#define DMA_ERR_ERR15_SHIFT 15
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK 0x1u
+#define DMA_HRS_HRS0_SHIFT 0
+#define DMA_HRS_HRS1_MASK 0x2u
+#define DMA_HRS_HRS1_SHIFT 1
+#define DMA_HRS_HRS2_MASK 0x4u
+#define DMA_HRS_HRS2_SHIFT 2
+#define DMA_HRS_HRS3_MASK 0x8u
+#define DMA_HRS_HRS3_SHIFT 3
+#define DMA_HRS_HRS4_MASK 0x10u
+#define DMA_HRS_HRS4_SHIFT 4
+#define DMA_HRS_HRS5_MASK 0x20u
+#define DMA_HRS_HRS5_SHIFT 5
+#define DMA_HRS_HRS6_MASK 0x40u
+#define DMA_HRS_HRS6_SHIFT 6
+#define DMA_HRS_HRS7_MASK 0x80u
+#define DMA_HRS_HRS7_SHIFT 7
+#define DMA_HRS_HRS8_MASK 0x100u
+#define DMA_HRS_HRS8_SHIFT 8
+#define DMA_HRS_HRS9_MASK 0x200u
+#define DMA_HRS_HRS9_SHIFT 9
+#define DMA_HRS_HRS10_MASK 0x400u
+#define DMA_HRS_HRS10_SHIFT 10
+#define DMA_HRS_HRS11_MASK 0x800u
+#define DMA_HRS_HRS11_SHIFT 11
+#define DMA_HRS_HRS12_MASK 0x1000u
+#define DMA_HRS_HRS12_SHIFT 12
+#define DMA_HRS_HRS13_MASK 0x2000u
+#define DMA_HRS_HRS13_SHIFT 13
+#define DMA_HRS_HRS14_MASK 0x4000u
+#define DMA_HRS_HRS14_SHIFT 14
+#define DMA_HRS_HRS15_MASK 0x8000u
+#define DMA_HRS_HRS15_SHIFT 15
+/* EARS Bit Fields */
+#define DMA_EARS_EDREQ_0_MASK 0x1u
+#define DMA_EARS_EDREQ_0_SHIFT 0
+#define DMA_EARS_EDREQ_1_MASK 0x2u
+#define DMA_EARS_EDREQ_1_SHIFT 1
+#define DMA_EARS_EDREQ_2_MASK 0x4u
+#define DMA_EARS_EDREQ_2_SHIFT 2
+#define DMA_EARS_EDREQ_3_MASK 0x8u
+#define DMA_EARS_EDREQ_3_SHIFT 3
+#define DMA_EARS_EDREQ_4_MASK 0x10u
+#define DMA_EARS_EDREQ_4_SHIFT 4
+#define DMA_EARS_EDREQ_5_MASK 0x20u
+#define DMA_EARS_EDREQ_5_SHIFT 5
+#define DMA_EARS_EDREQ_6_MASK 0x40u
+#define DMA_EARS_EDREQ_6_SHIFT 6
+#define DMA_EARS_EDREQ_7_MASK 0x80u
+#define DMA_EARS_EDREQ_7_SHIFT 7
+#define DMA_EARS_EDREQ_8_MASK 0x100u
+#define DMA_EARS_EDREQ_8_SHIFT 8
+#define DMA_EARS_EDREQ_9_MASK 0x200u
+#define DMA_EARS_EDREQ_9_SHIFT 9
+#define DMA_EARS_EDREQ_10_MASK 0x400u
+#define DMA_EARS_EDREQ_10_SHIFT 10
+#define DMA_EARS_EDREQ_11_MASK 0x800u
+#define DMA_EARS_EDREQ_11_SHIFT 11
+#define DMA_EARS_EDREQ_12_MASK 0x1000u
+#define DMA_EARS_EDREQ_12_SHIFT 12
+#define DMA_EARS_EDREQ_13_MASK 0x2000u
+#define DMA_EARS_EDREQ_13_SHIFT 13
+#define DMA_EARS_EDREQ_14_MASK 0x4000u
+#define DMA_EARS_EDREQ_14_SHIFT 14
+#define DMA_EARS_EDREQ_15_MASK 0x8000u
+#define DMA_EARS_EDREQ_15_SHIFT 15
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK 0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT 0
+#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK 0x40u
+#define DMA_DCHPRI3_DPA_SHIFT 6
+#define DMA_DCHPRI3_ECP_MASK 0x80u
+#define DMA_DCHPRI3_ECP_SHIFT 7
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK 0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT 0
+#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK 0x40u
+#define DMA_DCHPRI2_DPA_SHIFT 6
+#define DMA_DCHPRI2_ECP_MASK 0x80u
+#define DMA_DCHPRI2_ECP_SHIFT 7
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK 0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT 0
+#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK 0x40u
+#define DMA_DCHPRI1_DPA_SHIFT 6
+#define DMA_DCHPRI1_ECP_MASK 0x80u
+#define DMA_DCHPRI1_ECP_SHIFT 7
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK 0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT 0
+#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK 0x40u
+#define DMA_DCHPRI0_DPA_SHIFT 6
+#define DMA_DCHPRI0_ECP_MASK 0x80u
+#define DMA_DCHPRI0_ECP_SHIFT 7
+/* DCHPRI7 Bit Fields */
+#define DMA_DCHPRI7_CHPRI_MASK 0xFu
+#define DMA_DCHPRI7_CHPRI_SHIFT 0
+#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK 0x40u
+#define DMA_DCHPRI7_DPA_SHIFT 6
+#define DMA_DCHPRI7_ECP_MASK 0x80u
+#define DMA_DCHPRI7_ECP_SHIFT 7
+/* DCHPRI6 Bit Fields */
+#define DMA_DCHPRI6_CHPRI_MASK 0xFu
+#define DMA_DCHPRI6_CHPRI_SHIFT 0
+#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK 0x40u
+#define DMA_DCHPRI6_DPA_SHIFT 6
+#define DMA_DCHPRI6_ECP_MASK 0x80u
+#define DMA_DCHPRI6_ECP_SHIFT 7
+/* DCHPRI5 Bit Fields */
+#define DMA_DCHPRI5_CHPRI_MASK 0xFu
+#define DMA_DCHPRI5_CHPRI_SHIFT 0
+#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK 0x40u
+#define DMA_DCHPRI5_DPA_SHIFT 6
+#define DMA_DCHPRI5_ECP_MASK 0x80u
+#define DMA_DCHPRI5_ECP_SHIFT 7
+/* DCHPRI4 Bit Fields */
+#define DMA_DCHPRI4_CHPRI_MASK 0xFu
+#define DMA_DCHPRI4_CHPRI_SHIFT 0
+#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK 0x40u
+#define DMA_DCHPRI4_DPA_SHIFT 6
+#define DMA_DCHPRI4_ECP_MASK 0x80u
+#define DMA_DCHPRI4_ECP_SHIFT 7
+/* DCHPRI11 Bit Fields */
+#define DMA_DCHPRI11_CHPRI_MASK 0xFu
+#define DMA_DCHPRI11_CHPRI_SHIFT 0
+#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK 0x40u
+#define DMA_DCHPRI11_DPA_SHIFT 6
+#define DMA_DCHPRI11_ECP_MASK 0x80u
+#define DMA_DCHPRI11_ECP_SHIFT 7
+/* DCHPRI10 Bit Fields */
+#define DMA_DCHPRI10_CHPRI_MASK 0xFu
+#define DMA_DCHPRI10_CHPRI_SHIFT 0
+#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK 0x40u
+#define DMA_DCHPRI10_DPA_SHIFT 6
+#define DMA_DCHPRI10_ECP_MASK 0x80u
+#define DMA_DCHPRI10_ECP_SHIFT 7
+/* DCHPRI9 Bit Fields */
+#define DMA_DCHPRI9_CHPRI_MASK 0xFu
+#define DMA_DCHPRI9_CHPRI_SHIFT 0
+#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK 0x40u
+#define DMA_DCHPRI9_DPA_SHIFT 6
+#define DMA_DCHPRI9_ECP_MASK 0x80u
+#define DMA_DCHPRI9_ECP_SHIFT 7
+/* DCHPRI8 Bit Fields */
+#define DMA_DCHPRI8_CHPRI_MASK 0xFu
+#define DMA_DCHPRI8_CHPRI_SHIFT 0
+#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK 0x40u
+#define DMA_DCHPRI8_DPA_SHIFT 6
+#define DMA_DCHPRI8_ECP_MASK 0x80u
+#define DMA_DCHPRI8_ECP_SHIFT 7
+/* DCHPRI15 Bit Fields */
+#define DMA_DCHPRI15_CHPRI_MASK 0xFu
+#define DMA_DCHPRI15_CHPRI_SHIFT 0
+#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK 0x40u
+#define DMA_DCHPRI15_DPA_SHIFT 6
+#define DMA_DCHPRI15_ECP_MASK 0x80u
+#define DMA_DCHPRI15_ECP_SHIFT 7
+/* DCHPRI14 Bit Fields */
+#define DMA_DCHPRI14_CHPRI_MASK 0xFu
+#define DMA_DCHPRI14_CHPRI_SHIFT 0
+#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK 0x40u
+#define DMA_DCHPRI14_DPA_SHIFT 6
+#define DMA_DCHPRI14_ECP_MASK 0x80u
+#define DMA_DCHPRI14_ECP_SHIFT 7
+/* DCHPRI13 Bit Fields */
+#define DMA_DCHPRI13_CHPRI_MASK 0xFu
+#define DMA_DCHPRI13_CHPRI_SHIFT 0
+#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK 0x40u
+#define DMA_DCHPRI13_DPA_SHIFT 6
+#define DMA_DCHPRI13_ECP_MASK 0x80u
+#define DMA_DCHPRI13_ECP_SHIFT 7
+/* DCHPRI12 Bit Fields */
+#define DMA_DCHPRI12_CHPRI_MASK 0xFu
+#define DMA_DCHPRI12_CHPRI_SHIFT 0
+#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK 0x40u
+#define DMA_DCHPRI12_DPA_SHIFT 6
+#define DMA_DCHPRI12_ECP_MASK 0x80u
+#define DMA_DCHPRI12_ECP_SHIFT 7
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT 0
+#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK 0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT 0
+#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK 0x7u
+#define DMA_ATTR_DSIZE_SHIFT 0
+#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK 0xF8u
+#define DMA_ATTR_DMOD_SHIFT 3
+#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK 0x700u
+#define DMA_ATTR_SSIZE_SHIFT 8
+#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK 0xF800u
+#define DMA_ATTR_SMOD_SHIFT 11
+#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
+#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
+#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT 0
+#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT 0
+#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK 0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT 0
+#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT 0
+#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT 15
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT 0
+#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT 15
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
+#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK 0x1u
+#define DMA_CSR_START_SHIFT 0
+#define DMA_CSR_INTMAJOR_MASK 0x2u
+#define DMA_CSR_INTMAJOR_SHIFT 1
+#define DMA_CSR_INTHALF_MASK 0x4u
+#define DMA_CSR_INTHALF_SHIFT 2
+#define DMA_CSR_DREQ_MASK 0x8u
+#define DMA_CSR_DREQ_SHIFT 3
+#define DMA_CSR_ESG_MASK 0x10u
+#define DMA_CSR_ESG_SHIFT 4
+#define DMA_CSR_MAJORELINK_MASK 0x20u
+#define DMA_CSR_MAJORELINK_SHIFT 5
+#define DMA_CSR_ACTIVE_MASK 0x40u
+#define DMA_CSR_ACTIVE_SHIFT 6
+#define DMA_CSR_DONE_MASK 0x80u
+#define DMA_CSR_DONE_SHIFT 7
+#define DMA_CSR_MAJORLINKCH_MASK 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT 8
+#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK 0xC000u
+#define DMA_CSR_BWC_SHIFT 14
+#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT 0
+#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT 15
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT 0
+#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
+#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT 15
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+#define DMA_BASE_PTR (DMA0)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
+#define DMA_ERROR_IRQS { DMA_Error_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- DMA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register instance definitions */
+/* DMA */
+#define DMA_CR DMA_CR_REG(DMA0)
+#define DMA_ES DMA_ES_REG(DMA0)
+#define DMA_ERQ DMA_ERQ_REG(DMA0)
+#define DMA_EEI DMA_EEI_REG(DMA0)
+#define DMA_CEEI DMA_CEEI_REG(DMA0)
+#define DMA_SEEI DMA_SEEI_REG(DMA0)
+#define DMA_CERQ DMA_CERQ_REG(DMA0)
+#define DMA_SERQ DMA_SERQ_REG(DMA0)
+#define DMA_CDNE DMA_CDNE_REG(DMA0)
+#define DMA_SSRT DMA_SSRT_REG(DMA0)
+#define DMA_CERR DMA_CERR_REG(DMA0)
+#define DMA_CINT DMA_CINT_REG(DMA0)
+#define DMA_INT DMA_INT_REG(DMA0)
+#define DMA_ERR DMA_ERR_REG(DMA0)
+#define DMA_HRS DMA_HRS_REG(DMA0)
+#define DMA_EARS DMA_EARS_REG(DMA0)
+#define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
+#define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
+#define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
+#define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
+#define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
+#define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
+#define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
+#define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
+#define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
+#define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
+#define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
+#define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
+#define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
+#define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
+#define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
+#define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
+#define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
+#define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
+#define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
+#define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
+#define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
+#define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
+#define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
+#define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
+#define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
+#define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
+#define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
+#define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
+#define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
+#define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
+#define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
+#define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
+#define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
+#define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
+#define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
+#define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
+#define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
+#define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
+#define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
+#define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
+#define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
+#define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
+#define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
+#define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
+#define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
+#define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
+#define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
+#define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
+#define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
+#define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
+#define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
+#define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
+#define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
+#define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
+#define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
+#define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
+#define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
+#define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
+#define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
+#define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
+#define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
+#define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
+#define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
+#define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
+#define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
+#define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
+#define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
+#define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
+#define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
+#define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
+#define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
+#define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
+#define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
+#define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
+#define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
+#define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
+#define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
+#define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
+#define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
+#define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
+#define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
+#define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
+#define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
+#define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
+#define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
+#define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
+#define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
+#define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
+#define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
+#define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
+#define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
+#define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
+#define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
+#define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
+#define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
+#define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
+#define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
+#define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
+#define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
+#define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
+#define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
+#define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
+#define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
+#define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
+#define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
+#define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
+#define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
+#define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
+#define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
+#define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
+#define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
+#define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
+#define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
+#define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
+#define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
+#define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
+#define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
+#define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
+#define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
+#define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
+#define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
+#define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
+#define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
+#define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
+#define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
+#define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
+#define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
+#define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
+#define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
+#define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
+#define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
+#define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
+#define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
+#define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
+#define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
+#define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
+#define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
+#define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
+#define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
+#define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
+#define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
+#define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
+#define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
+#define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
+#define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
+#define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
+#define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
+#define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
+#define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
+#define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
+#define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
+#define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
+#define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
+#define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
+#define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
+#define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
+#define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
+#define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
+#define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
+#define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
+#define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
+
+/* DMA - Register array accessors */
+#define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
+#define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
+#define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
+#define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
+#define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
+#define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
+#define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
+#define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
+#define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
+#define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
+#define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
+#define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
+#define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
+#define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register accessors */
+#define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
+#define DMAMUX_BASE_PTR (DMAMUX)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS { DMAMUX }
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register instance definitions */
+/* DMAMUX */
+#define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
+#define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
+#define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
+#define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
+#define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
+#define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
+#define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
+#define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
+#define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
+#define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
+#define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
+#define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
+#define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
+#define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
+#define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
+#define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
+
+/* DMAMUX - Register array accessors */
+#define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
+ __O uint8_t SERV; /**< Service Register, offset: 0x1 */
+ __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
+ __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
+} EWM_Type, *EWM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- EWM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register accessors */
+#define EWM_CTRL_REG(base) ((base)->CTRL)
+#define EWM_SERV_REG(base) ((base)->SERV)
+#define EWM_CMPL_REG(base) ((base)->CMPL)
+#define EWM_CMPH_REG(base) ((base)->CMPH)
+#define EWM_CLKPRESCALER_REG(base) ((base)->CLKPRESCALER)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- EWM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK 0x1u
+#define EWM_CTRL_EWMEN_SHIFT 0
+#define EWM_CTRL_ASSIN_MASK 0x2u
+#define EWM_CTRL_ASSIN_SHIFT 1
+#define EWM_CTRL_INEN_MASK 0x4u
+#define EWM_CTRL_INEN_SHIFT 2
+#define EWM_CTRL_INTEN_MASK 0x8u
+#define EWM_CTRL_INTEN_SHIFT 3
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK 0xFFu
+#define EWM_SERV_SERVICE_SHIFT 0
+#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK 0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT 0
+#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK 0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT 0
+#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+/* CLKPRESCALER Bit Fields */
+#define EWM_CLKPRESCALER_CLK_DIV_MASK 0xFFu
+#define EWM_CLKPRESCALER_CLK_DIV_SHIFT 0
+#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x))<<EWM_CLKPRESCALER_CLK_DIV_SHIFT))&EWM_CLKPRESCALER_CLK_DIV_MASK)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM ((EWM_Type *)EWM_BASE)
+#define EWM_BASE_PTR (EWM)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS { Watchdog_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- EWM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
+ * @{
+ */
+
+
+/* EWM - Register instance definitions */
+/* EWM */
+#define EWM_CTRL EWM_CTRL_REG(EWM)
+#define EWM_SERV EWM_SERV_REG(EWM)
+#define EWM_CMPL EWM_CMPL_REG(EWM)
+#define EWM_CMPH EWM_CMPH_REG(EWM)
+#define EWM_CLKPRESCALER EWM_CLKPRESCALER_REG(EWM)
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0xC */
+ __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+ __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+ __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+ } CS[6];
+ uint8_t RESERVED_0[24];
+ __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
+} FB_Type, *FB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register accessors */
+#define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
+#define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
+#define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
+#define FB_CSPMCR_REG(base) ((base)->CSPMCR)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/* CSAR Bit Fields */
+#define FB_CSAR_BA_MASK 0xFFFF0000u
+#define FB_CSAR_BA_SHIFT 16
+#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
+/* CSMR Bit Fields */
+#define FB_CSMR_V_MASK 0x1u
+#define FB_CSMR_V_SHIFT 0
+#define FB_CSMR_WP_MASK 0x100u
+#define FB_CSMR_WP_SHIFT 8
+#define FB_CSMR_BAM_MASK 0xFFFF0000u
+#define FB_CSMR_BAM_SHIFT 16
+#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
+/* CSCR Bit Fields */
+#define FB_CSCR_BSTW_MASK 0x8u
+#define FB_CSCR_BSTW_SHIFT 3
+#define FB_CSCR_BSTR_MASK 0x10u
+#define FB_CSCR_BSTR_SHIFT 4
+#define FB_CSCR_BEM_MASK 0x20u
+#define FB_CSCR_BEM_SHIFT 5
+#define FB_CSCR_PS_MASK 0xC0u
+#define FB_CSCR_PS_SHIFT 6
+#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK 0x100u
+#define FB_CSCR_AA_SHIFT 8
+#define FB_CSCR_BLS_MASK 0x200u
+#define FB_CSCR_BLS_SHIFT 9
+#define FB_CSCR_WS_MASK 0xFC00u
+#define FB_CSCR_WS_SHIFT 10
+#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK 0x30000u
+#define FB_CSCR_WRAH_SHIFT 16
+#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK 0xC0000u
+#define FB_CSCR_RDAH_SHIFT 18
+#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK 0x300000u
+#define FB_CSCR_ASET_SHIFT 20
+#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK 0x400000u
+#define FB_CSCR_EXTS_SHIFT 22
+#define FB_CSCR_SWSEN_MASK 0x800000u
+#define FB_CSCR_SWSEN_SHIFT 23
+#define FB_CSCR_SWS_MASK 0xFC000000u
+#define FB_CSCR_SWS_SHIFT 26
+#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
+/* CSPMCR Bit Fields */
+#define FB_CSPMCR_GROUP5_MASK 0xF000u
+#define FB_CSPMCR_GROUP5_SHIFT 12
+#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK 0xF0000u
+#define FB_CSPMCR_GROUP4_SHIFT 16
+#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK 0xF00000u
+#define FB_CSPMCR_GROUP3_SHIFT 20
+#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK 0xF000000u
+#define FB_CSPMCR_GROUP2_SHIFT 24
+#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK 0xF0000000u
+#define FB_CSPMCR_GROUP1_SHIFT 28
+#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB ((FB_Type *)FB_BASE)
+#define FB_BASE_PTR (FB)
+/** Array initializer of FB peripheral base addresses */
+#define FB_BASE_ADDRS { FB_BASE }
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASE_PTRS { FB }
+
+/* ----------------------------------------------------------------------------
+ -- FB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
+ * @{
+ */
+
+
+/* FB - Register instance definitions */
+/* FB */
+#define FB_CSAR0 FB_CSAR_REG(FB,0)
+#define FB_CSMR0 FB_CSMR_REG(FB,0)
+#define FB_CSCR0 FB_CSCR_REG(FB,0)
+#define FB_CSAR1 FB_CSAR_REG(FB,1)
+#define FB_CSMR1 FB_CSMR_REG(FB,1)
+#define FB_CSCR1 FB_CSCR_REG(FB,1)
+#define FB_CSAR2 FB_CSAR_REG(FB,2)
+#define FB_CSMR2 FB_CSMR_REG(FB,2)
+#define FB_CSCR2 FB_CSCR_REG(FB,2)
+#define FB_CSAR3 FB_CSAR_REG(FB,3)
+#define FB_CSMR3 FB_CSMR_REG(FB,3)
+#define FB_CSCR3 FB_CSCR_REG(FB,3)
+#define FB_CSAR4 FB_CSAR_REG(FB,4)
+#define FB_CSMR4 FB_CSMR_REG(FB,4)
+#define FB_CSCR4 FB_CSCR_REG(FB,4)
+#define FB_CSAR5 FB_CSAR_REG(FB,5)
+#define FB_CSMR5 FB_CSMR_REG(FB,5)
+#define FB_CSCR5 FB_CSCR_REG(FB,5)
+#define FB_CSPMCR FB_CSPMCR_REG(FB)
+
+/* FB - Register array accessors */
+#define FB_CSAR(index) FB_CSAR_REG(FB,index)
+#define FB_CSMR(index) FB_CSMR_REG(FB,index)
+#define FB_CSCR(index) FB_CSCR_REG(FB,index)
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
+ __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
+ __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
+ uint8_t RESERVED_0[244];
+ __IO uint32_t TAGVDW0S[8]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
+ __IO uint32_t TAGVDW1S[8]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
+ __IO uint32_t TAGVDW2S[8]; /**< Cache Tag Storage, array offset: 0x140, array step: 0x4 */
+ __IO uint32_t TAGVDW3S[8]; /**< Cache Tag Storage, array offset: 0x160, array step: 0x4 */
+ uint8_t RESERVED_1[128];
+ struct { /* offset: 0x200, array step: index*0x40, index2*0x8 */
+ __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
+ __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
+ } SET[4][8];
+} FMC_Type, *FMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register accessors */
+#define FMC_PFAPR_REG(base) ((base)->PFAPR)
+#define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
+#define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
+#define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
+#define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
+#define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
+#define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
+#define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
+#define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK 0x3u
+#define FMC_PFAPR_M0AP_SHIFT 0
+#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK 0xCu
+#define FMC_PFAPR_M1AP_SHIFT 2
+#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK 0x30u
+#define FMC_PFAPR_M2AP_SHIFT 4
+#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK 0xC0u
+#define FMC_PFAPR_M3AP_SHIFT 6
+#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK 0x300u
+#define FMC_PFAPR_M4AP_SHIFT 8
+#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK 0xC00u
+#define FMC_PFAPR_M5AP_SHIFT 10
+#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK 0x3000u
+#define FMC_PFAPR_M6AP_SHIFT 12
+#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK 0xC000u
+#define FMC_PFAPR_M7AP_SHIFT 14
+#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK 0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT 16
+#define FMC_PFAPR_M1PFD_MASK 0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT 17
+#define FMC_PFAPR_M2PFD_MASK 0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT 18
+#define FMC_PFAPR_M3PFD_MASK 0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT 19
+#define FMC_PFAPR_M4PFD_MASK 0x100000u
+#define FMC_PFAPR_M4PFD_SHIFT 20
+#define FMC_PFAPR_M5PFD_MASK 0x200000u
+#define FMC_PFAPR_M5PFD_SHIFT 21
+#define FMC_PFAPR_M6PFD_MASK 0x400000u
+#define FMC_PFAPR_M6PFD_SHIFT 22
+#define FMC_PFAPR_M7PFD_MASK 0x800000u
+#define FMC_PFAPR_M7PFD_SHIFT 23
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK 0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT 0
+#define FMC_PFB0CR_B0IPE_MASK 0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT 1
+#define FMC_PFB0CR_B0DPE_MASK 0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT 2
+#define FMC_PFB0CR_B0ICE_MASK 0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT 3
+#define FMC_PFB0CR_B0DCE_MASK 0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT 4
+#define FMC_PFB0CR_CRC_MASK 0xE0u
+#define FMC_PFB0CR_CRC_SHIFT 5
+#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK 0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT 17
+#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK 0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT 19
+#define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT 20
+#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT 24
+#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT 28
+#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* PFB1CR Bit Fields */
+#define FMC_PFB1CR_B1SEBE_MASK 0x1u
+#define FMC_PFB1CR_B1SEBE_SHIFT 0
+#define FMC_PFB1CR_B1IPE_MASK 0x2u
+#define FMC_PFB1CR_B1IPE_SHIFT 1
+#define FMC_PFB1CR_B1DPE_MASK 0x4u
+#define FMC_PFB1CR_B1DPE_SHIFT 2
+#define FMC_PFB1CR_B1ICE_MASK 0x8u
+#define FMC_PFB1CR_B1ICE_SHIFT 3
+#define FMC_PFB1CR_B1DCE_MASK 0x10u
+#define FMC_PFB1CR_B1DCE_SHIFT 4
+#define FMC_PFB1CR_B1MW_MASK 0x60000u
+#define FMC_PFB1CR_B1MW_SHIFT 17
+#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
+#define FMC_PFB1CR_B1RWSC_SHIFT 28
+#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
+/* TAGVDW0S Bit Fields */
+#define FMC_TAGVDW0S_valid_MASK 0x1u
+#define FMC_TAGVDW0S_valid_SHIFT 0
+#define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW0S_tag_SHIFT 5
+#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
+/* TAGVDW1S Bit Fields */
+#define FMC_TAGVDW1S_valid_MASK 0x1u
+#define FMC_TAGVDW1S_valid_SHIFT 0
+#define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW1S_tag_SHIFT 5
+#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
+/* TAGVDW2S Bit Fields */
+#define FMC_TAGVDW2S_valid_MASK 0x1u
+#define FMC_TAGVDW2S_valid_SHIFT 0
+#define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW2S_tag_SHIFT 5
+#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
+/* TAGVDW3S Bit Fields */
+#define FMC_TAGVDW3S_valid_MASK 0x1u
+#define FMC_TAGVDW3S_valid_SHIFT 0
+#define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
+#define FMC_TAGVDW3S_tag_SHIFT 5
+#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
+/* DATA_U Bit Fields */
+#define FMC_DATA_U_data_MASK 0xFFFFFFFFu
+#define FMC_DATA_U_data_SHIFT 0
+#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
+/* DATA_L Bit Fields */
+#define FMC_DATA_L_data_MASK 0xFFFFFFFFu
+#define FMC_DATA_L_data_SHIFT 0
+#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC ((FMC_Type *)FMC_BASE)
+#define FMC_BASE_PTR (FMC)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS { FMC }
+
+/* ----------------------------------------------------------------------------
+ -- FMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
+ * @{
+ */
+
+
+/* FMC - Register instance definitions */
+/* FMC */
+#define FMC_PFAPR FMC_PFAPR_REG(FMC)
+#define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
+#define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
+#define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
+#define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
+#define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
+#define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
+#define FMC_TAGVDW0S4 FMC_TAGVDW0S_REG(FMC,4)
+#define FMC_TAGVDW0S5 FMC_TAGVDW0S_REG(FMC,5)
+#define FMC_TAGVDW0S6 FMC_TAGVDW0S_REG(FMC,6)
+#define FMC_TAGVDW0S7 FMC_TAGVDW0S_REG(FMC,7)
+#define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
+#define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
+#define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
+#define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
+#define FMC_TAGVDW1S4 FMC_TAGVDW1S_REG(FMC,4)
+#define FMC_TAGVDW1S5 FMC_TAGVDW1S_REG(FMC,5)
+#define FMC_TAGVDW1S6 FMC_TAGVDW1S_REG(FMC,6)
+#define FMC_TAGVDW1S7 FMC_TAGVDW1S_REG(FMC,7)
+#define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
+#define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
+#define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
+#define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
+#define FMC_TAGVDW2S4 FMC_TAGVDW2S_REG(FMC,4)
+#define FMC_TAGVDW2S5 FMC_TAGVDW2S_REG(FMC,5)
+#define FMC_TAGVDW2S6 FMC_TAGVDW2S_REG(FMC,6)
+#define FMC_TAGVDW2S7 FMC_TAGVDW2S_REG(FMC,7)
+#define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
+#define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
+#define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
+#define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
+#define FMC_TAGVDW3S4 FMC_TAGVDW3S_REG(FMC,4)
+#define FMC_TAGVDW3S5 FMC_TAGVDW3S_REG(FMC,5)
+#define FMC_TAGVDW3S6 FMC_TAGVDW3S_REG(FMC,6)
+#define FMC_TAGVDW3S7 FMC_TAGVDW3S_REG(FMC,7)
+#define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
+#define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
+#define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
+#define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
+#define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
+#define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
+#define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
+#define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
+#define FMC_DATAW0S4U FMC_DATA_U_REG(FMC,0,4)
+#define FMC_DATAW0S4L FMC_DATA_L_REG(FMC,0,4)
+#define FMC_DATAW0S5U FMC_DATA_U_REG(FMC,0,5)
+#define FMC_DATAW0S5L FMC_DATA_L_REG(FMC,0,5)
+#define FMC_DATAW0S6U FMC_DATA_U_REG(FMC,0,6)
+#define FMC_DATAW0S6L FMC_DATA_L_REG(FMC,0,6)
+#define FMC_DATAW0S7U FMC_DATA_U_REG(FMC,0,7)
+#define FMC_DATAW0S7L FMC_DATA_L_REG(FMC,0,7)
+#define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
+#define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
+#define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
+#define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
+#define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
+#define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
+#define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
+#define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
+#define FMC_DATAW1S4U FMC_DATA_U_REG(FMC,1,4)
+#define FMC_DATAW1S4L FMC_DATA_L_REG(FMC,1,4)
+#define FMC_DATAW1S5U FMC_DATA_U_REG(FMC,1,5)
+#define FMC_DATAW1S5L FMC_DATA_L_REG(FMC,1,5)
+#define FMC_DATAW1S6U FMC_DATA_U_REG(FMC,1,6)
+#define FMC_DATAW1S6L FMC_DATA_L_REG(FMC,1,6)
+#define FMC_DATAW1S7U FMC_DATA_U_REG(FMC,1,7)
+#define FMC_DATAW1S7L FMC_DATA_L_REG(FMC,1,7)
+#define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
+#define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
+#define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
+#define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
+#define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
+#define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
+#define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
+#define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
+#define FMC_DATAW2S4U FMC_DATA_U_REG(FMC,2,4)
+#define FMC_DATAW2S4L FMC_DATA_L_REG(FMC,2,4)
+#define FMC_DATAW2S5U FMC_DATA_U_REG(FMC,2,5)
+#define FMC_DATAW2S5L FMC_DATA_L_REG(FMC,2,5)
+#define FMC_DATAW2S6U FMC_DATA_U_REG(FMC,2,6)
+#define FMC_DATAW2S6L FMC_DATA_L_REG(FMC,2,6)
+#define FMC_DATAW2S7U FMC_DATA_U_REG(FMC,2,7)
+#define FMC_DATAW2S7L FMC_DATA_L_REG(FMC,2,7)
+#define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
+#define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
+#define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
+#define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
+#define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
+#define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
+#define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
+#define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
+#define FMC_DATAW3S4U FMC_DATA_U_REG(FMC,3,4)
+#define FMC_DATAW3S4L FMC_DATA_L_REG(FMC,3,4)
+#define FMC_DATAW3S5U FMC_DATA_U_REG(FMC,3,5)
+#define FMC_DATAW3S5L FMC_DATA_L_REG(FMC,3,5)
+#define FMC_DATAW3S6U FMC_DATA_U_REG(FMC,3,6)
+#define FMC_DATAW3S6L FMC_DATA_L_REG(FMC,3,6)
+#define FMC_DATAW3S7U FMC_DATA_U_REG(FMC,3,7)
+#define FMC_DATAW3S7L FMC_DATA_L_REG(FMC,3,7)
+
+/* FMC - Register array accessors */
+#define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
+#define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
+#define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
+#define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
+#define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
+#define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+ uint8_t RESERVED_0[4];
+ __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
+ __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
+ __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
+ __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
+ __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
+ __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
+ __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
+ __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
+ __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
+ __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
+ __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
+ __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
+ __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
+ __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
+ __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
+ __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
+ __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
+ uint8_t RESERVED_1[2];
+ __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
+} FTFA_Type, *FTFA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FTFA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
+ * @{
+ */
+
+
+/* FTFA - Register accessors */
+#define FTFA_FSTAT_REG(base) ((base)->FSTAT)
+#define FTFA_FCNFG_REG(base) ((base)->FCNFG)
+#define FTFA_FSEC_REG(base) ((base)->FSEC)
+#define FTFA_FOPT_REG(base) ((base)->FOPT)
+#define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
+#define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
+#define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
+#define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
+#define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
+#define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
+#define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
+#define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
+#define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
+#define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
+#define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
+#define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
+#define FTFA_FPROT3_REG(base) ((base)->FPROT3)
+#define FTFA_FPROT2_REG(base) ((base)->FPROT2)
+#define FTFA_FPROT1_REG(base) ((base)->FPROT1)
+#define FTFA_FPROT0_REG(base) ((base)->FPROT0)
+#define FTFA_XACCH3_REG(base) ((base)->XACCH3)
+#define FTFA_XACCH2_REG(base) ((base)->XACCH2)
+#define FTFA_XACCH1_REG(base) ((base)->XACCH1)
+#define FTFA_XACCH0_REG(base) ((base)->XACCH0)
+#define FTFA_XACCL3_REG(base) ((base)->XACCL3)
+#define FTFA_XACCL2_REG(base) ((base)->XACCL2)
+#define FTFA_XACCL1_REG(base) ((base)->XACCL1)
+#define FTFA_XACCL0_REG(base) ((base)->XACCL0)
+#define FTFA_SACCH3_REG(base) ((base)->SACCH3)
+#define FTFA_SACCH2_REG(base) ((base)->SACCH2)
+#define FTFA_SACCH1_REG(base) ((base)->SACCH1)
+#define FTFA_SACCH0_REG(base) ((base)->SACCH0)
+#define FTFA_SACCL3_REG(base) ((base)->SACCL3)
+#define FTFA_SACCL2_REG(base) ((base)->SACCL2)
+#define FTFA_SACCL1_REG(base) ((base)->SACCL1)
+#define FTFA_SACCL0_REG(base) ((base)->SACCL0)
+#define FTFA_FACSS_REG(base) ((base)->FACSS)
+#define FTFA_FACSN_REG(base) ((base)->FACSN)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFA_FSTAT_MGSTAT0_SHIFT 0
+#define FTFA_FSTAT_FPVIOL_MASK 0x10u
+#define FTFA_FSTAT_FPVIOL_SHIFT 4
+#define FTFA_FSTAT_ACCERR_MASK 0x20u
+#define FTFA_FSTAT_ACCERR_SHIFT 5
+#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFA_FSTAT_RDCOLERR_SHIFT 6
+#define FTFA_FSTAT_CCIF_MASK 0x80u
+#define FTFA_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFA_FCNFG_ERSSUSP_SHIFT 4
+#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFA_FCNFG_ERSAREQ_SHIFT 5
+#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFA_FCNFG_CCIE_MASK 0x80u
+#define FTFA_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFA_FSEC_SEC_MASK 0x3u
+#define FTFA_FSEC_SEC_SHIFT 0
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK 0xCu
+#define FTFA_FSEC_FSLACC_SHIFT 2
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK 0x30u
+#define FTFA_FSEC_MEEN_SHIFT 4
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK 0xC0u
+#define FTFA_FSEC_KEYEN_SHIFT 6
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFA_FOPT_OPT_MASK 0xFFu
+#define FTFA_FOPT_OPT_SHIFT 0
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB3_CCOBn_SHIFT 0
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB2_CCOBn_SHIFT 0
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB1_CCOBn_SHIFT 0
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB0_CCOBn_SHIFT 0
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB7_CCOBn_SHIFT 0
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB6_CCOBn_SHIFT 0
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB5_CCOBn_SHIFT 0
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB4_CCOBn_SHIFT 0
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBB_CCOBn_SHIFT 0
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBA_CCOBn_SHIFT 0
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB9_CCOBn_SHIFT 0
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB8_CCOBn_SHIFT 0
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFA_FPROT3_PROT_MASK 0xFFu
+#define FTFA_FPROT3_PROT_SHIFT 0
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFA_FPROT2_PROT_MASK 0xFFu
+#define FTFA_FPROT2_PROT_SHIFT 0
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFA_FPROT1_PROT_MASK 0xFFu
+#define FTFA_FPROT1_PROT_SHIFT 0
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFA_FPROT0_PROT_MASK 0xFFu
+#define FTFA_FPROT0_PROT_SHIFT 0
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
+/* XACCH3 Bit Fields */
+#define FTFA_XACCH3_XA_MASK 0xFFu
+#define FTFA_XACCH3_XA_SHIFT 0
+#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH3_XA_SHIFT))&FTFA_XACCH3_XA_MASK)
+/* XACCH2 Bit Fields */
+#define FTFA_XACCH2_XA_MASK 0xFFu
+#define FTFA_XACCH2_XA_SHIFT 0
+#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH2_XA_SHIFT))&FTFA_XACCH2_XA_MASK)
+/* XACCH1 Bit Fields */
+#define FTFA_XACCH1_XA_MASK 0xFFu
+#define FTFA_XACCH1_XA_SHIFT 0
+#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH1_XA_SHIFT))&FTFA_XACCH1_XA_MASK)
+/* XACCH0 Bit Fields */
+#define FTFA_XACCH0_XA_MASK 0xFFu
+#define FTFA_XACCH0_XA_SHIFT 0
+#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCH0_XA_SHIFT))&FTFA_XACCH0_XA_MASK)
+/* XACCL3 Bit Fields */
+#define FTFA_XACCL3_XA_MASK 0xFFu
+#define FTFA_XACCL3_XA_SHIFT 0
+#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL3_XA_SHIFT))&FTFA_XACCL3_XA_MASK)
+/* XACCL2 Bit Fields */
+#define FTFA_XACCL2_XA_MASK 0xFFu
+#define FTFA_XACCL2_XA_SHIFT 0
+#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL2_XA_SHIFT))&FTFA_XACCL2_XA_MASK)
+/* XACCL1 Bit Fields */
+#define FTFA_XACCL1_XA_MASK 0xFFu
+#define FTFA_XACCL1_XA_SHIFT 0
+#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL1_XA_SHIFT))&FTFA_XACCL1_XA_MASK)
+/* XACCL0 Bit Fields */
+#define FTFA_XACCL0_XA_MASK 0xFFu
+#define FTFA_XACCL0_XA_SHIFT 0
+#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_XACCL0_XA_SHIFT))&FTFA_XACCL0_XA_MASK)
+/* SACCH3 Bit Fields */
+#define FTFA_SACCH3_SA_MASK 0xFFu
+#define FTFA_SACCH3_SA_SHIFT 0
+#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH3_SA_SHIFT))&FTFA_SACCH3_SA_MASK)
+/* SACCH2 Bit Fields */
+#define FTFA_SACCH2_SA_MASK 0xFFu
+#define FTFA_SACCH2_SA_SHIFT 0
+#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH2_SA_SHIFT))&FTFA_SACCH2_SA_MASK)
+/* SACCH1 Bit Fields */
+#define FTFA_SACCH1_SA_MASK 0xFFu
+#define FTFA_SACCH1_SA_SHIFT 0
+#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH1_SA_SHIFT))&FTFA_SACCH1_SA_MASK)
+/* SACCH0 Bit Fields */
+#define FTFA_SACCH0_SA_MASK 0xFFu
+#define FTFA_SACCH0_SA_SHIFT 0
+#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCH0_SA_SHIFT))&FTFA_SACCH0_SA_MASK)
+/* SACCL3 Bit Fields */
+#define FTFA_SACCL3_SA_MASK 0xFFu
+#define FTFA_SACCL3_SA_SHIFT 0
+#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL3_SA_SHIFT))&FTFA_SACCL3_SA_MASK)
+/* SACCL2 Bit Fields */
+#define FTFA_SACCL2_SA_MASK 0xFFu
+#define FTFA_SACCL2_SA_SHIFT 0
+#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL2_SA_SHIFT))&FTFA_SACCL2_SA_MASK)
+/* SACCL1 Bit Fields */
+#define FTFA_SACCL1_SA_MASK 0xFFu
+#define FTFA_SACCL1_SA_SHIFT 0
+#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL1_SA_SHIFT))&FTFA_SACCL1_SA_MASK)
+/* SACCL0 Bit Fields */
+#define FTFA_SACCL0_SA_MASK 0xFFu
+#define FTFA_SACCL0_SA_SHIFT 0
+#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x))<<FTFA_SACCL0_SA_SHIFT))&FTFA_SACCL0_SA_MASK)
+/* FACSS Bit Fields */
+#define FTFA_FACSS_SGSIZE_MASK 0xFFu
+#define FTFA_FACSS_SGSIZE_SHIFT 0
+#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSS_SGSIZE_SHIFT))&FTFA_FACSS_SGSIZE_MASK)
+/* FACSN Bit Fields */
+#define FTFA_FACSN_NUMSG_MASK 0xFFu
+#define FTFA_FACSN_NUMSG_SHIFT 0
+#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FACSN_NUMSG_SHIFT))&FTFA_FACSN_NUMSG_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA ((FTFA_Type *)FTFA_BASE)
+#define FTFA_BASE_PTR (FTFA)
+/** Array initializer of FTFA peripheral base addresses */
+#define FTFA_BASE_ADDRS { FTFA_BASE }
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASE_PTRS { FTFA }
+/** Interrupt vectors for the FTFA peripheral type */
+#define FTFA_COMMAND_COMPLETE_IRQS { FTF_IRQn }
+#define FTFA_READ_COLLISION_IRQS { Read_Collision_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- FTFA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
+ * @{
+ */
+
+
+/* FTFA - Register instance definitions */
+/* FTFA */
+#define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
+#define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
+#define FTFA_FSEC FTFA_FSEC_REG(FTFA)
+#define FTFA_FOPT FTFA_FOPT_REG(FTFA)
+#define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
+#define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
+#define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
+#define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
+#define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
+#define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
+#define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
+#define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
+#define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
+#define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
+#define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
+#define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
+#define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
+#define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
+#define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
+#define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
+#define FTFA_XACCH3 FTFA_XACCH3_REG(FTFA)
+#define FTFA_XACCH2 FTFA_XACCH2_REG(FTFA)
+#define FTFA_XACCH1 FTFA_XACCH1_REG(FTFA)
+#define FTFA_XACCH0 FTFA_XACCH0_REG(FTFA)
+#define FTFA_XACCL3 FTFA_XACCL3_REG(FTFA)
+#define FTFA_XACCL2 FTFA_XACCL2_REG(FTFA)
+#define FTFA_XACCL1 FTFA_XACCL1_REG(FTFA)
+#define FTFA_XACCL0 FTFA_XACCL0_REG(FTFA)
+#define FTFA_SACCH3 FTFA_SACCH3_REG(FTFA)
+#define FTFA_SACCH2 FTFA_SACCH2_REG(FTFA)
+#define FTFA_SACCH1 FTFA_SACCH1_REG(FTFA)
+#define FTFA_SACCH0 FTFA_SACCH0_REG(FTFA)
+#define FTFA_SACCL3 FTFA_SACCL3_REG(FTFA)
+#define FTFA_SACCL2 FTFA_SACCL2_REG(FTFA)
+#define FTFA_SACCL1 FTFA_SACCL1_REG(FTFA)
+#define FTFA_SACCL0 FTFA_SACCL0_REG(FTFA)
+#define FTFA_FACSS FTFA_FACSS_REG(FTFA)
+#define FTFA_FACSN FTFA_FACSN_REG(FTFA)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[8];
+ __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
+ __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
+ __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
+ __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
+ __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
+ __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
+ __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
+ __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
+ __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
+ __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
+ __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
+ __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
+ __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
+ __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+ __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
+ __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
+ __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
+ __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
+ __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type, *FTM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FTM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register accessors */
+#define FTM_SC_REG(base) ((base)->SC)
+#define FTM_CNT_REG(base) ((base)->CNT)
+#define FTM_MOD_REG(base) ((base)->MOD)
+#define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
+#define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
+#define FTM_CNTIN_REG(base) ((base)->CNTIN)
+#define FTM_STATUS_REG(base) ((base)->STATUS)
+#define FTM_MODE_REG(base) ((base)->MODE)
+#define FTM_SYNC_REG(base) ((base)->SYNC)
+#define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
+#define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
+#define FTM_COMBINE_REG(base) ((base)->COMBINE)
+#define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
+#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
+#define FTM_POL_REG(base) ((base)->POL)
+#define FTM_FMS_REG(base) ((base)->FMS)
+#define FTM_FILTER_REG(base) ((base)->FILTER)
+#define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
+#define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
+#define FTM_CONF_REG(base) ((base)->CONF)
+#define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
+#define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
+#define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
+#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
+#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK 0x7u
+#define FTM_SC_PS_SHIFT 0
+#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK 0x18u
+#define FTM_SC_CLKS_SHIFT 3
+#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK 0x20u
+#define FTM_SC_CPWMS_SHIFT 5
+#define FTM_SC_TOIE_MASK 0x40u
+#define FTM_SC_TOIE_SHIFT 6
+#define FTM_SC_TOF_MASK 0x80u
+#define FTM_SC_TOF_SHIFT 7
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK 0xFFFFu
+#define FTM_CNT_COUNT_SHIFT 0
+#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK 0xFFFFu
+#define FTM_MOD_MOD_SHIFT 0
+#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK 0x1u
+#define FTM_CnSC_DMA_SHIFT 0
+#define FTM_CnSC_ICRST_MASK 0x2u
+#define FTM_CnSC_ICRST_SHIFT 1
+#define FTM_CnSC_ELSA_MASK 0x4u
+#define FTM_CnSC_ELSA_SHIFT 2
+#define FTM_CnSC_ELSB_MASK 0x8u
+#define FTM_CnSC_ELSB_SHIFT 3
+#define FTM_CnSC_MSA_MASK 0x10u
+#define FTM_CnSC_MSA_SHIFT 4
+#define FTM_CnSC_MSB_MASK 0x20u
+#define FTM_CnSC_MSB_SHIFT 5
+#define FTM_CnSC_CHIE_MASK 0x40u
+#define FTM_CnSC_CHIE_SHIFT 6
+#define FTM_CnSC_CHF_MASK 0x80u
+#define FTM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK 0xFFFFu
+#define FTM_CnV_VAL_SHIFT 0
+#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK 0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT 0
+#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK 0x1u
+#define FTM_STATUS_CH0F_SHIFT 0
+#define FTM_STATUS_CH1F_MASK 0x2u
+#define FTM_STATUS_CH1F_SHIFT 1
+#define FTM_STATUS_CH2F_MASK 0x4u
+#define FTM_STATUS_CH2F_SHIFT 2
+#define FTM_STATUS_CH3F_MASK 0x8u
+#define FTM_STATUS_CH3F_SHIFT 3
+#define FTM_STATUS_CH4F_MASK 0x10u
+#define FTM_STATUS_CH4F_SHIFT 4
+#define FTM_STATUS_CH5F_MASK 0x20u
+#define FTM_STATUS_CH5F_SHIFT 5
+#define FTM_STATUS_CH6F_MASK 0x40u
+#define FTM_STATUS_CH6F_SHIFT 6
+#define FTM_STATUS_CH7F_MASK 0x80u
+#define FTM_STATUS_CH7F_SHIFT 7
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK 0x1u
+#define FTM_MODE_FTMEN_SHIFT 0
+#define FTM_MODE_INIT_MASK 0x2u
+#define FTM_MODE_INIT_SHIFT 1
+#define FTM_MODE_WPDIS_MASK 0x4u
+#define FTM_MODE_WPDIS_SHIFT 2
+#define FTM_MODE_PWMSYNC_MASK 0x8u
+#define FTM_MODE_PWMSYNC_SHIFT 3
+#define FTM_MODE_CAPTEST_MASK 0x10u
+#define FTM_MODE_CAPTEST_SHIFT 4
+#define FTM_MODE_FAULTM_MASK 0x60u
+#define FTM_MODE_FAULTM_SHIFT 5
+#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK 0x80u
+#define FTM_MODE_FAULTIE_SHIFT 7
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK 0x1u
+#define FTM_SYNC_CNTMIN_SHIFT 0
+#define FTM_SYNC_CNTMAX_MASK 0x2u
+#define FTM_SYNC_CNTMAX_SHIFT 1
+#define FTM_SYNC_REINIT_MASK 0x4u
+#define FTM_SYNC_REINIT_SHIFT 2
+#define FTM_SYNC_SYNCHOM_MASK 0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT 3
+#define FTM_SYNC_TRIG0_MASK 0x10u
+#define FTM_SYNC_TRIG0_SHIFT 4
+#define FTM_SYNC_TRIG1_MASK 0x20u
+#define FTM_SYNC_TRIG1_SHIFT 5
+#define FTM_SYNC_TRIG2_MASK 0x40u
+#define FTM_SYNC_TRIG2_SHIFT 6
+#define FTM_SYNC_SWSYNC_MASK 0x80u
+#define FTM_SYNC_SWSYNC_SHIFT 7
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK 0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT 0
+#define FTM_OUTINIT_CH1OI_MASK 0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT 1
+#define FTM_OUTINIT_CH2OI_MASK 0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT 2
+#define FTM_OUTINIT_CH3OI_MASK 0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT 3
+#define FTM_OUTINIT_CH4OI_MASK 0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT 4
+#define FTM_OUTINIT_CH5OI_MASK 0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT 5
+#define FTM_OUTINIT_CH6OI_MASK 0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT 6
+#define FTM_OUTINIT_CH7OI_MASK 0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT 7
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK 0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT 0
+#define FTM_OUTMASK_CH1OM_MASK 0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT 1
+#define FTM_OUTMASK_CH2OM_MASK 0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT 2
+#define FTM_OUTMASK_CH3OM_MASK 0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT 3
+#define FTM_OUTMASK_CH4OM_MASK 0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT 4
+#define FTM_OUTMASK_CH5OM_MASK 0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT 5
+#define FTM_OUTMASK_CH6OM_MASK 0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT 6
+#define FTM_OUTMASK_CH7OM_MASK 0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT 7
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK 0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT 0
+#define FTM_COMBINE_COMP0_MASK 0x2u
+#define FTM_COMBINE_COMP0_SHIFT 1
+#define FTM_COMBINE_DECAPEN0_MASK 0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT 2
+#define FTM_COMBINE_DECAP0_MASK 0x8u
+#define FTM_COMBINE_DECAP0_SHIFT 3
+#define FTM_COMBINE_DTEN0_MASK 0x10u
+#define FTM_COMBINE_DTEN0_SHIFT 4
+#define FTM_COMBINE_SYNCEN0_MASK 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT 5
+#define FTM_COMBINE_FAULTEN0_MASK 0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT 6
+#define FTM_COMBINE_COMBINE1_MASK 0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT 8
+#define FTM_COMBINE_COMP1_MASK 0x200u
+#define FTM_COMBINE_COMP1_SHIFT 9
+#define FTM_COMBINE_DECAPEN1_MASK 0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT 10
+#define FTM_COMBINE_DECAP1_MASK 0x800u
+#define FTM_COMBINE_DECAP1_SHIFT 11
+#define FTM_COMBINE_DTEN1_MASK 0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT 12
+#define FTM_COMBINE_SYNCEN1_MASK 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT 13
+#define FTM_COMBINE_FAULTEN1_MASK 0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT 14
+#define FTM_COMBINE_COMBINE2_MASK 0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT 16
+#define FTM_COMBINE_COMP2_MASK 0x20000u
+#define FTM_COMBINE_COMP2_SHIFT 17
+#define FTM_COMBINE_DECAPEN2_MASK 0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT 18
+#define FTM_COMBINE_DECAP2_MASK 0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT 19
+#define FTM_COMBINE_DTEN2_MASK 0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT 20
+#define FTM_COMBINE_SYNCEN2_MASK 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT 21
+#define FTM_COMBINE_FAULTEN2_MASK 0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT 22
+#define FTM_COMBINE_COMBINE3_MASK 0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT 24
+#define FTM_COMBINE_COMP3_MASK 0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT 25
+#define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT 26
+#define FTM_COMBINE_DECAP3_MASK 0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT 27
+#define FTM_COMBINE_DTEN3_MASK 0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT 28
+#define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT 29
+#define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT 30
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK 0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT 0
+#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK 0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT 6
+#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT 0
+#define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT 1
+#define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT 2
+#define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT 3
+#define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT 4
+#define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT 5
+#define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
+#define FTM_EXTTRIG_TRIGF_MASK 0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT 7
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK 0x1u
+#define FTM_POL_POL0_SHIFT 0
+#define FTM_POL_POL1_MASK 0x2u
+#define FTM_POL_POL1_SHIFT 1
+#define FTM_POL_POL2_MASK 0x4u
+#define FTM_POL_POL2_SHIFT 2
+#define FTM_POL_POL3_MASK 0x8u
+#define FTM_POL_POL3_SHIFT 3
+#define FTM_POL_POL4_MASK 0x10u
+#define FTM_POL_POL4_SHIFT 4
+#define FTM_POL_POL5_MASK 0x20u
+#define FTM_POL_POL5_SHIFT 5
+#define FTM_POL_POL6_MASK 0x40u
+#define FTM_POL_POL6_SHIFT 6
+#define FTM_POL_POL7_MASK 0x80u
+#define FTM_POL_POL7_SHIFT 7
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK 0x1u
+#define FTM_FMS_FAULTF0_SHIFT 0
+#define FTM_FMS_FAULTF1_MASK 0x2u
+#define FTM_FMS_FAULTF1_SHIFT 1
+#define FTM_FMS_FAULTF2_MASK 0x4u
+#define FTM_FMS_FAULTF2_SHIFT 2
+#define FTM_FMS_FAULTF3_MASK 0x8u
+#define FTM_FMS_FAULTF3_SHIFT 3
+#define FTM_FMS_FAULTIN_MASK 0x20u
+#define FTM_FMS_FAULTIN_SHIFT 5
+#define FTM_FMS_WPEN_MASK 0x40u
+#define FTM_FMS_WPEN_SHIFT 6
+#define FTM_FMS_FAULTF_MASK 0x80u
+#define FTM_FMS_FAULTF_SHIFT 7
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK 0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT 0
+#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK 0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT 4
+#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK 0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT 8
+#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK 0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT 12
+#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT 0
+#define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT 1
+#define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT 2
+#define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT 3
+#define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
+#define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
+#define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
+#define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
+#define FTM_FLTCTRL_FFVAL_MASK 0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT 8
+#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK 0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT 0
+#define FTM_QDCTRL_TOFDIR_MASK 0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT 1
+#define FTM_QDCTRL_QUADIR_MASK 0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT 2
+#define FTM_QDCTRL_QUADMODE_MASK 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT 3
+#define FTM_QDCTRL_PHBPOL_MASK 0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT 4
+#define FTM_QDCTRL_PHAPOL_MASK 0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT 5
+#define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT 6
+#define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT 7
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK 0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT 0
+#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK 0xC0u
+#define FTM_CONF_BDMMODE_SHIFT 6
+#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK 0x200u
+#define FTM_CONF_GTBEEN_SHIFT 9
+#define FTM_CONF_GTBEOUT_MASK 0x400u
+#define FTM_CONF_GTBEOUT_SHIFT 10
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK 0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT 0
+#define FTM_FLTPOL_FLT1POL_MASK 0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT 1
+#define FTM_FLTPOL_FLT2POL_MASK 0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT 2
+#define FTM_FLTPOL_FLT3POL_MASK 0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT 3
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
+#define FTM_SYNCONF_CNTINC_MASK 0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT 2
+#define FTM_SYNCONF_INVC_MASK 0x10u
+#define FTM_SYNCONF_INVC_SHIFT 4
+#define FTM_SYNCONF_SWOC_MASK 0x20u
+#define FTM_SYNCONF_SWOC_SHIFT 5
+#define FTM_SYNCONF_SYNCMODE_MASK 0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT 7
+#define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT 8
+#define FTM_SYNCONF_SWWRBUF_MASK 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT 9
+#define FTM_SYNCONF_SWOM_MASK 0x400u
+#define FTM_SYNCONF_SWOM_SHIFT 10
+#define FTM_SYNCONF_SWINVC_MASK 0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT 11
+#define FTM_SYNCONF_SWSOC_MASK 0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT 12
+#define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT 16
+#define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT 17
+#define FTM_SYNCONF_HWOM_MASK 0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT 18
+#define FTM_SYNCONF_HWINVC_MASK 0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT 19
+#define FTM_SYNCONF_HWSOC_MASK 0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT 20
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK 0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT 0
+#define FTM_INVCTRL_INV1EN_MASK 0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT 1
+#define FTM_INVCTRL_INV2EN_MASK 0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT 2
+#define FTM_INVCTRL_INV3EN_MASK 0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT 3
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK 0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT 0
+#define FTM_SWOCTRL_CH1OC_MASK 0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT 1
+#define FTM_SWOCTRL_CH2OC_MASK 0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT 2
+#define FTM_SWOCTRL_CH3OC_MASK 0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT 3
+#define FTM_SWOCTRL_CH4OC_MASK 0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT 4
+#define FTM_SWOCTRL_CH5OC_MASK 0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT 5
+#define FTM_SWOCTRL_CH6OC_MASK 0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT 6
+#define FTM_SWOCTRL_CH7OC_MASK 0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT 7
+#define FTM_SWOCTRL_CH0OCV_MASK 0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT 8
+#define FTM_SWOCTRL_CH1OCV_MASK 0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT 9
+#define FTM_SWOCTRL_CH2OCV_MASK 0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT 10
+#define FTM_SWOCTRL_CH3OCV_MASK 0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT 11
+#define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT 12
+#define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT 13
+#define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT 14
+#define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT 15
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK 0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT 0
+#define FTM_PWMLOAD_CH1SEL_MASK 0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT 1
+#define FTM_PWMLOAD_CH2SEL_MASK 0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT 2
+#define FTM_PWMLOAD_CH3SEL_MASK 0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT 3
+#define FTM_PWMLOAD_CH4SEL_MASK 0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT 4
+#define FTM_PWMLOAD_CH5SEL_MASK 0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT 5
+#define FTM_PWMLOAD_CH6SEL_MASK 0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT 6
+#define FTM_PWMLOAD_CH7SEL_MASK 0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT 7
+#define FTM_PWMLOAD_LDOK_MASK 0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT 9
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0 ((FTM_Type *)FTM0_BASE)
+#define FTM0_BASE_PTR (FTM0)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1 ((FTM_Type *)FTM1_BASE)
+#define FTM1_BASE_PTR (FTM1)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2 ((FTM_Type *)FTM2_BASE)
+#define FTM2_BASE_PTR (FTM2)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE (0x40026000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3 ((FTM_Type *)FTM3_BASE)
+#define FTM3_BASE_PTR (FTM3)
+/** Array initializer of FTM peripheral base addresses */
+#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
+/** Interrupt vectors for the FTM peripheral type */
+#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- FTM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
+ * @{
+ */
+
+
+/* FTM - Register instance definitions */
+/* FTM0 */
+#define FTM0_SC FTM_SC_REG(FTM0)
+#define FTM0_CNT FTM_CNT_REG(FTM0)
+#define FTM0_MOD FTM_MOD_REG(FTM0)
+#define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
+#define FTM0_C0V FTM_CnV_REG(FTM0,0)
+#define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
+#define FTM0_C1V FTM_CnV_REG(FTM0,1)
+#define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
+#define FTM0_C2V FTM_CnV_REG(FTM0,2)
+#define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
+#define FTM0_C3V FTM_CnV_REG(FTM0,3)
+#define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
+#define FTM0_C4V FTM_CnV_REG(FTM0,4)
+#define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
+#define FTM0_C5V FTM_CnV_REG(FTM0,5)
+#define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
+#define FTM0_C6V FTM_CnV_REG(FTM0,6)
+#define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
+#define FTM0_C7V FTM_CnV_REG(FTM0,7)
+#define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
+#define FTM0_STATUS FTM_STATUS_REG(FTM0)
+#define FTM0_MODE FTM_MODE_REG(FTM0)
+#define FTM0_SYNC FTM_SYNC_REG(FTM0)
+#define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
+#define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
+#define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
+#define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
+#define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
+#define FTM0_POL FTM_POL_REG(FTM0)
+#define FTM0_FMS FTM_FMS_REG(FTM0)
+#define FTM0_FILTER FTM_FILTER_REG(FTM0)
+#define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
+#define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
+#define FTM0_CONF FTM_CONF_REG(FTM0)
+#define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
+#define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
+#define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
+#define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
+#define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
+/* FTM1 */
+#define FTM1_SC FTM_SC_REG(FTM1)
+#define FTM1_CNT FTM_CNT_REG(FTM1)
+#define FTM1_MOD FTM_MOD_REG(FTM1)
+#define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
+#define FTM1_C0V FTM_CnV_REG(FTM1,0)
+#define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
+#define FTM1_C1V FTM_CnV_REG(FTM1,1)
+#define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
+#define FTM1_STATUS FTM_STATUS_REG(FTM1)
+#define FTM1_MODE FTM_MODE_REG(FTM1)
+#define FTM1_SYNC FTM_SYNC_REG(FTM1)
+#define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
+#define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
+#define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
+#define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
+#define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
+#define FTM1_POL FTM_POL_REG(FTM1)
+#define FTM1_FMS FTM_FMS_REG(FTM1)
+#define FTM1_FILTER FTM_FILTER_REG(FTM1)
+#define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
+#define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
+#define FTM1_CONF FTM_CONF_REG(FTM1)
+#define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
+#define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
+#define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
+#define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
+#define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
+/* FTM2 */
+#define FTM2_SC FTM_SC_REG(FTM2)
+#define FTM2_CNT FTM_CNT_REG(FTM2)
+#define FTM2_MOD FTM_MOD_REG(FTM2)
+#define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
+#define FTM2_C0V FTM_CnV_REG(FTM2,0)
+#define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
+#define FTM2_C1V FTM_CnV_REG(FTM2,1)
+#define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
+#define FTM2_STATUS FTM_STATUS_REG(FTM2)
+#define FTM2_MODE FTM_MODE_REG(FTM2)
+#define FTM2_SYNC FTM_SYNC_REG(FTM2)
+#define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
+#define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
+#define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
+#define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
+#define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
+#define FTM2_POL FTM_POL_REG(FTM2)
+#define FTM2_FMS FTM_FMS_REG(FTM2)
+#define FTM2_FILTER FTM_FILTER_REG(FTM2)
+#define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
+#define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
+#define FTM2_CONF FTM_CONF_REG(FTM2)
+#define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
+#define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
+#define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
+#define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
+#define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
+/* FTM3 */
+#define FTM3_SC FTM_SC_REG(FTM3)
+#define FTM3_CNT FTM_CNT_REG(FTM3)
+#define FTM3_MOD FTM_MOD_REG(FTM3)
+#define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
+#define FTM3_C0V FTM_CnV_REG(FTM3,0)
+#define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
+#define FTM3_C1V FTM_CnV_REG(FTM3,1)
+#define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
+#define FTM3_C2V FTM_CnV_REG(FTM3,2)
+#define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
+#define FTM3_C3V FTM_CnV_REG(FTM3,3)
+#define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
+#define FTM3_C4V FTM_CnV_REG(FTM3,4)
+#define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
+#define FTM3_C5V FTM_CnV_REG(FTM3,5)
+#define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
+#define FTM3_C6V FTM_CnV_REG(FTM3,6)
+#define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
+#define FTM3_C7V FTM_CnV_REG(FTM3,7)
+#define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
+#define FTM3_STATUS FTM_STATUS_REG(FTM3)
+#define FTM3_MODE FTM_MODE_REG(FTM3)
+#define FTM3_SYNC FTM_SYNC_REG(FTM3)
+#define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
+#define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
+#define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
+#define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
+#define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
+#define FTM3_POL FTM_POL_REG(FTM3)
+#define FTM3_FMS FTM_FMS_REG(FTM3)
+#define FTM3_FILTER FTM_FILTER_REG(FTM3)
+#define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
+#define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
+#define FTM3_CONF FTM_CONF_REG(FTM3)
+#define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
+#define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
+#define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
+#define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
+#define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
+
+/* FTM - Register array accessors */
+#define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
+#define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
+#define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
+#define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
+#define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
+#define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
+#define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
+#define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register accessors */
+#define GPIO_PDOR_REG(base) ((base)->PDOR)
+#define GPIO_PSOR_REG(base) ((base)->PSOR)
+#define GPIO_PCOR_REG(base) ((base)->PCOR)
+#define GPIO_PTOR_REG(base) ((base)->PTOR)
+#define GPIO_PDIR_REG(base) ((base)->PDIR)
+#define GPIO_PDDR_REG(base) ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+#define PTA_BASE_PTR (PTA)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+#define PTB_BASE_PTR (PTB)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+#define PTC_BASE_PTR (PTC)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+#define PTD_BASE_PTR (PTD)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+#define PTE_BASE_PTR (PTE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
+
+/* ----------------------------------------------------------------------------
+ -- GPIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register instance definitions */
+/* PTA */
+#define GPIOA_PDOR GPIO_PDOR_REG(PTA)
+#define GPIOA_PSOR GPIO_PSOR_REG(PTA)
+#define GPIOA_PCOR GPIO_PCOR_REG(PTA)
+#define GPIOA_PTOR GPIO_PTOR_REG(PTA)
+#define GPIOA_PDIR GPIO_PDIR_REG(PTA)
+#define GPIOA_PDDR GPIO_PDDR_REG(PTA)
+/* PTB */
+#define GPIOB_PDOR GPIO_PDOR_REG(PTB)
+#define GPIOB_PSOR GPIO_PSOR_REG(PTB)
+#define GPIOB_PCOR GPIO_PCOR_REG(PTB)
+#define GPIOB_PTOR GPIO_PTOR_REG(PTB)
+#define GPIOB_PDIR GPIO_PDIR_REG(PTB)
+#define GPIOB_PDDR GPIO_PDDR_REG(PTB)
+/* PTC */
+#define GPIOC_PDOR GPIO_PDOR_REG(PTC)
+#define GPIOC_PSOR GPIO_PSOR_REG(PTC)
+#define GPIOC_PCOR GPIO_PCOR_REG(PTC)
+#define GPIOC_PTOR GPIO_PTOR_REG(PTC)
+#define GPIOC_PDIR GPIO_PDIR_REG(PTC)
+#define GPIOC_PDDR GPIO_PDDR_REG(PTC)
+/* PTD */
+#define GPIOD_PDOR GPIO_PDOR_REG(PTD)
+#define GPIOD_PSOR GPIO_PSOR_REG(PTD)
+#define GPIOD_PCOR GPIO_PCOR_REG(PTD)
+#define GPIOD_PTOR GPIO_PTOR_REG(PTD)
+#define GPIOD_PDIR GPIO_PDIR_REG(PTD)
+#define GPIOD_PDDR GPIO_PDDR_REG(PTD)
+/* PTE */
+#define GPIOE_PDOR GPIO_PDOR_REG(PTE)
+#define GPIOE_PSOR GPIO_PSOR_REG(PTE)
+#define GPIOE_PCOR GPIO_PCOR_REG(PTE)
+#define GPIOE_PTOR GPIO_PTOR_REG(PTE)
+#define GPIOE_PDIR GPIO_PDIR_REG(PTE)
+#define GPIOE_PDDR GPIO_PDDR_REG(PTE)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type, *I2C_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- I2C - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register accessors */
+#define I2C_A1_REG(base) ((base)->A1)
+#define I2C_F_REG(base) ((base)->F)
+#define I2C_C1_REG(base) ((base)->C1)
+#define I2C_S_REG(base) ((base)->S)
+#define I2C_D_REG(base) ((base)->D)
+#define I2C_C2_REG(base) ((base)->C2)
+#define I2C_FLT_REG(base) ((base)->FLT)
+#define I2C_RA_REG(base) ((base)->RA)
+#define I2C_SMB_REG(base) ((base)->SMB)
+#define I2C_A2_REG(base) ((base)->A2)
+#define I2C_SLTH_REG(base) ((base)->SLTH)
+#define I2C_SLTL_REG(base) ((base)->SLTL)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0xFu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK 0x10u
+#define I2C_FLT_STARTF_SHIFT 4
+#define I2C_FLT_SSIE_MASK 0x20u
+#define I2C_FLT_SSIE_SHIFT 5
+#define I2C_FLT_STOPF_MASK 0x40u
+#define I2C_FLT_STOPF_SHIFT 6
+#define I2C_FLT_SHEN_MASK 0x80u
+#define I2C_FLT_SHEN_SHIFT 7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+#define I2C0_BASE_PTR (I2C0)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+#define I2C1_BASE_PTR (I2C1)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS { I2C0, I2C1 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- I2C - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register instance definitions */
+/* I2C0 */
+#define I2C0_A1 I2C_A1_REG(I2C0)
+#define I2C0_F I2C_F_REG(I2C0)
+#define I2C0_C1 I2C_C1_REG(I2C0)
+#define I2C0_S I2C_S_REG(I2C0)
+#define I2C0_D I2C_D_REG(I2C0)
+#define I2C0_C2 I2C_C2_REG(I2C0)
+#define I2C0_FLT I2C_FLT_REG(I2C0)
+#define I2C0_RA I2C_RA_REG(I2C0)
+#define I2C0_SMB I2C_SMB_REG(I2C0)
+#define I2C0_A2 I2C_A2_REG(I2C0)
+#define I2C0_SLTH I2C_SLTH_REG(I2C0)
+#define I2C0_SLTL I2C_SLTL_REG(I2C0)
+/* I2C1 */
+#define I2C1_A1 I2C_A1_REG(I2C1)
+#define I2C1_F I2C_F_REG(I2C1)
+#define I2C1_C1 I2C_C1_REG(I2C1)
+#define I2C1_S I2C_S_REG(I2C1)
+#define I2C1_D I2C_D_REG(I2C1)
+#define I2C1_C2 I2C_C2_REG(I2C1)
+#define I2C1_FLT I2C_FLT_REG(I2C1)
+#define I2C1_RA I2C_RA_REG(I2C1)
+#define I2C1_SMB I2C_SMB_REG(I2C1)
+#define I2C1_A2 I2C_A2_REG(I2C1)
+#define I2C1_SLTH I2C_SLTH_REG(I2C1)
+#define I2C1_SLTL I2C_SLTL_REG(I2C1)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_0[8];
+ __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[28];
+ __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+ uint8_t RESERVED_2[28];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_4[8];
+ __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_5[28];
+ __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_6[28];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+ __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type, *I2S_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- I2S - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register accessors */
+#define I2S_TCSR_REG(base) ((base)->TCSR)
+#define I2S_TCR1_REG(base) ((base)->TCR1)
+#define I2S_TCR2_REG(base) ((base)->TCR2)
+#define I2S_TCR3_REG(base) ((base)->TCR3)
+#define I2S_TCR4_REG(base) ((base)->TCR4)
+#define I2S_TCR5_REG(base) ((base)->TCR5)
+#define I2S_TDR_REG(base,index) ((base)->TDR[index])
+#define I2S_TFR_REG(base,index) ((base)->TFR[index])
+#define I2S_TMR_REG(base) ((base)->TMR)
+#define I2S_RCSR_REG(base) ((base)->RCSR)
+#define I2S_RCR1_REG(base) ((base)->RCR1)
+#define I2S_RCR2_REG(base) ((base)->RCR2)
+#define I2S_RCR3_REG(base) ((base)->RCR3)
+#define I2S_RCR4_REG(base) ((base)->RCR4)
+#define I2S_RCR5_REG(base) ((base)->RCR5)
+#define I2S_RDR_REG(base,index) ((base)->RDR[index])
+#define I2S_RFR_REG(base,index) ((base)->RFR[index])
+#define I2S_RMR_REG(base) ((base)->RMR)
+#define I2S_MCR_REG(base) ((base)->MCR)
+#define I2S_MDR_REG(base) ((base)->MDR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FRDE_MASK 0x1u
+#define I2S_TCSR_FRDE_SHIFT 0
+#define I2S_TCSR_FWDE_MASK 0x2u
+#define I2S_TCSR_FWDE_SHIFT 1
+#define I2S_TCSR_FRIE_MASK 0x100u
+#define I2S_TCSR_FRIE_SHIFT 8
+#define I2S_TCSR_FWIE_MASK 0x200u
+#define I2S_TCSR_FWIE_SHIFT 9
+#define I2S_TCSR_FEIE_MASK 0x400u
+#define I2S_TCSR_FEIE_SHIFT 10
+#define I2S_TCSR_SEIE_MASK 0x800u
+#define I2S_TCSR_SEIE_SHIFT 11
+#define I2S_TCSR_WSIE_MASK 0x1000u
+#define I2S_TCSR_WSIE_SHIFT 12
+#define I2S_TCSR_FRF_MASK 0x10000u
+#define I2S_TCSR_FRF_SHIFT 16
+#define I2S_TCSR_FWF_MASK 0x20000u
+#define I2S_TCSR_FWF_SHIFT 17
+#define I2S_TCSR_FEF_MASK 0x40000u
+#define I2S_TCSR_FEF_SHIFT 18
+#define I2S_TCSR_SEF_MASK 0x80000u
+#define I2S_TCSR_SEF_SHIFT 19
+#define I2S_TCSR_WSF_MASK 0x100000u
+#define I2S_TCSR_WSF_SHIFT 20
+#define I2S_TCSR_SR_MASK 0x1000000u
+#define I2S_TCSR_SR_SHIFT 24
+#define I2S_TCSR_FR_MASK 0x2000000u
+#define I2S_TCSR_FR_SHIFT 25
+#define I2S_TCSR_BCE_MASK 0x10000000u
+#define I2S_TCSR_BCE_SHIFT 28
+#define I2S_TCSR_DBGE_MASK 0x20000000u
+#define I2S_TCSR_DBGE_SHIFT 29
+#define I2S_TCSR_STOPE_MASK 0x40000000u
+#define I2S_TCSR_STOPE_SHIFT 30
+#define I2S_TCSR_TE_MASK 0x80000000u
+#define I2S_TCSR_TE_SHIFT 31
+/* TCR1 Bit Fields */
+#define I2S_TCR1_TFW_MASK 0x7u
+#define I2S_TCR1_TFW_SHIFT 0
+#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK 0xFFu
+#define I2S_TCR2_DIV_SHIFT 0
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK 0x1000000u
+#define I2S_TCR2_BCD_SHIFT 24
+#define I2S_TCR2_BCP_MASK 0x2000000u
+#define I2S_TCR2_BCP_SHIFT 25
+#define I2S_TCR2_MSEL_MASK 0xC000000u
+#define I2S_TCR2_MSEL_SHIFT 26
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK 0x10000000u
+#define I2S_TCR2_BCI_SHIFT 28
+#define I2S_TCR2_BCS_MASK 0x20000000u
+#define I2S_TCR2_BCS_SHIFT 29
+#define I2S_TCR2_SYNC_MASK 0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT 30
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK 0xFu
+#define I2S_TCR3_WDFL_SHIFT 0
+#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK 0x10000u
+#define I2S_TCR3_TCE_SHIFT 16
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK 0x1u
+#define I2S_TCR4_FSD_SHIFT 0
+#define I2S_TCR4_FSP_MASK 0x2u
+#define I2S_TCR4_FSP_SHIFT 1
+#define I2S_TCR4_ONDEM_MASK 0x4u
+#define I2S_TCR4_ONDEM_SHIFT 2
+#define I2S_TCR4_FSE_MASK 0x8u
+#define I2S_TCR4_FSE_SHIFT 3
+#define I2S_TCR4_MF_MASK 0x10u
+#define I2S_TCR4_MF_SHIFT 4
+#define I2S_TCR4_SYWD_MASK 0x1F00u
+#define I2S_TCR4_SYWD_SHIFT 8
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK 0xF0000u
+#define I2S_TCR4_FRSZ_SHIFT 16
+#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
+#define I2S_TCR4_FPACK_MASK 0x3000000u
+#define I2S_TCR4_FPACK_SHIFT 24
+#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
+#define I2S_TCR4_FCONT_MASK 0x10000000u
+#define I2S_TCR4_FCONT_SHIFT 28
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK 0x1F00u
+#define I2S_TCR5_FBT_SHIFT 8
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK 0x1F0000u
+#define I2S_TCR5_W0W_SHIFT 16
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK 0x1F000000u
+#define I2S_TCR5_WNW_SHIFT 24
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT 0
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TFR Bit Fields */
+#define I2S_TFR_RFP_MASK 0xFu
+#define I2S_TFR_RFP_SHIFT 0
+#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK 0xF0000u
+#define I2S_TFR_WFP_SHIFT 16
+#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK 0xFFFFu
+#define I2S_TMR_TWM_SHIFT 0
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FRDE_MASK 0x1u
+#define I2S_RCSR_FRDE_SHIFT 0
+#define I2S_RCSR_FWDE_MASK 0x2u
+#define I2S_RCSR_FWDE_SHIFT 1
+#define I2S_RCSR_FRIE_MASK 0x100u
+#define I2S_RCSR_FRIE_SHIFT 8
+#define I2S_RCSR_FWIE_MASK 0x200u
+#define I2S_RCSR_FWIE_SHIFT 9
+#define I2S_RCSR_FEIE_MASK 0x400u
+#define I2S_RCSR_FEIE_SHIFT 10
+#define I2S_RCSR_SEIE_MASK 0x800u
+#define I2S_RCSR_SEIE_SHIFT 11
+#define I2S_RCSR_WSIE_MASK 0x1000u
+#define I2S_RCSR_WSIE_SHIFT 12
+#define I2S_RCSR_FRF_MASK 0x10000u
+#define I2S_RCSR_FRF_SHIFT 16
+#define I2S_RCSR_FWF_MASK 0x20000u
+#define I2S_RCSR_FWF_SHIFT 17
+#define I2S_RCSR_FEF_MASK 0x40000u
+#define I2S_RCSR_FEF_SHIFT 18
+#define I2S_RCSR_SEF_MASK 0x80000u
+#define I2S_RCSR_SEF_SHIFT 19
+#define I2S_RCSR_WSF_MASK 0x100000u
+#define I2S_RCSR_WSF_SHIFT 20
+#define I2S_RCSR_SR_MASK 0x1000000u
+#define I2S_RCSR_SR_SHIFT 24
+#define I2S_RCSR_FR_MASK 0x2000000u
+#define I2S_RCSR_FR_SHIFT 25
+#define I2S_RCSR_BCE_MASK 0x10000000u
+#define I2S_RCSR_BCE_SHIFT 28
+#define I2S_RCSR_DBGE_MASK 0x20000000u
+#define I2S_RCSR_DBGE_SHIFT 29
+#define I2S_RCSR_STOPE_MASK 0x40000000u
+#define I2S_RCSR_STOPE_SHIFT 30
+#define I2S_RCSR_RE_MASK 0x80000000u
+#define I2S_RCSR_RE_SHIFT 31
+/* RCR1 Bit Fields */
+#define I2S_RCR1_RFW_MASK 0x7u
+#define I2S_RCR1_RFW_SHIFT 0
+#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK 0xFFu
+#define I2S_RCR2_DIV_SHIFT 0
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK 0x1000000u
+#define I2S_RCR2_BCD_SHIFT 24
+#define I2S_RCR2_BCP_MASK 0x2000000u
+#define I2S_RCR2_BCP_SHIFT 25
+#define I2S_RCR2_MSEL_MASK 0xC000000u
+#define I2S_RCR2_MSEL_SHIFT 26
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK 0x10000000u
+#define I2S_RCR2_BCI_SHIFT 28
+#define I2S_RCR2_BCS_MASK 0x20000000u
+#define I2S_RCR2_BCS_SHIFT 29
+#define I2S_RCR2_SYNC_MASK 0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT 30
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK 0xFu
+#define I2S_RCR3_WDFL_SHIFT 0
+#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK 0x10000u
+#define I2S_RCR3_RCE_SHIFT 16
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK 0x1u
+#define I2S_RCR4_FSD_SHIFT 0
+#define I2S_RCR4_FSP_MASK 0x2u
+#define I2S_RCR4_FSP_SHIFT 1
+#define I2S_RCR4_ONDEM_MASK 0x4u
+#define I2S_RCR4_ONDEM_SHIFT 2
+#define I2S_RCR4_FSE_MASK 0x8u
+#define I2S_RCR4_FSE_SHIFT 3
+#define I2S_RCR4_MF_MASK 0x10u
+#define I2S_RCR4_MF_SHIFT 4
+#define I2S_RCR4_SYWD_MASK 0x1F00u
+#define I2S_RCR4_SYWD_SHIFT 8
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK 0xF0000u
+#define I2S_RCR4_FRSZ_SHIFT 16
+#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
+#define I2S_RCR4_FPACK_MASK 0x3000000u
+#define I2S_RCR4_FPACK_SHIFT 24
+#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
+#define I2S_RCR4_FCONT_MASK 0x10000000u
+#define I2S_RCR4_FCONT_SHIFT 28
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK 0x1F00u
+#define I2S_RCR5_FBT_SHIFT 8
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK 0x1F0000u
+#define I2S_RCR5_W0W_SHIFT 16
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK 0x1F000000u
+#define I2S_RCR5_WNW_SHIFT 24
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT 0
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RFR Bit Fields */
+#define I2S_RFR_RFP_MASK 0xFu
+#define I2S_RFR_RFP_SHIFT 0
+#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK 0xF0000u
+#define I2S_RFR_WFP_SHIFT 16
+#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK 0xFFFFu
+#define I2S_RMR_RWM_SHIFT 0
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK 0x3000000u
+#define I2S_MCR_MICS_SHIFT 24
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK 0x40000000u
+#define I2S_MCR_MOE_SHIFT 30
+#define I2S_MCR_DUF_MASK 0x80000000u
+#define I2S_MCR_DUF_SHIFT 31
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK 0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT 0
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK 0xFF000u
+#define I2S_MDR_FRACT_SHIFT 12
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+#define I2S0_BASE_PTR (I2S0)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS { I2S0_Rx_IRQn }
+#define I2S_TX_IRQS { I2S0_Tx_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- I2S - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register instance definitions */
+/* I2S0 */
+#define I2S0_TCSR I2S_TCSR_REG(I2S0)
+#define I2S0_TCR1 I2S_TCR1_REG(I2S0)
+#define I2S0_TCR2 I2S_TCR2_REG(I2S0)
+#define I2S0_TCR3 I2S_TCR3_REG(I2S0)
+#define I2S0_TCR4 I2S_TCR4_REG(I2S0)
+#define I2S0_TCR5 I2S_TCR5_REG(I2S0)
+#define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
+#define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
+#define I2S0_TMR I2S_TMR_REG(I2S0)
+#define I2S0_RCSR I2S_RCSR_REG(I2S0)
+#define I2S0_RCR1 I2S_RCR1_REG(I2S0)
+#define I2S0_RCR2 I2S_RCR2_REG(I2S0)
+#define I2S0_RCR3 I2S_RCR3_REG(I2S0)
+#define I2S0_RCR4 I2S_RCR4_REG(I2S0)
+#define I2S0_RCR5 I2S_RCR5_REG(I2S0)
+#define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
+#define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
+#define I2S0_RMR I2S_RMR_REG(I2S0)
+#define I2S0_MCR I2S_MCR_REG(I2S0)
+#define I2S0_MDR I2S_MDR_REG(I2S0)
+
+/* I2S - Register array accessors */
+#define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
+#define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
+#define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
+#define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
+} LLWU_Type, *LLWU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register accessors */
+#define LLWU_PE1_REG(base) ((base)->PE1)
+#define LLWU_PE2_REG(base) ((base)->PE2)
+#define LLWU_PE3_REG(base) ((base)->PE3)
+#define LLWU_PE4_REG(base) ((base)->PE4)
+#define LLWU_ME_REG(base) ((base)->ME)
+#define LLWU_F1_REG(base) ((base)->F1)
+#define LLWU_F2_REG(base) ((base)->F2)
+#define LLWU_F3_REG(base) ((base)->F3)
+#define LLWU_FILT1_REG(base) ((base)->FILT1)
+#define LLWU_FILT2_REG(base) ((base)->FILT2)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+#define LLWU_BASE_PTR (LLWU)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS { LLW_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LLWU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register instance definitions */
+/* LLWU */
+#define LLWU_PE1 LLWU_PE1_REG(LLWU)
+#define LLWU_PE2 LLWU_PE2_REG(LLWU)
+#define LLWU_PE3 LLWU_PE3_REG(LLWU)
+#define LLWU_PE4 LLWU_PE4_REG(LLWU)
+#define LLWU_ME LLWU_ME_REG(LLWU)
+#define LLWU_F1 LLWU_F1_REG(LLWU)
+#define LLWU_F2 LLWU_F2_REG(LLWU)
+#define LLWU_F3 LLWU_F3_REG(LLWU)
+#define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
+#define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register accessors */
+#define LPTMR_CSR_REG(base) ((base)->CSR)
+#define LPTMR_PSR_REG(base) ((base)->PSR)
+#define LPTMR_CMR_REG(base) ((base)->CMR)
+#define LPTMR_CNR_REG(base) ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0_BASE_PTR (LPTMR0)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS { LPTimer_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register instance definitions */
+/* LPTMR0 */
+#define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
+#define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
+#define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
+#define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPUART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
+ * @{
+ */
+
+/** LPUART - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
+ __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
+ __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
+ __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
+ __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
+ __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
+} LPUART_Type, *LPUART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LPUART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
+ * @{
+ */
+
+
+/* LPUART - Register accessors */
+#define LPUART_BAUD_REG(base) ((base)->BAUD)
+#define LPUART_STAT_REG(base) ((base)->STAT)
+#define LPUART_CTRL_REG(base) ((base)->CTRL)
+#define LPUART_DATA_REG(base) ((base)->DATA)
+#define LPUART_MATCH_REG(base) ((base)->MATCH)
+#define LPUART_MODIR_REG(base) ((base)->MODIR)
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPUART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Masks LPUART Register Masks
+ * @{
+ */
+
+/* BAUD Bit Fields */
+#define LPUART_BAUD_SBR_MASK 0x1FFFu
+#define LPUART_BAUD_SBR_SHIFT 0
+#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
+#define LPUART_BAUD_SBNS_MASK 0x2000u
+#define LPUART_BAUD_SBNS_SHIFT 13
+#define LPUART_BAUD_RXEDGIE_MASK 0x4000u
+#define LPUART_BAUD_RXEDGIE_SHIFT 14
+#define LPUART_BAUD_LBKDIE_MASK 0x8000u
+#define LPUART_BAUD_LBKDIE_SHIFT 15
+#define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
+#define LPUART_BAUD_RESYNCDIS_SHIFT 16
+#define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
+#define LPUART_BAUD_BOTHEDGE_SHIFT 17
+#define LPUART_BAUD_MATCFG_MASK 0xC0000u
+#define LPUART_BAUD_MATCFG_SHIFT 18
+#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
+#define LPUART_BAUD_RDMAE_MASK 0x200000u
+#define LPUART_BAUD_RDMAE_SHIFT 21
+#define LPUART_BAUD_TDMAE_MASK 0x800000u
+#define LPUART_BAUD_TDMAE_SHIFT 23
+#define LPUART_BAUD_OSR_MASK 0x1F000000u
+#define LPUART_BAUD_OSR_SHIFT 24
+#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
+#define LPUART_BAUD_M10_MASK 0x20000000u
+#define LPUART_BAUD_M10_SHIFT 29
+#define LPUART_BAUD_MAEN2_MASK 0x40000000u
+#define LPUART_BAUD_MAEN2_SHIFT 30
+#define LPUART_BAUD_MAEN1_MASK 0x80000000u
+#define LPUART_BAUD_MAEN1_SHIFT 31
+/* STAT Bit Fields */
+#define LPUART_STAT_MA2F_MASK 0x4000u
+#define LPUART_STAT_MA2F_SHIFT 14
+#define LPUART_STAT_MA1F_MASK 0x8000u
+#define LPUART_STAT_MA1F_SHIFT 15
+#define LPUART_STAT_PF_MASK 0x10000u
+#define LPUART_STAT_PF_SHIFT 16
+#define LPUART_STAT_FE_MASK 0x20000u
+#define LPUART_STAT_FE_SHIFT 17
+#define LPUART_STAT_NF_MASK 0x40000u
+#define LPUART_STAT_NF_SHIFT 18
+#define LPUART_STAT_OR_MASK 0x80000u
+#define LPUART_STAT_OR_SHIFT 19
+#define LPUART_STAT_IDLE_MASK 0x100000u
+#define LPUART_STAT_IDLE_SHIFT 20
+#define LPUART_STAT_RDRF_MASK 0x200000u
+#define LPUART_STAT_RDRF_SHIFT 21
+#define LPUART_STAT_TC_MASK 0x400000u
+#define LPUART_STAT_TC_SHIFT 22
+#define LPUART_STAT_TDRE_MASK 0x800000u
+#define LPUART_STAT_TDRE_SHIFT 23
+#define LPUART_STAT_RAF_MASK 0x1000000u
+#define LPUART_STAT_RAF_SHIFT 24
+#define LPUART_STAT_LBKDE_MASK 0x2000000u
+#define LPUART_STAT_LBKDE_SHIFT 25
+#define LPUART_STAT_BRK13_MASK 0x4000000u
+#define LPUART_STAT_BRK13_SHIFT 26
+#define LPUART_STAT_RWUID_MASK 0x8000000u
+#define LPUART_STAT_RWUID_SHIFT 27
+#define LPUART_STAT_RXINV_MASK 0x10000000u
+#define LPUART_STAT_RXINV_SHIFT 28
+#define LPUART_STAT_MSBF_MASK 0x20000000u
+#define LPUART_STAT_MSBF_SHIFT 29
+#define LPUART_STAT_RXEDGIF_MASK 0x40000000u
+#define LPUART_STAT_RXEDGIF_SHIFT 30
+#define LPUART_STAT_LBKDIF_MASK 0x80000000u
+#define LPUART_STAT_LBKDIF_SHIFT 31
+/* CTRL Bit Fields */
+#define LPUART_CTRL_PT_MASK 0x1u
+#define LPUART_CTRL_PT_SHIFT 0
+#define LPUART_CTRL_PE_MASK 0x2u
+#define LPUART_CTRL_PE_SHIFT 1
+#define LPUART_CTRL_ILT_MASK 0x4u
+#define LPUART_CTRL_ILT_SHIFT 2
+#define LPUART_CTRL_WAKE_MASK 0x8u
+#define LPUART_CTRL_WAKE_SHIFT 3
+#define LPUART_CTRL_M_MASK 0x10u
+#define LPUART_CTRL_M_SHIFT 4
+#define LPUART_CTRL_RSRC_MASK 0x20u
+#define LPUART_CTRL_RSRC_SHIFT 5
+#define LPUART_CTRL_DOZEEN_MASK 0x40u
+#define LPUART_CTRL_DOZEEN_SHIFT 6
+#define LPUART_CTRL_LOOPS_MASK 0x80u
+#define LPUART_CTRL_LOOPS_SHIFT 7
+#define LPUART_CTRL_IDLECFG_MASK 0x700u
+#define LPUART_CTRL_IDLECFG_SHIFT 8
+#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
+#define LPUART_CTRL_MA2IE_MASK 0x4000u
+#define LPUART_CTRL_MA2IE_SHIFT 14
+#define LPUART_CTRL_MA1IE_MASK 0x8000u
+#define LPUART_CTRL_MA1IE_SHIFT 15
+#define LPUART_CTRL_SBK_MASK 0x10000u
+#define LPUART_CTRL_SBK_SHIFT 16
+#define LPUART_CTRL_RWU_MASK 0x20000u
+#define LPUART_CTRL_RWU_SHIFT 17
+#define LPUART_CTRL_RE_MASK 0x40000u
+#define LPUART_CTRL_RE_SHIFT 18
+#define LPUART_CTRL_TE_MASK 0x80000u
+#define LPUART_CTRL_TE_SHIFT 19
+#define LPUART_CTRL_ILIE_MASK 0x100000u
+#define LPUART_CTRL_ILIE_SHIFT 20
+#define LPUART_CTRL_RIE_MASK 0x200000u
+#define LPUART_CTRL_RIE_SHIFT 21
+#define LPUART_CTRL_TCIE_MASK 0x400000u
+#define LPUART_CTRL_TCIE_SHIFT 22
+#define LPUART_CTRL_TIE_MASK 0x800000u
+#define LPUART_CTRL_TIE_SHIFT 23
+#define LPUART_CTRL_PEIE_MASK 0x1000000u
+#define LPUART_CTRL_PEIE_SHIFT 24
+#define LPUART_CTRL_FEIE_MASK 0x2000000u
+#define LPUART_CTRL_FEIE_SHIFT 25
+#define LPUART_CTRL_NEIE_MASK 0x4000000u
+#define LPUART_CTRL_NEIE_SHIFT 26
+#define LPUART_CTRL_ORIE_MASK 0x8000000u
+#define LPUART_CTRL_ORIE_SHIFT 27
+#define LPUART_CTRL_TXINV_MASK 0x10000000u
+#define LPUART_CTRL_TXINV_SHIFT 28
+#define LPUART_CTRL_TXDIR_MASK 0x20000000u
+#define LPUART_CTRL_TXDIR_SHIFT 29
+#define LPUART_CTRL_R9T8_MASK 0x40000000u
+#define LPUART_CTRL_R9T8_SHIFT 30
+#define LPUART_CTRL_R8T9_MASK 0x80000000u
+#define LPUART_CTRL_R8T9_SHIFT 31
+/* DATA Bit Fields */
+#define LPUART_DATA_R0T0_MASK 0x1u
+#define LPUART_DATA_R0T0_SHIFT 0
+#define LPUART_DATA_R1T1_MASK 0x2u
+#define LPUART_DATA_R1T1_SHIFT 1
+#define LPUART_DATA_R2T2_MASK 0x4u
+#define LPUART_DATA_R2T2_SHIFT 2
+#define LPUART_DATA_R3T3_MASK 0x8u
+#define LPUART_DATA_R3T3_SHIFT 3
+#define LPUART_DATA_R4T4_MASK 0x10u
+#define LPUART_DATA_R4T4_SHIFT 4
+#define LPUART_DATA_R5T5_MASK 0x20u
+#define LPUART_DATA_R5T5_SHIFT 5
+#define LPUART_DATA_R6T6_MASK 0x40u
+#define LPUART_DATA_R6T6_SHIFT 6
+#define LPUART_DATA_R7T7_MASK 0x80u
+#define LPUART_DATA_R7T7_SHIFT 7
+#define LPUART_DATA_R8T8_MASK 0x100u
+#define LPUART_DATA_R8T8_SHIFT 8
+#define LPUART_DATA_R9T9_MASK 0x200u
+#define LPUART_DATA_R9T9_SHIFT 9
+#define LPUART_DATA_IDLINE_MASK 0x800u
+#define LPUART_DATA_IDLINE_SHIFT 11
+#define LPUART_DATA_RXEMPT_MASK 0x1000u
+#define LPUART_DATA_RXEMPT_SHIFT 12
+#define LPUART_DATA_FRETSC_MASK 0x2000u
+#define LPUART_DATA_FRETSC_SHIFT 13
+#define LPUART_DATA_PARITYE_MASK 0x4000u
+#define LPUART_DATA_PARITYE_SHIFT 14
+#define LPUART_DATA_NOISY_MASK 0x8000u
+#define LPUART_DATA_NOISY_SHIFT 15
+/* MATCH Bit Fields */
+#define LPUART_MATCH_MA1_MASK 0x3FFu
+#define LPUART_MATCH_MA1_SHIFT 0
+#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
+#define LPUART_MATCH_MA2_MASK 0x3FF0000u
+#define LPUART_MATCH_MA2_SHIFT 16
+#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
+/* MODIR Bit Fields */
+#define LPUART_MODIR_TXCTSE_MASK 0x1u
+#define LPUART_MODIR_TXCTSE_SHIFT 0
+#define LPUART_MODIR_TXRTSE_MASK 0x2u
+#define LPUART_MODIR_TXRTSE_SHIFT 1
+#define LPUART_MODIR_TXRTSPOL_MASK 0x4u
+#define LPUART_MODIR_TXRTSPOL_SHIFT 2
+#define LPUART_MODIR_RXRTSE_MASK 0x8u
+#define LPUART_MODIR_RXRTSE_SHIFT 3
+#define LPUART_MODIR_TXCTSC_MASK 0x10u
+#define LPUART_MODIR_TXCTSC_SHIFT 4
+#define LPUART_MODIR_TXCTSSRC_MASK 0x20u
+#define LPUART_MODIR_TXCTSSRC_SHIFT 5
+#define LPUART_MODIR_TNP_MASK 0x30000u
+#define LPUART_MODIR_TNP_SHIFT 16
+#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MODIR_TNP_SHIFT))&LPUART_MODIR_TNP_MASK)
+#define LPUART_MODIR_IREN_MASK 0x40000u
+#define LPUART_MODIR_IREN_SHIFT 18
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Masks */
+
+
+/* LPUART - Peripheral instance base addresses */
+/** Peripheral LPUART0 base address */
+#define LPUART0_BASE (0x4002A000u)
+/** Peripheral LPUART0 base pointer */
+#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
+#define LPUART0_BASE_PTR (LPUART0)
+/** Array initializer of LPUART peripheral base addresses */
+#define LPUART_BASE_ADDRS { LPUART0_BASE }
+/** Array initializer of LPUART peripheral base pointers */
+#define LPUART_BASE_PTRS { LPUART0 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS { LPUART0_IRQn }
+#define LPUART_ERR_IRQS { LPUART0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LPUART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
+ * @{
+ */
+
+
+/* LPUART - Register instance definitions */
+/* LPUART0 */
+#define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
+#define LPUART0_STAT LPUART_STAT_REG(LPUART0)
+#define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
+#define LPUART0_DATA LPUART_DATA_REG(LPUART0)
+#define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
+#define LPUART0_MODIR LPUART_MODIR_REG(LPUART0)
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPUART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+} MCG_Type, *MCG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MCG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register accessors */
+#define MCG_C1_REG(base) ((base)->C1)
+#define MCG_C2_REG(base) ((base)->C2)
+#define MCG_C3_REG(base) ((base)->C3)
+#define MCG_C4_REG(base) ((base)->C4)
+#define MCG_C5_REG(base) ((base)->C5)
+#define MCG_C6_REG(base) ((base)->C6)
+#define MCG_S_REG(base) ((base)->S)
+#define MCG_SC_REG(base) ((base)->SC)
+#define MCG_ATCVH_REG(base) ((base)->ATCVH)
+#define MCG_ATCVL_REG(base) ((base)->ATCVL)
+#define MCG_C7_REG(base) ((base)->C7)
+#define MCG_C8_REG(base) ((base)->C8)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS_MASK 0x4u
+#define MCG_C2_EREFS_SHIFT 2
+#define MCG_C2_HGO_MASK 0x8u
+#define MCG_C2_HGO_SHIFT 3
+#define MCG_C2_RANGE_MASK 0x30u
+#define MCG_C2_RANGE_SHIFT 4
+#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK 0x40u
+#define MCG_C2_FCFTRIM_SHIFT 6
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK 0x1Fu
+#define MCG_C5_PRDIV0_SHIFT 0
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK 0x20u
+#define MCG_C5_PLLSTEN0_SHIFT 5
+#define MCG_C5_PLLCLKEN0_MASK 0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT 6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK 0x1Fu
+#define MCG_C6_VDIV0_SHIFT 0
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK 0x20u
+#define MCG_C6_CME0_SHIFT 5
+#define MCG_C6_PLLS_MASK 0x40u
+#define MCG_C6_PLLS_SHIFT 6
+#define MCG_C6_LOLIE0_MASK 0x80u
+#define MCG_C6_LOLIE0_SHIFT 7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+#define MCG_S_PLLST_MASK 0x20u
+#define MCG_S_PLLST_SHIFT 5
+#define MCG_S_LOCK0_MASK 0x40u
+#define MCG_S_LOCK0_SHIFT 6
+#define MCG_S_LOLS0_MASK 0x80u
+#define MCG_S_LOLS0_SHIFT 7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C7 Bit Fields */
+#define MCG_C7_OSCSEL_MASK 0x3u
+#define MCG_C7_OSCSEL_SHIFT 0
+#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOCS1_MASK 0x1u
+#define MCG_C8_LOCS1_SHIFT 0
+#define MCG_C8_CME1_MASK 0x20u
+#define MCG_C8_CME1_SHIFT 5
+#define MCG_C8_LOLRE_MASK 0x40u
+#define MCG_C8_LOLRE_SHIFT 6
+#define MCG_C8_LOCRE1_MASK 0x80u
+#define MCG_C8_LOCRE1_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+#define MCG_BASE_PTR (MCG)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS { MCG }
+
+/* ----------------------------------------------------------------------------
+ -- MCG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register instance definitions */
+/* MCG */
+#define MCG_C1 MCG_C1_REG(MCG)
+#define MCG_C2 MCG_C2_REG(MCG)
+#define MCG_C3 MCG_C3_REG(MCG)
+#define MCG_C4 MCG_C4_REG(MCG)
+#define MCG_C5 MCG_C5_REG(MCG)
+#define MCG_C6 MCG_C6_REG(MCG)
+#define MCG_S MCG_S_REG(MCG)
+#define MCG_SC MCG_SC_REG(MCG)
+#define MCG_ATCVH MCG_ATCVH_REG(MCG)
+#define MCG_ATCVL MCG_ATCVL_REG(MCG)
+#define MCG_C7 MCG_C7_REG(MCG)
+#define MCG_C8 MCG_C8_REG(MCG)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
+ __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */
+ uint8_t RESERVED_1[44];
+ __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type, *MCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register accessors */
+#define MCM_PLASC_REG(base) ((base)->PLASC)
+#define MCM_PLAMC_REG(base) ((base)->PLAMC)
+#define MCM_PLACR_REG(base) ((base)->PLACR)
+#define MCM_ISCR_REG(base) ((base)->ISCR)
+#define MCM_CPO_REG(base) ((base)->CPO)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK 0xFFu
+#define MCM_PLASC_ASC_SHIFT 0
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK 0xFFu
+#define MCM_PLAMC_AMC_SHIFT 0
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_ARB_MASK 0x200u
+#define MCM_PLACR_ARB_SHIFT 9
+/* ISCR Bit Fields */
+#define MCM_ISCR_FIOC_MASK 0x100u
+#define MCM_ISCR_FIOC_SHIFT 8
+#define MCM_ISCR_FDZC_MASK 0x200u
+#define MCM_ISCR_FDZC_SHIFT 9
+#define MCM_ISCR_FOFC_MASK 0x400u
+#define MCM_ISCR_FOFC_SHIFT 10
+#define MCM_ISCR_FUFC_MASK 0x800u
+#define MCM_ISCR_FUFC_SHIFT 11
+#define MCM_ISCR_FIXC_MASK 0x1000u
+#define MCM_ISCR_FIXC_SHIFT 12
+#define MCM_ISCR_FIDC_MASK 0x8000u
+#define MCM_ISCR_FIDC_SHIFT 15
+#define MCM_ISCR_FIOCE_MASK 0x1000000u
+#define MCM_ISCR_FIOCE_SHIFT 24
+#define MCM_ISCR_FDZCE_MASK 0x2000000u
+#define MCM_ISCR_FDZCE_SHIFT 25
+#define MCM_ISCR_FOFCE_MASK 0x4000000u
+#define MCM_ISCR_FOFCE_SHIFT 26
+#define MCM_ISCR_FUFCE_MASK 0x8000000u
+#define MCM_ISCR_FUFCE_SHIFT 27
+#define MCM_ISCR_FIXCE_MASK 0x10000000u
+#define MCM_ISCR_FIXCE_SHIFT 28
+#define MCM_ISCR_FIDCE_MASK 0x80000000u
+#define MCM_ISCR_FIDCE_SHIFT 31
+/* CPO Bit Fields */
+#define MCM_CPO_CPOREQ_MASK 0x1u
+#define MCM_CPO_CPOREQ_SHIFT 0
+#define MCM_CPO_CPOACK_MASK 0x2u
+#define MCM_CPO_CPOACK_SHIFT 1
+#define MCM_CPO_CPOWOI_MASK 0x4u
+#define MCM_CPO_CPOWOI_SHIFT 2
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xE0080000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+#define MCM_BASE_PTR (MCM)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS { MCM }
+
+/* ----------------------------------------------------------------------------
+ -- MCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register instance definitions */
+/* MCM */
+#define MCM_PLASC MCM_PLASC_REG(MCM)
+#define MCM_PLAMC MCM_PLAMC_REG(MCM)
+#define MCM_PLACR MCM_PLACR_REG(MCM)
+#define MCM_ISCR MCM_ISCR_REG(MCM)
+#define MCM_CPO MCM_CPO_REG(MCM)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type, *NV_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- NV - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register accessors */
+#define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
+#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base) ((base)->FPROT3)
+#define NV_FPROT2_REG(base) ((base)->FPROT2)
+#define NV_FPROT1_REG(base) ((base)->FPROT1)
+#define NV_FPROT0_REG(base) ((base)->FPROT0)
+#define NV_FSEC_REG(base) ((base)->FSEC)
+#define NV_FOPT_REG(base) ((base)->FOPT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK 0x1u
+#define NV_FOPT_LPBOOT_SHIFT 0
+#define NV_FOPT_EZPORT_DIS_MASK 0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT 1
+#define NV_FOPT_NMI_DIS_MASK 0x4u
+#define NV_FOPT_NMI_DIS_SHIFT 2
+#define NV_FOPT_FAST_INIT_MASK 0x20u
+#define NV_FOPT_FAST_INIT_SHIFT 5
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
+#define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS { FTFA_FlashConfig }
+
+/* ----------------------------------------------------------------------------
+ -- NV - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register instance definitions */
+/* FTFA_FlashConfig */
+#define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
+#define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
+#define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
+#define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
+#define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
+#define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
+#define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
+#define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
+#define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
+#define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
+#define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
+#define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
+#define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
+#define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
+} OSC_Type, *OSC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- OSC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register accessors */
+#define OSC_CR_REG(base) ((base)->CR)
+#define OSC_DIV_REG(base) ((base)->DIV)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+/* DIV Bit Fields */
+#define OSC_DIV_ERPS_MASK 0xC0u
+#define OSC_DIV_ERPS_SHIFT 6
+#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x))<<OSC_DIV_ERPS_SHIFT))&OSC_DIV_ERPS_MASK)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC ((OSC_Type *)OSC_BASE)
+#define OSC_BASE_PTR (OSC)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS { OSC_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS { OSC }
+
+/* ----------------------------------------------------------------------------
+ -- OSC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC */
+#define OSC_CR OSC_CR_REG(OSC)
+#define OSC_DIV OSC_DIV_REG(OSC)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
+ __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
+ __I uint32_t CNT; /**< Counter register, offset: 0x8 */
+ __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
+ struct { /* offset: 0x10, array step: 0x28 */
+ __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
+ __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
+ __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+ uint8_t RESERVED_0[24];
+ } CH[2];
+ uint8_t RESERVED_0[240];
+ struct { /* offset: 0x150, array step: 0x8 */
+ __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
+ __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
+ } DAC[2];
+ uint8_t RESERVED_1[48];
+ __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
+ __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
+} PDB_Type, *PDB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PDB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register accessors */
+#define PDB_SC_REG(base) ((base)->SC)
+#define PDB_MOD_REG(base) ((base)->MOD)
+#define PDB_CNT_REG(base) ((base)->CNT)
+#define PDB_IDLY_REG(base) ((base)->IDLY)
+#define PDB_C1_REG(base,index) ((base)->CH[index].C1)
+#define PDB_S_REG(base,index) ((base)->CH[index].S)
+#define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
+#define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
+#define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
+#define PDB_POEN_REG(base) ((base)->POEN)
+#define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PDB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK 0x1u
+#define PDB_SC_LDOK_SHIFT 0
+#define PDB_SC_CONT_MASK 0x2u
+#define PDB_SC_CONT_SHIFT 1
+#define PDB_SC_MULT_MASK 0xCu
+#define PDB_SC_MULT_SHIFT 2
+#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK 0x20u
+#define PDB_SC_PDBIE_SHIFT 5
+#define PDB_SC_PDBIF_MASK 0x40u
+#define PDB_SC_PDBIF_SHIFT 6
+#define PDB_SC_PDBEN_MASK 0x80u
+#define PDB_SC_PDBEN_SHIFT 7
+#define PDB_SC_TRGSEL_MASK 0xF00u
+#define PDB_SC_TRGSEL_SHIFT 8
+#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK 0x7000u
+#define PDB_SC_PRESCALER_SHIFT 12
+#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK 0x8000u
+#define PDB_SC_DMAEN_SHIFT 15
+#define PDB_SC_SWTRIG_MASK 0x10000u
+#define PDB_SC_SWTRIG_SHIFT 16
+#define PDB_SC_PDBEIE_MASK 0x20000u
+#define PDB_SC_PDBEIE_SHIFT 17
+#define PDB_SC_LDMOD_MASK 0xC0000u
+#define PDB_SC_LDMOD_SHIFT 18
+#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK 0xFFFFu
+#define PDB_MOD_MOD_SHIFT 0
+#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK 0xFFFFu
+#define PDB_CNT_CNT_SHIFT 0
+#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK 0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT 0
+#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK 0xFFu
+#define PDB_C1_EN_SHIFT 0
+#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK 0xFF00u
+#define PDB_C1_TOS_SHIFT 8
+#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK 0xFF0000u
+#define PDB_C1_BB_SHIFT 16
+#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK 0xFFu
+#define PDB_S_ERR_SHIFT 0
+#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK 0xFF0000u
+#define PDB_S_CF_SHIFT 16
+#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK 0xFFFFu
+#define PDB_DLY_DLY_SHIFT 0
+#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* INTC Bit Fields */
+#define PDB_INTC_TOE_MASK 0x1u
+#define PDB_INTC_TOE_SHIFT 0
+#define PDB_INTC_EXT_MASK 0x2u
+#define PDB_INTC_EXT_SHIFT 1
+/* INT Bit Fields */
+#define PDB_INT_INT_MASK 0xFFFFu
+#define PDB_INT_INT_SHIFT 0
+#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK 0xFFu
+#define PDB_POEN_POEN_SHIFT 0
+#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK 0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT 0
+#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK 0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT 16
+#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0 ((PDB_Type *)PDB0_BASE)
+#define PDB0_BASE_PTR (PDB0)
+/** Array initializer of PDB peripheral base addresses */
+#define PDB_BASE_ADDRS { PDB0_BASE }
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASE_PTRS { PDB0 }
+/** Interrupt vectors for the PDB peripheral type */
+#define PDB_IRQS { PDB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PDB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
+ * @{
+ */
+
+
+/* PDB - Register instance definitions */
+/* PDB0 */
+#define PDB0_SC PDB_SC_REG(PDB0)
+#define PDB0_MOD PDB_MOD_REG(PDB0)
+#define PDB0_CNT PDB_CNT_REG(PDB0)
+#define PDB0_IDLY PDB_IDLY_REG(PDB0)
+#define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
+#define PDB0_CH0S PDB_S_REG(PDB0,0)
+#define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
+#define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
+#define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
+#define PDB0_CH1S PDB_S_REG(PDB0,1)
+#define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
+#define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
+#define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
+#define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
+#define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
+#define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
+#define PDB0_POEN PDB_POEN_REG(PDB0)
+#define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
+#define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
+
+/* PDB - Register array accessors */
+#define PDB0_C1(index) PDB_C1_REG(PDB0,index)
+#define PDB0_S(index) PDB_S_REG(PDB0,index)
+#define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
+#define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
+#define PDB0_INT(index) PDB_INT_REG(PDB0,index)
+#define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[252];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[4];
+} PIT_Type, *PIT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PIT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register accessors */
+#define PIT_MCR_REG(base) ((base)->MCR)
+#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
+#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
+#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
+#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+#define PIT_TCTRL_CHN_MASK 0x4u
+#define PIT_TCTRL_CHN_SHIFT 2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+#define PIT_BASE_PTR (PIT)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PIT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register instance definitions */
+/* PIT */
+#define PIT_MCR PIT_MCR_REG(PIT)
+#define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
+#define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
+#define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
+#define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
+#define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
+#define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
+#define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
+#define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
+#define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
+#define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
+#define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
+#define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
+#define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
+#define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
+#define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
+#define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
+
+/* PIT - Register array accessors */
+#define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
+#define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
+#define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
+#define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type, *PMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register accessors */
+#define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
+#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
+#define PMC_REGSC_REG(base) ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+#define PMC_REGSC_BGEN_MASK 0x10u
+#define PMC_REGSC_BGEN_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+#define PMC_BASE_PTR (PMC)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS { LVD_LVW_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register instance definitions */
+/* PMC */
+#define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
+#define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
+#define PMC_REGSC PMC_REGSC_REG(PMC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
+ __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
+ __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type, *PORT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PORT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register accessors */
+#define PORT_PCR_REG(base,index) ((base)->PCR[index])
+#define PORT_GPCLR_REG(base) ((base)->GPCLR)
+#define PORT_GPCHR_REG(base) ((base)->GPCHR)
+#define PORT_ISFR_REG(base) ((base)->ISFR)
+#define PORT_DFER_REG(base) ((base)->DFER)
+#define PORT_DFCR_REG(base) ((base)->DFCR)
+#define PORT_DFWR_REG(base) ((base)->DFWR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_ODE_MASK 0x20u
+#define PORT_PCR_ODE_SHIFT 5
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK 0x8000u
+#define PORT_PCR_LK_SHIFT 15
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK 0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT 0
+#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK 0x1u
+#define PORT_DFCR_CS_SHIFT 0
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK 0x1Fu
+#define PORT_DFWR_FILT_SHIFT 0
+#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+#define PORTA_BASE_PTR (PORTA)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+#define PORTB_BASE_PTR (PORTB)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+#define PORTC_BASE_PTR (PORTC)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+#define PORTD_BASE_PTR (PORTD)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+#define PORTE_BASE_PTR (PORTE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PORT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register instance definitions */
+/* PORTA */
+#define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
+#define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
+#define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
+#define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
+#define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
+#define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
+#define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
+#define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
+#define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
+#define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
+#define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
+#define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
+#define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
+#define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
+#define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
+#define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
+#define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
+#define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
+#define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
+#define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
+#define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
+#define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
+#define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
+#define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
+#define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
+#define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
+#define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
+#define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
+#define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
+#define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
+#define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
+#define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
+#define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
+#define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
+#define PORTA_ISFR PORT_ISFR_REG(PORTA)
+/* PORTB */
+#define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
+#define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
+#define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
+#define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
+#define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
+#define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
+#define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
+#define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
+#define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
+#define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
+#define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
+#define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
+#define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
+#define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
+#define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
+#define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
+#define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
+#define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
+#define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
+#define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
+#define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
+#define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
+#define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
+#define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
+#define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
+#define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
+#define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
+#define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
+#define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
+#define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
+#define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
+#define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
+#define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
+#define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
+#define PORTB_ISFR PORT_ISFR_REG(PORTB)
+/* PORTC */
+#define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
+#define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
+#define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
+#define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
+#define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
+#define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
+#define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
+#define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
+#define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
+#define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
+#define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
+#define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
+#define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
+#define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
+#define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
+#define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
+#define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
+#define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
+#define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
+#define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
+#define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
+#define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
+#define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
+#define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
+#define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
+#define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
+#define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
+#define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
+#define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
+#define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
+#define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
+#define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
+#define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
+#define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
+#define PORTC_ISFR PORT_ISFR_REG(PORTC)
+/* PORTD */
+#define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
+#define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
+#define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
+#define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
+#define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
+#define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
+#define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
+#define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
+#define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
+#define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
+#define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
+#define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
+#define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
+#define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
+#define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
+#define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
+#define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
+#define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
+#define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
+#define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
+#define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
+#define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
+#define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
+#define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
+#define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
+#define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
+#define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
+#define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
+#define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
+#define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
+#define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
+#define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
+#define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
+#define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
+#define PORTD_ISFR PORT_ISFR_REG(PORTD)
+#define PORTD_DFER PORT_DFER_REG(PORTD)
+#define PORTD_DFCR PORT_DFCR_REG(PORTD)
+#define PORTD_DFWR PORT_DFWR_REG(PORTD)
+/* PORTE */
+#define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
+#define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
+#define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
+#define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
+#define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
+#define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
+#define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
+#define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
+#define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
+#define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
+#define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
+#define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
+#define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
+#define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
+#define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
+#define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
+#define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
+#define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
+#define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
+#define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
+#define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
+#define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
+#define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
+#define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
+#define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
+#define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
+#define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
+#define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
+#define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
+#define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
+#define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
+#define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
+#define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
+#define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
+#define PORTE_ISFR PORT_ISFR_REG(PORTE)
+
+/* PORT - Register array accessors */
+#define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
+#define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
+#define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
+#define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
+#define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __I uint8_t MR; /**< Mode Register, offset: 0x7 */
+ __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
+ __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
+} RCM_Type, *RCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register accessors */
+#define RCM_SRS0_REG(base) ((base)->SRS0)
+#define RCM_SRS1_REG(base) ((base)->SRS1)
+#define RCM_RPFC_REG(base) ((base)->RPFC)
+#define RCM_RPFW_REG(base) ((base)->RPFW)
+#define RCM_MR_REG(base) ((base)->MR)
+#define RCM_SSRS0_REG(base) ((base)->SSRS0)
+#define RCM_SSRS1_REG(base) ((base)->SSRS1)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_LOL_MASK 0x8u
+#define RCM_SRS0_LOL_SHIFT 3
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_JTAG_MASK 0x1u
+#define RCM_SRS1_JTAG_SHIFT 0
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_EZPT_MASK 0x10u
+#define RCM_SRS1_EZPT_SHIFT 4
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* MR Bit Fields */
+#define RCM_MR_EZP_MS_MASK 0x2u
+#define RCM_MR_EZP_MS_SHIFT 1
+/* SSRS0 Bit Fields */
+#define RCM_SSRS0_SWAKEUP_MASK 0x1u
+#define RCM_SSRS0_SWAKEUP_SHIFT 0
+#define RCM_SSRS0_SLVD_MASK 0x2u
+#define RCM_SSRS0_SLVD_SHIFT 1
+#define RCM_SSRS0_SLOC_MASK 0x4u
+#define RCM_SSRS0_SLOC_SHIFT 2
+#define RCM_SSRS0_SLOL_MASK 0x8u
+#define RCM_SSRS0_SLOL_SHIFT 3
+#define RCM_SSRS0_SWDOG_MASK 0x20u
+#define RCM_SSRS0_SWDOG_SHIFT 5
+#define RCM_SSRS0_SPIN_MASK 0x40u
+#define RCM_SSRS0_SPIN_SHIFT 6
+#define RCM_SSRS0_SPOR_MASK 0x80u
+#define RCM_SSRS0_SPOR_SHIFT 7
+/* SSRS1 Bit Fields */
+#define RCM_SSRS1_SJTAG_MASK 0x1u
+#define RCM_SSRS1_SJTAG_SHIFT 0
+#define RCM_SSRS1_SLOCKUP_MASK 0x2u
+#define RCM_SSRS1_SLOCKUP_SHIFT 1
+#define RCM_SSRS1_SSW_MASK 0x4u
+#define RCM_SSRS1_SSW_SHIFT 2
+#define RCM_SSRS1_SMDM_AP_MASK 0x8u
+#define RCM_SSRS1_SMDM_AP_SHIFT 3
+#define RCM_SSRS1_SEZPT_MASK 0x10u
+#define RCM_SSRS1_SEZPT_SHIFT 4
+#define RCM_SSRS1_SSACKERR_MASK 0x20u
+#define RCM_SSRS1_SSACKERR_SHIFT 5
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+#define RCM_BASE_PTR (RCM)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS { RCM }
+
+/* ----------------------------------------------------------------------------
+ -- RCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register instance definitions */
+/* RCM */
+#define RCM_SRS0 RCM_SRS0_REG(RCM)
+#define RCM_SRS1 RCM_SRS1_REG(RCM)
+#define RCM_RPFC RCM_RPFC_REG(RCM)
+#define RCM_RPFW RCM_RPFW_REG(RCM)
+#define RCM_MR RCM_MR_REG(RCM)
+#define RCM_SSRS0 RCM_SSRS0_REG(RCM)
+#define RCM_SSRS1 RCM_SSRS1_REG(RCM)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type, *RFSYS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register accessors */
+#define RFSYS_REG_REG(base,index) ((base)->REG[index])
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK 0xFFu
+#define RFSYS_REG_LL_SHIFT 0
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK 0xFF00u
+#define RFSYS_REG_LH_SHIFT 8
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK 0xFF0000u
+#define RFSYS_REG_HL_SHIFT 16
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK 0xFF000000u
+#define RFSYS_REG_HH_SHIFT 24
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS_BASE_PTR (RFSYS)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS { RFSYS }
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register instance definitions */
+/* RFSYS */
+#define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
+#define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
+#define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
+#define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
+#define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
+#define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
+#define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
+#define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
+
+/* RFSYS - Register array accessors */
+#define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type, *RFVBAT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register accessors */
+#define RFVBAT_REG_REG(base,index) ((base)->REG[index])
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK 0xFFu
+#define RFVBAT_REG_LL_SHIFT 0
+#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK 0xFF00u
+#define RFVBAT_REG_LH_SHIFT 8
+#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK 0xFF0000u
+#define RFVBAT_REG_HL_SHIFT 16
+#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK 0xFF000000u
+#define RFVBAT_REG_HH_SHIFT 24
+#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
+#define RFVBAT_BASE_PTR (RFVBAT)
+/** Array initializer of RFVBAT peripheral base addresses */
+#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASE_PTRS { RFVBAT }
+
+/* ----------------------------------------------------------------------------
+ -- RFVBAT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
+ * @{
+ */
+
+
+/* RFVBAT - Register instance definitions */
+/* RFVBAT */
+#define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
+#define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
+#define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
+#define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
+#define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
+#define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
+#define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
+#define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
+
+/* RFVBAT - Register array accessors */
+#define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RNG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
+ * @{
+ */
+
+/** RNG - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
+ __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
+ __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
+ __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
+} RNG_Type, *RNG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RNG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register accessors */
+#define RNG_CR_REG(base) ((base)->CR)
+#define RNG_SR_REG(base) ((base)->SR)
+#define RNG_ER_REG(base) ((base)->ER)
+#define RNG_OR_REG(base) ((base)->OR)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RNG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define RNG_CR_GO_MASK 0x1u
+#define RNG_CR_GO_SHIFT 0
+#define RNG_CR_HA_MASK 0x2u
+#define RNG_CR_HA_SHIFT 1
+#define RNG_CR_INTM_MASK 0x4u
+#define RNG_CR_INTM_SHIFT 2
+#define RNG_CR_CLRI_MASK 0x8u
+#define RNG_CR_CLRI_SHIFT 3
+#define RNG_CR_SLP_MASK 0x10u
+#define RNG_CR_SLP_SHIFT 4
+/* SR Bit Fields */
+#define RNG_SR_SECV_MASK 0x1u
+#define RNG_SR_SECV_SHIFT 0
+#define RNG_SR_LRS_MASK 0x2u
+#define RNG_SR_LRS_SHIFT 1
+#define RNG_SR_ORU_MASK 0x4u
+#define RNG_SR_ORU_SHIFT 2
+#define RNG_SR_ERRI_MASK 0x8u
+#define RNG_SR_ERRI_SHIFT 3
+#define RNG_SR_SLP_MASK 0x10u
+#define RNG_SR_SLP_SHIFT 4
+#define RNG_SR_OREG_LVL_MASK 0xFF00u
+#define RNG_SR_OREG_LVL_SHIFT 8
+#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK 0xFF0000u
+#define RNG_SR_OREG_SIZE_SHIFT 16
+#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
+/* ER Bit Fields */
+#define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
+#define RNG_ER_EXT_ENT_SHIFT 0
+#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
+/* OR Bit Fields */
+#define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
+#define RNG_OR_RANDOUT_SHIFT 0
+#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Masks */
+
+
+/* RNG - Peripheral instance base addresses */
+/** Peripheral RNG base address */
+#define RNG_BASE (0x40029000u)
+/** Peripheral RNG base pointer */
+#define RNG ((RNG_Type *)RNG_BASE)
+#define RNG_BASE_PTR (RNG)
+/** Array initializer of RNG peripheral base addresses */
+#define RNG_BASE_ADDRS { RNG_BASE }
+/** Array initializer of RNG peripheral base pointers */
+#define RNG_BASE_PTRS { RNG }
+/** Interrupt vectors for the RNG peripheral type */
+#define RNG_IRQS { RNG_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- RNG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
+ * @{
+ */
+
+
+/* RNG - Register instance definitions */
+/* RNG */
+#define RNG_CR RNG_CR_REG(RNG)
+#define RNG_SR RNG_SR_REG(RNG)
+#define RNG_ER RNG_ER_REG(RNG)
+#define RNG_OR RNG_OR_REG(RNG)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+ uint8_t RESERVED_0[2016];
+ __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
+ __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type, *RTC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RTC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register accessors */
+#define RTC_TSR_REG(base) ((base)->TSR)
+#define RTC_TPR_REG(base) ((base)->TPR)
+#define RTC_TAR_REG(base) ((base)->TAR)
+#define RTC_TCR_REG(base) ((base)->TCR)
+#define RTC_CR_REG(base) ((base)->CR)
+#define RTC_SR_REG(base) ((base)->SR)
+#define RTC_LR_REG(base) ((base)->LR)
+#define RTC_IER_REG(base) ((base)->IER)
+#define RTC_WAR_REG(base) ((base)->WAR)
+#define RTC_RAR_REG(base) ((base)->RAR)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_WPS_MASK 0x10u
+#define RTC_CR_WPS_SHIFT 4
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+#define RTC_IER_WPON_MASK 0x80u
+#define RTC_IER_WPON_SHIFT 7
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK 0x1u
+#define RTC_WAR_TSRW_SHIFT 0
+#define RTC_WAR_TPRW_MASK 0x2u
+#define RTC_WAR_TPRW_SHIFT 1
+#define RTC_WAR_TARW_MASK 0x4u
+#define RTC_WAR_TARW_SHIFT 2
+#define RTC_WAR_TCRW_MASK 0x8u
+#define RTC_WAR_TCRW_SHIFT 3
+#define RTC_WAR_CRW_MASK 0x10u
+#define RTC_WAR_CRW_SHIFT 4
+#define RTC_WAR_SRW_MASK 0x20u
+#define RTC_WAR_SRW_SHIFT 5
+#define RTC_WAR_LRW_MASK 0x40u
+#define RTC_WAR_LRW_SHIFT 6
+#define RTC_WAR_IERW_MASK 0x80u
+#define RTC_WAR_IERW_SHIFT 7
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK 0x1u
+#define RTC_RAR_TSRR_SHIFT 0
+#define RTC_RAR_TPRR_MASK 0x2u
+#define RTC_RAR_TPRR_SHIFT 1
+#define RTC_RAR_TARR_MASK 0x4u
+#define RTC_RAR_TARR_SHIFT 2
+#define RTC_RAR_TCRR_MASK 0x8u
+#define RTC_RAR_TCRR_SHIFT 3
+#define RTC_RAR_CRR_MASK 0x10u
+#define RTC_RAR_CRR_SHIFT 4
+#define RTC_RAR_SRR_MASK 0x20u
+#define RTC_RAR_SRR_SHIFT 5
+#define RTC_RAR_LRR_MASK 0x40u
+#define RTC_RAR_LRR_SHIFT 6
+#define RTC_RAR_IERR_MASK 0x80u
+#define RTC_RAR_IERR_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+#define RTC_BASE_PTR (RTC)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS { RTC_IRQn }
+#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- RTC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register instance definitions */
+/* RTC */
+#define RTC_TSR RTC_TSR_REG(RTC)
+#define RTC_TPR RTC_TPR_REG(RTC)
+#define RTC_TAR RTC_TAR_REG(RTC)
+#define RTC_TCR RTC_TCR_REG(RTC)
+#define RTC_CR RTC_CR_REG(RTC)
+#define RTC_SR RTC_SR_REG(RTC)
+#define RTC_LR RTC_LR_REG(RTC)
+#define RTC_IER RTC_IER_REG(RTC)
+#define RTC_WAR RTC_WAR_REG(RTC)
+#define RTC_RAR RTC_RAR_REG(RTC)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
+ uint8_t RESERVED_3[4];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type, *SIM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SIM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register accessors */
+#define SIM_SOPT1_REG(base) ((base)->SOPT1)
+#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base) ((base)->SOPT2)
+#define SIM_SOPT4_REG(base) ((base)->SOPT4)
+#define SIM_SOPT5_REG(base) ((base)->SOPT5)
+#define SIM_SOPT7_REG(base) ((base)->SOPT7)
+#define SIM_SOPT8_REG(base) ((base)->SOPT8)
+#define SIM_SDID_REG(base) ((base)->SDID)
+#define SIM_SCGC4_REG(base) ((base)->SCGC4)
+#define SIM_SCGC5_REG(base) ((base)->SCGC5)
+#define SIM_SCGC6_REG(base) ((base)->SCGC6)
+#define SIM_SCGC7_REG(base) ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
+#define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
+#define SIM_FCFG1_REG(base) ((base)->FCFG1)
+#define SIM_FCFG2_REG(base) ((base)->FCFG2)
+#define SIM_UIDH_REG(base) ((base)->UIDH)
+#define SIM_UIDMH_REG(base) ((base)->UIDMH)
+#define SIM_UIDML_REG(base) ((base)->UIDML)
+#define SIM_UIDL_REG(base) ((base)->UIDL)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK 0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT 12
+#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KOUT_MASK 0x30000u
+#define SIM_SOPT1_OSC32KOUT_SHIFT 16
+#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK 0x300u
+#define SIM_SOPT2_FBSL_SHIFT 8
+#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT 12
+#define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
+#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+#define SIM_SOPT2_LPUARTSRC_MASK 0xC000000u
+#define SIM_SOPT2_LPUARTSRC_SHIFT 26
+#define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUARTSRC_SHIFT))&SIM_SOPT2_LPUARTSRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK 0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT 0
+#define SIM_SOPT4_FTM0FLT1_MASK 0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT 1
+#define SIM_SOPT4_FTM1FLT0_MASK 0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT 4
+#define SIM_SOPT4_FTM2FLT0_MASK 0x100u
+#define SIM_SOPT4_FTM2FLT0_SHIFT 8
+#define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
+#define SIM_SOPT4_FTM3FLT0_SHIFT 12
+#define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
+#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH1SRC_MASK 0x400000u
+#define SIM_SOPT4_FTM2CH1SRC_SHIFT 22
+#define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
+#define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
+#define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
+#define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
+#define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
+#define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
+#define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
+#define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
+#define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK 0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT 4
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT 6
+#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+#define SIM_SOPT5_LPUART0RXSRC_MASK 0xC0000u
+#define SIM_SOPT5_LPUART0RXSRC_SHIFT 18
+#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0RXSRC_SHIFT))&SIM_SOPT5_LPUART0RXSRC_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+#define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
+#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
+/* SOPT8 Bit Fields */
+#define SIM_SOPT8_FTM0SYNCBIT_MASK 0x1u
+#define SIM_SOPT8_FTM0SYNCBIT_SHIFT 0
+#define SIM_SOPT8_FTM1SYNCBIT_MASK 0x2u
+#define SIM_SOPT8_FTM1SYNCBIT_SHIFT 1
+#define SIM_SOPT8_FTM2SYNCBIT_MASK 0x4u
+#define SIM_SOPT8_FTM2SYNCBIT_SHIFT 2
+#define SIM_SOPT8_FTM3SYNCBIT_MASK 0x8u
+#define SIM_SOPT8_FTM3SYNCBIT_SHIFT 3
+#define SIM_SOPT8_FTM0OCH0SRC_MASK 0x10000u
+#define SIM_SOPT8_FTM0OCH0SRC_SHIFT 16
+#define SIM_SOPT8_FTM0OCH1SRC_MASK 0x20000u
+#define SIM_SOPT8_FTM0OCH1SRC_SHIFT 17
+#define SIM_SOPT8_FTM0OCH2SRC_MASK 0x40000u
+#define SIM_SOPT8_FTM0OCH2SRC_SHIFT 18
+#define SIM_SOPT8_FTM0OCH3SRC_MASK 0x80000u
+#define SIM_SOPT8_FTM0OCH3SRC_SHIFT 19
+#define SIM_SOPT8_FTM0OCH4SRC_MASK 0x100000u
+#define SIM_SOPT8_FTM0OCH4SRC_SHIFT 20
+#define SIM_SOPT8_FTM0OCH5SRC_MASK 0x200000u
+#define SIM_SOPT8_FTM0OCH5SRC_SHIFT 21
+#define SIM_SOPT8_FTM0OCH6SRC_MASK 0x400000u
+#define SIM_SOPT8_FTM0OCH6SRC_SHIFT 22
+#define SIM_SOPT8_FTM0OCH7SRC_MASK 0x800000u
+#define SIM_SOPT8_FTM0OCH7SRC_SHIFT 23
+#define SIM_SOPT8_FTM3OCH0SRC_MASK 0x1000000u
+#define SIM_SOPT8_FTM3OCH0SRC_SHIFT 24
+#define SIM_SOPT8_FTM3OCH1SRC_MASK 0x2000000u
+#define SIM_SOPT8_FTM3OCH1SRC_SHIFT 25
+#define SIM_SOPT8_FTM3OCH2SRC_MASK 0x4000000u
+#define SIM_SOPT8_FTM3OCH2SRC_SHIFT 26
+#define SIM_SOPT8_FTM3OCH3SRC_MASK 0x8000000u
+#define SIM_SOPT8_FTM3OCH3SRC_SHIFT 27
+#define SIM_SOPT8_FTM3OCH4SRC_MASK 0x10000000u
+#define SIM_SOPT8_FTM3OCH4SRC_SHIFT 28
+#define SIM_SOPT8_FTM3OCH5SRC_MASK 0x20000000u
+#define SIM_SOPT8_FTM3OCH5SRC_SHIFT 29
+#define SIM_SOPT8_FTM3OCH6SRC_MASK 0x40000000u
+#define SIM_SOPT8_FTM3OCH6SRC_SHIFT 30
+#define SIM_SOPT8_FTM3OCH7SRC_MASK 0x80000000u
+#define SIM_SOPT8_FTM3OCH7SRC_SHIFT 31
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK 0x70u
+#define SIM_SDID_FAMID_SHIFT 4
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK 0xF80u
+#define SIM_SDID_DIEID_SHIFT 7
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK 0xF00000u
+#define SIM_SDID_SERIESID_SHIFT 20
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK 0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT 24
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK 0xF0000000u
+#define SIM_SDID_FAMILYID_SHIFT 28
+#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK 0x2u
+#define SIM_SCGC4_EWM_SHIFT 1
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_I2C1_MASK 0x80u
+#define SIM_SCGC4_I2C1_SHIFT 7
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_UART1_MASK 0x800u
+#define SIM_SCGC4_UART1_SHIFT 11
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_USBOTG_MASK 0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT 18
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_VREF_MASK 0x100000u
+#define SIM_SCGC4_VREF_SHIFT 20
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK 0x1u
+#define SIM_SCGC5_LPTMR_SHIFT 0
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK 0x1u
+#define SIM_SCGC6_FTF_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_FTM3_MASK 0x40u
+#define SIM_SCGC6_FTM3_SHIFT 6
+#define SIM_SCGC6_ADC1_MASK 0x80u
+#define SIM_SCGC6_ADC1_SHIFT 7
+#define SIM_SCGC6_DAC1_MASK 0x100u
+#define SIM_SCGC6_DAC1_SHIFT 8
+#define SIM_SCGC6_RNGA_MASK 0x200u
+#define SIM_SCGC6_RNGA_SHIFT 9
+#define SIM_SCGC6_LPUART0_MASK 0x400u
+#define SIM_SCGC6_LPUART0_SHIFT 10
+#define SIM_SCGC6_SPI0_MASK 0x1000u
+#define SIM_SCGC6_SPI0_SHIFT 12
+#define SIM_SCGC6_SPI1_MASK 0x2000u
+#define SIM_SCGC6_SPI1_SHIFT 13
+#define SIM_SCGC6_I2S_MASK 0x8000u
+#define SIM_SCGC6_I2S_SHIFT 15
+#define SIM_SCGC6_CRC_MASK 0x40000u
+#define SIM_SCGC6_CRC_SHIFT 18
+#define SIM_SCGC6_PDB_MASK 0x400000u
+#define SIM_SCGC6_PDB_SHIFT 22
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_FTM0_MASK 0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT 24
+#define SIM_SCGC6_FTM1_MASK 0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT 25
+#define SIM_SCGC6_FTM2_MASK 0x4000000u
+#define SIM_SCGC6_FTM2_SHIFT 26
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+#define SIM_SCGC6_DAC0_MASK 0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT 31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_FLEXBUS_MASK 0x1u
+#define SIM_SCGC7_FLEXBUS_SHIFT 0
+#define SIM_SCGC7_DMA_MASK 0x2u
+#define SIM_SCGC7_DMA_SHIFT 1
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
+#define SIM_CLKDIV1_OUTDIV3_SHIFT 20
+#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
+#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT 0
+#define SIM_CLKDIV2_USBDIV_MASK 0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT 1
+#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT 16
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT 24
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT 0
+#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+#define SIM_BASE_PTR (SIM)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS { SIM }
+
+/* ----------------------------------------------------------------------------
+ -- SIM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register instance definitions */
+/* SIM */
+#define SIM_SOPT1 SIM_SOPT1_REG(SIM)
+#define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
+#define SIM_SOPT2 SIM_SOPT2_REG(SIM)
+#define SIM_SOPT4 SIM_SOPT4_REG(SIM)
+#define SIM_SOPT5 SIM_SOPT5_REG(SIM)
+#define SIM_SOPT7 SIM_SOPT7_REG(SIM)
+#define SIM_SOPT8 SIM_SOPT8_REG(SIM)
+#define SIM_SDID SIM_SDID_REG(SIM)
+#define SIM_SCGC4 SIM_SCGC4_REG(SIM)
+#define SIM_SCGC5 SIM_SCGC5_REG(SIM)
+#define SIM_SCGC6 SIM_SCGC6_REG(SIM)
+#define SIM_SCGC7 SIM_SCGC7_REG(SIM)
+#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
+#define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
+#define SIM_FCFG1 SIM_FCFG1_REG(SIM)
+#define SIM_FCFG2 SIM_FCFG2_REG(SIM)
+#define SIM_UIDH SIM_UIDH_REG(SIM)
+#define SIM_UIDMH SIM_UIDMH_REG(SIM)
+#define SIM_UIDML SIM_UIDML_REG(SIM)
+#define SIM_UIDL SIM_UIDL_REG(SIM)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type, *SMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register accessors */
+#define SMC_PMPROT_REG(base) ((base)->PMPROT)
+#define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
+#define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
+#define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+#define SMC_PMPROT_AHSRUN_MASK 0x80u
+#define SMC_PMPROT_AHSRUN_SHIFT 7
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+/* STOPCTRL Bit Fields */
+#define SMC_STOPCTRL_LLSM_MASK 0x7u
+#define SMC_STOPCTRL_LLSM_SHIFT 0
+#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_LLSM_SHIFT))&SMC_STOPCTRL_LLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK 0x20u
+#define SMC_STOPCTRL_PORPO_SHIFT 5
+#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
+#define SMC_STOPCTRL_PSTOPO_SHIFT 6
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0xFFu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+#define SMC_BASE_PTR (SMC)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS { SMC }
+
+/* ----------------------------------------------------------------------------
+ -- SMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register instance definitions */
+/* SMC */
+#define SMC_PMPROT SMC_PMPROT_REG(SMC)
+#define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
+#define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
+#define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
+ union { /* offset: 0xC */
+ __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+ __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+ };
+ uint8_t RESERVED_1[24];
+ __IO uint32_t SR; /**< Status Register, offset: 0x2C */
+ __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+ union { /* offset: 0x34 */
+ __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+ __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+ };
+ __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
+ __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
+ __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
+ __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
+ __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
+ uint8_t RESERVED_2[48];
+ __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
+ __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
+ __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
+ __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_Type, *SPI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SPI - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register accessors */
+#define SPI_MCR_REG(base) ((base)->MCR)
+#define SPI_TCR_REG(base) ((base)->TCR)
+#define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
+#define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
+#define SPI_SR_REG(base) ((base)->SR)
+#define SPI_RSER_REG(base) ((base)->RSER)
+#define SPI_PUSHR_REG(base) ((base)->PUSHR)
+#define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
+#define SPI_POPR_REG(base) ((base)->POPR)
+#define SPI_TXFR0_REG(base) ((base)->TXFR0)
+#define SPI_TXFR1_REG(base) ((base)->TXFR1)
+#define SPI_TXFR2_REG(base) ((base)->TXFR2)
+#define SPI_TXFR3_REG(base) ((base)->TXFR3)
+#define SPI_RXFR0_REG(base) ((base)->RXFR0)
+#define SPI_RXFR1_REG(base) ((base)->RXFR1)
+#define SPI_RXFR2_REG(base) ((base)->RXFR2)
+#define SPI_RXFR3_REG(base) ((base)->RXFR3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK 0x1u
+#define SPI_MCR_HALT_SHIFT 0
+#define SPI_MCR_SMPL_PT_MASK 0x300u
+#define SPI_MCR_SMPL_PT_SHIFT 8
+#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK 0x400u
+#define SPI_MCR_CLR_RXF_SHIFT 10
+#define SPI_MCR_CLR_TXF_MASK 0x800u
+#define SPI_MCR_CLR_TXF_SHIFT 11
+#define SPI_MCR_DIS_RXF_MASK 0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT 12
+#define SPI_MCR_DIS_TXF_MASK 0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT 13
+#define SPI_MCR_MDIS_MASK 0x4000u
+#define SPI_MCR_MDIS_SHIFT 14
+#define SPI_MCR_DOZE_MASK 0x8000u
+#define SPI_MCR_DOZE_SHIFT 15
+#define SPI_MCR_PCSIS_MASK 0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT 16
+#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK 0x1000000u
+#define SPI_MCR_ROOE_SHIFT 24
+#define SPI_MCR_PCSSE_MASK 0x2000000u
+#define SPI_MCR_PCSSE_SHIFT 25
+#define SPI_MCR_MTFE_MASK 0x4000000u
+#define SPI_MCR_MTFE_SHIFT 26
+#define SPI_MCR_FRZ_MASK 0x8000000u
+#define SPI_MCR_FRZ_SHIFT 27
+#define SPI_MCR_DCONF_MASK 0x30000000u
+#define SPI_MCR_DCONF_SHIFT 28
+#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK 0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT 30
+#define SPI_MCR_MSTR_MASK 0x80000000u
+#define SPI_MCR_MSTR_SHIFT 31
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT 16
+#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK 0xFu
+#define SPI_CTAR_BR_SHIFT 0
+#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK 0xF0u
+#define SPI_CTAR_DT_SHIFT 4
+#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK 0xF00u
+#define SPI_CTAR_ASC_SHIFT 8
+#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK 0xF000u
+#define SPI_CTAR_CSSCK_SHIFT 12
+#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK 0x30000u
+#define SPI_CTAR_PBR_SHIFT 16
+#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK 0xC0000u
+#define SPI_CTAR_PDT_SHIFT 18
+#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK 0x300000u
+#define SPI_CTAR_PASC_SHIFT 20
+#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK 0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT 22
+#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK 0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT 24
+#define SPI_CTAR_CPHA_MASK 0x2000000u
+#define SPI_CTAR_CPHA_SHIFT 25
+#define SPI_CTAR_CPOL_MASK 0x4000000u
+#define SPI_CTAR_CPOL_SHIFT 26
+#define SPI_CTAR_FMSZ_MASK 0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT 27
+#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK 0x80000000u
+#define SPI_CTAR_DBR_SHIFT 31
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT 25
+#define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT 26
+#define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
+#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK 0xFu
+#define SPI_SR_POPNXTPTR_SHIFT 0
+#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK 0xF0u
+#define SPI_SR_RXCTR_SHIFT 4
+#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK 0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT 8
+#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK 0xF000u
+#define SPI_SR_TXCTR_SHIFT 12
+#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK 0x20000u
+#define SPI_SR_RFDF_SHIFT 17
+#define SPI_SR_RFOF_MASK 0x80000u
+#define SPI_SR_RFOF_SHIFT 19
+#define SPI_SR_TFFF_MASK 0x2000000u
+#define SPI_SR_TFFF_SHIFT 25
+#define SPI_SR_TFUF_MASK 0x8000000u
+#define SPI_SR_TFUF_SHIFT 27
+#define SPI_SR_EOQF_MASK 0x10000000u
+#define SPI_SR_EOQF_SHIFT 28
+#define SPI_SR_TXRXS_MASK 0x40000000u
+#define SPI_SR_TXRXS_SHIFT 30
+#define SPI_SR_TCF_MASK 0x80000000u
+#define SPI_SR_TCF_SHIFT 31
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK 0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT 16
+#define SPI_RSER_RFDF_RE_MASK 0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT 17
+#define SPI_RSER_RFOF_RE_MASK 0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT 19
+#define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT 24
+#define SPI_RSER_TFFF_RE_MASK 0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT 25
+#define SPI_RSER_TFUF_RE_MASK 0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT 27
+#define SPI_RSER_EOQF_RE_MASK 0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT 28
+#define SPI_RSER_TCF_RE_MASK 0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT 31
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK 0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT 0
+#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK 0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT 16
+#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK 0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT 26
+#define SPI_PUSHR_EOQ_MASK 0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT 27
+#define SPI_PUSHR_CTAS_MASK 0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT 28
+#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK 0x80000000u
+#define SPI_PUSHR_CONT_SHIFT 31
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
+#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT 0
+#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT 0
+#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT 0
+#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT 0
+#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK 0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT 0
+#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
+#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT 0
+#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT 0
+#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT 0
+#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT 0
+#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+#define SPI0_BASE_PTR (SPI0)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+#define SPI1_BASE_PTR (SPI1)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS { SPI0, SPI1 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- SPI - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register instance definitions */
+/* SPI0 */
+#define SPI0_MCR SPI_MCR_REG(SPI0)
+#define SPI0_TCR SPI_TCR_REG(SPI0)
+#define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
+#define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
+#define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
+#define SPI0_SR SPI_SR_REG(SPI0)
+#define SPI0_RSER SPI_RSER_REG(SPI0)
+#define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
+#define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
+#define SPI0_POPR SPI_POPR_REG(SPI0)
+#define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
+#define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
+#define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
+#define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
+#define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
+#define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
+#define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
+#define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
+/* SPI1 */
+#define SPI1_MCR SPI_MCR_REG(SPI1)
+#define SPI1_TCR SPI_TCR_REG(SPI1)
+#define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
+#define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
+#define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
+#define SPI1_SR SPI_SR_REG(SPI1)
+#define SPI1_RSER SPI_RSER_REG(SPI1)
+#define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
+#define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
+#define SPI1_POPR SPI_POPR_REG(SPI1)
+#define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
+#define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
+#define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
+#define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
+#define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
+#define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
+#define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
+#define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
+
+/* SPI - Register array accessors */
+#define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
+#define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
+#define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
+#define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+ __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
+ __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
+ __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
+ __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
+ __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
+ __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
+ __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
+ __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
+ __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
+ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+ __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
+ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
+ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
+ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
+ uint8_t RESERVED_2[26];
+ __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
+ __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
+ union { /* offset: 0x3C */
+ struct { /* offset: 0x3C */
+ __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+ __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+ } TYPE0;
+ struct { /* offset: 0x3C */
+ __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+ __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+ } TYPE1;
+ };
+ __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
+ __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
+} UART_Type, *UART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- UART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register accessors */
+#define UART_BDH_REG(base) ((base)->BDH)
+#define UART_BDL_REG(base) ((base)->BDL)
+#define UART_C1_REG(base) ((base)->C1)
+#define UART_C2_REG(base) ((base)->C2)
+#define UART_S1_REG(base) ((base)->S1)
+#define UART_S2_REG(base) ((base)->S2)
+#define UART_C3_REG(base) ((base)->C3)
+#define UART_D_REG(base) ((base)->D)
+#define UART_MA1_REG(base) ((base)->MA1)
+#define UART_MA2_REG(base) ((base)->MA2)
+#define UART_C4_REG(base) ((base)->C4)
+#define UART_C5_REG(base) ((base)->C5)
+#define UART_ED_REG(base) ((base)->ED)
+#define UART_MODEM_REG(base) ((base)->MODEM)
+#define UART_IR_REG(base) ((base)->IR)
+#define UART_PFIFO_REG(base) ((base)->PFIFO)
+#define UART_CFIFO_REG(base) ((base)->CFIFO)
+#define UART_SFIFO_REG(base) ((base)->SFIFO)
+#define UART_TWFIFO_REG(base) ((base)->TWFIFO)
+#define UART_TCFIFO_REG(base) ((base)->TCFIFO)
+#define UART_RWFIFO_REG(base) ((base)->RWFIFO)
+#define UART_RCFIFO_REG(base) ((base)->RCFIFO)
+#define UART_C7816_REG(base) ((base)->C7816)
+#define UART_IE7816_REG(base) ((base)->IE7816)
+#define UART_IS7816_REG(base) ((base)->IS7816)
+#define UART_WP7816_REG(base) ((base)->WP7816)
+#define UART_WN7816_REG(base) ((base)->WN7816)
+#define UART_WF7816_REG(base) ((base)->WF7816)
+#define UART_ET7816_REG(base) ((base)->ET7816)
+#define UART_TL7816_REG(base) ((base)->TL7816)
+#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
+#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
+#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
+#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
+#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
+#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
+#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
+#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+#define UART_BDH_LBKDIE_MASK 0x80u
+#define UART_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_UARTSWAI_MASK 0x40u
+#define UART_C1_UARTSWAI_SHIFT 6
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_LBKDE_MASK 0x2u
+#define UART_S2_LBKDE_SHIFT 1
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_MSBF_MASK 0x20u
+#define UART_S2_MSBF_SHIFT 5
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+#define UART_S2_LBKDIF_MASK 0x80u
+#define UART_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_RT_MASK 0xFFu
+#define UART_D_RT_SHIFT 0
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK 0xFFu
+#define UART_MA1_MA_SHIFT 0
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK 0xFFu
+#define UART_MA2_MA_SHIFT 0
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK 0x1Fu
+#define UART_C4_BRFA_SHIFT 0
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK 0x20u
+#define UART_C4_M10_SHIFT 5
+#define UART_C4_MAEN2_MASK 0x40u
+#define UART_C4_MAEN2_SHIFT 6
+#define UART_C4_MAEN1_MASK 0x80u
+#define UART_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UART_C5_RDMAS_MASK 0x20u
+#define UART_C5_RDMAS_SHIFT 5
+#define UART_C5_TDMAS_MASK 0x80u
+#define UART_C5_TDMAS_SHIFT 7
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK 0x40u
+#define UART_ED_PARITYE_SHIFT 6
+#define UART_ED_NOISY_MASK 0x80u
+#define UART_ED_NOISY_SHIFT 7
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK 0x1u
+#define UART_MODEM_TXCTSE_SHIFT 0
+#define UART_MODEM_TXRTSE_MASK 0x2u
+#define UART_MODEM_TXRTSE_SHIFT 1
+#define UART_MODEM_TXRTSPOL_MASK 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT 2
+#define UART_MODEM_RXRTSE_MASK 0x8u
+#define UART_MODEM_RXRTSE_SHIFT 3
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK 0x3u
+#define UART_IR_TNP_SHIFT 0
+#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK 0x4u
+#define UART_IR_IREN_SHIFT 2
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT 0
+#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK 0x8u
+#define UART_PFIFO_RXFE_SHIFT 3
+#define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT 4
+#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK 0x80u
+#define UART_PFIFO_TXFE_SHIFT 7
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK 0x1u
+#define UART_CFIFO_RXUFE_SHIFT 0
+#define UART_CFIFO_TXOFE_MASK 0x2u
+#define UART_CFIFO_TXOFE_SHIFT 1
+#define UART_CFIFO_RXOFE_MASK 0x4u
+#define UART_CFIFO_RXOFE_SHIFT 2
+#define UART_CFIFO_RXFLUSH_MASK 0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT 6
+#define UART_CFIFO_TXFLUSH_MASK 0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT 7
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK 0x1u
+#define UART_SFIFO_RXUF_SHIFT 0
+#define UART_SFIFO_TXOF_MASK 0x2u
+#define UART_SFIFO_TXOF_SHIFT 1
+#define UART_SFIFO_RXOF_MASK 0x4u
+#define UART_SFIFO_RXOF_SHIFT 2
+#define UART_SFIFO_RXEMPT_MASK 0x40u
+#define UART_SFIFO_RXEMPT_SHIFT 6
+#define UART_SFIFO_TXEMPT_MASK 0x80u
+#define UART_SFIFO_TXEMPT_SHIFT 7
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT 0
+#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT 0
+#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT 0
+#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT 0
+#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK 0x1u
+#define UART_C7816_ISO_7816E_SHIFT 0
+#define UART_C7816_TTYPE_MASK 0x2u
+#define UART_C7816_TTYPE_SHIFT 1
+#define UART_C7816_INIT_MASK 0x4u
+#define UART_C7816_INIT_SHIFT 2
+#define UART_C7816_ANACK_MASK 0x8u
+#define UART_C7816_ANACK_SHIFT 3
+#define UART_C7816_ONACK_MASK 0x10u
+#define UART_C7816_ONACK_SHIFT 4
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK 0x1u
+#define UART_IE7816_RXTE_SHIFT 0
+#define UART_IE7816_TXTE_MASK 0x2u
+#define UART_IE7816_TXTE_SHIFT 1
+#define UART_IE7816_GTVE_MASK 0x4u
+#define UART_IE7816_GTVE_SHIFT 2
+#define UART_IE7816_ADTE_MASK 0x8u
+#define UART_IE7816_ADTE_SHIFT 3
+#define UART_IE7816_INITDE_MASK 0x10u
+#define UART_IE7816_INITDE_SHIFT 4
+#define UART_IE7816_BWTE_MASK 0x20u
+#define UART_IE7816_BWTE_SHIFT 5
+#define UART_IE7816_CWTE_MASK 0x40u
+#define UART_IE7816_CWTE_SHIFT 6
+#define UART_IE7816_WTE_MASK 0x80u
+#define UART_IE7816_WTE_SHIFT 7
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK 0x1u
+#define UART_IS7816_RXT_SHIFT 0
+#define UART_IS7816_TXT_MASK 0x2u
+#define UART_IS7816_TXT_SHIFT 1
+#define UART_IS7816_GTV_MASK 0x4u
+#define UART_IS7816_GTV_SHIFT 2
+#define UART_IS7816_ADT_MASK 0x8u
+#define UART_IS7816_ADT_SHIFT 3
+#define UART_IS7816_INITD_MASK 0x10u
+#define UART_IS7816_INITD_SHIFT 4
+#define UART_IS7816_BWT_MASK 0x20u
+#define UART_IS7816_BWT_SHIFT 5
+#define UART_IS7816_CWT_MASK 0x40u
+#define UART_IS7816_CWT_SHIFT 6
+#define UART_IS7816_WT_MASK 0x80u
+#define UART_IS7816_WT_SHIFT 7
+/* WP7816 Bit Fields */
+#define UART_WP7816_WTX_MASK 0xFFu
+#define UART_WP7816_WTX_SHIFT 0
+#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK 0xFFu
+#define UART_WN7816_GTN_SHIFT 0
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK 0xFFu
+#define UART_WF7816_GTFD_SHIFT 0
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT 0
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT 4
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK 0xFFu
+#define UART_TL7816_TLEN_SHIFT 0
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+/* AP7816A_T0 Bit Fields */
+#define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
+#define UART_AP7816A_T0_ADTI_H_SHIFT 0
+#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
+/* AP7816B_T0 Bit Fields */
+#define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
+#define UART_AP7816B_T0_ADTI_L_SHIFT 0
+#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
+/* WP7816A_T0 Bit Fields */
+#define UART_WP7816A_T0_WI_H_MASK 0xFFu
+#define UART_WP7816A_T0_WI_H_SHIFT 0
+#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
+/* WP7816B_T0 Bit Fields */
+#define UART_WP7816B_T0_WI_L_MASK 0xFFu
+#define UART_WP7816B_T0_WI_L_SHIFT 0
+#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
+/* WP7816A_T1 Bit Fields */
+#define UART_WP7816A_T1_BWI_H_MASK 0xFFu
+#define UART_WP7816A_T1_BWI_H_SHIFT 0
+#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
+/* WP7816B_T1 Bit Fields */
+#define UART_WP7816B_T1_BWI_L_MASK 0xFFu
+#define UART_WP7816B_T1_BWI_L_SHIFT 0
+#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
+/* WGP7816_T1 Bit Fields */
+#define UART_WGP7816_T1_BGI_MASK 0xFu
+#define UART_WGP7816_T1_BGI_SHIFT 0
+#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
+#define UART_WGP7816_T1_CWI1_MASK 0xF0u
+#define UART_WGP7816_T1_CWI1_SHIFT 4
+#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
+/* WP7816C_T1 Bit Fields */
+#define UART_WP7816C_T1_CWI2_MASK 0x1Fu
+#define UART_WP7816C_T1_CWI2_SHIFT 0
+#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART_Type *)UART0_BASE)
+#define UART0_BASE_PTR (UART0)
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+#define UART1_BASE_PTR (UART1)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+#define UART2_BASE_PTR (UART2)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS { UART0, UART1, UART2 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn }
+#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- UART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register instance definitions */
+/* UART0 */
+#define UART0_BDH UART_BDH_REG(UART0)
+#define UART0_BDL UART_BDL_REG(UART0)
+#define UART0_C1 UART_C1_REG(UART0)
+#define UART0_C2 UART_C2_REG(UART0)
+#define UART0_S1 UART_S1_REG(UART0)
+#define UART0_S2 UART_S2_REG(UART0)
+#define UART0_C3 UART_C3_REG(UART0)
+#define UART0_D UART_D_REG(UART0)
+#define UART0_MA1 UART_MA1_REG(UART0)
+#define UART0_MA2 UART_MA2_REG(UART0)
+#define UART0_C4 UART_C4_REG(UART0)
+#define UART0_C5 UART_C5_REG(UART0)
+#define UART0_ED UART_ED_REG(UART0)
+#define UART0_MODEM UART_MODEM_REG(UART0)
+#define UART0_IR UART_IR_REG(UART0)
+#define UART0_PFIFO UART_PFIFO_REG(UART0)
+#define UART0_CFIFO UART_CFIFO_REG(UART0)
+#define UART0_SFIFO UART_SFIFO_REG(UART0)
+#define UART0_TWFIFO UART_TWFIFO_REG(UART0)
+#define UART0_TCFIFO UART_TCFIFO_REG(UART0)
+#define UART0_RWFIFO UART_RWFIFO_REG(UART0)
+#define UART0_RCFIFO UART_RCFIFO_REG(UART0)
+#define UART0_C7816 UART_C7816_REG(UART0)
+#define UART0_IE7816 UART_IE7816_REG(UART0)
+#define UART0_IS7816 UART_IS7816_REG(UART0)
+#define UART0_WP7816 UART_WP7816_REG(UART0)
+#define UART0_WN7816 UART_WN7816_REG(UART0)
+#define UART0_WF7816 UART_WF7816_REG(UART0)
+#define UART0_ET7816 UART_ET7816_REG(UART0)
+#define UART0_TL7816 UART_TL7816_REG(UART0)
+#define UART0_AP7816A_T0 UART_AP7816A_T0_REG(UART0)
+#define UART0_AP7816B_T0 UART_AP7816B_T0_REG(UART0)
+#define UART0_WP7816A_T0 UART_WP7816A_T0_REG(UART0)
+#define UART0_WP7816A_T1 UART_WP7816A_T1_REG(UART0)
+#define UART0_WP7816B_T0 UART_WP7816B_T0_REG(UART0)
+#define UART0_WP7816B_T1 UART_WP7816B_T1_REG(UART0)
+#define UART0_WGP7816_T1 UART_WGP7816_T1_REG(UART0)
+#define UART0_WP7816C_T1 UART_WP7816C_T1_REG(UART0)
+/* UART1 */
+#define UART1_BDH UART_BDH_REG(UART1)
+#define UART1_BDL UART_BDL_REG(UART1)
+#define UART1_C1 UART_C1_REG(UART1)
+#define UART1_C2 UART_C2_REG(UART1)
+#define UART1_S1 UART_S1_REG(UART1)
+#define UART1_S2 UART_S2_REG(UART1)
+#define UART1_C3 UART_C3_REG(UART1)
+#define UART1_D UART_D_REG(UART1)
+#define UART1_MA1 UART_MA1_REG(UART1)
+#define UART1_MA2 UART_MA2_REG(UART1)
+#define UART1_C4 UART_C4_REG(UART1)
+#define UART1_C5 UART_C5_REG(UART1)
+#define UART1_ED UART_ED_REG(UART1)
+#define UART1_MODEM UART_MODEM_REG(UART1)
+#define UART1_IR UART_IR_REG(UART1)
+#define UART1_PFIFO UART_PFIFO_REG(UART1)
+#define UART1_CFIFO UART_CFIFO_REG(UART1)
+#define UART1_SFIFO UART_SFIFO_REG(UART1)
+#define UART1_TWFIFO UART_TWFIFO_REG(UART1)
+#define UART1_TCFIFO UART_TCFIFO_REG(UART1)
+#define UART1_RWFIFO UART_RWFIFO_REG(UART1)
+#define UART1_RCFIFO UART_RCFIFO_REG(UART1)
+/* UART2 */
+#define UART2_BDH UART_BDH_REG(UART2)
+#define UART2_BDL UART_BDL_REG(UART2)
+#define UART2_C1 UART_C1_REG(UART2)
+#define UART2_C2 UART_C2_REG(UART2)
+#define UART2_S1 UART_S1_REG(UART2)
+#define UART2_S2 UART_S2_REG(UART2)
+#define UART2_C3 UART_C3_REG(UART2)
+#define UART2_D UART_D_REG(UART2)
+#define UART2_MA1 UART_MA1_REG(UART2)
+#define UART2_MA2 UART_MA2_REG(UART2)
+#define UART2_C4 UART_C4_REG(UART2)
+#define UART2_C5 UART_C5_REG(UART2)
+#define UART2_ED UART_ED_REG(UART2)
+#define UART2_MODEM UART_MODEM_REG(UART2)
+#define UART2_IR UART_IR_REG(UART2)
+#define UART2_PFIFO UART_PFIFO_REG(UART2)
+#define UART2_CFIFO UART_CFIFO_REG(UART2)
+#define UART2_SFIFO UART_SFIFO_REG(UART2)
+#define UART2_TWFIFO UART_TWFIFO_REG(UART2)
+#define UART2_TCFIFO UART_TCFIFO_REG(UART2)
+#define UART2_RWFIFO UART_RWFIFO_REG(UART2)
+#define UART2_RCFIFO UART_RCFIFO_REG(UART2)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
+ uint8_t RESERVED_25[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+ uint8_t RESERVED_26[43];
+ __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
+ uint8_t RESERVED_27[3];
+ __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
+ uint8_t RESERVED_28[23];
+ __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type, *USB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- USB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register accessors */
+#define USB_PERID_REG(base) ((base)->PERID)
+#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
+#define USB_REV_REG(base) ((base)->REV)
+#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
+#define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
+#define USB_OTGICR_REG(base) ((base)->OTGICR)
+#define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
+#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
+#define USB_ISTAT_REG(base) ((base)->ISTAT)
+#define USB_INTEN_REG(base) ((base)->INTEN)
+#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
+#define USB_ERREN_REG(base) ((base)->ERREN)
+#define USB_STAT_REG(base) ((base)->STAT)
+#define USB_CTL_REG(base) ((base)->CTL)
+#define USB_ADDR_REG(base) ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
+#define USB_TOKEN_REG(base) ((base)->TOKEN)
+#define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
+#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
+#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
+#define USB_CONTROL_REG(base) ((base)->CONTROL)
+#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
+#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
+#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
+#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
+#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
+#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
+#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT 6
+#define USB_OTGISTAT_IDCHG_MASK 0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK 0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT 0
+#define USB_OTGICR_BSESSEN_MASK 0x4u
+#define USB_OTGICR_BSESSEN_SHIFT 2
+#define USB_OTGICR_SESSVLDEN_MASK 0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT 3
+#define USB_OTGICR_LINESTATEEN_MASK 0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT 5
+#define USB_OTGICR_ONEMSECEN_MASK 0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT 6
+#define USB_OTGICR_IDEN_MASK 0x80u
+#define USB_OTGICR_IDEN_SHIFT 7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
+#define USB_OTGSTAT_BSESSEND_MASK 0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT 2
+#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT 3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
+#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
+#define USB_OTGSTAT_ID_MASK 0x80u
+#define USB_OTGSTAT_ID_SHIFT 7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK 0x4u
+#define USB_OTGCTL_OTGEN_SHIFT 2
+#define USB_OTGCTL_DMLOW_MASK 0x10u
+#define USB_OTGCTL_DMLOW_SHIFT 4
+#define USB_OTGCTL_DPLOW_MASK 0x20u
+#define USB_OTGCTL_DPLOW_SHIFT 5
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_ATTACH_MASK 0x40u
+#define USB_ISTAT_ATTACH_SHIFT 6
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_ATTACHEN_MASK 0x40u
+#define USB_INTEN_ATTACHEN_SHIFT 6
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_RESUME_MASK 0x4u
+#define USB_CTL_RESUME_SHIFT 2
+#define USB_CTL_HOSTMODEEN_MASK 0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT 3
+#define USB_CTL_RESET_MASK 0x10u
+#define USB_CTL_RESET_SHIFT 4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK 0x80u
+#define USB_ADDR_LSEN_SHIFT 7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK 0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT 0
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK 0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT 4
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK 0xFFu
+#define USB_SOFTHLD_CNT_SHIFT 0
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+#define USB_ENDPT_RETRYDIS_MASK 0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT 6
+#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT 7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT 0
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/* CLK_RECOVER_CTRL Bit Fields */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
+/* CLK_RECOVER_IRC_EN Bit Fields */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
+#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
+/* CLK_RECOVER_INT_STATUS Bit Fields */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+#define USB0_BASE_PTR (USB0)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS { USB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- USB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register instance definitions */
+/* USB0 */
+#define USB0_PERID USB_PERID_REG(USB0)
+#define USB0_IDCOMP USB_IDCOMP_REG(USB0)
+#define USB0_REV USB_REV_REG(USB0)
+#define USB0_ADDINFO USB_ADDINFO_REG(USB0)
+#define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
+#define USB0_OTGICR USB_OTGICR_REG(USB0)
+#define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
+#define USB0_OTGCTL USB_OTGCTL_REG(USB0)
+#define USB0_ISTAT USB_ISTAT_REG(USB0)
+#define USB0_INTEN USB_INTEN_REG(USB0)
+#define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
+#define USB0_ERREN USB_ERREN_REG(USB0)
+#define USB0_STAT USB_STAT_REG(USB0)
+#define USB0_CTL USB_CTL_REG(USB0)
+#define USB0_ADDR USB_ADDR_REG(USB0)
+#define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
+#define USB0_FRMNUML USB_FRMNUML_REG(USB0)
+#define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
+#define USB0_TOKEN USB_TOKEN_REG(USB0)
+#define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
+#define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
+#define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
+#define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
+#define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
+#define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
+#define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
+#define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
+#define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
+#define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
+#define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
+#define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
+#define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
+#define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
+#define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
+#define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
+#define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
+#define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
+#define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
+#define USB0_USBCTRL USB_USBCTRL_REG(USB0)
+#define USB0_OBSERVE USB_OBSERVE_REG(USB0)
+#define USB0_CONTROL USB_CONTROL_REG(USB0)
+#define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
+#define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
+#define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
+#define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
+
+/* USB - Register array accessors */
+#define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
+ __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type, *VREF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- VREF - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register accessors */
+#define VREF_TRM_REG(base) ((base)->TRM)
+#define VREF_SC_REG(base) ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK 0x3Fu
+#define VREF_TRM_TRIM_SHIFT 0
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK 0x40u
+#define VREF_TRM_CHOPEN_SHIFT 6
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK 0x3u
+#define VREF_SC_MODE_LV_SHIFT 0
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK 0x4u
+#define VREF_SC_VREFST_SHIFT 2
+#define VREF_SC_ICOMPEN_MASK 0x20u
+#define VREF_SC_ICOMPEN_SHIFT 5
+#define VREF_SC_REGEN_MASK 0x40u
+#define VREF_SC_REGEN_SHIFT 6
+#define VREF_SC_VREFEN_MASK 0x80u
+#define VREF_SC_VREFEN_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF ((VREF_Type *)VREF_BASE)
+#define VREF_BASE_PTR (VREF)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS { VREF }
+
+/* ----------------------------------------------------------------------------
+ -- VREF - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register instance definitions */
+/* VREF */
+#define VREF_TRM VREF_TRM_REG(VREF)
+#define VREF_SC VREF_SC_REG(VREF)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+ __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
+ __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
+ __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
+ __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+ __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
+ __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
+ __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
+ __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
+ __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
+ __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
+ __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
+ __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_Type, *WDOG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- WDOG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register accessors */
+#define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
+#define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
+#define WDOG_TOVALH_REG(base) ((base)->TOVALH)
+#define WDOG_TOVALL_REG(base) ((base)->TOVALL)
+#define WDOG_WINH_REG(base) ((base)->WINH)
+#define WDOG_WINL_REG(base) ((base)->WINL)
+#define WDOG_REFRESH_REG(base) ((base)->REFRESH)
+#define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
+#define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
+#define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
+#define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
+#define WDOG_PRESC_REG(base) ((base)->PRESC)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- WDOG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT 0
+#define WDOG_STCTRLH_CLKSRC_MASK 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT 1
+#define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
+#define WDOG_STCTRLH_WINEN_MASK 0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT 3
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
+#define WDOG_STCTRLH_DBGEN_MASK 0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT 5
+#define WDOG_STCTRLH_STOPEN_MASK 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT 6
+#define WDOG_STCTRLH_WAITEN_MASK 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT 7
+#define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT 10
+#define WDOG_STCTRLH_TESTSEL_MASK 0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT 11
+#define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT 12
+#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT 15
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT 0
+#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT 0
+#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK 0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT 0
+#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK 0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT 0
+#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
+#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
+#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
+#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
+#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT 0
+#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT 8
+#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG ((WDOG_Type *)WDOG_BASE)
+#define WDOG_BASE_PTR (WDOG)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS { WDOG_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS { WDOG }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS { Watchdog_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- WDOG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
+ * @{
+ */
+
+
+/* WDOG - Register instance definitions */
+/* WDOG */
+#define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
+#define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
+#define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
+#define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
+#define WDOG_WINH WDOG_WINH_REG(WDOG)
+#define WDOG_WINL WDOG_WINL_REG(WDOG)
+#define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
+#define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
+#define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
+#define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
+#define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
+#define WDOG_PRESC WDOG_PRESC_REG(WDOG)
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
+#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
+#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
+#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
+#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
+#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
+#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
+#define MCM_ISR_REG(base) MCM_ISCR_REG(base)
+#define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
+#define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
+#define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
+#define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
+#define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
+#define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
+#define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
+#define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
+#define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
+#define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
+#define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
+#define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
+#define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
+#define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
+#define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
+#define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
+#define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
+#define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
+#define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
+#define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
+#define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
+#define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
+#define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
+#define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
+#define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated
+#define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated
+#define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#else /* #if !defined(MK22F51212_H_) */
+ /* There is already included the same memory map. Check if it is compatible (has the same major version) */
+ #if (MCU_MEM_MAP_VERSION != 0x0200u)
+ #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
+ #warning There are included two not compatible versions of memory maps. Please check possible differences.
+ #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
+ #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
+#endif /* #if !defined(MK22F51212_H_) */
+
+/* MK22F51212.h, eof. */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F51212.sct b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F51212.sct
new file mode 100644
index 000000000..710144bf3
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/MK22F51212.sct
@@ -0,0 +1,13 @@
+
+LR_IROM1 0x00000000 0x80000 { ; load region size_region (512k)
+ ER_IROM1 0x00000000 0x80000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198
+ ; 0x20000 - 0x198 = 0x1FE68
+ RW_IRAM1 0x1FFF0198 0x1FE68 {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.s
new file mode 100644
index 000000000..5c53006d0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/startup_MK22F12.s
@@ -0,0 +1,679 @@
+;/*****************************************************************************
+; * @file: startup_MK22F12.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
+; * MK22F12
+; * @version: 1.5
+; * @date: 2013-5-16
+; *
+; * Copyright: 1997 - 2013 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20010000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
+ DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
+ DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
+ DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
+ DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
+ DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
+ DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
+ DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
+ DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
+ DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
+ DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
+ DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
+ DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
+ DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
+ DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
+ DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
+ DCD DMA_Error_IRQHandler ; DMA Error Interrupt
+ DCD MCM_IRQHandler ; Normal Interrupt
+ DCD FTFE_IRQHandler ; FTFE Command complete interrupt
+ DCD Read_Collision_IRQHandler ; Read Collision Interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD Watchdog_IRQHandler ; WDOG Interrupt
+ DCD Reserved39_IRQHandler ; Reserved Interrupt 39
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C1 interrupt
+ DCD SPI0_IRQHandler ; SPI0 Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
+ DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
+ DCD UART0_LON_IRQHandler ; UART0 LON interrupt
+ DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
+ DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
+ DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
+ DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
+ DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
+ DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
+ DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
+ DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD CMP1_IRQHandler ; CMP1 interrupt
+ DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
+ DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
+ DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
+ DCD CMT_IRQHandler ; CMT interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
+ DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
+ DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
+ DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
+ DCD PDB0_IRQHandler ; PDB0 Interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD USBDCD_IRQHandler ; USBDCD Interrupt
+ DCD Reserved71_IRQHandler ; Reserved interrupt 71
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD MCG_IRQHandler ; MCG Interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTB_IRQHandler ; Port B interrupt
+ DCD PORTC_IRQHandler ; Port C interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+ DCD PORTE_IRQHandler ; Port E interrupt
+ DCD SWI_IRQHandler ; Software interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
+ DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
+ DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
+ DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
+ DCD CMP2_IRQHandler ; CMP2 interrupt
+ DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
+ DCD DAC1_IRQHandler ; DAC1 interrupt
+ DCD ADC1_IRQHandler ; ADC1 interrupt
+ DCD I2C2_IRQHandler ; I2C2 interrupt
+ DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
+ DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
+ DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
+ DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
+ DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
+ DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
+ DCD SDHC_IRQHandler ; SDHC interrupt
+ DCD DefaultISR ; 98
+ DCD DefaultISR ; 99
+ DCD DefaultISR ; 100
+ DCD DefaultISR ; 101
+ DCD DefaultISR ; 102
+ DCD DefaultISR ; 103
+ DCD DefaultISR ; 104
+ DCD DefaultISR ; 105
+ DCD DefaultISR ; 106
+ DCD DefaultISR ; 107
+ DCD DefaultISR ; 108
+ DCD DefaultISR ; 109
+ DCD DefaultISR ; 110
+ DCD DefaultISR ; 111
+ DCD DefaultISR ; 112
+ DCD DefaultISR ; 113
+ DCD DefaultISR ; 114
+ DCD DefaultISR ; 115
+ DCD DefaultISR ; 116
+ DCD DefaultISR ; 117
+ DCD DefaultISR ; 118
+ DCD DefaultISR ; 119
+ DCD DefaultISR ; 120
+ DCD DefaultISR ; 121
+ DCD DefaultISR ; 122
+ DCD DefaultISR ; 123
+ DCD DefaultISR ; 124
+ DCD DefaultISR ; 125
+ DCD DefaultISR ; 126
+ DCD DefaultISR ; 127
+ DCD DefaultISR ; 128
+ DCD DefaultISR ; 129
+ DCD DefaultISR ; 130
+ DCD DefaultISR ; 131
+ DCD DefaultISR ; 132
+ DCD DefaultISR ; 133
+ DCD DefaultISR ; 134
+ DCD DefaultISR ; 135
+ DCD DefaultISR ; 136
+ DCD DefaultISR ; 137
+ DCD DefaultISR ; 138
+ DCD DefaultISR ; 139
+ DCD DefaultISR ; 140
+ DCD DefaultISR ; 141
+ DCD DefaultISR ; 142
+ DCD DefaultISR ; 143
+ DCD DefaultISR ; 144
+ DCD DefaultISR ; 145
+ DCD DefaultISR ; 146
+ DCD DefaultISR ; 147
+ DCD DefaultISR ; 148
+ DCD DefaultISR ; 149
+ DCD DefaultISR ; 150
+ DCD DefaultISR ; 151
+ DCD DefaultISR ; 152
+ DCD DefaultISR ; 153
+ DCD DefaultISR ; 154
+ DCD DefaultISR ; 155
+ DCD DefaultISR ; 156
+ DCD DefaultISR ; 157
+ DCD DefaultISR ; 158
+ DCD DefaultISR ; 159
+ DCD DefaultISR ; 160
+ DCD DefaultISR ; 161
+ DCD DefaultISR ; 162
+ DCD DefaultISR ; 163
+ DCD DefaultISR ; 164
+ DCD DefaultISR ; 165
+ DCD DefaultISR ; 166
+ DCD DefaultISR ; 167
+ DCD DefaultISR ; 168
+ DCD DefaultISR ; 169
+ DCD DefaultISR ; 170
+ DCD DefaultISR ; 171
+ DCD DefaultISR ; 172
+ DCD DefaultISR ; 173
+ DCD DefaultISR ; 174
+ DCD DefaultISR ; 175
+ DCD DefaultISR ; 176
+ DCD DefaultISR ; 177
+ DCD DefaultISR ; 178
+ DCD DefaultISR ; 179
+ DCD DefaultISR ; 180
+ DCD DefaultISR ; 181
+ DCD DefaultISR ; 182
+ DCD DefaultISR ; 183
+ DCD DefaultISR ; 184
+ DCD DefaultISR ; 185
+ DCD DefaultISR ; 186
+ DCD DefaultISR ; 187
+ DCD DefaultISR ; 188
+ DCD DefaultISR ; 189
+ DCD DefaultISR ; 190
+ DCD DefaultISR ; 191
+ DCD DefaultISR ; 192
+ DCD DefaultISR ; 193
+ DCD DefaultISR ; 194
+ DCD DefaultISR ; 195
+ DCD DefaultISR ; 196
+ DCD DefaultISR ; 197
+ DCD DefaultISR ; 198
+ DCD DefaultISR ; 199
+ DCD DefaultISR ; 200
+ DCD DefaultISR ; 201
+ DCD DefaultISR ; 202
+ DCD DefaultISR ; 203
+ DCD DefaultISR ; 204
+ DCD DefaultISR ; 205
+ DCD DefaultISR ; 206
+ DCD DefaultISR ; 207
+ DCD DefaultISR ; 208
+ DCD DefaultISR ; 209
+ DCD DefaultISR ; 210
+ DCD DefaultISR ; 211
+ DCD DefaultISR ; 212
+ DCD DefaultISR ; 213
+ DCD DefaultISR ; 214
+ DCD DefaultISR ; 215
+ DCD DefaultISR ; 216
+ DCD DefaultISR ; 217
+ DCD DefaultISR ; 218
+ DCD DefaultISR ; 219
+ DCD DefaultISR ; 220
+ DCD DefaultISR ; 221
+ DCD DefaultISR ; 222
+ DCD DefaultISR ; 223
+ DCD DefaultISR ; 224
+ DCD DefaultISR ; 225
+ DCD DefaultISR ; 226
+ DCD DefaultISR ; 227
+ DCD DefaultISR ; 228
+ DCD DefaultISR ; 229
+ DCD DefaultISR ; 230
+ DCD DefaultISR ; 231
+ DCD DefaultISR ; 232
+ DCD DefaultISR ; 233
+ DCD DefaultISR ; 234
+ DCD DefaultISR ; 235
+ DCD DefaultISR ; 236
+ DCD DefaultISR ; 237
+ DCD DefaultISR ; 238
+ DCD DefaultISR ; 239
+ DCD DefaultISR ; 240
+ DCD DefaultISR ; 241
+ DCD DefaultISR ; 242
+ DCD DefaultISR ; 243
+ DCD DefaultISR ; 244
+ DCD DefaultISR ; 245
+ DCD DefaultISR ; 246
+ DCD DefaultISR ; 247
+ DCD DefaultISR ; 248
+ DCD DefaultISR ; 249
+ DCD DefaultISR ; 250
+ DCD DefaultISR ; 251
+ DCD DefaultISR ; 252
+ DCD DefaultISR ; 253
+ DCD DefaultISR ; 254
+ DCD DefaultISR ; 255
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; <h> Data flash protection byte (FDPROT)
+; <i> Each bit protects a 1/8 region of the data flash memory.
+; <i> (Program flash only devices: Reserved)
+; <o.0> FDPROT.0
+; <o.1> FDPROT.1
+; <o.2> FDPROT.2
+; <o.3> FDPROT.3
+; <o.4> FDPROT.4
+; <o.5> FDPROT.5
+; <o.6> FDPROT.6
+; <o.7> FDPROT.7
+nFDPROT EQU 0x00
+FDPROT EQU nFDPROT:EOR:0xFF
+; </h>
+; <h> EEPROM protection byte (FEPROT)
+; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
+; <i> (Program flash only devices: Reserved)
+; <o.0> FEPROT.0
+; <o.1> FEPROT.1
+; <o.2> FEPROT.2
+; <o.3> FEPROT.3
+; <o.4> FEPROT.4
+; <o.5> FEPROT.5
+; <o.6> FEPROT.6
+; <o.7> FEPROT.7
+nFEPROT EQU 0x00
+FEPROT EQU nFEPROT:EOR:0xFF
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT
+; <0=> Low-power boot
+; <1=> normal boot
+; <o.1> EZPORT_DIS
+; <0=> EzPort operation is enabled
+; <1=> EzPort operation is disabled
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+; </h>
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, FEPROT, FDPROT
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT DMA4_IRQHandler [WEAK]
+ EXPORT DMA5_IRQHandler [WEAK]
+ EXPORT DMA6_IRQHandler [WEAK]
+ EXPORT DMA7_IRQHandler [WEAK]
+ EXPORT DMA8_IRQHandler [WEAK]
+ EXPORT DMA9_IRQHandler [WEAK]
+ EXPORT DMA10_IRQHandler [WEAK]
+ EXPORT DMA11_IRQHandler [WEAK]
+ EXPORT DMA12_IRQHandler [WEAK]
+ EXPORT DMA13_IRQHandler [WEAK]
+ EXPORT DMA14_IRQHandler [WEAK]
+ EXPORT DMA15_IRQHandler [WEAK]
+ EXPORT DMA_Error_IRQHandler [WEAK]
+ EXPORT MCM_IRQHandler [WEAK]
+ EXPORT FTFE_IRQHandler [WEAK]
+ EXPORT Read_Collision_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT Watchdog_IRQHandler [WEAK]
+ EXPORT Reserved39_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT I2S0_Tx_IRQHandler [WEAK]
+ EXPORT I2S0_Rx_IRQHandler [WEAK]
+ EXPORT UART0_LON_IRQHandler [WEAK]
+ EXPORT UART0_RX_TX_IRQHandler [WEAK]
+ EXPORT UART0_ERR_IRQHandler [WEAK]
+ EXPORT UART1_RX_TX_IRQHandler [WEAK]
+ EXPORT UART1_ERR_IRQHandler [WEAK]
+ EXPORT UART2_RX_TX_IRQHandler [WEAK]
+ EXPORT UART2_ERR_IRQHandler [WEAK]
+ EXPORT UART3_RX_TX_IRQHandler [WEAK]
+ EXPORT UART3_ERR_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT CMP1_IRQHandler [WEAK]
+ EXPORT FTM0_IRQHandler [WEAK]
+ EXPORT FTM1_IRQHandler [WEAK]
+ EXPORT FTM2_IRQHandler [WEAK]
+ EXPORT CMT_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT0_IRQHandler [WEAK]
+ EXPORT PIT1_IRQHandler [WEAK]
+ EXPORT PIT2_IRQHandler [WEAK]
+ EXPORT PIT3_IRQHandler [WEAK]
+ EXPORT PDB0_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT USBDCD_IRQHandler [WEAK]
+ EXPORT Reserved71_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTB_IRQHandler [WEAK]
+ EXPORT PORTC_IRQHandler [WEAK]
+ EXPORT PORTD_IRQHandler [WEAK]
+ EXPORT PORTE_IRQHandler [WEAK]
+ EXPORT SWI_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT UART4_RX_TX_IRQHandler [WEAK]
+ EXPORT UART4_ERR_IRQHandler [WEAK]
+ EXPORT UART5_RX_TX_IRQHandler [WEAK]
+ EXPORT UART5_ERR_IRQHandler [WEAK]
+ EXPORT CMP2_IRQHandler [WEAK]
+ EXPORT FTM3_IRQHandler [WEAK]
+ EXPORT DAC1_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT I2C2_IRQHandler [WEAK]
+ EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK]
+ EXPORT CAN0_Bus_Off_IRQHandler [WEAK]
+ EXPORT CAN0_Error_IRQHandler [WEAK]
+ EXPORT CAN0_Tx_Warning_IRQHandler [WEAK]
+ EXPORT CAN0_Rx_Warning_IRQHandler [WEAK]
+ EXPORT CAN0_Wake_Up_IRQHandler [WEAK]
+ EXPORT SDHC_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+DMA8_IRQHandler
+DMA9_IRQHandler
+DMA10_IRQHandler
+DMA11_IRQHandler
+DMA12_IRQHandler
+DMA13_IRQHandler
+DMA14_IRQHandler
+DMA15_IRQHandler
+DMA_Error_IRQHandler
+MCM_IRQHandler
+FTFE_IRQHandler
+Read_Collision_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+Watchdog_IRQHandler
+Reserved39_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+I2S0_Tx_IRQHandler
+I2S0_Rx_IRQHandler
+UART0_LON_IRQHandler
+UART0_RX_TX_IRQHandler
+UART0_ERR_IRQHandler
+UART1_RX_TX_IRQHandler
+UART1_ERR_IRQHandler
+UART2_RX_TX_IRQHandler
+UART2_ERR_IRQHandler
+UART3_RX_TX_IRQHandler
+UART3_ERR_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+FTM0_IRQHandler
+FTM1_IRQHandler
+FTM2_IRQHandler
+CMT_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT0_IRQHandler
+PIT1_IRQHandler
+PIT2_IRQHandler
+PIT3_IRQHandler
+PDB0_IRQHandler
+USB0_IRQHandler
+USBDCD_IRQHandler
+Reserved71_IRQHandler
+DAC0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+SWI_IRQHandler
+SPI2_IRQHandler
+UART4_RX_TX_IRQHandler
+UART4_ERR_IRQHandler
+UART5_RX_TX_IRQHandler
+UART5_ERR_IRQHandler
+CMP2_IRQHandler
+FTM3_IRQHandler
+DAC1_IRQHandler
+ADC1_IRQHandler
+I2C2_IRQHandler
+CAN0_ORed_Message_buffer_IRQHandler
+CAN0_Bus_Off_IRQHandler
+CAN0_Error_IRQHandler
+CAN0_Tx_Warning_IRQHandler
+CAN0_Rx_Warning_IRQHandler
+CAN0_Wake_Up_IRQHandler
+SDHC_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..b129b2c2a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld
new file mode 100644
index 000000000..b7b3fe61c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/K22FN512xxx12.ld
@@ -0,0 +1,164 @@
+/*
+ * K64F ARM GCC linker script file
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 0x000080000 - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFF0400, LENGTH = 0x000020000 - 0x00000400
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ *(.text.Reset_Handler)
+ *(.text.System_Init)
+ . = ALIGN(4);
+ } > VECTORS
+
+ .flash_protect :
+ {
+ KEEP(*(.kinetis_flash_config_field))
+ . = ALIGN(4);
+ } > FLASH_PROTECTION
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F12.S b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F12.S
new file mode 100644
index 000000000..2b5675164
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_GCC_ARM/startup_MK22F12.S
@@ -0,0 +1,369 @@
+/* K64F startup ARM GCC
+ * Purpose: startup file for Cortex-M4 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv7-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0xC00
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x400
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vector_table,"a",%progbits
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long MemManage_Handler /* MPU Fault Handler */
+ .long BusFault_Handler /* Bus Fault Handler */
+ .long UsageFault_Handler /* Usage Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long DebugMon_Handler /* Debug Monitor Handler */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External Interrupts */
+ .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/
+ .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/
+ .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/
+ .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/
+ .long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/
+ .long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/
+ .long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/
+ .long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/
+ .long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/
+ .long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/
+ .long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/
+ .long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/
+ .long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/
+ .long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/
+ .long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/
+ .long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/
+ .long DMA_Error_IRQHandler /* DMA Error Interrupt*/
+ .long MCM_IRQHandler /* Normal Interrupt*/
+ .long FTF_IRQHandler /* FTFA Command complete interrupt*/
+ .long Read_Collision_IRQHandler /* Read Collision Interrupt*/
+ .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/
+ .long LLW_IRQHandler /* Low Leakage Wakeup*/
+ .long Watchdog_IRQHandler /* WDOG Interrupt*/
+ .long RNG_IRQHandler /* RNG Interrupt*/
+ .long I2C0_IRQHandler /* I2C0 interrupt*/
+ .long I2C1_IRQHandler /* I2C1 interrupt*/
+ .long SPI0_IRQHandler /* SPI0 Interrupt*/
+ .long SPI1_IRQHandler /* SPI1 Interrupt*/
+ .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/
+ .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/
+ .long LPUART0_IRQHandler /* LPUART0 status/error interrupt*/
+ .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/
+ .long UART0_ERR_IRQHandler /* UART0 Error interrupt*/
+ .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/
+ .long UART1_ERR_IRQHandler /* UART1 Error interrupt*/
+ .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/
+ .long UART2_ERR_IRQHandler /* UART2 Error interrupt*/
+ .long Reserved53_IRQHandler /* Reserved interrupt 53*/
+ .long Reserved54_IRQHandler /* Reserved interrupt 54*/
+ .long ADC0_IRQHandler /* ADC0 interrupt*/
+ .long CMP0_IRQHandler /* CMP0 interrupt*/
+ .long CMP1_IRQHandler /* CMP1 interrupt*/
+ .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/
+ .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/
+ .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/
+ .long Reserved61_IRQHandler /* Reserved interrupt 61*/
+ .long RTC_IRQHandler /* RTC interrupt*/
+ .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/
+ .long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/
+ .long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/
+ .long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/
+ .long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/
+ .long PDB0_IRQHandler /* PDB0 Interrupt*/
+ .long USB0_IRQHandler /* USB0 interrupt*/
+ .long Reserved70_IRQHandler /* Reserved interrupt 70*/
+ .long Reserved71_IRQHandler /* Reserved interrupt 71*/
+ .long DAC0_IRQHandler /* DAC0 interrupt*/
+ .long MCG_IRQHandler /* MCG Interrupt*/
+ .long LPTimer_IRQHandler /* LPTimer interrupt*/
+ .long PORTA_IRQHandler /* Port A interrupt*/
+ .long PORTB_IRQHandler /* Port B interrupt*/
+ .long PORTC_IRQHandler /* Port C interrupt*/
+ .long PORTD_IRQHandler /* Port D interrupt*/
+ .long PORTE_IRQHandler /* Port E interrupt*/
+ .long SWI_IRQHandler /* Software interrupt*/
+ .long Reserved81_IRQHandler /* Reserved interrupt 81*/
+ .long Reserved82_IRQHandler /* Reserved interrupt 82*/
+ .long Reserved83_IRQHandler /* Reserved interrupt 83*/
+ .long Reserved84_IRQHandler /* Reserved interrupt 84*/
+ .long Reserved85_IRQHandler /* Reserved interrupt 85*/
+ .long Reserved86_IRQHandler /* Reserved interrupt 86*/
+ .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/
+ .long DAC1_IRQHandler /* DAC1 interrupt*/
+ .long ADC1_IRQHandler /* ADC1 interrupt*/
+ .long Reserved90_IRQHandler /* Reserved Interrupt 90*/
+ .long Reserved91_IRQHandler /* Reserved Interrupt 91*/
+ .long Reserved92_IRQHandler /* Reserved Interrupt 92*/
+ .long Reserved93_IRQHandler /* Reserved Interrupt 93*/
+ .long Reserved94_IRQHandler /* Reserved Interrupt 94*/
+ .long Reserved95_IRQHandler /* Reserved Interrupt 95*/
+ .long Reserved96_IRQHandler /* Reserved Interrupt 96*/
+ .long Reserved97_IRQHandler /* Reserved Interrupt 97*/
+ .long Reserved98_IRQHandler /* Reserved Interrupt 98*/
+ .long Reserved99_IRQHandler /* Reserved Interrupt 99*/
+ .long Reserved100_IRQHandler /* Reserved Interrupt 100*/
+ .long Reserved101_IRQHandler /* Reserved Interrupt 101*/
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+disable_watchdog:
+ /* unlock */
+ ldr r1, =0x4005200e
+ ldr r0, =0xc520
+ strh r0, [r1]
+ ldr r0, =0xd928
+ strh r0, [r1]
+ /* disable */
+ ldr r1, =0x40052000
+ ldr r0, =0x01d2
+ strh r0, [r1]
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+/* Exception Handlers */
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler MemManage_Handler
+ def_default_handler BusFault_Handler
+ def_default_handler UsageFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler DebugMon_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+/* IRQ Handlers */
+ def_irq_default_handler DMA0_IRQHandler
+ def_irq_default_handler DMA1_IRQHandler
+ def_irq_default_handler DMA2_IRQHandler
+ def_irq_default_handler DMA3_IRQHandler
+ def_irq_default_handler DMA4_IRQHandler
+ def_irq_default_handler DMA5_IRQHandler
+ def_irq_default_handler DMA6_IRQHandler
+ def_irq_default_handler DMA7_IRQHandler
+ def_irq_default_handler DMA8_IRQHandler
+ def_irq_default_handler DMA9_IRQHandler
+ def_irq_default_handler DMA10_IRQHandler
+ def_irq_default_handler DMA11_IRQHandler
+ def_irq_default_handler DMA12_IRQHandler
+ def_irq_default_handler DMA13_IRQHandler
+ def_irq_default_handler DMA14_IRQHandler
+ def_irq_default_handler DMA15_IRQHandler
+ def_irq_default_handler DMA_Error_IRQHandler
+ def_irq_default_handler MCM_IRQHandler
+ def_irq_default_handler FTF_IRQHandler
+ def_irq_default_handler Read_Collision_IRQHandler
+ def_irq_default_handler LVD_LVW_IRQHandler
+ def_irq_default_handler LLW_IRQHandler
+ def_irq_default_handler Watchdog_IRQHandler
+ def_irq_default_handler RNG_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler I2S0_Tx_IRQHandler
+ def_irq_default_handler I2S0_Rx_IRQHandler
+ def_irq_default_handler LPUART0_IRQHandler
+ def_irq_default_handler UART0_RX_TX_IRQHandler
+ def_irq_default_handler UART0_ERR_IRQHandler
+ def_irq_default_handler UART1_RX_TX_IRQHandler
+ def_irq_default_handler UART1_ERR_IRQHandler
+ def_irq_default_handler UART2_RX_TX_IRQHandler
+ def_irq_default_handler UART2_ERR_IRQHandler
+ def_irq_default_handler Reserved53_IRQHandler
+ def_irq_default_handler Reserved54_IRQHandler
+ def_irq_default_handler ADC0_IRQHandler
+ def_irq_default_handler CMP0_IRQHandler
+ def_irq_default_handler CMP1_IRQHandler
+ def_irq_default_handler FTM0_IRQHandler
+ def_irq_default_handler FTM1_IRQHandler
+ def_irq_default_handler FTM2_IRQHandler
+ def_irq_default_handler Reserved61_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler RTC_Seconds_IRQHandler
+ def_irq_default_handler PIT0_IRQHandler
+ def_irq_default_handler PIT1_IRQHandler
+ def_irq_default_handler PIT2_IRQHandler
+ def_irq_default_handler PIT3_IRQHandler
+ def_irq_default_handler PDB0_IRQHandler
+ def_irq_default_handler USB0_IRQHandler
+ def_irq_default_handler Reserved70_IRQHandler
+ def_irq_default_handler Reserved71_IRQHandler
+ def_irq_default_handler DAC0_IRQHandler
+ def_irq_default_handler MCG_IRQHandler
+ def_irq_default_handler LPTimer_IRQHandler
+ def_irq_default_handler PORTA_IRQHandler
+ def_irq_default_handler PORTB_IRQHandler
+ def_irq_default_handler PORTC_IRQHandler
+ def_irq_default_handler PORTD_IRQHandler
+ def_irq_default_handler PORTE_IRQHandler
+ def_irq_default_handler SWI_IRQHandler
+ def_irq_default_handler Reserved81_IRQHandler
+ def_irq_default_handler Reserved82_IRQHandler
+ def_irq_default_handler Reserved83_IRQHandler
+ def_irq_default_handler Reserved84_IRQHandler
+ def_irq_default_handler Reserved85_IRQHandler
+ def_irq_default_handler Reserved86_IRQHandler
+ def_irq_default_handler FTM3_IRQHandler
+ def_irq_default_handler DAC1_IRQHandler
+ def_irq_default_handler ADC1_IRQHandler
+ def_irq_default_handler Reserved90_IRQHandler
+ def_irq_default_handler Reserved91_IRQHandler
+ def_irq_default_handler Reserved92_IRQHandler
+ def_irq_default_handler Reserved93_IRQHandler
+ def_irq_default_handler Reserved94_IRQHandler
+ def_irq_default_handler Reserved95_IRQHandler
+ def_irq_default_handler Reserved96_IRQHandler
+ def_irq_default_handler Reserved97_IRQHandler
+ def_irq_default_handler Reserved98_IRQHandler
+ def_irq_default_handler Reserved99_IRQHandler
+ def_irq_default_handler Reserved100_IRQHandler
+ def_irq_default_handler Reserved101_IRQHandler
+ def_irq_default_handler DefaultISR
+
+/* Flash protection region, placed at 0x400 */
+ .text
+ .thumb
+ .align 2
+ .section .kinetis_flash_config_field,"a",%progbits
+kinetis_flash_config:
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xfffffffe
+
+ .end
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf
new file mode 100644
index 000000000..4955517c8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/MK22F51212.icf
@@ -0,0 +1,43 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0007ffff;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x1fff0000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x1fff03ff;
+define symbol __ICFEDIT_region_RAM_start__ = 0x1fff0400;
+define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x4000;
+define symbol __ICFEDIT_size_heap__ = 0x8000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM2_start__ = 0x20000000;
+define symbol __region_RAM2_end__ = 0x2000ffff;
+
+define symbol __FlashConfig_start__ = 0x00000400;
+define symbol __FlashConfig_end__ = 0x0000040f;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in FlashConfig_region {section FlashConfig};
+
+place in ROM_region { readonly };
+
+place in RAM_region { readwrite, block HEAP, block CSTACK };
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.s
new file mode 100644
index 000000000..90ee34879
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/TOOLCHAIN_IAR/startup_MK22F12.s
@@ -0,0 +1,535 @@
+/**************************************************
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 16 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:ROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA Channel 0 Transfer Complete
+ DCD DMA1_IRQHandler ; DMA Channel 1 Transfer Complete
+ DCD DMA2_IRQHandler ; DMA Channel 2 Transfer Complete
+ DCD DMA3_IRQHandler ; DMA Channel 3 Transfer Complete
+ DCD DMA4_IRQHandler ; DMA Channel 4 Transfer Complete
+ DCD DMA5_IRQHandler ; DMA Channel 5 Transfer Complete
+ DCD DMA6_IRQHandler ; DMA Channel 6 Transfer Complete
+ DCD DMA7_IRQHandler ; DMA Channel 7 Transfer Complete
+ DCD DMA8_IRQHandler ; DMA Channel 8 Transfer Complete
+ DCD DMA9_IRQHandler ; DMA Channel 9 Transfer Complete
+ DCD DMA10_IRQHandler ; DMA Channel 10 Transfer Complete
+ DCD DMA11_IRQHandler ; DMA Channel 11 Transfer Complete
+ DCD DMA12_IRQHandler ; DMA Channel 12 Transfer Complete
+ DCD DMA13_IRQHandler ; DMA Channel 13 Transfer Complete
+ DCD DMA14_IRQHandler ; DMA Channel 14 Transfer Complete
+ DCD DMA15_IRQHandler ; DMA Channel 15 Transfer Complete
+ DCD DMA_Error_IRQHandler ; DMA Error Interrupt
+ DCD MCM_IRQHandler ; Normal Interrupt
+ DCD FTFE_IRQHandler ; FTFE Command complete interrupt
+ DCD Read_Collision_IRQHandler ; Read Collision Interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD Watchdog_IRQHandler ; WDOG Interrupt
+ DCD 0 ; Reserved
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C1 interrupt
+ DCD SPI0_IRQHandler ; SPI0 Interrupt
+ DCD SPI1_IRQHandler ; SPI1 Interrupt
+ DCD I2S0_Tx_IRQHandler ; I2S0 transmit interrupt
+ DCD I2S0_Rx_IRQHandler ; I2S0 receive interrupt
+ DCD UART0_LON_IRQHandler ; UART0 LON interrupt
+ DCD UART0_RX_TX_IRQHandler ; UART0 Receive/Transmit interrupt
+ DCD UART0_ERR_IRQHandler ; UART0 Error interrupt
+ DCD UART1_RX_TX_IRQHandler ; UART1 Receive/Transmit interrupt
+ DCD UART1_ERR_IRQHandler ; UART1 Error interrupt
+ DCD UART2_RX_TX_IRQHandler ; UART2 Receive/Transmit interrupt
+ DCD UART2_ERR_IRQHandler ; UART2 Error interrupt
+ DCD UART3_RX_TX_IRQHandler ; UART3 Receive/Transmit interrupt
+ DCD UART3_ERR_IRQHandler ; UART3 Error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD CMP1_IRQHandler ; CMP1 interrupt
+ DCD FTM0_IRQHandler ; FTM0 fault, overflow and channels interrupt
+ DCD FTM1_IRQHandler ; FTM1 fault, overflow and channels interrupt
+ DCD FTM2_IRQHandler ; FTM2 fault, overflow and channels interrupt
+ DCD CMT_IRQHandler ; CMT interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT0_IRQHandler ; PIT timer channel 0 interrupt
+ DCD PIT1_IRQHandler ; PIT timer channel 1 interrupt
+ DCD PIT2_IRQHandler ; PIT timer channel 2 interrupt
+ DCD PIT3_IRQHandler ; PIT timer channel 3 interrupt
+ DCD PDB0_IRQHandler ; PDB0 Interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD USBDCD_IRQHandler ; USBDCD Interrupt
+ DCD 0 ; Reserved
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD MCG_IRQHandler ; MCG Interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTB_IRQHandler ; Port B interrupt
+ DCD PORTC_IRQHandler ; Port C interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+ DCD PORTE_IRQHandler ; Port E interrupt
+ DCD SWI_IRQHandler ; Software interrupt
+ DCD SPI2_IRQHandler ; SPI2 Interrupt
+ DCD UART4_RX_TX_IRQHandler ; UART4 Receive/Transmit interrupt
+ DCD UART4_ERR_IRQHandler ; UART4 Error interrupt
+ DCD UART5_RX_TX_IRQHandler ; UART5 Receive/Transmit interrupt
+ DCD UART5_ERR_IRQHandler ; UART5 Error interrupt
+ DCD CMP2_IRQHandler ; CMP2 interrupt
+ DCD FTM3_IRQHandler ; FTM3 fault, overflow and channels interrupt
+ DCD DAC1_IRQHandler ; DAC1 interrupt
+ DCD ADC1_IRQHandler ; ADC1 interrupt
+ DCD I2C2_IRQHandler ; I2C2 interrupt
+ DCD CAN0_ORed_Message_buffer_IRQHandler ; CAN0 OR'd message buffers interrupt
+ DCD CAN0_Bus_Off_IRQHandler ; CAN0 bus off interrupt
+ DCD CAN0_Error_IRQHandler ; CAN0 error interrupt
+ DCD CAN0_Tx_Warning_IRQHandler ; CAN0 Tx warning interrupt
+ DCD CAN0_Rx_Warning_IRQHandler ; CAN0 Rx warning interrupt
+ DCD CAN0_Wake_Up_IRQHandler ; CAN0 wake up interrupt
+ DCD SDHC_IRQHandler ; SDHC interrupt
+ DCD Default_Handler ; 98
+ DCD Default_Handler ; 99
+ DCD Default_Handler ; 100
+ DCD Default_Handler ; 101
+ DCD Default_Handler ; 102
+ DCD Default_Handler ; 103
+ DCD Default_Handler ; 104
+ DCD Default_Handler ; 105
+ DCD Default_Handler ; 106
+ DCD Default_Handler ; 107
+ DCD Default_Handler ; 108
+ DCD Default_Handler ; 109
+ DCD Default_Handler ; 110
+ DCD Default_Handler ; 111
+ DCD Default_Handler ; 112
+ DCD Default_Handler ; 113
+ DCD Default_Handler ; 114
+ DCD Default_Handler ; 115
+ DCD Default_Handler ; 116
+ DCD Default_Handler ; 117
+ DCD Default_Handler ; 118
+ DCD Default_Handler ; 119
+ DCD Default_Handler ; 120
+ DCD Default_Handler ; 121
+ DCD Default_Handler ; 122
+ DCD Default_Handler ; 123
+ DCD Default_Handler ; 124
+ DCD Default_Handler ; 125
+ DCD Default_Handler ; 126
+ DCD Default_Handler ; 127
+ DCD Default_Handler ; 128
+ DCD Default_Handler ; 129
+ DCD Default_Handler ; 130
+ DCD Default_Handler ; 131
+ DCD Default_Handler ; 132
+ DCD Default_Handler ; 133
+ DCD Default_Handler ; 134
+ DCD Default_Handler ; 135
+ DCD Default_Handler ; 136
+ DCD Default_Handler ; 137
+ DCD Default_Handler ; 138
+ DCD Default_Handler ; 139
+ DCD Default_Handler ; 140
+ DCD Default_Handler ; 141
+ DCD Default_Handler ; 142
+ DCD Default_Handler ; 143
+ DCD Default_Handler ; 144
+ DCD Default_Handler ; 145
+ DCD Default_Handler ; 146
+ DCD Default_Handler ; 147
+ DCD Default_Handler ; 148
+ DCD Default_Handler ; 149
+ DCD Default_Handler ; 150
+ DCD Default_Handler ; 151
+ DCD Default_Handler ; 152
+ DCD Default_Handler ; 153
+ DCD Default_Handler ; 154
+ DCD Default_Handler ; 155
+ DCD Default_Handler ; 156
+ DCD Default_Handler ; 157
+ DCD Default_Handler ; 158
+ DCD Default_Handler ; 159
+ DCD Default_Handler ; 160
+ DCD Default_Handler ; 161
+ DCD Default_Handler ; 162
+ DCD Default_Handler ; 163
+ DCD Default_Handler ; 164
+ DCD Default_Handler ; 165
+ DCD Default_Handler ; 166
+ DCD Default_Handler ; 167
+ DCD Default_Handler ; 168
+ DCD Default_Handler ; 169
+ DCD Default_Handler ; 170
+ DCD Default_Handler ; 171
+ DCD Default_Handler ; 172
+ DCD Default_Handler ; 173
+ DCD Default_Handler ; 174
+ DCD Default_Handler ; 175
+ DCD Default_Handler ; 176
+ DCD Default_Handler ; 177
+ DCD Default_Handler ; 178
+ DCD Default_Handler ; 179
+ DCD Default_Handler ; 180
+ DCD Default_Handler ; 181
+ DCD Default_Handler ; 182
+ DCD Default_Handler ; 183
+ DCD Default_Handler ; 184
+ DCD Default_Handler ; 185
+ DCD Default_Handler ; 186
+ DCD Default_Handler ; 187
+ DCD Default_Handler ; 188
+ DCD Default_Handler ; 189
+ DCD Default_Handler ; 190
+ DCD Default_Handler ; 191
+ DCD Default_Handler ; 192
+ DCD Default_Handler ; 193
+ DCD Default_Handler ; 194
+ DCD Default_Handler ; 195
+ DCD Default_Handler ; 196
+ DCD Default_Handler ; 197
+ DCD Default_Handler ; 198
+ DCD Default_Handler ; 199
+ DCD Default_Handler ; 200
+ DCD Default_Handler ; 201
+ DCD Default_Handler ; 202
+ DCD Default_Handler ; 203
+ DCD Default_Handler ; 204
+ DCD Default_Handler ; 205
+ DCD Default_Handler ; 206
+ DCD Default_Handler ; 207
+ DCD Default_Handler ; 208
+ DCD Default_Handler ; 209
+ DCD Default_Handler ; 210
+ DCD Default_Handler ; 211
+ DCD Default_Handler ; 212
+ DCD Default_Handler ; 213
+ DCD Default_Handler ; 214
+ DCD Default_Handler ; 215
+ DCD Default_Handler ; 216
+ DCD Default_Handler ; 217
+ DCD Default_Handler ; 218
+ DCD Default_Handler ; 219
+ DCD Default_Handler ; 220
+ DCD Default_Handler ; 221
+ DCD Default_Handler ; 222
+ DCD Default_Handler ; 223
+ DCD Default_Handler ; 224
+ DCD Default_Handler ; 225
+ DCD Default_Handler ; 226
+ DCD Default_Handler ; 227
+ DCD Default_Handler ; 228
+ DCD Default_Handler ; 229
+ DCD Default_Handler ; 230
+ DCD Default_Handler ; 231
+ DCD Default_Handler ; 232
+ DCD Default_Handler ; 233
+ DCD Default_Handler ; 234
+ DCD Default_Handler ; 235
+ DCD Default_Handler ; 236
+ DCD Default_Handler ; 237
+ DCD Default_Handler ; 238
+ DCD Default_Handler ; 239
+ DCD Default_Handler ; 240
+ DCD Default_Handler ; 241
+ DCD Default_Handler ; 242
+ DCD Default_Handler ; 243
+ DCD Default_Handler ; 244
+ DCD Default_Handler ; 245
+ DCD Default_Handler ; 246
+ DCD Default_Handler ; 247
+ DCD Default_Handler ; 248
+ DCD Default_Handler ; 249
+ DCD Default_Handler ; 250
+ DCD Default_Handler ; 251
+ DCD Default_Handler ; 252
+ DCD Default_Handler ; 253
+ DCD Default_Handler ; 254
+ DCD Default_Handler ; 255
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;Flash Configuration
+;;16-byte flash configuration field that stores default protection settings (loaded on reset)
+;;and security information that allows the MCU to restrict acces to the FTFL module.
+
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0^0xFF
+
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1^0xFF
+
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2^0xFF
+
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3^0xFF
+
+nFEPROT EQU 0x00
+FEPROT EQU nFEPROT^0xFF
+
+nFDPROT EQU 0x00
+FDPROT EQU nFDPROT^0xFF
+
+FOPT EQU 0xFF
+
+FSEC EQU 0xFE
+ SECTION FlashConfig:CONST:REORDER:ROOT(2)
+Config:
+ DATA
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, FEPROT, FDPROT
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK MemManage_Handler
+ PUBWEAK BusFault_Handler
+ PUBWEAK UsageFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK DebugMon_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK DMA0_IRQHandler
+ PUBWEAK DMA1_IRQHandler
+ PUBWEAK DMA2_IRQHandler
+ PUBWEAK DMA3_IRQHandler
+ PUBWEAK DMA4_IRQHandler
+ PUBWEAK DMA5_IRQHandler
+ PUBWEAK DMA6_IRQHandler
+ PUBWEAK DMA7_IRQHandler
+ PUBWEAK DMA8_IRQHandler
+ PUBWEAK DMA9_IRQHandler
+ PUBWEAK DMA10_IRQHandler
+ PUBWEAK DMA11_IRQHandler
+ PUBWEAK DMA12_IRQHandler
+ PUBWEAK DMA13_IRQHandler
+ PUBWEAK DMA14_IRQHandler
+ PUBWEAK DMA15_IRQHandler
+ PUBWEAK DMA_Error_IRQHandler
+ PUBWEAK MCM_IRQHandler
+ PUBWEAK FTFE_IRQHandler
+ PUBWEAK Read_Collision_IRQHandler
+ PUBWEAK LVD_LVW_IRQHandler
+ PUBWEAK LLW_IRQHandler
+ PUBWEAK Watchdog_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK I2S0_Tx_IRQHandler
+ PUBWEAK I2S0_Rx_IRQHandler
+ PUBWEAK UART0_LON_IRQHandler
+ PUBWEAK UART0_RX_TX_IRQHandler
+ PUBWEAK UART0_ERR_IRQHandler
+ PUBWEAK UART1_RX_TX_IRQHandler
+ PUBWEAK UART1_ERR_IRQHandler
+ PUBWEAK UART2_RX_TX_IRQHandler
+ PUBWEAK UART2_ERR_IRQHandler
+ PUBWEAK UART3_RX_TX_IRQHandler
+ PUBWEAK UART3_ERR_IRQHandler
+ PUBWEAK ADC0_IRQHandler
+ PUBWEAK CMP0_IRQHandler
+ PUBWEAK CMP1_IRQHandler
+ PUBWEAK FTM0_IRQHandler
+ PUBWEAK FTM1_IRQHandler
+ PUBWEAK FTM2_IRQHandler
+ PUBWEAK CMT_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK RTC_Seconds_IRQHandler
+ PUBWEAK PIT0_IRQHandler
+ PUBWEAK PIT1_IRQHandler
+ PUBWEAK PIT2_IRQHandler
+ PUBWEAK PIT3_IRQHandler
+ PUBWEAK PDB0_IRQHandler
+ PUBWEAK USB0_IRQHandler
+ PUBWEAK USBDCD_IRQHandler
+ PUBWEAK DAC0_IRQHandler
+ PUBWEAK MCG_IRQHandler
+ PUBWEAK LPTimer_IRQHandler
+ PUBWEAK PORTA_IRQHandler
+ PUBWEAK PORTB_IRQHandler
+ PUBWEAK PORTC_IRQHandler
+ PUBWEAK PORTD_IRQHandler
+ PUBWEAK PORTE_IRQHandler
+ PUBWEAK SWI_IRQHandler
+ PUBWEAK SPI2_IRQHandler
+ PUBWEAK UART4_RX_TX_IRQHandler
+ PUBWEAK UART4_ERR_IRQHandler
+ PUBWEAK UART5_RX_TX_IRQHandler
+ PUBWEAK UART5_ERR_IRQHandler
+ PUBWEAK CMP2_IRQHandler
+ PUBWEAK FTM3_IRQHandler
+ PUBWEAK DAC1_IRQHandler
+ PUBWEAK ADC1_IRQHandler
+ PUBWEAK I2C2_IRQHandler
+ PUBWEAK CAN0_ORed_Message_buffer_IRQHandler
+ PUBWEAK CAN0_Bus_Off_IRQHandler
+ PUBWEAK CAN0_Error_IRQHandler
+ PUBWEAK CAN0_Tx_Warning_IRQHandler
+ PUBWEAK CAN0_Rx_Warning_IRQHandler
+ PUBWEAK CAN0_Wake_Up_IRQHandler
+ PUBWEAK SDHC_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler
+HardFault_Handler
+MemManage_Handler
+BusFault_Handler
+UsageFault_Handler
+SVC_Handler
+DebugMon_Handler
+PendSV_Handler
+SysTick_Handler
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+DMA8_IRQHandler
+DMA9_IRQHandler
+DMA10_IRQHandler
+DMA11_IRQHandler
+DMA12_IRQHandler
+DMA13_IRQHandler
+DMA14_IRQHandler
+DMA15_IRQHandler
+DMA_Error_IRQHandler
+MCM_IRQHandler
+FTFE_IRQHandler
+Read_Collision_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+Watchdog_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+I2S0_Tx_IRQHandler
+I2S0_Rx_IRQHandler
+UART0_LON_IRQHandler
+UART0_RX_TX_IRQHandler
+UART0_ERR_IRQHandler
+UART1_RX_TX_IRQHandler
+UART1_ERR_IRQHandler
+UART2_RX_TX_IRQHandler
+UART2_ERR_IRQHandler
+UART3_RX_TX_IRQHandler
+UART3_ERR_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+FTM0_IRQHandler
+FTM1_IRQHandler
+FTM2_IRQHandler
+CMT_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT0_IRQHandler
+PIT1_IRQHandler
+PIT2_IRQHandler
+PIT3_IRQHandler
+PDB0_IRQHandler
+USB0_IRQHandler
+USBDCD_IRQHandler
+DAC0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+SWI_IRQHandler
+SPI2_IRQHandler
+UART4_RX_TX_IRQHandler
+UART4_ERR_IRQHandler
+UART5_RX_TX_IRQHandler
+UART5_ERR_IRQHandler
+CMP2_IRQHandler
+FTM3_IRQHandler
+DAC1_IRQHandler
+ADC1_IRQHandler
+I2C2_IRQHandler
+CAN0_ORed_Message_buffer_IRQHandler
+CAN0_Bus_Off_IRQHandler
+CAN0_Error_IRQHandler
+CAN0_Tx_Warning_IRQHandler
+CAN0_Rx_Warning_IRQHandler
+CAN0_Wake_Up_IRQHandler
+SDHC_IRQHandler
+Default_Handler
+
+ B Default_Handler
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h
new file mode 100644
index 000000000..ff19283b7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MK22F51212.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c
new file mode 100644
index 000000000..fc13c884f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFF0000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h
new file mode 100644
index 000000000..206b64543
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 86) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c
new file mode 100644
index 000000000..bc387c16c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c
@@ -0,0 +1,395 @@
+/*
+** ###################################################################
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
+** Version: rev. 2.5, 2014-05-06
+** Build: b140611
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright (c) 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2013-07-23)
+** Initial version.
+** - rev. 1.1 (2013-09-17)
+** RM rev. 0.4 update.
+** - rev. 2.0 (2013-10-29)
+** Register accessor macros added to the memory map.
+** Symbols for Processor Expert memory map compatibility added to the memory map.
+** Startup file for gcc has been updated according to CMSIS 3.2.
+** System initialization updated.
+** - rev. 2.1 (2013-10-30)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+** - rev. 2.2 (2013-12-20)
+** Update according to reference manual rev. 0.6,
+** - rev. 2.3 (2014-01-13)
+** Update according to reference manual rev. 0.61,
+** - rev. 2.4 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
+** - rev. 2.5 (2014-05-06)
+** Update according to reference manual rev. 1.0,
+** Update of system and startup files.
+** Module access macro module_BASES replaced by module_BASE_PTRS.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK22F51212
+ * @version 2.5
+ * @date 2014-05-06
+ * @brief Device specific configuration file for MK22F51212 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "cmsis.h"
+
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+#if (DISABLE_WDOG)
+ /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
+ WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
+ /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
+ WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
+ /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+ WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
+ WDOG_STCTRLH_WAITEN_MASK |
+ WDOG_STCTRLH_STOPEN_MASK |
+ WDOG_STCTRLH_ALLOWUPDATE_MASK |
+ WDOG_STCTRLH_CLKSRC_MASK |
+ 0x0100U;
+#endif /* (DISABLE_WDOG) */
+ if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
+ {
+ if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
+ {
+ PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
+ }
+ } else {
+#ifdef SYSTEM_RTC_CR_VALUE
+ SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
+ if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
+ RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
+ RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
+ RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
+ }
+#endif
+ }
+
+ /* Power mode protection initialization */
+#ifdef SYSTEM_SMC_PMPROT_VALUE
+ SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
+#endif
+
+ /* High speed run mode enable */
+#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x03U << SMC_PMCTRL_RUNM_SHIFT))
+ SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable HSRUN mode */
+ while(SMC->PMSTAT != 0x80U) { /* Wait until the system is in HSRUN mode */
+ }
+#endif
+ /* System clock initialization */
+ /* Internal reference clock trim initialization */
+#if defined(SLOW_TRIM_ADDRESS)
+ if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */
+ MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
+ #endif /* defined(SLOW_TRIM_ADDRESS) */
+ #if defined(SLOW_FINE_TRIM_ADDRESS)
+ MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
+ #endif
+ #if defined(FAST_TRIM_ADDRESS)
+ MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
+ #endif
+ #if defined(FAST_FINE_TRIM_ADDRESS)
+ MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
+ #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
+#if defined(SLOW_TRIM_ADDRESS)
+ }
+ #endif /* defined(SLOW_TRIM_ADDRESS) */
+
+ /* Set system prescalers and clock sources */
+ SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
+ SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
+ SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+ /* Set MCG and OSC */
+#if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
+ /* SIM_SCGC5: PORTA=1 */
+ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+ /* PORTA_PCR18: ISF=0,MUX=0 */
+ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+ /* PORTA_PCR19: ISF=0,MUX=0 */
+ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ }
+#endif
+ MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
+ MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+ /* Check that the source of the FLL reference clock is the requested one. */
+ if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+ }
+ } else {
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+ }
+ }
+ MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+ MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+ OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+ MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
+ #if (MCG_MODE == MCG_MODE_BLPI)
+ /* BLPI specific */
+ MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
+ #endif
+
+#else /* MCG_MODE */
+ /* Set MCG and OSC */
+#if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
+ /* SIM_SCGC5: PORTA=1 */
+ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+ /* PORTA_PCR18: ISF=0,MUX=0 */
+ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
+ /* PORTA_PCR19: ISF=0,MUX=0 */
+ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ }
+#endif
+ MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
+ MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
+ OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
+ MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
+ #if (MCG_MODE == MCG_MODE_PEE)
+ MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
+ #else
+ MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
+ #endif
+ if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
+ }
+ }
+ /* Check that the source of the FLL reference clock is the requested one. */
+ if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
+ }
+ } else {
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
+ }
+ }
+ MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
+#endif /* MCG_MODE */
+
+ /* Common for all MCG modes */
+
+ /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
+ MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
+ MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
+ if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
+ MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
+ }
+ /* BLPE, PEE and PBE MCG mode specific */
+
+#if (MCG_MODE == MCG_MODE_BLPE)
+ MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
+#elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
+ MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
+ }
+ #if (MCG_MODE == MCG_MODE_PEE)
+ MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
+ #endif
+#endif
+#if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
+ }
+#elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
+ }
+#elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+#elif (MCG_MODE == MCG_MODE_PEE)
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
+ }
+#endif
+#if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
+ SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
+ while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
+ }
+#endif
+
+#if defined(SYSTEM_SIM_CLKDIV2_VALUE)
+ SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
+#endif
+
+ /* PLL loss of lock interrupt request initialization */
+ if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
+ NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
+ }
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint16_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
+ /* Output of FLL or PLL is selected */
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
+ /* FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
+ /* External reference clock is selected */
+ switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+ case 0x00U:
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ break;
+ case 0x01U:
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ break;
+ case 0x02U:
+ default:
+ MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+ break;
+ }
+ if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
+ switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
+ case 0x38U:
+ Divider = 1536U;
+ break;
+ case 0x30U:
+ Divider = 1280U;
+ break;
+ default:
+ Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ break;
+ }
+ } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
+ Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ }
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x00U:
+ MCGOUTClock *= 640U;
+ break;
+ case 0x20U:
+ MCGOUTClock *= 1280U;
+ break;
+ case 0x40U:
+ MCGOUTClock *= 1920U;
+ break;
+ case 0x60U:
+ MCGOUTClock *= 2560U;
+ break;
+ case 0x80U:
+ MCGOUTClock *= 732U;
+ break;
+ case 0xA0U:
+ MCGOUTClock *= 1464U;
+ break;
+ case 0xC0U:
+ MCGOUTClock *= 2197U;
+ break;
+ case 0xE0U:
+ MCGOUTClock *= 2929U;
+ break;
+ default:
+ break;
+ }
+ } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+ /* PLL is selected */
+ Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
+ MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+ Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
+ MCGOUTClock *= Divider; /* Calculate the MCG output clock */
+ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+ Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+ MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
+ /* External reference clock is selected */
+ switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
+ case 0x00U:
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ break;
+ case 0x01U:
+ MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
+ break;
+ case 0x02U:
+ default:
+ MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
+ break;
+ }
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
+ SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h
new file mode 100644
index 000000000..bdeed9c5a
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h
@@ -0,0 +1,367 @@
+/*
+** ###################################################################
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
+** Version: rev. 2.5, 2014-05-06
+** Build: b140611
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright (c) 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2013-07-23)
+** Initial version.
+** - rev. 1.1 (2013-09-17)
+** RM rev. 0.4 update.
+** - rev. 2.0 (2013-10-29)
+** Register accessor macros added to the memory map.
+** Symbols for Processor Expert memory map compatibility added to the memory map.
+** Startup file for gcc has been updated according to CMSIS 3.2.
+** System initialization updated.
+** - rev. 2.1 (2013-10-30)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+** - rev. 2.2 (2013-12-20)
+** Update according to reference manual rev. 0.6,
+** - rev. 2.3 (2014-01-13)
+** Update according to reference manual rev. 0.61,
+** - rev. 2.4 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
+** - rev. 2.5 (2014-05-06)
+** Update according to reference manual rev. 1.0,
+** Update of system and startup files.
+** Module access macro module_BASES replaced by module_BASE_PTRS.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK22F51212
+ * @version 2.5
+ * @date 2014-05-06
+ * @brief Device specific configuration file for MK22F51212 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MK22F51212_H_
+#define SYSTEM_MK22F51212_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#define DISABLE_WDOG 1
+
+#ifndef CLOCK_SETUP
+ #define CLOCK_SETUP 4
+#endif
+
+/* MCG mode constants */
+
+#define MCG_MODE_FEI 0U
+#define MCG_MODE_FBI 1U
+#define MCG_MODE_BLPI 2U
+#define MCG_MODE_FEE 3U
+#define MCG_MODE_FBE 4U
+#define MCG_MODE_BLPE 5U
+#define MCG_MODE_PBE 6U
+#define MCG_MODE_PEE 7U
+
+/* Predefined clock setups
+ 0 ... Default part configuration
+ Multipurpose Clock Generator (MCG) in FEI mode.
+ Reference clock source for MCG module: Slow internal reference clock
+ Core clock = 20.97152MHz
+ Bus clock = 20.97152MHz
+ 1 ... Maximum achievable clock frequency configuration
+ Multipurpose Clock Generator (MCG) in PEE mode.
+ Reference clock source for MCG module: System oscillator 0 reference clock
+ Core clock = 120MHz
+ Bus clock = 60MHz
+ 2 ... Chip internaly clocked, ready for Very Low Power Run mode.
+ Multipurpose Clock Generator (MCG) in BLPI mode.
+ Reference clock source for MCG module: Fast internal reference clock
+ Core clock = 4MHz
+ Bus clock = 4MHz
+ 3 ... Chip externally clocked, ready for Very Low Power Run mode.
+ Multipurpose Clock Generator (MCG) in BLPE mode.
+ Reference clock source for MCG module: System oscillator 0 reference clock
+ Core clock = 4MHz
+ Bus clock = 4MHz
+ 4 ... USB clock setup
+ Multipurpose Clock Generator (MCG) in PEE mode.
+ Reference clock source for MCG module: System oscillator 0 reference clock
+ Core clock = 120MHz
+ Bus clock = 60MHz
+ 5 ... Maximum achievable clock frequency configuration in RUN mode
+ Multipurpose Clock Generator (MCG) in PEE mode.
+ Reference clock source for MCG module: System oscillator 0 reference clock
+ Core clock = 80MHz
+ Bus clock = 40MHz
+ */
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_XTAL32k_CLK_HZ 32768u /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE 0x0300U /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE 0xAAU /* SMC_PMPROT */
+
+/* Internal reference clock trim */
+/* #undef SLOW_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef SLOW_FINE_TRIM_ADDRESS */ /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+/* #undef FAST_FINE_TRIM_ADDRESS */ /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
+
+#if (CLOCK_SETUP == 0)
+ #define DEFAULT_SYSTEM_CLOCK 20971520u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_FEI /* Clock generator mode */
+ /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x06U /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x00110000U /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 1)
+ #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
+ /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
+ #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
+ #define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 2)
+ #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_BLPI /* Clock generator mode */
+ /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x46U /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+ #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x00040000U /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 3)
+ #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_BLPE /* Clock generator mode */
+ /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x9AU /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
+ #define SYSTEM_MCG_C2_VALUE 0x27U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x02U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ #define SYSTEM_MCG_C5_VALUE 0x00U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ #define SYSTEM_MCG_C6_VALUE 0x00U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x00U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV3=1,OUTDIV4=7 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x11170000U /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00030000U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 4)
+ #define DEFAULT_SYSTEM_CLOCK 120000000u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
+ /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
+ #define SYSTEM_MCG_C5_VALUE 0x01U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
+ #define SYSTEM_MCG_C6_VALUE 0x46U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x60U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x01140000U /* SIM_CLKDIV1 */
+/* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
+ #define SYSTEM_SIM_CLKDIV2_VALUE 0x09U /* SIM_CLKDIV2 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 5)
+ #define DEFAULT_SYSTEM_CLOCK 80000000u /* Default System clock value */
+ #define MCG_MODE MCG_MODE_PEE /* Clock generator mode */
+ /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ #define SYSTEM_MCG_C1_VALUE 0x1AU /* MCG_C1 */
+ /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+ #define SYSTEM_MCG_C2_VALUE 0x24U /* MCG_C2 */
+ /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
+ #define SYSTEM_MCG_C4_VALUE 0x00U /* MCG_C4 */
+ /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
+ #define SYSTEM_MCG_SC_VALUE 0x00U /* MCG_SC */
+/* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
+ #define SYSTEM_MCG_C5_VALUE 0x03U /* MCG_C5 */
+/* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x10 */
+ #define SYSTEM_MCG_C6_VALUE 0x50U /* MCG_C6 */
+/* MCG_C7: OSCSEL=0 */
+ #define SYSTEM_MCG_C7_VALUE 0x00U /* MCG_C7 */
+/* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define SYSTEM_OSC_CR_VALUE 0x80U /* OSC_CR */
+/* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SYSTEM_SMC_PMCTRL_VALUE 0x00U /* SMC_PMCTRL */
+/* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x01130000U /* SIM_CLKDIV1 */
+/* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00080000U /* SIM_SOPT1 */
+/* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x00010000U /* SIM_SOPT2 */
+#endif
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MK22F51212_H_) */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/MKL05Z4.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/MKL05Z4.h
new file mode 100644
index 000000000..cc046d06e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/MKL05Z4.h
@@ -0,0 +1,3613 @@
+/*
+** ###################################################################
+** Processors: MKL05Z32FK4
+** MKL05Z32LC4
+** MKL05Z32VLF4
+**
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
+** Version: rev. 1.3, 2012-10-04
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MKL05Z4
+**
+** Copyright: 1997 - 2012 Freescale, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-08)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+** - rev. 1.2 (2012-08-01)
+** Device type UARTLP changed to UART0.
+** Missing PORTB_IRQn interrupt number definition added.
+** - rev. 1.3 (2012-10-04)
+** Update according to reference manual rev. 3.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL05Z4.h
+ * @version 1.3
+ * @date 2012-10-04
+ * @brief CMSIS Peripheral Access Layer for MKL05Z4
+ *
+ * CMSIS Peripheral Access Layer for MKL05Z4
+ */
+
+#if !defined(MKL05Z4_H_)
+#define MKL05Z4_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0003u
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
+ Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
+ FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
+ LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 7, /**< Low Leakage Wakeup */
+ I2C0_IRQn = 8, /**< I2C0 interrupt */
+ Reserved25_IRQn = 9, /**< Reserved interrupt 25 */
+ SPI0_IRQn = 10, /**< SPI0 interrupt */
+ Reserved27_IRQn = 11, /**< Reserved interrupt 27 */
+ UART0_IRQn = 12, /**< UART0 status/error interrupt */
+ Reserved29_IRQn = 13, /**< Reserved interrupt 29 */
+ Reserved30_IRQn = 14, /**< Reserved interrupt 30 */
+ ADC0_IRQn = 15, /**< ADC0 interrupt */
+ CMP0_IRQn = 16, /**< CMP0 interrupt */
+ TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
+ TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
+ Reserved35_IRQn = 19, /**< Reserved interrupt 35 */
+ RTC_IRQn = 20, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
+ PIT_IRQn = 22, /**< PIT timer interrupt */
+ Reserved39_IRQn = 23, /**< Reserved interrupt 39 */
+ Reserved40_IRQn = 24, /**< Reserved interrupt 40 */
+ DAC0_IRQn = 25, /**< DAC0 interrupt */
+ TSI0_IRQn = 26, /**< TSI0 interrupt */
+ MCG_IRQn = 27, /**< MCG interrupt */
+ LPTimer_IRQn = 28, /**< LPTimer interrupt */
+ Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
+ PORTA_IRQn = 30, /**< Port A interrupt */
+ PORTB_IRQn = 31 /**< Port B interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M0 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h" /* Core Peripheral Access Layer */
+#include "system_MKL05Z4.h" /* Device specific configuration file */
+
+/**
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+
+/**
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASES { ADC0 }
+
+/**
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_TRIGM_MASK 0x20u
+#define CMP_CR1_TRIGM_SHIFT 5
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK 0x80u
+#define CMP_MUXCR_PSTM_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASES { CMP0 }
+
+/**
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[2];
+ uint8_t RESERVED_0[28];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x4u
+#define DAC_C1_DACBFMD_SHIFT 2
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0x1u
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFRP_MASK 0x10u
+#define DAC_C2_DACBFRP_SHIFT 4
+
+/**
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASES { DAC0 }
+
+/**
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[256];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
+ __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
+ union { /* offset: 0x108, array step: 0x10 */
+ __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
+ struct { /* offset: 0x108, array step: 0x10 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
+ } DMA_DSR_ACCESS8BIT;
+ };
+ __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
+ } DMA[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* SAR Bit Fields */
+#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
+#define DMA_SAR_SAR_SHIFT 0
+#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
+/* DAR Bit Fields */
+#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
+#define DMA_DAR_DAR_SHIFT 0
+#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
+/* DSR_BCR Bit Fields */
+#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
+#define DMA_DSR_BCR_BCR_SHIFT 0
+#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
+#define DMA_DSR_BCR_DONE_MASK 0x1000000u
+#define DMA_DSR_BCR_DONE_SHIFT 24
+#define DMA_DSR_BCR_BSY_MASK 0x2000000u
+#define DMA_DSR_BCR_BSY_SHIFT 25
+#define DMA_DSR_BCR_REQ_MASK 0x4000000u
+#define DMA_DSR_BCR_REQ_SHIFT 26
+#define DMA_DSR_BCR_BED_MASK 0x10000000u
+#define DMA_DSR_BCR_BED_SHIFT 28
+#define DMA_DSR_BCR_BES_MASK 0x20000000u
+#define DMA_DSR_BCR_BES_SHIFT 29
+#define DMA_DSR_BCR_CE_MASK 0x40000000u
+#define DMA_DSR_BCR_CE_SHIFT 30
+/* DCR Bit Fields */
+#define DMA_DCR_LCH2_MASK 0x3u
+#define DMA_DCR_LCH2_SHIFT 0
+#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
+#define DMA_DCR_LCH1_MASK 0xCu
+#define DMA_DCR_LCH1_SHIFT 2
+#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
+#define DMA_DCR_LINKCC_MASK 0x30u
+#define DMA_DCR_LINKCC_SHIFT 4
+#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
+#define DMA_DCR_D_REQ_MASK 0x80u
+#define DMA_DCR_D_REQ_SHIFT 7
+#define DMA_DCR_DMOD_MASK 0xF00u
+#define DMA_DCR_DMOD_SHIFT 8
+#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
+#define DMA_DCR_SMOD_MASK 0xF000u
+#define DMA_DCR_SMOD_SHIFT 12
+#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
+#define DMA_DCR_START_MASK 0x10000u
+#define DMA_DCR_START_SHIFT 16
+#define DMA_DCR_DSIZE_MASK 0x60000u
+#define DMA_DCR_DSIZE_SHIFT 17
+#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
+#define DMA_DCR_DINC_MASK 0x80000u
+#define DMA_DCR_DINC_SHIFT 19
+#define DMA_DCR_SSIZE_MASK 0x300000u
+#define DMA_DCR_SSIZE_SHIFT 20
+#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
+#define DMA_DCR_SINC_MASK 0x400000u
+#define DMA_DCR_SINC_SHIFT 22
+#define DMA_DCR_EADREQ_MASK 0x800000u
+#define DMA_DCR_EADREQ_SHIFT 23
+#define DMA_DCR_AA_MASK 0x10000000u
+#define DMA_DCR_AA_SHIFT 28
+#define DMA_DCR_CS_MASK 0x20000000u
+#define DMA_DCR_CS_SHIFT 29
+#define DMA_DCR_ERQ_MASK 0x40000000u
+#define DMA_DCR_ERQ_SHIFT 30
+#define DMA_DCR_EINT_MASK 0x80000000u
+#define DMA_DCR_EINT_SHIFT 31
+
+/**
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASES { DMA0 }
+
+/**
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASES { DMAMUX0 }
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define FGPIO_PDOR_PDO_SHIFT 0
+#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define FGPIO_PSOR_PTSO_SHIFT 0
+#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define FGPIO_PCOR_PTCO_SHIFT 0
+#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define FGPIO_PTOR_PTTO_SHIFT 0
+#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define FGPIO_PDIR_PDI_SHIFT 0
+#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define FGPIO_PDDR_PDD_SHIFT 0
+#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FPTA base address */
+#define FPTA_BASE (0xF80FF000u)
+/** Peripheral FPTA base pointer */
+#define FPTA ((FGPIO_Type *)FPTA_BASE)
+/** Peripheral FPTB base address */
+#define FPTB_BASE (0xF80FF040u)
+/** Peripheral FPTB base pointer */
+#define FPTB ((FGPIO_Type *)FPTB_BASE)
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASES { FPTA, FPTB }
+
+/**
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+} FTFA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFA_FSTAT_MGSTAT0_SHIFT 0
+#define FTFA_FSTAT_FPVIOL_MASK 0x10u
+#define FTFA_FSTAT_FPVIOL_SHIFT 4
+#define FTFA_FSTAT_ACCERR_MASK 0x20u
+#define FTFA_FSTAT_ACCERR_SHIFT 5
+#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFA_FSTAT_RDCOLERR_SHIFT 6
+#define FTFA_FSTAT_CCIF_MASK 0x80u
+#define FTFA_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFA_FCNFG_ERSSUSP_SHIFT 4
+#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFA_FCNFG_ERSAREQ_SHIFT 5
+#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFA_FCNFG_CCIE_MASK 0x80u
+#define FTFA_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFA_FSEC_SEC_MASK 0x3u
+#define FTFA_FSEC_SEC_SHIFT 0
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK 0xCu
+#define FTFA_FSEC_FSLACC_SHIFT 2
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK 0x30u
+#define FTFA_FSEC_MEEN_SHIFT 4
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK 0xC0u
+#define FTFA_FSEC_KEYEN_SHIFT 6
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFA_FOPT_OPT_MASK 0xFFu
+#define FTFA_FOPT_OPT_SHIFT 0
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB3_CCOBn_SHIFT 0
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB2_CCOBn_SHIFT 0
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB1_CCOBn_SHIFT 0
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB0_CCOBn_SHIFT 0
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB7_CCOBn_SHIFT 0
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB6_CCOBn_SHIFT 0
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB5_CCOBn_SHIFT 0
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB4_CCOBn_SHIFT 0
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBB_CCOBn_SHIFT 0
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBA_CCOBn_SHIFT 0
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB9_CCOBn_SHIFT 0
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB8_CCOBn_SHIFT 0
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFA_FPROT3_PROT_MASK 0xFFu
+#define FTFA_FPROT3_PROT_SHIFT 0
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFA_FPROT2_PROT_MASK 0xFFu
+#define FTFA_FPROT2_PROT_SHIFT 0
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFA_FPROT1_PROT_MASK 0xFFu
+#define FTFA_FPROT1_PROT_SHIFT 0
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFA_FPROT0_PROT_MASK 0xFFu
+#define FTFA_FPROT0_PROT_SHIFT 0
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
+
+/**
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA ((FTFA_Type *)FTFA_BASE)
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASES { FTFA }
+
+/**
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASES { PTA, PTB }
+
+/**
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0x1Fu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STOPIE_MASK 0x20u
+#define I2C_FLT_STOPIE_SHIFT 5
+#define I2C_FLT_STOPF_MASK 0x40u
+#define I2C_FLT_STOPF_SHIFT 6
+#define I2C_FLT_SHEN_MASK 0x80u
+#define I2C_FLT_SHEN_SHIFT 7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASES { I2C0 }
+
+/**
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x2 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x3 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x4 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x5 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x6 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASES { LLWU }
+
+/**
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/**
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASES { LPTMR0 }
+
+/**
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __I uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS0_MASK 0x4u
+#define MCG_C2_EREFS0_SHIFT 2
+#define MCG_C2_HGO0_MASK 0x8u
+#define MCG_C2_HGO0_SHIFT 3
+#define MCG_C2_RANGE0_MASK 0x30u
+#define MCG_C2_RANGE0_SHIFT 4
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C6 Bit Fields */
+#define MCG_C6_CME_MASK 0x20u
+#define MCG_C6_CME_SHIFT 5
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+
+/**
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASES { MCG }
+
+/**
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK 0xFFu
+#define MCM_PLASC_ASC_SHIFT 0
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK 0xFFu
+#define MCM_PLAMC_AMC_SHIFT 0
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_ARB_MASK 0x200u
+#define MCM_PLACR_ARB_SHIFT 9
+#define MCM_PLACR_CFCC_MASK 0x400u
+#define MCM_PLACR_CFCC_SHIFT 10
+#define MCM_PLACR_DFCDA_MASK 0x800u
+#define MCM_PLACR_DFCDA_SHIFT 11
+#define MCM_PLACR_DFCIC_MASK 0x1000u
+#define MCM_PLACR_DFCIC_SHIFT 12
+#define MCM_PLACR_DFCC_MASK 0x2000u
+#define MCM_PLACR_DFCC_SHIFT 13
+#define MCM_PLACR_EFDS_MASK 0x4000u
+#define MCM_PLACR_EFDS_SHIFT 14
+#define MCM_PLACR_DFCS_MASK 0x8000u
+#define MCM_PLACR_DFCS_SHIFT 15
+#define MCM_PLACR_ESFC_MASK 0x10000u
+#define MCM_PLACR_ESFC_SHIFT 16
+/* CPO Bit Fields */
+#define MCM_CPO_CPOREQ_MASK 0x1u
+#define MCM_CPO_CPOREQ_SHIFT 0
+#define MCM_CPO_CPOACK_MASK 0x2u
+#define MCM_CPO_CPOACK_SHIFT 1
+#define MCM_CPO_CPOWOI_MASK 0x4u
+#define MCM_CPO_CPOWOI_SHIFT 2
+
+/**
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASES { MCM }
+
+/**
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
+ __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
+ __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
+ __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
+ uint8_t RESERVED_0[3824];
+ __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
+ uint8_t RESERVED_1[156];
+ __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
+ __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
+ uint8_t RESERVED_2[8];
+ __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
+ __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
+ __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
+ __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
+ uint8_t RESERVED_3[8];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/* POSITION Bit Fields */
+#define MTB_POSITION_WRAP_MASK 0x4u
+#define MTB_POSITION_WRAP_SHIFT 2
+#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
+#define MTB_POSITION_POINTER_SHIFT 3
+#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
+/* MASTER Bit Fields */
+#define MTB_MASTER_MASK_MASK 0x1Fu
+#define MTB_MASTER_MASK_SHIFT 0
+#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK 0x20u
+#define MTB_MASTER_TSTARTEN_SHIFT 5
+#define MTB_MASTER_TSTOPEN_MASK 0x40u
+#define MTB_MASTER_TSTOPEN_SHIFT 6
+#define MTB_MASTER_SFRWPRIV_MASK 0x80u
+#define MTB_MASTER_SFRWPRIV_SHIFT 7
+#define MTB_MASTER_RAMPRIV_MASK 0x100u
+#define MTB_MASTER_RAMPRIV_SHIFT 8
+#define MTB_MASTER_HALTREQ_MASK 0x200u
+#define MTB_MASTER_HALTREQ_SHIFT 9
+#define MTB_MASTER_EN_MASK 0x80000000u
+#define MTB_MASTER_EN_SHIFT 31
+/* FLOW Bit Fields */
+#define MTB_FLOW_AUTOSTOP_MASK 0x1u
+#define MTB_FLOW_AUTOSTOP_SHIFT 0
+#define MTB_FLOW_AUTOHALT_MASK 0x2u
+#define MTB_FLOW_AUTOHALT_SHIFT 1
+#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
+#define MTB_FLOW_WATERMARK_SHIFT 3
+#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
+/* BASE Bit Fields */
+#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
+#define MTB_BASE_BASEADDR_SHIFT 0
+#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
+/* MODECTRL Bit Fields */
+#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
+#define MTB_MODECTRL_MODECTRL_SHIFT 0
+#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
+/* TAGSET Bit Fields */
+#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
+#define MTB_TAGSET_TAGSET_SHIFT 0
+#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
+/* TAGCLEAR Bit Fields */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
+#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
+/* LOCKACCESS Bit Fields */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
+#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
+/* LOCKSTAT Bit Fields */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
+#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
+/* AUTHSTAT Bit Fields */
+#define MTB_AUTHSTAT_BIT0_MASK 0x1u
+#define MTB_AUTHSTAT_BIT0_SHIFT 0
+#define MTB_AUTHSTAT_BIT1_MASK 0x2u
+#define MTB_AUTHSTAT_BIT1_SHIFT 1
+#define MTB_AUTHSTAT_BIT2_MASK 0x4u
+#define MTB_AUTHSTAT_BIT2_SHIFT 2
+#define MTB_AUTHSTAT_BIT3_MASK 0x8u
+#define MTB_AUTHSTAT_BIT3_SHIFT 3
+/* DEVICEARCH Bit Fields */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
+#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
+/* DEVICECFG Bit Fields */
+#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTB_PERIPHID_PERIPHID_SHIFT 0
+#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTB_COMPID_COMPID_SHIFT 0
+#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB ((MTB_Type *)MTB_BASE)
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASES { MTB }
+
+/**
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+ __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ struct { /* offset: 0x20, array step: 0x10 */
+ __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+ __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+ __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } COMPARATOR[2];
+ uint8_t RESERVED_1[448];
+ __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+ uint8_t RESERVED_2[3524];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
+#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
+#define MTBDWT_CTRL_NUMCMP_SHIFT 28
+#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
+/* COMP Bit Fields */
+#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
+#define MTBDWT_COMP_COMP_SHIFT 0
+#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
+/* MASK Bit Fields */
+#define MTBDWT_MASK_MASK_MASK 0x1Fu
+#define MTBDWT_MASK_MASK_SHIFT 0
+#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
+/* FCT Bit Fields */
+#define MTBDWT_FCT_FUNCTION_MASK 0xFu
+#define MTBDWT_FCT_FUNCTION_SHIFT 0
+#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
+#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
+#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
+#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
+#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
+#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
+#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
+#define MTBDWT_FCT_MATCHED_SHIFT 24
+/* TBCTRL Bit Fields */
+#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
+#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
+#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
+#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
+/* DEVICECFG Bit Fields */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
+#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTBDWT_COMPID_COMPID_SHIFT 0
+#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASES { MTBDWT }
+
+/**
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT0_MASK 0x1u
+#define NV_FOPT_LPBOOT0_SHIFT 0
+#define NV_FOPT_EZPORT_DIS_MASK 0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT 1
+#define NV_FOPT_NMI_DIS_MASK 0x4u
+#define NV_FOPT_NMI_DIS_SHIFT 2
+#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
+#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
+#define NV_FOPT_LPBOOT1_MASK 0x10u
+#define NV_FOPT_LPBOOT1_SHIFT 4
+#define NV_FOPT_FAST_INIT_MASK 0x20u
+#define NV_FOPT_FAST_INIT_SHIFT 5
+
+/**
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASES { FTFA_FlashConfig }
+
+/**
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASES { OSC0 }
+
+/**
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[220];
+ __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+ __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+ uint8_t RESERVED_1[24];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[2];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LTMR64H Bit Fields */
+#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
+#define PIT_LTMR64H_LTH_SHIFT 0
+#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
+/* LTMR64L Bit Fields */
+#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
+#define PIT_LTMR64L_LTL_SHIFT 0
+#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+#define PIT_TCTRL_CHN_MASK 0x4u
+#define PIT_TCTRL_CHN_SHIFT 2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/**
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASES { PIT }
+
+/**
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+#define PMC_REGSC_BGEN_MASK 0x10u
+#define PMC_REGSC_BGEN_SHIFT 4
+
+/**
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASES { PMC }
+
+/**
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+
+/**
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASES { PORTA, PORTB }
+
+/**
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASES { RCM }
+
+/**
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ROM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+ __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
+ __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
+ uint8_t RESERVED_0[4028];
+ __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ROM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/* ENTRY Bit Fields */
+#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
+#define ROM_ENTRY_ENTRY_SHIFT 0
+#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
+/* TABLEMARK Bit Fields */
+#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
+#define ROM_TABLEMARK_MARK_SHIFT 0
+#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
+/* SYSACCESS Bit Fields */
+#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
+#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
+#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
+/* PERIPHID4 Bit Fields */
+#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID4_PERIPHID_SHIFT 0
+#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
+/* PERIPHID5 Bit Fields */
+#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID5_PERIPHID_SHIFT 0
+#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
+/* PERIPHID6 Bit Fields */
+#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID6_PERIPHID_SHIFT 0
+#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
+/* PERIPHID7 Bit Fields */
+#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID7_PERIPHID_SHIFT 0
+#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
+/* PERIPHID0 Bit Fields */
+#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID0_PERIPHID_SHIFT 0
+#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
+/* PERIPHID1 Bit Fields */
+#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID1_PERIPHID_SHIFT 0
+#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
+/* PERIPHID2 Bit Fields */
+#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID2_PERIPHID_SHIFT 0
+#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
+/* PERIPHID3 Bit Fields */
+#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID3_PERIPHID_SHIFT 0
+#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define ROM_COMPID_COMPID_SHIFT 0
+#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM ((ROM_Type *)ROM_BASE)
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASES { ROM }
+
+/**
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+#define RTC_IER_WPON_MASK 0x80u
+#define RTC_IER_WPON_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASES { RTC }
+
+/**
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __I uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ uint8_t RESERVED_6[4];
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+ uint8_t RESERVED_7[156];
+ __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
+ __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
+#define SIM_SOPT2_TPMSRC_SHIFT 24
+#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
+#define SIM_SOPT2_UART0SRC_SHIFT 26
+#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
+#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x1u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART0ODE_MASK 0x10000u
+#define SIM_SOPT5_UART0ODE_SHIFT 16
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_DIEID_MASK 0xF80u
+#define SIM_SDID_DIEID_SHIFT 7
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
+#define SIM_SDID_SRAMSIZE_SHIFT 16
+#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
+#define SIM_SDID_SERIESID_MASK 0xF00000u
+#define SIM_SDID_SERIESID_SHIFT 20
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK 0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT 24
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK 0xF0000000u
+#define SIM_SDID_FAMID_SHIFT 28
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_SPI0_MASK 0x400000u
+#define SIM_SCGC4_SPI0_SHIFT 22
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK 0x1u
+#define SIM_SCGC5_LPTMR_SHIFT 0
+#define SIM_SCGC5_TSI_MASK 0x20u
+#define SIM_SCGC5_TSI_SHIFT 5
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK 0x1u
+#define SIM_SCGC6_FTF_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_TPM0_MASK 0x1000000u
+#define SIM_SCGC6_TPM0_SHIFT 24
+#define SIM_SCGC6_TPM1_MASK 0x2000000u
+#define SIM_SCGC6_TPM1_SHIFT 25
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+#define SIM_SCGC6_DAC0_MASK 0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT 31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK 0x100u
+#define SIM_SCGC7_DMA_SHIFT 8
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT 24
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/* COPC Bit Fields */
+#define SIM_COPC_COPW_MASK 0x1u
+#define SIM_COPC_COPW_SHIFT 0
+#define SIM_COPC_COPCLKS_MASK 0x2u
+#define SIM_COPC_COPCLKS_SHIFT 1
+#define SIM_COPC_COPT_MASK 0xCu
+#define SIM_COPC_COPT_SHIFT 2
+#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
+/* SRVCOP Bit Fields */
+#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
+#define SIM_SRVCOP_SRVCOP_SHIFT 0
+#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
+
+/**
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASES { SIM }
+
+/**
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+/* STOPCTRL Bit Fields */
+#define SMC_STOPCTRL_VLLSM_MASK 0x7u
+#define SMC_STOPCTRL_VLLSM_SHIFT 0
+#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK 0x20u
+#define SMC_STOPCTRL_PORPO_SHIFT 5
+#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
+#define SMC_STOPCTRL_PSTOPO_SHIFT 6
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/**
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASES { SMC }
+
+/**
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */
+ __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */
+ __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
+ __I uint8_t S; /**< SPI status register, offset: 0x3 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t D; /**< SPI data register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t M; /**< SPI match register, offset: 0x7 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define SPI_C1_LSBFE_MASK 0x1u
+#define SPI_C1_LSBFE_SHIFT 0
+#define SPI_C1_SSOE_MASK 0x2u
+#define SPI_C1_SSOE_SHIFT 1
+#define SPI_C1_CPHA_MASK 0x4u
+#define SPI_C1_CPHA_SHIFT 2
+#define SPI_C1_CPOL_MASK 0x8u
+#define SPI_C1_CPOL_SHIFT 3
+#define SPI_C1_MSTR_MASK 0x10u
+#define SPI_C1_MSTR_SHIFT 4
+#define SPI_C1_SPTIE_MASK 0x20u
+#define SPI_C1_SPTIE_SHIFT 5
+#define SPI_C1_SPE_MASK 0x40u
+#define SPI_C1_SPE_SHIFT 6
+#define SPI_C1_SPIE_MASK 0x80u
+#define SPI_C1_SPIE_SHIFT 7
+/* C2 Bit Fields */
+#define SPI_C2_SPC0_MASK 0x1u
+#define SPI_C2_SPC0_SHIFT 0
+#define SPI_C2_SPISWAI_MASK 0x2u
+#define SPI_C2_SPISWAI_SHIFT 1
+#define SPI_C2_RXDMAE_MASK 0x4u
+#define SPI_C2_RXDMAE_SHIFT 2
+#define SPI_C2_BIDIROE_MASK 0x8u
+#define SPI_C2_BIDIROE_SHIFT 3
+#define SPI_C2_MODFEN_MASK 0x10u
+#define SPI_C2_MODFEN_SHIFT 4
+#define SPI_C2_TXDMAE_MASK 0x20u
+#define SPI_C2_TXDMAE_SHIFT 5
+#define SPI_C2_SPMIE_MASK 0x80u
+#define SPI_C2_SPMIE_SHIFT 7
+/* BR Bit Fields */
+#define SPI_BR_SPR_MASK 0xFu
+#define SPI_BR_SPR_SHIFT 0
+#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK 0x70u
+#define SPI_BR_SPPR_SHIFT 4
+#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
+/* S Bit Fields */
+#define SPI_S_MODF_MASK 0x10u
+#define SPI_S_MODF_SHIFT 4
+#define SPI_S_SPTEF_MASK 0x20u
+#define SPI_S_SPTEF_SHIFT 5
+#define SPI_S_SPMF_MASK 0x40u
+#define SPI_S_SPMF_SHIFT 6
+#define SPI_S_SPRF_MASK 0x80u
+#define SPI_S_SPRF_SHIFT 7
+/* D Bit Fields */
+#define SPI_D_Bits_MASK 0xFFu
+#define SPI_D_Bits_SHIFT 0
+#define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
+/* M Bit Fields */
+#define SPI_M_Bits_MASK 0xFFu
+#define SPI_M_Bits_SHIFT 0
+#define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
+
+/**
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASES { SPI0 }
+
+/**
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[6];
+ uint8_t RESERVED_0[20];
+ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TPM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define TPM_SC_PS_MASK 0x7u
+#define TPM_SC_PS_SHIFT 0
+#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK 0x18u
+#define TPM_SC_CMOD_SHIFT 3
+#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK 0x20u
+#define TPM_SC_CPWMS_SHIFT 5
+#define TPM_SC_TOIE_MASK 0x40u
+#define TPM_SC_TOIE_SHIFT 6
+#define TPM_SC_TOF_MASK 0x80u
+#define TPM_SC_TOF_SHIFT 7
+#define TPM_SC_DMA_MASK 0x100u
+#define TPM_SC_DMA_SHIFT 8
+/* CNT Bit Fields */
+#define TPM_CNT_COUNT_MASK 0xFFFFu
+#define TPM_CNT_COUNT_SHIFT 0
+#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define TPM_MOD_MOD_MASK 0xFFFFu
+#define TPM_MOD_MOD_SHIFT 0
+#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define TPM_CnSC_DMA_MASK 0x1u
+#define TPM_CnSC_DMA_SHIFT 0
+#define TPM_CnSC_ELSA_MASK 0x4u
+#define TPM_CnSC_ELSA_SHIFT 2
+#define TPM_CnSC_ELSB_MASK 0x8u
+#define TPM_CnSC_ELSB_SHIFT 3
+#define TPM_CnSC_MSA_MASK 0x10u
+#define TPM_CnSC_MSA_SHIFT 4
+#define TPM_CnSC_MSB_MASK 0x20u
+#define TPM_CnSC_MSB_SHIFT 5
+#define TPM_CnSC_CHIE_MASK 0x40u
+#define TPM_CnSC_CHIE_SHIFT 6
+#define TPM_CnSC_CHF_MASK 0x80u
+#define TPM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define TPM_CnV_VAL_MASK 0xFFFFu
+#define TPM_CnV_VAL_SHIFT 0
+#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
+/* STATUS Bit Fields */
+#define TPM_STATUS_CH0F_MASK 0x1u
+#define TPM_STATUS_CH0F_SHIFT 0
+#define TPM_STATUS_CH1F_MASK 0x2u
+#define TPM_STATUS_CH1F_SHIFT 1
+#define TPM_STATUS_CH2F_MASK 0x4u
+#define TPM_STATUS_CH2F_SHIFT 2
+#define TPM_STATUS_CH3F_MASK 0x8u
+#define TPM_STATUS_CH3F_SHIFT 3
+#define TPM_STATUS_CH4F_MASK 0x10u
+#define TPM_STATUS_CH4F_SHIFT 4
+#define TPM_STATUS_CH5F_MASK 0x20u
+#define TPM_STATUS_CH5F_SHIFT 5
+#define TPM_STATUS_TOF_MASK 0x100u
+#define TPM_STATUS_TOF_SHIFT 8
+/* CONF Bit Fields */
+#define TPM_CONF_DOZEEN_MASK 0x20u
+#define TPM_CONF_DOZEEN_SHIFT 5
+#define TPM_CONF_DBGMODE_MASK 0xC0u
+#define TPM_CONF_DBGMODE_SHIFT 6
+#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBEEN_MASK 0x200u
+#define TPM_CONF_GTBEEN_SHIFT 9
+#define TPM_CONF_CSOT_MASK 0x10000u
+#define TPM_CONF_CSOT_SHIFT 16
+#define TPM_CONF_CSOO_MASK 0x20000u
+#define TPM_CONF_CSOO_SHIFT 17
+#define TPM_CONF_CROT_MASK 0x40000u
+#define TPM_CONF_CROT_SHIFT 18
+#define TPM_CONF_TRGSEL_MASK 0xF000000u
+#define TPM_CONF_TRGSEL_SHIFT 24
+#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0 ((TPM_Type *)TPM0_BASE)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1 ((TPM_Type *)TPM1_BASE)
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASES { TPM0, TPM1 }
+
+/**
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
+ __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
+ __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/* GENCS Bit Fields */
+#define TSI_GENCS_CURSW_MASK 0x2u
+#define TSI_GENCS_CURSW_SHIFT 1
+#define TSI_GENCS_EOSF_MASK 0x4u
+#define TSI_GENCS_EOSF_SHIFT 2
+#define TSI_GENCS_SCNIP_MASK 0x8u
+#define TSI_GENCS_SCNIP_SHIFT 3
+#define TSI_GENCS_STM_MASK 0x10u
+#define TSI_GENCS_STM_SHIFT 4
+#define TSI_GENCS_STPE_MASK 0x20u
+#define TSI_GENCS_STPE_SHIFT 5
+#define TSI_GENCS_TSIIEN_MASK 0x40u
+#define TSI_GENCS_TSIIEN_SHIFT 6
+#define TSI_GENCS_TSIEN_MASK 0x80u
+#define TSI_GENCS_TSIEN_SHIFT 7
+#define TSI_GENCS_NSCN_MASK 0x1F00u
+#define TSI_GENCS_NSCN_SHIFT 8
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_PS_MASK 0xE000u
+#define TSI_GENCS_PS_SHIFT 13
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
+#define TSI_GENCS_EXTCHRG_MASK 0x70000u
+#define TSI_GENCS_EXTCHRG_SHIFT 16
+#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_DVOLT_MASK 0x180000u
+#define TSI_GENCS_DVOLT_SHIFT 19
+#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_REFCHRG_MASK 0xE00000u
+#define TSI_GENCS_REFCHRG_SHIFT 21
+#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_MODE_MASK 0xF000000u
+#define TSI_GENCS_MODE_SHIFT 24
+#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_ESOR_MASK 0x10000000u
+#define TSI_GENCS_ESOR_SHIFT 28
+#define TSI_GENCS_OUTRGF_MASK 0x80000000u
+#define TSI_GENCS_OUTRGF_SHIFT 31
+/* DATA Bit Fields */
+#define TSI_DATA_TSICNT_MASK 0xFFFFu
+#define TSI_DATA_TSICNT_SHIFT 0
+#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_SWTS_MASK 0x400000u
+#define TSI_DATA_SWTS_SHIFT 22
+#define TSI_DATA_DMAEN_MASK 0x800000u
+#define TSI_DATA_DMAEN_SHIFT 23
+#define TSI_DATA_TSICH_MASK 0xF0000000u
+#define TSI_DATA_TSICH_SHIFT 28
+#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
+/* TSHD Bit Fields */
+#define TSI_TSHD_THRESL_MASK 0xFFFFu
+#define TSI_TSHD_THRESL_SHIFT 0
+#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
+#define TSI_TSHD_THRESH_SHIFT 16
+#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
+
+/**
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+/** Array initializer of TSI peripheral base pointers */
+#define TSI_BASES { TSI0 }
+
+/**
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART0 Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
+ * @{
+ */
+
+/** UART0 - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+} UART0_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART0 Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART0_Register_Masks UART0 Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART0_BDH_SBR_MASK 0x1Fu
+#define UART0_BDH_SBR_SHIFT 0
+#define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
+#define UART0_BDH_SBNS_MASK 0x20u
+#define UART0_BDH_SBNS_SHIFT 5
+#define UART0_BDH_RXEDGIE_MASK 0x40u
+#define UART0_BDH_RXEDGIE_SHIFT 6
+#define UART0_BDH_LBKDIE_MASK 0x80u
+#define UART0_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART0_BDL_SBR_MASK 0xFFu
+#define UART0_BDL_SBR_SHIFT 0
+#define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART0_C1_PT_MASK 0x1u
+#define UART0_C1_PT_SHIFT 0
+#define UART0_C1_PE_MASK 0x2u
+#define UART0_C1_PE_SHIFT 1
+#define UART0_C1_ILT_MASK 0x4u
+#define UART0_C1_ILT_SHIFT 2
+#define UART0_C1_WAKE_MASK 0x8u
+#define UART0_C1_WAKE_SHIFT 3
+#define UART0_C1_M_MASK 0x10u
+#define UART0_C1_M_SHIFT 4
+#define UART0_C1_RSRC_MASK 0x20u
+#define UART0_C1_RSRC_SHIFT 5
+#define UART0_C1_DOZEEN_MASK 0x40u
+#define UART0_C1_DOZEEN_SHIFT 6
+#define UART0_C1_LOOPS_MASK 0x80u
+#define UART0_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART0_C2_SBK_MASK 0x1u
+#define UART0_C2_SBK_SHIFT 0
+#define UART0_C2_RWU_MASK 0x2u
+#define UART0_C2_RWU_SHIFT 1
+#define UART0_C2_RE_MASK 0x4u
+#define UART0_C2_RE_SHIFT 2
+#define UART0_C2_TE_MASK 0x8u
+#define UART0_C2_TE_SHIFT 3
+#define UART0_C2_ILIE_MASK 0x10u
+#define UART0_C2_ILIE_SHIFT 4
+#define UART0_C2_RIE_MASK 0x20u
+#define UART0_C2_RIE_SHIFT 5
+#define UART0_C2_TCIE_MASK 0x40u
+#define UART0_C2_TCIE_SHIFT 6
+#define UART0_C2_TIE_MASK 0x80u
+#define UART0_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART0_S1_PF_MASK 0x1u
+#define UART0_S1_PF_SHIFT 0
+#define UART0_S1_FE_MASK 0x2u
+#define UART0_S1_FE_SHIFT 1
+#define UART0_S1_NF_MASK 0x4u
+#define UART0_S1_NF_SHIFT 2
+#define UART0_S1_OR_MASK 0x8u
+#define UART0_S1_OR_SHIFT 3
+#define UART0_S1_IDLE_MASK 0x10u
+#define UART0_S1_IDLE_SHIFT 4
+#define UART0_S1_RDRF_MASK 0x20u
+#define UART0_S1_RDRF_SHIFT 5
+#define UART0_S1_TC_MASK 0x40u
+#define UART0_S1_TC_SHIFT 6
+#define UART0_S1_TDRE_MASK 0x80u
+#define UART0_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART0_S2_RAF_MASK 0x1u
+#define UART0_S2_RAF_SHIFT 0
+#define UART0_S2_LBKDE_MASK 0x2u
+#define UART0_S2_LBKDE_SHIFT 1
+#define UART0_S2_BRK13_MASK 0x4u
+#define UART0_S2_BRK13_SHIFT 2
+#define UART0_S2_RWUID_MASK 0x8u
+#define UART0_S2_RWUID_SHIFT 3
+#define UART0_S2_RXINV_MASK 0x10u
+#define UART0_S2_RXINV_SHIFT 4
+#define UART0_S2_MSBF_MASK 0x20u
+#define UART0_S2_MSBF_SHIFT 5
+#define UART0_S2_RXEDGIF_MASK 0x40u
+#define UART0_S2_RXEDGIF_SHIFT 6
+#define UART0_S2_LBKDIF_MASK 0x80u
+#define UART0_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART0_C3_PEIE_MASK 0x1u
+#define UART0_C3_PEIE_SHIFT 0
+#define UART0_C3_FEIE_MASK 0x2u
+#define UART0_C3_FEIE_SHIFT 1
+#define UART0_C3_NEIE_MASK 0x4u
+#define UART0_C3_NEIE_SHIFT 2
+#define UART0_C3_ORIE_MASK 0x8u
+#define UART0_C3_ORIE_SHIFT 3
+#define UART0_C3_TXINV_MASK 0x10u
+#define UART0_C3_TXINV_SHIFT 4
+#define UART0_C3_TXDIR_MASK 0x20u
+#define UART0_C3_TXDIR_SHIFT 5
+#define UART0_C3_R9T8_MASK 0x40u
+#define UART0_C3_R9T8_SHIFT 6
+#define UART0_C3_R8T9_MASK 0x80u
+#define UART0_C3_R8T9_SHIFT 7
+/* D Bit Fields */
+#define UART0_D_R0T0_MASK 0x1u
+#define UART0_D_R0T0_SHIFT 0
+#define UART0_D_R1T1_MASK 0x2u
+#define UART0_D_R1T1_SHIFT 1
+#define UART0_D_R2T2_MASK 0x4u
+#define UART0_D_R2T2_SHIFT 2
+#define UART0_D_R3T3_MASK 0x8u
+#define UART0_D_R3T3_SHIFT 3
+#define UART0_D_R4T4_MASK 0x10u
+#define UART0_D_R4T4_SHIFT 4
+#define UART0_D_R5T5_MASK 0x20u
+#define UART0_D_R5T5_SHIFT 5
+#define UART0_D_R6T6_MASK 0x40u
+#define UART0_D_R6T6_SHIFT 6
+#define UART0_D_R7T7_MASK 0x80u
+#define UART0_D_R7T7_SHIFT 7
+/* MA1 Bit Fields */
+#define UART0_MA1_MA_MASK 0xFFu
+#define UART0_MA1_MA_SHIFT 0
+#define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART0_MA2_MA_MASK 0xFFu
+#define UART0_MA2_MA_SHIFT 0
+#define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART0_C4_OSR_MASK 0x1Fu
+#define UART0_C4_OSR_SHIFT 0
+#define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
+#define UART0_C4_M10_MASK 0x20u
+#define UART0_C4_M10_SHIFT 5
+#define UART0_C4_MAEN2_MASK 0x40u
+#define UART0_C4_MAEN2_SHIFT 6
+#define UART0_C4_MAEN1_MASK 0x80u
+#define UART0_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UART0_C5_RESYNCDIS_MASK 0x1u
+#define UART0_C5_RESYNCDIS_SHIFT 0
+#define UART0_C5_BOTHEDGE_MASK 0x2u
+#define UART0_C5_BOTHEDGE_SHIFT 1
+#define UART0_C5_RDMAE_MASK 0x20u
+#define UART0_C5_RDMAE_SHIFT 5
+#define UART0_C5_TDMAE_MASK 0x80u
+#define UART0_C5_TDMAE_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group UART0_Register_Masks */
+
+
+/* UART0 - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART0_Type *)UART0_BASE)
+/** Array initializer of UART0 peripheral base pointers */
+#define UART0_BASES { UART0 }
+
+/**
+ * @}
+ */ /* end of group UART0_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/**
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define DMA_REQC_ARR_DMAC_MASK This_symbol_has_been_deprecated
+#define DMA_REQC_ARR_DMAC_SHIFT This_symbol_has_been_deprecated
+#define DMA_REQC_ARR_DMAC(x) This_symbol_has_been_deprecated
+#define DMA_REQC_ARR_CFSM_MASK This_symbol_has_been_deprecated
+#define DMA_REQC_ARR_CFSM_SHIFT This_symbol_has_been_deprecated
+#define DMA_REQC0 This_symbol_has_been_deprecated
+#define DMA_REQC1 This_symbol_has_been_deprecated
+#define DMA_REQC2 This_symbol_has_been_deprecated
+#define DMA_REQC3 This_symbol_has_been_deprecated
+#define MCG_C6_CME0_MASK MCG_C6_CME_MASK
+#define MCG_C6_CME0_SHIFT MCG_C6_CME_SHIFT
+#define MCM_MATCR_ATC0_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC0_SHIFT This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC0(x) This_symbol_has_been_deprecated
+#define MCM_MATCR_RO0_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_RO0_SHIFT This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC1_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC1_SHIFT This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC1(x) This_symbol_has_been_deprecated
+#define MCM_MATCR_RO1_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_RO1_SHIFT This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC2_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC2_SHIFT This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC2(x) This_symbol_has_been_deprecated
+#define MCM_MATCR_RO2_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_RO2_SHIFT This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC3_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC3_SHIFT This_symbol_has_been_deprecated
+#define MCM_MATCR_ATC3(x) This_symbol_has_been_deprecated
+#define MCM_MATCR_RO3_MASK This_symbol_has_been_deprecated
+#define MCM_MATCR_RO3_SHIFT This_symbol_has_been_deprecated
+#define SIM_FCFG2_MAXADDR_MASK SIM_FCFG2_MAXADDR0_MASK
+#define SIM_FCFG2_MAXADDR_SHIFT SIM_FCFG2_MAXADDR0_SHIFT
+#define SIM_FCFG2_MAXADDR SIM_FCFG2_MAXADDR0
+#define SPI_C2_SPLPIE_MASK This_symbol_has_been_deprecated
+#define SPI_C2_SPLPIE_SHIFT This_symbol_has_been_deprecated
+#define UARTLP_Type UART0_Type
+#define UARTLP_BDH_REG UART0_BDH_REG
+#define UARTLP_BDL_REG UART0_BDL_REG
+#define UARTLP_C1_REG UART0_C1_REG
+#define UARTLP_C2_REG UART0_C2_REG
+#define UARTLP_S1_REG UART0_S1_REG
+#define UARTLP_S2_REG UART0_S2_REG
+#define UARTLP_C3_REG UART0_C3_REG
+#define UARTLP_D_REG UART0_D_REG
+#define UARTLP_MA1_REG UART0_MA1_REG
+#define UARTLP_MA2_REG UART0_MA2_REG
+#define UARTLP_C4_REG UART0_C4_REG
+#define UARTLP_C5_REG UART0_C5_REG
+#define UARTLP_BDH_SBR_MASK UART0_BDH_SBR_MASK
+#define UARTLP_BDH_SBR_SHIFT UART0_BDH_SBR_SHIFT
+#define UARTLP_BDH_SBR(x) UART0_BDH_SBR(x)
+#define UARTLP_BDH_SBNS_MASK UART0_BDH_SBNS_MASK
+#define UARTLP_BDH_SBNS_SHIFT UART0_BDH_SBNS_SHIFT
+#define UARTLP_BDH_RXEDGIE_MASK UART0_BDH_RXEDGIE_MASK
+#define UARTLP_BDH_RXEDGIE_SHIFT UART0_BDH_RXEDGIE_SHIFT
+#define UARTLP_BDH_LBKDIE_MASK UART0_BDH_LBKDIE_MASK
+#define UARTLP_BDH_LBKDIE_SHIFT UART0_BDH_LBKDIE_SHIFT
+#define UARTLP_BDL_SBR_MASK UART0_BDL_SBR_MASK
+#define UARTLP_BDL_SBR_SHIFT UART0_BDL_SBR_SHIFT
+#define UARTLP_BDL_SBR(x) UART0_BDL_SBR(x)
+#define UARTLP_C1_PT_MASK UART0_C1_PT_MASK
+#define UARTLP_C1_PT_SHIFT UART0_C1_PT_SHIFT
+#define UARTLP_C1_PE_MASK UART0_C1_PE_MASK
+#define UARTLP_C1_PE_SHIFT UART0_C1_PE_SHIFT
+#define UARTLP_C1_ILT_MASK UART0_C1_ILT_MASK
+#define UARTLP_C1_ILT_SHIFT UART0_C1_ILT_SHIFT
+#define UARTLP_C1_WAKE_MASK UART0_C1_WAKE_MASK
+#define UARTLP_C1_WAKE_SHIFT UART0_C1_WAKE_SHIFT
+#define UARTLP_C1_M_MASK UART0_C1_M_MASK
+#define UARTLP_C1_M_SHIFT UART0_C1_M_SHIFT
+#define UARTLP_C1_RSRC_MASK UART0_C1_RSRC_MASK
+#define UARTLP_C1_RSRC_SHIFT UART0_C1_RSRC_SHIFT
+#define UARTLP_C1_DOZEEN_MASK UART0_C1_DOZEEN_MASK
+#define UARTLP_C1_DOZEEN_SHIFT UART0_C1_DOZEEN_SHIFT
+#define UARTLP_C1_LOOPS_MASK UART0_C1_LOOPS_MASK
+#define UARTLP_C1_LOOPS_SHIFT UART0_C1_LOOPS_SHIFT
+#define UARTLP_C2_SBK_MASK UART0_C2_SBK_MASK
+#define UARTLP_C2_SBK_SHIFT UART0_C2_SBK_SHIFT
+#define UARTLP_C2_RWU_MASK UART0_C2_RWU_MASK
+#define UARTLP_C2_RWU_SHIFT UART0_C2_RWU_SHIFT
+#define UARTLP_C2_RE_MASK UART0_C2_RE_MASK
+#define UARTLP_C2_RE_SHIFT UART0_C2_RE_SHIFT
+#define UARTLP_C2_TE_MASK UART0_C2_TE_MASK
+#define UARTLP_C2_TE_SHIFT UART0_C2_TE_SHIFT
+#define UARTLP_C2_ILIE_MASK UART0_C2_ILIE_MASK
+#define UARTLP_C2_ILIE_SHIFT UART0_C2_ILIE_SHIFT
+#define UARTLP_C2_RIE_MASK UART0_C2_RIE_MASK
+#define UARTLP_C2_RIE_SHIFT UART0_C2_RIE_SHIFT
+#define UARTLP_C2_TCIE_MASK UART0_C2_TCIE_MASK
+#define UARTLP_C2_TCIE_SHIFT UART0_C2_TCIE_SHIFT
+#define UARTLP_C2_TIE_MASK UART0_C2_TIE_MASK
+#define UARTLP_C2_TIE_SHIFT UART0_C2_TIE_SHIFT
+#define UARTLP_S1_PF_MASK UART0_S1_PF_MASK
+#define UARTLP_S1_PF_SHIFT UART0_S1_PF_SHIFT
+#define UARTLP_S1_FE_MASK UART0_S1_FE_MASK
+#define UARTLP_S1_FE_SHIFT UART0_S1_FE_SHIFT
+#define UARTLP_S1_NF_MASK UART0_S1_NF_MASK
+#define UARTLP_S1_NF_SHIFT UART0_S1_NF_SHIFT
+#define UARTLP_S1_OR_MASK UART0_S1_OR_MASK
+#define UARTLP_S1_OR_SHIFT UART0_S1_OR_SHIFT
+#define UARTLP_S1_IDLE_MASK UART0_S1_IDLE_MASK
+#define UARTLP_S1_IDLE_SHIFT UART0_S1_IDLE_SHIFT
+#define UARTLP_S1_RDRF_MASK UART0_S1_RDRF_MASK
+#define UARTLP_S1_RDRF_SHIFT UART0_S1_RDRF_SHIFT
+#define UARTLP_S1_TC_MASK UART0_S1_TC_MASK
+#define UARTLP_S1_TC_SHIFT UART0_S1_TC_SHIFT
+#define UARTLP_S1_TDRE_MASK UART0_S1_TDRE_MASK
+#define UARTLP_S1_TDRE_SHIFT UART0_S1_TDRE_SHIFT
+#define UARTLP_S2_RAF_MASK UART0_S2_RAF_MASK
+#define UARTLP_S2_RAF_SHIFT UART0_S2_RAF_SHIFT
+#define UARTLP_S2_LBKDE_MASK UART0_S2_LBKDE_MASK
+#define UARTLP_S2_LBKDE_SHIFT UART0_S2_LBKDE_SHIFT
+#define UARTLP_S2_BRK13_MASK UART0_S2_BRK13_MASK
+#define UARTLP_S2_BRK13_SHIFT UART0_S2_BRK13_SHIFT
+#define UARTLP_S2_RWUID_MASK UART0_S2_RWUID_MASK
+#define UARTLP_S2_RWUID_SHIFT UART0_S2_RWUID_SHIFT
+#define UARTLP_S2_RXINV_MASK UART0_S2_RXINV_MASK
+#define UARTLP_S2_RXINV_SHIFT UART0_S2_RXINV_SHIFT
+#define UARTLP_S2_MSBF_MASK UART0_S2_MSBF_MASK
+#define UARTLP_S2_MSBF_SHIFT UART0_S2_MSBF_SHIFT
+#define UARTLP_S2_RXEDGIF_MASK UART0_S2_RXEDGIF_MASK
+#define UARTLP_S2_RXEDGIF_SHIFT UART0_S2_RXEDGIF_SHIFT
+#define UARTLP_S2_LBKDIF_MASK UART0_S2_LBKDIF_MASK
+#define UARTLP_S2_LBKDIF_SHIFT UART0_S2_LBKDIF_SHIFT
+#define UARTLP_C3_PEIE_MASK UART0_C3_PEIE_MASK
+#define UARTLP_C3_PEIE_SHIFT UART0_C3_PEIE_SHIFT
+#define UARTLP_C3_FEIE_MASK UART0_C3_FEIE_MASK
+#define UARTLP_C3_FEIE_SHIFT UART0_C3_FEIE_SHIFT
+#define UARTLP_C3_NEIE_MASK UART0_C3_NEIE_MASK
+#define UARTLP_C3_NEIE_SHIFT UART0_C3_NEIE_SHIFT
+#define UARTLP_C3_ORIE_MASK UART0_C3_ORIE_MASK
+#define UARTLP_C3_ORIE_SHIFT UART0_C3_ORIE_SHIFT
+#define UARTLP_C3_TXINV_MASK UART0_C3_TXINV_MASK
+#define UARTLP_C3_TXINV_SHIFT UART0_C3_TXINV_SHIFT
+#define UARTLP_C3_TXDIR_MASK UART0_C3_TXDIR_MASK
+#define UARTLP_C3_TXDIR_SHIFT UART0_C3_TXDIR_SHIFT
+#define UARTLP_C3_R9T8_MASK UART0_C3_R9T8_MASK
+#define UARTLP_C3_R9T8_SHIFT UART0_C3_R9T8_SHIFT
+#define UARTLP_C3_R8T9_MASK UART0_C3_R8T9_MASK
+#define UARTLP_C3_R8T9_SHIFT UART0_C3_R8T9_SHIFT
+#define UARTLP_D_R0T0_MASK UART0_D_R0T0_MASK
+#define UARTLP_D_R0T0_SHIFT UART0_D_R0T0_SHIFT
+#define UARTLP_D_R1T1_MASK UART0_D_R1T1_MASK
+#define UARTLP_D_R1T1_SHIFT UART0_D_R1T1_SHIFT
+#define UARTLP_D_R2T2_MASK UART0_D_R2T2_MASK
+#define UARTLP_D_R2T2_SHIFT UART0_D_R2T2_SHIFT
+#define UARTLP_D_R3T3_MASK UART0_D_R3T3_MASK
+#define UARTLP_D_R3T3_SHIFT UART0_D_R3T3_SHIFT
+#define UARTLP_D_R4T4_MASK UART0_D_R4T4_MASK
+#define UARTLP_D_R4T4_SHIFT UART0_D_R4T4_SHIFT
+#define UARTLP_D_R5T5_MASK UART0_D_R5T5_MASK
+#define UARTLP_D_R5T5_SHIFT UART0_D_R5T5_SHIFT
+#define UARTLP_D_R6T6_MASK UART0_D_R6T6_MASK
+#define UARTLP_D_R6T6_SHIFT UART0_D_R6T6_SHIFT
+#define UARTLP_D_R7T7_MASK UART0_D_R7T7_MASK
+#define UARTLP_D_R7T7_SHIFT UART0_D_R7T7_SHIFT
+#define UARTLP_MA1_MA_MASK UART0_MA1_MA_MASK
+#define UARTLP_MA1_MA_SHIFT UART0_MA1_MA_SHIFT
+#define UARTLP_MA1_MA(x) UART0_MA1_MA(x)
+#define UARTLP_MA2_MA_MASK UART0_MA2_MA_MASK
+#define UARTLP_MA2_MA_SHIFT UART0_MA2_MA_SHIFT
+#define UARTLP_MA2_MA(x) UART0_MA2_MA(x)
+#define UARTLP_C4_OSR_MASK UART0_C4_OSR_MASK
+#define UARTLP_C4_OSR_SHIFT UART0_C4_OSR_SHIFT
+#define UARTLP_C4_OSR(x) UART0_C4_OSR(x)
+#define UARTLP_C4_M10_MASK UART0_C4_M10_MASK
+#define UARTLP_C4_M10_SHIFT UART0_C4_M10_SHIFT
+#define UARTLP_C4_MAEN2_MASK UART0_C4_MAEN2_MASK
+#define UARTLP_C4_MAEN2_SHIFT UART0_C4_MAEN2_SHIFT
+#define UARTLP_C4_MAEN1_MASK UART0_C4_MAEN1_MASK
+#define UARTLP_C4_MAEN1_SHIFT UART0_C4_MAEN1_SHIFT
+#define UARTLP_C5_RESYNCDIS_MASK UART0_C5_RESYNCDIS_MASK
+#define UARTLP_C5_RESYNCDIS_SHIFT UART0_C5_RESYNCDIS_SHIFT
+#define UARTLP_C5_BOTHEDGE_MASK UART0_C5_BOTHEDGE_MASK
+#define UARTLP_C5_BOTHEDGE_SHIFT UART0_C5_BOTHEDGE_SHIFT
+#define UARTLP_C5_RDMAE_MASK UART0_C5_RDMAE_MASK
+#define UARTLP_C5_RDMAE_SHIFT UART0_C5_RDMAE_SHIFT
+#define UARTLP_C5_TDMAE_MASK UART0_C5_TDMAE_MASK
+#define UARTLP_C5_TDMAE_SHIFT UART0_C5_TDMAE_SHIFT
+#define UARTLP_BASES UARTLP_BASES
+
+/**
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#endif /* #if !defined(MKL05Z4_H_) */
+
+/* MKL05Z4.h, eof. */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/MKL05Z4.sct b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/MKL05Z4.sct
new file mode 100644
index 000000000..1afd9a9dc
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/MKL05Z4.sct
@@ -0,0 +1,12 @@
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 0x1000 - 0xC0 = 0xF40
+ RW_IRAM1 0x1FFFFCC0 0xF40 {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/startup_MKL05Z4.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/startup_MKL05Z4.s
new file mode 100644
index 000000000..0e8a17c57
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/startup_MKL05Z4.s
@@ -0,0 +1,348 @@
+;/*****************************************************************************
+; * @file: startup_MKL25Z4.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; * MKL05Z4
+; * @version: 1.1
+; * @date: 2012-6-21
+; *
+; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20000C00 ; Top of RAM
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
+ DCD Reserved20_IRQHandler ; Reserved interrupt 20
+ DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD Reserved_25_IRQHandler ; Reserved interrupt 25
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD Reserved_27_IRQHandler ; Reserved interrupt 27
+ DCD UART0_IRQHandler ; UART0 status and error interrupt
+ DCD Reserved_29_IRQHandler ; Reserved interrupt 29
+ DCD Reserved_30_IRQHandler ; Reserved interrupt 30
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
+ DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
+ DCD Reserved_35_IRQHandler ; Reserved interrupt 35
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT_IRQHandler ; PIT timer channel 0 interrupt
+ DCD Reserved_39_IRQHandler ; Reserved interrupt 39
+ DCD Reserved_40_IRQHandler ; Reserved interrupt 40
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD Reserved_45_IRQHandler ; Reserved interrupt 45
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTB_IRQHandler ; Port B interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT0
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
+; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
+; <o.4> LPBOOT1
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
+; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
+; <o.2> NMI_DIS
+; <0=> NMI interrupts are always blocked
+; <1=> NMI pin/interrupts reset default to enabled
+; <o.3> RESET_PIN_CFG
+; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
+; <1=> RESET pin is dedicated
+; <o.3> FAST_INIT
+; <0=> Slower initialization
+; <1=> Fast Initialization
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT Reserved20_IRQHandler [WEAK]
+ EXPORT FTFA_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT Reserved_25_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT Reserved_27_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT Reserved_29_IRQHandler [WEAK]
+ EXPORT Reserved_30_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT TPM0_IRQHandler [WEAK]
+ EXPORT TPM1_IRQHandler [WEAK]
+ EXPORT Reserved_35_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT_IRQHandler [WEAK]
+ EXPORT Reserved_39_IRQHandler [WEAK]
+ EXPORT Reserved_40_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT Reserved_45_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTB_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+Reserved_25_IRQHandler
+SPI0_IRQHandler
+Reserved_27_IRQHandler
+UART0_IRQHandler
+Reserved_29_IRQHandler
+Reserved_30_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+Reserved_35_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+Reserved_39_IRQHandler
+Reserved_40_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+Reserved_45_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/sys.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/MKL05Z4.sct b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/MKL05Z4.sct
new file mode 100644
index 000000000..1afd9a9dc
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/MKL05Z4.sct
@@ -0,0 +1,12 @@
+LR_IROM1 0x00000000 0x8000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x8000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 0x1000 - 0xC0 = 0xF40
+ RW_IRAM1 0x1FFFFCC0 0xF40 {
+ .ANY (+RW +ZI)
+ }
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/startup_MKL05Z4.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/startup_MKL05Z4.s
new file mode 100644
index 000000000..2fbfad033
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/startup_MKL05Z4.s
@@ -0,0 +1,332 @@
+;/*****************************************************************************
+; * @file: startup_MKL25Z4.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; * MKL05Z4
+; * @version: 1.1
+; * @date: 2012-6-21
+; *
+; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20000C00 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
+ DCD Reserved20_IRQHandler ; Reserved interrupt 20
+ DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD Reserved_25_IRQHandler ; Reserved interrupt 25
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD Reserved_27_IRQHandler ; Reserved interrupt 27
+ DCD UART0_IRQHandler ; UART0 status and error interrupt
+ DCD Reserved_29_IRQHandler ; Reserved interrupt 29
+ DCD Reserved_30_IRQHandler ; Reserved interrupt 30
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
+ DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
+ DCD Reserved_35_IRQHandler ; Reserved interrupt 35
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT_IRQHandler ; PIT timer channel 0 interrupt
+ DCD Reserved_39_IRQHandler ; Reserved interrupt 39
+ DCD Reserved_40_IRQHandler ; Reserved interrupt 40
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD Reserved_45_IRQHandler ; Reserved interrupt 45
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTB_IRQHandler ; Port B interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT0
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
+; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
+; <o.4> LPBOOT1
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
+; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
+; <o.2> NMI_DIS
+; <0=> NMI interrupts are always blocked
+; <1=> NMI pin/interrupts reset default to enabled
+; <o.3> RESET_PIN_CFG
+; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
+; <1=> RESET pin is dedicated
+; <o.3> FAST_INIT
+; <0=> Slower initialization
+; <1=> Fast Initialization
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT Reserved20_IRQHandler [WEAK]
+ EXPORT FTFA_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT Reserved_25_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT Reserved_27_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT Reserved_29_IRQHandler [WEAK]
+ EXPORT Reserved_30_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT TPM0_IRQHandler [WEAK]
+ EXPORT TPM1_IRQHandler [WEAK]
+ EXPORT Reserved_35_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT_IRQHandler [WEAK]
+ EXPORT Reserved_39_IRQHandler [WEAK]
+ EXPORT Reserved_40_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT Reserved_45_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTB_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+Reserved_25_IRQHandler
+SPI0_IRQHandler
+Reserved_27_IRQHandler
+UART0_IRQHandler
+Reserved_29_IRQHandler
+Reserved_30_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+Reserved_35_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+Reserved_39_IRQHandler
+Reserved_40_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+Reserved_45_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/sys.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/MKL05Z4.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/MKL05Z4.ld
new file mode 100644
index 000000000..65eba85be
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/MKL05Z4.ld
@@ -0,0 +1,154 @@
+/*
+ * KL05Z ARM GCC linker script file, Martin Kojtal (0xc0170)
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000410
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 32K - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFFFCC0, LENGTH = 4K - 0xC0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ . = ALIGN(4);
+ } > VECTORS
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/startup_MKL05Z4.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/startup_MKL05Z4.s
new file mode 100644
index 000000000..384c489e2
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_GCC_ARM/startup_MKL05Z4.s
@@ -0,0 +1,225 @@
+/* KL05Z startup ARM GCC, Martin Kojtal (0xc0170)
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x80
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x80
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vector_table,"a",%progbits
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
+ .long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
+ .long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
+ .long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
+ .long Default_Handler /* Reserved interrupt 20 */
+ .long FTFA_IRQHandler /* FTFA interrupt */
+ .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
+ .long LLW_IRQHandler /* Low Leakage Wakeup */
+ .long I2C0_IRQHandler /* I2C0 interrupt */
+ .long Default_Handler /* Reserved interrupt 25 */
+ .long SPI0_IRQHandler /* SPI0 interrupt */
+ .long Default_Handler /* Reserved interrupt 27 */
+ .long UART0_IRQHandler /* UART0 status/error interrupt */
+ .long Default_Handler /* Reserved interrupt 29 */
+ .long Default_Handler /* Reserved interrupt 30 */
+ .long ADC0_IRQHandler /* ADC0 interrupt */
+ .long CMP0_IRQHandler /* CMP0 interrupt */
+ .long TPM0_IRQHandler /* TPM0 fault, overflow and channels interrupt */
+ .long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt */
+ .long Default_Handler /* Reserved interrupt 35 */
+ .long RTC_IRQHandler /* RTC interrupt */
+ .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
+ .long PIT_IRQHandler /* PIT timer interrupt */
+ .long Default_Handler /* Reserved interrupt 39 */
+ .long Default_Handler /* Reserved interrupt 40 */
+ .long DAC0_IRQHandler /* DAC interrupt */
+ .long TSI0_IRQHandler /* TSI0 interrupt */
+ .long MCG_IRQHandler /* MCG interrupt */
+ .long LPTimer_IRQHandler /* LPTimer interrupt */
+ .long Default_Handler /* Reserved interrupt 45 */
+ .long PORTA_IRQHandler /* Port A interrupt */
+ .long PORTB_IRQHandler /* Port B interrupt */
+
+ .size __isr_vector, . - __isr_vector
+ .org 0x400, 0xff
+
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xfffffffe
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .flash_to_ram_loop_end
+
+ movs r4, 0
+.flash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .flash_to_ram_loop
+.flash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ def_default_handler DMA0_IRQHandler
+ def_default_handler DMA1_IRQHandler
+ def_default_handler DMA2_IRQHandler
+ def_default_handler DMA3_IRQHandler
+ def_default_handler FTFA_IRQHandler
+ def_default_handler LVD_LVW_IRQHandler
+ def_default_handler LLW_IRQHandler
+ def_default_handler I2C0_IRQHandler
+ def_default_handler SPI0_IRQHandler
+ def_default_handler UART0_IRQHandler
+ def_default_handler ADC0_IRQHandler
+ def_default_handler CMP0_IRQHandler
+ def_default_handler TPM0_IRQHandler
+ def_default_handler TPM1_IRQHandler
+ def_default_handler RTC_IRQHandler
+ def_default_handler RTC_Seconds_IRQHandler
+ def_default_handler PIT_IRQHandler
+ def_default_handler DAC0_IRQHandler
+ def_default_handler TSI0_IRQHandler
+ def_default_handler MCG_IRQHandler
+ def_default_handler LPTimer_IRQHandler
+ def_default_handler PORTA_IRQHandler
+ def_default_handler PORTB_IRQHandler
+
+ .weak DEF_IRQHandler
+ .set DEF_IRQHandler, Default_Handler
+
+ .end
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/MKL05Z4.icf b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/MKL05Z4.icf
new file mode 100644
index 000000000..4bfab3fc1
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/MKL05Z4.icf
@@ -0,0 +1,43 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x00007fff;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x1ffffc00;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x1ffffcbf;
+define symbol __ICFEDIT_region_RAM_start__ = 0x1ffffcc0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x200;
+define symbol __ICFEDIT_size_heap__ = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM2_start__ = 0x20000000;
+define symbol __region_RAM2_end__ = 0x20000bff;
+
+define symbol __FlashConfig_start__ = 0x00000400;
+define symbol __FlashConfig_end__ = 0x0000040f;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in FlashConfig_region {section FlashConfig};
+
+place in ROM_region { readonly };
+
+place in RAM_region { readwrite, block HEAP, block CSTACK };
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/startup_MKL05Z4.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/startup_MKL05Z4.s
new file mode 100644
index 000000000..34b906e4f
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/TOOLCHAIN_IAR/startup_MKL05Z4.s
@@ -0,0 +1,199 @@
+/**************************************************
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 16 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:ROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete intertrupt
+ DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete intertrupt
+ DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete intertrupt
+ DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete intertrupt
+ DCD 0 ; 4: Reserved
+ DCD FTFA_IRQHandler ; 5: FTFA
+ DCD LVD_LVW_IRQHandler ; 6: Low-voltage detect, low-voltage warning
+ DCD LLW_IRQHandler ; 7: Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; 8: IIC 0 interrupt
+ DCD 0 ; 9: Reserved
+ DCD SPI0_IRQHandler ;10: SPI0 intertrupt
+ DCD 0 ;11: Reserved
+ DCD UART0_IRQHandler ;12: UART 0 status and error intertrupt
+ DCD 0 ;13: Reserved
+ DCD 0 ;14: Reserved
+ DCD ADC0_IRQHandler ;15: ADC 0 interrupt
+ DCD CMP0_IRQHandler ;16: CMP 0 interrupt
+ DCD TPM0_IRQHandler ;17: TPM 0 interrupt
+ DCD TPM1_IRQHandler ;18: TPM 1 interrupt
+ DCD 0 ;19: Reserved
+ DCD RTC_IRQHandler ;20: RTC interrupt
+ DCD RTC_Seconds_IRQHandler ;21: RTC Seconds interrupt
+ DCD PIT_IRQHandler ;22: PIT Single interrupt vector for all channels
+ DCD 0 ;23: Reserved
+ DCD 0 ;24: Reserved
+ DCD DAC0_IRQHandler ;25: UART 0 status intertrupt
+ DCD TSI0_IRQHandler ;26: TSI 0 interrupt
+ DCD MCG_IRQHandler ;27: MCG intertrupt
+ DCD LPTimer_IRQHandler ;28: LPTimer interrupt
+ DCD 0 ;29: Reserved
+ DCD PORTA_IRQHandler ;30: PORT A interrupt
+ DCD PORTB_IRQHandler ;31: PORT B interrupt
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;Flash Configuration
+;;16-byte flash configuration field that stores default protection settings (loaded on reset)
+;;and security information that allows the MCU to restrict acces to the FTFL module.
+
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0^0xFF
+
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1^0xFF
+
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2^0xFF
+
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3^0xFF
+
+FOPT EQU 0xFF
+
+FSEC EQU 0xFE
+ SECTION FlashConfig:CONST:REORDER:ROOT(2)
+Config:
+ DATA
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK DMA0_IRQHandler
+ PUBWEAK DMA1_IRQHandler
+ PUBWEAK DMA2_IRQHandler
+ PUBWEAK DMA3_IRQHandler
+ PUBWEAK FTFA_IRQHandler
+ PUBWEAK LVD_LVW_IRQHandler
+ PUBWEAK LLW_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK ADC0_IRQHandler
+ PUBWEAK CMP0_IRQHandler
+ PUBWEAK TPM0_IRQHandler
+ PUBWEAK TPM1_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK RTC_Seconds_IRQHandler
+ PUBWEAK PIT_IRQHandler
+ PUBWEAK DAC0_IRQHandler
+ PUBWEAK TSI0_IRQHandler
+ PUBWEAK MCG_IRQHandler
+ PUBWEAK LPTimer_IRQHandler
+ PUBWEAK PORTA_IRQHandler
+ PUBWEAK PORTB_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler
+HardFault_Handler
+SVC_Handler
+PendSV_Handler
+SysTick_Handler
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+SPI0_IRQHandler
+UART0_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+Default_Handler
+
+ B Default_Handler
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis.h
new file mode 100644
index 000000000..6df5d3792
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in KL05Z specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MKL05Z4.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.c
new file mode 100644
index 000000000..cce960bdf
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFFC00) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.h
new file mode 100644
index 000000000..324e79704
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include "cmsis.h"
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c
new file mode 100644
index 000000000..012d472a7
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c
@@ -0,0 +1,256 @@
+/*
+** ###################################################################
+** Processors: MKL05Z32FK4
+** MKL05Z32LC4
+** MKL05Z32VLF4
+**
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
+** Version: rev. 1.6, 2013-04-11
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2013 Freescale, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-08)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+** - rev. 1.2 (2012-08-01)
+** Device type UARTLP changed to UART0.
+** Missing PORTB_IRQn interrupt number definition added.
+** - rev. 1.3 (2012-10-04)
+** Update according to reference manual rev. 3.
+** - rev. 1.4 (2012-11-22)
+** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
+** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
+** - rev. 1.5 (2013-04-05)
+** Changed start of doxygen comment.
+** - rev. 1.6 (2013-04-11)
+** SystemInit methods updated with predefined initialization sequence.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL05Z4
+ * @version 1.6
+ * @date 2013-04-11
+ * @brief Device specific configuration file for MKL05Z4 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MKL05Z4.h"
+
+#define DISABLE_WDOG 1
+
+#define CLOCK_SETUP 1
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+ Reference clock source for MCG module is the slow internal clock source 32.768kHz
+ Core clock = 41.94MHz, BusClock = 20.97MHz
+ 1 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
+ Reference clock source for MCG module is an external crystal 32.768kHz
+ Core clock = 47.97MHz, BusClock = 23.98MHz
+ 2 ... Multipurpose Clock Generator (MCG) in FLL Bypassed Low Power Internal (BLPI) mode
+ Core clock/Bus clock derived directly from an fast internal 4MHz clock with no multiplication
+ Core clock = 4MHz, BusClock = 4MHz
+*/
+
+/*----------------------------------------------------------------------------
+ Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+ #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+ #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+ #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+ /* Disable the WDOG module */
+ /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
+ SIM->COPC = (uint32_t)0x00u;
+#endif /* (DISABLE_WDOG) */
+#if (CLOCK_SETUP == 0)
+ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
+ /* Switch to FEI Mode */
+ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_CLKS(0x00) |
+ MCG_C1_FRDIV(0x00) |
+ MCG_C1_IREFS_MASK |
+ MCG_C1_IRCLKEN_MASK;
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+ MCG->C2 = MCG_C2_RANGE0(0x00);
+ /* MCG_C4: DMX32=0,DRST_DRS=1 */
+ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
+ MCG_C4_DMX32_MASK |
+ MCG_C4_DRST_DRS(0x02)
+ )) | (uint8_t)(
+ MCG_C4_DRST_DRS(0x01)
+ ));
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = OSC_CR_ERCLKEN_MASK;
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
+ }
+#elif (CLOCK_SETUP == 1)
+ /* SIM->SCGC5: PORTA=1 */
+ SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
+ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
+ /* PORTA->PCR[3]: ISF=0,MUX=0 */
+ PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ /* PORTA->PCR[4]: ISF=0,MUX=0 */
+ PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ /* Switch to FEE Mode */
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+ MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=1,SC8P=1,SC16P=0 */
+ OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC4P_MASK;
+ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
+ /* MCG->C4: DMX32=1,DRST_DRS=1 */
+ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
+ MCG_C4_DRST_DRS(0x02)
+ )) | (uint8_t)(
+ MCG_C4_DMX32_MASK |
+ MCG_C4_DRST_DRS(0x01)
+ ));
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
+ }
+#elif (CLOCK_SETUP == 2)
+ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x00)); /* Update system prescalers */
+ /* MCG->SC: FCRDIV=0 */
+ MCG->SC &= (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x07));
+ /* Switch to FBI Mode */
+ /* MCG->C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = MCG_C1_CLKS(0x01) |
+ MCG_C1_FRDIV(0x00) |
+ MCG_C1_IREFS_MASK |
+ MCG_C1_IRCLKEN_MASK;
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
+ MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK);
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = OSC_CR_ERCLKEN_MASK;
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
+ }
+ /* Switch to BLPI Mode */
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=1 */
+ MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK);
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG->S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the fast external reference clock is selected. */
+ }
+#endif /* (CLOCK_SETUP == 2) */
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint8_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+ /* Output of FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x0u:
+ MCGOUTClock *= 640u;
+ break;
+ case 0x20u:
+ MCGOUTClock *= 1280u;
+ break;
+ case 0x40u:
+ MCGOUTClock *= 1920u;
+ break;
+ case 0x60u:
+ MCGOUTClock *= 2560u;
+ break;
+ case 0x80u:
+ MCGOUTClock *= 732u;
+ break;
+ case 0xA0u:
+ MCGOUTClock *= 1464u;
+ break;
+ case 0xC0u:
+ MCGOUTClock *= 2197u;
+ break;
+ case 0xE0u:
+ MCGOUTClock *= 2929u;
+ break;
+ default:
+ break;
+ }
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.h
new file mode 100644
index 000000000..0fd05f2ea
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.h
@@ -0,0 +1,99 @@
+/*
+** ###################################################################
+** Processors: MKL05Z32FK4
+** MKL05Z32LC4
+** MKL05Z32VLF4
+**
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
+** Version: rev. 1.6, 2013-04-11
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2013 Freescale, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-08)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+** - rev. 1.2 (2012-08-01)
+** Device type UARTLP changed to UART0.
+** Missing PORTB_IRQn interrupt number definition added.
+** - rev. 1.3 (2012-10-04)
+** Update according to reference manual rev. 3.
+** - rev. 1.4 (2012-11-22)
+** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
+** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
+** - rev. 1.5 (2013-04-05)
+** Changed start of doxygen comment.
+** - rev. 1.6 (2013-04-11)
+** SystemInit methods updated with predefined initialization sequence.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL05Z4
+ * @version 1.6
+ * @date 2013-04-11
+ * @brief Device specific configuration file for MKL05Z4 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MKL05Z4_H_
+#define SYSTEM_MKL05Z4_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MKL05Z4_H_) */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/MKL25Z4.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/MKL25Z4.h
new file mode 100644
index 000000000..c54be80e8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/MKL25Z4.h
@@ -0,0 +1,4155 @@
+/*
+** ###################################################################
+** Processor: MKL25Z128VLK4
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL25RM, Rev.1, Jun 2012
+** Version: rev. 1.1, 2012-06-21
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MKL25Z4
+**
+** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-13)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL25Z4.h
+ * @version 1.1
+ * @date 2012-06-21
+ * @brief CMSIS Peripheral Access Layer for MKL25Z4
+ *
+ * CMSIS Peripheral Access Layer for MKL25Z4
+ */
+
+#if !defined(MKL25Z4_H_)
+#define MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0001u
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete interrupt */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete interrupt */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete interrupt */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete interrupt */
+ Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
+ FTFA_IRQn = 5, /**< FTFA interrupt */
+ LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 7, /**< Low Leakage Wakeup */
+ I2C0_IRQn = 8, /**< I2C0 interrupt */
+ I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
+ SPI0_IRQn = 10, /**< SPI0 interrupt */
+ SPI1_IRQn = 11, /**< SPI1 interrupt */
+ UART0_IRQn = 12, /**< UART0 status/error interrupt */
+ UART1_IRQn = 13, /**< UART1 status/error interrupt */
+ UART2_IRQn = 14, /**< UART2 status/error interrupt */
+ ADC0_IRQn = 15, /**< ADC0 interrupt */
+ CMP0_IRQn = 16, /**< CMP0 interrupt */
+ TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
+ TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
+ TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
+ RTC_IRQn = 20, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
+ PIT_IRQn = 22, /**< PIT timer interrupt */
+ Reserved39_IRQn = 23, /**< Reserved interrupt 39 */
+ USB0_IRQn = 24, /**< USB0 interrupt */
+ DAC0_IRQn = 25, /**< DAC interrupt */
+ TSI0_IRQn = 26, /**< TSI0 interrupt */
+ MCG_IRQn = 27, /**< MCG interrupt */
+ LPTimer_IRQn = 28, /**< LPTimer interrupt */
+ Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
+ PORTA_IRQn = 30, /**< Port A interrupt */
+ PORTD_IRQn = 31 /**< Port D interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M0 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h" /* Core Peripheral Access Layer */
+#include "system_MKL25Z4.h" /* Device specific configuration file */
+
+/**
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/**
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASES { ADC0 }
+
+/**
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_TRIGM_MASK 0x20u
+#define CMP_CR1_TRIGM_SHIFT 5
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK 0x40u
+#define CMP_MUXCR_PSTM_SHIFT 6
+
+/**
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASES { CMP0 }
+
+/**
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[2];
+ uint8_t RESERVED_0[28];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x4u
+#define DAC_C1_DACBFMD_SHIFT 2
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0x1u
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFRP_MASK 0x10u
+#define DAC_C2_DACBFRP_SHIFT 4
+
+/**
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASES { DAC0 }
+
+/**
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ __IO uint8_t REQC_ARR[4]; /**< DMA_REQC0 register...DMA_REQC3 register., array offset: 0x0, array step: 0x1 */
+ };
+ uint8_t RESERVED_0[252];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
+ __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
+ union { /* offset: 0x108, array step: 0x10 */
+ __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
+ struct { /* offset: 0x108, array step: 0x10 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
+ } DMA_DSR_ACCESS8BIT;
+ };
+ __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
+ } DMA[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* REQC_ARR Bit Fields */
+#define DMA_REQC_ARR_DMAC_MASK 0xFu
+#define DMA_REQC_ARR_DMAC_SHIFT 0
+#define DMA_REQC_ARR_DMAC(x) (((uint8_t)(((uint8_t)(x))<<DMA_REQC_ARR_DMAC_SHIFT))&DMA_REQC_ARR_DMAC_MASK)
+#define DMA_REQC_ARR_CFSM_MASK 0x80u
+#define DMA_REQC_ARR_CFSM_SHIFT 7
+/* SAR Bit Fields */
+#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
+#define DMA_SAR_SAR_SHIFT 0
+#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
+/* DAR Bit Fields */
+#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
+#define DMA_DAR_DAR_SHIFT 0
+#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
+/* DSR_BCR Bit Fields */
+#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
+#define DMA_DSR_BCR_BCR_SHIFT 0
+#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
+#define DMA_DSR_BCR_DONE_MASK 0x1000000u
+#define DMA_DSR_BCR_DONE_SHIFT 24
+#define DMA_DSR_BCR_BSY_MASK 0x2000000u
+#define DMA_DSR_BCR_BSY_SHIFT 25
+#define DMA_DSR_BCR_REQ_MASK 0x4000000u
+#define DMA_DSR_BCR_REQ_SHIFT 26
+#define DMA_DSR_BCR_BED_MASK 0x10000000u
+#define DMA_DSR_BCR_BED_SHIFT 28
+#define DMA_DSR_BCR_BES_MASK 0x20000000u
+#define DMA_DSR_BCR_BES_SHIFT 29
+#define DMA_DSR_BCR_CE_MASK 0x40000000u
+#define DMA_DSR_BCR_CE_SHIFT 30
+/* DCR Bit Fields */
+#define DMA_DCR_LCH2_MASK 0x3u
+#define DMA_DCR_LCH2_SHIFT 0
+#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
+#define DMA_DCR_LCH1_MASK 0xCu
+#define DMA_DCR_LCH1_SHIFT 2
+#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
+#define DMA_DCR_LINKCC_MASK 0x30u
+#define DMA_DCR_LINKCC_SHIFT 4
+#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
+#define DMA_DCR_D_REQ_MASK 0x80u
+#define DMA_DCR_D_REQ_SHIFT 7
+#define DMA_DCR_DMOD_MASK 0xF00u
+#define DMA_DCR_DMOD_SHIFT 8
+#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
+#define DMA_DCR_SMOD_MASK 0xF000u
+#define DMA_DCR_SMOD_SHIFT 12
+#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
+#define DMA_DCR_START_MASK 0x10000u
+#define DMA_DCR_START_SHIFT 16
+#define DMA_DCR_DSIZE_MASK 0x60000u
+#define DMA_DCR_DSIZE_SHIFT 17
+#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
+#define DMA_DCR_DINC_MASK 0x80000u
+#define DMA_DCR_DINC_SHIFT 19
+#define DMA_DCR_SSIZE_MASK 0x300000u
+#define DMA_DCR_SSIZE_SHIFT 20
+#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
+#define DMA_DCR_SINC_MASK 0x400000u
+#define DMA_DCR_SINC_SHIFT 22
+#define DMA_DCR_EADREQ_MASK 0x800000u
+#define DMA_DCR_EADREQ_SHIFT 23
+#define DMA_DCR_AA_MASK 0x10000000u
+#define DMA_DCR_AA_SHIFT 28
+#define DMA_DCR_CS_MASK 0x20000000u
+#define DMA_DCR_CS_SHIFT 29
+#define DMA_DCR_ERQ_MASK 0x40000000u
+#define DMA_DCR_ERQ_SHIFT 30
+#define DMA_DCR_EINT_MASK 0x80000000u
+#define DMA_DCR_EINT_SHIFT 31
+
+/**
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASES { DMA0 }
+
+/**
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASES { DMAMUX0 }
+
+/**
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define FGPIO_PDOR_PDO_SHIFT 0
+#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define FGPIO_PSOR_PTSO_SHIFT 0
+#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define FGPIO_PCOR_PTCO_SHIFT 0
+#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define FGPIO_PTOR_PTTO_SHIFT 0
+#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define FGPIO_PDIR_PDI_SHIFT 0
+#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define FGPIO_PDDR_PDD_SHIFT 0
+#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FPTA base address */
+#define FPTA_BASE (0xF80FF000u)
+/** Peripheral FPTA base pointer */
+#define FPTA ((FGPIO_Type *)FPTA_BASE)
+/** Peripheral FPTB base address */
+#define FPTB_BASE (0xF80FF040u)
+/** Peripheral FPTB base pointer */
+#define FPTB ((FGPIO_Type *)FPTB_BASE)
+/** Peripheral FPTC base address */
+#define FPTC_BASE (0xF80FF080u)
+/** Peripheral FPTC base pointer */
+#define FPTC ((FGPIO_Type *)FPTC_BASE)
+/** Peripheral FPTD base address */
+#define FPTD_BASE (0xF80FF0C0u)
+/** Peripheral FPTD base pointer */
+#define FPTD ((FGPIO_Type *)FPTD_BASE)
+/** Peripheral FPTE base address */
+#define FPTE_BASE (0xF80FF100u)
+/** Peripheral FPTE base pointer */
+#define FPTE ((FGPIO_Type *)FPTE_BASE)
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
+
+/**
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+} FTFA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFA_FSTAT_MGSTAT0_SHIFT 0
+#define FTFA_FSTAT_FPVIOL_MASK 0x10u
+#define FTFA_FSTAT_FPVIOL_SHIFT 4
+#define FTFA_FSTAT_ACCERR_MASK 0x20u
+#define FTFA_FSTAT_ACCERR_SHIFT 5
+#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFA_FSTAT_RDCOLERR_SHIFT 6
+#define FTFA_FSTAT_CCIF_MASK 0x80u
+#define FTFA_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFA_FCNFG_ERSSUSP_SHIFT 4
+#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFA_FCNFG_ERSAREQ_SHIFT 5
+#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFA_FCNFG_CCIE_MASK 0x80u
+#define FTFA_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFA_FSEC_SEC_MASK 0x3u
+#define FTFA_FSEC_SEC_SHIFT 0
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK 0xCu
+#define FTFA_FSEC_FSLACC_SHIFT 2
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK 0x30u
+#define FTFA_FSEC_MEEN_SHIFT 4
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK 0xC0u
+#define FTFA_FSEC_KEYEN_SHIFT 6
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFA_FOPT_OPT_MASK 0xFFu
+#define FTFA_FOPT_OPT_SHIFT 0
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB3_CCOBn_SHIFT 0
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB2_CCOBn_SHIFT 0
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB1_CCOBn_SHIFT 0
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB0_CCOBn_SHIFT 0
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB7_CCOBn_SHIFT 0
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB6_CCOBn_SHIFT 0
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB5_CCOBn_SHIFT 0
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB4_CCOBn_SHIFT 0
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBB_CCOBn_SHIFT 0
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBA_CCOBn_SHIFT 0
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB9_CCOBn_SHIFT 0
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB8_CCOBn_SHIFT 0
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFA_FPROT3_PROT_MASK 0xFFu
+#define FTFA_FPROT3_PROT_SHIFT 0
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFA_FPROT2_PROT_MASK 0xFFu
+#define FTFA_FPROT2_PROT_SHIFT 0
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFA_FPROT1_PROT_MASK 0xFFu
+#define FTFA_FPROT1_PROT_SHIFT 0
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFA_FPROT0_PROT_MASK 0xFFu
+#define FTFA_FPROT0_PROT_SHIFT 0
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
+
+/**
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA ((FTFA_Type *)FTFA_BASE)
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASES { FTFA }
+
+/**
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/**
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
+
+/**
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0x1Fu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STOPIE_MASK 0x20u
+#define I2C_FLT_STOPIE_SHIFT 5
+#define I2C_FLT_STOPF_MASK 0x40u
+#define I2C_FLT_STOPF_SHIFT 6
+#define I2C_FLT_SHEN_MASK 0x80u
+#define I2C_FLT_SHEN_SHIFT 7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/**
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASES { I2C0, I2C1 }
+
+/**
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASES { LLWU }
+
+/**
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/**
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASES { LPTMR0 }
+
+/**
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+ __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
+ __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS0_MASK 0x4u
+#define MCG_C2_EREFS0_SHIFT 2
+#define MCG_C2_HGO0_MASK 0x8u
+#define MCG_C2_HGO0_SHIFT 3
+#define MCG_C2_RANGE0_MASK 0x30u
+#define MCG_C2_RANGE0_SHIFT 4
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK 0x1Fu
+#define MCG_C5_PRDIV0_SHIFT 0
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK 0x20u
+#define MCG_C5_PLLSTEN0_SHIFT 5
+#define MCG_C5_PLLCLKEN0_MASK 0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT 6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK 0x1Fu
+#define MCG_C6_VDIV0_SHIFT 0
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK 0x20u
+#define MCG_C6_CME0_SHIFT 5
+#define MCG_C6_PLLS_MASK 0x40u
+#define MCG_C6_PLLS_SHIFT 6
+#define MCG_C6_LOLIE0_MASK 0x80u
+#define MCG_C6_LOLIE0_SHIFT 7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+#define MCG_S_PLLST_MASK 0x20u
+#define MCG_S_PLLST_SHIFT 5
+#define MCG_S_LOCK0_MASK 0x40u
+#define MCG_S_LOCK0_SHIFT 6
+#define MCG_S_LOLS_MASK 0x80u
+#define MCG_S_LOLS_SHIFT 7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOLRE_MASK 0x40u
+#define MCG_C8_LOLRE_SHIFT 6
+
+/**
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASES { MCG }
+
+/**
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK 0xFFu
+#define MCM_PLASC_ASC_SHIFT 0
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK 0xFFu
+#define MCM_PLAMC_AMC_SHIFT 0
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_ARB_MASK 0x200u
+#define MCM_PLACR_ARB_SHIFT 9
+#define MCM_PLACR_CFCC_MASK 0x400u
+#define MCM_PLACR_CFCC_SHIFT 10
+#define MCM_PLACR_DFCDA_MASK 0x800u
+#define MCM_PLACR_DFCDA_SHIFT 11
+#define MCM_PLACR_DFCIC_MASK 0x1000u
+#define MCM_PLACR_DFCIC_SHIFT 12
+#define MCM_PLACR_DFCC_MASK 0x2000u
+#define MCM_PLACR_DFCC_SHIFT 13
+#define MCM_PLACR_EFDS_MASK 0x4000u
+#define MCM_PLACR_EFDS_SHIFT 14
+#define MCM_PLACR_DFCS_MASK 0x8000u
+#define MCM_PLACR_DFCS_SHIFT 15
+#define MCM_PLACR_ESFC_MASK 0x10000u
+#define MCM_PLACR_ESFC_SHIFT 16
+/* CPO Bit Fields */
+#define MCM_CPO_CPOREQ_MASK 0x1u
+#define MCM_CPO_CPOREQ_SHIFT 0
+#define MCM_CPO_CPOACK_MASK 0x2u
+#define MCM_CPO_CPOACK_SHIFT 1
+#define MCM_CPO_CPOWOI_MASK 0x4u
+#define MCM_CPO_CPOWOI_SHIFT 2
+
+/**
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASES { MCM }
+
+/**
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
+ __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
+ __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
+ __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
+ uint8_t RESERVED_0[3824];
+ __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
+ uint8_t RESERVED_1[156];
+ __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
+ __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
+ uint8_t RESERVED_2[8];
+ __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
+ __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
+ __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
+ __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
+ uint8_t RESERVED_3[8];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/* POSITION Bit Fields */
+#define MTB_POSITION_WRAP_MASK 0x4u
+#define MTB_POSITION_WRAP_SHIFT 2
+#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
+#define MTB_POSITION_POINTER_SHIFT 3
+#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
+/* MASTER Bit Fields */
+#define MTB_MASTER_MASK_MASK 0x1Fu
+#define MTB_MASTER_MASK_SHIFT 0
+#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK 0x20u
+#define MTB_MASTER_TSTARTEN_SHIFT 5
+#define MTB_MASTER_TSTOPEN_MASK 0x40u
+#define MTB_MASTER_TSTOPEN_SHIFT 6
+#define MTB_MASTER_SFRWPRIV_MASK 0x80u
+#define MTB_MASTER_SFRWPRIV_SHIFT 7
+#define MTB_MASTER_RAMPRIV_MASK 0x100u
+#define MTB_MASTER_RAMPRIV_SHIFT 8
+#define MTB_MASTER_HALTREQ_MASK 0x200u
+#define MTB_MASTER_HALTREQ_SHIFT 9
+#define MTB_MASTER_EN_MASK 0x80000000u
+#define MTB_MASTER_EN_SHIFT 31
+/* FLOW Bit Fields */
+#define MTB_FLOW_AUTOSTOP_MASK 0x1u
+#define MTB_FLOW_AUTOSTOP_SHIFT 0
+#define MTB_FLOW_AUTOHALT_MASK 0x2u
+#define MTB_FLOW_AUTOHALT_SHIFT 1
+#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
+#define MTB_FLOW_WATERMARK_SHIFT 3
+#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
+/* BASE Bit Fields */
+#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
+#define MTB_BASE_BASEADDR_SHIFT 0
+#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
+/* MODECTRL Bit Fields */
+#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
+#define MTB_MODECTRL_MODECTRL_SHIFT 0
+#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
+/* TAGSET Bit Fields */
+#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
+#define MTB_TAGSET_TAGSET_SHIFT 0
+#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
+/* TAGCLEAR Bit Fields */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
+#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
+/* LOCKACCESS Bit Fields */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
+#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
+/* LOCKSTAT Bit Fields */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
+#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
+/* AUTHSTAT Bit Fields */
+#define MTB_AUTHSTAT_BIT0_MASK 0x1u
+#define MTB_AUTHSTAT_BIT0_SHIFT 0
+#define MTB_AUTHSTAT_BIT1_MASK 0x2u
+#define MTB_AUTHSTAT_BIT1_SHIFT 1
+#define MTB_AUTHSTAT_BIT2_MASK 0x4u
+#define MTB_AUTHSTAT_BIT2_SHIFT 2
+#define MTB_AUTHSTAT_BIT3_MASK 0x8u
+#define MTB_AUTHSTAT_BIT3_SHIFT 3
+/* DEVICEARCH Bit Fields */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
+#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
+/* DEVICECFG Bit Fields */
+#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTB_PERIPHID_PERIPHID_SHIFT 0
+#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTB_COMPID_COMPID_SHIFT 0
+#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB ((MTB_Type *)MTB_BASE)
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASES { MTB }
+
+/**
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+ __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ struct { /* offset: 0x20, array step: 0x10 */
+ __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+ __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+ __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } COMPARATOR[2];
+ uint8_t RESERVED_1[448];
+ __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+ uint8_t RESERVED_2[3524];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
+#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
+#define MTBDWT_CTRL_NUMCMP_SHIFT 28
+#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
+/* COMP Bit Fields */
+#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
+#define MTBDWT_COMP_COMP_SHIFT 0
+#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
+/* MASK Bit Fields */
+#define MTBDWT_MASK_MASK_MASK 0x1Fu
+#define MTBDWT_MASK_MASK_SHIFT 0
+#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
+/* FCT Bit Fields */
+#define MTBDWT_FCT_FUNCTION_MASK 0xFu
+#define MTBDWT_FCT_FUNCTION_SHIFT 0
+#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
+#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
+#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
+#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
+#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
+#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
+#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
+#define MTBDWT_FCT_MATCHED_SHIFT 24
+/* TBCTRL Bit Fields */
+#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
+#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
+#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
+#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
+/* DEVICECFG Bit Fields */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
+#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTBDWT_COMPID_COMPID_SHIFT 0
+#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASES { MTBDWT }
+
+/**
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT0_MASK 0x1u
+#define NV_FOPT_LPBOOT0_SHIFT 0
+#define NV_FOPT_NMI_DIS_MASK 0x4u
+#define NV_FOPT_NMI_DIS_SHIFT 2
+#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
+#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
+#define NV_FOPT_LPBOOT1_MASK 0x10u
+#define NV_FOPT_LPBOOT1_SHIFT 4
+#define NV_FOPT_FAST_INIT_MASK 0x20u
+#define NV_FOPT_FAST_INIT_SHIFT 5
+
+/**
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASES { FTFA_FlashConfig }
+
+/**
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASES { OSC0 }
+
+/**
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[220];
+ __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+ __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+ uint8_t RESERVED_1[24];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[2];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LTMR64H Bit Fields */
+#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
+#define PIT_LTMR64H_LTH_SHIFT 0
+#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
+/* LTMR64L Bit Fields */
+#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
+#define PIT_LTMR64L_LTL_SHIFT 0
+#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+#define PIT_TCTRL_CHN_MASK 0x4u
+#define PIT_TCTRL_CHN_SHIFT 2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/**
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASES { PIT }
+
+/**
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+#define PMC_REGSC_BGEN_MASK 0x10u
+#define PMC_REGSC_BGEN_SHIFT 4
+
+/**
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASES { PMC }
+
+/**
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+
+/**
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
+
+/**
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_LOL_MASK 0x8u
+#define RCM_SRS0_LOL_SHIFT 3
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASES { RCM }
+
+/**
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ROM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+ __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
+ __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
+ uint8_t RESERVED_0[4028];
+ __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ROM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/* ENTRY Bit Fields */
+#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
+#define ROM_ENTRY_ENTRY_SHIFT 0
+#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
+/* TABLEMARK Bit Fields */
+#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
+#define ROM_TABLEMARK_MARK_SHIFT 0
+#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
+/* SYSACCESS Bit Fields */
+#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
+#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
+#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
+/* PERIPHID4 Bit Fields */
+#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID4_PERIPHID_SHIFT 0
+#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
+/* PERIPHID5 Bit Fields */
+#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID5_PERIPHID_SHIFT 0
+#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
+/* PERIPHID6 Bit Fields */
+#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID6_PERIPHID_SHIFT 0
+#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
+/* PERIPHID7 Bit Fields */
+#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID7_PERIPHID_SHIFT 0
+#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
+/* PERIPHID0 Bit Fields */
+#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID0_PERIPHID_SHIFT 0
+#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
+/* PERIPHID1 Bit Fields */
+#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID1_PERIPHID_SHIFT 0
+#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
+/* PERIPHID2 Bit Fields */
+#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID2_PERIPHID_SHIFT 0
+#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
+/* PERIPHID3 Bit Fields */
+#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID3_PERIPHID_SHIFT 0
+#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define ROM_COMPID_COMPID_SHIFT 0
+#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
+
+/**
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM ((ROM_Type *)ROM_BASE)
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASES { ROM }
+
+/**
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+#define RTC_IER_WPON_MASK 0x80u
+#define RTC_IER_WPON_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASES { RTC }
+
+/**
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ uint8_t RESERVED_6[4];
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+ uint8_t RESERVED_7[156];
+ __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
+ __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
+#define SIM_SOPT2_TPMSRC_SHIFT 24
+#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
+#define SIM_SOPT2_UART0SRC_SHIFT 26
+#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
+#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
+#define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
+#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
+#define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT 4
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK 0x40u
+#define SIM_SOPT5_UART1RXSRC_SHIFT 6
+#define SIM_SOPT5_UART0ODE_MASK 0x10000u
+#define SIM_SOPT5_UART0ODE_SHIFT 16
+#define SIM_SOPT5_UART1ODE_MASK 0x20000u
+#define SIM_SOPT5_UART1ODE_SHIFT 17
+#define SIM_SOPT5_UART2ODE_MASK 0x40000u
+#define SIM_SOPT5_UART2ODE_SHIFT 18
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_DIEID_MASK 0xF80u
+#define SIM_SDID_DIEID_SHIFT 7
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
+#define SIM_SDID_SRAMSIZE_SHIFT 16
+#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
+#define SIM_SDID_SERIESID_MASK 0xF00000u
+#define SIM_SDID_SERIESID_SHIFT 20
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK 0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT 24
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK 0xF0000000u
+#define SIM_SDID_FAMID_SHIFT 28
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_I2C1_MASK 0x80u
+#define SIM_SCGC4_I2C1_SHIFT 7
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_UART1_MASK 0x800u
+#define SIM_SCGC4_UART1_SHIFT 11
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_USBOTG_MASK 0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT 18
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_SPI0_MASK 0x400000u
+#define SIM_SCGC4_SPI0_SHIFT 22
+#define SIM_SCGC4_SPI1_MASK 0x800000u
+#define SIM_SCGC4_SPI1_SHIFT 23
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK 0x1u
+#define SIM_SCGC5_LPTMR_SHIFT 0
+#define SIM_SCGC5_TSI_MASK 0x20u
+#define SIM_SCGC5_TSI_SHIFT 5
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK 0x1u
+#define SIM_SCGC6_FTF_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_TPM0_MASK 0x1000000u
+#define SIM_SCGC6_TPM0_SHIFT 24
+#define SIM_SCGC6_TPM1_MASK 0x2000000u
+#define SIM_SCGC6_TPM1_SHIFT 25
+#define SIM_SCGC6_TPM2_MASK 0x4000000u
+#define SIM_SCGC6_TPM2_SHIFT 26
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+#define SIM_SCGC6_DAC0_MASK 0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT 31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK 0x100u
+#define SIM_SCGC7_DMA_SHIFT 8
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR_SHIFT 24
+#define SIM_FCFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/* COPC Bit Fields */
+#define SIM_COPC_COPW_MASK 0x1u
+#define SIM_COPC_COPW_SHIFT 0
+#define SIM_COPC_COPCLKS_MASK 0x2u
+#define SIM_COPC_COPCLKS_SHIFT 1
+#define SIM_COPC_COPT_MASK 0xCu
+#define SIM_COPC_COPT_SHIFT 2
+#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
+/* SRVCOP Bit Fields */
+#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
+#define SIM_SRVCOP_SRVCOP_SHIFT 0
+#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
+
+/**
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASES { SIM }
+
+/**
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+/* STOPCTRL Bit Fields */
+#define SMC_STOPCTRL_VLLSM_MASK 0x7u
+#define SMC_STOPCTRL_VLLSM_SHIFT 0
+#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK 0x20u
+#define SMC_STOPCTRL_PORPO_SHIFT 5
+#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
+#define SMC_STOPCTRL_PSTOPO_SHIFT 6
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/**
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASES { SMC }
+
+/**
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< SPI control register 1, offset: 0x0 */
+ __IO uint8_t C2; /**< SPI control register 2, offset: 0x1 */
+ __IO uint8_t BR; /**< SPI baud rate register, offset: 0x2 */
+ __I uint8_t S; /**< SPI status register, offset: 0x3 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t D; /**< SPI data register, offset: 0x5 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t M; /**< SPI match register, offset: 0x7 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define SPI_C1_LSBFE_MASK 0x1u
+#define SPI_C1_LSBFE_SHIFT 0
+#define SPI_C1_SSOE_MASK 0x2u
+#define SPI_C1_SSOE_SHIFT 1
+#define SPI_C1_CPHA_MASK 0x4u
+#define SPI_C1_CPHA_SHIFT 2
+#define SPI_C1_CPOL_MASK 0x8u
+#define SPI_C1_CPOL_SHIFT 3
+#define SPI_C1_MSTR_MASK 0x10u
+#define SPI_C1_MSTR_SHIFT 4
+#define SPI_C1_SPTIE_MASK 0x20u
+#define SPI_C1_SPTIE_SHIFT 5
+#define SPI_C1_SPE_MASK 0x40u
+#define SPI_C1_SPE_SHIFT 6
+#define SPI_C1_SPIE_MASK 0x80u
+#define SPI_C1_SPIE_SHIFT 7
+/* C2 Bit Fields */
+#define SPI_C2_SPC0_MASK 0x1u
+#define SPI_C2_SPC0_SHIFT 0
+#define SPI_C2_SPISWAI_MASK 0x2u
+#define SPI_C2_SPISWAI_SHIFT 1
+#define SPI_C2_RXDMAE_MASK 0x4u
+#define SPI_C2_RXDMAE_SHIFT 2
+#define SPI_C2_BIDIROE_MASK 0x8u
+#define SPI_C2_BIDIROE_SHIFT 3
+#define SPI_C2_MODFEN_MASK 0x10u
+#define SPI_C2_MODFEN_SHIFT 4
+#define SPI_C2_TXDMAE_MASK 0x20u
+#define SPI_C2_TXDMAE_SHIFT 5
+#define SPI_C2_SPLPIE_MASK 0x40u
+#define SPI_C2_SPLPIE_SHIFT 6
+#define SPI_C2_SPMIE_MASK 0x80u
+#define SPI_C2_SPMIE_SHIFT 7
+/* BR Bit Fields */
+#define SPI_BR_SPR_MASK 0xFu
+#define SPI_BR_SPR_SHIFT 0
+#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK 0x70u
+#define SPI_BR_SPPR_SHIFT 4
+#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
+/* S Bit Fields */
+#define SPI_S_MODF_MASK 0x10u
+#define SPI_S_MODF_SHIFT 4
+#define SPI_S_SPTEF_MASK 0x20u
+#define SPI_S_SPTEF_SHIFT 5
+#define SPI_S_SPMF_MASK 0x40u
+#define SPI_S_SPMF_SHIFT 6
+#define SPI_S_SPRF_MASK 0x80u
+#define SPI_S_SPRF_SHIFT 7
+/* D Bit Fields */
+#define SPI_D_Bits_MASK 0xFFu
+#define SPI_D_Bits_SHIFT 0
+#define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
+/* M Bit Fields */
+#define SPI_M_Bits_MASK 0xFFu
+#define SPI_M_Bits_SHIFT 0
+#define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
+
+/**
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x40077000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASES { SPI0, SPI1 }
+
+/**
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[6];
+ uint8_t RESERVED_0[20];
+ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TPM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define TPM_SC_PS_MASK 0x7u
+#define TPM_SC_PS_SHIFT 0
+#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK 0x18u
+#define TPM_SC_CMOD_SHIFT 3
+#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK 0x20u
+#define TPM_SC_CPWMS_SHIFT 5
+#define TPM_SC_TOIE_MASK 0x40u
+#define TPM_SC_TOIE_SHIFT 6
+#define TPM_SC_TOF_MASK 0x80u
+#define TPM_SC_TOF_SHIFT 7
+#define TPM_SC_DMA_MASK 0x100u
+#define TPM_SC_DMA_SHIFT 8
+/* CNT Bit Fields */
+#define TPM_CNT_COUNT_MASK 0xFFFFu
+#define TPM_CNT_COUNT_SHIFT 0
+#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define TPM_MOD_MOD_MASK 0xFFFFu
+#define TPM_MOD_MOD_SHIFT 0
+#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define TPM_CnSC_DMA_MASK 0x1u
+#define TPM_CnSC_DMA_SHIFT 0
+#define TPM_CnSC_ELSA_MASK 0x4u
+#define TPM_CnSC_ELSA_SHIFT 2
+#define TPM_CnSC_ELSB_MASK 0x8u
+#define TPM_CnSC_ELSB_SHIFT 3
+#define TPM_CnSC_MSA_MASK 0x10u
+#define TPM_CnSC_MSA_SHIFT 4
+#define TPM_CnSC_MSB_MASK 0x20u
+#define TPM_CnSC_MSB_SHIFT 5
+#define TPM_CnSC_CHIE_MASK 0x40u
+#define TPM_CnSC_CHIE_SHIFT 6
+#define TPM_CnSC_CHF_MASK 0x80u
+#define TPM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define TPM_CnV_VAL_MASK 0xFFFFu
+#define TPM_CnV_VAL_SHIFT 0
+#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
+/* STATUS Bit Fields */
+#define TPM_STATUS_CH0F_MASK 0x1u
+#define TPM_STATUS_CH0F_SHIFT 0
+#define TPM_STATUS_CH1F_MASK 0x2u
+#define TPM_STATUS_CH1F_SHIFT 1
+#define TPM_STATUS_CH2F_MASK 0x4u
+#define TPM_STATUS_CH2F_SHIFT 2
+#define TPM_STATUS_CH3F_MASK 0x8u
+#define TPM_STATUS_CH3F_SHIFT 3
+#define TPM_STATUS_CH4F_MASK 0x10u
+#define TPM_STATUS_CH4F_SHIFT 4
+#define TPM_STATUS_CH5F_MASK 0x20u
+#define TPM_STATUS_CH5F_SHIFT 5
+#define TPM_STATUS_TOF_MASK 0x100u
+#define TPM_STATUS_TOF_SHIFT 8
+/* CONF Bit Fields */
+#define TPM_CONF_DOZEEN_MASK 0x20u
+#define TPM_CONF_DOZEEN_SHIFT 5
+#define TPM_CONF_DBGMODE_MASK 0xC0u
+#define TPM_CONF_DBGMODE_SHIFT 6
+#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBEEN_MASK 0x200u
+#define TPM_CONF_GTBEEN_SHIFT 9
+#define TPM_CONF_CSOT_MASK 0x10000u
+#define TPM_CONF_CSOT_SHIFT 16
+#define TPM_CONF_CSOO_MASK 0x20000u
+#define TPM_CONF_CSOO_SHIFT 17
+#define TPM_CONF_CROT_MASK 0x40000u
+#define TPM_CONF_CROT_SHIFT 18
+#define TPM_CONF_TRGSEL_MASK 0xF000000u
+#define TPM_CONF_TRGSEL_SHIFT 24
+#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
+
+/**
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0 ((TPM_Type *)TPM0_BASE)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1 ((TPM_Type *)TPM1_BASE)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE (0x4003A000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2 ((TPM_Type *)TPM2_BASE)
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASES { TPM0, TPM1, TPM2 }
+
+/**
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
+ __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
+ __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/* GENCS Bit Fields */
+#define TSI_GENCS_CURSW_MASK 0x2u
+#define TSI_GENCS_CURSW_SHIFT 1
+#define TSI_GENCS_EOSF_MASK 0x4u
+#define TSI_GENCS_EOSF_SHIFT 2
+#define TSI_GENCS_SCNIP_MASK 0x8u
+#define TSI_GENCS_SCNIP_SHIFT 3
+#define TSI_GENCS_STM_MASK 0x10u
+#define TSI_GENCS_STM_SHIFT 4
+#define TSI_GENCS_STPE_MASK 0x20u
+#define TSI_GENCS_STPE_SHIFT 5
+#define TSI_GENCS_TSIIEN_MASK 0x40u
+#define TSI_GENCS_TSIIEN_SHIFT 6
+#define TSI_GENCS_TSIEN_MASK 0x80u
+#define TSI_GENCS_TSIEN_SHIFT 7
+#define TSI_GENCS_NSCN_MASK 0x1F00u
+#define TSI_GENCS_NSCN_SHIFT 8
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_PS_MASK 0xE000u
+#define TSI_GENCS_PS_SHIFT 13
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
+#define TSI_GENCS_EXTCHRG_MASK 0x70000u
+#define TSI_GENCS_EXTCHRG_SHIFT 16
+#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_DVOLT_MASK 0x180000u
+#define TSI_GENCS_DVOLT_SHIFT 19
+#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_REFCHRG_MASK 0xE00000u
+#define TSI_GENCS_REFCHRG_SHIFT 21
+#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_MODE_MASK 0xF000000u
+#define TSI_GENCS_MODE_SHIFT 24
+#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_ESOR_MASK 0x10000000u
+#define TSI_GENCS_ESOR_SHIFT 28
+#define TSI_GENCS_OUTRGF_MASK 0x80000000u
+#define TSI_GENCS_OUTRGF_SHIFT 31
+/* DATA Bit Fields */
+#define TSI_DATA_TSICNT_MASK 0xFFFFu
+#define TSI_DATA_TSICNT_SHIFT 0
+#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_SWTS_MASK 0x400000u
+#define TSI_DATA_SWTS_SHIFT 22
+#define TSI_DATA_DMAEN_MASK 0x800000u
+#define TSI_DATA_DMAEN_SHIFT 23
+#define TSI_DATA_TSICH_MASK 0xF0000000u
+#define TSI_DATA_TSICH_SHIFT 28
+#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
+/* TSHD Bit Fields */
+#define TSI_TSHD_THRESL_MASK 0xFFFFu
+#define TSI_TSHD_THRESL_SHIFT 0
+#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
+#define TSI_TSHD_THRESH_SHIFT 16
+#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
+
+/**
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+/** Array initializer of TSI peripheral base pointers */
+#define TSI_BASES { TSI0 }
+
+/**
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK 0x20u
+#define UART_BDH_SBNS_SHIFT 5
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+#define UART_BDH_LBKDIE_MASK 0x80u
+#define UART_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_UARTSWAI_MASK 0x40u
+#define UART_C1_UARTSWAI_SHIFT 6
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_LBKDE_MASK 0x2u
+#define UART_S2_LBKDE_SHIFT 1
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+#define UART_S2_LBKDIF_MASK 0x80u
+#define UART_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_R0T0_MASK 0x1u
+#define UART_D_R0T0_SHIFT 0
+#define UART_D_R1T1_MASK 0x2u
+#define UART_D_R1T1_SHIFT 1
+#define UART_D_R2T2_MASK 0x4u
+#define UART_D_R2T2_SHIFT 2
+#define UART_D_R3T3_MASK 0x8u
+#define UART_D_R3T3_SHIFT 3
+#define UART_D_R4T4_MASK 0x10u
+#define UART_D_R4T4_SHIFT 4
+#define UART_D_R5T5_MASK 0x20u
+#define UART_D_R5T5_SHIFT 5
+#define UART_D_R6T6_MASK 0x40u
+#define UART_D_R6T6_SHIFT 6
+#define UART_D_R7T7_MASK 0x80u
+#define UART_D_R7T7_SHIFT 7
+/* C4 Bit Fields */
+#define UART_C4_LBKDDMAS_MASK 0x8u
+#define UART_C4_LBKDDMAS_SHIFT 3
+#define UART_C4_ILDMAS_MASK 0x10u
+#define UART_C4_ILDMAS_SHIFT 4
+#define UART_C4_RDMAS_MASK 0x20u
+#define UART_C4_RDMAS_SHIFT 5
+#define UART_C4_TCDMAS_MASK 0x40u
+#define UART_C4_TCDMAS_SHIFT 6
+#define UART_C4_TDMAS_MASK 0x80u
+#define UART_C4_TDMAS_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASES { UART1, UART2 }
+
+/**
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UARTLP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UARTLP_Peripheral_Access_Layer UARTLP Peripheral Access Layer
+ * @{
+ */
+
+/** UARTLP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+} UARTLP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UARTLP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup UARTLP_Register_Masks UARTLP Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UARTLP_BDH_SBR_MASK 0x1Fu
+#define UARTLP_BDH_SBR_SHIFT 0
+#define UARTLP_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDH_SBR_SHIFT))&UARTLP_BDH_SBR_MASK)
+#define UARTLP_BDH_SBNS_MASK 0x20u
+#define UARTLP_BDH_SBNS_SHIFT 5
+#define UARTLP_BDH_RXEDGIE_MASK 0x40u
+#define UARTLP_BDH_RXEDGIE_SHIFT 6
+#define UARTLP_BDH_LBKDIE_MASK 0x80u
+#define UARTLP_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UARTLP_BDL_SBR_MASK 0xFFu
+#define UARTLP_BDL_SBR_SHIFT 0
+#define UARTLP_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDL_SBR_SHIFT))&UARTLP_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UARTLP_C1_PT_MASK 0x1u
+#define UARTLP_C1_PT_SHIFT 0
+#define UARTLP_C1_PE_MASK 0x2u
+#define UARTLP_C1_PE_SHIFT 1
+#define UARTLP_C1_ILT_MASK 0x4u
+#define UARTLP_C1_ILT_SHIFT 2
+#define UARTLP_C1_WAKE_MASK 0x8u
+#define UARTLP_C1_WAKE_SHIFT 3
+#define UARTLP_C1_M_MASK 0x10u
+#define UARTLP_C1_M_SHIFT 4
+#define UARTLP_C1_RSRC_MASK 0x20u
+#define UARTLP_C1_RSRC_SHIFT 5
+#define UARTLP_C1_DOZEEN_MASK 0x40u
+#define UARTLP_C1_DOZEEN_SHIFT 6
+#define UARTLP_C1_LOOPS_MASK 0x80u
+#define UARTLP_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UARTLP_C2_SBK_MASK 0x1u
+#define UARTLP_C2_SBK_SHIFT 0
+#define UARTLP_C2_RWU_MASK 0x2u
+#define UARTLP_C2_RWU_SHIFT 1
+#define UARTLP_C2_RE_MASK 0x4u
+#define UARTLP_C2_RE_SHIFT 2
+#define UARTLP_C2_TE_MASK 0x8u
+#define UARTLP_C2_TE_SHIFT 3
+#define UARTLP_C2_ILIE_MASK 0x10u
+#define UARTLP_C2_ILIE_SHIFT 4
+#define UARTLP_C2_RIE_MASK 0x20u
+#define UARTLP_C2_RIE_SHIFT 5
+#define UARTLP_C2_TCIE_MASK 0x40u
+#define UARTLP_C2_TCIE_SHIFT 6
+#define UARTLP_C2_TIE_MASK 0x80u
+#define UARTLP_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UARTLP_S1_PF_MASK 0x1u
+#define UARTLP_S1_PF_SHIFT 0
+#define UARTLP_S1_FE_MASK 0x2u
+#define UARTLP_S1_FE_SHIFT 1
+#define UARTLP_S1_NF_MASK 0x4u
+#define UARTLP_S1_NF_SHIFT 2
+#define UARTLP_S1_OR_MASK 0x8u
+#define UARTLP_S1_OR_SHIFT 3
+#define UARTLP_S1_IDLE_MASK 0x10u
+#define UARTLP_S1_IDLE_SHIFT 4
+#define UARTLP_S1_RDRF_MASK 0x20u
+#define UARTLP_S1_RDRF_SHIFT 5
+#define UARTLP_S1_TC_MASK 0x40u
+#define UARTLP_S1_TC_SHIFT 6
+#define UARTLP_S1_TDRE_MASK 0x80u
+#define UARTLP_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UARTLP_S2_RAF_MASK 0x1u
+#define UARTLP_S2_RAF_SHIFT 0
+#define UARTLP_S2_LBKDE_MASK 0x2u
+#define UARTLP_S2_LBKDE_SHIFT 1
+#define UARTLP_S2_BRK13_MASK 0x4u
+#define UARTLP_S2_BRK13_SHIFT 2
+#define UARTLP_S2_RWUID_MASK 0x8u
+#define UARTLP_S2_RWUID_SHIFT 3
+#define UARTLP_S2_RXINV_MASK 0x10u
+#define UARTLP_S2_RXINV_SHIFT 4
+#define UARTLP_S2_MSBF_MASK 0x20u
+#define UARTLP_S2_MSBF_SHIFT 5
+#define UARTLP_S2_RXEDGIF_MASK 0x40u
+#define UARTLP_S2_RXEDGIF_SHIFT 6
+#define UARTLP_S2_LBKDIF_MASK 0x80u
+#define UARTLP_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UARTLP_C3_PEIE_MASK 0x1u
+#define UARTLP_C3_PEIE_SHIFT 0
+#define UARTLP_C3_FEIE_MASK 0x2u
+#define UARTLP_C3_FEIE_SHIFT 1
+#define UARTLP_C3_NEIE_MASK 0x4u
+#define UARTLP_C3_NEIE_SHIFT 2
+#define UARTLP_C3_ORIE_MASK 0x8u
+#define UARTLP_C3_ORIE_SHIFT 3
+#define UARTLP_C3_TXINV_MASK 0x10u
+#define UARTLP_C3_TXINV_SHIFT 4
+#define UARTLP_C3_TXDIR_MASK 0x20u
+#define UARTLP_C3_TXDIR_SHIFT 5
+#define UARTLP_C3_R9T8_MASK 0x40u
+#define UARTLP_C3_R9T8_SHIFT 6
+#define UARTLP_C3_R8T9_MASK 0x80u
+#define UARTLP_C3_R8T9_SHIFT 7
+/* D Bit Fields */
+#define UARTLP_D_R0T0_MASK 0x1u
+#define UARTLP_D_R0T0_SHIFT 0
+#define UARTLP_D_R1T1_MASK 0x2u
+#define UARTLP_D_R1T1_SHIFT 1
+#define UARTLP_D_R2T2_MASK 0x4u
+#define UARTLP_D_R2T2_SHIFT 2
+#define UARTLP_D_R3T3_MASK 0x8u
+#define UARTLP_D_R3T3_SHIFT 3
+#define UARTLP_D_R4T4_MASK 0x10u
+#define UARTLP_D_R4T4_SHIFT 4
+#define UARTLP_D_R5T5_MASK 0x20u
+#define UARTLP_D_R5T5_SHIFT 5
+#define UARTLP_D_R6T6_MASK 0x40u
+#define UARTLP_D_R6T6_SHIFT 6
+#define UARTLP_D_R7T7_MASK 0x80u
+#define UARTLP_D_R7T7_SHIFT 7
+/* MA1 Bit Fields */
+#define UARTLP_MA1_MA_MASK 0xFFu
+#define UARTLP_MA1_MA_SHIFT 0
+#define UARTLP_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA1_MA_SHIFT))&UARTLP_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UARTLP_MA2_MA_MASK 0xFFu
+#define UARTLP_MA2_MA_SHIFT 0
+#define UARTLP_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA2_MA_SHIFT))&UARTLP_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UARTLP_C4_OSR_MASK 0x1Fu
+#define UARTLP_C4_OSR_SHIFT 0
+#define UARTLP_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_C4_OSR_SHIFT))&UARTLP_C4_OSR_MASK)
+#define UARTLP_C4_M10_MASK 0x20u
+#define UARTLP_C4_M10_SHIFT 5
+#define UARTLP_C4_MAEN2_MASK 0x40u
+#define UARTLP_C4_MAEN2_SHIFT 6
+#define UARTLP_C4_MAEN1_MASK 0x80u
+#define UARTLP_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UARTLP_C5_RESYNCDIS_MASK 0x1u
+#define UARTLP_C5_RESYNCDIS_SHIFT 0
+#define UARTLP_C5_BOTHEDGE_MASK 0x2u
+#define UARTLP_C5_BOTHEDGE_SHIFT 1
+#define UARTLP_C5_RDMAE_MASK 0x20u
+#define UARTLP_C5_RDMAE_SHIFT 5
+#define UARTLP_C5_TDMAE_MASK 0x80u
+#define UARTLP_C5_TDMAE_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group UARTLP_Register_Masks */
+
+
+/* UARTLP - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UARTLP_Type *)UART0_BASE)
+/** Array initializer of UARTLP peripheral base pointers */
+#define UARTLP_BASES { UART0 }
+
+/**
+ * @}
+ */ /* end of group UARTLP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+#define USB_ADDINFO_IRQNUM_MASK 0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT 3
+#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
+#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
+#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
+#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT 6
+#define USB_OTGISTAT_IDCHG_MASK 0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK 0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT 0
+#define USB_OTGICR_BSESSEN_MASK 0x4u
+#define USB_OTGICR_BSESSEN_SHIFT 2
+#define USB_OTGICR_SESSVLDEN_MASK 0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT 3
+#define USB_OTGICR_LINESTATEEN_MASK 0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT 5
+#define USB_OTGICR_ONEMSECEN_MASK 0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT 6
+#define USB_OTGICR_IDEN_MASK 0x80u
+#define USB_OTGICR_IDEN_SHIFT 7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
+#define USB_OTGSTAT_BSESSEND_MASK 0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT 2
+#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT 3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
+#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
+#define USB_OTGSTAT_ID_MASK 0x80u
+#define USB_OTGSTAT_ID_SHIFT 7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK 0x4u
+#define USB_OTGCTL_OTGEN_SHIFT 2
+#define USB_OTGCTL_DMLOW_MASK 0x10u
+#define USB_OTGCTL_DMLOW_SHIFT 4
+#define USB_OTGCTL_DPLOW_MASK 0x20u
+#define USB_OTGCTL_DPLOW_SHIFT 5
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_ATTACH_MASK 0x40u
+#define USB_ISTAT_ATTACH_SHIFT 6
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_ATTACHEN_MASK 0x40u
+#define USB_INTEN_ATTACHEN_SHIFT 6
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_RESUME_MASK 0x4u
+#define USB_CTL_RESUME_SHIFT 2
+#define USB_CTL_HOSTMODEEN_MASK 0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT 3
+#define USB_CTL_RESET_MASK 0x10u
+#define USB_CTL_RESET_SHIFT 4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK 0x80u
+#define USB_ADDR_LSEN_SHIFT 7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK 0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT 0
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK 0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT 4
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK 0xFFu
+#define USB_SOFTHLD_CNT_SHIFT 0
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+#define USB_ENDPT_RETRYDIS_MASK 0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT 6
+#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT 7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+
+/**
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASES { USB0 }
+
+/**
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/**
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/**
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+/* No backward compatibility issues. */
+
+/**
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#endif /* #if !defined(MKL25Z4_H_) */
+
+/* MKL25Z4.h, eof. */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/MKL25Z4.sct b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/MKL25Z4.sct
new file mode 100644
index 000000000..101606842
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/MKL25Z4.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x20000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 0x4000 - 0xC0 = 0x3F40
+ RW_IRAM1 0x1FFFF0C0 0x3F40 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.s
new file mode 100644
index 000000000..e83f4fcbd
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.s
@@ -0,0 +1,353 @@
+;/*****************************************************************************
+; * @file: startup_MKL25Z4.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; * MKL25Z4
+; * @version: 1.1
+; * @date: 2012-6-21
+; *
+; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size EQU 0x00000400
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+ EXPORT __initial_sp
+
+Stack_Mem SPACE Stack_Size
+__initial_sp EQU 0x20003000 ; Top of RAM
+
+
+Heap_Size EQU 0x00000000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
+ DCD Reserved20_IRQHandler ; Reserved interrupt 20
+ DCD FTFA_IRQHandler ; FTFA interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C0 interrupt 25
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD SPI1_IRQHandler ; SPI1 interrupt
+ DCD UART0_IRQHandler ; UART0 status/error interrupt
+ DCD UART1_IRQHandler ; UART1 status/error interrupt
+ DCD UART2_IRQHandler ; UART2 status/error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
+ DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
+ DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT_IRQHandler ; PIT timer interrupt
+ DCD Reserved39_IRQHandler ; Reserved interrupt 39
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD DAC0_IRQHandler ; DAC interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD Reserved45_IRQHandler ; Reserved interrupt 45
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT0
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
+; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
+; <o.4> LPBOOT1
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
+; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
+; <o.2> NMI_DIS
+; <0=> NMI interrupts are always blocked
+; <1=> NMI pin/interrupts reset default to enabled
+; <o.3> RESET_PIN_CFG
+; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
+; <1=> RESET pin is dedicated
+; <o.3> FAST_INIT
+; <0=> Slower initialization
+; <1=> Fast Initialization
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT Reserved20_IRQHandler [WEAK]
+ EXPORT FTFA_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT TPM0_IRQHandler [WEAK]
+ EXPORT TPM1_IRQHandler [WEAK]
+ EXPORT TPM2_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT_IRQHandler [WEAK]
+ EXPORT Reserved39_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT Reserved45_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTD_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+Reserved39_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+Reserved45_IRQHandler
+PORTA_IRQHandler
+PORTD_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/sys.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_MICRO/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/MKL25Z4.sct b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/MKL25Z4.sct
new file mode 100644
index 000000000..101606842
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/MKL25Z4.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x20000 { ; load region size_region (32k)
+ ER_IROM1 0x00000000 0x20000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 0x4000 - 0xC0 = 0x3F40
+ RW_IRAM1 0x1FFFF0C0 0x3F40 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/startup_MKL25Z4.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/startup_MKL25Z4.s
new file mode 100644
index 000000000..19bec0a7c
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/startup_MKL25Z4.s
@@ -0,0 +1,332 @@
+;/*****************************************************************************
+; * @file: startup_MKL25Z4.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; * MKL25Z4
+; * @version: 1.1
+; * @date: 2012-6-21
+; *
+; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20003000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
+ DCD Reserved20_IRQHandler ; Reserved interrupt 20
+ DCD FTFA_IRQHandler ; FTFA interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C0 interrupt 25
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD SPI1_IRQHandler ; SPI1 interrupt
+ DCD UART0_IRQHandler ; UART0 status/error interrupt
+ DCD UART1_IRQHandler ; UART1 status/error interrupt
+ DCD UART2_IRQHandler ; UART2 status/error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
+ DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
+ DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT_IRQHandler ; PIT timer interrupt
+ DCD Reserved39_IRQHandler ; Reserved interrupt 39
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD DAC0_IRQHandler ; DAC interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD Reserved45_IRQHandler ; Reserved interrupt 45
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT0
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
+; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
+; <o.4> LPBOOT1
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
+; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
+; <o.2> NMI_DIS
+; <0=> NMI interrupts are always blocked
+; <1=> NMI pin/interrupts reset default to enabled
+; <o.3> RESET_PIN_CFG
+; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
+; <1=> RESET pin is dedicated
+; <o.3> FAST_INIT
+; <0=> Slower initialization
+; <1=> Fast Initialization
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT Reserved20_IRQHandler [WEAK]
+ EXPORT FTFA_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT TPM0_IRQHandler [WEAK]
+ EXPORT TPM1_IRQHandler [WEAK]
+ EXPORT TPM2_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT_IRQHandler [WEAK]
+ EXPORT Reserved39_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT Reserved45_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTD_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+Reserved39_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+Reserved45_IRQHandler
+PORTA_IRQHandler
+PORTD_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/sys.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/MKL25Z4.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/MKL25Z4.ld
new file mode 100644
index 000000000..6c8da015b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/MKL25Z4.ld
@@ -0,0 +1,163 @@
+/*
+ * KL25Z ARM GCC linker script file
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 128K - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFFF0C0, LENGTH = 16K - 0xC0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ *(.text.Reset_Handler)
+ *(.text.System_Init)
+ . = ALIGN(4);
+ } > VECTORS
+
+ .flash_protect :
+ {
+ KEEP(*(.kinetis_flash_config_field))
+ . = ALIGN(4);
+ } > FLASH_PROTECTION
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/startup_MKL25Z4.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/startup_MKL25Z4.s
new file mode 100644
index 000000000..d1a47ceaf
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_ARM/startup_MKL25Z4.s
@@ -0,0 +1,239 @@
+/* KL25Z startup ARM GCC
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x80
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x80
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vector_table,"a",%progbits
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
+ .long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
+ .long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
+ .long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
+ .long Default_Handler /* Reserved interrupt 20 */
+ .long FTFA_IRQHandler /* FTFA interrupt */
+ .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
+ .long LLW_IRQHandler /* Low Leakage Wakeup */
+ .long I2C0_IRQHandler /* I2C0 interrupt */
+ .long I2C1_IRQHandler /* I2C0 interrupt 25 */
+ .long SPI0_IRQHandler /* SPI0 interrupt */
+ .long SPI1_IRQHandler /* SPI1 interrupt */
+ .long UART0_IRQHandler /* UART0 status/error interrupt */
+ .long UART1_IRQHandler /* UART1 status/error interrupt */
+ .long UART2_IRQHandler /* UART2 status/error interrupt */
+ .long ADC0_IRQHandler /* ADC0 interrupt */
+ .long CMP0_IRQHandler /* CMP0 interrupt */
+ .long TPM0_IRQHandler /* TPM0 fault, overflow and channels interrupt */
+ .long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt */
+ .long TPM2_IRQHandler /* TPM2 fault, overflow and channels interrupt */
+ .long RTC_IRQHandler /* RTC interrupt */
+ .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
+ .long PIT_IRQHandler /* PIT timer interrupt */
+ .long Default_Handler /* Reserved interrupt 39 */
+ .long USB0_IRQHandler /* USB0 interrupt */
+ .long DAC0_IRQHandler /* DAC interrupt */
+ .long TSI0_IRQHandler /* TSI0 interrupt */
+ .long MCG_IRQHandler /* MCG interrupt */
+ .long LPTimer_IRQHandler /* LPTimer interrupt */
+ .long Default_Handler /* Reserved interrupt 45 */
+ .long PORTA_IRQHandler /* Port A interrupt */
+ .long PORTD_IRQHandler /* Port D interrupt */
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler DMA0_IRQHandler
+ def_irq_default_handler DMA1_IRQHandler
+ def_irq_default_handler DMA2_IRQHandler
+ def_irq_default_handler DMA3_IRQHandler
+ def_irq_default_handler FTFA_IRQHandler
+ def_irq_default_handler LVD_LVW_IRQHandler
+ def_irq_default_handler LLW_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler UART0_IRQHandler
+ def_irq_default_handler UART1_IRQHandler
+ def_irq_default_handler UART2_IRQHandler
+ def_irq_default_handler ADC0_IRQHandler
+ def_irq_default_handler CMP0_IRQHandler
+ def_irq_default_handler TPM0_IRQHandler
+ def_irq_default_handler TPM1_IRQHandler
+ def_irq_default_handler TPM2_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler RTC_Seconds_IRQHandler
+ def_irq_default_handler PIT_IRQHandler
+ def_irq_default_handler USB0_IRQHandler
+ def_irq_default_handler DAC0_IRQHandler
+ def_irq_default_handler TSI0_IRQHandler
+ def_irq_default_handler MCG_IRQHandler
+ def_irq_default_handler LPTimer_IRQHandler
+ def_irq_default_handler PORTA_IRQHandler
+ def_irq_default_handler PORTD_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+/* Flash protection region, placed at 0x400 */
+ .text
+ .thumb
+ .align 2
+ .section .kinetis_flash_config_field,"a",%progbits
+kinetis_flash_config:
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xfffffffe
+
+ .end
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/MKL25Z4.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/MKL25Z4.ld
new file mode 100644
index 000000000..dc26b23e4
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/MKL25Z4.ld
@@ -0,0 +1,197 @@
+/*
+*****************************************************************************
+**
+** File : KL25Z128M4_flash.ld
+**
+** Default linker command file for Flash targets
+**
+*****************************************************************************
+*/
+/* Entry Point */
+ENTRY(__thumb_startup)
+
+/* Highest address of the user mode stack */
+_estack = 0x20003000; /* end of SRAM */
+__SP_INIT = _estack;
+
+/* Generate a link error if heap and stack don't fit into RAM */
+__heap_size = 0x400; /* required amount of heap */
+__stack_size = 0x400; /* required amount of stack */
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (rx) : ORIGIN = 0x00000000, LENGTH = 0xC0
+ m_cfmprotrom (rx) : ORIGIN = 0x00000400, LENGTH = 0x10
+ m_text (rx) : ORIGIN = 0x00000800, LENGTH = 128K - 0x800
+ m_data (rwx) : ORIGIN = 0x1FFFF000, LENGTH = 16K /* SRAM */
+}
+
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into Flash */
+ .interrupts :
+ {
+ __vector_table = .;
+ . = ALIGN(4);
+ KEEP(*(.vectortable)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ .cfmprotect :
+ {
+ . = ALIGN(4);
+ KEEP(*(.cfmconfig)) /* Flash Configuration Field (FCF) */
+ . = ALIGN(4);
+ } > m_cfmprotrom
+
+ /* The program code and other data goes into Flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } > m_text
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > m_text
+ .ARM : {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ ___ROM_AT = .;
+ } > m_text
+
+ /* reserve MTB memory at the beginning of m_data */
+ .mtb : /* MTB buffer address as defined by the hardware */
+ {
+ . = ALIGN(8);
+ _mtb_start = .;
+ KEEP(*(.mtb_buf)) /* need to KEEP Micro Trace Buffer as not referenced by application */
+ . = ALIGN(8);
+ _mtb_end = .;
+ } > m_data
+
+ /* Initialized data sections goes into RAM, load LMA copy after code */
+ .data : AT(___ROM_AT)
+ {
+ . = ALIGN(4);
+ __sinit__ = .;
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+ } > m_data
+
+ ___data_size = _edata - _sdata;
+
+ /* Uninitialized data section */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ __START_BSS = .;
+ PROVIDE ( __bss_start__ = __START_BSS );
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ __END_BSS = .;
+ PROVIDE ( __bss_end__ = __END_BSS );
+ } > m_data
+
+ _romp_at = ___ROM_AT + SIZEOF(.data);
+ .romp : AT(_romp_at)
+ {
+ __S_romp = _romp_at;
+ LONG(___ROM_AT);
+ LONG(_sdata);
+ LONG(___data_size);
+ LONG(0);
+ LONG(0);
+ LONG(0);
+ } > m_data
+
+ /* User_heap_stack section, used to check that there is enough RAM left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(4);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ __heap_addr = .;
+ . = . + __heap_size;
+ . = . + __stack_size;
+ . = ALIGN(4);
+ } > m_data
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/startup_MKL25Z4.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/startup_MKL25Z4.c
new file mode 100644
index 000000000..49a3a3735
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_EWL/startup_MKL25Z4.c
@@ -0,0 +1,147 @@
+#include <string.h>
+#include <stdlib.h>
+
+#include "cmsis.h"
+
+// Linker Script
+extern unsigned long _estack;
+extern char __S_romp[];
+
+extern char __START_BSS[];
+extern char __END_BSS[];
+
+// CRT0
+extern void __init_registers();
+extern void __copy_rom_sections_to_ram(void);
+extern void __call_static_initializers(void);
+extern void __init_user();
+
+// User/mbed Defined
+extern int main();
+extern void mbed_exit(int return_code);
+
+void _ExitProcess(int return_code) {
+ mbed_exit(return_code);
+}
+
+void __thumb_startup(void) {
+ // Setup registers
+ __init_registers();
+
+ // Disable the Watchdog because it may reset the core before entering main().
+ SIM->COPC = 0x0;
+
+ // zero-fill the .bss section
+ memset(__START_BSS, 0, (__END_BSS - __START_BSS));
+
+ if (__S_romp != 0L)
+ __copy_rom_sections_to_ram();
+
+ // call C++ static initializers
+ __call_static_initializers();
+
+ // initializations before main, user specific
+ __init_user();
+
+ exit(main());
+
+ // should never get here
+ while (1);
+}
+
+void Default_Handler() {
+ __asm("bkpt");
+}
+
+/* Weak definitions of handlers point to Default_Handler if not implemented */
+void NMI_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void HardFault_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SVC_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void PendSV_Handler() __attribute__ ((weak, alias("Default_Handler")));
+void SysTick_Handler() __attribute__ ((weak, alias("Default_Handler")));
+
+void DMA0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void DMA1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void DMA2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void DMA3_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MCM_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void FTFL_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PMC_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void LLW_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void I2C0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void I2C1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void SPI0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void SPI1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void UART0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void UART1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void UART2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void ADC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void CMP0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void FTM0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void FTM1_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void FTM2_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void RTC_Alarm_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void RTC_Seconds_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PIT_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void USBOTG_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void DAC0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void TSI0_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void MCG_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void LPTimer_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PORTA_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+void PORTD_IRQHandler() __attribute__ ((weak, alias("Default_Handler")));
+
+/* The Interrupt Vector Table */
+void (* const InterruptVector[])() __attribute__ ((section(".vectortable"))) = {
+ /* Processor exceptions */
+ (void(*)(void)) &_estack,
+ __thumb_startup,
+ NMI_Handler,
+ HardFault_Handler,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ SVC_Handler,
+ 0,
+ 0,
+ PendSV_Handler,
+ SysTick_Handler,
+
+ /* Interrupts */
+ DMA0_IRQHandler, /* DMA Channel 0 Transfer Complete and Error */
+ DMA1_IRQHandler, /* DMA Channel 1 Transfer Complete and Error */
+ DMA2_IRQHandler, /* DMA Channel 2 Transfer Complete and Error */
+ DMA3_IRQHandler, /* DMA Channel 3 Transfer Complete and Error */
+ MCM_IRQHandler, /* Normal Interrupt */
+ FTFL_IRQHandler, /* FTFL Interrupt */
+ PMC_IRQHandler, /* PMC Interrupt */
+ LLW_IRQHandler, /* Low Leakage Wake-up */
+ I2C0_IRQHandler, /* I2C0 interrupt */
+ I2C1_IRQHandler, /* I2C1 interrupt */
+ SPI0_IRQHandler, /* SPI0 Interrupt */
+ SPI1_IRQHandler, /* SPI1 Interrupt */
+ UART0_IRQHandler, /* UART0 Status and Error interrupt */
+ UART1_IRQHandler, /* UART1 Status and Error interrupt */
+ UART2_IRQHandler, /* UART2 Status and Error interrupt */
+ ADC0_IRQHandler, /* ADC0 interrupt */
+ CMP0_IRQHandler, /* CMP0 interrupt */
+ FTM0_IRQHandler, /* FTM0 fault, overflow and channels interrupt */
+ FTM1_IRQHandler, /* FTM1 fault, overflow and channels interrupt */
+ FTM2_IRQHandler, /* FTM2 fault, overflow and channels interrupt */
+ RTC_Alarm_IRQHandler, /* RTC Alarm interrupt */
+ RTC_Seconds_IRQHandler, /* RTC Seconds interrupt */
+ PIT_IRQHandler, /* PIT timer all channels interrupt */
+ Default_Handler, /* Reserved interrupt 39/23 */
+ USBOTG_IRQHandler, /* USB interrupt */
+ DAC0_IRQHandler, /* DAC0 interrupt */
+ TSI0_IRQHandler, /* TSI0 Interrupt */
+ MCG_IRQHandler, /* MCG Interrupt */
+ LPTimer_IRQHandler, /* LPTimer interrupt */
+ Default_Handler, /* Reserved interrupt 45/29 */
+ PORTA_IRQHandler, /* Port A interrupt */
+ PORTD_IRQHandler /* Port D interrupt */
+};
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/MKL25Z4.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/MKL25Z4.ld
new file mode 100644
index 000000000..3ea44c046
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/MKL25Z4.ld
@@ -0,0 +1,153 @@
+/* Linker script for mbed LPC1768 */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K
+ RAM (rwx) : ORIGIN = 0x1FFFF0C0, LENGTH = 0x3F40
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text.Reset_Handler)
+ *(.text.SystemInit)
+
+ /* Only vectors and code running at reset are safe to be in first 512
+ bytes since RAM can be mapped into this area for RAM based interrupt
+ vectors. */
+ . = 0x00000200;
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/startup_MKL25Z4.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/startup_MKL25Z4.s
new file mode 100644
index 000000000..84bfb6b68
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_GCC_CW_NEWLIB/startup_MKL25Z4.s
@@ -0,0 +1,226 @@
+/* File: startup_ARMCM0.S
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x80
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x80
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .isr_vector
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
+ .long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
+ .long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
+ .long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
+ .long Reserved20_IRQHandler /* Reserved interrupt 20 */
+ .long FTFA_IRQHandler /* FTFA interrupt */
+ .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
+ .long LLW_IRQHandler /* Low Leakage Wakeup */
+ .long I2C0_IRQHandler /* I2C0 interrupt */
+ .long I2C1_IRQHandler /* I2C0 interrupt 25 */
+ .long SPI0_IRQHandler /* SPI0 interrupt */
+ .long SPI1_IRQHandler /* SPI1 interrupt */
+ .long UART0_IRQHandler /* UART0 status/error interrupt */
+ .long UART1_IRQHandler /* UART1 status/error interrupt */
+ .long UART2_IRQHandler /* UART2 status/error interrupt */
+ .long ADC0_IRQHandler /* ADC0 interrupt */
+ .long CMP0_IRQHandler /* CMP0 interrupt */
+ .long TPM0_IRQHandler /* TPM0 fault, overflow and channels interrupt */
+ .long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt */
+ .long TPM2_IRQHandler /* TPM2 fault, overflow and channels interrupt */
+ .long RTC_IRQHandler /* RTC interrupt */
+ .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
+ .long PIT_IRQHandler /* PIT timer interrupt */
+ .long Reserved39_IRQHandler /* Reserved interrupt 39 */
+ .long USB0_IRQHandler /* USB0 interrupt */
+ .long DAC0_IRQHandler /* DAC interrupt */
+ .long TSI0_IRQHandler /* TSI0 interrupt */
+ .long MCG_IRQHandler /* MCG interrupt */
+ .long LPTimer_IRQHandler /* LPTimer interrupt */
+ .long Reserved45_IRQHandler /* Reserved interrupt 45 */
+ .long PORTA_IRQHandler /* Port A interrupt */
+ .long PORTD_IRQHandler /* Port D interrupt */
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .flash_to_ram_loop_end
+
+ movs r4, 0
+.flash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .flash_to_ram_loop
+.flash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler DMA0_IRQHandler
+ def_default_handler DMA1_IRQHandler
+ def_default_handler DMA2_IRQHandler
+ def_default_handler DMA3_IRQHandler
+ def_default_handler Reserved20_IRQHandler
+ def_default_handler FTFA_IRQHandler
+ def_default_handler LVD_LVW_IRQHandler
+ def_default_handler LLW_IRQHandler
+ def_default_handler I2C0_IRQHandler
+ def_default_handler I2C1_IRQHandler
+ def_default_handler SPI0_IRQHandler
+ def_default_handler SPI1_IRQHandler
+ def_default_handler UART0_IRQHandler
+ def_default_handler UART1_IRQHandler
+ def_default_handler UART2_IRQHandler
+ def_default_handler ADC0_IRQHandler
+ def_default_handler CMP0_IRQHandler
+ def_default_handler TPM0_IRQHandler
+ def_default_handler TPM1_IRQHandler
+ def_default_handler TPM2_IRQHandler
+ def_default_handler RTC_IRQHandler
+ def_default_handler RTC_Seconds_IRQHandler
+ def_default_handler PIT_IRQHandler
+ def_default_handler Reserved39_IRQHandler
+ def_default_handler USB0_IRQHandler
+ def_default_handler DAC0_IRQHandler
+ def_default_handler TSI0_IRQHandler
+ def_default_handler MCG_IRQHandler
+ def_default_handler LPTimer_IRQHandler
+ def_default_handler Reserved45_IRQHandler
+ def_default_handler PORTA_IRQHandler
+ def_default_handler PORTD_IRQHandler
+
+ .weak DEF_IRQHandler
+ .set DEF_IRQHandler, Default_Handler
+
+ .end
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/MKL25Z4.icf b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/MKL25Z4.icf
new file mode 100644
index 000000000..55caa8084
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/MKL25Z4.icf
@@ -0,0 +1,43 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0001ffff;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x1ffff000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x1ffff0bf;
+define symbol __ICFEDIT_region_RAM_start__ = 0x1ffff0c0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_heap__ = 0x1000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM2_start__ = 0x20000000;
+define symbol __region_RAM2_end__ = 0x20002fff;
+
+define symbol __FlashConfig_start__ = 0x00000400;
+define symbol __FlashConfig_end__ = 0x0000040f;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in FlashConfig_region {section FlashConfig};
+
+place in ROM_region { readonly };
+
+place in RAM_region { readwrite, block HEAP, block CSTACK };
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/startup_MKL25Z4.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/startup_MKL25Z4.s
new file mode 100644
index 000000000..88a8a876e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/TOOLCHAIN_IAR/startup_MKL25Z4.s
@@ -0,0 +1,213 @@
+/**************************************************
+ *
+ * Copyright 2012 IAR Systems. All rights reserved.
+ *
+ * $Revision: 16 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:ROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete intertrupt
+ DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete intertrupt
+ DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete intertrupt
+ DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete intertrupt
+ DCD 0 ; 4: Reserved DMA Channel 5 transfer complete intertrupt
+ DCD FTFA_IRQHandler ; 5: FTFA
+ DCD LVD_LVW_IRQHandler ; 6: Low-voltage detect, low-voltage warning
+ DCD LLW_IRQHandler ; 7: Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; 8: IIC 0 interrupt
+ DCD I2C1_IRQHandler ; 9: IIC 1 intertrupt
+ DCD SPI0_IRQHandler ;10: SPI0 intertrupt
+ DCD SPI1_IRQHandler ;11: SPI1 intertrupt
+ DCD UART0_IRQHandler ;12: UART 0 status and error intertrupt
+ DCD UART1_IRQHandler ;13: UART 1 status and error intertrupt
+ DCD UART2_IRQHandler ;14: UART 2 status and error intertrupt
+ DCD ADC0_IRQHandler ;15: ADC 0 interrupt
+ DCD CMP0_IRQHandler ;16: CMP 0 interrupt
+ DCD TPM0_IRQHandler ;17: TPM 0 interrupt
+ DCD TPM1_IRQHandler ;18: TPM 1 interrupt
+ DCD TPM2_IRQHandler ;19: TPM 2 interrupt
+ DCD RTC_IRQHandler ;20: RTC Alarm interrupt
+ DCD RTC_Seconds_IRQHandler ;21: RTC Seconds interrupt
+ DCD PIT_IRQHandler ;22: PIT Single interrupt vector for all channels
+ DCD 0 ;23: Reserved
+ DCD USB0_IRQHandler ;24: USB OTG intertrupt
+ DCD DAC0_IRQHandler ;25: UART 0 status intertrupt
+ DCD TSI0_IRQHandler ;26: TSI 0 interrupt
+ DCD MCG_IRQHandler ;27: MCG intertrupt
+ DCD LPTimer_IRQHandler ;28: LPTMR0 intertrupt
+ DCD 0 ;29: Reserved
+ DCD PORTA_IRQHandler ;30: PORT A interrupt
+ DCD PORTD_IRQHandler ;31: PORT D interrupt
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;Flash Configuration
+;;16-byte flash configuration field that stores default protection settings (loaded on reset)
+;;and security information that allows the MCU to restrict acces to the FTFL module.
+
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0^0xFF
+
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1^0xFF
+
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2^0xFF
+
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3^0xFF
+
+FOPT EQU 0xFF
+
+FSEC EQU 0xFE
+ SECTION FlashConfig:CONST:REORDER:ROOT(2)
+Config:
+ DATA
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK DMA0_IRQHandler
+ PUBWEAK DMA1_IRQHandler
+ PUBWEAK DMA2_IRQHandler
+ PUBWEAK DMA3_IRQHandler
+ PUBWEAK FTFA_IRQHandler
+ PUBWEAK LVD_LVW_IRQHandler
+ PUBWEAK LLW_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK ADC0_IRQHandler
+ PUBWEAK CMP0_IRQHandler
+ PUBWEAK TPM0_IRQHandler
+ PUBWEAK TPM1_IRQHandler
+ PUBWEAK TPM2_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK RTC_Seconds_IRQHandler
+ PUBWEAK PIT_IRQHandler
+ PUBWEAK USB0_IRQHandler
+ PUBWEAK DAC0_IRQHandler
+ PUBWEAK TSI0_IRQHandler
+ PUBWEAK MCG_IRQHandler
+ PUBWEAK LPTimer_IRQHandler
+ PUBWEAK PORTA_IRQHandler
+ PUBWEAK PORTD_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler
+HardFault_Handler
+SVC_Handler
+PendSV_Handler
+SysTick_Handler
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+PORTA_IRQHandler
+PORTD_IRQHandler
+Default_Handler
+
+ B Default_Handler
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis.h
new file mode 100644
index 000000000..82dab2b69
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MKL25Z4.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.c
new file mode 100644
index 000000000..cb17abc0d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFF000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.h
new file mode 100644
index 000000000..64f36b316
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.c
new file mode 100644
index 000000000..92255f236
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.c
@@ -0,0 +1,263 @@
+/*
+** ###################################################################
+** Processor: MKL25Z128VLK4
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL25RM, Rev.1, Jun 2012
+** Version: rev. 1.1, 2012-06-21
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-13)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL25Z4
+ * @version 1.1
+ * @date 2012-06-21
+ * @brief Device specific configuration file for MKL25Z4 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MKL25Z4.h"
+
+#define DISABLE_WDOG 1
+
+#define CLOCK_SETUP 1
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+ Reference clock source for MCG module is the slow internal clock source 32.768kHz
+ Core clock = 41.94MHz, BusClock = 13.98MHz
+ 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+ Reference clock source for MCG module is an external crystal 8MHz
+ Core clock = 48MHz, BusClock = 24MHz
+ 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+ Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
+ Core clock = 8MHz, BusClock = 8MHz
+*/
+
+/*----------------------------------------------------------------------------
+ Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+ /* Disable the WDOG module */
+ /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
+ SIM->COPC = (uint32_t)0x00u;
+#endif /* (DISABLE_WDOG) */
+#if (CLOCK_SETUP == 0)
+ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
+ /* Switch to FEI Mode */
+ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x06U;
+ /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x00U;
+ /* MCG->C4: DMX32=0,DRST_DRS=1 */
+ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x80U;
+ /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00U;
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
+ }
+#elif (CLOCK_SETUP == 1)
+ /* SIM->SCGC5: PORTA=1 */
+ SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
+ /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
+ /* PORTA->PCR18: ISF=0,MUX=0 */
+ PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+ /* PORTA->PCR19: ISF=0,MUX=0 */
+ PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
+ /* Switch to FBE Mode */
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
+ OSC0->CR = (uint8_t)0x89U;
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24U;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9AU;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+ /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
+ MCG->C5 = (uint8_t)0x01U;
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to PBE Mode */
+ /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x40U;
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
+ }
+ /* Switch to PEE Mode */
+ /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x1AU;
+ while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
+ }
+#elif (CLOCK_SETUP == 2)
+ /* SIM->SCGC5: PORTA=1 */
+ SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
+ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
+ /* PORTA->PCR18: ISF=0,MUX=0 */
+ PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+ /* PORTA->PCR19: ISF=0,MUX=0 */
+ PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
+ /* Switch to FBE Mode */
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
+ OSC0->CR = (uint8_t)0x89U;
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24U;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9AU;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+ /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00U;
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to BLPE Mode */
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
+ MCG->C2 = (uint8_t)0x26U;
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+#endif /* (CLOCK_SETUP == 2) */
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint8_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+ /* Output of FLL or PLL is selected */
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
+ /* FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
+ MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
+ } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x0u:
+ MCGOUTClock *= 640u;
+ break;
+ case 0x20u:
+ MCGOUTClock *= 1280u;
+ break;
+ case 0x40u:
+ MCGOUTClock *= 1920u;
+ break;
+ case 0x60u:
+ MCGOUTClock *= 2560u;
+ break;
+ case 0x80u:
+ MCGOUTClock *= 732u;
+ break;
+ case 0xA0u:
+ MCGOUTClock *= 1464u;
+ break;
+ case 0xC0u:
+ MCGOUTClock *= 2197u;
+ break;
+ case 0xE0u:
+ MCGOUTClock *= 2929u;
+ break;
+ default:
+ break;
+ }
+ } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ /* PLL is selected */
+ Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+ MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+ Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+ MCGOUTClock *= Divider; /* Calculate the MCG output clock */
+ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.h
new file mode 100644
index 000000000..69ed7b04e
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.h
@@ -0,0 +1,84 @@
+/*
+** ###################################################################
+** Processor: MKL25Z128VLK4
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL25RM, Rev.1, Jun 2012
+** Version: rev. 1.1, 2012-06-21
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-06-13)
+** Initial version.
+** - rev. 1.1 (2012-06-21)
+** Update according to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL25Z4
+ * @version 1.1
+ * @date 2012-06-21
+ * @brief Device specific configuration file for MKL25Z4 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MKL25Z4_H_
+#define SYSTEM_MKL25Z4_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MKL25Z4_H_) */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h
new file mode 100644
index 000000000..96162e2a8
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h
@@ -0,0 +1,8856 @@
+/*
+** ###################################################################
+** Processors: MKL43Z256VLH4
+** MKL43Z128VLH4
+** MKL43Z64VLH4
+** MKL43Z256VMP4
+** MKL43Z128VMP4
+** MKL43Z64VMP4
+**
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
+** Version: rev. 1.5, 2014-09-05
+** Build: b140905
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MKL43Z4
+**
+** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2014-03-27)
+** Initial version.
+** - rev. 1.1 (2014-05-26)
+** I2S registers TCR2/RCR2 and others were changed.
+** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
+** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
+** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
+** Clock configuration for high range external oscillator has been added.
+** RFSYS module access has been added.
+** - rev. 1.2 (2014-07-10)
+** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
+** UART0 - UART0 module renamed to UART2.
+** I2S - removed MDR register.
+** - rev. 1.3 (2014-08-21)
+** UART2 - Removed ED register.
+** UART2 - Removed MODEM register.
+** UART2 - Removed IR register.
+** UART2 - Removed PFIFO register.
+** UART2 - Removed CFIFO register.
+** UART2 - Removed SFIFO register.
+** UART2 - Removed TWFIFO register.
+** UART2 - Removed TCFIFO register.
+** UART2 - Removed RWFIFO register.
+** UART2 - Removed RCFIFO register.
+** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
+** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
+** SIM - Removed bitfield DIEID in SDID register.
+** - rev. 1.4 (2014-09-01)
+** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
+** USB - USB0_CTL1 was renamed to USB0_CTL register.
+** - rev. 1.5 (2014-09-05)
+** USB - USBEN bitfield of the USB0_CTL renamed to USBENSOFEN.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL43Z4.h
+ * @version 1.5
+ * @date 2014-09-05
+ * @brief CMSIS Peripheral Access Layer for MKL43Z4
+ *
+ * CMSIS Peripheral Access Layer for MKL43Z4
+ */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCU activation
+ ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MKL43Z4_H_) /* Check if memory map has not been already included */
+#define MKL43Z4_H_
+#define MCU_MKL43Z4
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+ #error MKL43Z4 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0005u
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Auxiliary constants */
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */
+
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
+ Reserved20_IRQn = 4, /**< Reserved interrupt */
+ FTFA_IRQn = 5, /**< Command complete and read collision */
+ PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
+ LLWU_IRQn = 7, /**< Low leakage wakeup */
+ I2C0_IRQn = 8, /**< I2C0 interrupt */
+ I2C1_IRQn = 9, /**< I2C1 interrupt */
+ SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
+ SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
+ LPUART0_IRQn = 12, /**< LPUART0 status and error */
+ LPUART1_IRQn = 13, /**< LPUART1 status and error */
+ UART2_FLEXIO_IRQn = 14, /**< UART2 or FLEXIO */
+ ADC0_IRQn = 15, /**< ADC0 interrupt */
+ CMP0_IRQn = 16, /**< CMP0 interrupt */
+ TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
+ TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
+ TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
+ RTC_IRQn = 20, /**< RTC alarm */
+ RTC_Seconds_IRQn = 21, /**< RTC seconds */
+ PIT_IRQn = 22, /**< PIT interrupt */
+ I2S0_IRQn = 23, /**< I2S0 interrupt */
+ USB0_IRQn = 24, /**< USB0 interrupt */
+ DAC0_IRQn = 25, /**< DAC0 interrupt */
+ Reserved42_IRQn = 26, /**< Reserved interrupt */
+ Reserved43_IRQn = 27, /**< Reserved interrupt */
+ LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
+ LCD_IRQn = 29, /**< LCD interrupt */
+ PORTA_IRQn = 30, /**< PORTA Pin detect */
+ PORTCD_IRQn = 31 /**< Single interrupt vector for PORTC; PORTD Pin detect */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M0 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h" /* Core Peripheral Access Layer */
+#include "system_MKL43Z4.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index) ((base)->SC1[index])
+#define ADC_CFG1_REG(base) ((base)->CFG1)
+#define ADC_CFG2_REG(base) ((base)->CFG2)
+#define ADC_R_REG(base,index) ((base)->R[index])
+#define ADC_CV1_REG(base) ((base)->CV1)
+#define ADC_CV2_REG(base) ((base)->CV2)
+#define ADC_SC2_REG(base) ((base)->SC2)
+#define ADC_SC3_REG(base) ((base)->SC3)
+#define ADC_OFS_REG(base) ((base)->OFS)
+#define ADC_PG_REG(base) ((base)->PG)
+#define ADC_MG_REG(base) ((base)->MG)
+#define ADC_CLPD_REG(base) ((base)->CLPD)
+#define ADC_CLPS_REG(base) ((base)->CLPS)
+#define ADC_CLP4_REG(base) ((base)->CLP4)
+#define ADC_CLP3_REG(base) ((base)->CLP3)
+#define ADC_CLP2_REG(base) ((base)->CLP2)
+#define ADC_CLP1_REG(base) ((base)->CLP1)
+#define ADC_CLP0_REG(base) ((base)->CLP0)
+#define ADC_CLMD_REG(base) ((base)->CLMD)
+#define ADC_CLMS_REG(base) ((base)->CLMS)
+#define ADC_CLM4_REG(base) ((base)->CLM4)
+#define ADC_CLM3_REG(base) ((base)->CLM3)
+#define ADC_CLM2_REG(base) ((base)->CLM2)
+#define ADC_CLM1_REG(base) ((base)->CLM1)
+#define ADC_CLM0_REG(base) ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR (ADC0)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS { ADC0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
+#define ADC0_RA ADC_R_REG(ADC0,0)
+#define ADC0_RB ADC_R_REG(ADC0,1)
+#define ADC0_CV1 ADC_CV1_REG(ADC0)
+#define ADC0_CV2 ADC_CV2_REG(ADC0)
+#define ADC0_SC2 ADC_SC2_REG(ADC0)
+#define ADC0_SC3 ADC_SC3_REG(ADC0)
+#define ADC0_OFS ADC_OFS_REG(ADC0)
+#define ADC0_PG ADC_PG_REG(ADC0)
+#define ADC0_MG ADC_MG_REG(ADC0)
+#define ADC0_CLPD ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
+#define ADC0_R(index) ADC_R_REG(ADC0,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type, *CMP_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- CMP - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register accessors */
+#define CMP_CR0_REG(base) ((base)->CR0)
+#define CMP_CR1_REG(base) ((base)->CR1)
+#define CMP_FPR_REG(base) ((base)->FPR)
+#define CMP_SCR_REG(base) ((base)->SCR)
+#define CMP_DACCR_REG(base) ((base)->DACCR)
+#define CMP_MUXCR_REG(base) ((base)->MUXCR)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_TRIGM_MASK 0x20u
+#define CMP_CR1_TRIGM_SHIFT 5
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK 0x80u
+#define CMP_MUXCR_PSTM_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+#define CMP0_BASE_PTR (CMP0)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS { CMP0_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS { CMP0 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS { CMP0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- CMP - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
+ * @{
+ */
+
+
+/* CMP - Register instance definitions */
+/* CMP0 */
+#define CMP0_CR0 CMP_CR0_REG(CMP0)
+#define CMP0_CR1 CMP_CR1_REG(CMP0)
+#define CMP0_FPR CMP_FPR_REG(CMP0)
+#define CMP0_SCR CMP_SCR_REG(CMP0)
+#define CMP0_DACCR CMP_DACCR_REG(CMP0)
+#define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[2];
+ uint8_t RESERVED_0[28];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type, *DAC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DAC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register accessors */
+#define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
+#define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
+#define DAC_SR_REG(base) ((base)->SR)
+#define DAC_C0_REG(base) ((base)->C0)
+#define DAC_C1_REG(base) ((base)->C1)
+#define DAC_C2_REG(base) ((base)->C2)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x6u
+#define DAC_C1_DACBFMD_SHIFT 1
+#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0x1u
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFRP_MASK 0x10u
+#define DAC_C2_DACBFRP_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+#define DAC0_BASE_PTR (DAC0)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS { DAC0_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS { DAC0 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS { DAC0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- DAC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
+ * @{
+ */
+
+
+/* DAC - Register instance definitions */
+/* DAC0 */
+#define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
+#define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
+#define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
+#define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
+#define DAC0_SR DAC_SR_REG(DAC0)
+#define DAC0_C0 DAC_C0_REG(DAC0)
+#define DAC0_C1 DAC_C1_REG(DAC0)
+#define DAC0_C2 DAC_C2_REG(DAC0)
+
+/* DAC - Register array accessors */
+#define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
+#define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[256];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
+ __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
+ union { /* offset: 0x108, array step: 0x10 */
+ __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
+ struct { /* offset: 0x108, array step: 0x10 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
+ } DMA_DSR_ACCESS8BIT;
+ };
+ __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
+ } DMA[4];
+} DMA_Type, *DMA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DMA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register accessors */
+#define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR)
+#define DMA_DAR_REG(base,index) ((base)->DMA[index].DAR)
+#define DMA_DSR_BCR_REG(base,index) ((base)->DMA[index].DSR_BCR)
+#define DMA_DSR_REG(base,index) ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR)
+#define DMA_DCR_REG(base,index) ((base)->DMA[index].DCR)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* SAR Bit Fields */
+#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
+#define DMA_SAR_SAR_SHIFT 0
+#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
+/* DAR Bit Fields */
+#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
+#define DMA_DAR_DAR_SHIFT 0
+#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
+/* DSR_BCR Bit Fields */
+#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
+#define DMA_DSR_BCR_BCR_SHIFT 0
+#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
+#define DMA_DSR_BCR_DONE_MASK 0x1000000u
+#define DMA_DSR_BCR_DONE_SHIFT 24
+#define DMA_DSR_BCR_BSY_MASK 0x2000000u
+#define DMA_DSR_BCR_BSY_SHIFT 25
+#define DMA_DSR_BCR_REQ_MASK 0x4000000u
+#define DMA_DSR_BCR_REQ_SHIFT 26
+#define DMA_DSR_BCR_BED_MASK 0x10000000u
+#define DMA_DSR_BCR_BED_SHIFT 28
+#define DMA_DSR_BCR_BES_MASK 0x20000000u
+#define DMA_DSR_BCR_BES_SHIFT 29
+#define DMA_DSR_BCR_CE_MASK 0x40000000u
+#define DMA_DSR_BCR_CE_SHIFT 30
+/* DCR Bit Fields */
+#define DMA_DCR_LCH2_MASK 0x3u
+#define DMA_DCR_LCH2_SHIFT 0
+#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
+#define DMA_DCR_LCH1_MASK 0xCu
+#define DMA_DCR_LCH1_SHIFT 2
+#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
+#define DMA_DCR_LINKCC_MASK 0x30u
+#define DMA_DCR_LINKCC_SHIFT 4
+#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
+#define DMA_DCR_D_REQ_MASK 0x80u
+#define DMA_DCR_D_REQ_SHIFT 7
+#define DMA_DCR_DMOD_MASK 0xF00u
+#define DMA_DCR_DMOD_SHIFT 8
+#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
+#define DMA_DCR_SMOD_MASK 0xF000u
+#define DMA_DCR_SMOD_SHIFT 12
+#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
+#define DMA_DCR_START_MASK 0x10000u
+#define DMA_DCR_START_SHIFT 16
+#define DMA_DCR_DSIZE_MASK 0x60000u
+#define DMA_DCR_DSIZE_SHIFT 17
+#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
+#define DMA_DCR_DINC_MASK 0x80000u
+#define DMA_DCR_DINC_SHIFT 19
+#define DMA_DCR_SSIZE_MASK 0x300000u
+#define DMA_DCR_SSIZE_SHIFT 20
+#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
+#define DMA_DCR_SINC_MASK 0x400000u
+#define DMA_DCR_SINC_SHIFT 22
+#define DMA_DCR_EADREQ_MASK 0x800000u
+#define DMA_DCR_EADREQ_SHIFT 23
+#define DMA_DCR_AA_MASK 0x10000000u
+#define DMA_DCR_AA_SHIFT 28
+#define DMA_DCR_CS_MASK 0x20000000u
+#define DMA_DCR_CS_SHIFT 29
+#define DMA_DCR_ERQ_MASK 0x40000000u
+#define DMA_DCR_ERQ_SHIFT 30
+#define DMA_DCR_EINT_MASK 0x80000000u
+#define DMA_DCR_EINT_SHIFT 31
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+#define DMA_BASE_PTR (DMA0)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- DMA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
+ * @{
+ */
+
+
+/* DMA - Register instance definitions */
+/* DMA */
+#define DMA_SAR0 DMA_SAR_REG(DMA0,0)
+#define DMA_DAR0 DMA_DAR_REG(DMA0,0)
+#define DMA_DSR_BCR0 DMA_DSR_BCR_REG(DMA0,0)
+#define DMA_DSR0 DMA_DSR_REG(DMA0,0)
+#define DMA_DCR0 DMA_DCR_REG(DMA0,0)
+#define DMA_SAR1 DMA_SAR_REG(DMA0,1)
+#define DMA_DAR1 DMA_DAR_REG(DMA0,1)
+#define DMA_DSR_BCR1 DMA_DSR_BCR_REG(DMA0,1)
+#define DMA_DSR1 DMA_DSR_REG(DMA0,1)
+#define DMA_DCR1 DMA_DCR_REG(DMA0,1)
+#define DMA_SAR2 DMA_SAR_REG(DMA0,2)
+#define DMA_DAR2 DMA_DAR_REG(DMA0,2)
+#define DMA_DSR_BCR2 DMA_DSR_BCR_REG(DMA0,2)
+#define DMA_DSR2 DMA_DSR_REG(DMA0,2)
+#define DMA_DCR2 DMA_DCR_REG(DMA0,2)
+#define DMA_SAR3 DMA_SAR_REG(DMA0,3)
+#define DMA_DAR3 DMA_DAR_REG(DMA0,3)
+#define DMA_DSR_BCR3 DMA_DSR_BCR_REG(DMA0,3)
+#define DMA_DSR3 DMA_DSR_REG(DMA0,3)
+#define DMA_DCR3 DMA_DCR_REG(DMA0,3)
+
+/* DMA - Register array accessors */
+#define DMA_SAR(index) DMA_SAR_REG(DMA0,index)
+#define DMA_DAR(index) DMA_DAR_REG(DMA0,index)
+#define DMA_DSR_BCR(index) DMA_DSR_BCR_REG(DMA0,index)
+#define DMA_DSR(index) DMA_DSR_REG(DMA0,index)
+#define DMA_DCR(index) DMA_DCR_REG(DMA0,index)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type, *DMAMUX_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register accessors */
+#define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
+#define DMAMUX0_BASE_PTR (DMAMUX0)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS { DMAMUX0 }
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
+ * @{
+ */
+
+
+/* DMAMUX - Register instance definitions */
+/* DMAMUX0 */
+#define DMAMUX0_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX0,0)
+#define DMAMUX0_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX0,1)
+#define DMAMUX0_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX0,2)
+#define DMAMUX0_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX0,3)
+
+/* DMAMUX - Register array accessors */
+#define DMAMUX0_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX0,index)
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FLEXIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXIO - Register Layout Typedef */
+typedef struct {
+ __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
+ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
+ __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
+ __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
+ __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
+ __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
+ __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
+ uint8_t RESERVED_3[76];
+ __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
+ uint8_t RESERVED_4[112];
+ __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
+ uint8_t RESERVED_5[240];
+ __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
+ uint8_t RESERVED_6[112];
+ __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x280, array step: 0x4 */
+ uint8_t RESERVED_7[112];
+ __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
+ uint8_t RESERVED_8[112];
+ __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x380, array step: 0x4 */
+ uint8_t RESERVED_9[112];
+ __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
+ uint8_t RESERVED_10[112];
+ __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
+ uint8_t RESERVED_11[112];
+ __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
+} FLEXIO_Type, *FLEXIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FLEXIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
+ * @{
+ */
+
+
+/* FLEXIO - Register accessors */
+#define FLEXIO_VERID_REG(base) ((base)->VERID)
+#define FLEXIO_PARAM_REG(base) ((base)->PARAM)
+#define FLEXIO_CTRL_REG(base) ((base)->CTRL)
+#define FLEXIO_SHIFTSTAT_REG(base) ((base)->SHIFTSTAT)
+#define FLEXIO_SHIFTERR_REG(base) ((base)->SHIFTERR)
+#define FLEXIO_TIMSTAT_REG(base) ((base)->TIMSTAT)
+#define FLEXIO_SHIFTSIEN_REG(base) ((base)->SHIFTSIEN)
+#define FLEXIO_SHIFTEIEN_REG(base) ((base)->SHIFTEIEN)
+#define FLEXIO_TIMIEN_REG(base) ((base)->TIMIEN)
+#define FLEXIO_SHIFTSDEN_REG(base) ((base)->SHIFTSDEN)
+#define FLEXIO_SHIFTCTL_REG(base,index) ((base)->SHIFTCTL[index])
+#define FLEXIO_SHIFTCFG_REG(base,index) ((base)->SHIFTCFG[index])
+#define FLEXIO_SHIFTBUF_REG(base,index) ((base)->SHIFTBUF[index])
+#define FLEXIO_SHIFTBUFBBS_REG(base,index) ((base)->SHIFTBUFBBS[index])
+#define FLEXIO_SHIFTBUFBYS_REG(base,index) ((base)->SHIFTBUFBYS[index])
+#define FLEXIO_SHIFTBUFBIS_REG(base,index) ((base)->SHIFTBUFBIS[index])
+#define FLEXIO_TIMCTL_REG(base,index) ((base)->TIMCTL[index])
+#define FLEXIO_TIMCFG_REG(base,index) ((base)->TIMCFG[index])
+#define FLEXIO_TIMCMP_REG(base,index) ((base)->TIMCMP[index])
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FLEXIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
+ * @{
+ */
+
+/* VERID Bit Fields */
+#define FLEXIO_VERID_FEATURE_MASK 0xFFFFu
+#define FLEXIO_VERID_FEATURE_SHIFT 0
+#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
+#define FLEXIO_VERID_MINOR_MASK 0xFF0000u
+#define FLEXIO_VERID_MINOR_SHIFT 16
+#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
+#define FLEXIO_VERID_MAJOR_MASK 0xFF000000u
+#define FLEXIO_VERID_MAJOR_SHIFT 24
+#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
+/* PARAM Bit Fields */
+#define FLEXIO_PARAM_SHIFTER_MASK 0xFFu
+#define FLEXIO_PARAM_SHIFTER_SHIFT 0
+#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
+#define FLEXIO_PARAM_TIMER_MASK 0xFF00u
+#define FLEXIO_PARAM_TIMER_SHIFT 8
+#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
+#define FLEXIO_PARAM_PIN_MASK 0xFF0000u
+#define FLEXIO_PARAM_PIN_SHIFT 16
+#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
+#define FLEXIO_PARAM_TRIGGER_MASK 0xFF000000u
+#define FLEXIO_PARAM_TRIGGER_SHIFT 24
+#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
+/* CTRL Bit Fields */
+#define FLEXIO_CTRL_FLEXEN_MASK 0x1u
+#define FLEXIO_CTRL_FLEXEN_SHIFT 0
+#define FLEXIO_CTRL_SWRST_MASK 0x2u
+#define FLEXIO_CTRL_SWRST_SHIFT 1
+#define FLEXIO_CTRL_FASTACC_MASK 0x4u
+#define FLEXIO_CTRL_FASTACC_SHIFT 2
+#define FLEXIO_CTRL_DBGE_MASK 0x40000000u
+#define FLEXIO_CTRL_DBGE_SHIFT 30
+#define FLEXIO_CTRL_DOZEN_MASK 0x80000000u
+#define FLEXIO_CTRL_DOZEN_SHIFT 31
+/* SHIFTSTAT Bit Fields */
+#define FLEXIO_SHIFTSTAT_SSF_MASK 0xFu
+#define FLEXIO_SHIFTSTAT_SSF_SHIFT 0
+#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
+/* SHIFTERR Bit Fields */
+#define FLEXIO_SHIFTERR_SEF_MASK 0xFu
+#define FLEXIO_SHIFTERR_SEF_SHIFT 0
+#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
+/* TIMSTAT Bit Fields */
+#define FLEXIO_TIMSTAT_TSF_MASK 0xFu
+#define FLEXIO_TIMSTAT_TSF_SHIFT 0
+#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
+/* SHIFTSIEN Bit Fields */
+#define FLEXIO_SHIFTSIEN_SSIE_MASK 0xFu
+#define FLEXIO_SHIFTSIEN_SSIE_SHIFT 0
+#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
+/* SHIFTEIEN Bit Fields */
+#define FLEXIO_SHIFTEIEN_SEIE_MASK 0xFu
+#define FLEXIO_SHIFTEIEN_SEIE_SHIFT 0
+#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
+/* TIMIEN Bit Fields */
+#define FLEXIO_TIMIEN_TEIE_MASK 0xFu
+#define FLEXIO_TIMIEN_TEIE_SHIFT 0
+#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
+/* SHIFTSDEN Bit Fields */
+#define FLEXIO_SHIFTSDEN_SSDE_MASK 0xFu
+#define FLEXIO_SHIFTSDEN_SSDE_SHIFT 0
+#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
+/* SHIFTCTL Bit Fields */
+#define FLEXIO_SHIFTCTL_SMOD_MASK 0x7u
+#define FLEXIO_SHIFTCTL_SMOD_SHIFT 0
+#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
+#define FLEXIO_SHIFTCTL_PINPOL_MASK 0x80u
+#define FLEXIO_SHIFTCTL_PINPOL_SHIFT 7
+#define FLEXIO_SHIFTCTL_PINSEL_MASK 0x700u
+#define FLEXIO_SHIFTCTL_PINSEL_SHIFT 8
+#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
+#define FLEXIO_SHIFTCTL_PINCFG_MASK 0x30000u
+#define FLEXIO_SHIFTCTL_PINCFG_SHIFT 16
+#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
+#define FLEXIO_SHIFTCTL_TIMPOL_MASK 0x800000u
+#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT 23
+#define FLEXIO_SHIFTCTL_TIMSEL_MASK 0x3000000u
+#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT 24
+#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
+/* SHIFTCFG Bit Fields */
+#define FLEXIO_SHIFTCFG_SSTART_MASK 0x3u
+#define FLEXIO_SHIFTCFG_SSTART_SHIFT 0
+#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
+#define FLEXIO_SHIFTCFG_SSTOP_MASK 0x30u
+#define FLEXIO_SHIFTCFG_SSTOP_SHIFT 4
+#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
+#define FLEXIO_SHIFTCFG_INSRC_MASK 0x100u
+#define FLEXIO_SHIFTCFG_INSRC_SHIFT 8
+/* SHIFTBUF Bit Fields */
+#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK 0xFFFFFFFFu
+#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT 0
+#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
+/* SHIFTBUFBBS Bit Fields */
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK 0xFFFFFFFFu
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT 0
+#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
+/* SHIFTBUFBYS Bit Fields */
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK 0xFFFFFFFFu
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT 0
+#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
+/* SHIFTBUFBIS Bit Fields */
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK 0xFFFFFFFFu
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT 0
+#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
+/* TIMCTL Bit Fields */
+#define FLEXIO_TIMCTL_TIMOD_MASK 0x3u
+#define FLEXIO_TIMCTL_TIMOD_SHIFT 0
+#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
+#define FLEXIO_TIMCTL_PINPOL_MASK 0x80u
+#define FLEXIO_TIMCTL_PINPOL_SHIFT 7
+#define FLEXIO_TIMCTL_PINSEL_MASK 0x700u
+#define FLEXIO_TIMCTL_PINSEL_SHIFT 8
+#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
+#define FLEXIO_TIMCTL_PINCFG_MASK 0x30000u
+#define FLEXIO_TIMCTL_PINCFG_SHIFT 16
+#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
+#define FLEXIO_TIMCTL_TRGSRC_MASK 0x400000u
+#define FLEXIO_TIMCTL_TRGSRC_SHIFT 22
+#define FLEXIO_TIMCTL_TRGPOL_MASK 0x800000u
+#define FLEXIO_TIMCTL_TRGPOL_SHIFT 23
+#define FLEXIO_TIMCTL_TRGSEL_MASK 0xF000000u
+#define FLEXIO_TIMCTL_TRGSEL_SHIFT 24
+#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
+/* TIMCFG Bit Fields */
+#define FLEXIO_TIMCFG_TSTART_MASK 0x2u
+#define FLEXIO_TIMCFG_TSTART_SHIFT 1
+#define FLEXIO_TIMCFG_TSTOP_MASK 0x30u
+#define FLEXIO_TIMCFG_TSTOP_SHIFT 4
+#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
+#define FLEXIO_TIMCFG_TIMENA_MASK 0x700u
+#define FLEXIO_TIMCFG_TIMENA_SHIFT 8
+#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
+#define FLEXIO_TIMCFG_TIMDIS_MASK 0x7000u
+#define FLEXIO_TIMCFG_TIMDIS_SHIFT 12
+#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
+#define FLEXIO_TIMCFG_TIMRST_MASK 0x70000u
+#define FLEXIO_TIMCFG_TIMRST_SHIFT 16
+#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
+#define FLEXIO_TIMCFG_TIMDEC_MASK 0x300000u
+#define FLEXIO_TIMCFG_TIMDEC_SHIFT 20
+#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
+#define FLEXIO_TIMCFG_TIMOUT_MASK 0x3000000u
+#define FLEXIO_TIMCFG_TIMOUT_SHIFT 24
+#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
+/* TIMCMP Bit Fields */
+#define FLEXIO_TIMCMP_CMP_MASK 0xFFFFu
+#define FLEXIO_TIMCMP_CMP_SHIFT 0
+#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Masks */
+
+
+/* FLEXIO - Peripheral instance base addresses */
+/** Peripheral FLEXIO base address */
+#define FLEXIO_BASE (0x4005F000u)
+/** Peripheral FLEXIO base pointer */
+#define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
+#define FLEXIO_BASE_PTR (FLEXIO)
+/** Array initializer of FLEXIO peripheral base addresses */
+#define FLEXIO_BASE_ADDRS { FLEXIO_BASE }
+/** Array initializer of FLEXIO peripheral base pointers */
+#define FLEXIO_BASE_PTRS { FLEXIO }
+
+/* ----------------------------------------------------------------------------
+ -- FLEXIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
+ * @{
+ */
+
+
+/* FLEXIO - Register instance definitions */
+/* FLEXIO */
+#define FLEXIO_VERID FLEXIO_VERID_REG(FLEXIO)
+#define FLEXIO_PARAM FLEXIO_PARAM_REG(FLEXIO)
+#define FLEXIO_CTRL FLEXIO_CTRL_REG(FLEXIO)
+#define FLEXIO_SHIFTSTAT FLEXIO_SHIFTSTAT_REG(FLEXIO)
+#define FLEXIO_SHIFTERR FLEXIO_SHIFTERR_REG(FLEXIO)
+#define FLEXIO_TIMSTAT FLEXIO_TIMSTAT_REG(FLEXIO)
+#define FLEXIO_SHIFTSIEN FLEXIO_SHIFTSIEN_REG(FLEXIO)
+#define FLEXIO_SHIFTEIEN FLEXIO_SHIFTEIEN_REG(FLEXIO)
+#define FLEXIO_TIMIEN FLEXIO_TIMIEN_REG(FLEXIO)
+#define FLEXIO_SHIFTSDEN FLEXIO_SHIFTSDEN_REG(FLEXIO)
+#define FLEXIO_SHIFTCTL0 FLEXIO_SHIFTCTL_REG(FLEXIO,0)
+#define FLEXIO_SHIFTCTL1 FLEXIO_SHIFTCTL_REG(FLEXIO,1)
+#define FLEXIO_SHIFTCTL2 FLEXIO_SHIFTCTL_REG(FLEXIO,2)
+#define FLEXIO_SHIFTCTL3 FLEXIO_SHIFTCTL_REG(FLEXIO,3)
+#define FLEXIO_SHIFTCFG0 FLEXIO_SHIFTCFG_REG(FLEXIO,0)
+#define FLEXIO_SHIFTCFG1 FLEXIO_SHIFTCFG_REG(FLEXIO,1)
+#define FLEXIO_SHIFTCFG2 FLEXIO_SHIFTCFG_REG(FLEXIO,2)
+#define FLEXIO_SHIFTCFG3 FLEXIO_SHIFTCFG_REG(FLEXIO,3)
+#define FLEXIO_SHIFTBUF0 FLEXIO_SHIFTBUF_REG(FLEXIO,0)
+#define FLEXIO_SHIFTBUF1 FLEXIO_SHIFTBUF_REG(FLEXIO,1)
+#define FLEXIO_SHIFTBUF2 FLEXIO_SHIFTBUF_REG(FLEXIO,2)
+#define FLEXIO_SHIFTBUF3 FLEXIO_SHIFTBUF_REG(FLEXIO,3)
+#define FLEXIO_SHIFTBUFBBS0 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,0)
+#define FLEXIO_SHIFTBUFBBS1 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,1)
+#define FLEXIO_SHIFTBUFBBS2 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,2)
+#define FLEXIO_SHIFTBUFBBS3 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,3)
+#define FLEXIO_SHIFTBUFBYS0 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,0)
+#define FLEXIO_SHIFTBUFBYS1 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,1)
+#define FLEXIO_SHIFTBUFBYS2 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,2)
+#define FLEXIO_SHIFTBUFBYS3 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,3)
+#define FLEXIO_SHIFTBUFBIS0 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,0)
+#define FLEXIO_SHIFTBUFBIS1 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,1)
+#define FLEXIO_SHIFTBUFBIS2 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,2)
+#define FLEXIO_SHIFTBUFBIS3 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,3)
+#define FLEXIO_TIMCTL0 FLEXIO_TIMCTL_REG(FLEXIO,0)
+#define FLEXIO_TIMCTL1 FLEXIO_TIMCTL_REG(FLEXIO,1)
+#define FLEXIO_TIMCTL2 FLEXIO_TIMCTL_REG(FLEXIO,2)
+#define FLEXIO_TIMCTL3 FLEXIO_TIMCTL_REG(FLEXIO,3)
+#define FLEXIO_TIMCFG0 FLEXIO_TIMCFG_REG(FLEXIO,0)
+#define FLEXIO_TIMCFG1 FLEXIO_TIMCFG_REG(FLEXIO,1)
+#define FLEXIO_TIMCFG2 FLEXIO_TIMCFG_REG(FLEXIO,2)
+#define FLEXIO_TIMCFG3 FLEXIO_TIMCFG_REG(FLEXIO,3)
+#define FLEXIO_TIMCMP0 FLEXIO_TIMCMP_REG(FLEXIO,0)
+#define FLEXIO_TIMCMP1 FLEXIO_TIMCMP_REG(FLEXIO,1)
+#define FLEXIO_TIMCMP2 FLEXIO_TIMCMP_REG(FLEXIO,2)
+#define FLEXIO_TIMCMP3 FLEXIO_TIMCMP_REG(FLEXIO,3)
+
+/* FLEXIO - Register array accessors */
+#define FLEXIO_SHIFTCTL(index) FLEXIO_SHIFTCTL_REG(FLEXIO,index)
+#define FLEXIO_SHIFTCFG(index) FLEXIO_SHIFTCFG_REG(FLEXIO,index)
+#define FLEXIO_SHIFTBUF(index) FLEXIO_SHIFTBUF_REG(FLEXIO,index)
+#define FLEXIO_SHIFTBUFBBS(index) FLEXIO_SHIFTBUFBBS_REG(FLEXIO,index)
+#define FLEXIO_SHIFTBUFBYS(index) FLEXIO_SHIFTBUFBYS_REG(FLEXIO,index)
+#define FLEXIO_SHIFTBUFBIS(index) FLEXIO_SHIFTBUFBIS_REG(FLEXIO,index)
+#define FLEXIO_TIMCTL(index) FLEXIO_TIMCTL_REG(FLEXIO,index)
+#define FLEXIO_TIMCFG(index) FLEXIO_TIMCFG_REG(FLEXIO,index)
+#define FLEXIO_TIMCMP(index) FLEXIO_TIMCMP_REG(FLEXIO,index)
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FLEXIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+} FTFA_Type, *FTFA_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- FTFA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
+ * @{
+ */
+
+
+/* FTFA - Register accessors */
+#define FTFA_FSTAT_REG(base) ((base)->FSTAT)
+#define FTFA_FCNFG_REG(base) ((base)->FCNFG)
+#define FTFA_FSEC_REG(base) ((base)->FSEC)
+#define FTFA_FOPT_REG(base) ((base)->FOPT)
+#define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
+#define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
+#define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
+#define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
+#define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
+#define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
+#define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
+#define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
+#define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
+#define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
+#define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
+#define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
+#define FTFA_FPROT3_REG(base) ((base)->FPROT3)
+#define FTFA_FPROT2_REG(base) ((base)->FPROT2)
+#define FTFA_FPROT1_REG(base) ((base)->FPROT1)
+#define FTFA_FPROT0_REG(base) ((base)->FPROT0)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFA_FSTAT_MGSTAT0_SHIFT 0
+#define FTFA_FSTAT_FPVIOL_MASK 0x10u
+#define FTFA_FSTAT_FPVIOL_SHIFT 4
+#define FTFA_FSTAT_ACCERR_MASK 0x20u
+#define FTFA_FSTAT_ACCERR_SHIFT 5
+#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFA_FSTAT_RDCOLERR_SHIFT 6
+#define FTFA_FSTAT_CCIF_MASK 0x80u
+#define FTFA_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFA_FCNFG_ERSSUSP_SHIFT 4
+#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFA_FCNFG_ERSAREQ_SHIFT 5
+#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFA_FCNFG_CCIE_MASK 0x80u
+#define FTFA_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFA_FSEC_SEC_MASK 0x3u
+#define FTFA_FSEC_SEC_SHIFT 0
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK 0xCu
+#define FTFA_FSEC_FSLACC_SHIFT 2
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK 0x30u
+#define FTFA_FSEC_MEEN_SHIFT 4
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK 0xC0u
+#define FTFA_FSEC_KEYEN_SHIFT 6
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFA_FOPT_OPT_MASK 0xFFu
+#define FTFA_FOPT_OPT_SHIFT 0
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB3_CCOBn_SHIFT 0
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB2_CCOBn_SHIFT 0
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB1_CCOBn_SHIFT 0
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB0_CCOBn_SHIFT 0
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB7_CCOBn_SHIFT 0
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB6_CCOBn_SHIFT 0
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB5_CCOBn_SHIFT 0
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB4_CCOBn_SHIFT 0
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBB_CCOBn_SHIFT 0
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBA_CCOBn_SHIFT 0
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB9_CCOBn_SHIFT 0
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB8_CCOBn_SHIFT 0
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFA_FPROT3_PROT_MASK 0xFFu
+#define FTFA_FPROT3_PROT_SHIFT 0
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFA_FPROT2_PROT_MASK 0xFFu
+#define FTFA_FPROT2_PROT_SHIFT 0
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFA_FPROT1_PROT_MASK 0xFFu
+#define FTFA_FPROT1_PROT_SHIFT 0
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFA_FPROT0_PROT_MASK 0xFFu
+#define FTFA_FPROT0_PROT_SHIFT 0
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA ((FTFA_Type *)FTFA_BASE)
+#define FTFA_BASE_PTR (FTFA)
+/** Array initializer of FTFA peripheral base addresses */
+#define FTFA_BASE_ADDRS { FTFA_BASE }
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASE_PTRS { FTFA }
+/** Interrupt vectors for the FTFA peripheral type */
+#define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- FTFA - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
+ * @{
+ */
+
+
+/* FTFA - Register instance definitions */
+/* FTFA */
+#define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
+#define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
+#define FTFA_FSEC FTFA_FSEC_REG(FTFA)
+#define FTFA_FOPT FTFA_FOPT_REG(FTFA)
+#define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
+#define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
+#define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
+#define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
+#define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
+#define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
+#define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
+#define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
+#define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
+#define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
+#define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
+#define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
+#define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
+#define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
+#define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
+#define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type, *GPIO_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register accessors */
+#define GPIO_PDOR_REG(base) ((base)->PDOR)
+#define GPIO_PSOR_REG(base) ((base)->PSOR)
+#define GPIO_PCOR_REG(base) ((base)->PCOR)
+#define GPIO_PTOR_REG(base) ((base)->PTOR)
+#define GPIO_PDIR_REG(base) ((base)->PDIR)
+#define GPIO_PDDR_REG(base) ((base)->PDDR)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA ((GPIO_Type *)GPIOA_BASE)
+#define GPIOA_BASE_PTR (GPIOA)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB ((GPIO_Type *)GPIOB_BASE)
+#define GPIOB_BASE_PTR (GPIOB)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE (0x400FF080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC ((GPIO_Type *)GPIOC_BASE)
+#define GPIOC_BASE_PTR (GPIOC)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE (0x400FF0C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD ((GPIO_Type *)GPIOD_BASE)
+#define GPIOD_BASE_PTR (GPIOD)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE (0x400FF100u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE ((GPIO_Type *)GPIOE_BASE)
+#define GPIOE_BASE_PTR (GPIOE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
+
+/* ----------------------------------------------------------------------------
+ -- GPIO - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
+ * @{
+ */
+
+
+/* GPIO - Register instance definitions */
+/* GPIOA */
+#define GPIOA_PDOR GPIO_PDOR_REG(GPIOA)
+#define GPIOA_PSOR GPIO_PSOR_REG(GPIOA)
+#define GPIOA_PCOR GPIO_PCOR_REG(GPIOA)
+#define GPIOA_PTOR GPIO_PTOR_REG(GPIOA)
+#define GPIOA_PDIR GPIO_PDIR_REG(GPIOA)
+#define GPIOA_PDDR GPIO_PDDR_REG(GPIOA)
+/* GPIOB */
+#define GPIOB_PDOR GPIO_PDOR_REG(GPIOB)
+#define GPIOB_PSOR GPIO_PSOR_REG(GPIOB)
+#define GPIOB_PCOR GPIO_PCOR_REG(GPIOB)
+#define GPIOB_PTOR GPIO_PTOR_REG(GPIOB)
+#define GPIOB_PDIR GPIO_PDIR_REG(GPIOB)
+#define GPIOB_PDDR GPIO_PDDR_REG(GPIOB)
+/* GPIOC */
+#define GPIOC_PDOR GPIO_PDOR_REG(GPIOC)
+#define GPIOC_PSOR GPIO_PSOR_REG(GPIOC)
+#define GPIOC_PCOR GPIO_PCOR_REG(GPIOC)
+#define GPIOC_PTOR GPIO_PTOR_REG(GPIOC)
+#define GPIOC_PDIR GPIO_PDIR_REG(GPIOC)
+#define GPIOC_PDDR GPIO_PDDR_REG(GPIOC)
+/* GPIOD */
+#define GPIOD_PDOR GPIO_PDOR_REG(GPIOD)
+#define GPIOD_PSOR GPIO_PSOR_REG(GPIOD)
+#define GPIOD_PCOR GPIO_PCOR_REG(GPIOD)
+#define GPIOD_PTOR GPIO_PTOR_REG(GPIOD)
+#define GPIOD_PDIR GPIO_PDIR_REG(GPIOD)
+#define GPIOD_PDDR GPIO_PDDR_REG(GPIOD)
+/* GPIOE */
+#define GPIOE_PDOR GPIO_PDOR_REG(GPIOE)
+#define GPIOE_PSOR GPIO_PSOR_REG(GPIOE)
+#define GPIOE_PCOR GPIO_PCOR_REG(GPIOE)
+#define GPIOE_PTOR GPIO_PTOR_REG(GPIOE)
+#define GPIOE_PDIR GPIO_PDIR_REG(GPIOE)
+#define GPIOE_PDDR GPIO_PDDR_REG(GPIOE)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+ __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */
+} I2C_Type, *I2C_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- I2C - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register accessors */
+#define I2C_A1_REG(base) ((base)->A1)
+#define I2C_F_REG(base) ((base)->F)
+#define I2C_C1_REG(base) ((base)->C1)
+#define I2C_S_REG(base) ((base)->S)
+#define I2C_D_REG(base) ((base)->D)
+#define I2C_C2_REG(base) ((base)->C2)
+#define I2C_FLT_REG(base) ((base)->FLT)
+#define I2C_RA_REG(base) ((base)->RA)
+#define I2C_SMB_REG(base) ((base)->SMB)
+#define I2C_A2_REG(base) ((base)->A2)
+#define I2C_SLTH_REG(base) ((base)->SLTH)
+#define I2C_SLTL_REG(base) ((base)->SLTL)
+#define I2C_S2_REG(base) ((base)->S2)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0xFu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK 0x10u
+#define I2C_FLT_STARTF_SHIFT 4
+#define I2C_FLT_SSIE_MASK 0x20u
+#define I2C_FLT_SSIE_SHIFT 5
+#define I2C_FLT_STOPF_MASK 0x40u
+#define I2C_FLT_STOPF_SHIFT 6
+#define I2C_FLT_SHEN_MASK 0x80u
+#define I2C_FLT_SHEN_SHIFT 7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+/* S2 Bit Fields */
+#define I2C_S2_EMPTY_MASK 0x1u
+#define I2C_S2_EMPTY_SHIFT 0
+#define I2C_S2_ERROR_MASK 0x2u
+#define I2C_S2_ERROR_SHIFT 1
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+#define I2C0_BASE_PTR (I2C0)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+#define I2C1_BASE_PTR (I2C1)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS { I2C0, I2C1 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- I2C - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
+ * @{
+ */
+
+
+/* I2C - Register instance definitions */
+/* I2C0 */
+#define I2C0_A1 I2C_A1_REG(I2C0)
+#define I2C0_F I2C_F_REG(I2C0)
+#define I2C0_C1 I2C_C1_REG(I2C0)
+#define I2C0_S I2C_S_REG(I2C0)
+#define I2C0_D I2C_D_REG(I2C0)
+#define I2C0_C2 I2C_C2_REG(I2C0)
+#define I2C0_FLT I2C_FLT_REG(I2C0)
+#define I2C0_RA I2C_RA_REG(I2C0)
+#define I2C0_SMB I2C_SMB_REG(I2C0)
+#define I2C0_A2 I2C_A2_REG(I2C0)
+#define I2C0_SLTH I2C_SLTH_REG(I2C0)
+#define I2C0_SLTL I2C_SLTL_REG(I2C0)
+#define I2C0_S2 I2C_S2_REG(I2C0)
+/* I2C1 */
+#define I2C1_A1 I2C_A1_REG(I2C1)
+#define I2C1_F I2C_F_REG(I2C1)
+#define I2C1_C1 I2C_C1_REG(I2C1)
+#define I2C1_S I2C_S_REG(I2C1)
+#define I2C1_D I2C_D_REG(I2C1)
+#define I2C1_C2 I2C_C2_REG(I2C1)
+#define I2C1_FLT I2C_FLT_REG(I2C1)
+#define I2C1_RA I2C_RA_REG(I2C1)
+#define I2C1_SMB I2C_SMB_REG(I2C1)
+#define I2C1_A2 I2C_A2_REG(I2C1)
+#define I2C1_SLTH I2C_SLTH_REG(I2C1)
+#define I2C1_SLTL I2C_SLTL_REG(I2C1)
+#define I2C1_S2 I2C_S2_REG(I2C1)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_1[8];
+ __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_2[60];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_5[8];
+ __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_6[60];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+} I2S_Type, *I2S_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- I2S - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register accessors */
+#define I2S_TCSR_REG(base) ((base)->TCSR)
+#define I2S_TCR2_REG(base) ((base)->TCR2)
+#define I2S_TCR3_REG(base) ((base)->TCR3)
+#define I2S_TCR4_REG(base) ((base)->TCR4)
+#define I2S_TCR5_REG(base) ((base)->TCR5)
+#define I2S_TDR_REG(base,index) ((base)->TDR[index])
+#define I2S_TMR_REG(base) ((base)->TMR)
+#define I2S_RCSR_REG(base) ((base)->RCSR)
+#define I2S_RCR2_REG(base) ((base)->RCR2)
+#define I2S_RCR3_REG(base) ((base)->RCR3)
+#define I2S_RCR4_REG(base) ((base)->RCR4)
+#define I2S_RCR5_REG(base) ((base)->RCR5)
+#define I2S_RDR_REG(base,index) ((base)->RDR[index])
+#define I2S_RMR_REG(base) ((base)->RMR)
+#define I2S_MCR_REG(base) ((base)->MCR)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FWDE_MASK 0x2u
+#define I2S_TCSR_FWDE_SHIFT 1
+#define I2S_TCSR_FWIE_MASK 0x200u
+#define I2S_TCSR_FWIE_SHIFT 9
+#define I2S_TCSR_FEIE_MASK 0x400u
+#define I2S_TCSR_FEIE_SHIFT 10
+#define I2S_TCSR_SEIE_MASK 0x800u
+#define I2S_TCSR_SEIE_SHIFT 11
+#define I2S_TCSR_WSIE_MASK 0x1000u
+#define I2S_TCSR_WSIE_SHIFT 12
+#define I2S_TCSR_FWF_MASK 0x20000u
+#define I2S_TCSR_FWF_SHIFT 17
+#define I2S_TCSR_FEF_MASK 0x40000u
+#define I2S_TCSR_FEF_SHIFT 18
+#define I2S_TCSR_SEF_MASK 0x80000u
+#define I2S_TCSR_SEF_SHIFT 19
+#define I2S_TCSR_WSF_MASK 0x100000u
+#define I2S_TCSR_WSF_SHIFT 20
+#define I2S_TCSR_SR_MASK 0x1000000u
+#define I2S_TCSR_SR_SHIFT 24
+#define I2S_TCSR_FR_MASK 0x2000000u
+#define I2S_TCSR_FR_SHIFT 25
+#define I2S_TCSR_BCE_MASK 0x10000000u
+#define I2S_TCSR_BCE_SHIFT 28
+#define I2S_TCSR_DBGE_MASK 0x20000000u
+#define I2S_TCSR_DBGE_SHIFT 29
+#define I2S_TCSR_STOPE_MASK 0x40000000u
+#define I2S_TCSR_STOPE_SHIFT 30
+#define I2S_TCSR_TE_MASK 0x80000000u
+#define I2S_TCSR_TE_SHIFT 31
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK 0xFFu
+#define I2S_TCR2_DIV_SHIFT 0
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK 0x1000000u
+#define I2S_TCR2_BCD_SHIFT 24
+#define I2S_TCR2_BCP_MASK 0x2000000u
+#define I2S_TCR2_BCP_SHIFT 25
+#define I2S_TCR2_MSEL_MASK 0xC000000u
+#define I2S_TCR2_MSEL_SHIFT 26
+#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK 0x10000000u
+#define I2S_TCR2_BCI_SHIFT 28
+#define I2S_TCR2_BCS_MASK 0x20000000u
+#define I2S_TCR2_BCS_SHIFT 29
+#define I2S_TCR2_SYNC_MASK 0xC0000000u
+#define I2S_TCR2_SYNC_SHIFT 30
+#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK 0x1u
+#define I2S_TCR3_WDFL_SHIFT 0
+#define I2S_TCR3_TCE_MASK 0x10000u
+#define I2S_TCR3_TCE_SHIFT 16
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK 0x1u
+#define I2S_TCR4_FSD_SHIFT 0
+#define I2S_TCR4_FSP_MASK 0x2u
+#define I2S_TCR4_FSP_SHIFT 1
+#define I2S_TCR4_ONDEM_MASK 0x4u
+#define I2S_TCR4_ONDEM_SHIFT 2
+#define I2S_TCR4_FSE_MASK 0x8u
+#define I2S_TCR4_FSE_SHIFT 3
+#define I2S_TCR4_MF_MASK 0x10u
+#define I2S_TCR4_MF_SHIFT 4
+#define I2S_TCR4_SYWD_MASK 0x1F00u
+#define I2S_TCR4_SYWD_SHIFT 8
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK 0x10000u
+#define I2S_TCR4_FRSZ_SHIFT 16
+#define I2S_TCR4_FPACK_MASK 0x3000000u
+#define I2S_TCR4_FPACK_SHIFT 24
+#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
+#define I2S_TCR4_FCONT_MASK 0x10000000u
+#define I2S_TCR4_FCONT_SHIFT 28
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK 0x1F00u
+#define I2S_TCR5_FBT_SHIFT 8
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK 0x1F0000u
+#define I2S_TCR5_W0W_SHIFT 16
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK 0x1F000000u
+#define I2S_TCR5_WNW_SHIFT 24
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT 0
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK 0x3u
+#define I2S_TMR_TWM_SHIFT 0
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FWDE_MASK 0x2u
+#define I2S_RCSR_FWDE_SHIFT 1
+#define I2S_RCSR_FWIE_MASK 0x200u
+#define I2S_RCSR_FWIE_SHIFT 9
+#define I2S_RCSR_FEIE_MASK 0x400u
+#define I2S_RCSR_FEIE_SHIFT 10
+#define I2S_RCSR_SEIE_MASK 0x800u
+#define I2S_RCSR_SEIE_SHIFT 11
+#define I2S_RCSR_WSIE_MASK 0x1000u
+#define I2S_RCSR_WSIE_SHIFT 12
+#define I2S_RCSR_FWF_MASK 0x20000u
+#define I2S_RCSR_FWF_SHIFT 17
+#define I2S_RCSR_FEF_MASK 0x40000u
+#define I2S_RCSR_FEF_SHIFT 18
+#define I2S_RCSR_SEF_MASK 0x80000u
+#define I2S_RCSR_SEF_SHIFT 19
+#define I2S_RCSR_WSF_MASK 0x100000u
+#define I2S_RCSR_WSF_SHIFT 20
+#define I2S_RCSR_SR_MASK 0x1000000u
+#define I2S_RCSR_SR_SHIFT 24
+#define I2S_RCSR_FR_MASK 0x2000000u
+#define I2S_RCSR_FR_SHIFT 25
+#define I2S_RCSR_BCE_MASK 0x10000000u
+#define I2S_RCSR_BCE_SHIFT 28
+#define I2S_RCSR_DBGE_MASK 0x20000000u
+#define I2S_RCSR_DBGE_SHIFT 29
+#define I2S_RCSR_STOPE_MASK 0x40000000u
+#define I2S_RCSR_STOPE_SHIFT 30
+#define I2S_RCSR_RE_MASK 0x80000000u
+#define I2S_RCSR_RE_SHIFT 31
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK 0xFFu
+#define I2S_RCR2_DIV_SHIFT 0
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK 0x1000000u
+#define I2S_RCR2_BCD_SHIFT 24
+#define I2S_RCR2_BCP_MASK 0x2000000u
+#define I2S_RCR2_BCP_SHIFT 25
+#define I2S_RCR2_MSEL_MASK 0xC000000u
+#define I2S_RCR2_MSEL_SHIFT 26
+#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK 0x10000000u
+#define I2S_RCR2_BCI_SHIFT 28
+#define I2S_RCR2_BCS_MASK 0x20000000u
+#define I2S_RCR2_BCS_SHIFT 29
+#define I2S_RCR2_SYNC_MASK 0xC0000000u
+#define I2S_RCR2_SYNC_SHIFT 30
+#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK 0x1u
+#define I2S_RCR3_WDFL_SHIFT 0
+#define I2S_RCR3_RCE_MASK 0x10000u
+#define I2S_RCR3_RCE_SHIFT 16
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK 0x1u
+#define I2S_RCR4_FSD_SHIFT 0
+#define I2S_RCR4_FSP_MASK 0x2u
+#define I2S_RCR4_FSP_SHIFT 1
+#define I2S_RCR4_ONDEM_MASK 0x4u
+#define I2S_RCR4_ONDEM_SHIFT 2
+#define I2S_RCR4_FSE_MASK 0x8u
+#define I2S_RCR4_FSE_SHIFT 3
+#define I2S_RCR4_MF_MASK 0x10u
+#define I2S_RCR4_MF_SHIFT 4
+#define I2S_RCR4_SYWD_MASK 0x1F00u
+#define I2S_RCR4_SYWD_SHIFT 8
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK 0x10000u
+#define I2S_RCR4_FRSZ_SHIFT 16
+#define I2S_RCR4_FPACK_MASK 0x3000000u
+#define I2S_RCR4_FPACK_SHIFT 24
+#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
+#define I2S_RCR4_FCONT_MASK 0x10000000u
+#define I2S_RCR4_FCONT_SHIFT 28
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK 0x1F00u
+#define I2S_RCR5_FBT_SHIFT 8
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK 0x1F0000u
+#define I2S_RCR5_W0W_SHIFT 16
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK 0x1F000000u
+#define I2S_RCR5_WNW_SHIFT 24
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT 0
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK 0x3u
+#define I2S_RMR_RWM_SHIFT 0
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK 0x3000000u
+#define I2S_MCR_MICS_SHIFT 24
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK 0x40000000u
+#define I2S_MCR_MOE_SHIFT 30
+#define I2S_MCR_DUF_MASK 0x80000000u
+#define I2S_MCR_DUF_SHIFT 31
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+#define I2S0_BASE_PTR (I2S0)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS { I2S0_IRQn }
+#define I2S_TX_IRQS { I2S0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- I2S - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
+ * @{
+ */
+
+
+/* I2S - Register instance definitions */
+/* I2S0 */
+#define I2S0_TCSR I2S_TCSR_REG(I2S0)
+#define I2S0_TCR2 I2S_TCR2_REG(I2S0)
+#define I2S0_TCR3 I2S_TCR3_REG(I2S0)
+#define I2S0_TCR4 I2S_TCR4_REG(I2S0)
+#define I2S0_TCR5 I2S_TCR5_REG(I2S0)
+#define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
+#define I2S0_TMR I2S_TMR_REG(I2S0)
+#define I2S0_RCSR I2S_RCSR_REG(I2S0)
+#define I2S0_RCR2 I2S_RCR2_REG(I2S0)
+#define I2S0_RCR3 I2S_RCR3_REG(I2S0)
+#define I2S0_RCR4 I2S_RCR4_REG(I2S0)
+#define I2S0_RCR5 I2S_RCR5_REG(I2S0)
+#define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
+#define I2S0_RMR I2S_RMR_REG(I2S0)
+#define I2S0_MCR I2S_MCR_REG(I2S0)
+
+/* I2S - Register array accessors */
+#define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
+#define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
+ * @{
+ */
+
+/** LCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */
+ __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */
+ __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */
+ __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */
+ __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
+ union { /* offset: 0x20 */
+ __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
+ __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
+ };
+} LCD_Type, *LCD_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LCD - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Register_Accessor_Macros LCD - Register accessor macros
+ * @{
+ */
+
+
+/* LCD - Register accessors */
+#define LCD_GCR_REG(base) ((base)->GCR)
+#define LCD_AR_REG(base) ((base)->AR)
+#define LCD_FDCR_REG(base) ((base)->FDCR)
+#define LCD_FDSR_REG(base) ((base)->FDSR)
+#define LCD_PEN_REG(base,index) ((base)->PEN[index])
+#define LCD_BPEN_REG(base,index) ((base)->BPEN[index])
+#define LCD_WF_REG(base,index2) ((base)->WF[index2])
+#define LCD_WF8B_REG(base,index2) ((base)->WF8B[index2])
+
+/*!
+ * @}
+ */ /* end of group LCD_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Register_Masks LCD Register Masks
+ * @{
+ */
+
+/* GCR Bit Fields */
+#define LCD_GCR_DUTY_MASK 0x7u
+#define LCD_GCR_DUTY_SHIFT 0
+#define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
+#define LCD_GCR_LCLK_MASK 0x38u
+#define LCD_GCR_LCLK_SHIFT 3
+#define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
+#define LCD_GCR_SOURCE_MASK 0x40u
+#define LCD_GCR_SOURCE_SHIFT 6
+#define LCD_GCR_LCDEN_MASK 0x80u
+#define LCD_GCR_LCDEN_SHIFT 7
+#define LCD_GCR_LCDSTP_MASK 0x100u
+#define LCD_GCR_LCDSTP_SHIFT 8
+#define LCD_GCR_LCDDOZE_MASK 0x200u
+#define LCD_GCR_LCDDOZE_SHIFT 9
+#define LCD_GCR_FFR_MASK 0x400u
+#define LCD_GCR_FFR_SHIFT 10
+#define LCD_GCR_ALTSOURCE_MASK 0x800u
+#define LCD_GCR_ALTSOURCE_SHIFT 11
+#define LCD_GCR_ALTDIV_MASK 0x3000u
+#define LCD_GCR_ALTDIV_SHIFT 12
+#define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
+#define LCD_GCR_FDCIEN_MASK 0x4000u
+#define LCD_GCR_FDCIEN_SHIFT 14
+#define LCD_GCR_PADSAFE_MASK 0x8000u
+#define LCD_GCR_PADSAFE_SHIFT 15
+#define LCD_GCR_VSUPPLY_MASK 0x20000u
+#define LCD_GCR_VSUPPLY_SHIFT 17
+#define LCD_GCR_LADJ_MASK 0x300000u
+#define LCD_GCR_LADJ_SHIFT 20
+#define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
+#define LCD_GCR_CPSEL_MASK 0x800000u
+#define LCD_GCR_CPSEL_SHIFT 23
+#define LCD_GCR_RVTRIM_MASK 0xF000000u
+#define LCD_GCR_RVTRIM_SHIFT 24
+#define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
+#define LCD_GCR_RVEN_MASK 0x80000000u
+#define LCD_GCR_RVEN_SHIFT 31
+/* AR Bit Fields */
+#define LCD_AR_BRATE_MASK 0x7u
+#define LCD_AR_BRATE_SHIFT 0
+#define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
+#define LCD_AR_BMODE_MASK 0x8u
+#define LCD_AR_BMODE_SHIFT 3
+#define LCD_AR_BLANK_MASK 0x20u
+#define LCD_AR_BLANK_SHIFT 5
+#define LCD_AR_ALT_MASK 0x40u
+#define LCD_AR_ALT_SHIFT 6
+#define LCD_AR_BLINK_MASK 0x80u
+#define LCD_AR_BLINK_SHIFT 7
+/* FDCR Bit Fields */
+#define LCD_FDCR_FDPINID_MASK 0x3Fu
+#define LCD_FDCR_FDPINID_SHIFT 0
+#define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
+#define LCD_FDCR_FDBPEN_MASK 0x40u
+#define LCD_FDCR_FDBPEN_SHIFT 6
+#define LCD_FDCR_FDEN_MASK 0x80u
+#define LCD_FDCR_FDEN_SHIFT 7
+#define LCD_FDCR_FDSWW_MASK 0xE00u
+#define LCD_FDCR_FDSWW_SHIFT 9
+#define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
+#define LCD_FDCR_FDPRS_MASK 0x7000u
+#define LCD_FDCR_FDPRS_SHIFT 12
+#define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
+/* FDSR Bit Fields */
+#define LCD_FDSR_FDCNT_MASK 0xFFu
+#define LCD_FDSR_FDCNT_SHIFT 0
+#define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
+#define LCD_FDSR_FDCF_MASK 0x8000u
+#define LCD_FDSR_FDCF_SHIFT 15
+/* PEN Bit Fields */
+#define LCD_PEN_PEN_MASK 0xFFFFFFFFu
+#define LCD_PEN_PEN_SHIFT 0
+#define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
+/* BPEN Bit Fields */
+#define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
+#define LCD_BPEN_BPEN_SHIFT 0
+#define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
+/* WF Bit Fields */
+#define LCD_WF_WF0_MASK 0xFFu
+#define LCD_WF_WF0_SHIFT 0
+#define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
+#define LCD_WF_WF60_MASK 0xFFu
+#define LCD_WF_WF60_SHIFT 0
+#define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
+#define LCD_WF_WF56_MASK 0xFFu
+#define LCD_WF_WF56_SHIFT 0
+#define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
+#define LCD_WF_WF52_MASK 0xFFu
+#define LCD_WF_WF52_SHIFT 0
+#define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
+#define LCD_WF_WF4_MASK 0xFFu
+#define LCD_WF_WF4_SHIFT 0
+#define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
+#define LCD_WF_WF48_MASK 0xFFu
+#define LCD_WF_WF48_SHIFT 0
+#define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
+#define LCD_WF_WF44_MASK 0xFFu
+#define LCD_WF_WF44_SHIFT 0
+#define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
+#define LCD_WF_WF40_MASK 0xFFu
+#define LCD_WF_WF40_SHIFT 0
+#define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
+#define LCD_WF_WF8_MASK 0xFFu
+#define LCD_WF_WF8_SHIFT 0
+#define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
+#define LCD_WF_WF36_MASK 0xFFu
+#define LCD_WF_WF36_SHIFT 0
+#define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
+#define LCD_WF_WF32_MASK 0xFFu
+#define LCD_WF_WF32_SHIFT 0
+#define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
+#define LCD_WF_WF28_MASK 0xFFu
+#define LCD_WF_WF28_SHIFT 0
+#define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
+#define LCD_WF_WF12_MASK 0xFFu
+#define LCD_WF_WF12_SHIFT 0
+#define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
+#define LCD_WF_WF24_MASK 0xFFu
+#define LCD_WF_WF24_SHIFT 0
+#define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
+#define LCD_WF_WF20_MASK 0xFFu
+#define LCD_WF_WF20_SHIFT 0
+#define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
+#define LCD_WF_WF16_MASK 0xFFu
+#define LCD_WF_WF16_SHIFT 0
+#define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
+#define LCD_WF_WF5_MASK 0xFF00u
+#define LCD_WF_WF5_SHIFT 8
+#define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
+#define LCD_WF_WF49_MASK 0xFF00u
+#define LCD_WF_WF49_SHIFT 8
+#define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
+#define LCD_WF_WF45_MASK 0xFF00u
+#define LCD_WF_WF45_SHIFT 8
+#define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
+#define LCD_WF_WF61_MASK 0xFF00u
+#define LCD_WF_WF61_SHIFT 8
+#define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
+#define LCD_WF_WF25_MASK 0xFF00u
+#define LCD_WF_WF25_SHIFT 8
+#define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
+#define LCD_WF_WF17_MASK 0xFF00u
+#define LCD_WF_WF17_SHIFT 8
+#define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
+#define LCD_WF_WF41_MASK 0xFF00u
+#define LCD_WF_WF41_SHIFT 8
+#define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
+#define LCD_WF_WF13_MASK 0xFF00u
+#define LCD_WF_WF13_SHIFT 8
+#define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
+#define LCD_WF_WF57_MASK 0xFF00u
+#define LCD_WF_WF57_SHIFT 8
+#define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
+#define LCD_WF_WF53_MASK 0xFF00u
+#define LCD_WF_WF53_SHIFT 8
+#define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
+#define LCD_WF_WF37_MASK 0xFF00u
+#define LCD_WF_WF37_SHIFT 8
+#define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
+#define LCD_WF_WF9_MASK 0xFF00u
+#define LCD_WF_WF9_SHIFT 8
+#define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
+#define LCD_WF_WF1_MASK 0xFF00u
+#define LCD_WF_WF1_SHIFT 8
+#define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
+#define LCD_WF_WF29_MASK 0xFF00u
+#define LCD_WF_WF29_SHIFT 8
+#define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
+#define LCD_WF_WF33_MASK 0xFF00u
+#define LCD_WF_WF33_SHIFT 8
+#define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
+#define LCD_WF_WF21_MASK 0xFF00u
+#define LCD_WF_WF21_SHIFT 8
+#define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
+#define LCD_WF_WF26_MASK 0xFF0000u
+#define LCD_WF_WF26_SHIFT 16
+#define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
+#define LCD_WF_WF46_MASK 0xFF0000u
+#define LCD_WF_WF46_SHIFT 16
+#define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
+#define LCD_WF_WF6_MASK 0xFF0000u
+#define LCD_WF_WF6_SHIFT 16
+#define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
+#define LCD_WF_WF42_MASK 0xFF0000u
+#define LCD_WF_WF42_SHIFT 16
+#define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
+#define LCD_WF_WF18_MASK 0xFF0000u
+#define LCD_WF_WF18_SHIFT 16
+#define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
+#define LCD_WF_WF38_MASK 0xFF0000u
+#define LCD_WF_WF38_SHIFT 16
+#define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
+#define LCD_WF_WF22_MASK 0xFF0000u
+#define LCD_WF_WF22_SHIFT 16
+#define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
+#define LCD_WF_WF34_MASK 0xFF0000u
+#define LCD_WF_WF34_SHIFT 16
+#define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
+#define LCD_WF_WF50_MASK 0xFF0000u
+#define LCD_WF_WF50_SHIFT 16
+#define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
+#define LCD_WF_WF14_MASK 0xFF0000u
+#define LCD_WF_WF14_SHIFT 16
+#define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
+#define LCD_WF_WF54_MASK 0xFF0000u
+#define LCD_WF_WF54_SHIFT 16
+#define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
+#define LCD_WF_WF2_MASK 0xFF0000u
+#define LCD_WF_WF2_SHIFT 16
+#define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
+#define LCD_WF_WF58_MASK 0xFF0000u
+#define LCD_WF_WF58_SHIFT 16
+#define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
+#define LCD_WF_WF30_MASK 0xFF0000u
+#define LCD_WF_WF30_SHIFT 16
+#define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
+#define LCD_WF_WF62_MASK 0xFF0000u
+#define LCD_WF_WF62_SHIFT 16
+#define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
+#define LCD_WF_WF10_MASK 0xFF0000u
+#define LCD_WF_WF10_SHIFT 16
+#define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
+#define LCD_WF_WF63_MASK 0xFF000000u
+#define LCD_WF_WF63_SHIFT 24
+#define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
+#define LCD_WF_WF59_MASK 0xFF000000u
+#define LCD_WF_WF59_SHIFT 24
+#define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
+#define LCD_WF_WF55_MASK 0xFF000000u
+#define LCD_WF_WF55_SHIFT 24
+#define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
+#define LCD_WF_WF3_MASK 0xFF000000u
+#define LCD_WF_WF3_SHIFT 24
+#define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
+#define LCD_WF_WF51_MASK 0xFF000000u
+#define LCD_WF_WF51_SHIFT 24
+#define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
+#define LCD_WF_WF47_MASK 0xFF000000u
+#define LCD_WF_WF47_SHIFT 24
+#define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
+#define LCD_WF_WF43_MASK 0xFF000000u
+#define LCD_WF_WF43_SHIFT 24
+#define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
+#define LCD_WF_WF7_MASK 0xFF000000u
+#define LCD_WF_WF7_SHIFT 24
+#define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
+#define LCD_WF_WF39_MASK 0xFF000000u
+#define LCD_WF_WF39_SHIFT 24
+#define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
+#define LCD_WF_WF35_MASK 0xFF000000u
+#define LCD_WF_WF35_SHIFT 24
+#define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
+#define LCD_WF_WF31_MASK 0xFF000000u
+#define LCD_WF_WF31_SHIFT 24
+#define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
+#define LCD_WF_WF11_MASK 0xFF000000u
+#define LCD_WF_WF11_SHIFT 24
+#define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
+#define LCD_WF_WF27_MASK 0xFF000000u
+#define LCD_WF_WF27_SHIFT 24
+#define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
+#define LCD_WF_WF23_MASK 0xFF000000u
+#define LCD_WF_WF23_SHIFT 24
+#define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
+#define LCD_WF_WF19_MASK 0xFF000000u
+#define LCD_WF_WF19_SHIFT 24
+#define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
+#define LCD_WF_WF15_MASK 0xFF000000u
+#define LCD_WF_WF15_SHIFT 24
+#define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
+/* WF8B Bit Fields */
+#define LCD_WF8B_BPALCD0_MASK 0x1u
+#define LCD_WF8B_BPALCD0_SHIFT 0
+#define LCD_WF8B_BPALCD63_MASK 0x1u
+#define LCD_WF8B_BPALCD63_SHIFT 0
+#define LCD_WF8B_BPALCD62_MASK 0x1u
+#define LCD_WF8B_BPALCD62_SHIFT 0
+#define LCD_WF8B_BPALCD61_MASK 0x1u
+#define LCD_WF8B_BPALCD61_SHIFT 0
+#define LCD_WF8B_BPALCD60_MASK 0x1u
+#define LCD_WF8B_BPALCD60_SHIFT 0
+#define LCD_WF8B_BPALCD59_MASK 0x1u
+#define LCD_WF8B_BPALCD59_SHIFT 0
+#define LCD_WF8B_BPALCD58_MASK 0x1u
+#define LCD_WF8B_BPALCD58_SHIFT 0
+#define LCD_WF8B_BPALCD57_MASK 0x1u
+#define LCD_WF8B_BPALCD57_SHIFT 0
+#define LCD_WF8B_BPALCD1_MASK 0x1u
+#define LCD_WF8B_BPALCD1_SHIFT 0
+#define LCD_WF8B_BPALCD56_MASK 0x1u
+#define LCD_WF8B_BPALCD56_SHIFT 0
+#define LCD_WF8B_BPALCD55_MASK 0x1u
+#define LCD_WF8B_BPALCD55_SHIFT 0
+#define LCD_WF8B_BPALCD54_MASK 0x1u
+#define LCD_WF8B_BPALCD54_SHIFT 0
+#define LCD_WF8B_BPALCD53_MASK 0x1u
+#define LCD_WF8B_BPALCD53_SHIFT 0
+#define LCD_WF8B_BPALCD52_MASK 0x1u
+#define LCD_WF8B_BPALCD52_SHIFT 0
+#define LCD_WF8B_BPALCD51_MASK 0x1u
+#define LCD_WF8B_BPALCD51_SHIFT 0
+#define LCD_WF8B_BPALCD50_MASK 0x1u
+#define LCD_WF8B_BPALCD50_SHIFT 0
+#define LCD_WF8B_BPALCD2_MASK 0x1u
+#define LCD_WF8B_BPALCD2_SHIFT 0
+#define LCD_WF8B_BPALCD49_MASK 0x1u
+#define LCD_WF8B_BPALCD49_SHIFT 0
+#define LCD_WF8B_BPALCD48_MASK 0x1u
+#define LCD_WF8B_BPALCD48_SHIFT 0
+#define LCD_WF8B_BPALCD47_MASK 0x1u
+#define LCD_WF8B_BPALCD47_SHIFT 0
+#define LCD_WF8B_BPALCD46_MASK 0x1u
+#define LCD_WF8B_BPALCD46_SHIFT 0
+#define LCD_WF8B_BPALCD45_MASK 0x1u
+#define LCD_WF8B_BPALCD45_SHIFT 0
+#define LCD_WF8B_BPALCD44_MASK 0x1u
+#define LCD_WF8B_BPALCD44_SHIFT 0
+#define LCD_WF8B_BPALCD43_MASK 0x1u
+#define LCD_WF8B_BPALCD43_SHIFT 0
+#define LCD_WF8B_BPALCD3_MASK 0x1u
+#define LCD_WF8B_BPALCD3_SHIFT 0
+#define LCD_WF8B_BPALCD42_MASK 0x1u
+#define LCD_WF8B_BPALCD42_SHIFT 0
+#define LCD_WF8B_BPALCD41_MASK 0x1u
+#define LCD_WF8B_BPALCD41_SHIFT 0
+#define LCD_WF8B_BPALCD40_MASK 0x1u
+#define LCD_WF8B_BPALCD40_SHIFT 0
+#define LCD_WF8B_BPALCD39_MASK 0x1u
+#define LCD_WF8B_BPALCD39_SHIFT 0
+#define LCD_WF8B_BPALCD38_MASK 0x1u
+#define LCD_WF8B_BPALCD38_SHIFT 0
+#define LCD_WF8B_BPALCD37_MASK 0x1u
+#define LCD_WF8B_BPALCD37_SHIFT 0
+#define LCD_WF8B_BPALCD36_MASK 0x1u
+#define LCD_WF8B_BPALCD36_SHIFT 0
+#define LCD_WF8B_BPALCD4_MASK 0x1u
+#define LCD_WF8B_BPALCD4_SHIFT 0
+#define LCD_WF8B_BPALCD35_MASK 0x1u
+#define LCD_WF8B_BPALCD35_SHIFT 0
+#define LCD_WF8B_BPALCD34_MASK 0x1u
+#define LCD_WF8B_BPALCD34_SHIFT 0
+#define LCD_WF8B_BPALCD33_MASK 0x1u
+#define LCD_WF8B_BPALCD33_SHIFT 0
+#define LCD_WF8B_BPALCD32_MASK 0x1u
+#define LCD_WF8B_BPALCD32_SHIFT 0
+#define LCD_WF8B_BPALCD31_MASK 0x1u
+#define LCD_WF8B_BPALCD31_SHIFT 0
+#define LCD_WF8B_BPALCD30_MASK 0x1u
+#define LCD_WF8B_BPALCD30_SHIFT 0
+#define LCD_WF8B_BPALCD29_MASK 0x1u
+#define LCD_WF8B_BPALCD29_SHIFT 0
+#define LCD_WF8B_BPALCD5_MASK 0x1u
+#define LCD_WF8B_BPALCD5_SHIFT 0
+#define LCD_WF8B_BPALCD28_MASK 0x1u
+#define LCD_WF8B_BPALCD28_SHIFT 0
+#define LCD_WF8B_BPALCD27_MASK 0x1u
+#define LCD_WF8B_BPALCD27_SHIFT 0
+#define LCD_WF8B_BPALCD26_MASK 0x1u
+#define LCD_WF8B_BPALCD26_SHIFT 0
+#define LCD_WF8B_BPALCD25_MASK 0x1u
+#define LCD_WF8B_BPALCD25_SHIFT 0
+#define LCD_WF8B_BPALCD24_MASK 0x1u
+#define LCD_WF8B_BPALCD24_SHIFT 0
+#define LCD_WF8B_BPALCD23_MASK 0x1u
+#define LCD_WF8B_BPALCD23_SHIFT 0
+#define LCD_WF8B_BPALCD22_MASK 0x1u
+#define LCD_WF8B_BPALCD22_SHIFT 0
+#define LCD_WF8B_BPALCD6_MASK 0x1u
+#define LCD_WF8B_BPALCD6_SHIFT 0
+#define LCD_WF8B_BPALCD21_MASK 0x1u
+#define LCD_WF8B_BPALCD21_SHIFT 0
+#define LCD_WF8B_BPALCD20_MASK 0x1u
+#define LCD_WF8B_BPALCD20_SHIFT 0
+#define LCD_WF8B_BPALCD19_MASK 0x1u
+#define LCD_WF8B_BPALCD19_SHIFT 0
+#define LCD_WF8B_BPALCD18_MASK 0x1u
+#define LCD_WF8B_BPALCD18_SHIFT 0
+#define LCD_WF8B_BPALCD17_MASK 0x1u
+#define LCD_WF8B_BPALCD17_SHIFT 0
+#define LCD_WF8B_BPALCD16_MASK 0x1u
+#define LCD_WF8B_BPALCD16_SHIFT 0
+#define LCD_WF8B_BPALCD15_MASK 0x1u
+#define LCD_WF8B_BPALCD15_SHIFT 0
+#define LCD_WF8B_BPALCD7_MASK 0x1u
+#define LCD_WF8B_BPALCD7_SHIFT 0
+#define LCD_WF8B_BPALCD14_MASK 0x1u
+#define LCD_WF8B_BPALCD14_SHIFT 0
+#define LCD_WF8B_BPALCD13_MASK 0x1u
+#define LCD_WF8B_BPALCD13_SHIFT 0
+#define LCD_WF8B_BPALCD12_MASK 0x1u
+#define LCD_WF8B_BPALCD12_SHIFT 0
+#define LCD_WF8B_BPALCD11_MASK 0x1u
+#define LCD_WF8B_BPALCD11_SHIFT 0
+#define LCD_WF8B_BPALCD10_MASK 0x1u
+#define LCD_WF8B_BPALCD10_SHIFT 0
+#define LCD_WF8B_BPALCD9_MASK 0x1u
+#define LCD_WF8B_BPALCD9_SHIFT 0
+#define LCD_WF8B_BPALCD8_MASK 0x1u
+#define LCD_WF8B_BPALCD8_SHIFT 0
+#define LCD_WF8B_BPBLCD1_MASK 0x2u
+#define LCD_WF8B_BPBLCD1_SHIFT 1
+#define LCD_WF8B_BPBLCD32_MASK 0x2u
+#define LCD_WF8B_BPBLCD32_SHIFT 1
+#define LCD_WF8B_BPBLCD30_MASK 0x2u
+#define LCD_WF8B_BPBLCD30_SHIFT 1
+#define LCD_WF8B_BPBLCD60_MASK 0x2u
+#define LCD_WF8B_BPBLCD60_SHIFT 1
+#define LCD_WF8B_BPBLCD24_MASK 0x2u
+#define LCD_WF8B_BPBLCD24_SHIFT 1
+#define LCD_WF8B_BPBLCD28_MASK 0x2u
+#define LCD_WF8B_BPBLCD28_SHIFT 1
+#define LCD_WF8B_BPBLCD23_MASK 0x2u
+#define LCD_WF8B_BPBLCD23_SHIFT 1
+#define LCD_WF8B_BPBLCD48_MASK 0x2u
+#define LCD_WF8B_BPBLCD48_SHIFT 1
+#define LCD_WF8B_BPBLCD10_MASK 0x2u
+#define LCD_WF8B_BPBLCD10_SHIFT 1
+#define LCD_WF8B_BPBLCD15_MASK 0x2u
+#define LCD_WF8B_BPBLCD15_SHIFT 1
+#define LCD_WF8B_BPBLCD36_MASK 0x2u
+#define LCD_WF8B_BPBLCD36_SHIFT 1
+#define LCD_WF8B_BPBLCD44_MASK 0x2u
+#define LCD_WF8B_BPBLCD44_SHIFT 1
+#define LCD_WF8B_BPBLCD62_MASK 0x2u
+#define LCD_WF8B_BPBLCD62_SHIFT 1
+#define LCD_WF8B_BPBLCD53_MASK 0x2u
+#define LCD_WF8B_BPBLCD53_SHIFT 1
+#define LCD_WF8B_BPBLCD22_MASK 0x2u
+#define LCD_WF8B_BPBLCD22_SHIFT 1
+#define LCD_WF8B_BPBLCD47_MASK 0x2u
+#define LCD_WF8B_BPBLCD47_SHIFT 1
+#define LCD_WF8B_BPBLCD33_MASK 0x2u
+#define LCD_WF8B_BPBLCD33_SHIFT 1
+#define LCD_WF8B_BPBLCD2_MASK 0x2u
+#define LCD_WF8B_BPBLCD2_SHIFT 1
+#define LCD_WF8B_BPBLCD49_MASK 0x2u
+#define LCD_WF8B_BPBLCD49_SHIFT 1
+#define LCD_WF8B_BPBLCD0_MASK 0x2u
+#define LCD_WF8B_BPBLCD0_SHIFT 1
+#define LCD_WF8B_BPBLCD55_MASK 0x2u
+#define LCD_WF8B_BPBLCD55_SHIFT 1
+#define LCD_WF8B_BPBLCD56_MASK 0x2u
+#define LCD_WF8B_BPBLCD56_SHIFT 1
+#define LCD_WF8B_BPBLCD21_MASK 0x2u
+#define LCD_WF8B_BPBLCD21_SHIFT 1
+#define LCD_WF8B_BPBLCD6_MASK 0x2u
+#define LCD_WF8B_BPBLCD6_SHIFT 1
+#define LCD_WF8B_BPBLCD29_MASK 0x2u
+#define LCD_WF8B_BPBLCD29_SHIFT 1
+#define LCD_WF8B_BPBLCD25_MASK 0x2u
+#define LCD_WF8B_BPBLCD25_SHIFT 1
+#define LCD_WF8B_BPBLCD8_MASK 0x2u
+#define LCD_WF8B_BPBLCD8_SHIFT 1
+#define LCD_WF8B_BPBLCD54_MASK 0x2u
+#define LCD_WF8B_BPBLCD54_SHIFT 1
+#define LCD_WF8B_BPBLCD38_MASK 0x2u
+#define LCD_WF8B_BPBLCD38_SHIFT 1
+#define LCD_WF8B_BPBLCD43_MASK 0x2u
+#define LCD_WF8B_BPBLCD43_SHIFT 1
+#define LCD_WF8B_BPBLCD20_MASK 0x2u
+#define LCD_WF8B_BPBLCD20_SHIFT 1
+#define LCD_WF8B_BPBLCD9_MASK 0x2u
+#define LCD_WF8B_BPBLCD9_SHIFT 1
+#define LCD_WF8B_BPBLCD7_MASK 0x2u
+#define LCD_WF8B_BPBLCD7_SHIFT 1
+#define LCD_WF8B_BPBLCD50_MASK 0x2u
+#define LCD_WF8B_BPBLCD50_SHIFT 1
+#define LCD_WF8B_BPBLCD40_MASK 0x2u
+#define LCD_WF8B_BPBLCD40_SHIFT 1
+#define LCD_WF8B_BPBLCD63_MASK 0x2u
+#define LCD_WF8B_BPBLCD63_SHIFT 1
+#define LCD_WF8B_BPBLCD26_MASK 0x2u
+#define LCD_WF8B_BPBLCD26_SHIFT 1
+#define LCD_WF8B_BPBLCD12_MASK 0x2u
+#define LCD_WF8B_BPBLCD12_SHIFT 1
+#define LCD_WF8B_BPBLCD19_MASK 0x2u
+#define LCD_WF8B_BPBLCD19_SHIFT 1
+#define LCD_WF8B_BPBLCD34_MASK 0x2u
+#define LCD_WF8B_BPBLCD34_SHIFT 1
+#define LCD_WF8B_BPBLCD39_MASK 0x2u
+#define LCD_WF8B_BPBLCD39_SHIFT 1
+#define LCD_WF8B_BPBLCD59_MASK 0x2u
+#define LCD_WF8B_BPBLCD59_SHIFT 1
+#define LCD_WF8B_BPBLCD61_MASK 0x2u
+#define LCD_WF8B_BPBLCD61_SHIFT 1
+#define LCD_WF8B_BPBLCD37_MASK 0x2u
+#define LCD_WF8B_BPBLCD37_SHIFT 1
+#define LCD_WF8B_BPBLCD31_MASK 0x2u
+#define LCD_WF8B_BPBLCD31_SHIFT 1
+#define LCD_WF8B_BPBLCD58_MASK 0x2u
+#define LCD_WF8B_BPBLCD58_SHIFT 1
+#define LCD_WF8B_BPBLCD18_MASK 0x2u
+#define LCD_WF8B_BPBLCD18_SHIFT 1
+#define LCD_WF8B_BPBLCD45_MASK 0x2u
+#define LCD_WF8B_BPBLCD45_SHIFT 1
+#define LCD_WF8B_BPBLCD27_MASK 0x2u
+#define LCD_WF8B_BPBLCD27_SHIFT 1
+#define LCD_WF8B_BPBLCD14_MASK 0x2u
+#define LCD_WF8B_BPBLCD14_SHIFT 1
+#define LCD_WF8B_BPBLCD51_MASK 0x2u
+#define LCD_WF8B_BPBLCD51_SHIFT 1
+#define LCD_WF8B_BPBLCD52_MASK 0x2u
+#define LCD_WF8B_BPBLCD52_SHIFT 1
+#define LCD_WF8B_BPBLCD4_MASK 0x2u
+#define LCD_WF8B_BPBLCD4_SHIFT 1
+#define LCD_WF8B_BPBLCD35_MASK 0x2u
+#define LCD_WF8B_BPBLCD35_SHIFT 1
+#define LCD_WF8B_BPBLCD17_MASK 0x2u
+#define LCD_WF8B_BPBLCD17_SHIFT 1
+#define LCD_WF8B_BPBLCD41_MASK 0x2u
+#define LCD_WF8B_BPBLCD41_SHIFT 1
+#define LCD_WF8B_BPBLCD11_MASK 0x2u
+#define LCD_WF8B_BPBLCD11_SHIFT 1
+#define LCD_WF8B_BPBLCD46_MASK 0x2u
+#define LCD_WF8B_BPBLCD46_SHIFT 1
+#define LCD_WF8B_BPBLCD57_MASK 0x2u
+#define LCD_WF8B_BPBLCD57_SHIFT 1
+#define LCD_WF8B_BPBLCD42_MASK 0x2u
+#define LCD_WF8B_BPBLCD42_SHIFT 1
+#define LCD_WF8B_BPBLCD5_MASK 0x2u
+#define LCD_WF8B_BPBLCD5_SHIFT 1
+#define LCD_WF8B_BPBLCD3_MASK 0x2u
+#define LCD_WF8B_BPBLCD3_SHIFT 1
+#define LCD_WF8B_BPBLCD16_MASK 0x2u
+#define LCD_WF8B_BPBLCD16_SHIFT 1
+#define LCD_WF8B_BPBLCD13_MASK 0x2u
+#define LCD_WF8B_BPBLCD13_SHIFT 1
+#define LCD_WF8B_BPCLCD10_MASK 0x4u
+#define LCD_WF8B_BPCLCD10_SHIFT 2
+#define LCD_WF8B_BPCLCD55_MASK 0x4u
+#define LCD_WF8B_BPCLCD55_SHIFT 2
+#define LCD_WF8B_BPCLCD2_MASK 0x4u
+#define LCD_WF8B_BPCLCD2_SHIFT 2
+#define LCD_WF8B_BPCLCD23_MASK 0x4u
+#define LCD_WF8B_BPCLCD23_SHIFT 2
+#define LCD_WF8B_BPCLCD48_MASK 0x4u
+#define LCD_WF8B_BPCLCD48_SHIFT 2
+#define LCD_WF8B_BPCLCD24_MASK 0x4u
+#define LCD_WF8B_BPCLCD24_SHIFT 2
+#define LCD_WF8B_BPCLCD60_MASK 0x4u
+#define LCD_WF8B_BPCLCD60_SHIFT 2
+#define LCD_WF8B_BPCLCD47_MASK 0x4u
+#define LCD_WF8B_BPCLCD47_SHIFT 2
+#define LCD_WF8B_BPCLCD22_MASK 0x4u
+#define LCD_WF8B_BPCLCD22_SHIFT 2
+#define LCD_WF8B_BPCLCD8_MASK 0x4u
+#define LCD_WF8B_BPCLCD8_SHIFT 2
+#define LCD_WF8B_BPCLCD21_MASK 0x4u
+#define LCD_WF8B_BPCLCD21_SHIFT 2
+#define LCD_WF8B_BPCLCD49_MASK 0x4u
+#define LCD_WF8B_BPCLCD49_SHIFT 2
+#define LCD_WF8B_BPCLCD25_MASK 0x4u
+#define LCD_WF8B_BPCLCD25_SHIFT 2
+#define LCD_WF8B_BPCLCD1_MASK 0x4u
+#define LCD_WF8B_BPCLCD1_SHIFT 2
+#define LCD_WF8B_BPCLCD20_MASK 0x4u
+#define LCD_WF8B_BPCLCD20_SHIFT 2
+#define LCD_WF8B_BPCLCD50_MASK 0x4u
+#define LCD_WF8B_BPCLCD50_SHIFT 2
+#define LCD_WF8B_BPCLCD19_MASK 0x4u
+#define LCD_WF8B_BPCLCD19_SHIFT 2
+#define LCD_WF8B_BPCLCD26_MASK 0x4u
+#define LCD_WF8B_BPCLCD26_SHIFT 2
+#define LCD_WF8B_BPCLCD59_MASK 0x4u
+#define LCD_WF8B_BPCLCD59_SHIFT 2
+#define LCD_WF8B_BPCLCD61_MASK 0x4u
+#define LCD_WF8B_BPCLCD61_SHIFT 2
+#define LCD_WF8B_BPCLCD46_MASK 0x4u
+#define LCD_WF8B_BPCLCD46_SHIFT 2
+#define LCD_WF8B_BPCLCD18_MASK 0x4u
+#define LCD_WF8B_BPCLCD18_SHIFT 2
+#define LCD_WF8B_BPCLCD5_MASK 0x4u
+#define LCD_WF8B_BPCLCD5_SHIFT 2
+#define LCD_WF8B_BPCLCD63_MASK 0x4u
+#define LCD_WF8B_BPCLCD63_SHIFT 2
+#define LCD_WF8B_BPCLCD27_MASK 0x4u
+#define LCD_WF8B_BPCLCD27_SHIFT 2
+#define LCD_WF8B_BPCLCD17_MASK 0x4u
+#define LCD_WF8B_BPCLCD17_SHIFT 2
+#define LCD_WF8B_BPCLCD51_MASK 0x4u
+#define LCD_WF8B_BPCLCD51_SHIFT 2
+#define LCD_WF8B_BPCLCD9_MASK 0x4u
+#define LCD_WF8B_BPCLCD9_SHIFT 2
+#define LCD_WF8B_BPCLCD54_MASK 0x4u
+#define LCD_WF8B_BPCLCD54_SHIFT 2
+#define LCD_WF8B_BPCLCD15_MASK 0x4u
+#define LCD_WF8B_BPCLCD15_SHIFT 2
+#define LCD_WF8B_BPCLCD16_MASK 0x4u
+#define LCD_WF8B_BPCLCD16_SHIFT 2
+#define LCD_WF8B_BPCLCD14_MASK 0x4u
+#define LCD_WF8B_BPCLCD14_SHIFT 2
+#define LCD_WF8B_BPCLCD32_MASK 0x4u
+#define LCD_WF8B_BPCLCD32_SHIFT 2
+#define LCD_WF8B_BPCLCD28_MASK 0x4u
+#define LCD_WF8B_BPCLCD28_SHIFT 2
+#define LCD_WF8B_BPCLCD53_MASK 0x4u
+#define LCD_WF8B_BPCLCD53_SHIFT 2
+#define LCD_WF8B_BPCLCD33_MASK 0x4u
+#define LCD_WF8B_BPCLCD33_SHIFT 2
+#define LCD_WF8B_BPCLCD0_MASK 0x4u
+#define LCD_WF8B_BPCLCD0_SHIFT 2
+#define LCD_WF8B_BPCLCD43_MASK 0x4u
+#define LCD_WF8B_BPCLCD43_SHIFT 2
+#define LCD_WF8B_BPCLCD7_MASK 0x4u
+#define LCD_WF8B_BPCLCD7_SHIFT 2
+#define LCD_WF8B_BPCLCD4_MASK 0x4u
+#define LCD_WF8B_BPCLCD4_SHIFT 2
+#define LCD_WF8B_BPCLCD34_MASK 0x4u
+#define LCD_WF8B_BPCLCD34_SHIFT 2
+#define LCD_WF8B_BPCLCD29_MASK 0x4u
+#define LCD_WF8B_BPCLCD29_SHIFT 2
+#define LCD_WF8B_BPCLCD45_MASK 0x4u
+#define LCD_WF8B_BPCLCD45_SHIFT 2
+#define LCD_WF8B_BPCLCD57_MASK 0x4u
+#define LCD_WF8B_BPCLCD57_SHIFT 2
+#define LCD_WF8B_BPCLCD42_MASK 0x4u
+#define LCD_WF8B_BPCLCD42_SHIFT 2
+#define LCD_WF8B_BPCLCD35_MASK 0x4u
+#define LCD_WF8B_BPCLCD35_SHIFT 2
+#define LCD_WF8B_BPCLCD13_MASK 0x4u
+#define LCD_WF8B_BPCLCD13_SHIFT 2
+#define LCD_WF8B_BPCLCD36_MASK 0x4u
+#define LCD_WF8B_BPCLCD36_SHIFT 2
+#define LCD_WF8B_BPCLCD30_MASK 0x4u
+#define LCD_WF8B_BPCLCD30_SHIFT 2
+#define LCD_WF8B_BPCLCD52_MASK 0x4u
+#define LCD_WF8B_BPCLCD52_SHIFT 2
+#define LCD_WF8B_BPCLCD58_MASK 0x4u
+#define LCD_WF8B_BPCLCD58_SHIFT 2
+#define LCD_WF8B_BPCLCD41_MASK 0x4u
+#define LCD_WF8B_BPCLCD41_SHIFT 2
+#define LCD_WF8B_BPCLCD37_MASK 0x4u
+#define LCD_WF8B_BPCLCD37_SHIFT 2
+#define LCD_WF8B_BPCLCD3_MASK 0x4u
+#define LCD_WF8B_BPCLCD3_SHIFT 2
+#define LCD_WF8B_BPCLCD12_MASK 0x4u
+#define LCD_WF8B_BPCLCD12_SHIFT 2
+#define LCD_WF8B_BPCLCD11_MASK 0x4u
+#define LCD_WF8B_BPCLCD11_SHIFT 2
+#define LCD_WF8B_BPCLCD38_MASK 0x4u
+#define LCD_WF8B_BPCLCD38_SHIFT 2
+#define LCD_WF8B_BPCLCD44_MASK 0x4u
+#define LCD_WF8B_BPCLCD44_SHIFT 2
+#define LCD_WF8B_BPCLCD31_MASK 0x4u
+#define LCD_WF8B_BPCLCD31_SHIFT 2
+#define LCD_WF8B_BPCLCD40_MASK 0x4u
+#define LCD_WF8B_BPCLCD40_SHIFT 2
+#define LCD_WF8B_BPCLCD62_MASK 0x4u
+#define LCD_WF8B_BPCLCD62_SHIFT 2
+#define LCD_WF8B_BPCLCD56_MASK 0x4u
+#define LCD_WF8B_BPCLCD56_SHIFT 2
+#define LCD_WF8B_BPCLCD39_MASK 0x4u
+#define LCD_WF8B_BPCLCD39_SHIFT 2
+#define LCD_WF8B_BPCLCD6_MASK 0x4u
+#define LCD_WF8B_BPCLCD6_SHIFT 2
+#define LCD_WF8B_BPDLCD47_MASK 0x8u
+#define LCD_WF8B_BPDLCD47_SHIFT 3
+#define LCD_WF8B_BPDLCD23_MASK 0x8u
+#define LCD_WF8B_BPDLCD23_SHIFT 3
+#define LCD_WF8B_BPDLCD48_MASK 0x8u
+#define LCD_WF8B_BPDLCD48_SHIFT 3
+#define LCD_WF8B_BPDLCD24_MASK 0x8u
+#define LCD_WF8B_BPDLCD24_SHIFT 3
+#define LCD_WF8B_BPDLCD15_MASK 0x8u
+#define LCD_WF8B_BPDLCD15_SHIFT 3
+#define LCD_WF8B_BPDLCD22_MASK 0x8u
+#define LCD_WF8B_BPDLCD22_SHIFT 3
+#define LCD_WF8B_BPDLCD60_MASK 0x8u
+#define LCD_WF8B_BPDLCD60_SHIFT 3
+#define LCD_WF8B_BPDLCD10_MASK 0x8u
+#define LCD_WF8B_BPDLCD10_SHIFT 3
+#define LCD_WF8B_BPDLCD21_MASK 0x8u
+#define LCD_WF8B_BPDLCD21_SHIFT 3
+#define LCD_WF8B_BPDLCD49_MASK 0x8u
+#define LCD_WF8B_BPDLCD49_SHIFT 3
+#define LCD_WF8B_BPDLCD1_MASK 0x8u
+#define LCD_WF8B_BPDLCD1_SHIFT 3
+#define LCD_WF8B_BPDLCD25_MASK 0x8u
+#define LCD_WF8B_BPDLCD25_SHIFT 3
+#define LCD_WF8B_BPDLCD20_MASK 0x8u
+#define LCD_WF8B_BPDLCD20_SHIFT 3
+#define LCD_WF8B_BPDLCD2_MASK 0x8u
+#define LCD_WF8B_BPDLCD2_SHIFT 3
+#define LCD_WF8B_BPDLCD55_MASK 0x8u
+#define LCD_WF8B_BPDLCD55_SHIFT 3
+#define LCD_WF8B_BPDLCD59_MASK 0x8u
+#define LCD_WF8B_BPDLCD59_SHIFT 3
+#define LCD_WF8B_BPDLCD5_MASK 0x8u
+#define LCD_WF8B_BPDLCD5_SHIFT 3
+#define LCD_WF8B_BPDLCD19_MASK 0x8u
+#define LCD_WF8B_BPDLCD19_SHIFT 3
+#define LCD_WF8B_BPDLCD6_MASK 0x8u
+#define LCD_WF8B_BPDLCD6_SHIFT 3
+#define LCD_WF8B_BPDLCD26_MASK 0x8u
+#define LCD_WF8B_BPDLCD26_SHIFT 3
+#define LCD_WF8B_BPDLCD0_MASK 0x8u
+#define LCD_WF8B_BPDLCD0_SHIFT 3
+#define LCD_WF8B_BPDLCD50_MASK 0x8u
+#define LCD_WF8B_BPDLCD50_SHIFT 3
+#define LCD_WF8B_BPDLCD46_MASK 0x8u
+#define LCD_WF8B_BPDLCD46_SHIFT 3
+#define LCD_WF8B_BPDLCD18_MASK 0x8u
+#define LCD_WF8B_BPDLCD18_SHIFT 3
+#define LCD_WF8B_BPDLCD61_MASK 0x8u
+#define LCD_WF8B_BPDLCD61_SHIFT 3
+#define LCD_WF8B_BPDLCD9_MASK 0x8u
+#define LCD_WF8B_BPDLCD9_SHIFT 3
+#define LCD_WF8B_BPDLCD17_MASK 0x8u
+#define LCD_WF8B_BPDLCD17_SHIFT 3
+#define LCD_WF8B_BPDLCD27_MASK 0x8u
+#define LCD_WF8B_BPDLCD27_SHIFT 3
+#define LCD_WF8B_BPDLCD53_MASK 0x8u
+#define LCD_WF8B_BPDLCD53_SHIFT 3
+#define LCD_WF8B_BPDLCD51_MASK 0x8u
+#define LCD_WF8B_BPDLCD51_SHIFT 3
+#define LCD_WF8B_BPDLCD54_MASK 0x8u
+#define LCD_WF8B_BPDLCD54_SHIFT 3
+#define LCD_WF8B_BPDLCD13_MASK 0x8u
+#define LCD_WF8B_BPDLCD13_SHIFT 3
+#define LCD_WF8B_BPDLCD16_MASK 0x8u
+#define LCD_WF8B_BPDLCD16_SHIFT 3
+#define LCD_WF8B_BPDLCD32_MASK 0x8u
+#define LCD_WF8B_BPDLCD32_SHIFT 3
+#define LCD_WF8B_BPDLCD14_MASK 0x8u
+#define LCD_WF8B_BPDLCD14_SHIFT 3
+#define LCD_WF8B_BPDLCD28_MASK 0x8u
+#define LCD_WF8B_BPDLCD28_SHIFT 3
+#define LCD_WF8B_BPDLCD43_MASK 0x8u
+#define LCD_WF8B_BPDLCD43_SHIFT 3
+#define LCD_WF8B_BPDLCD4_MASK 0x8u
+#define LCD_WF8B_BPDLCD4_SHIFT 3
+#define LCD_WF8B_BPDLCD45_MASK 0x8u
+#define LCD_WF8B_BPDLCD45_SHIFT 3
+#define LCD_WF8B_BPDLCD8_MASK 0x8u
+#define LCD_WF8B_BPDLCD8_SHIFT 3
+#define LCD_WF8B_BPDLCD62_MASK 0x8u
+#define LCD_WF8B_BPDLCD62_SHIFT 3
+#define LCD_WF8B_BPDLCD33_MASK 0x8u
+#define LCD_WF8B_BPDLCD33_SHIFT 3
+#define LCD_WF8B_BPDLCD34_MASK 0x8u
+#define LCD_WF8B_BPDLCD34_SHIFT 3
+#define LCD_WF8B_BPDLCD29_MASK 0x8u
+#define LCD_WF8B_BPDLCD29_SHIFT 3
+#define LCD_WF8B_BPDLCD58_MASK 0x8u
+#define LCD_WF8B_BPDLCD58_SHIFT 3
+#define LCD_WF8B_BPDLCD57_MASK 0x8u
+#define LCD_WF8B_BPDLCD57_SHIFT 3
+#define LCD_WF8B_BPDLCD42_MASK 0x8u
+#define LCD_WF8B_BPDLCD42_SHIFT 3
+#define LCD_WF8B_BPDLCD35_MASK 0x8u
+#define LCD_WF8B_BPDLCD35_SHIFT 3
+#define LCD_WF8B_BPDLCD52_MASK 0x8u
+#define LCD_WF8B_BPDLCD52_SHIFT 3
+#define LCD_WF8B_BPDLCD7_MASK 0x8u
+#define LCD_WF8B_BPDLCD7_SHIFT 3
+#define LCD_WF8B_BPDLCD36_MASK 0x8u
+#define LCD_WF8B_BPDLCD36_SHIFT 3
+#define LCD_WF8B_BPDLCD30_MASK 0x8u
+#define LCD_WF8B_BPDLCD30_SHIFT 3
+#define LCD_WF8B_BPDLCD41_MASK 0x8u
+#define LCD_WF8B_BPDLCD41_SHIFT 3
+#define LCD_WF8B_BPDLCD37_MASK 0x8u
+#define LCD_WF8B_BPDLCD37_SHIFT 3
+#define LCD_WF8B_BPDLCD44_MASK 0x8u
+#define LCD_WF8B_BPDLCD44_SHIFT 3
+#define LCD_WF8B_BPDLCD63_MASK 0x8u
+#define LCD_WF8B_BPDLCD63_SHIFT 3
+#define LCD_WF8B_BPDLCD38_MASK 0x8u
+#define LCD_WF8B_BPDLCD38_SHIFT 3
+#define LCD_WF8B_BPDLCD56_MASK 0x8u
+#define LCD_WF8B_BPDLCD56_SHIFT 3
+#define LCD_WF8B_BPDLCD40_MASK 0x8u
+#define LCD_WF8B_BPDLCD40_SHIFT 3
+#define LCD_WF8B_BPDLCD31_MASK 0x8u
+#define LCD_WF8B_BPDLCD31_SHIFT 3
+#define LCD_WF8B_BPDLCD12_MASK 0x8u
+#define LCD_WF8B_BPDLCD12_SHIFT 3
+#define LCD_WF8B_BPDLCD39_MASK 0x8u
+#define LCD_WF8B_BPDLCD39_SHIFT 3
+#define LCD_WF8B_BPDLCD3_MASK 0x8u
+#define LCD_WF8B_BPDLCD3_SHIFT 3
+#define LCD_WF8B_BPDLCD11_MASK 0x8u
+#define LCD_WF8B_BPDLCD11_SHIFT 3
+#define LCD_WF8B_BPELCD12_MASK 0x10u
+#define LCD_WF8B_BPELCD12_SHIFT 4
+#define LCD_WF8B_BPELCD39_MASK 0x10u
+#define LCD_WF8B_BPELCD39_SHIFT 4
+#define LCD_WF8B_BPELCD3_MASK 0x10u
+#define LCD_WF8B_BPELCD3_SHIFT 4
+#define LCD_WF8B_BPELCD38_MASK 0x10u
+#define LCD_WF8B_BPELCD38_SHIFT 4
+#define LCD_WF8B_BPELCD40_MASK 0x10u
+#define LCD_WF8B_BPELCD40_SHIFT 4
+#define LCD_WF8B_BPELCD37_MASK 0x10u
+#define LCD_WF8B_BPELCD37_SHIFT 4
+#define LCD_WF8B_BPELCD41_MASK 0x10u
+#define LCD_WF8B_BPELCD41_SHIFT 4
+#define LCD_WF8B_BPELCD36_MASK 0x10u
+#define LCD_WF8B_BPELCD36_SHIFT 4
+#define LCD_WF8B_BPELCD8_MASK 0x10u
+#define LCD_WF8B_BPELCD8_SHIFT 4
+#define LCD_WF8B_BPELCD35_MASK 0x10u
+#define LCD_WF8B_BPELCD35_SHIFT 4
+#define LCD_WF8B_BPELCD42_MASK 0x10u
+#define LCD_WF8B_BPELCD42_SHIFT 4
+#define LCD_WF8B_BPELCD34_MASK 0x10u
+#define LCD_WF8B_BPELCD34_SHIFT 4
+#define LCD_WF8B_BPELCD33_MASK 0x10u
+#define LCD_WF8B_BPELCD33_SHIFT 4
+#define LCD_WF8B_BPELCD11_MASK 0x10u
+#define LCD_WF8B_BPELCD11_SHIFT 4
+#define LCD_WF8B_BPELCD43_MASK 0x10u
+#define LCD_WF8B_BPELCD43_SHIFT 4
+#define LCD_WF8B_BPELCD32_MASK 0x10u
+#define LCD_WF8B_BPELCD32_SHIFT 4
+#define LCD_WF8B_BPELCD31_MASK 0x10u
+#define LCD_WF8B_BPELCD31_SHIFT 4
+#define LCD_WF8B_BPELCD44_MASK 0x10u
+#define LCD_WF8B_BPELCD44_SHIFT 4
+#define LCD_WF8B_BPELCD30_MASK 0x10u
+#define LCD_WF8B_BPELCD30_SHIFT 4
+#define LCD_WF8B_BPELCD29_MASK 0x10u
+#define LCD_WF8B_BPELCD29_SHIFT 4
+#define LCD_WF8B_BPELCD7_MASK 0x10u
+#define LCD_WF8B_BPELCD7_SHIFT 4
+#define LCD_WF8B_BPELCD45_MASK 0x10u
+#define LCD_WF8B_BPELCD45_SHIFT 4
+#define LCD_WF8B_BPELCD28_MASK 0x10u
+#define LCD_WF8B_BPELCD28_SHIFT 4
+#define LCD_WF8B_BPELCD2_MASK 0x10u
+#define LCD_WF8B_BPELCD2_SHIFT 4
+#define LCD_WF8B_BPELCD27_MASK 0x10u
+#define LCD_WF8B_BPELCD27_SHIFT 4
+#define LCD_WF8B_BPELCD46_MASK 0x10u
+#define LCD_WF8B_BPELCD46_SHIFT 4
+#define LCD_WF8B_BPELCD26_MASK 0x10u
+#define LCD_WF8B_BPELCD26_SHIFT 4
+#define LCD_WF8B_BPELCD10_MASK 0x10u
+#define LCD_WF8B_BPELCD10_SHIFT 4
+#define LCD_WF8B_BPELCD13_MASK 0x10u
+#define LCD_WF8B_BPELCD13_SHIFT 4
+#define LCD_WF8B_BPELCD25_MASK 0x10u
+#define LCD_WF8B_BPELCD25_SHIFT 4
+#define LCD_WF8B_BPELCD5_MASK 0x10u
+#define LCD_WF8B_BPELCD5_SHIFT 4
+#define LCD_WF8B_BPELCD24_MASK 0x10u
+#define LCD_WF8B_BPELCD24_SHIFT 4
+#define LCD_WF8B_BPELCD47_MASK 0x10u
+#define LCD_WF8B_BPELCD47_SHIFT 4
+#define LCD_WF8B_BPELCD23_MASK 0x10u
+#define LCD_WF8B_BPELCD23_SHIFT 4
+#define LCD_WF8B_BPELCD22_MASK 0x10u
+#define LCD_WF8B_BPELCD22_SHIFT 4
+#define LCD_WF8B_BPELCD48_MASK 0x10u
+#define LCD_WF8B_BPELCD48_SHIFT 4
+#define LCD_WF8B_BPELCD21_MASK 0x10u
+#define LCD_WF8B_BPELCD21_SHIFT 4
+#define LCD_WF8B_BPELCD49_MASK 0x10u
+#define LCD_WF8B_BPELCD49_SHIFT 4
+#define LCD_WF8B_BPELCD20_MASK 0x10u
+#define LCD_WF8B_BPELCD20_SHIFT 4
+#define LCD_WF8B_BPELCD19_MASK 0x10u
+#define LCD_WF8B_BPELCD19_SHIFT 4
+#define LCD_WF8B_BPELCD9_MASK 0x10u
+#define LCD_WF8B_BPELCD9_SHIFT 4
+#define LCD_WF8B_BPELCD50_MASK 0x10u
+#define LCD_WF8B_BPELCD50_SHIFT 4
+#define LCD_WF8B_BPELCD18_MASK 0x10u
+#define LCD_WF8B_BPELCD18_SHIFT 4
+#define LCD_WF8B_BPELCD6_MASK 0x10u
+#define LCD_WF8B_BPELCD6_SHIFT 4
+#define LCD_WF8B_BPELCD17_MASK 0x10u
+#define LCD_WF8B_BPELCD17_SHIFT 4
+#define LCD_WF8B_BPELCD51_MASK 0x10u
+#define LCD_WF8B_BPELCD51_SHIFT 4
+#define LCD_WF8B_BPELCD16_MASK 0x10u
+#define LCD_WF8B_BPELCD16_SHIFT 4
+#define LCD_WF8B_BPELCD56_MASK 0x10u
+#define LCD_WF8B_BPELCD56_SHIFT 4
+#define LCD_WF8B_BPELCD57_MASK 0x10u
+#define LCD_WF8B_BPELCD57_SHIFT 4
+#define LCD_WF8B_BPELCD52_MASK 0x10u
+#define LCD_WF8B_BPELCD52_SHIFT 4
+#define LCD_WF8B_BPELCD1_MASK 0x10u
+#define LCD_WF8B_BPELCD1_SHIFT 4
+#define LCD_WF8B_BPELCD58_MASK 0x10u
+#define LCD_WF8B_BPELCD58_SHIFT 4
+#define LCD_WF8B_BPELCD59_MASK 0x10u
+#define LCD_WF8B_BPELCD59_SHIFT 4
+#define LCD_WF8B_BPELCD53_MASK 0x10u
+#define LCD_WF8B_BPELCD53_SHIFT 4
+#define LCD_WF8B_BPELCD14_MASK 0x10u
+#define LCD_WF8B_BPELCD14_SHIFT 4
+#define LCD_WF8B_BPELCD0_MASK 0x10u
+#define LCD_WF8B_BPELCD0_SHIFT 4
+#define LCD_WF8B_BPELCD60_MASK 0x10u
+#define LCD_WF8B_BPELCD60_SHIFT 4
+#define LCD_WF8B_BPELCD15_MASK 0x10u
+#define LCD_WF8B_BPELCD15_SHIFT 4
+#define LCD_WF8B_BPELCD61_MASK 0x10u
+#define LCD_WF8B_BPELCD61_SHIFT 4
+#define LCD_WF8B_BPELCD54_MASK 0x10u
+#define LCD_WF8B_BPELCD54_SHIFT 4
+#define LCD_WF8B_BPELCD62_MASK 0x10u
+#define LCD_WF8B_BPELCD62_SHIFT 4
+#define LCD_WF8B_BPELCD63_MASK 0x10u
+#define LCD_WF8B_BPELCD63_SHIFT 4
+#define LCD_WF8B_BPELCD55_MASK 0x10u
+#define LCD_WF8B_BPELCD55_SHIFT 4
+#define LCD_WF8B_BPELCD4_MASK 0x10u
+#define LCD_WF8B_BPELCD4_SHIFT 4
+#define LCD_WF8B_BPFLCD13_MASK 0x20u
+#define LCD_WF8B_BPFLCD13_SHIFT 5
+#define LCD_WF8B_BPFLCD39_MASK 0x20u
+#define LCD_WF8B_BPFLCD39_SHIFT 5
+#define LCD_WF8B_BPFLCD55_MASK 0x20u
+#define LCD_WF8B_BPFLCD55_SHIFT 5
+#define LCD_WF8B_BPFLCD47_MASK 0x20u
+#define LCD_WF8B_BPFLCD47_SHIFT 5
+#define LCD_WF8B_BPFLCD63_MASK 0x20u
+#define LCD_WF8B_BPFLCD63_SHIFT 5
+#define LCD_WF8B_BPFLCD43_MASK 0x20u
+#define LCD_WF8B_BPFLCD43_SHIFT 5
+#define LCD_WF8B_BPFLCD5_MASK 0x20u
+#define LCD_WF8B_BPFLCD5_SHIFT 5
+#define LCD_WF8B_BPFLCD62_MASK 0x20u
+#define LCD_WF8B_BPFLCD62_SHIFT 5
+#define LCD_WF8B_BPFLCD14_MASK 0x20u
+#define LCD_WF8B_BPFLCD14_SHIFT 5
+#define LCD_WF8B_BPFLCD24_MASK 0x20u
+#define LCD_WF8B_BPFLCD24_SHIFT 5
+#define LCD_WF8B_BPFLCD54_MASK 0x20u
+#define LCD_WF8B_BPFLCD54_SHIFT 5
+#define LCD_WF8B_BPFLCD15_MASK 0x20u
+#define LCD_WF8B_BPFLCD15_SHIFT 5
+#define LCD_WF8B_BPFLCD32_MASK 0x20u
+#define LCD_WF8B_BPFLCD32_SHIFT 5
+#define LCD_WF8B_BPFLCD61_MASK 0x20u
+#define LCD_WF8B_BPFLCD61_SHIFT 5
+#define LCD_WF8B_BPFLCD25_MASK 0x20u
+#define LCD_WF8B_BPFLCD25_SHIFT 5
+#define LCD_WF8B_BPFLCD60_MASK 0x20u
+#define LCD_WF8B_BPFLCD60_SHIFT 5
+#define LCD_WF8B_BPFLCD41_MASK 0x20u
+#define LCD_WF8B_BPFLCD41_SHIFT 5
+#define LCD_WF8B_BPFLCD33_MASK 0x20u
+#define LCD_WF8B_BPFLCD33_SHIFT 5
+#define LCD_WF8B_BPFLCD53_MASK 0x20u
+#define LCD_WF8B_BPFLCD53_SHIFT 5
+#define LCD_WF8B_BPFLCD59_MASK 0x20u
+#define LCD_WF8B_BPFLCD59_SHIFT 5
+#define LCD_WF8B_BPFLCD0_MASK 0x20u
+#define LCD_WF8B_BPFLCD0_SHIFT 5
+#define LCD_WF8B_BPFLCD46_MASK 0x20u
+#define LCD_WF8B_BPFLCD46_SHIFT 5
+#define LCD_WF8B_BPFLCD58_MASK 0x20u
+#define LCD_WF8B_BPFLCD58_SHIFT 5
+#define LCD_WF8B_BPFLCD26_MASK 0x20u
+#define LCD_WF8B_BPFLCD26_SHIFT 5
+#define LCD_WF8B_BPFLCD36_MASK 0x20u
+#define LCD_WF8B_BPFLCD36_SHIFT 5
+#define LCD_WF8B_BPFLCD10_MASK 0x20u
+#define LCD_WF8B_BPFLCD10_SHIFT 5
+#define LCD_WF8B_BPFLCD52_MASK 0x20u
+#define LCD_WF8B_BPFLCD52_SHIFT 5
+#define LCD_WF8B_BPFLCD57_MASK 0x20u
+#define LCD_WF8B_BPFLCD57_SHIFT 5
+#define LCD_WF8B_BPFLCD27_MASK 0x20u
+#define LCD_WF8B_BPFLCD27_SHIFT 5
+#define LCD_WF8B_BPFLCD11_MASK 0x20u
+#define LCD_WF8B_BPFLCD11_SHIFT 5
+#define LCD_WF8B_BPFLCD56_MASK 0x20u
+#define LCD_WF8B_BPFLCD56_SHIFT 5
+#define LCD_WF8B_BPFLCD1_MASK 0x20u
+#define LCD_WF8B_BPFLCD1_SHIFT 5
+#define LCD_WF8B_BPFLCD8_MASK 0x20u
+#define LCD_WF8B_BPFLCD8_SHIFT 5
+#define LCD_WF8B_BPFLCD40_MASK 0x20u
+#define LCD_WF8B_BPFLCD40_SHIFT 5
+#define LCD_WF8B_BPFLCD51_MASK 0x20u
+#define LCD_WF8B_BPFLCD51_SHIFT 5
+#define LCD_WF8B_BPFLCD16_MASK 0x20u
+#define LCD_WF8B_BPFLCD16_SHIFT 5
+#define LCD_WF8B_BPFLCD45_MASK 0x20u
+#define LCD_WF8B_BPFLCD45_SHIFT 5
+#define LCD_WF8B_BPFLCD6_MASK 0x20u
+#define LCD_WF8B_BPFLCD6_SHIFT 5
+#define LCD_WF8B_BPFLCD17_MASK 0x20u
+#define LCD_WF8B_BPFLCD17_SHIFT 5
+#define LCD_WF8B_BPFLCD28_MASK 0x20u
+#define LCD_WF8B_BPFLCD28_SHIFT 5
+#define LCD_WF8B_BPFLCD42_MASK 0x20u
+#define LCD_WF8B_BPFLCD42_SHIFT 5
+#define LCD_WF8B_BPFLCD29_MASK 0x20u
+#define LCD_WF8B_BPFLCD29_SHIFT 5
+#define LCD_WF8B_BPFLCD50_MASK 0x20u
+#define LCD_WF8B_BPFLCD50_SHIFT 5
+#define LCD_WF8B_BPFLCD18_MASK 0x20u
+#define LCD_WF8B_BPFLCD18_SHIFT 5
+#define LCD_WF8B_BPFLCD34_MASK 0x20u
+#define LCD_WF8B_BPFLCD34_SHIFT 5
+#define LCD_WF8B_BPFLCD19_MASK 0x20u
+#define LCD_WF8B_BPFLCD19_SHIFT 5
+#define LCD_WF8B_BPFLCD2_MASK 0x20u
+#define LCD_WF8B_BPFLCD2_SHIFT 5
+#define LCD_WF8B_BPFLCD9_MASK 0x20u
+#define LCD_WF8B_BPFLCD9_SHIFT 5
+#define LCD_WF8B_BPFLCD3_MASK 0x20u
+#define LCD_WF8B_BPFLCD3_SHIFT 5
+#define LCD_WF8B_BPFLCD37_MASK 0x20u
+#define LCD_WF8B_BPFLCD37_SHIFT 5
+#define LCD_WF8B_BPFLCD49_MASK 0x20u
+#define LCD_WF8B_BPFLCD49_SHIFT 5
+#define LCD_WF8B_BPFLCD20_MASK 0x20u
+#define LCD_WF8B_BPFLCD20_SHIFT 5
+#define LCD_WF8B_BPFLCD44_MASK 0x20u
+#define LCD_WF8B_BPFLCD44_SHIFT 5
+#define LCD_WF8B_BPFLCD30_MASK 0x20u
+#define LCD_WF8B_BPFLCD30_SHIFT 5
+#define LCD_WF8B_BPFLCD21_MASK 0x20u
+#define LCD_WF8B_BPFLCD21_SHIFT 5
+#define LCD_WF8B_BPFLCD35_MASK 0x20u
+#define LCD_WF8B_BPFLCD35_SHIFT 5
+#define LCD_WF8B_BPFLCD4_MASK 0x20u
+#define LCD_WF8B_BPFLCD4_SHIFT 5
+#define LCD_WF8B_BPFLCD31_MASK 0x20u
+#define LCD_WF8B_BPFLCD31_SHIFT 5
+#define LCD_WF8B_BPFLCD48_MASK 0x20u
+#define LCD_WF8B_BPFLCD48_SHIFT 5
+#define LCD_WF8B_BPFLCD7_MASK 0x20u
+#define LCD_WF8B_BPFLCD7_SHIFT 5
+#define LCD_WF8B_BPFLCD22_MASK 0x20u
+#define LCD_WF8B_BPFLCD22_SHIFT 5
+#define LCD_WF8B_BPFLCD38_MASK 0x20u
+#define LCD_WF8B_BPFLCD38_SHIFT 5
+#define LCD_WF8B_BPFLCD12_MASK 0x20u
+#define LCD_WF8B_BPFLCD12_SHIFT 5
+#define LCD_WF8B_BPFLCD23_MASK 0x20u
+#define LCD_WF8B_BPFLCD23_SHIFT 5
+#define LCD_WF8B_BPGLCD14_MASK 0x40u
+#define LCD_WF8B_BPGLCD14_SHIFT 6
+#define LCD_WF8B_BPGLCD55_MASK 0x40u
+#define LCD_WF8B_BPGLCD55_SHIFT 6
+#define LCD_WF8B_BPGLCD63_MASK 0x40u
+#define LCD_WF8B_BPGLCD63_SHIFT 6
+#define LCD_WF8B_BPGLCD15_MASK 0x40u
+#define LCD_WF8B_BPGLCD15_SHIFT 6
+#define LCD_WF8B_BPGLCD62_MASK 0x40u
+#define LCD_WF8B_BPGLCD62_SHIFT 6
+#define LCD_WF8B_BPGLCD54_MASK 0x40u
+#define LCD_WF8B_BPGLCD54_SHIFT 6
+#define LCD_WF8B_BPGLCD61_MASK 0x40u
+#define LCD_WF8B_BPGLCD61_SHIFT 6
+#define LCD_WF8B_BPGLCD60_MASK 0x40u
+#define LCD_WF8B_BPGLCD60_SHIFT 6
+#define LCD_WF8B_BPGLCD59_MASK 0x40u
+#define LCD_WF8B_BPGLCD59_SHIFT 6
+#define LCD_WF8B_BPGLCD53_MASK 0x40u
+#define LCD_WF8B_BPGLCD53_SHIFT 6
+#define LCD_WF8B_BPGLCD58_MASK 0x40u
+#define LCD_WF8B_BPGLCD58_SHIFT 6
+#define LCD_WF8B_BPGLCD0_MASK 0x40u
+#define LCD_WF8B_BPGLCD0_SHIFT 6
+#define LCD_WF8B_BPGLCD57_MASK 0x40u
+#define LCD_WF8B_BPGLCD57_SHIFT 6
+#define LCD_WF8B_BPGLCD52_MASK 0x40u
+#define LCD_WF8B_BPGLCD52_SHIFT 6
+#define LCD_WF8B_BPGLCD7_MASK 0x40u
+#define LCD_WF8B_BPGLCD7_SHIFT 6
+#define LCD_WF8B_BPGLCD56_MASK 0x40u
+#define LCD_WF8B_BPGLCD56_SHIFT 6
+#define LCD_WF8B_BPGLCD6_MASK 0x40u
+#define LCD_WF8B_BPGLCD6_SHIFT 6
+#define LCD_WF8B_BPGLCD51_MASK 0x40u
+#define LCD_WF8B_BPGLCD51_SHIFT 6
+#define LCD_WF8B_BPGLCD16_MASK 0x40u
+#define LCD_WF8B_BPGLCD16_SHIFT 6
+#define LCD_WF8B_BPGLCD1_MASK 0x40u
+#define LCD_WF8B_BPGLCD1_SHIFT 6
+#define LCD_WF8B_BPGLCD17_MASK 0x40u
+#define LCD_WF8B_BPGLCD17_SHIFT 6
+#define LCD_WF8B_BPGLCD50_MASK 0x40u
+#define LCD_WF8B_BPGLCD50_SHIFT 6
+#define LCD_WF8B_BPGLCD18_MASK 0x40u
+#define LCD_WF8B_BPGLCD18_SHIFT 6
+#define LCD_WF8B_BPGLCD19_MASK 0x40u
+#define LCD_WF8B_BPGLCD19_SHIFT 6
+#define LCD_WF8B_BPGLCD8_MASK 0x40u
+#define LCD_WF8B_BPGLCD8_SHIFT 6
+#define LCD_WF8B_BPGLCD49_MASK 0x40u
+#define LCD_WF8B_BPGLCD49_SHIFT 6
+#define LCD_WF8B_BPGLCD20_MASK 0x40u
+#define LCD_WF8B_BPGLCD20_SHIFT 6
+#define LCD_WF8B_BPGLCD9_MASK 0x40u
+#define LCD_WF8B_BPGLCD9_SHIFT 6
+#define LCD_WF8B_BPGLCD21_MASK 0x40u
+#define LCD_WF8B_BPGLCD21_SHIFT 6
+#define LCD_WF8B_BPGLCD13_MASK 0x40u
+#define LCD_WF8B_BPGLCD13_SHIFT 6
+#define LCD_WF8B_BPGLCD48_MASK 0x40u
+#define LCD_WF8B_BPGLCD48_SHIFT 6
+#define LCD_WF8B_BPGLCD22_MASK 0x40u
+#define LCD_WF8B_BPGLCD22_SHIFT 6
+#define LCD_WF8B_BPGLCD5_MASK 0x40u
+#define LCD_WF8B_BPGLCD5_SHIFT 6
+#define LCD_WF8B_BPGLCD47_MASK 0x40u
+#define LCD_WF8B_BPGLCD47_SHIFT 6
+#define LCD_WF8B_BPGLCD23_MASK 0x40u
+#define LCD_WF8B_BPGLCD23_SHIFT 6
+#define LCD_WF8B_BPGLCD24_MASK 0x40u
+#define LCD_WF8B_BPGLCD24_SHIFT 6
+#define LCD_WF8B_BPGLCD25_MASK 0x40u
+#define LCD_WF8B_BPGLCD25_SHIFT 6
+#define LCD_WF8B_BPGLCD46_MASK 0x40u
+#define LCD_WF8B_BPGLCD46_SHIFT 6
+#define LCD_WF8B_BPGLCD26_MASK 0x40u
+#define LCD_WF8B_BPGLCD26_SHIFT 6
+#define LCD_WF8B_BPGLCD27_MASK 0x40u
+#define LCD_WF8B_BPGLCD27_SHIFT 6
+#define LCD_WF8B_BPGLCD10_MASK 0x40u
+#define LCD_WF8B_BPGLCD10_SHIFT 6
+#define LCD_WF8B_BPGLCD45_MASK 0x40u
+#define LCD_WF8B_BPGLCD45_SHIFT 6
+#define LCD_WF8B_BPGLCD28_MASK 0x40u
+#define LCD_WF8B_BPGLCD28_SHIFT 6
+#define LCD_WF8B_BPGLCD29_MASK 0x40u
+#define LCD_WF8B_BPGLCD29_SHIFT 6
+#define LCD_WF8B_BPGLCD4_MASK 0x40u
+#define LCD_WF8B_BPGLCD4_SHIFT 6
+#define LCD_WF8B_BPGLCD44_MASK 0x40u
+#define LCD_WF8B_BPGLCD44_SHIFT 6
+#define LCD_WF8B_BPGLCD30_MASK 0x40u
+#define LCD_WF8B_BPGLCD30_SHIFT 6
+#define LCD_WF8B_BPGLCD2_MASK 0x40u
+#define LCD_WF8B_BPGLCD2_SHIFT 6
+#define LCD_WF8B_BPGLCD31_MASK 0x40u
+#define LCD_WF8B_BPGLCD31_SHIFT 6
+#define LCD_WF8B_BPGLCD43_MASK 0x40u
+#define LCD_WF8B_BPGLCD43_SHIFT 6
+#define LCD_WF8B_BPGLCD32_MASK 0x40u
+#define LCD_WF8B_BPGLCD32_SHIFT 6
+#define LCD_WF8B_BPGLCD33_MASK 0x40u
+#define LCD_WF8B_BPGLCD33_SHIFT 6
+#define LCD_WF8B_BPGLCD42_MASK 0x40u
+#define LCD_WF8B_BPGLCD42_SHIFT 6
+#define LCD_WF8B_BPGLCD34_MASK 0x40u
+#define LCD_WF8B_BPGLCD34_SHIFT 6
+#define LCD_WF8B_BPGLCD11_MASK 0x40u
+#define LCD_WF8B_BPGLCD11_SHIFT 6
+#define LCD_WF8B_BPGLCD35_MASK 0x40u
+#define LCD_WF8B_BPGLCD35_SHIFT 6
+#define LCD_WF8B_BPGLCD12_MASK 0x40u
+#define LCD_WF8B_BPGLCD12_SHIFT 6
+#define LCD_WF8B_BPGLCD41_MASK 0x40u
+#define LCD_WF8B_BPGLCD41_SHIFT 6
+#define LCD_WF8B_BPGLCD36_MASK 0x40u
+#define LCD_WF8B_BPGLCD36_SHIFT 6
+#define LCD_WF8B_BPGLCD3_MASK 0x40u
+#define LCD_WF8B_BPGLCD3_SHIFT 6
+#define LCD_WF8B_BPGLCD37_MASK 0x40u
+#define LCD_WF8B_BPGLCD37_SHIFT 6
+#define LCD_WF8B_BPGLCD40_MASK 0x40u
+#define LCD_WF8B_BPGLCD40_SHIFT 6
+#define LCD_WF8B_BPGLCD38_MASK 0x40u
+#define LCD_WF8B_BPGLCD38_SHIFT 6
+#define LCD_WF8B_BPGLCD39_MASK 0x40u
+#define LCD_WF8B_BPGLCD39_SHIFT 6
+#define LCD_WF8B_BPHLCD63_MASK 0x80u
+#define LCD_WF8B_BPHLCD63_SHIFT 7
+#define LCD_WF8B_BPHLCD62_MASK 0x80u
+#define LCD_WF8B_BPHLCD62_SHIFT 7
+#define LCD_WF8B_BPHLCD61_MASK 0x80u
+#define LCD_WF8B_BPHLCD61_SHIFT 7
+#define LCD_WF8B_BPHLCD60_MASK 0x80u
+#define LCD_WF8B_BPHLCD60_SHIFT 7
+#define LCD_WF8B_BPHLCD59_MASK 0x80u
+#define LCD_WF8B_BPHLCD59_SHIFT 7
+#define LCD_WF8B_BPHLCD58_MASK 0x80u
+#define LCD_WF8B_BPHLCD58_SHIFT 7
+#define LCD_WF8B_BPHLCD57_MASK 0x80u
+#define LCD_WF8B_BPHLCD57_SHIFT 7
+#define LCD_WF8B_BPHLCD0_MASK 0x80u
+#define LCD_WF8B_BPHLCD0_SHIFT 7
+#define LCD_WF8B_BPHLCD56_MASK 0x80u
+#define LCD_WF8B_BPHLCD56_SHIFT 7
+#define LCD_WF8B_BPHLCD55_MASK 0x80u
+#define LCD_WF8B_BPHLCD55_SHIFT 7
+#define LCD_WF8B_BPHLCD54_MASK 0x80u
+#define LCD_WF8B_BPHLCD54_SHIFT 7
+#define LCD_WF8B_BPHLCD53_MASK 0x80u
+#define LCD_WF8B_BPHLCD53_SHIFT 7
+#define LCD_WF8B_BPHLCD52_MASK 0x80u
+#define LCD_WF8B_BPHLCD52_SHIFT 7
+#define LCD_WF8B_BPHLCD51_MASK 0x80u
+#define LCD_WF8B_BPHLCD51_SHIFT 7
+#define LCD_WF8B_BPHLCD50_MASK 0x80u
+#define LCD_WF8B_BPHLCD50_SHIFT 7
+#define LCD_WF8B_BPHLCD1_MASK 0x80u
+#define LCD_WF8B_BPHLCD1_SHIFT 7
+#define LCD_WF8B_BPHLCD49_MASK 0x80u
+#define LCD_WF8B_BPHLCD49_SHIFT 7
+#define LCD_WF8B_BPHLCD48_MASK 0x80u
+#define LCD_WF8B_BPHLCD48_SHIFT 7
+#define LCD_WF8B_BPHLCD47_MASK 0x80u
+#define LCD_WF8B_BPHLCD47_SHIFT 7
+#define LCD_WF8B_BPHLCD46_MASK 0x80u
+#define LCD_WF8B_BPHLCD46_SHIFT 7
+#define LCD_WF8B_BPHLCD45_MASK 0x80u
+#define LCD_WF8B_BPHLCD45_SHIFT 7
+#define LCD_WF8B_BPHLCD44_MASK 0x80u
+#define LCD_WF8B_BPHLCD44_SHIFT 7
+#define LCD_WF8B_BPHLCD43_MASK 0x80u
+#define LCD_WF8B_BPHLCD43_SHIFT 7
+#define LCD_WF8B_BPHLCD2_MASK 0x80u
+#define LCD_WF8B_BPHLCD2_SHIFT 7
+#define LCD_WF8B_BPHLCD42_MASK 0x80u
+#define LCD_WF8B_BPHLCD42_SHIFT 7
+#define LCD_WF8B_BPHLCD41_MASK 0x80u
+#define LCD_WF8B_BPHLCD41_SHIFT 7
+#define LCD_WF8B_BPHLCD40_MASK 0x80u
+#define LCD_WF8B_BPHLCD40_SHIFT 7
+#define LCD_WF8B_BPHLCD39_MASK 0x80u
+#define LCD_WF8B_BPHLCD39_SHIFT 7
+#define LCD_WF8B_BPHLCD38_MASK 0x80u
+#define LCD_WF8B_BPHLCD38_SHIFT 7
+#define LCD_WF8B_BPHLCD37_MASK 0x80u
+#define LCD_WF8B_BPHLCD37_SHIFT 7
+#define LCD_WF8B_BPHLCD36_MASK 0x80u
+#define LCD_WF8B_BPHLCD36_SHIFT 7
+#define LCD_WF8B_BPHLCD3_MASK 0x80u
+#define LCD_WF8B_BPHLCD3_SHIFT 7
+#define LCD_WF8B_BPHLCD35_MASK 0x80u
+#define LCD_WF8B_BPHLCD35_SHIFT 7
+#define LCD_WF8B_BPHLCD34_MASK 0x80u
+#define LCD_WF8B_BPHLCD34_SHIFT 7
+#define LCD_WF8B_BPHLCD33_MASK 0x80u
+#define LCD_WF8B_BPHLCD33_SHIFT 7
+#define LCD_WF8B_BPHLCD32_MASK 0x80u
+#define LCD_WF8B_BPHLCD32_SHIFT 7
+#define LCD_WF8B_BPHLCD31_MASK 0x80u
+#define LCD_WF8B_BPHLCD31_SHIFT 7
+#define LCD_WF8B_BPHLCD30_MASK 0x80u
+#define LCD_WF8B_BPHLCD30_SHIFT 7
+#define LCD_WF8B_BPHLCD29_MASK 0x80u
+#define LCD_WF8B_BPHLCD29_SHIFT 7
+#define LCD_WF8B_BPHLCD4_MASK 0x80u
+#define LCD_WF8B_BPHLCD4_SHIFT 7
+#define LCD_WF8B_BPHLCD28_MASK 0x80u
+#define LCD_WF8B_BPHLCD28_SHIFT 7
+#define LCD_WF8B_BPHLCD27_MASK 0x80u
+#define LCD_WF8B_BPHLCD27_SHIFT 7
+#define LCD_WF8B_BPHLCD26_MASK 0x80u
+#define LCD_WF8B_BPHLCD26_SHIFT 7
+#define LCD_WF8B_BPHLCD25_MASK 0x80u
+#define LCD_WF8B_BPHLCD25_SHIFT 7
+#define LCD_WF8B_BPHLCD24_MASK 0x80u
+#define LCD_WF8B_BPHLCD24_SHIFT 7
+#define LCD_WF8B_BPHLCD23_MASK 0x80u
+#define LCD_WF8B_BPHLCD23_SHIFT 7
+#define LCD_WF8B_BPHLCD22_MASK 0x80u
+#define LCD_WF8B_BPHLCD22_SHIFT 7
+#define LCD_WF8B_BPHLCD5_MASK 0x80u
+#define LCD_WF8B_BPHLCD5_SHIFT 7
+#define LCD_WF8B_BPHLCD21_MASK 0x80u
+#define LCD_WF8B_BPHLCD21_SHIFT 7
+#define LCD_WF8B_BPHLCD20_MASK 0x80u
+#define LCD_WF8B_BPHLCD20_SHIFT 7
+#define LCD_WF8B_BPHLCD19_MASK 0x80u
+#define LCD_WF8B_BPHLCD19_SHIFT 7
+#define LCD_WF8B_BPHLCD18_MASK 0x80u
+#define LCD_WF8B_BPHLCD18_SHIFT 7
+#define LCD_WF8B_BPHLCD17_MASK 0x80u
+#define LCD_WF8B_BPHLCD17_SHIFT 7
+#define LCD_WF8B_BPHLCD16_MASK 0x80u
+#define LCD_WF8B_BPHLCD16_SHIFT 7
+#define LCD_WF8B_BPHLCD15_MASK 0x80u
+#define LCD_WF8B_BPHLCD15_SHIFT 7
+#define LCD_WF8B_BPHLCD6_MASK 0x80u
+#define LCD_WF8B_BPHLCD6_SHIFT 7
+#define LCD_WF8B_BPHLCD14_MASK 0x80u
+#define LCD_WF8B_BPHLCD14_SHIFT 7
+#define LCD_WF8B_BPHLCD13_MASK 0x80u
+#define LCD_WF8B_BPHLCD13_SHIFT 7
+#define LCD_WF8B_BPHLCD12_MASK 0x80u
+#define LCD_WF8B_BPHLCD12_SHIFT 7
+#define LCD_WF8B_BPHLCD11_MASK 0x80u
+#define LCD_WF8B_BPHLCD11_SHIFT 7
+#define LCD_WF8B_BPHLCD10_MASK 0x80u
+#define LCD_WF8B_BPHLCD10_SHIFT 7
+#define LCD_WF8B_BPHLCD9_MASK 0x80u
+#define LCD_WF8B_BPHLCD9_SHIFT 7
+#define LCD_WF8B_BPHLCD8_MASK 0x80u
+#define LCD_WF8B_BPHLCD8_SHIFT 7
+#define LCD_WF8B_BPHLCD7_MASK 0x80u
+#define LCD_WF8B_BPHLCD7_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group LCD_Register_Masks */
+
+
+/* LCD - Peripheral instance base addresses */
+/** Peripheral LCD base address */
+#define LCD_BASE (0x40053000u)
+/** Peripheral LCD base pointer */
+#define LCD ((LCD_Type *)LCD_BASE)
+#define LCD_BASE_PTR (LCD)
+/** Array initializer of LCD peripheral base addresses */
+#define LCD_BASE_ADDRS { LCD_BASE }
+/** Array initializer of LCD peripheral base pointers */
+#define LCD_BASE_PTRS { LCD }
+/** Interrupt vectors for the LCD peripheral type */
+#define LCD_LCD_IRQS { LCD_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LCD - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Register_Accessor_Macros LCD - Register accessor macros
+ * @{
+ */
+
+
+/* LCD - Register instance definitions */
+/* LCD */
+#define LCD_GCR LCD_GCR_REG(LCD)
+#define LCD_AR LCD_AR_REG(LCD)
+#define LCD_FDCR LCD_FDCR_REG(LCD)
+#define LCD_FDSR LCD_FDSR_REG(LCD)
+#define LCD_PENL LCD_PEN_REG(LCD,0)
+#define LCD_PENH LCD_PEN_REG(LCD,1)
+#define LCD_BPENL LCD_BPEN_REG(LCD,0)
+#define LCD_BPENH LCD_BPEN_REG(LCD,1)
+#define LCD_WF0 LCD_WF8B_REG(LCD,0)
+#define LCD_WF3TO0 LCD_WF_REG(LCD,0)
+#define LCD_WF1 LCD_WF8B_REG(LCD,1)
+#define LCD_WF2 LCD_WF8B_REG(LCD,2)
+#define LCD_WF3 LCD_WF8B_REG(LCD,3)
+#define LCD_WF4 LCD_WF8B_REG(LCD,4)
+#define LCD_WF7TO4 LCD_WF_REG(LCD,1)
+#define LCD_WF5 LCD_WF8B_REG(LCD,5)
+#define LCD_WF6 LCD_WF8B_REG(LCD,6)
+#define LCD_WF7 LCD_WF8B_REG(LCD,7)
+#define LCD_WF11TO8 LCD_WF_REG(LCD,2)
+#define LCD_WF8 LCD_WF8B_REG(LCD,8)
+#define LCD_WF9 LCD_WF8B_REG(LCD,9)
+#define LCD_WF10 LCD_WF8B_REG(LCD,10)
+#define LCD_WF11 LCD_WF8B_REG(LCD,11)
+#define LCD_WF12 LCD_WF8B_REG(LCD,12)
+#define LCD_WF15TO12 LCD_WF_REG(LCD,3)
+#define LCD_WF13 LCD_WF8B_REG(LCD,13)
+#define LCD_WF14 LCD_WF8B_REG(LCD,14)
+#define LCD_WF15 LCD_WF8B_REG(LCD,15)
+#define LCD_WF16 LCD_WF8B_REG(LCD,16)
+#define LCD_WF19TO16 LCD_WF_REG(LCD,4)
+#define LCD_WF17 LCD_WF8B_REG(LCD,17)
+#define LCD_WF18 LCD_WF8B_REG(LCD,18)
+#define LCD_WF19 LCD_WF8B_REG(LCD,19)
+#define LCD_WF20 LCD_WF8B_REG(LCD,20)
+#define LCD_WF23TO20 LCD_WF_REG(LCD,5)
+#define LCD_WF21 LCD_WF8B_REG(LCD,21)
+#define LCD_WF22 LCD_WF8B_REG(LCD,22)
+#define LCD_WF23 LCD_WF8B_REG(LCD,23)
+#define LCD_WF24 LCD_WF8B_REG(LCD,24)
+#define LCD_WF27TO24 LCD_WF_REG(LCD,6)
+#define LCD_WF25 LCD_WF8B_REG(LCD,25)
+#define LCD_WF26 LCD_WF8B_REG(LCD,26)
+#define LCD_WF27 LCD_WF8B_REG(LCD,27)
+#define LCD_WF28 LCD_WF8B_REG(LCD,28)
+#define LCD_WF31TO28 LCD_WF_REG(LCD,7)
+#define LCD_WF29 LCD_WF8B_REG(LCD,29)
+#define LCD_WF30 LCD_WF8B_REG(LCD,30)
+#define LCD_WF31 LCD_WF8B_REG(LCD,31)
+#define LCD_WF32 LCD_WF8B_REG(LCD,32)
+#define LCD_WF35TO32 LCD_WF_REG(LCD,8)
+#define LCD_WF33 LCD_WF8B_REG(LCD,33)
+#define LCD_WF34 LCD_WF8B_REG(LCD,34)
+#define LCD_WF35 LCD_WF8B_REG(LCD,35)
+#define LCD_WF36 LCD_WF8B_REG(LCD,36)
+#define LCD_WF39TO36 LCD_WF_REG(LCD,9)
+#define LCD_WF37 LCD_WF8B_REG(LCD,37)
+#define LCD_WF38 LCD_WF8B_REG(LCD,38)
+#define LCD_WF39 LCD_WF8B_REG(LCD,39)
+#define LCD_WF40 LCD_WF8B_REG(LCD,40)
+#define LCD_WF43TO40 LCD_WF_REG(LCD,10)
+#define LCD_WF41 LCD_WF8B_REG(LCD,41)
+#define LCD_WF42 LCD_WF8B_REG(LCD,42)
+#define LCD_WF43 LCD_WF8B_REG(LCD,43)
+#define LCD_WF44 LCD_WF8B_REG(LCD,44)
+#define LCD_WF47TO44 LCD_WF_REG(LCD,11)
+#define LCD_WF45 LCD_WF8B_REG(LCD,45)
+#define LCD_WF46 LCD_WF8B_REG(LCD,46)
+#define LCD_WF47 LCD_WF8B_REG(LCD,47)
+#define LCD_WF48 LCD_WF8B_REG(LCD,48)
+#define LCD_WF51TO48 LCD_WF_REG(LCD,12)
+#define LCD_WF49 LCD_WF8B_REG(LCD,49)
+#define LCD_WF50 LCD_WF8B_REG(LCD,50)
+#define LCD_WF51 LCD_WF8B_REG(LCD,51)
+#define LCD_WF52 LCD_WF8B_REG(LCD,52)
+#define LCD_WF55TO52 LCD_WF_REG(LCD,13)
+#define LCD_WF53 LCD_WF8B_REG(LCD,53)
+#define LCD_WF54 LCD_WF8B_REG(LCD,54)
+#define LCD_WF55 LCD_WF8B_REG(LCD,55)
+#define LCD_WF56 LCD_WF8B_REG(LCD,56)
+#define LCD_WF59TO56 LCD_WF_REG(LCD,14)
+#define LCD_WF57 LCD_WF8B_REG(LCD,57)
+#define LCD_WF58 LCD_WF8B_REG(LCD,58)
+#define LCD_WF59 LCD_WF8B_REG(LCD,59)
+#define LCD_WF60 LCD_WF8B_REG(LCD,60)
+#define LCD_WF63TO60 LCD_WF_REG(LCD,15)
+#define LCD_WF61 LCD_WF8B_REG(LCD,61)
+#define LCD_WF62 LCD_WF8B_REG(LCD,62)
+#define LCD_WF63 LCD_WF8B_REG(LCD,63)
+
+/* LCD - Register array accessors */
+#define LCD_PEN(index) LCD_PEN_REG(LCD,index)
+#define LCD_BPEN(index) LCD_BPEN_REG(LCD,index)
+#define LCD_WF(index2) LCD_WF_REG(LCD,index2)
+#define LCD_WF8B(index2) LCD_WF8B_REG(LCD,index2)
+
+/*!
+ * @}
+ */ /* end of group LCD_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
+} LLWU_Type, *LLWU_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register accessors */
+#define LLWU_PE1_REG(base) ((base)->PE1)
+#define LLWU_PE2_REG(base) ((base)->PE2)
+#define LLWU_PE3_REG(base) ((base)->PE3)
+#define LLWU_PE4_REG(base) ((base)->PE4)
+#define LLWU_ME_REG(base) ((base)->ME)
+#define LLWU_F1_REG(base) ((base)->F1)
+#define LLWU_F2_REG(base) ((base)->F2)
+#define LLWU_F3_REG(base) ((base)->F3)
+#define LLWU_FILT1_REG(base) ((base)->FILT1)
+#define LLWU_FILT2_REG(base) ((base)->FILT2)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+#define LLWU_BASE_PTR (LLWU)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS { LLWU_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LLWU - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
+ * @{
+ */
+
+
+/* LLWU - Register instance definitions */
+/* LLWU */
+#define LLWU_PE1 LLWU_PE1_REG(LLWU)
+#define LLWU_PE2 LLWU_PE2_REG(LLWU)
+#define LLWU_PE3 LLWU_PE3_REG(LLWU)
+#define LLWU_PE4 LLWU_PE4_REG(LLWU)
+#define LLWU_ME LLWU_ME_REG(LLWU)
+#define LLWU_F1 LLWU_F1_REG(LLWU)
+#define LLWU_F2 LLWU_F2_REG(LLWU)
+#define LLWU_F3 LLWU_F3_REG(LLWU)
+#define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
+#define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type, *LPTMR_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register accessors */
+#define LPTMR_CSR_REG(base) ((base)->CSR)
+#define LPTMR_PSR_REG(base) ((base)->PSR)
+#define LPTMR_CMR_REG(base) ((base)->CMR)
+#define LPTMR_CNR_REG(base) ((base)->CNR)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0_BASE_PTR (LPTMR0)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS { LPTMR0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
+ * @{
+ */
+
+
+/* LPTMR - Register instance definitions */
+/* LPTMR0 */
+#define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
+#define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
+#define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
+#define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPUART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
+ * @{
+ */
+
+/** LPUART - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
+ __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
+ __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
+ __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
+ __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
+} LPUART_Type, *LPUART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- LPUART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
+ * @{
+ */
+
+
+/* LPUART - Register accessors */
+#define LPUART_BAUD_REG(base) ((base)->BAUD)
+#define LPUART_STAT_REG(base) ((base)->STAT)
+#define LPUART_CTRL_REG(base) ((base)->CTRL)
+#define LPUART_DATA_REG(base) ((base)->DATA)
+#define LPUART_MATCH_REG(base) ((base)->MATCH)
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPUART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Masks LPUART Register Masks
+ * @{
+ */
+
+/* BAUD Bit Fields */
+#define LPUART_BAUD_SBR_MASK 0x1FFFu
+#define LPUART_BAUD_SBR_SHIFT 0
+#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
+#define LPUART_BAUD_SBNS_MASK 0x2000u
+#define LPUART_BAUD_SBNS_SHIFT 13
+#define LPUART_BAUD_RXEDGIE_MASK 0x4000u
+#define LPUART_BAUD_RXEDGIE_SHIFT 14
+#define LPUART_BAUD_LBKDIE_MASK 0x8000u
+#define LPUART_BAUD_LBKDIE_SHIFT 15
+#define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
+#define LPUART_BAUD_RESYNCDIS_SHIFT 16
+#define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
+#define LPUART_BAUD_BOTHEDGE_SHIFT 17
+#define LPUART_BAUD_MATCFG_MASK 0xC0000u
+#define LPUART_BAUD_MATCFG_SHIFT 18
+#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
+#define LPUART_BAUD_RDMAE_MASK 0x200000u
+#define LPUART_BAUD_RDMAE_SHIFT 21
+#define LPUART_BAUD_TDMAE_MASK 0x800000u
+#define LPUART_BAUD_TDMAE_SHIFT 23
+#define LPUART_BAUD_OSR_MASK 0x1F000000u
+#define LPUART_BAUD_OSR_SHIFT 24
+#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
+#define LPUART_BAUD_M10_MASK 0x20000000u
+#define LPUART_BAUD_M10_SHIFT 29
+#define LPUART_BAUD_MAEN2_MASK 0x40000000u
+#define LPUART_BAUD_MAEN2_SHIFT 30
+#define LPUART_BAUD_MAEN1_MASK 0x80000000u
+#define LPUART_BAUD_MAEN1_SHIFT 31
+/* STAT Bit Fields */
+#define LPUART_STAT_MA2F_MASK 0x4000u
+#define LPUART_STAT_MA2F_SHIFT 14
+#define LPUART_STAT_MA1F_MASK 0x8000u
+#define LPUART_STAT_MA1F_SHIFT 15
+#define LPUART_STAT_PF_MASK 0x10000u
+#define LPUART_STAT_PF_SHIFT 16
+#define LPUART_STAT_FE_MASK 0x20000u
+#define LPUART_STAT_FE_SHIFT 17
+#define LPUART_STAT_NF_MASK 0x40000u
+#define LPUART_STAT_NF_SHIFT 18
+#define LPUART_STAT_OR_MASK 0x80000u
+#define LPUART_STAT_OR_SHIFT 19
+#define LPUART_STAT_IDLE_MASK 0x100000u
+#define LPUART_STAT_IDLE_SHIFT 20
+#define LPUART_STAT_RDRF_MASK 0x200000u
+#define LPUART_STAT_RDRF_SHIFT 21
+#define LPUART_STAT_TC_MASK 0x400000u
+#define LPUART_STAT_TC_SHIFT 22
+#define LPUART_STAT_TDRE_MASK 0x800000u
+#define LPUART_STAT_TDRE_SHIFT 23
+#define LPUART_STAT_RAF_MASK 0x1000000u
+#define LPUART_STAT_RAF_SHIFT 24
+#define LPUART_STAT_LBKDE_MASK 0x2000000u
+#define LPUART_STAT_LBKDE_SHIFT 25
+#define LPUART_STAT_BRK13_MASK 0x4000000u
+#define LPUART_STAT_BRK13_SHIFT 26
+#define LPUART_STAT_RWUID_MASK 0x8000000u
+#define LPUART_STAT_RWUID_SHIFT 27
+#define LPUART_STAT_RXINV_MASK 0x10000000u
+#define LPUART_STAT_RXINV_SHIFT 28
+#define LPUART_STAT_MSBF_MASK 0x20000000u
+#define LPUART_STAT_MSBF_SHIFT 29
+#define LPUART_STAT_RXEDGIF_MASK 0x40000000u
+#define LPUART_STAT_RXEDGIF_SHIFT 30
+#define LPUART_STAT_LBKDIF_MASK 0x80000000u
+#define LPUART_STAT_LBKDIF_SHIFT 31
+/* CTRL Bit Fields */
+#define LPUART_CTRL_PT_MASK 0x1u
+#define LPUART_CTRL_PT_SHIFT 0
+#define LPUART_CTRL_PE_MASK 0x2u
+#define LPUART_CTRL_PE_SHIFT 1
+#define LPUART_CTRL_ILT_MASK 0x4u
+#define LPUART_CTRL_ILT_SHIFT 2
+#define LPUART_CTRL_WAKE_MASK 0x8u
+#define LPUART_CTRL_WAKE_SHIFT 3
+#define LPUART_CTRL_M_MASK 0x10u
+#define LPUART_CTRL_M_SHIFT 4
+#define LPUART_CTRL_RSRC_MASK 0x20u
+#define LPUART_CTRL_RSRC_SHIFT 5
+#define LPUART_CTRL_DOZEEN_MASK 0x40u
+#define LPUART_CTRL_DOZEEN_SHIFT 6
+#define LPUART_CTRL_LOOPS_MASK 0x80u
+#define LPUART_CTRL_LOOPS_SHIFT 7
+#define LPUART_CTRL_IDLECFG_MASK 0x700u
+#define LPUART_CTRL_IDLECFG_SHIFT 8
+#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
+#define LPUART_CTRL_MA2IE_MASK 0x4000u
+#define LPUART_CTRL_MA2IE_SHIFT 14
+#define LPUART_CTRL_MA1IE_MASK 0x8000u
+#define LPUART_CTRL_MA1IE_SHIFT 15
+#define LPUART_CTRL_SBK_MASK 0x10000u
+#define LPUART_CTRL_SBK_SHIFT 16
+#define LPUART_CTRL_RWU_MASK 0x20000u
+#define LPUART_CTRL_RWU_SHIFT 17
+#define LPUART_CTRL_RE_MASK 0x40000u
+#define LPUART_CTRL_RE_SHIFT 18
+#define LPUART_CTRL_TE_MASK 0x80000u
+#define LPUART_CTRL_TE_SHIFT 19
+#define LPUART_CTRL_ILIE_MASK 0x100000u
+#define LPUART_CTRL_ILIE_SHIFT 20
+#define LPUART_CTRL_RIE_MASK 0x200000u
+#define LPUART_CTRL_RIE_SHIFT 21
+#define LPUART_CTRL_TCIE_MASK 0x400000u
+#define LPUART_CTRL_TCIE_SHIFT 22
+#define LPUART_CTRL_TIE_MASK 0x800000u
+#define LPUART_CTRL_TIE_SHIFT 23
+#define LPUART_CTRL_PEIE_MASK 0x1000000u
+#define LPUART_CTRL_PEIE_SHIFT 24
+#define LPUART_CTRL_FEIE_MASK 0x2000000u
+#define LPUART_CTRL_FEIE_SHIFT 25
+#define LPUART_CTRL_NEIE_MASK 0x4000000u
+#define LPUART_CTRL_NEIE_SHIFT 26
+#define LPUART_CTRL_ORIE_MASK 0x8000000u
+#define LPUART_CTRL_ORIE_SHIFT 27
+#define LPUART_CTRL_TXINV_MASK 0x10000000u
+#define LPUART_CTRL_TXINV_SHIFT 28
+#define LPUART_CTRL_TXDIR_MASK 0x20000000u
+#define LPUART_CTRL_TXDIR_SHIFT 29
+#define LPUART_CTRL_R9T8_MASK 0x40000000u
+#define LPUART_CTRL_R9T8_SHIFT 30
+#define LPUART_CTRL_R8T9_MASK 0x80000000u
+#define LPUART_CTRL_R8T9_SHIFT 31
+/* DATA Bit Fields */
+#define LPUART_DATA_R0T0_MASK 0x1u
+#define LPUART_DATA_R0T0_SHIFT 0
+#define LPUART_DATA_R1T1_MASK 0x2u
+#define LPUART_DATA_R1T1_SHIFT 1
+#define LPUART_DATA_R2T2_MASK 0x4u
+#define LPUART_DATA_R2T2_SHIFT 2
+#define LPUART_DATA_R3T3_MASK 0x8u
+#define LPUART_DATA_R3T3_SHIFT 3
+#define LPUART_DATA_R4T4_MASK 0x10u
+#define LPUART_DATA_R4T4_SHIFT 4
+#define LPUART_DATA_R5T5_MASK 0x20u
+#define LPUART_DATA_R5T5_SHIFT 5
+#define LPUART_DATA_R6T6_MASK 0x40u
+#define LPUART_DATA_R6T6_SHIFT 6
+#define LPUART_DATA_R7T7_MASK 0x80u
+#define LPUART_DATA_R7T7_SHIFT 7
+#define LPUART_DATA_R8T8_MASK 0x100u
+#define LPUART_DATA_R8T8_SHIFT 8
+#define LPUART_DATA_R9T9_MASK 0x200u
+#define LPUART_DATA_R9T9_SHIFT 9
+#define LPUART_DATA_IDLINE_MASK 0x800u
+#define LPUART_DATA_IDLINE_SHIFT 11
+#define LPUART_DATA_RXEMPT_MASK 0x1000u
+#define LPUART_DATA_RXEMPT_SHIFT 12
+#define LPUART_DATA_FRETSC_MASK 0x2000u
+#define LPUART_DATA_FRETSC_SHIFT 13
+#define LPUART_DATA_PARITYE_MASK 0x4000u
+#define LPUART_DATA_PARITYE_SHIFT 14
+#define LPUART_DATA_NOISY_MASK 0x8000u
+#define LPUART_DATA_NOISY_SHIFT 15
+/* MATCH Bit Fields */
+#define LPUART_MATCH_MA1_MASK 0x3FFu
+#define LPUART_MATCH_MA1_SHIFT 0
+#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
+#define LPUART_MATCH_MA2_MASK 0x3FF0000u
+#define LPUART_MATCH_MA2_SHIFT 16
+#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Masks */
+
+
+/* LPUART - Peripheral instance base addresses */
+/** Peripheral LPUART0 base address */
+#define LPUART0_BASE (0x40054000u)
+/** Peripheral LPUART0 base pointer */
+#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
+#define LPUART0_BASE_PTR (LPUART0)
+/** Peripheral LPUART1 base address */
+#define LPUART1_BASE (0x40055000u)
+/** Peripheral LPUART1 base pointer */
+#define LPUART1 ((LPUART_Type *)LPUART1_BASE)
+#define LPUART1_BASE_PTR (LPUART1)
+/** Array initializer of LPUART peripheral base addresses */
+#define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE }
+/** Array initializer of LPUART peripheral base pointers */
+#define LPUART_BASE_PTRS { LPUART0, LPUART1 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn }
+#define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- LPUART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
+ * @{
+ */
+
+
+/* LPUART - Register instance definitions */
+/* LPUART0 */
+#define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
+#define LPUART0_STAT LPUART_STAT_REG(LPUART0)
+#define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
+#define LPUART0_DATA LPUART_DATA_REG(LPUART0)
+#define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
+/* LPUART1 */
+#define LPUART1_BAUD LPUART_BAUD_REG(LPUART1)
+#define LPUART1_STAT LPUART_STAT_REG(LPUART1)
+#define LPUART1_CTRL LPUART_CTRL_REG(LPUART1)
+#define LPUART1_DATA LPUART_DATA_REG(LPUART1)
+#define LPUART1_MATCH LPUART_MATCH_REG(LPUART1)
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group LPUART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control Register 1, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control Register 2, offset: 0x1 */
+ uint8_t RESERVED_0[4];
+ __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_2[11];
+ __I uint8_t HCTRIM; /**< MCG High-frequency IRC Coarse Trim Register, offset: 0x14 */
+ __I uint8_t HTTRIM; /**< MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register, offset: 0x15 */
+ __I uint8_t HFTRIM; /**< MCG High-frequency IRC Fine Trim Register, offset: 0x16 */
+ uint8_t RESERVED_3[1];
+ __IO uint8_t MC; /**< MCG Miscellaneous Control Register, offset: 0x18 */
+ __I uint8_t LTRIMRNG; /**< MCG Low-frequency IRC Trim Range Register, offset: 0x19 */
+ __I uint8_t LFTRIM; /**< MCG Low-frequency IRC8M Trim Register, offset: 0x1A */
+ __I uint8_t LSTRIM; /**< MCG Low-frequency IRC2M Trim Register, offset: 0x1B */
+} MCG_Type, *MCG_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MCG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register accessors */
+#define MCG_C1_REG(base) ((base)->C1)
+#define MCG_C2_REG(base) ((base)->C2)
+#define MCG_S_REG(base) ((base)->S)
+#define MCG_SC_REG(base) ((base)->SC)
+#define MCG_HCTRIM_REG(base) ((base)->HCTRIM)
+#define MCG_HTTRIM_REG(base) ((base)->HTTRIM)
+#define MCG_HFTRIM_REG(base) ((base)->HFTRIM)
+#define MCG_MC_REG(base) ((base)->MC)
+#define MCG_LTRIMRNG_REG(base) ((base)->LTRIMRNG)
+#define MCG_LFTRIM_REG(base) ((base)->LFTRIM)
+#define MCG_LSTRIM_REG(base) ((base)->LSTRIM)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_EREFS0_MASK 0x4u
+#define MCG_C2_EREFS0_SHIFT 2
+#define MCG_C2_HGO0_MASK 0x8u
+#define MCG_C2_HGO0_SHIFT 3
+#define MCG_C2_RANGE0_MASK 0x30u
+#define MCG_C2_RANGE0_SHIFT 4
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+/* S Bit Fields */
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+/* SC Bit Fields */
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+/* HCTRIM Bit Fields */
+#define MCG_HCTRIM_COARSE_TRIM_MASK 0x3Fu
+#define MCG_HCTRIM_COARSE_TRIM_SHIFT 0
+#define MCG_HCTRIM_COARSE_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HCTRIM_COARSE_TRIM_SHIFT))&MCG_HCTRIM_COARSE_TRIM_MASK)
+/* HTTRIM Bit Fields */
+#define MCG_HTTRIM_TEMPCO_TRIM_MASK 0x1Fu
+#define MCG_HTTRIM_TEMPCO_TRIM_SHIFT 0
+#define MCG_HTTRIM_TEMPCO_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HTTRIM_TEMPCO_TRIM_SHIFT))&MCG_HTTRIM_TEMPCO_TRIM_MASK)
+/* HFTRIM Bit Fields */
+#define MCG_HFTRIM_FINE_TRIM_MASK 0x7Fu
+#define MCG_HFTRIM_FINE_TRIM_SHIFT 0
+#define MCG_HFTRIM_FINE_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HFTRIM_FINE_TRIM_SHIFT))&MCG_HFTRIM_FINE_TRIM_MASK)
+/* MC Bit Fields */
+#define MCG_MC_LIRC_DIV2_MASK 0x7u
+#define MCG_MC_LIRC_DIV2_SHIFT 0
+#define MCG_MC_LIRC_DIV2(x) (((uint8_t)(((uint8_t)(x))<<MCG_MC_LIRC_DIV2_SHIFT))&MCG_MC_LIRC_DIV2_MASK)
+#define MCG_MC_HIRCEN_MASK 0x80u
+#define MCG_MC_HIRCEN_SHIFT 7
+/* LTRIMRNG Bit Fields */
+#define MCG_LTRIMRNG_STRIMRNG_MASK 0x3u
+#define MCG_LTRIMRNG_STRIMRNG_SHIFT 0
+#define MCG_LTRIMRNG_STRIMRNG(x) (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_STRIMRNG_SHIFT))&MCG_LTRIMRNG_STRIMRNG_MASK)
+#define MCG_LTRIMRNG_FTRIMRNG_MASK 0xCu
+#define MCG_LTRIMRNG_FTRIMRNG_SHIFT 2
+#define MCG_LTRIMRNG_FTRIMRNG(x) (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_FTRIMRNG_SHIFT))&MCG_LTRIMRNG_FTRIMRNG_MASK)
+/* LFTRIM Bit Fields */
+#define MCG_LFTRIM_LIRC_FTRIM_MASK 0x7Fu
+#define MCG_LFTRIM_LIRC_FTRIM_SHIFT 0
+#define MCG_LFTRIM_LIRC_FTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_LFTRIM_LIRC_FTRIM_SHIFT))&MCG_LFTRIM_LIRC_FTRIM_MASK)
+/* LSTRIM Bit Fields */
+#define MCG_LSTRIM_LIRC_STRIM_MASK 0x7Fu
+#define MCG_LSTRIM_LIRC_STRIM_SHIFT 0
+#define MCG_LSTRIM_LIRC_STRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_LSTRIM_LIRC_STRIM_SHIFT))&MCG_LSTRIM_LIRC_STRIM_MASK)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+#define MCG_BASE_PTR (MCG)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS { MCG }
+
+/* ----------------------------------------------------------------------------
+ -- MCG - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
+ * @{
+ */
+
+
+/* MCG - Register instance definitions */
+/* MCG */
+#define MCG_C1 MCG_C1_REG(MCG)
+#define MCG_C2 MCG_C2_REG(MCG)
+#define MCG_S MCG_S_REG(MCG)
+#define MCG_SC MCG_SC_REG(MCG)
+#define MCG_HCTRIM MCG_HCTRIM_REG(MCG)
+#define MCG_HTTRIM MCG_HTTRIM_REG(MCG)
+#define MCG_HFTRIM MCG_HFTRIM_REG(MCG)
+#define MCG_MC MCG_MC_REG(MCG)
+#define MCG_LTRIMRNG MCG_LTRIMRNG_REG(MCG)
+#define MCG_LFTRIM MCG_LFTRIM_REG(MCG)
+#define MCG_LSTRIM MCG_LSTRIM_REG(MCG)
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type, *MCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register accessors */
+#define MCM_PLASC_REG(base) ((base)->PLASC)
+#define MCM_PLAMC_REG(base) ((base)->PLAMC)
+#define MCM_PLACR_REG(base) ((base)->PLACR)
+#define MCM_CPO_REG(base) ((base)->CPO)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK 0xFFu
+#define MCM_PLASC_ASC_SHIFT 0
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK 0xFFu
+#define MCM_PLAMC_AMC_SHIFT 0
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_ARB_MASK 0x200u
+#define MCM_PLACR_ARB_SHIFT 9
+#define MCM_PLACR_CFCC_MASK 0x400u
+#define MCM_PLACR_CFCC_SHIFT 10
+#define MCM_PLACR_DFCDA_MASK 0x800u
+#define MCM_PLACR_DFCDA_SHIFT 11
+#define MCM_PLACR_DFCIC_MASK 0x1000u
+#define MCM_PLACR_DFCIC_SHIFT 12
+#define MCM_PLACR_DFCC_MASK 0x2000u
+#define MCM_PLACR_DFCC_SHIFT 13
+#define MCM_PLACR_EFDS_MASK 0x4000u
+#define MCM_PLACR_EFDS_SHIFT 14
+#define MCM_PLACR_DFCS_MASK 0x8000u
+#define MCM_PLACR_DFCS_SHIFT 15
+#define MCM_PLACR_ESFC_MASK 0x10000u
+#define MCM_PLACR_ESFC_SHIFT 16
+/* CPO Bit Fields */
+#define MCM_CPO_CPOREQ_MASK 0x1u
+#define MCM_CPO_CPOREQ_SHIFT 0
+#define MCM_CPO_CPOACK_MASK 0x2u
+#define MCM_CPO_CPOACK_SHIFT 1
+#define MCM_CPO_CPOWOI_MASK 0x4u
+#define MCM_CPO_CPOWOI_SHIFT 2
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+#define MCM_BASE_PTR (MCM)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS { MCM }
+
+/* ----------------------------------------------------------------------------
+ -- MCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
+ * @{
+ */
+
+
+/* MCM - Register instance definitions */
+/* MCM */
+#define MCM_PLASC MCM_PLASC_REG(MCM)
+#define MCM_PLAMC MCM_PLAMC_REG(MCM)
+#define MCM_PLACR MCM_PLACR_REG(MCM)
+#define MCM_CPO MCM_CPO_REG(MCM)
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
+ __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
+ __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
+ __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
+ uint8_t RESERVED_0[3824];
+ __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
+ uint8_t RESERVED_1[156];
+ __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
+ __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
+ uint8_t RESERVED_2[8];
+ __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
+ __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
+ __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
+ __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
+ uint8_t RESERVED_3[8];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type, *MTB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MTB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
+ * @{
+ */
+
+
+/* MTB - Register accessors */
+#define MTB_POSITION_REG(base) ((base)->POSITION)
+#define MTB_MASTER_REG(base) ((base)->MASTER)
+#define MTB_FLOW_REG(base) ((base)->FLOW)
+#define MTB_BASE_REG(base) ((base)->BASE)
+#define MTB_MODECTRL_REG(base) ((base)->MODECTRL)
+#define MTB_TAGSET_REG(base) ((base)->TAGSET)
+#define MTB_TAGCLEAR_REG(base) ((base)->TAGCLEAR)
+#define MTB_LOCKACCESS_REG(base) ((base)->LOCKACCESS)
+#define MTB_LOCKSTAT_REG(base) ((base)->LOCKSTAT)
+#define MTB_AUTHSTAT_REG(base) ((base)->AUTHSTAT)
+#define MTB_DEVICEARCH_REG(base) ((base)->DEVICEARCH)
+#define MTB_DEVICECFG_REG(base) ((base)->DEVICECFG)
+#define MTB_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
+#define MTB_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
+#define MTB_COMPID_REG(base,index) ((base)->COMPID[index])
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/* POSITION Bit Fields */
+#define MTB_POSITION_WRAP_MASK 0x4u
+#define MTB_POSITION_WRAP_SHIFT 2
+#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
+#define MTB_POSITION_POINTER_SHIFT 3
+#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
+/* MASTER Bit Fields */
+#define MTB_MASTER_MASK_MASK 0x1Fu
+#define MTB_MASTER_MASK_SHIFT 0
+#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK 0x20u
+#define MTB_MASTER_TSTARTEN_SHIFT 5
+#define MTB_MASTER_TSTOPEN_MASK 0x40u
+#define MTB_MASTER_TSTOPEN_SHIFT 6
+#define MTB_MASTER_SFRWPRIV_MASK 0x80u
+#define MTB_MASTER_SFRWPRIV_SHIFT 7
+#define MTB_MASTER_RAMPRIV_MASK 0x100u
+#define MTB_MASTER_RAMPRIV_SHIFT 8
+#define MTB_MASTER_HALTREQ_MASK 0x200u
+#define MTB_MASTER_HALTREQ_SHIFT 9
+#define MTB_MASTER_EN_MASK 0x80000000u
+#define MTB_MASTER_EN_SHIFT 31
+/* FLOW Bit Fields */
+#define MTB_FLOW_AUTOSTOP_MASK 0x1u
+#define MTB_FLOW_AUTOSTOP_SHIFT 0
+#define MTB_FLOW_AUTOHALT_MASK 0x2u
+#define MTB_FLOW_AUTOHALT_SHIFT 1
+#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
+#define MTB_FLOW_WATERMARK_SHIFT 3
+#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
+/* BASE Bit Fields */
+#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
+#define MTB_BASE_BASEADDR_SHIFT 0
+#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
+/* MODECTRL Bit Fields */
+#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
+#define MTB_MODECTRL_MODECTRL_SHIFT 0
+#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
+/* TAGSET Bit Fields */
+#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
+#define MTB_TAGSET_TAGSET_SHIFT 0
+#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
+/* TAGCLEAR Bit Fields */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
+#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
+/* LOCKACCESS Bit Fields */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
+#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
+/* LOCKSTAT Bit Fields */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
+#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
+/* AUTHSTAT Bit Fields */
+#define MTB_AUTHSTAT_BIT0_MASK 0x1u
+#define MTB_AUTHSTAT_BIT0_SHIFT 0
+#define MTB_AUTHSTAT_BIT1_MASK 0x2u
+#define MTB_AUTHSTAT_BIT1_SHIFT 1
+#define MTB_AUTHSTAT_BIT2_MASK 0x4u
+#define MTB_AUTHSTAT_BIT2_SHIFT 2
+#define MTB_AUTHSTAT_BIT3_MASK 0x8u
+#define MTB_AUTHSTAT_BIT3_SHIFT 3
+/* DEVICEARCH Bit Fields */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
+#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
+/* DEVICECFG Bit Fields */
+#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTB_PERIPHID_PERIPHID_SHIFT 0
+#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTB_COMPID_COMPID_SHIFT 0
+#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB ((MTB_Type *)MTB_BASE)
+#define MTB_BASE_PTR (MTB)
+/** Array initializer of MTB peripheral base addresses */
+#define MTB_BASE_ADDRS { MTB_BASE }
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASE_PTRS { MTB }
+
+/* ----------------------------------------------------------------------------
+ -- MTB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
+ * @{
+ */
+
+
+/* MTB - Register instance definitions */
+/* MTB */
+#define MTB_POSITION MTB_POSITION_REG(MTB)
+#define MTB_MASTER MTB_MASTER_REG(MTB)
+#define MTB_FLOW MTB_FLOW_REG(MTB)
+#define MTB_BASEr MTB_BASE_REG(MTB)
+#define MTB_MODECTRL MTB_MODECTRL_REG(MTB)
+#define MTB_TAGSET MTB_TAGSET_REG(MTB)
+#define MTB_TAGCLEAR MTB_TAGCLEAR_REG(MTB)
+#define MTB_LOCKACCESS MTB_LOCKACCESS_REG(MTB)
+#define MTB_LOCKSTAT MTB_LOCKSTAT_REG(MTB)
+#define MTB_AUTHSTAT MTB_AUTHSTAT_REG(MTB)
+#define MTB_DEVICEARCH MTB_DEVICEARCH_REG(MTB)
+#define MTB_DEVICECFG MTB_DEVICECFG_REG(MTB)
+#define MTB_DEVICETYPID MTB_DEVICETYPID_REG(MTB)
+#define MTB_PERIPHID4 MTB_PERIPHID_REG(MTB,0)
+#define MTB_PERIPHID5 MTB_PERIPHID_REG(MTB,1)
+#define MTB_PERIPHID6 MTB_PERIPHID_REG(MTB,2)
+#define MTB_PERIPHID7 MTB_PERIPHID_REG(MTB,3)
+#define MTB_PERIPHID0 MTB_PERIPHID_REG(MTB,4)
+#define MTB_PERIPHID1 MTB_PERIPHID_REG(MTB,5)
+#define MTB_PERIPHID2 MTB_PERIPHID_REG(MTB,6)
+#define MTB_PERIPHID3 MTB_PERIPHID_REG(MTB,7)
+#define MTB_COMPID0 MTB_COMPID_REG(MTB,0)
+#define MTB_COMPID1 MTB_COMPID_REG(MTB,1)
+#define MTB_COMPID2 MTB_COMPID_REG(MTB,2)
+#define MTB_COMPID3 MTB_COMPID_REG(MTB,3)
+
+/* MTB - Register array accessors */
+#define MTB_PERIPHID(index) MTB_PERIPHID_REG(MTB,index)
+#define MTB_COMPID(index) MTB_COMPID_REG(MTB,index)
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+ __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ struct { /* offset: 0x20, array step: 0x10 */
+ __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+ __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+ __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } COMPARATOR[2];
+ uint8_t RESERVED_1[448];
+ __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+ uint8_t RESERVED_2[3524];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type, *MTBDWT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
+ * @{
+ */
+
+
+/* MTBDWT - Register accessors */
+#define MTBDWT_CTRL_REG(base) ((base)->CTRL)
+#define MTBDWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP)
+#define MTBDWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK)
+#define MTBDWT_FCT_REG(base,index) ((base)->COMPARATOR[index].FCT)
+#define MTBDWT_TBCTRL_REG(base) ((base)->TBCTRL)
+#define MTBDWT_DEVICECFG_REG(base) ((base)->DEVICECFG)
+#define MTBDWT_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
+#define MTBDWT_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
+#define MTBDWT_COMPID_REG(base,index) ((base)->COMPID[index])
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
+#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
+#define MTBDWT_CTRL_NUMCMP_SHIFT 28
+#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
+/* COMP Bit Fields */
+#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
+#define MTBDWT_COMP_COMP_SHIFT 0
+#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
+/* MASK Bit Fields */
+#define MTBDWT_MASK_MASK_MASK 0x1Fu
+#define MTBDWT_MASK_MASK_SHIFT 0
+#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
+/* FCT Bit Fields */
+#define MTBDWT_FCT_FUNCTION_MASK 0xFu
+#define MTBDWT_FCT_FUNCTION_SHIFT 0
+#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
+#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
+#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
+#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
+#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
+#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
+#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
+#define MTBDWT_FCT_MATCHED_SHIFT 24
+/* TBCTRL Bit Fields */
+#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
+#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
+#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
+#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
+/* DEVICECFG Bit Fields */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
+#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTBDWT_COMPID_COMPID_SHIFT 0
+#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
+#define MTBDWT_BASE_PTR (MTBDWT)
+/** Array initializer of MTBDWT peripheral base addresses */
+#define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASE_PTRS { MTBDWT }
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
+ * @{
+ */
+
+
+/* MTBDWT - Register instance definitions */
+/* MTBDWT */
+#define MTBDWT_CTRL MTBDWT_CTRL_REG(MTBDWT)
+#define MTBDWT_COMP0 MTBDWT_COMP_REG(MTBDWT,0)
+#define MTBDWT_MASK0 MTBDWT_MASK_REG(MTBDWT,0)
+#define MTBDWT_FCT0 MTBDWT_FCT_REG(MTBDWT,0)
+#define MTBDWT_COMP1 MTBDWT_COMP_REG(MTBDWT,1)
+#define MTBDWT_MASK1 MTBDWT_MASK_REG(MTBDWT,1)
+#define MTBDWT_FCT1 MTBDWT_FCT_REG(MTBDWT,1)
+#define MTBDWT_TBCTRL MTBDWT_TBCTRL_REG(MTBDWT)
+#define MTBDWT_DEVICECFG MTBDWT_DEVICECFG_REG(MTBDWT)
+#define MTBDWT_DEVICETYPID MTBDWT_DEVICETYPID_REG(MTBDWT)
+#define MTBDWT_PERIPHID4 MTBDWT_PERIPHID_REG(MTBDWT,0)
+#define MTBDWT_PERIPHID5 MTBDWT_PERIPHID_REG(MTBDWT,1)
+#define MTBDWT_PERIPHID6 MTBDWT_PERIPHID_REG(MTBDWT,2)
+#define MTBDWT_PERIPHID7 MTBDWT_PERIPHID_REG(MTBDWT,3)
+#define MTBDWT_PERIPHID0 MTBDWT_PERIPHID_REG(MTBDWT,4)
+#define MTBDWT_PERIPHID1 MTBDWT_PERIPHID_REG(MTBDWT,5)
+#define MTBDWT_PERIPHID2 MTBDWT_PERIPHID_REG(MTBDWT,6)
+#define MTBDWT_PERIPHID3 MTBDWT_PERIPHID_REG(MTBDWT,7)
+#define MTBDWT_COMPID0 MTBDWT_COMPID_REG(MTBDWT,0)
+#define MTBDWT_COMPID1 MTBDWT_COMPID_REG(MTBDWT,1)
+#define MTBDWT_COMPID2 MTBDWT_COMPID_REG(MTBDWT,2)
+#define MTBDWT_COMPID3 MTBDWT_COMPID_REG(MTBDWT,3)
+
+/* MTBDWT - Register array accessors */
+#define MTBDWT_COMP(index) MTBDWT_COMP_REG(MTBDWT,index)
+#define MTBDWT_MASK(index) MTBDWT_MASK_REG(MTBDWT,index)
+#define MTBDWT_FCT(index) MTBDWT_FCT_REG(MTBDWT,index)
+#define MTBDWT_PERIPHID(index) MTBDWT_PERIPHID_REG(MTBDWT,index)
+#define MTBDWT_COMPID(index) MTBDWT_COMPID_REG(MTBDWT,index)
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type, *NV_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- NV - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register accessors */
+#define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
+#define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
+#define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
+#define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
+#define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
+#define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
+#define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
+#define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
+#define NV_FPROT3_REG(base) ((base)->FPROT3)
+#define NV_FPROT2_REG(base) ((base)->FPROT2)
+#define NV_FPROT1_REG(base) ((base)->FPROT1)
+#define NV_FPROT0_REG(base) ((base)->FPROT0)
+#define NV_FSEC_REG(base) ((base)->FSEC)
+#define NV_FOPT_REG(base) ((base)->FOPT)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT0_MASK 0x1u
+#define NV_FOPT_LPBOOT0_SHIFT 0
+#define NV_FOPT_BOOTPIN_OPT_MASK 0x2u
+#define NV_FOPT_BOOTPIN_OPT_SHIFT 1
+#define NV_FOPT_NMI_DIS_MASK 0x4u
+#define NV_FOPT_NMI_DIS_SHIFT 2
+#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
+#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
+#define NV_FOPT_LPBOOT1_MASK 0x10u
+#define NV_FOPT_LPBOOT1_SHIFT 4
+#define NV_FOPT_FAST_INIT_MASK 0x20u
+#define NV_FOPT_FAST_INIT_SHIFT 5
+#define NV_FOPT_BOOTSRC_SEL_MASK 0xC0u
+#define NV_FOPT_BOOTSRC_SEL_SHIFT 6
+#define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_BOOTSRC_SEL_SHIFT))&NV_FOPT_BOOTSRC_SEL_MASK)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
+#define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS { FTFA_FlashConfig }
+
+/* ----------------------------------------------------------------------------
+ -- NV - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
+ * @{
+ */
+
+
+/* NV - Register instance definitions */
+/* FTFA_FlashConfig */
+#define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
+#define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
+#define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
+#define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
+#define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
+#define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
+#define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
+#define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
+#define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
+#define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
+#define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
+#define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
+#define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
+#define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type, *OSC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- OSC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register accessors */
+#define OSC_CR_REG(base) ((base)->CR)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+#define OSC0_BASE_PTR (OSC0)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS { OSC0_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS { OSC0 }
+
+/* ----------------------------------------------------------------------------
+ -- OSC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
+ * @{
+ */
+
+
+/* OSC - Register instance definitions */
+/* OSC0 */
+#define OSC0_CR OSC_CR_REG(OSC0)
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[220];
+ __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+ __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+ uint8_t RESERVED_1[24];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[2];
+} PIT_Type, *PIT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PIT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register accessors */
+#define PIT_MCR_REG(base) ((base)->MCR)
+#define PIT_LTMR64H_REG(base) ((base)->LTMR64H)
+#define PIT_LTMR64L_REG(base) ((base)->LTMR64L)
+#define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
+#define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
+#define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
+#define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LTMR64H Bit Fields */
+#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
+#define PIT_LTMR64H_LTH_SHIFT 0
+#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
+/* LTMR64L Bit Fields */
+#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
+#define PIT_LTMR64L_LTL_SHIFT 0
+#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+#define PIT_TCTRL_CHN_MASK 0x4u
+#define PIT_TCTRL_CHN_SHIFT 2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+#define PIT_BASE_PTR (PIT)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS { PIT_IRQn, PIT_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PIT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
+ * @{
+ */
+
+
+/* PIT - Register instance definitions */
+/* PIT */
+#define PIT_MCR PIT_MCR_REG(PIT)
+#define PIT_LTMR64H PIT_LTMR64H_REG(PIT)
+#define PIT_LTMR64L PIT_LTMR64L_REG(PIT)
+#define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
+#define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
+#define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
+#define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
+#define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
+#define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
+#define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
+#define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
+
+/* PIT - Register array accessors */
+#define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
+#define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
+#define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
+#define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type, *PMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register accessors */
+#define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
+#define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
+#define PMC_REGSC_REG(base) ((base)->REGSC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+#define PMC_REGSC_BGEN_MASK 0x10u
+#define PMC_REGSC_BGEN_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+#define PMC_BASE_PTR (PMC)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS { PMC_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
+ * @{
+ */
+
+
+/* PMC - Register instance definitions */
+/* PMC */
+#define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
+#define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
+#define PMC_REGSC PMC_REGSC_REG(PMC)
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type, *PORT_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- PORT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register accessors */
+#define PORT_PCR_REG(base,index) ((base)->PCR[index])
+#define PORT_GPCLR_REG(base) ((base)->GPCLR)
+#define PORT_GPCHR_REG(base) ((base)->GPCHR)
+#define PORT_ISFR_REG(base) ((base)->ISFR)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+#define PORTA_BASE_PTR (PORTA)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+#define PORTB_BASE_PTR (PORTB)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+#define PORTC_BASE_PTR (PORTC)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+#define PORTD_BASE_PTR (PORTD)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+#define PORTE_BASE_PTR (PORTE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, PORTCD_IRQn, PORTCD_IRQn, NotAvail_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- PORT - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
+ * @{
+ */
+
+
+/* PORT - Register instance definitions */
+/* PORTA */
+#define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
+#define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
+#define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
+#define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
+#define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
+#define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
+#define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
+#define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
+#define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
+#define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
+#define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
+#define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
+#define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
+#define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
+#define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
+#define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
+#define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
+#define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
+#define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
+#define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
+#define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
+#define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
+#define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
+#define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
+#define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
+#define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
+#define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
+#define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
+#define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
+#define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
+#define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
+#define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
+#define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
+#define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
+#define PORTA_ISFR PORT_ISFR_REG(PORTA)
+/* PORTB */
+#define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
+#define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
+#define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
+#define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
+#define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
+#define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
+#define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
+#define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
+#define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
+#define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
+#define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
+#define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
+#define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
+#define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
+#define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
+#define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
+#define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
+#define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
+#define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
+#define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
+#define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
+#define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
+#define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
+#define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
+#define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
+#define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
+#define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
+#define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
+#define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
+#define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
+#define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
+#define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
+#define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
+#define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
+#define PORTB_ISFR PORT_ISFR_REG(PORTB)
+/* PORTC */
+#define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
+#define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
+#define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
+#define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
+#define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
+#define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
+#define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
+#define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
+#define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
+#define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
+#define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
+#define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
+#define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
+#define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
+#define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
+#define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
+#define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
+#define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
+#define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
+#define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
+#define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
+#define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
+#define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
+#define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
+#define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
+#define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
+#define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
+#define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
+#define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
+#define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
+#define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
+#define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
+#define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
+#define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
+#define PORTC_ISFR PORT_ISFR_REG(PORTC)
+/* PORTD */
+#define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
+#define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
+#define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
+#define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
+#define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
+#define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
+#define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
+#define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
+#define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
+#define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
+#define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
+#define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
+#define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
+#define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
+#define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
+#define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
+#define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
+#define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
+#define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
+#define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
+#define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
+#define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
+#define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
+#define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
+#define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
+#define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
+#define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
+#define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
+#define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
+#define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
+#define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
+#define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
+#define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
+#define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
+#define PORTD_ISFR PORT_ISFR_REG(PORTD)
+/* PORTE */
+#define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
+#define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
+#define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
+#define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
+#define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
+#define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
+#define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
+#define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
+#define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
+#define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
+#define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
+#define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
+#define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
+#define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
+#define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
+#define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
+#define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
+#define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
+#define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
+#define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
+#define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
+#define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
+#define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
+#define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
+#define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
+#define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
+#define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
+#define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
+#define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
+#define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
+#define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
+#define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
+#define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
+#define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
+#define PORTE_ISFR PORT_ISFR_REG(PORTE)
+
+/* PORT - Register array accessors */
+#define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
+#define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
+#define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
+#define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
+#define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+ __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */
+ __IO uint8_t MR; /**< Mode Register, offset: 0x7 */
+ __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
+ __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
+} RCM_Type, *RCM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register accessors */
+#define RCM_SRS0_REG(base) ((base)->SRS0)
+#define RCM_SRS1_REG(base) ((base)->SRS1)
+#define RCM_RPFC_REG(base) ((base)->RPFC)
+#define RCM_RPFW_REG(base) ((base)->RPFW)
+#define RCM_FM_REG(base) ((base)->FM)
+#define RCM_MR_REG(base) ((base)->MR)
+#define RCM_SSRS0_REG(base) ((base)->SSRS0)
+#define RCM_SSRS1_REG(base) ((base)->SSRS1)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+/* FM Bit Fields */
+#define RCM_FM_FORCEROM_MASK 0x6u
+#define RCM_FM_FORCEROM_SHIFT 1
+#define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x))<<RCM_FM_FORCEROM_SHIFT))&RCM_FM_FORCEROM_MASK)
+/* MR Bit Fields */
+#define RCM_MR_BOOTROM_MASK 0x6u
+#define RCM_MR_BOOTROM_SHIFT 1
+#define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x))<<RCM_MR_BOOTROM_SHIFT))&RCM_MR_BOOTROM_MASK)
+/* SSRS0 Bit Fields */
+#define RCM_SSRS0_SWAKEUP_MASK 0x1u
+#define RCM_SSRS0_SWAKEUP_SHIFT 0
+#define RCM_SSRS0_SLVD_MASK 0x2u
+#define RCM_SSRS0_SLVD_SHIFT 1
+#define RCM_SSRS0_SWDOG_MASK 0x20u
+#define RCM_SSRS0_SWDOG_SHIFT 5
+#define RCM_SSRS0_SPIN_MASK 0x40u
+#define RCM_SSRS0_SPIN_SHIFT 6
+#define RCM_SSRS0_SPOR_MASK 0x80u
+#define RCM_SSRS0_SPOR_SHIFT 7
+/* SSRS1 Bit Fields */
+#define RCM_SSRS1_SLOCKUP_MASK 0x2u
+#define RCM_SSRS1_SLOCKUP_SHIFT 1
+#define RCM_SSRS1_SSW_MASK 0x4u
+#define RCM_SSRS1_SSW_SHIFT 2
+#define RCM_SSRS1_SMDM_AP_MASK 0x8u
+#define RCM_SSRS1_SMDM_AP_SHIFT 3
+#define RCM_SSRS1_SSACKERR_MASK 0x20u
+#define RCM_SSRS1_SSACKERR_SHIFT 5
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+#define RCM_BASE_PTR (RCM)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS { RCM }
+
+/* ----------------------------------------------------------------------------
+ -- RCM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
+ * @{
+ */
+
+
+/* RCM - Register instance definitions */
+/* RCM */
+#define RCM_SRS0 RCM_SRS0_REG(RCM)
+#define RCM_SRS1 RCM_SRS1_REG(RCM)
+#define RCM_RPFC RCM_RPFC_REG(RCM)
+#define RCM_RPFW RCM_RPFW_REG(RCM)
+#define RCM_FM RCM_FM_REG(RCM)
+#define RCM_MR RCM_MR_REG(RCM)
+#define RCM_SSRS0 RCM_SSRS0_REG(RCM)
+#define RCM_SSRS1 RCM_SSRS1_REG(RCM)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type, *RFSYS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register accessors */
+#define RFSYS_REG_REG(base,index) ((base)->REG[index])
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK 0xFFu
+#define RFSYS_REG_LL_SHIFT 0
+#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK 0xFF00u
+#define RFSYS_REG_LH_SHIFT 8
+#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK 0xFF0000u
+#define RFSYS_REG_HL_SHIFT 16
+#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK 0xFF000000u
+#define RFSYS_REG_HH_SHIFT 24
+#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS_BASE_PTR (RFSYS)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS { RFSYS }
+
+/* ----------------------------------------------------------------------------
+ -- RFSYS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
+ * @{
+ */
+
+
+/* RFSYS - Register instance definitions */
+/* RFSYS */
+#define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
+#define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
+#define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
+#define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
+#define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
+#define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
+#define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
+#define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
+
+/* RFSYS - Register array accessors */
+#define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ROM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+ __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
+ __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
+ uint8_t RESERVED_0[4028];
+ __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type, *ROM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ROM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
+ * @{
+ */
+
+
+/* ROM - Register accessors */
+#define ROM_ENTRY_REG(base,index) ((base)->ENTRY[index])
+#define ROM_TABLEMARK_REG(base) ((base)->TABLEMARK)
+#define ROM_SYSACCESS_REG(base) ((base)->SYSACCESS)
+#define ROM_PERIPHID4_REG(base) ((base)->PERIPHID4)
+#define ROM_PERIPHID5_REG(base) ((base)->PERIPHID5)
+#define ROM_PERIPHID6_REG(base) ((base)->PERIPHID6)
+#define ROM_PERIPHID7_REG(base) ((base)->PERIPHID7)
+#define ROM_PERIPHID0_REG(base) ((base)->PERIPHID0)
+#define ROM_PERIPHID1_REG(base) ((base)->PERIPHID1)
+#define ROM_PERIPHID2_REG(base) ((base)->PERIPHID2)
+#define ROM_PERIPHID3_REG(base) ((base)->PERIPHID3)
+#define ROM_COMPID_REG(base,index) ((base)->COMPID[index])
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ROM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/* ENTRY Bit Fields */
+#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
+#define ROM_ENTRY_ENTRY_SHIFT 0
+#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
+/* TABLEMARK Bit Fields */
+#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
+#define ROM_TABLEMARK_MARK_SHIFT 0
+#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
+/* SYSACCESS Bit Fields */
+#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
+#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
+#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
+/* PERIPHID4 Bit Fields */
+#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID4_PERIPHID_SHIFT 0
+#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
+/* PERIPHID5 Bit Fields */
+#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID5_PERIPHID_SHIFT 0
+#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
+/* PERIPHID6 Bit Fields */
+#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID6_PERIPHID_SHIFT 0
+#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
+/* PERIPHID7 Bit Fields */
+#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID7_PERIPHID_SHIFT 0
+#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
+/* PERIPHID0 Bit Fields */
+#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID0_PERIPHID_SHIFT 0
+#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
+/* PERIPHID1 Bit Fields */
+#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID1_PERIPHID_SHIFT 0
+#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
+/* PERIPHID2 Bit Fields */
+#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID2_PERIPHID_SHIFT 0
+#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
+/* PERIPHID3 Bit Fields */
+#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID3_PERIPHID_SHIFT 0
+#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define ROM_COMPID_COMPID_SHIFT 0
+#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM ((ROM_Type *)ROM_BASE)
+#define ROM_BASE_PTR (ROM)
+/** Array initializer of ROM peripheral base addresses */
+#define ROM_BASE_ADDRS { ROM_BASE }
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASE_PTRS { ROM }
+
+/* ----------------------------------------------------------------------------
+ -- ROM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
+ * @{
+ */
+
+
+/* ROM - Register instance definitions */
+/* ROM */
+#define ROM_ENTRY0 ROM_ENTRY_REG(ROM,0)
+#define ROM_ENTRY1 ROM_ENTRY_REG(ROM,1)
+#define ROM_ENTRY2 ROM_ENTRY_REG(ROM,2)
+#define ROM_TABLEMARK ROM_TABLEMARK_REG(ROM)
+#define ROM_SYSACCESS ROM_SYSACCESS_REG(ROM)
+#define ROM_PERIPHID4 ROM_PERIPHID4_REG(ROM)
+#define ROM_PERIPHID5 ROM_PERIPHID5_REG(ROM)
+#define ROM_PERIPHID6 ROM_PERIPHID6_REG(ROM)
+#define ROM_PERIPHID7 ROM_PERIPHID7_REG(ROM)
+#define ROM_PERIPHID0 ROM_PERIPHID0_REG(ROM)
+#define ROM_PERIPHID1 ROM_PERIPHID1_REG(ROM)
+#define ROM_PERIPHID2 ROM_PERIPHID2_REG(ROM)
+#define ROM_PERIPHID3 ROM_PERIPHID3_REG(ROM)
+#define ROM_COMPID0 ROM_COMPID_REG(ROM,0)
+#define ROM_COMPID1 ROM_COMPID_REG(ROM,1)
+#define ROM_COMPID2 ROM_COMPID_REG(ROM,2)
+#define ROM_COMPID3 ROM_COMPID_REG(ROM,3)
+
+/* ROM - Register array accessors */
+#define ROM_ENTRY(index) ROM_ENTRY_REG(ROM,index)
+#define ROM_COMPID(index) ROM_COMPID_REG(ROM,index)
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+} RTC_Type, *RTC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- RTC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register accessors */
+#define RTC_TSR_REG(base) ((base)->TSR)
+#define RTC_TPR_REG(base) ((base)->TPR)
+#define RTC_TAR_REG(base) ((base)->TAR)
+#define RTC_TCR_REG(base) ((base)->TCR)
+#define RTC_CR_REG(base) ((base)->CR)
+#define RTC_SR_REG(base) ((base)->SR)
+#define RTC_LR_REG(base) ((base)->LR)
+#define RTC_IER_REG(base) ((base)->IER)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_WPS_MASK 0x10u
+#define RTC_CR_WPS_SHIFT 4
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+#define RTC_IER_WPON_MASK 0x80u
+#define RTC_IER_WPON_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+#define RTC_BASE_PTR (RTC)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS { RTC_IRQn }
+#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- RTC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
+ * @{
+ */
+
+
+/* RTC - Register instance definitions */
+/* RTC */
+#define RTC_TSR RTC_TSR_REG(RTC)
+#define RTC_TPR RTC_TPR_REG(RTC)
+#define RTC_TAR RTC_TAR_REG(RTC)
+#define RTC_TCR RTC_TCR_REG(RTC)
+#define RTC_CR RTC_CR_REG(RTC)
+#define RTC_SR RTC_SR_REG(RTC)
+#define RTC_LR RTC_LR_REG(RTC)
+#define RTC_IER RTC_IER_REG(RTC)
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ uint8_t RESERVED_6[4];
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+ uint8_t RESERVED_7[156];
+ __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
+ __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */
+} SIM_Type, *SIM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SIM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register accessors */
+#define SIM_SOPT1_REG(base) ((base)->SOPT1)
+#define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
+#define SIM_SOPT2_REG(base) ((base)->SOPT2)
+#define SIM_SOPT4_REG(base) ((base)->SOPT4)
+#define SIM_SOPT5_REG(base) ((base)->SOPT5)
+#define SIM_SOPT7_REG(base) ((base)->SOPT7)
+#define SIM_SDID_REG(base) ((base)->SDID)
+#define SIM_SCGC4_REG(base) ((base)->SCGC4)
+#define SIM_SCGC5_REG(base) ((base)->SCGC5)
+#define SIM_SCGC6_REG(base) ((base)->SCGC6)
+#define SIM_SCGC7_REG(base) ((base)->SCGC7)
+#define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
+#define SIM_FCFG1_REG(base) ((base)->FCFG1)
+#define SIM_FCFG2_REG(base) ((base)->FCFG2)
+#define SIM_UIDMH_REG(base) ((base)->UIDMH)
+#define SIM_UIDML_REG(base) ((base)->UIDML)
+#define SIM_UIDL_REG(base) ((base)->UIDL)
+#define SIM_COPC_REG(base) ((base)->COPC)
+#define SIM_SRVCOP_REG(base) ((base)->SRVCOP)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_OSC32KOUT_MASK 0x30000u
+#define SIM_SOPT1_OSC32KOUT_SHIFT 16
+#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+#define SIM_SOPT2_FLEXIOSRC_MASK 0xC00000u
+#define SIM_SOPT2_FLEXIOSRC_SHIFT 22
+#define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FLEXIOSRC_SHIFT))&SIM_SOPT2_FLEXIOSRC_MASK)
+#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
+#define SIM_SOPT2_TPMSRC_SHIFT 24
+#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_LPUART0SRC_MASK 0xC000000u
+#define SIM_SOPT2_LPUART0SRC_SHIFT 26
+#define SIM_SOPT2_LPUART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART0SRC_SHIFT))&SIM_SOPT2_LPUART0SRC_MASK)
+#define SIM_SOPT2_LPUART1SRC_MASK 0x30000000u
+#define SIM_SOPT2_LPUART1SRC_SHIFT 28
+#define SIM_SOPT2_LPUART1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART1SRC_SHIFT))&SIM_SOPT2_LPUART1SRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
+#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
+#define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
+#define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
+#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
+#define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_LPUART0TXSRC_MASK 0x3u
+#define SIM_SOPT5_LPUART0TXSRC_SHIFT 0
+#define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0TXSRC_SHIFT))&SIM_SOPT5_LPUART0TXSRC_MASK)
+#define SIM_SOPT5_LPUART0RXSRC_MASK 0x4u
+#define SIM_SOPT5_LPUART0RXSRC_SHIFT 2
+#define SIM_SOPT5_LPUART1TXSRC_MASK 0x30u
+#define SIM_SOPT5_LPUART1TXSRC_SHIFT 4
+#define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART1TXSRC_SHIFT))&SIM_SOPT5_LPUART1TXSRC_MASK)
+#define SIM_SOPT5_LPUART1RXSRC_MASK 0x40u
+#define SIM_SOPT5_LPUART1RXSRC_SHIFT 6
+#define SIM_SOPT5_LPUART0ODE_MASK 0x10000u
+#define SIM_SOPT5_LPUART0ODE_SHIFT 16
+#define SIM_SOPT5_LPUART1ODE_MASK 0x20000u
+#define SIM_SOPT5_LPUART1ODE_SHIFT 17
+#define SIM_SOPT5_UART2ODE_MASK 0x40000u
+#define SIM_SOPT5_UART2ODE_SHIFT 18
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
+#define SIM_SDID_SRAMSIZE_SHIFT 16
+#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
+#define SIM_SDID_SERIESID_MASK 0xF00000u
+#define SIM_SDID_SERIESID_SHIFT 20
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK 0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT 24
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK 0xF0000000u
+#define SIM_SDID_FAMID_SHIFT 28
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_I2C1_MASK 0x80u
+#define SIM_SCGC4_I2C1_SHIFT 7
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_USBFS_MASK 0x40000u
+#define SIM_SCGC4_USBFS_SHIFT 18
+#define SIM_SCGC4_CMP0_MASK 0x80000u
+#define SIM_SCGC4_CMP0_SHIFT 19
+#define SIM_SCGC4_VREF_MASK 0x100000u
+#define SIM_SCGC4_VREF_SHIFT 20
+#define SIM_SCGC4_SPI0_MASK 0x400000u
+#define SIM_SCGC4_SPI0_SHIFT 22
+#define SIM_SCGC4_SPI1_MASK 0x800000u
+#define SIM_SCGC4_SPI1_SHIFT 23
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK 0x1u
+#define SIM_SCGC5_LPTMR_SHIFT 0
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+#define SIM_SCGC5_SLCD_MASK 0x80000u
+#define SIM_SCGC5_SLCD_SHIFT 19
+#define SIM_SCGC5_LPUART0_MASK 0x100000u
+#define SIM_SCGC5_LPUART0_SHIFT 20
+#define SIM_SCGC5_LPUART1_MASK 0x200000u
+#define SIM_SCGC5_LPUART1_SHIFT 21
+#define SIM_SCGC5_FLEXIO_MASK 0x80000000u
+#define SIM_SCGC5_FLEXIO_SHIFT 31
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK 0x1u
+#define SIM_SCGC6_FTF_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_I2S_MASK 0x8000u
+#define SIM_SCGC6_I2S_SHIFT 15
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_TPM0_MASK 0x1000000u
+#define SIM_SCGC6_TPM0_SHIFT 24
+#define SIM_SCGC6_TPM1_MASK 0x2000000u
+#define SIM_SCGC6_TPM1_SHIFT 25
+#define SIM_SCGC6_TPM2_MASK 0x4000000u
+#define SIM_SCGC6_TPM2_SHIFT 26
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+#define SIM_SCGC6_DAC0_MASK 0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT 31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK 0x100u
+#define SIM_SCGC7_DMA_SHIFT 8
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT 16
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT 24
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/* COPC Bit Fields */
+#define SIM_COPC_COPW_MASK 0x1u
+#define SIM_COPC_COPW_SHIFT 0
+#define SIM_COPC_COPCLKS_MASK 0x2u
+#define SIM_COPC_COPCLKS_SHIFT 1
+#define SIM_COPC_COPT_MASK 0xCu
+#define SIM_COPC_COPT_SHIFT 2
+#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
+#define SIM_COPC_COPSTPEN_MASK 0x10u
+#define SIM_COPC_COPSTPEN_SHIFT 4
+#define SIM_COPC_COPDBGEN_MASK 0x20u
+#define SIM_COPC_COPDBGEN_SHIFT 5
+#define SIM_COPC_COPCLKSEL_MASK 0xC0u
+#define SIM_COPC_COPCLKSEL_SHIFT 6
+#define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPCLKSEL_SHIFT))&SIM_COPC_COPCLKSEL_MASK)
+/* SRVCOP Bit Fields */
+#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
+#define SIM_SRVCOP_SRVCOP_SHIFT 0
+#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+#define SIM_BASE_PTR (SIM)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS { SIM }
+
+/* ----------------------------------------------------------------------------
+ -- SIM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
+ * @{
+ */
+
+
+/* SIM - Register instance definitions */
+/* SIM */
+#define SIM_SOPT1 SIM_SOPT1_REG(SIM)
+#define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
+#define SIM_SOPT2 SIM_SOPT2_REG(SIM)
+#define SIM_SOPT4 SIM_SOPT4_REG(SIM)
+#define SIM_SOPT5 SIM_SOPT5_REG(SIM)
+#define SIM_SOPT7 SIM_SOPT7_REG(SIM)
+#define SIM_SDID SIM_SDID_REG(SIM)
+#define SIM_SCGC4 SIM_SCGC4_REG(SIM)
+#define SIM_SCGC5 SIM_SCGC5_REG(SIM)
+#define SIM_SCGC6 SIM_SCGC6_REG(SIM)
+#define SIM_SCGC7 SIM_SCGC7_REG(SIM)
+#define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
+#define SIM_FCFG1 SIM_FCFG1_REG(SIM)
+#define SIM_FCFG2 SIM_FCFG2_REG(SIM)
+#define SIM_UIDMH SIM_UIDMH_REG(SIM)
+#define SIM_UIDML SIM_UIDML_REG(SIM)
+#define SIM_UIDL SIM_UIDL_REG(SIM)
+#define SIM_COPC SIM_COPC_REG(SIM)
+#define SIM_SRVCOP SIM_SRVCOP_REG(SIM)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type, *SMC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register accessors */
+#define SMC_PMPROT_REG(base) ((base)->PMPROT)
+#define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
+#define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
+#define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+/* STOPCTRL Bit Fields */
+#define SMC_STOPCTRL_VLLSM_MASK 0x7u
+#define SMC_STOPCTRL_VLLSM_SHIFT 0
+#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK 0x20u
+#define SMC_STOPCTRL_PORPO_SHIFT 5
+#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
+#define SMC_STOPCTRL_PSTOPO_SHIFT 6
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0xFFu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+#define SMC_BASE_PTR (SMC)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS { SMC }
+
+/* ----------------------------------------------------------------------------
+ -- SMC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
+ * @{
+ */
+
+
+/* SMC - Register instance definitions */
+/* SMC */
+#define SMC_PMPROT SMC_PMPROT_REG(SMC)
+#define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
+#define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
+#define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __I uint8_t S; /**< SPI Status Register, offset: 0x0 */
+ __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */
+ __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */
+ __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */
+ __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */
+ __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
+ __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */
+ __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
+ __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
+} SPI_Type, *SPI_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- SPI - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register accessors */
+#define SPI_S_REG(base) ((base)->S)
+#define SPI_BR_REG(base) ((base)->BR)
+#define SPI_C2_REG(base) ((base)->C2)
+#define SPI_C1_REG(base) ((base)->C1)
+#define SPI_ML_REG(base) ((base)->ML)
+#define SPI_MH_REG(base) ((base)->MH)
+#define SPI_DL_REG(base) ((base)->DL)
+#define SPI_DH_REG(base) ((base)->DH)
+#define SPI_CI_REG(base) ((base)->CI)
+#define SPI_C3_REG(base) ((base)->C3)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* S Bit Fields */
+#define SPI_S_RFIFOEF_MASK 0x1u
+#define SPI_S_RFIFOEF_SHIFT 0
+#define SPI_S_TXFULLF_MASK 0x2u
+#define SPI_S_TXFULLF_SHIFT 1
+#define SPI_S_TNEAREF_MASK 0x4u
+#define SPI_S_TNEAREF_SHIFT 2
+#define SPI_S_RNFULLF_MASK 0x8u
+#define SPI_S_RNFULLF_SHIFT 3
+#define SPI_S_MODF_MASK 0x10u
+#define SPI_S_MODF_SHIFT 4
+#define SPI_S_SPTEF_MASK 0x20u
+#define SPI_S_SPTEF_SHIFT 5
+#define SPI_S_SPMF_MASK 0x40u
+#define SPI_S_SPMF_SHIFT 6
+#define SPI_S_SPRF_MASK 0x80u
+#define SPI_S_SPRF_SHIFT 7
+/* BR Bit Fields */
+#define SPI_BR_SPR_MASK 0xFu
+#define SPI_BR_SPR_SHIFT 0
+#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK 0x70u
+#define SPI_BR_SPPR_SHIFT 4
+#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
+/* C2 Bit Fields */
+#define SPI_C2_SPC0_MASK 0x1u
+#define SPI_C2_SPC0_SHIFT 0
+#define SPI_C2_SPISWAI_MASK 0x2u
+#define SPI_C2_SPISWAI_SHIFT 1
+#define SPI_C2_RXDMAE_MASK 0x4u
+#define SPI_C2_RXDMAE_SHIFT 2
+#define SPI_C2_BIDIROE_MASK 0x8u
+#define SPI_C2_BIDIROE_SHIFT 3
+#define SPI_C2_MODFEN_MASK 0x10u
+#define SPI_C2_MODFEN_SHIFT 4
+#define SPI_C2_TXDMAE_MASK 0x20u
+#define SPI_C2_TXDMAE_SHIFT 5
+#define SPI_C2_SPIMODE_MASK 0x40u
+#define SPI_C2_SPIMODE_SHIFT 6
+#define SPI_C2_SPMIE_MASK 0x80u
+#define SPI_C2_SPMIE_SHIFT 7
+/* C1 Bit Fields */
+#define SPI_C1_LSBFE_MASK 0x1u
+#define SPI_C1_LSBFE_SHIFT 0
+#define SPI_C1_SSOE_MASK 0x2u
+#define SPI_C1_SSOE_SHIFT 1
+#define SPI_C1_CPHA_MASK 0x4u
+#define SPI_C1_CPHA_SHIFT 2
+#define SPI_C1_CPOL_MASK 0x8u
+#define SPI_C1_CPOL_SHIFT 3
+#define SPI_C1_MSTR_MASK 0x10u
+#define SPI_C1_MSTR_SHIFT 4
+#define SPI_C1_SPTIE_MASK 0x20u
+#define SPI_C1_SPTIE_SHIFT 5
+#define SPI_C1_SPE_MASK 0x40u
+#define SPI_C1_SPE_SHIFT 6
+#define SPI_C1_SPIE_MASK 0x80u
+#define SPI_C1_SPIE_SHIFT 7
+/* ML Bit Fields */
+#define SPI_ML_Bits_MASK 0xFFu
+#define SPI_ML_Bits_SHIFT 0
+#define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
+/* MH Bit Fields */
+#define SPI_MH_Bits_MASK 0xFFu
+#define SPI_MH_Bits_SHIFT 0
+#define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
+/* DL Bit Fields */
+#define SPI_DL_Bits_MASK 0xFFu
+#define SPI_DL_Bits_SHIFT 0
+#define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
+/* DH Bit Fields */
+#define SPI_DH_Bits_MASK 0xFFu
+#define SPI_DH_Bits_SHIFT 0
+#define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
+/* CI Bit Fields */
+#define SPI_CI_SPRFCI_MASK 0x1u
+#define SPI_CI_SPRFCI_SHIFT 0
+#define SPI_CI_SPTEFCI_MASK 0x2u
+#define SPI_CI_SPTEFCI_SHIFT 1
+#define SPI_CI_RNFULLFCI_MASK 0x4u
+#define SPI_CI_RNFULLFCI_SHIFT 2
+#define SPI_CI_TNEAREFCI_MASK 0x8u
+#define SPI_CI_TNEAREFCI_SHIFT 3
+#define SPI_CI_RXFOF_MASK 0x10u
+#define SPI_CI_RXFOF_SHIFT 4
+#define SPI_CI_TXFOF_MASK 0x20u
+#define SPI_CI_TXFOF_SHIFT 5
+#define SPI_CI_RXFERR_MASK 0x40u
+#define SPI_CI_RXFERR_SHIFT 6
+#define SPI_CI_TXFERR_MASK 0x80u
+#define SPI_CI_TXFERR_SHIFT 7
+/* C3 Bit Fields */
+#define SPI_C3_FIFOMODE_MASK 0x1u
+#define SPI_C3_FIFOMODE_SHIFT 0
+#define SPI_C3_RNFULLIEN_MASK 0x2u
+#define SPI_C3_RNFULLIEN_SHIFT 1
+#define SPI_C3_TNEARIEN_MASK 0x4u
+#define SPI_C3_TNEARIEN_SHIFT 2
+#define SPI_C3_INTCLR_MASK 0x8u
+#define SPI_C3_INTCLR_SHIFT 3
+#define SPI_C3_RNFULLF_MARK_MASK 0x10u
+#define SPI_C3_RNFULLF_MARK_SHIFT 4
+#define SPI_C3_TNEAREF_MARK_MASK 0x20u
+#define SPI_C3_TNEAREF_MARK_SHIFT 5
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+#define SPI0_BASE_PTR (SPI0)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x40077000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+#define SPI1_BASE_PTR (SPI1)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS { SPI0, SPI1 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- SPI - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
+ * @{
+ */
+
+
+/* SPI - Register instance definitions */
+/* SPI0 */
+#define SPI0_S SPI_S_REG(SPI0)
+#define SPI0_BR SPI_BR_REG(SPI0)
+#define SPI0_C2 SPI_C2_REG(SPI0)
+#define SPI0_C1 SPI_C1_REG(SPI0)
+#define SPI0_ML SPI_ML_REG(SPI0)
+#define SPI0_MH SPI_MH_REG(SPI0)
+#define SPI0_DL SPI_DL_REG(SPI0)
+#define SPI0_DH SPI_DH_REG(SPI0)
+/* SPI1 */
+#define SPI1_S SPI_S_REG(SPI1)
+#define SPI1_BR SPI_BR_REG(SPI1)
+#define SPI1_C2 SPI_C2_REG(SPI1)
+#define SPI1_C1 SPI_C1_REG(SPI1)
+#define SPI1_ML SPI_ML_REG(SPI1)
+#define SPI1_MH SPI_MH_REG(SPI1)
+#define SPI1_DL SPI_DL_REG(SPI1)
+#define SPI1_DH SPI_DH_REG(SPI1)
+#define SPI1_CI SPI_CI_REG(SPI1)
+#define SPI1_C3 SPI_C3_REG(SPI1)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[6];
+ uint8_t RESERVED_0[20];
+ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
+ uint8_t RESERVED_2[16];
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+} TPM_Type, *TPM_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- TPM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
+ * @{
+ */
+
+
+/* TPM - Register accessors */
+#define TPM_SC_REG(base) ((base)->SC)
+#define TPM_CNT_REG(base) ((base)->CNT)
+#define TPM_MOD_REG(base) ((base)->MOD)
+#define TPM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
+#define TPM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
+#define TPM_STATUS_REG(base) ((base)->STATUS)
+#define TPM_POL_REG(base) ((base)->POL)
+#define TPM_CONF_REG(base) ((base)->CONF)
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define TPM_SC_PS_MASK 0x7u
+#define TPM_SC_PS_SHIFT 0
+#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK 0x18u
+#define TPM_SC_CMOD_SHIFT 3
+#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK 0x20u
+#define TPM_SC_CPWMS_SHIFT 5
+#define TPM_SC_TOIE_MASK 0x40u
+#define TPM_SC_TOIE_SHIFT 6
+#define TPM_SC_TOF_MASK 0x80u
+#define TPM_SC_TOF_SHIFT 7
+#define TPM_SC_DMA_MASK 0x100u
+#define TPM_SC_DMA_SHIFT 8
+/* CNT Bit Fields */
+#define TPM_CNT_COUNT_MASK 0xFFFFu
+#define TPM_CNT_COUNT_SHIFT 0
+#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define TPM_MOD_MOD_MASK 0xFFFFu
+#define TPM_MOD_MOD_SHIFT 0
+#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define TPM_CnSC_DMA_MASK 0x1u
+#define TPM_CnSC_DMA_SHIFT 0
+#define TPM_CnSC_ELSA_MASK 0x4u
+#define TPM_CnSC_ELSA_SHIFT 2
+#define TPM_CnSC_ELSB_MASK 0x8u
+#define TPM_CnSC_ELSB_SHIFT 3
+#define TPM_CnSC_MSA_MASK 0x10u
+#define TPM_CnSC_MSA_SHIFT 4
+#define TPM_CnSC_MSB_MASK 0x20u
+#define TPM_CnSC_MSB_SHIFT 5
+#define TPM_CnSC_CHIE_MASK 0x40u
+#define TPM_CnSC_CHIE_SHIFT 6
+#define TPM_CnSC_CHF_MASK 0x80u
+#define TPM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define TPM_CnV_VAL_MASK 0xFFFFu
+#define TPM_CnV_VAL_SHIFT 0
+#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
+/* STATUS Bit Fields */
+#define TPM_STATUS_CH0F_MASK 0x1u
+#define TPM_STATUS_CH0F_SHIFT 0
+#define TPM_STATUS_CH1F_MASK 0x2u
+#define TPM_STATUS_CH1F_SHIFT 1
+#define TPM_STATUS_CH2F_MASK 0x4u
+#define TPM_STATUS_CH2F_SHIFT 2
+#define TPM_STATUS_CH3F_MASK 0x8u
+#define TPM_STATUS_CH3F_SHIFT 3
+#define TPM_STATUS_CH4F_MASK 0x10u
+#define TPM_STATUS_CH4F_SHIFT 4
+#define TPM_STATUS_CH5F_MASK 0x20u
+#define TPM_STATUS_CH5F_SHIFT 5
+#define TPM_STATUS_TOF_MASK 0x100u
+#define TPM_STATUS_TOF_SHIFT 8
+/* POL Bit Fields */
+#define TPM_POL_POL0_MASK 0x1u
+#define TPM_POL_POL0_SHIFT 0
+#define TPM_POL_POL1_MASK 0x2u
+#define TPM_POL_POL1_SHIFT 1
+#define TPM_POL_POL2_MASK 0x4u
+#define TPM_POL_POL2_SHIFT 2
+#define TPM_POL_POL3_MASK 0x8u
+#define TPM_POL_POL3_SHIFT 3
+#define TPM_POL_POL4_MASK 0x10u
+#define TPM_POL_POL4_SHIFT 4
+#define TPM_POL_POL5_MASK 0x20u
+#define TPM_POL_POL5_SHIFT 5
+/* CONF Bit Fields */
+#define TPM_CONF_DOZEEN_MASK 0x20u
+#define TPM_CONF_DOZEEN_SHIFT 5
+#define TPM_CONF_DBGMODE_MASK 0xC0u
+#define TPM_CONF_DBGMODE_SHIFT 6
+#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBSYNC_MASK 0x100u
+#define TPM_CONF_GTBSYNC_SHIFT 8
+#define TPM_CONF_GTBEEN_MASK 0x200u
+#define TPM_CONF_GTBEEN_SHIFT 9
+#define TPM_CONF_CSOT_MASK 0x10000u
+#define TPM_CONF_CSOT_SHIFT 16
+#define TPM_CONF_CSOO_MASK 0x20000u
+#define TPM_CONF_CSOO_SHIFT 17
+#define TPM_CONF_CROT_MASK 0x40000u
+#define TPM_CONF_CROT_SHIFT 18
+#define TPM_CONF_CPOT_MASK 0x80000u
+#define TPM_CONF_CPOT_SHIFT 19
+#define TPM_CONF_TRGPOL_MASK 0x400000u
+#define TPM_CONF_TRGPOL_SHIFT 22
+#define TPM_CONF_TRGSRC_MASK 0x800000u
+#define TPM_CONF_TRGSRC_SHIFT 23
+#define TPM_CONF_TRGSEL_MASK 0xF000000u
+#define TPM_CONF_TRGSEL_SHIFT 24
+#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0 ((TPM_Type *)TPM0_BASE)
+#define TPM0_BASE_PTR (TPM0)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1 ((TPM_Type *)TPM1_BASE)
+#define TPM1_BASE_PTR (TPM1)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE (0x4003A000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2 ((TPM_Type *)TPM2_BASE)
+#define TPM2_BASE_PTR (TPM2)
+/** Array initializer of TPM peripheral base addresses */
+#define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
+/** Interrupt vectors for the TPM peripheral type */
+#define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- TPM - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
+ * @{
+ */
+
+
+/* TPM - Register instance definitions */
+/* TPM0 */
+#define TPM0_SC TPM_SC_REG(TPM0)
+#define TPM0_CNT TPM_CNT_REG(TPM0)
+#define TPM0_MOD TPM_MOD_REG(TPM0)
+#define TPM0_C0SC TPM_CnSC_REG(TPM0,0)
+#define TPM0_C0V TPM_CnV_REG(TPM0,0)
+#define TPM0_C1SC TPM_CnSC_REG(TPM0,1)
+#define TPM0_C1V TPM_CnV_REG(TPM0,1)
+#define TPM0_C2SC TPM_CnSC_REG(TPM0,2)
+#define TPM0_C2V TPM_CnV_REG(TPM0,2)
+#define TPM0_C3SC TPM_CnSC_REG(TPM0,3)
+#define TPM0_C3V TPM_CnV_REG(TPM0,3)
+#define TPM0_C4SC TPM_CnSC_REG(TPM0,4)
+#define TPM0_C4V TPM_CnV_REG(TPM0,4)
+#define TPM0_C5SC TPM_CnSC_REG(TPM0,5)
+#define TPM0_C5V TPM_CnV_REG(TPM0,5)
+#define TPM0_STATUS TPM_STATUS_REG(TPM0)
+#define TPM0_POL TPM_POL_REG(TPM0)
+#define TPM0_CONF TPM_CONF_REG(TPM0)
+/* TPM1 */
+#define TPM1_SC TPM_SC_REG(TPM1)
+#define TPM1_CNT TPM_CNT_REG(TPM1)
+#define TPM1_MOD TPM_MOD_REG(TPM1)
+#define TPM1_C0SC TPM_CnSC_REG(TPM1,0)
+#define TPM1_C0V TPM_CnV_REG(TPM1,0)
+#define TPM1_C1SC TPM_CnSC_REG(TPM1,1)
+#define TPM1_C1V TPM_CnV_REG(TPM1,1)
+#define TPM1_STATUS TPM_STATUS_REG(TPM1)
+#define TPM1_POL TPM_POL_REG(TPM1)
+#define TPM1_CONF TPM_CONF_REG(TPM1)
+/* TPM2 */
+#define TPM2_SC TPM_SC_REG(TPM2)
+#define TPM2_CNT TPM_CNT_REG(TPM2)
+#define TPM2_MOD TPM_MOD_REG(TPM2)
+#define TPM2_C0SC TPM_CnSC_REG(TPM2,0)
+#define TPM2_C0V TPM_CnV_REG(TPM2,0)
+#define TPM2_C1SC TPM_CnSC_REG(TPM2,1)
+#define TPM2_C1V TPM_CnV_REG(TPM2,1)
+#define TPM2_STATUS TPM_STATUS_REG(TPM2)
+#define TPM2_POL TPM_POL_REG(TPM2)
+#define TPM2_CONF TPM_CONF_REG(TPM2)
+
+/* TPM - Register array accessors */
+#define TPM0_CnSC(index) TPM_CnSC_REG(TPM0,index)
+#define TPM1_CnSC(index) TPM_CnSC_REG(TPM1,index)
+#define TPM2_CnSC(index) TPM_CnSC_REG(TPM2,index)
+#define TPM0_CnV(index) TPM_CnV_REG(TPM0,index)
+#define TPM1_CnV(index) TPM_CnV_REG(TPM1,index)
+#define TPM2_CnV(index) TPM_CnV_REG(TPM2,index)
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+ uint8_t RESERVED_0[12];
+ __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
+ __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+ __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+ __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+ __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
+ __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
+ __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
+ __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
+ uint8_t RESERVED_1[26];
+ __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
+ __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
+ union { /* offset: 0x3C */
+ struct { /* offset: 0x3C */
+ __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+ __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+ } TYPE0;
+ struct { /* offset: 0x3C */
+ __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+ __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+ } TYPE1;
+ };
+ __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
+ __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
+} UART_Type, *UART_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- UART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register accessors */
+#define UART_BDH_REG(base) ((base)->BDH)
+#define UART_BDL_REG(base) ((base)->BDL)
+#define UART_C1_REG(base) ((base)->C1)
+#define UART_C2_REG(base) ((base)->C2)
+#define UART_S1_REG(base) ((base)->S1)
+#define UART_S2_REG(base) ((base)->S2)
+#define UART_C3_REG(base) ((base)->C3)
+#define UART_D_REG(base) ((base)->D)
+#define UART_MA1_REG(base) ((base)->MA1)
+#define UART_MA2_REG(base) ((base)->MA2)
+#define UART_C4_REG(base) ((base)->C4)
+#define UART_C5_REG(base) ((base)->C5)
+#define UART_C7816_REG(base) ((base)->C7816)
+#define UART_IE7816_REG(base) ((base)->IE7816)
+#define UART_IS7816_REG(base) ((base)->IS7816)
+#define UART_WP7816_REG(base) ((base)->WP7816)
+#define UART_WN7816_REG(base) ((base)->WN7816)
+#define UART_WF7816_REG(base) ((base)->WF7816)
+#define UART_ET7816_REG(base) ((base)->ET7816)
+#define UART_TL7816_REG(base) ((base)->TL7816)
+#define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
+#define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
+#define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
+#define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
+#define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
+#define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
+#define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
+#define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_MSBF_MASK 0x20u
+#define UART_S2_MSBF_SHIFT 5
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_RT_MASK 0xFFu
+#define UART_D_RT_SHIFT 0
+#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK 0xFFu
+#define UART_MA1_MA_SHIFT 0
+#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK 0xFFu
+#define UART_MA2_MA_SHIFT 0
+#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK 0x1Fu
+#define UART_C4_BRFA_SHIFT 0
+#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK 0x20u
+#define UART_C4_M10_SHIFT 5
+#define UART_C4_MAEN2_MASK 0x40u
+#define UART_C4_MAEN2_SHIFT 6
+#define UART_C4_MAEN1_MASK 0x80u
+#define UART_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UART_C5_RDMAS_MASK 0x20u
+#define UART_C5_RDMAS_SHIFT 5
+#define UART_C5_TDMAS_MASK 0x80u
+#define UART_C5_TDMAS_SHIFT 7
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK 0x1u
+#define UART_C7816_ISO_7816E_SHIFT 0
+#define UART_C7816_TTYPE_MASK 0x2u
+#define UART_C7816_TTYPE_SHIFT 1
+#define UART_C7816_INIT_MASK 0x4u
+#define UART_C7816_INIT_SHIFT 2
+#define UART_C7816_ANACK_MASK 0x8u
+#define UART_C7816_ANACK_SHIFT 3
+#define UART_C7816_ONACK_MASK 0x10u
+#define UART_C7816_ONACK_SHIFT 4
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK 0x1u
+#define UART_IE7816_RXTE_SHIFT 0
+#define UART_IE7816_TXTE_MASK 0x2u
+#define UART_IE7816_TXTE_SHIFT 1
+#define UART_IE7816_GTVE_MASK 0x4u
+#define UART_IE7816_GTVE_SHIFT 2
+#define UART_IE7816_ADTE_MASK 0x8u
+#define UART_IE7816_ADTE_SHIFT 3
+#define UART_IE7816_INITDE_MASK 0x10u
+#define UART_IE7816_INITDE_SHIFT 4
+#define UART_IE7816_BWTE_MASK 0x20u
+#define UART_IE7816_BWTE_SHIFT 5
+#define UART_IE7816_CWTE_MASK 0x40u
+#define UART_IE7816_CWTE_SHIFT 6
+#define UART_IE7816_WTE_MASK 0x80u
+#define UART_IE7816_WTE_SHIFT 7
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK 0x1u
+#define UART_IS7816_RXT_SHIFT 0
+#define UART_IS7816_TXT_MASK 0x2u
+#define UART_IS7816_TXT_SHIFT 1
+#define UART_IS7816_GTV_MASK 0x4u
+#define UART_IS7816_GTV_SHIFT 2
+#define UART_IS7816_ADT_MASK 0x8u
+#define UART_IS7816_ADT_SHIFT 3
+#define UART_IS7816_INITD_MASK 0x10u
+#define UART_IS7816_INITD_SHIFT 4
+#define UART_IS7816_BWT_MASK 0x20u
+#define UART_IS7816_BWT_SHIFT 5
+#define UART_IS7816_CWT_MASK 0x40u
+#define UART_IS7816_CWT_SHIFT 6
+#define UART_IS7816_WT_MASK 0x80u
+#define UART_IS7816_WT_SHIFT 7
+/* WP7816 Bit Fields */
+#define UART_WP7816_WTX_MASK 0xFFu
+#define UART_WP7816_WTX_SHIFT 0
+#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK 0xFFu
+#define UART_WN7816_GTN_SHIFT 0
+#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK 0xFFu
+#define UART_WF7816_GTFD_SHIFT 0
+#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK 0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT 0
+#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT 4
+#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK 0xFFu
+#define UART_TL7816_TLEN_SHIFT 0
+#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+/* AP7816A_T0 Bit Fields */
+#define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
+#define UART_AP7816A_T0_ADTI_H_SHIFT 0
+#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
+/* AP7816B_T0 Bit Fields */
+#define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
+#define UART_AP7816B_T0_ADTI_L_SHIFT 0
+#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
+/* WP7816A_T0 Bit Fields */
+#define UART_WP7816A_T0_WI_H_MASK 0xFFu
+#define UART_WP7816A_T0_WI_H_SHIFT 0
+#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
+/* WP7816B_T0 Bit Fields */
+#define UART_WP7816B_T0_WI_L_MASK 0xFFu
+#define UART_WP7816B_T0_WI_L_SHIFT 0
+#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
+/* WP7816A_T1 Bit Fields */
+#define UART_WP7816A_T1_BWI_H_MASK 0xFFu
+#define UART_WP7816A_T1_BWI_H_SHIFT 0
+#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
+/* WP7816B_T1 Bit Fields */
+#define UART_WP7816B_T1_BWI_L_MASK 0xFFu
+#define UART_WP7816B_T1_BWI_L_SHIFT 0
+#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
+/* WGP7816_T1 Bit Fields */
+#define UART_WGP7816_T1_BGI_MASK 0xFu
+#define UART_WGP7816_T1_BGI_SHIFT 0
+#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
+#define UART_WGP7816_T1_CWI1_MASK 0xF0u
+#define UART_WGP7816_T1_CWI1_SHIFT 4
+#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
+/* WP7816C_T1 Bit Fields */
+#define UART_WP7816C_T1_CWI2_MASK 0x1Fu
+#define UART_WP7816C_T1_CWI2_SHIFT 0
+#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+#define UART2_BASE_PTR (UART2)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS { UART2_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS { UART2 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS { UART2_FLEXIO_IRQn }
+#define UART_ERR_IRQS { UART2_FLEXIO_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- UART - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
+ * @{
+ */
+
+
+/* UART - Register instance definitions */
+/* UART2 */
+#define UART2_BDH UART_BDH_REG(UART2)
+#define UART2_BDL UART_BDL_REG(UART2)
+#define UART2_C1 UART_C1_REG(UART2)
+#define UART2_C2 UART_C2_REG(UART2)
+#define UART2_S1 UART_S1_REG(UART2)
+#define UART2_S2 UART_S2_REG(UART2)
+#define UART2_C3 UART_C3_REG(UART2)
+#define UART2_D UART_D_REG(UART2)
+#define UART2_MA1 UART_MA1_REG(UART2)
+#define UART2_MA2 UART_MA2_REG(UART2)
+#define UART2_C4 UART_C4_REG(UART2)
+#define UART2_C5 UART_C5_REG(UART2)
+#define UART2_C7816 UART_C7816_REG(UART2)
+#define UART2_IE7816 UART_IE7816_REG(UART2)
+#define UART2_IS7816 UART_IS7816_REG(UART2)
+#define UART2_WP7816 UART_WP7816_REG(UART2)
+#define UART2_WN7816 UART_WN7816_REG(UART2)
+#define UART2_WF7816 UART_WF7816_REG(UART2)
+#define UART2_ET7816 UART_ET7816_REG(UART2)
+#define UART2_TL7816 UART_TL7816_REG(UART2)
+#define UART2_AP7816A_T0 UART_AP7816A_T0_REG(UART2)
+#define UART2_AP7816B_T0 UART_AP7816B_T0_REG(UART2)
+#define UART2_WP7816A_T0 UART_WP7816A_T0_REG(UART2)
+#define UART2_WP7816A_T1 UART_WP7816A_T1_REG(UART2)
+#define UART2_WP7816B_T0 UART_WP7816B_T0_REG(UART2)
+#define UART2_WP7816B_T1 UART_WP7816B_T1_REG(UART2)
+#define UART2_WGP7816_T1 UART_WGP7816_T1_REG(UART2)
+#define UART2_WP7816C_T1 UART_WP7816C_T1_REG(UART2)
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
+ uint8_t RESERVED_3[15];
+ __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
+ uint8_t RESERVED_4[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
+ uint8_t RESERVED_7[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
+ uint8_t RESERVED_8[3];
+ __I uint8_t STAT; /**< Status register, offset: 0x90 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t CTL; /**< Control register, offset: 0x94 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
+ uint8_t RESERVED_11[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
+ uint8_t RESERVED_14[11];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_16[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
+ uint8_t RESERVED_17[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
+ uint8_t RESERVED_20[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+ uint8_t RESERVED_21[43];
+ __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
+ uint8_t RESERVED_22[3];
+ __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
+ uint8_t RESERVED_23[15];
+ __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
+ uint8_t RESERVED_24[7];
+ __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_Type, *USB_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- USB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register accessors */
+#define USB_PERID_REG(base) ((base)->PERID)
+#define USB_IDCOMP_REG(base) ((base)->IDCOMP)
+#define USB_REV_REG(base) ((base)->REV)
+#define USB_ADDINFO_REG(base) ((base)->ADDINFO)
+#define USB_OTGCTL_REG(base) ((base)->OTGCTL)
+#define USB_ISTAT_REG(base) ((base)->ISTAT)
+#define USB_INTEN_REG(base) ((base)->INTEN)
+#define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
+#define USB_ERREN_REG(base) ((base)->ERREN)
+#define USB_STAT_REG(base) ((base)->STAT)
+#define USB_CTL_REG(base) ((base)->CTL)
+#define USB_ADDR_REG(base) ((base)->ADDR)
+#define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
+#define USB_FRMNUML_REG(base) ((base)->FRMNUML)
+#define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
+#define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
+#define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
+#define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
+#define USB_USBCTRL_REG(base) ((base)->USBCTRL)
+#define USB_OBSERVE_REG(base) ((base)->OBSERVE)
+#define USB_CONTROL_REG(base) ((base)->CONTROL)
+#define USB_USBTRC0_REG(base) ((base)->USBTRC0)
+#define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
+#define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
+#define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
+#define USB_CLK_RECOVER_INT_EN_REG(base) ((base)->CLK_RECOVER_INT_EN)
+#define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5_MASK 0x2u
+#define USB_ERRSTAT_CRC5_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT 0
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+/* CLK_RECOVER_CTRL Bit Fields */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
+/* CLK_RECOVER_IRC_EN Bit Fields */
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
+/* CLK_RECOVER_INT_EN Bit Fields */
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK 0x10u
+#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT 4
+/* CLK_RECOVER_INT_STATUS Bit Fields */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+#define USB0_BASE_PTR (USB0)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS { USB0_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- USB - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
+ * @{
+ */
+
+
+/* USB - Register instance definitions */
+/* USB0 */
+#define USB0_PERID USB_PERID_REG(USB0)
+#define USB0_IDCOMP USB_IDCOMP_REG(USB0)
+#define USB0_REV USB_REV_REG(USB0)
+#define USB0_ADDINFO USB_ADDINFO_REG(USB0)
+#define USB0_OTGCTL USB_OTGCTL_REG(USB0)
+#define USB0_ISTAT USB_ISTAT_REG(USB0)
+#define USB0_INTEN USB_INTEN_REG(USB0)
+#define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
+#define USB0_ERREN USB_ERREN_REG(USB0)
+#define USB0_STAT USB_STAT_REG(USB0)
+#define USB0_CTL USB_CTL_REG(USB0)
+#define USB0_ADDR USB_ADDR_REG(USB0)
+#define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
+#define USB0_FRMNUML USB_FRMNUML_REG(USB0)
+#define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
+#define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
+#define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
+#define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
+#define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
+#define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
+#define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
+#define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
+#define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
+#define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
+#define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
+#define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
+#define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
+#define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
+#define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
+#define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
+#define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
+#define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
+#define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
+#define USB0_USBCTRL USB_USBCTRL_REG(USB0)
+#define USB0_OBSERVE USB_OBSERVE_REG(USB0)
+#define USB0_CONTROL USB_CONTROL_REG(USB0)
+#define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
+#define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
+#define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
+#define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_EN USB_CLK_RECOVER_INT_EN_REG(USB0)
+#define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
+
+/* USB - Register array accessors */
+#define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
+ __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type, *VREF_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- VREF - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register accessors */
+#define VREF_TRM_REG(base) ((base)->TRM)
+#define VREF_SC_REG(base) ((base)->SC)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- VREF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/* TRM Bit Fields */
+#define VREF_TRM_TRIM_MASK 0x3Fu
+#define VREF_TRM_TRIM_SHIFT 0
+#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK 0x40u
+#define VREF_TRM_CHOPEN_SHIFT 6
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK 0x3u
+#define VREF_SC_MODE_LV_SHIFT 0
+#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK 0x4u
+#define VREF_SC_VREFST_SHIFT 2
+#define VREF_SC_ICOMPEN_MASK 0x20u
+#define VREF_SC_ICOMPEN_SHIFT 5
+#define VREF_SC_REGEN_MASK 0x40u
+#define VREF_SC_REGEN_SHIFT 6
+#define VREF_SC_VREFEN_MASK 0x80u
+#define VREF_SC_VREFEN_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF ((VREF_Type *)VREF_BASE)
+#define VREF_BASE_PTR (VREF)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS { VREF }
+
+/* ----------------------------------------------------------------------------
+ -- VREF - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
+ * @{
+ */
+
+
+/* VREF - Register instance definitions */
+/* VREF */
+#define VREF_TRM VREF_TRM_REG(VREF)
+#define VREF_SC VREF_SC_REG(VREF)
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+#define I2C_S1_RXAK_MASK I2C_S_RXAK_MASK
+#define I2C_S1_RXAK_SHIFT I2C_S_RXAK_SHIFT
+#define I2C_S1_IICIF_MASK I2C_S_IICIF_MASK
+#define I2C_S1_IICIF_SHIFT I2C_S_IICIF_SHIFTFT
+#define I2C_S1_SRW_MASK I2C_S_SRW_MASK
+#define I2C_S1_SRW_SHIFT I2C_S_SRW_SHIFT
+#define I2C_S1_RAM_MASK I2C_S_RAM_MASK
+#define I2C_S1_RAM_SHIFT I2C_S_RAM_SHIFT
+#define I2C_S1_ARBL_MASK I2C_S_ARBL_MASK
+#define I2C_S1_ARBL_SHIFT I2C_S_ARBL_SHIFT
+#define I2C_S1_BUSY_MASK I2C_S_BUSY_MASK
+#define I2C_S1_BUSY_SHIFT I2C_S_BUSY_SHIFT
+#define I2C_S1_IAAS_MASK I2C_S_IAAS_MASK
+#define I2C_S1_IAAS_SHIFT I2C_S_IAAS_SHIFT
+#define I2C_S1_TCF_MASK I2C_S_TCF_MASK
+#define I2C_S1_TCF_SHIFT I2C_S_TCF_SHIFT
+#define I2C_S1_REG(base) I2C_S_REG(base)
+#define I2C0_S1 I2C0_S
+#define I2C1_S1 I2C1_S
+#define ADC_BASES ADC_BASE_PTRS
+#define CMP_BASES CMP_BASE_PTRS
+#define DAC_BASES DAC_BASE_PTRS
+#define DMA_BASES DMA_BASE_PTRS
+#define DMAMUX_BASES DMAMUX_BASE_PTRS
+#define FLEXIO_BASES FLEXIO_BASE_PTRS
+#define FTFA_BASES FTFA_BASE_PTRS
+#define GPIO_BASES GPIO_BASE_PTRS
+#define I2C_BASES I2C_BASE_PTRS
+#define I2S_BASES I2S_BASE_PTRS
+#define LCD_BASES LCD_BASE_PTRS
+#define LLWU_BASES LLWU_BASE_PTRS
+#define LPTMR_BASES LPTMR_BASE_PTRS
+#define LPUART_BASES LPUART_BASE_PTRS
+#define MCG_BASES MCG_BASE_PTRS
+#define MCM_BASES MCM_BASE_PTRS
+#define MTB_BASES MTB_BASE_PTRS
+#define MTBDWT_BASES MTBDWT_BASE_PTRS
+#define NV_BASES NV_BASE_PTRS
+#define OSC_BASES OSC_BASE_PTRS
+#define PIT_BASES PIT_BASE_PTRS
+#define PMC_BASES PMC_BASE_PTRS
+#define PORT_BASES PORT_BASE_PTRS
+#define RCM_BASES RCM_BASE_PTRS
+#define ROM_BASES ROM_BASE_PTRS
+#define RTC_BASES RTC_BASE_PTRS
+#define SIM_BASES SIM_BASE_PTRS
+#define SMC_BASES SMC_BASE_PTRS
+#define SPI_BASES SPI_BASE_PTRS
+#define TPM_BASES TPM_BASE_PTRS
+#define UART_BASES UART_BASE_PTRS
+#define USB_BASES USB_BASE_PTRS
+#define VREF_BASES VREF_BASE_PTRS
+#define PTA_BASE_PTR GPIOA_BASE_PTR
+#define PTB_BASE_PTR GPIOB_BASE_PTR
+#define PTC_BASE_PTR GPIOC_BASE_PTR
+#define PTD_BASE_PTR GPIOD_BASE_PTR
+#define PTE_BASE_PTR GPIOE_BASE_PTR
+#define PTA_BASE GPIOA_BASE
+#define PTB_BASE GPIOB_BASE
+#define PTC_BASE GPIOC_BASE
+#define PTD_BASE GPIOD_BASE
+#define PTE_BASE GPIOE_BASE
+#define PTA GPIOA
+#define PTB GPIOB
+#define PTC GPIOC
+#define PTD GPIOD
+#define PTE GPIOE
+#define UART0_FLEXIO_IRQn UART2_FLEXIO_IRQn
+#define SIM_SOPT5_UART0ODE_MASK SIM_SOPT5_UART2ODE_MASK
+#define SIM_SOPT5_UART0ODE_SHIFT SIM_SOPT5_UART2ODE_SHIFT
+#define SIM_SCGC4_UART0_MASK SIM_SCGC4_UART2_MASK
+#define SIM_SCGC4_UART0_SHIFT SIM_SCGC4_UART2_SHIFT
+#define UART0_BASE UART2_BASE
+#define UART0 UART2
+#define UART0_BASE_PTR UART2_BASE_PTR
+#define UART0_BDH UART2_BDH
+#define UART0_BDL UART2_BDL
+#define UART0_C1 UART2_C1
+#define UART0_C2 UART2_C2
+#define UART0_S1 UART2_S1
+#define UART0_S2 UART2_S2
+#define UART0_C3 UART2_C3
+#define UART0_D UART2_D
+#define UART0_MA1 UART2_MA1
+#define UART0_MA2 UART2_MA2
+#define UART0_C4 UART2_C4
+#define UART0_C5 UART2_C5
+#define UART0_ED UART2_ED
+#define UART0_MODEM UART2_MODEM
+#define UART0_IR UART2_IR
+#define UART0_PFIFO UART2_PFIFO
+#define UART0_CFIFO UART2_CFIFO
+#define UART0_SFIFO UART2_SFIFO
+#define UART0_TWFIFO UART2_TWFIFO
+#define UART0_TCFIFO UART2_TCFIFO
+#define UART0_RWFIFO UART2_RWFIFO
+#define UART0_RCFIFO UART2_RCFIFO
+#define UART0_C7816 UART2_C7816
+#define UART0_IE7816 UART2_IE7816
+#define UART0_IS7816 UART2_IS7816
+#define UART0_WP7816 UART2_WP7816
+#define UART0_WN7816 UART2_WN7816
+#define UART0_WF7816 UART2_WF7816
+#define UART0_ET7816 UART2_ET7816
+#define UART0_TL7816 UART2_TL7816
+#define UART0_AP7816A_T0 UART2_AP7816A_T0
+#define UART0_AP7816B_T0 UART2_AP7816B_T0
+#define UART0_WP7816A_T0 UART2_WP7816A_T0
+#define UART0_WP7816A_T1 UART2_WP7816A_T1
+#define UART0_WP7816B_T0 UART2_WP7816B_T0
+#define UART0_WP7816B_T1 UART2_WP7816B_T1
+#define UART0_WGP7816_T1 UART2_WGP7816_T1
+#define UART0_WP7816C_T1 UART2_WP7816C_T1
+#define I2S0_MDR This_symb_has_been_deprecated
+#define I2S_MDR_DIVIDE_MASK This_symb_has_been_deprecated
+#define I2S_MDR_DIVIDE_SHIFT This_symb_has_been_deprecated
+#define I2S_MDR_DIVIDE(x) This_symb_has_been_deprecated
+#define I2S_MDR_FRACT_MASK This_symb_has_been_deprecated
+#define I2S_MDR_FRACT_SHIFT This_symb_has_been_deprecated
+#define I2S_MDR_FRACT(x) This_symb_has_been_deprecated
+#define I2S_MDR_REG(base) This_symb_has_been_deprecated
+#define CTL0 OTGCTL
+#define USB0_CTL0 USB0_OTGCTL
+#define USB_CTL0_REG(base) USB_OTGCTL_REG(base)
+#define USB_CTL0_DPHIGH_MASK USB_OTGCTL_DPHIGH_MASK
+#define USB_CTL0_DPHIGH_SHIFT USB_OTGCTL_DPHIGH_SHIFT
+#define CTL1 CTL
+#define USB0_CTL1 USB0_CTL
+#define USB_CTL1_REG(base) USB_CTL_REG(base)
+#define USB_CTL1_USBEN_MASK USB_CTL_USBEN_MASK
+#define USB_CTL1_USBEN_SHIFT USB_CTL_USBEN_SHIFT
+#define USB_CTL1_ODDRST_MASK USB_CTL_ODDRST_MASK
+#define USB_CTL1_ODDRST_SHIFT USB_CTL_ODDRST_SHIFT
+#define USB_CTL1_TXSUSPENDTOKENBUSY_MASK USB_CTL_TXSUSPENDTOKENBUSY_MASK
+#define USB_CTL1_TXSUSPENDTOKENBUSY_SHIFT USB_CTL_TXSUSPENDTOKENBUSY_SHIFT
+#define USB_CTL1_SE0_MASK USB_CTL_SE0_MASK
+#define USB_CTL1_SE0_SHIFT USB_CTL_SE0_SHIFT
+#define USB_CTL1_JSTATE_MASK USB_CTL_JSTATE_MASK
+#define USB_CTL1_JSTATE_SHIFT USB_CTL_JSTATE_SHIFT
+#define USB_CTL_USBEN_MASK USB_CTL_USBENSOFEN_MASK
+#define USB_CTL_USBEN_SHIFT USB_CTL_USBENSOFEN_SHIFT
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#else /* #if !defined(MKL43Z4_H_) */
+ /* There is already included the same memory map. Check if it is compatible (has the same major version) */
+ #if (MCU_MEM_MAP_VERSION != 0x0100u)
+ #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
+ #warning There are included two not compatible versions of memory maps. Please check possible differences.
+ #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
+ #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
+#endif /* #if !defined(MKL43Z4_H_) */
+
+/* MKL43Z4.h, eof. */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/MKL43Z4.sct b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/MKL43Z4.sct
new file mode 100644
index 000000000..82ddfb878
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/MKL43Z4.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
+ ER_IROM1 0x00000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 0x8000 - 0xC0 = 0x7F40
+ RW_IRAM1 0x1FFFE0C0 0x7F40 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/startup_MKL43Z4.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/startup_MKL43Z4.s
new file mode 100644
index 000000000..58abd545d
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/startup_MKL43Z4.s
@@ -0,0 +1,362 @@
+; * ---------------------------------------------------------------------------------------
+; * @file: startup_MKL43Z4.s
+; * @purpose: CMSIS Cortex-M0P Core Device Startup File
+; * MKL43Z4
+; * @version: 1.3
+; * @date: 2014-8-21
+; * @build: b140821
+; * ---------------------------------------------------------------------------------------
+; *
+; * Copyright (c) 1997 - 2014 , Freescale Semiconductor, Inc.
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without modification,
+; * are permitted provided that the following conditions are met:
+; *
+; * o Redistributions of source code must retain the above copyright notice, this list
+; * of conditions and the following disclaimer.
+; *
+; * o Redistributions in binary form must reproduce the above copyright notice, this
+; * list of conditions and the following disclaimer in the documentation and/or
+; * other materials provided with the distribution.
+; *
+; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+; * contributors may be used to endorse or promote products derived from this
+; * software without specific prior written permission.
+; *
+; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; *
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20006000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ;NMI Handler
+ DCD HardFault_Handler ;Hard Fault Handler
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD SVC_Handler ;SVCall Handler
+ DCD 0 ;Reserved
+ DCD 0 ;Reserved
+ DCD PendSV_Handler ;PendSV Handler
+ DCD SysTick_Handler ;SysTick Handler
+
+ ;External Interrupts
+ DCD DMA0_IRQHandler ;DMA channel 0 transfer complete
+ DCD DMA1_IRQHandler ;DMA channel 1 transfer complete
+ DCD DMA2_IRQHandler ;DMA channel 2 transfer complete
+ DCD DMA3_IRQHandler ;DMA channel 3 transfer complete
+ DCD Reserved20_IRQHandler ;Reserved interrupt
+ DCD FTFA_IRQHandler ;Command complete and read collision
+ DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning
+ DCD LLWU_IRQHandler ;Low leakage wakeup
+ DCD I2C0_IRQHandler ;I2C0 interrupt
+ DCD I2C1_IRQHandler ;I2C1 interrupt
+ DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources
+ DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources
+ DCD LPUART0_IRQHandler ;LPUART0 status and error
+ DCD LPUART1_IRQHandler ;LPUART1 status and error
+ DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO
+ DCD ADC0_IRQHandler ;ADC0 interrupt
+ DCD CMP0_IRQHandler ;CMP0 interrupt
+ DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources
+ DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources
+ DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources
+ DCD RTC_IRQHandler ;RTC alarm
+ DCD RTC_Seconds_IRQHandler ;RTC seconds
+ DCD PIT_IRQHandler ;PIT interrupt
+ DCD I2S0_IRQHandler ;I2S0 interrupt
+ DCD USB0_IRQHandler ;USB0 interrupt
+ DCD DAC0_IRQHandler ;DAC0 interrupt
+ DCD Reserved42_IRQHandler ;Reserved interrupt
+ DCD Reserved43_IRQHandler ;Reserved interrupt
+ DCD LPTMR0_IRQHandler ;LPTMR0 interrupt
+ DCD LCD_IRQHandler ;LCD interrupt
+ DCD PORTA_IRQHandler ;PORTA Pin detect
+ DCD PORTCD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict access to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2>
+; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2>
+; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2>
+; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2>
+; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2>
+; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2>
+; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2>
+; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program Flash Region Protect Register 0
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT0
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
+; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
+; <o.1> BOOTPIN_OPT
+; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin
+; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits
+; <o.2> NMI_DIS
+; <0=> NMI interrupts are always blocked
+; <1=> NMI_b pin/interrupts reset default to enabled
+; <o.3> RESET_PIN_CFG
+; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function
+; <1=> RESET_b pin is dedicated
+; <o.4> LPBOOT1
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
+; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
+; <o.5> FAST_INIT
+; <0=> Slower initialization
+; <1=> Fast Initialization
+; <o.6..7> BOOTSRC_SEL
+; <0=> Boot from Flash
+; <2=> Boot from ROM
+; <3=> Boot from ROM
+; <i> Boot source selection
+FOPT EQU 0x3F
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor Key Security Enable
+FSEC EQU 0xFE
+; </h>
+; </h>
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, DATA, READONLY
+__FlashConfig
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0 , FPROT1 , FPROT2 , FPROT3
+ DCB FSEC , FOPT , 0xFF , 0xFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+NMI_Handler\
+ PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler\
+ PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler\
+ PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler\
+ PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+Default_Handler\
+ PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT Reserved20_IRQHandler [WEAK]
+ EXPORT FTFA_IRQHandler [WEAK]
+ EXPORT PMC_IRQHandler [WEAK]
+ EXPORT LLWU_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT LPUART0_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT UART2_FLEXIO_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT TPM0_IRQHandler [WEAK]
+ EXPORT TPM1_IRQHandler [WEAK]
+ EXPORT TPM2_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT_IRQHandler [WEAK]
+ EXPORT I2S0_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT Reserved42_IRQHandler [WEAK]
+ EXPORT Reserved43_IRQHandler [WEAK]
+ EXPORT LPTMR0_IRQHandler [WEAK]
+ EXPORT LCD_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTCD_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+PMC_IRQHandler
+LLWU_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+LPUART0_IRQHandler
+LPUART1_IRQHandler
+UART2_FLEXIO_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+I2S0_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+Reserved42_IRQHandler
+Reserved43_IRQHandler
+LPTMR0_IRQHandler
+LCD_IRQHandler
+PORTA_IRQHandler
+PORTCD_IRQHandler
+DefaultISR
+ B .
+ ENDP
+ ALIGN
+
+
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/sys.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/MKL43Z4.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/MKL43Z4.ld
new file mode 100644
index 000000000..80cc231e5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/MKL43Z4.ld
@@ -0,0 +1,163 @@
+/*
+ * KL43Z ARM GCC linker script file
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFFE0C0, LENGTH = 32K - 0xC0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ *(.text.Reset_Handler)
+ *(.text.System_Init)
+ . = ALIGN(4);
+ } > VECTORS
+
+ .flash_protect :
+ {
+ KEEP(*(.kinetis_flash_config_field))
+ . = ALIGN(4);
+ } > FLASH_PROTECTION
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/startup_MKL43Z4.S b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/startup_MKL43Z4.S
new file mode 100644
index 000000000..7f1b04ccf
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/startup_MKL43Z4.S
@@ -0,0 +1,243 @@
+/* KL43Z startup ARM GCC
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.3
+ * Date: 10 Nov 2014
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x200 + 0x400 = 0x600
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x200
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vector_table,"a",%progbits
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
+ .long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
+ .long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
+ .long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
+ .long Default_Handler /* Reserved interrupt 20 */
+ .long FTFA_IRQHandler /* FTFA interrupt */
+ .long PMC_IRQHandler /* Low-voltage detect, low-voltage warning*/
+ .long LLWU_IRQHandler /* Low leakage wakeup*/
+ .long I2C0_IRQHandler /* I2C0 interrupt*/
+ .long I2C1_IRQHandler /* I2C1 interrupt*/
+ .long SPI0_IRQHandler /* SPI0 single interrupt vector for all sources*/
+ .long SPI1_IRQHandler /* SPI1 single interrupt vector for all sources*/
+ .long LPUART0_IRQHandler /* LPUART0 status and error*/
+ .long LPUART1_IRQHandler /* LPUART1 status and error*/
+ .long UART2_FLEXIO_IRQHandler /* UART2 or FLEXIO*/
+ .long ADC0_IRQHandler /* ADC0 interrupt*/
+ .long CMP0_IRQHandler /* CMP0 interrupt*/
+ .long TPM0_IRQHandler /* TPM0 single interrupt vector for all sources*/
+ .long TPM1_IRQHandler /* TPM1 single interrupt vector for all sources*/
+ .long TPM2_IRQHandler /* TPM2 single interrupt vector for all sources*/
+ .long RTC_IRQHandler /* RTC alarm*/
+ .long RTC_Seconds_IRQHandler /* RTC seconds*/
+ .long PIT_IRQHandler /* PIT interrupt*/
+ .long I2S0_IRQHandler /* I2S0 interrupt*/
+ .long USB0_IRQHandler /* USB0 interrupt*/
+ .long DAC0_IRQHandler /* DAC0 interrupt*/
+ .long Reserved42_IRQHandler /* Reserved interrupt*/
+ .long Reserved43_IRQHandler /* Reserved interrupt*/
+ .long LPTMR0_IRQHandler /* LPTMR0 interrupt*/
+ .long LCD_IRQHandler /* LCD interrupt*/
+ .long PORTA_IRQHandler /* PORTA Pin detect*/
+ .long PORTCD_IRQHandler /* Single interrupt vector for PORTC; PORTD Pin detect*/
+
+ .size __isr_vector, . - __isr_vector
+
+ /* Reset Handler */
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ /* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler DMA0_IRQHandler
+ def_irq_default_handler DMA1_IRQHandler
+ def_irq_default_handler DMA2_IRQHandler
+ def_irq_default_handler DMA3_IRQHandler
+ def_irq_default_handler Reserved20_IRQHandler
+ def_irq_default_handler FTFA_IRQHandler
+ def_irq_default_handler PMC_IRQHandler
+ def_irq_default_handler LLWU_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler LPUART0_IRQHandler
+ def_irq_default_handler LPUART1_IRQHandler
+ def_irq_default_handler UART2_FLEXIO_IRQHandler
+ def_irq_default_handler ADC0_IRQHandler
+ def_irq_default_handler CMP0_IRQHandler
+ def_irq_default_handler TPM0_IRQHandler
+ def_irq_default_handler TPM1_IRQHandler
+ def_irq_default_handler TPM2_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler RTC_Seconds_IRQHandler
+ def_irq_default_handler PIT_IRQHandler
+ def_irq_default_handler I2S0_IRQHandler
+ def_irq_default_handler USB0_IRQHandler
+ def_irq_default_handler DAC0_IRQHandler
+ def_irq_default_handler Reserved42_IRQHandler
+ def_irq_default_handler Reserved43_IRQHandler
+ def_irq_default_handler LPTMR0_IRQHandler
+ def_irq_default_handler LCD_IRQHandler
+ def_irq_default_handler PORTA_IRQHandler
+ def_irq_default_handler PORTCD_IRQHandler
+ def_irq_default_handler DefaultISR
+
+ /* Flash protection region, placed at 0x400 */
+ .text
+ .thumb
+ .align 2
+ .section .kinetis_flash_config_field,"a",%progbits
+kinetis_flash_config:
+ .long 0xFFFFFFFF
+ .long 0xFFFFFFFF
+ .long 0xFFFFFFFF
+ .long 0xFFFF3FFE
+
+ .end
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/sys.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/sys.cpp
new file mode 100644
index 000000000..fe88ed4fc
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/TOOLCHAIN_GCC_ARM/sys.cpp
@@ -0,0 +1,32 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <sys/types.h>
+#include <errno.h>
+
+extern void exit(int return_code);
+
+int _kill(int pid, int sig) {
+ errno = EINVAL;
+ return -1;
+}
+
+void _exit(int status) {
+ exit(status);
+}
+
+int _getpid(void) {
+ return 1;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis.h
new file mode 100644
index 000000000..c7bc71154
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MKL43Z4.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.c
new file mode 100644
index 000000000..8d6430685
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.c
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library - cmsis_nvic for LPC11U24
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.h
new file mode 100644
index 000000000..6acdca9ef
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/cmsis_nvic.h
@@ -0,0 +1,26 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.c
new file mode 100644
index 000000000..e17528f3b
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.c
@@ -0,0 +1,224 @@
+/*
+** ###################################################################
+** Processors: MKL43Z256VLH4
+** MKL43Z128VLH4
+** MKL43Z64VLH4
+** MKL43Z256VMP4
+** MKL43Z128VMP4
+** MKL43Z64VMP4
+**
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
+** Version: rev. 1.4, 2014-09-01
+** Build: b140904
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright (c) 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2014-03-27)
+** Initial version.
+** - rev. 1.1 (2014-05-26)
+** I2S registers TCR2/RCR2 and others were changed.
+** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
+** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
+** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
+** Clock configuration for high range external oscillator has been added.
+** RFSYS module access has been added.
+** - rev. 1.2 (2014-07-10)
+** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
+** UART0 - UART0 module renamed to UART2.
+** I2S - removed MDR register.
+** - rev. 1.3 (2014-08-21)
+** UART2 - Removed ED register.
+** UART2 - Removed MODEM register.
+** UART2 - Removed IR register.
+** UART2 - Removed PFIFO register.
+** UART2 - Removed CFIFO register.
+** UART2 - Removed SFIFO register.
+** UART2 - Removed TWFIFO register.
+** UART2 - Removed TCFIFO register.
+** UART2 - Removed RWFIFO register.
+** UART2 - Removed RCFIFO register.
+** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
+** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
+** SIM - Removed bitfield DIEID in SDID register.
+** - rev. 1.4 (2014-09-01)
+** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
+** USB - USB0_CTL1 was renamed to USB0_CTL register.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL43Z4
+ * @version 1.4
+ * @date 2014-09-01
+ * @brief Device specific configuration file for MKL43Z4 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MKL43Z4.h"
+
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+
+#if (ACK_ISOLATION)
+ if(PMC->REGSC & PMC_REGSC_ACKISO_MASK) {
+ PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
+ }
+#endif
+
+#if (DISABLE_WDOG)
+ /* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
+ SIM->COPC = (uint32_t)0x00u;
+#endif /* (DISABLE_WDOG) */
+
+ /* Power mode protection initialization */
+#ifdef SMC_PMPROT_VALUE
+ SMC->PMPROT = SMC_PMPROT_VALUE;
+#endif
+
+ /* System clock initialization */
+
+ /* Set system prescalers and clock sources */
+ SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
+ SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
+#define SOPT2_WRITE_MASK ((SIM_SOPT2_USBSRC_MASK) | (SIM_SOPT2_TPMSRC_MASK) | (SIM_SOPT2_LPUART0SRC_MASK) | (SIM_SOPT2_LPUART1SRC_MASK)) /* define mask of written bits. */
+ SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~SOPT2_WRITE_MASK)) | ((SYSTEM_SIM_SOPT2_VALUE) & SOPT2_WRITE_MASK); /* Selects the clock source for the TPM counter clock. */
+#if (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M || MCG_MODE == MCG_MODE_HIRC)
+ /* Set MCG and OSC0 */
+#if (((OSC0_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U)
+ /* SIM_SCGC5: PORTA=1 */
+ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+ /* PORTA_PCR3: ISF=0,MUX=0 */
+ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
+ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ }
+#endif
+ MCG->SC = MCG_SC_VALUE; /* Set SC (internal reference clock divider) */
+ MCG->MC = MCG_MC_VALUE; /* Set MC (high-frequency IRC enable, second LIRC divider) */
+ MCG->C1 = MCG_C1_VALUE; /* Set C1 (clock source selection, int. reference enable etc.) */
+ MCG->C2 = MCG_C2_VALUE; /* Set C2 (ext. and int. reference clock selection) */
+ OSC0->CR = OSC0_CR_VALUE; /* Set OSC0_CR (OSCERCLK enable, oscillator capacitor load) */
+
+#else /* MCG_MODE */
+ /* Set MCG and OSC0 */
+ /* SIM_SCGC5: PORTA=1 */
+ SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
+ /* PORTA_PCR3: ISF=0,MUX=0 */
+ PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
+ PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
+ }
+ MCG->SC = MCG_SC_VALUE; /* Set SC (internal reference clock divider) */
+ MCG->C2 = MCG_C2_VALUE; /* Set C2 (ext. and int. reference clock selection) */
+ OSC0->CR = OSC0_CR_VALUE; /* Set OSC0_CR (OSCERCLK enable, oscillator capacitor load) */
+ MCG->C1 = MCG_C1_VALUE; /* Set C1 (clock source selection, int. reference enable etc.) */
+ MCG->MC = MCG_MC_VALUE; /* Set MC (high-frequency IRC enable, second LIRC divider) */
+ if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0U) {
+ while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
+ }
+ }
+#endif /* MCG_MODE */
+
+ /* Common for all MCG modes */
+
+#if (MCG_MODE == MCG_MODE_HIRC)
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until high internal reference clock is selected as MCG_Lite output */
+ }
+#elif (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M)
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until low internal reference clock is selected as MCG_Lite output */
+ }
+#elif (MCG_MODE == MCG_MODE_EXT)
+ while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG_Lite output */
+ }
+#endif
+ if (((SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == SMC_PMCTRL_RUNM(0x02U)) {
+ SMC->PMCTRL = (uint8_t)((SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
+ while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
+ }
+ }
+
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint16_t Divider;
+
+ if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U) {
+ /* High internal reference clock is selected */
+ MCGOUTClock = CPU_INT_FAST_CLK_HZ; /* Fast internal reference clock selected */
+ } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U) {
+ /* Internal reference clock is selected */
+ Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
+ MCGOUTClock = (uint32_t) (CPU_INT_SLOW_CLK_HZ / Divider); /* Slow internal reference clock 8MHz selected */
+ } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ;
+ } else {
+ /* Reserved value */
+ return;
+ } /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */
+ SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h
new file mode 100644
index 000000000..4b07fde83
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h
@@ -0,0 +1,335 @@
+/*
+** ###################################################################
+** Processors: MKL43Z256VLH4
+** MKL43Z128VLH4
+** MKL43Z64VLH4
+** MKL43Z256VMP4
+** MKL43Z128VMP4
+** MKL43Z64VMP4
+**
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
+** Version: rev. 1.4, 2014-09-01
+** Build: b140904
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright (c) 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2014-03-27)
+** Initial version.
+** - rev. 1.1 (2014-05-26)
+** I2S registers TCR2/RCR2 and others were changed.
+** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
+** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
+** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
+** Clock configuration for high range external oscillator has been added.
+** RFSYS module access has been added.
+** - rev. 1.2 (2014-07-10)
+** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
+** UART0 - UART0 module renamed to UART2.
+** I2S - removed MDR register.
+** - rev. 1.3 (2014-08-21)
+** UART2 - Removed ED register.
+** UART2 - Removed MODEM register.
+** UART2 - Removed IR register.
+** UART2 - Removed PFIFO register.
+** UART2 - Removed CFIFO register.
+** UART2 - Removed SFIFO register.
+** UART2 - Removed TWFIFO register.
+** UART2 - Removed TCFIFO register.
+** UART2 - Removed RWFIFO register.
+** UART2 - Removed RCFIFO register.
+** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
+** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
+** SIM - Removed bitfield DIEID in SDID register.
+** - rev. 1.4 (2014-09-01)
+** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
+** USB - USB0_CTL1 was renamed to USB0_CTL register.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL43Z4
+ * @version 1.4
+ * @date 2014-09-01
+ * @brief Device specific configuration file for MKL43Z4 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MKL43Z4_H_
+#define SYSTEM_MKL43Z4_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#ifndef DISABLE_WDOG
+ #define DISABLE_WDOG 1
+#endif
+
+#define ACK_ISOLATION 1
+
+#ifndef CLOCK_SETUP
+ #define CLOCK_SETUP 1
+#endif
+
+/* MCG_Lite mode constants */
+
+#define MCG_MODE_LIRC_8M 0U
+#define MCG_MODE_HIRC 1U
+#define MCG_MODE_LIRC_2M 2U
+#define MCG_MODE_EXT 3U
+
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 8 MHz (LIRC 8 MHz) mode
+ Default part configuration.
+ Core clock/Bus clock derived from the internal clock source 8 MHz
+ Core clock = 4MHz, BusClock = 2MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+ 1 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
+ Maximum achievable clock frequency configuration using internal clock.
+ Core clock/Bus clock derived from the internal clock source 48MHz
+ Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+ 2 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
+ Core clock/Bus clock derived directly from the external crystal 32.768kHz
+ The clock settings is ready for Very Low Power Run mode.
+ Core clock = 32.768kHz, BusClock = 32.768kHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+ 3 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 2 MHz (LIRC 2 MHz) mode
+ Core clock/Bus clock derived from the internal clock source 2 MHz
+ The clock settings is ready for Very Low Power Run mode.
+ Core clock = 2MHz, BusClock = 1MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+ 4 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
+ USB clock setup - for USB to receive internal 48MHz clock derived from HIRC.
+ Core clock/Bus clock derived from the internal clock source 48MHz
+ Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from HIRC (MCGPCLK)
+ 5 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
+ Core clock/Bus clock derived directly from the external crystal 8 MHz
+ Core clock = 8MHz, BusClock = 4MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
+*/
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ 48000000u /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AVLP=1,AVLLS=1 */
+#define SMC_PMPROT_VALUE 0x22u /* SMC_PMPROT */
+
+#if (CLOCK_SETUP == 0)
+ #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
+ #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define MCG_MODE MCG_MODE_LIRC_8M /* Clock generator mode */
+ /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
+ #define MCG_C1_VALUE 0x42u /* MCG_C1 */
+ /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
+ #define MCG_C2_VALUE 0x01u /* MCG_C2 */
+ /* MCG_SC: FCRDIV=0 */
+ #define MCG_SC_VALUE 0x00u /* MCG_SC */
+ /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
+ #define MCG_MC_VALUE 0x00u /* MCG_MC */
+ /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
+ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
+ /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000u /* SIM_CLKDIV1 */
+ /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
+ /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 1)
+ #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
+ #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define MCG_MODE MCG_MODE_HIRC /* Clock generator mode */
+ /* MCG_C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */
+ #define MCG_C1_VALUE 0x00u /* MCG_C1 */
+ /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
+ #define MCG_C2_VALUE 0x01u /* MCG_C2 */
+ /* MCG_SC: FCRDIV=0 */
+ #define MCG_SC_VALUE 0x00u /* MCG_SC */
+ /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
+ #define MCG_MC_VALUE 0x80u /* MCG_MC */
+ /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
+ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
+ /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
+ /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x03000000U /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 2)
+ #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
+ #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define MCG_MODE MCG_MODE_EXT /* Clock generator mode */
+ /* MCG_C1: CLKS=2,IRCLKEN=1,IREFSTEN=0 */
+ #define MCG_C1_VALUE 0x82u /* MCG_C1 */
+ /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=1,IRCS=1 */
+ #define MCG_C2_VALUE 0x05u /* MCG_C2 */
+ /* MCG_SC: FCRDIV=0 */
+ #define MCG_SC_VALUE 0x00u /* MCG_SC */
+ /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
+ #define MCG_MC_VALUE 0x00u /* MCG_MC */
+ /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define OSC0_CR_VALUE 0x80u /* OSC0_CR */
+ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x00u /* SIM_CLKDIV1 */
+ /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
+ /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=2,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x02000000u /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 3)
+ #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
+ #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
+ /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
+ #define MCG_C1_VALUE 0x42u /* MCG_C1 */
+ /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=0 */
+ #define MCG_C2_VALUE 0x00u /* MCG_C2 */
+ /* MCG_SC: FCRDIV=0 */
+ #define MCG_SC_VALUE 0x00u /* MCG_SC */
+ /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
+ #define MCG_MC_VALUE 0x00u /* MCG_MC */
+ /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
+ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
+ /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
+ /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 4)
+ #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
+ #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
+ /* MCG_C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */
+ #define MCG_C1_VALUE 0x02u /* MCG_C1 */
+ /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
+ #define MCG_C2_VALUE 0x01u /* MCG_C2 */
+ /* MCG_SC: FCRDIV=0 */
+ #define MCG_SC_VALUE 0x00u /* MCG_SC */
+ /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
+ #define MCG_MC_VALUE 0x80u /* MCG_MC */
+ /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
+ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
+ /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
+ /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x03040000u /* SIM_SOPT2 */
+#elif (CLOCK_SETUP == 5)
+ #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
+ #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
+ /* MCG_C1: CLKS=2,IRCLKEN=0,IREFSTEN=0 */
+ #define MCG_C1_VALUE 0x80u /* MCG_C1 */
+ /* MCG_C2: RANGE0=1,HGO0=0,EREFS0=1,IRCS=1 */
+ #define MCG_C2_VALUE 0x15u /* MCG_C2 */
+ /* MCG_SC: FCRDIV=0 */
+ #define MCG_SC_VALUE 0x00u /* MCG_SC */
+ /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
+ #define MCG_MC_VALUE 0x00u /* MCG_MC */
+ /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ #define OSC0_CR_VALUE 0x80u /* OSC0_CR */
+ /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
+ #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
+ /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
+ #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
+ /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
+ #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
+ /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
+ #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
+#else
+ #error The selected clock setup is not supported.
+#endif /* (CLOCK_SETUP == 5) */
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MKL43Z4_H_) */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/MKL46Z4.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/MKL46Z4.h
new file mode 100644
index 000000000..9f975d7d0
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/MKL46Z4.h
@@ -0,0 +1,5801 @@
+/*
+** ###################################################################
+** Processors: MKL46Z256VLH4
+** MKL46Z128VLH4
+** MKL46Z256VLL4
+** MKL46Z128VLL4
+** MKL46Z256VMC4
+** MKL46Z128VMC4
+**
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL46P121M48SF4RM, Rev.2, Dec 2012
+** Version: rev. 2.2, 2013-04-12
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MKL46Z4
+**
+** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-10-16)
+** Initial version.
+** - rev. 2.0 (2012-12-12)
+** Update to reference manual rev. 1.
+** - rev. 2.1 (2013-04-05)
+** Changed start of doxygen comment.
+** - rev. 2.2 (2013-04-12)
+** SystemInit function fixed for clock configuration 1.
+** Name of the interrupt num. 31 updated to reflect proper function.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MKL46Z4.h
+ * @version 2.2
+ * @date 2013-04-12
+ * @brief CMSIS Peripheral Access Layer for MKL46Z4
+ *
+ * CMSIS Peripheral Access Layer for MKL46Z4
+ */
+
+#if !defined(MKL46Z4_H_)
+#define MKL46Z4_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0002u
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */
+ DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */
+ DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */
+ DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */
+ Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
+ FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */
+ LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 7, /**< Low Leakage Wakeup */
+ I2C0_IRQn = 8, /**< I2C0 interrupt */
+ I2C1_IRQn = 9, /**< I2C0 interrupt 25 */
+ SPI0_IRQn = 10, /**< SPI0 interrupt */
+ SPI1_IRQn = 11, /**< SPI1 interrupt */
+ UART0_IRQn = 12, /**< UART0 status/error interrupt */
+ UART1_IRQn = 13, /**< UART1 status/error interrupt */
+ UART2_IRQn = 14, /**< UART2 status/error interrupt */
+ ADC0_IRQn = 15, /**< ADC0 interrupt */
+ CMP0_IRQn = 16, /**< CMP0 interrupt */
+ TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */
+ TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */
+ TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */
+ RTC_IRQn = 20, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */
+ PIT_IRQn = 22, /**< PIT timer interrupt */
+ I2S0_IRQn = 23, /**< I2S0 transmit interrupt */
+ USB0_IRQn = 24, /**< USB0 interrupt */
+ DAC0_IRQn = 25, /**< DAC0 interrupt */
+ TSI0_IRQn = 26, /**< TSI0 interrupt */
+ MCG_IRQn = 27, /**< MCG interrupt */
+ LPTimer_IRQn = 28, /**< LPTimer interrupt */
+ LCD_IRQn = 29, /**< Segment LCD Interrupt */
+ PORTA_IRQn = 30, /**< Port A interrupt */
+ PORTC_PORTD_IRQn = 31 /**< Port C and port D interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M0 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
+ * @{
+ */
+
+#define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm0plus.h" /* Core Peripheral Access Layer */
+#include "system_MKL46Z4.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASES { ADC0 }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK 0x3u
+#define CMP_CR0_HYSTCTR_SHIFT 0
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK 0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT 4
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK 0x1u
+#define CMP_CR1_EN_SHIFT 0
+#define CMP_CR1_OPE_MASK 0x2u
+#define CMP_CR1_OPE_SHIFT 1
+#define CMP_CR1_COS_MASK 0x4u
+#define CMP_CR1_COS_SHIFT 2
+#define CMP_CR1_INV_MASK 0x8u
+#define CMP_CR1_INV_SHIFT 3
+#define CMP_CR1_PMODE_MASK 0x10u
+#define CMP_CR1_PMODE_SHIFT 4
+#define CMP_CR1_TRIGM_MASK 0x20u
+#define CMP_CR1_TRIGM_SHIFT 5
+#define CMP_CR1_WE_MASK 0x40u
+#define CMP_CR1_WE_SHIFT 6
+#define CMP_CR1_SE_MASK 0x80u
+#define CMP_CR1_SE_SHIFT 7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK 0xFFu
+#define CMP_FPR_FILT_PER_SHIFT 0
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK 0x1u
+#define CMP_SCR_COUT_SHIFT 0
+#define CMP_SCR_CFF_MASK 0x2u
+#define CMP_SCR_CFF_SHIFT 1
+#define CMP_SCR_CFR_MASK 0x4u
+#define CMP_SCR_CFR_SHIFT 2
+#define CMP_SCR_IEF_MASK 0x8u
+#define CMP_SCR_IEF_SHIFT 3
+#define CMP_SCR_IER_MASK 0x10u
+#define CMP_SCR_IER_SHIFT 4
+#define CMP_SCR_DMAEN_MASK 0x40u
+#define CMP_SCR_DMAEN_SHIFT 6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK 0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT 0
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK 0x40u
+#define CMP_DACCR_VRSEL_SHIFT 6
+#define CMP_DACCR_DACEN_MASK 0x80u
+#define CMP_DACCR_DACEN_SHIFT 7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK 0x7u
+#define CMP_MUXCR_MSEL_SHIFT 0
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK 0x38u
+#define CMP_MUXCR_PSEL_SHIFT 3
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK 0x80u
+#define CMP_MUXCR_PSTM_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0 ((CMP_Type *)CMP0_BASE)
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASES { CMP0 }
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DAC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+ __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+ } DAT[2];
+ uint8_t RESERVED_0[28];
+ __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
+ __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
+ __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
+ __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DAC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA0_MASK 0xFFu
+#define DAC_DATL_DATA0_SHIFT 0
+#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA1_MASK 0xFu
+#define DAC_DATH_DATA1_SHIFT 0
+#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK 0x1u
+#define DAC_SR_DACBFRPBF_SHIFT 0
+#define DAC_SR_DACBFRPTF_MASK 0x2u
+#define DAC_SR_DACBFRPTF_SHIFT 1
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK 0x1u
+#define DAC_C0_DACBBIEN_SHIFT 0
+#define DAC_C0_DACBTIEN_MASK 0x2u
+#define DAC_C0_DACBTIEN_SHIFT 1
+#define DAC_C0_LPEN_MASK 0x8u
+#define DAC_C0_LPEN_SHIFT 3
+#define DAC_C0_DACSWTRG_MASK 0x10u
+#define DAC_C0_DACSWTRG_SHIFT 4
+#define DAC_C0_DACTRGSEL_MASK 0x20u
+#define DAC_C0_DACTRGSEL_SHIFT 5
+#define DAC_C0_DACRFS_MASK 0x40u
+#define DAC_C0_DACRFS_SHIFT 6
+#define DAC_C0_DACEN_MASK 0x80u
+#define DAC_C0_DACEN_SHIFT 7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK 0x1u
+#define DAC_C1_DACBFEN_SHIFT 0
+#define DAC_C1_DACBFMD_MASK 0x4u
+#define DAC_C1_DACBFMD_SHIFT 2
+#define DAC_C1_DMAEN_MASK 0x80u
+#define DAC_C1_DMAEN_SHIFT 7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK 0x1u
+#define DAC_C2_DACBFUP_SHIFT 0
+#define DAC_C2_DACBFRP_MASK 0x10u
+#define DAC_C2_DACBFRP_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE (0x4003F000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0 ((DAC_Type *)DAC0_BASE)
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASES { DAC0 }
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[256];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
+ __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
+ union { /* offset: 0x108, array step: 0x10 */
+ __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
+ struct { /* offset: 0x108, array step: 0x10 */
+ uint8_t RESERVED_0[3];
+ __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
+ } DMA_DSR_ACCESS8BIT;
+ };
+ __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
+ } DMA[4];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/* SAR Bit Fields */
+#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
+#define DMA_SAR_SAR_SHIFT 0
+#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
+/* DAR Bit Fields */
+#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
+#define DMA_DAR_DAR_SHIFT 0
+#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
+/* DSR_BCR Bit Fields */
+#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
+#define DMA_DSR_BCR_BCR_SHIFT 0
+#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
+#define DMA_DSR_BCR_DONE_MASK 0x1000000u
+#define DMA_DSR_BCR_DONE_SHIFT 24
+#define DMA_DSR_BCR_BSY_MASK 0x2000000u
+#define DMA_DSR_BCR_BSY_SHIFT 25
+#define DMA_DSR_BCR_REQ_MASK 0x4000000u
+#define DMA_DSR_BCR_REQ_SHIFT 26
+#define DMA_DSR_BCR_BED_MASK 0x10000000u
+#define DMA_DSR_BCR_BED_SHIFT 28
+#define DMA_DSR_BCR_BES_MASK 0x20000000u
+#define DMA_DSR_BCR_BES_SHIFT 29
+#define DMA_DSR_BCR_CE_MASK 0x40000000u
+#define DMA_DSR_BCR_CE_SHIFT 30
+/* DCR Bit Fields */
+#define DMA_DCR_LCH2_MASK 0x3u
+#define DMA_DCR_LCH2_SHIFT 0
+#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
+#define DMA_DCR_LCH1_MASK 0xCu
+#define DMA_DCR_LCH1_SHIFT 2
+#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
+#define DMA_DCR_LINKCC_MASK 0x30u
+#define DMA_DCR_LINKCC_SHIFT 4
+#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
+#define DMA_DCR_D_REQ_MASK 0x80u
+#define DMA_DCR_D_REQ_SHIFT 7
+#define DMA_DCR_DMOD_MASK 0xF00u
+#define DMA_DCR_DMOD_SHIFT 8
+#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
+#define DMA_DCR_SMOD_MASK 0xF000u
+#define DMA_DCR_SMOD_SHIFT 12
+#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
+#define DMA_DCR_START_MASK 0x10000u
+#define DMA_DCR_START_SHIFT 16
+#define DMA_DCR_DSIZE_MASK 0x60000u
+#define DMA_DCR_DSIZE_SHIFT 17
+#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
+#define DMA_DCR_DINC_MASK 0x80000u
+#define DMA_DCR_DINC_SHIFT 19
+#define DMA_DCR_SSIZE_MASK 0x300000u
+#define DMA_DCR_SSIZE_SHIFT 20
+#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
+#define DMA_DCR_SINC_MASK 0x400000u
+#define DMA_DCR_SINC_SHIFT 22
+#define DMA_DCR_EADREQ_MASK 0x800000u
+#define DMA_DCR_EADREQ_SHIFT 23
+#define DMA_DCR_AA_MASK 0x10000000u
+#define DMA_DCR_AA_SHIFT 28
+#define DMA_DCR_CS_MASK 0x20000000u
+#define DMA_DCR_CS_SHIFT 29
+#define DMA_DCR_ERQ_MASK 0x40000000u
+#define DMA_DCR_ERQ_SHIFT 30
+#define DMA_DCR_EINT_MASK 0x80000000u
+#define DMA_DCR_EINT_SHIFT 31
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0 ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASES { DMA0 }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMAMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT 0
+#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK 0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT 6
+#define DMAMUX_CHCFG_ENBL_MASK 0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX0 base address */
+#define DMAMUX0_BASE (0x40021000u)
+/** Peripheral DMAMUX0 base pointer */
+#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASES { DMAMUX0 }
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
+ * @{
+ */
+
+/** FGPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} FGPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FGPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FGPIO_Register_Masks FGPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define FGPIO_PDOR_PDO_SHIFT 0
+#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define FGPIO_PSOR_PTSO_SHIFT 0
+#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define FGPIO_PCOR_PTCO_SHIFT 0
+#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define FGPIO_PTOR_PTTO_SHIFT 0
+#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define FGPIO_PDIR_PDI_SHIFT 0
+#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define FGPIO_PDDR_PDD_SHIFT 0
+#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Register_Masks */
+
+
+/* FGPIO - Peripheral instance base addresses */
+/** Peripheral FPTA base address */
+#define FPTA_BASE (0xF80FF000u)
+/** Peripheral FPTA base pointer */
+#define FPTA ((FGPIO_Type *)FPTA_BASE)
+/** Peripheral FPTB base address */
+#define FPTB_BASE (0xF80FF040u)
+/** Peripheral FPTB base pointer */
+#define FPTB ((FGPIO_Type *)FPTB_BASE)
+/** Peripheral FPTC base address */
+#define FPTC_BASE (0xF80FF080u)
+/** Peripheral FPTC base pointer */
+#define FPTC ((FGPIO_Type *)FPTC_BASE)
+/** Peripheral FPTD base address */
+#define FPTD_BASE (0xF80FF0C0u)
+/** Peripheral FPTD base pointer */
+#define FPTD ((FGPIO_Type *)FPTD_BASE)
+/** Peripheral FPTE base address */
+#define FPTE_BASE (0xF80FF100u)
+/** Peripheral FPTE base pointer */
+#define FPTE ((FGPIO_Type *)FPTE_BASE)
+/** Array initializer of FGPIO peripheral base pointers */
+#define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
+
+/*!
+ * @}
+ */ /* end of group FGPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
+ * @{
+ */
+
+/** FTFA - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
+ __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
+ __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
+ __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
+ __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
+ __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
+ __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
+ __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
+ __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
+ __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
+ __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
+ __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
+ __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
+ __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
+ __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
+ __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
+ __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
+ __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
+ __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
+ __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
+} FTFA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FTFA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFA_Register_Masks FTFA Register Masks
+ * @{
+ */
+
+/* FSTAT Bit Fields */
+#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
+#define FTFA_FSTAT_MGSTAT0_SHIFT 0
+#define FTFA_FSTAT_FPVIOL_MASK 0x10u
+#define FTFA_FSTAT_FPVIOL_SHIFT 4
+#define FTFA_FSTAT_ACCERR_MASK 0x20u
+#define FTFA_FSTAT_ACCERR_SHIFT 5
+#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
+#define FTFA_FSTAT_RDCOLERR_SHIFT 6
+#define FTFA_FSTAT_CCIF_MASK 0x80u
+#define FTFA_FSTAT_CCIF_SHIFT 7
+/* FCNFG Bit Fields */
+#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
+#define FTFA_FCNFG_ERSSUSP_SHIFT 4
+#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
+#define FTFA_FCNFG_ERSAREQ_SHIFT 5
+#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
+#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
+#define FTFA_FCNFG_CCIE_MASK 0x80u
+#define FTFA_FCNFG_CCIE_SHIFT 7
+/* FSEC Bit Fields */
+#define FTFA_FSEC_SEC_MASK 0x3u
+#define FTFA_FSEC_SEC_SHIFT 0
+#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
+#define FTFA_FSEC_FSLACC_MASK 0xCu
+#define FTFA_FSEC_FSLACC_SHIFT 2
+#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
+#define FTFA_FSEC_MEEN_MASK 0x30u
+#define FTFA_FSEC_MEEN_SHIFT 4
+#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
+#define FTFA_FSEC_KEYEN_MASK 0xC0u
+#define FTFA_FSEC_KEYEN_SHIFT 6
+#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFA_FOPT_OPT_MASK 0xFFu
+#define FTFA_FOPT_OPT_SHIFT 0
+#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB3_CCOBn_SHIFT 0
+#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB2_CCOBn_SHIFT 0
+#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB1_CCOBn_SHIFT 0
+#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB0_CCOBn_SHIFT 0
+#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB7_CCOBn_SHIFT 0
+#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB6_CCOBn_SHIFT 0
+#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB5_CCOBn_SHIFT 0
+#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB4_CCOBn_SHIFT 0
+#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBB_CCOBn_SHIFT 0
+#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
+#define FTFA_FCCOBA_CCOBn_SHIFT 0
+#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB9_CCOBn_SHIFT 0
+#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
+#define FTFA_FCCOB8_CCOBn_SHIFT 0
+#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFA_FPROT3_PROT_MASK 0xFFu
+#define FTFA_FPROT3_PROT_SHIFT 0
+#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFA_FPROT2_PROT_MASK 0xFFu
+#define FTFA_FPROT2_PROT_SHIFT 0
+#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFA_FPROT1_PROT_MASK 0xFFu
+#define FTFA_FPROT1_PROT_SHIFT 0
+#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFA_FPROT0_PROT_MASK 0xFFu
+#define FTFA_FPROT0_PROT_SHIFT 0
+#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
+
+/*!
+ * @}
+ */ /* end of group FTFA_Register_Masks */
+
+
+/* FTFA - Peripheral instance base addresses */
+/** Peripheral FTFA base address */
+#define FTFA_BASE (0x40020000u)
+/** Peripheral FTFA base pointer */
+#define FTFA ((FTFA_Type *)FTFA_BASE)
+/** Array initializer of FTFA peripheral base pointers */
+#define FTFA_BASES { FTFA }
+
+/*!
+ * @}
+ */ /* end of group FTFA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
+ __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
+ __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
+ __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
+ __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
+ __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT 0
+#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT 0
+#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT 0
+#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT 0
+#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT 0
+#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT 0
+#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral PTA base address */
+#define PTA_BASE (0x400FF000u)
+/** Peripheral PTA base pointer */
+#define PTA ((GPIO_Type *)PTA_BASE)
+/** Peripheral PTB base address */
+#define PTB_BASE (0x400FF040u)
+/** Peripheral PTB base pointer */
+#define PTB ((GPIO_Type *)PTB_BASE)
+/** Peripheral PTC base address */
+#define PTC_BASE (0x400FF080u)
+/** Peripheral PTC base pointer */
+#define PTC ((GPIO_Type *)PTC_BASE)
+/** Peripheral PTD base address */
+#define PTD_BASE (0x400FF0C0u)
+/** Peripheral PTD base pointer */
+#define PTD ((GPIO_Type *)PTD_BASE)
+/** Peripheral PTE base address */
+#define PTE_BASE (0x400FF100u)
+/** Peripheral PTE base pointer */
+#define PTE ((GPIO_Type *)PTE_BASE)
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
+ __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
+ __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
+ __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
+ __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
+ __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
+ __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+ __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
+ __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
+ __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
+ __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
+ __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK 0xFEu
+#define I2C_A1_AD_SHIFT 1
+#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK 0x3Fu
+#define I2C_F_ICR_SHIFT 0
+#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK 0xC0u
+#define I2C_F_MULT_SHIFT 6
+#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK 0x1u
+#define I2C_C1_DMAEN_SHIFT 0
+#define I2C_C1_WUEN_MASK 0x2u
+#define I2C_C1_WUEN_SHIFT 1
+#define I2C_C1_RSTA_MASK 0x4u
+#define I2C_C1_RSTA_SHIFT 2
+#define I2C_C1_TXAK_MASK 0x8u
+#define I2C_C1_TXAK_SHIFT 3
+#define I2C_C1_TX_MASK 0x10u
+#define I2C_C1_TX_SHIFT 4
+#define I2C_C1_MST_MASK 0x20u
+#define I2C_C1_MST_SHIFT 5
+#define I2C_C1_IICIE_MASK 0x40u
+#define I2C_C1_IICIE_SHIFT 6
+#define I2C_C1_IICEN_MASK 0x80u
+#define I2C_C1_IICEN_SHIFT 7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK 0x1u
+#define I2C_S_RXAK_SHIFT 0
+#define I2C_S_IICIF_MASK 0x2u
+#define I2C_S_IICIF_SHIFT 1
+#define I2C_S_SRW_MASK 0x4u
+#define I2C_S_SRW_SHIFT 2
+#define I2C_S_RAM_MASK 0x8u
+#define I2C_S_RAM_SHIFT 3
+#define I2C_S_ARBL_MASK 0x10u
+#define I2C_S_ARBL_SHIFT 4
+#define I2C_S_BUSY_MASK 0x20u
+#define I2C_S_BUSY_SHIFT 5
+#define I2C_S_IAAS_MASK 0x40u
+#define I2C_S_IAAS_SHIFT 6
+#define I2C_S_TCF_MASK 0x80u
+#define I2C_S_TCF_SHIFT 7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK 0xFFu
+#define I2C_D_DATA_SHIFT 0
+#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK 0x7u
+#define I2C_C2_AD_SHIFT 0
+#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK 0x8u
+#define I2C_C2_RMEN_SHIFT 3
+#define I2C_C2_SBRC_MASK 0x10u
+#define I2C_C2_SBRC_SHIFT 4
+#define I2C_C2_HDRS_MASK 0x20u
+#define I2C_C2_HDRS_SHIFT 5
+#define I2C_C2_ADEXT_MASK 0x40u
+#define I2C_C2_ADEXT_SHIFT 6
+#define I2C_C2_GCAEN_MASK 0x80u
+#define I2C_C2_GCAEN_SHIFT 7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK 0x1Fu
+#define I2C_FLT_FLT_SHIFT 0
+#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+#define I2C_FLT_STOPIE_MASK 0x20u
+#define I2C_FLT_STOPIE_SHIFT 5
+#define I2C_FLT_STOPF_MASK 0x40u
+#define I2C_FLT_STOPF_SHIFT 6
+#define I2C_FLT_SHEN_MASK 0x80u
+#define I2C_FLT_SHEN_SHIFT 7
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK 0xFEu
+#define I2C_RA_RAD_SHIFT 1
+#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK 0x1u
+#define I2C_SMB_SHTF2IE_SHIFT 0
+#define I2C_SMB_SHTF2_MASK 0x2u
+#define I2C_SMB_SHTF2_SHIFT 1
+#define I2C_SMB_SHTF1_MASK 0x4u
+#define I2C_SMB_SHTF1_SHIFT 2
+#define I2C_SMB_SLTF_MASK 0x8u
+#define I2C_SMB_SLTF_SHIFT 3
+#define I2C_SMB_TCKSEL_MASK 0x10u
+#define I2C_SMB_TCKSEL_SHIFT 4
+#define I2C_SMB_SIICAEN_MASK 0x20u
+#define I2C_SMB_SIICAEN_SHIFT 5
+#define I2C_SMB_ALERTEN_MASK 0x40u
+#define I2C_SMB_ALERTEN_SHIFT 6
+#define I2C_SMB_FACK_MASK 0x80u
+#define I2C_SMB_FACK_SHIFT 7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK 0xFEu
+#define I2C_A2_SAD_SHIFT 1
+#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK 0xFFu
+#define I2C_SLTH_SSLT_SHIFT 0
+#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK 0xFFu
+#define I2C_SLTL_SSLT_SHIFT 0
+#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASES { I2C0, I2C1 }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+ __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+ __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+ __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+ uint8_t RESERVED_1[8];
+ __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_2[60];
+ __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
+ uint8_t RESERVED_3[28];
+ __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+ __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+ __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+ __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+ uint8_t RESERVED_5[8];
+ __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_6[60];
+ __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
+ uint8_t RESERVED_7[28];
+ __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
+ __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/* TCSR Bit Fields */
+#define I2S_TCSR_FWDE_MASK 0x2u
+#define I2S_TCSR_FWDE_SHIFT 1
+#define I2S_TCSR_FWIE_MASK 0x200u
+#define I2S_TCSR_FWIE_SHIFT 9
+#define I2S_TCSR_FEIE_MASK 0x400u
+#define I2S_TCSR_FEIE_SHIFT 10
+#define I2S_TCSR_SEIE_MASK 0x800u
+#define I2S_TCSR_SEIE_SHIFT 11
+#define I2S_TCSR_WSIE_MASK 0x1000u
+#define I2S_TCSR_WSIE_SHIFT 12
+#define I2S_TCSR_FWF_MASK 0x20000u
+#define I2S_TCSR_FWF_SHIFT 17
+#define I2S_TCSR_FEF_MASK 0x40000u
+#define I2S_TCSR_FEF_SHIFT 18
+#define I2S_TCSR_SEF_MASK 0x80000u
+#define I2S_TCSR_SEF_SHIFT 19
+#define I2S_TCSR_WSF_MASK 0x100000u
+#define I2S_TCSR_WSF_SHIFT 20
+#define I2S_TCSR_SR_MASK 0x1000000u
+#define I2S_TCSR_SR_SHIFT 24
+#define I2S_TCSR_FR_MASK 0x2000000u
+#define I2S_TCSR_FR_SHIFT 25
+#define I2S_TCSR_BCE_MASK 0x10000000u
+#define I2S_TCSR_BCE_SHIFT 28
+#define I2S_TCSR_DBGE_MASK 0x20000000u
+#define I2S_TCSR_DBGE_SHIFT 29
+#define I2S_TCSR_STOPE_MASK 0x40000000u
+#define I2S_TCSR_STOPE_SHIFT 30
+#define I2S_TCSR_TE_MASK 0x80000000u
+#define I2S_TCSR_TE_SHIFT 31
+/* TCR2 Bit Fields */
+#define I2S_TCR2_DIV_MASK 0xFFu
+#define I2S_TCR2_DIV_SHIFT 0
+#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK 0x1000000u
+#define I2S_TCR2_BCD_SHIFT 24
+#define I2S_TCR2_BCP_MASK 0x2000000u
+#define I2S_TCR2_BCP_SHIFT 25
+#define I2S_TCR2_CLKMODE_MASK 0xC000000u
+#define I2S_TCR2_CLKMODE_SHIFT 26
+#define I2S_TCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_CLKMODE_SHIFT))&I2S_TCR2_CLKMODE_MASK)
+/* TCR3 Bit Fields */
+#define I2S_TCR3_WDFL_MASK 0x1u
+#define I2S_TCR3_WDFL_SHIFT 0
+#define I2S_TCR3_TCE_MASK 0x10000u
+#define I2S_TCR3_TCE_SHIFT 16
+/* TCR4 Bit Fields */
+#define I2S_TCR4_FSD_MASK 0x1u
+#define I2S_TCR4_FSD_SHIFT 0
+#define I2S_TCR4_FSP_MASK 0x2u
+#define I2S_TCR4_FSP_SHIFT 1
+#define I2S_TCR4_FSE_MASK 0x8u
+#define I2S_TCR4_FSE_SHIFT 3
+#define I2S_TCR4_MF_MASK 0x10u
+#define I2S_TCR4_MF_SHIFT 4
+#define I2S_TCR4_SYWD_MASK 0x1F00u
+#define I2S_TCR4_SYWD_SHIFT 8
+#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK 0x10000u
+#define I2S_TCR4_FRSZ_SHIFT 16
+/* TCR5 Bit Fields */
+#define I2S_TCR5_FBT_MASK 0x1F00u
+#define I2S_TCR5_FBT_SHIFT 8
+#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK 0x1F0000u
+#define I2S_TCR5_W0W_SHIFT 16
+#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK 0x1F000000u
+#define I2S_TCR5_WNW_SHIFT 24
+#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
+/* TDR Bit Fields */
+#define I2S_TDR_TDR_MASK 0xFFFFFFFFu
+#define I2S_TDR_TDR_SHIFT 0
+#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
+/* TMR Bit Fields */
+#define I2S_TMR_TWM_MASK 0x3u
+#define I2S_TMR_TWM_SHIFT 0
+#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
+/* RCSR Bit Fields */
+#define I2S_RCSR_FWDE_MASK 0x2u
+#define I2S_RCSR_FWDE_SHIFT 1
+#define I2S_RCSR_FWIE_MASK 0x200u
+#define I2S_RCSR_FWIE_SHIFT 9
+#define I2S_RCSR_FEIE_MASK 0x400u
+#define I2S_RCSR_FEIE_SHIFT 10
+#define I2S_RCSR_SEIE_MASK 0x800u
+#define I2S_RCSR_SEIE_SHIFT 11
+#define I2S_RCSR_WSIE_MASK 0x1000u
+#define I2S_RCSR_WSIE_SHIFT 12
+#define I2S_RCSR_FWF_MASK 0x20000u
+#define I2S_RCSR_FWF_SHIFT 17
+#define I2S_RCSR_FEF_MASK 0x40000u
+#define I2S_RCSR_FEF_SHIFT 18
+#define I2S_RCSR_SEF_MASK 0x80000u
+#define I2S_RCSR_SEF_SHIFT 19
+#define I2S_RCSR_WSF_MASK 0x100000u
+#define I2S_RCSR_WSF_SHIFT 20
+#define I2S_RCSR_SR_MASK 0x1000000u
+#define I2S_RCSR_SR_SHIFT 24
+#define I2S_RCSR_FR_MASK 0x2000000u
+#define I2S_RCSR_FR_SHIFT 25
+#define I2S_RCSR_BCE_MASK 0x10000000u
+#define I2S_RCSR_BCE_SHIFT 28
+#define I2S_RCSR_DBGE_MASK 0x20000000u
+#define I2S_RCSR_DBGE_SHIFT 29
+#define I2S_RCSR_STOPE_MASK 0x40000000u
+#define I2S_RCSR_STOPE_SHIFT 30
+#define I2S_RCSR_RE_MASK 0x80000000u
+#define I2S_RCSR_RE_SHIFT 31
+/* RCR2 Bit Fields */
+#define I2S_RCR2_DIV_MASK 0xFFu
+#define I2S_RCR2_DIV_SHIFT 0
+#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK 0x1000000u
+#define I2S_RCR2_BCD_SHIFT 24
+#define I2S_RCR2_BCP_MASK 0x2000000u
+#define I2S_RCR2_BCP_SHIFT 25
+#define I2S_RCR2_CLKMODE_MASK 0xC000000u
+#define I2S_RCR2_CLKMODE_SHIFT 26
+#define I2S_RCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_CLKMODE_SHIFT))&I2S_RCR2_CLKMODE_MASK)
+/* RCR3 Bit Fields */
+#define I2S_RCR3_WDFL_MASK 0x1u
+#define I2S_RCR3_WDFL_SHIFT 0
+#define I2S_RCR3_RCE_MASK 0x10000u
+#define I2S_RCR3_RCE_SHIFT 16
+/* RCR4 Bit Fields */
+#define I2S_RCR4_FSD_MASK 0x1u
+#define I2S_RCR4_FSD_SHIFT 0
+#define I2S_RCR4_FSP_MASK 0x2u
+#define I2S_RCR4_FSP_SHIFT 1
+#define I2S_RCR4_FSE_MASK 0x8u
+#define I2S_RCR4_FSE_SHIFT 3
+#define I2S_RCR4_MF_MASK 0x10u
+#define I2S_RCR4_MF_SHIFT 4
+#define I2S_RCR4_SYWD_MASK 0x1F00u
+#define I2S_RCR4_SYWD_SHIFT 8
+#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK 0x10000u
+#define I2S_RCR4_FRSZ_SHIFT 16
+/* RCR5 Bit Fields */
+#define I2S_RCR5_FBT_MASK 0x1F00u
+#define I2S_RCR5_FBT_SHIFT 8
+#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK 0x1F0000u
+#define I2S_RCR5_W0W_SHIFT 16
+#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK 0x1F000000u
+#define I2S_RCR5_WNW_SHIFT 24
+#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
+/* RDR Bit Fields */
+#define I2S_RDR_RDR_MASK 0xFFFFFFFFu
+#define I2S_RDR_RDR_SHIFT 0
+#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
+/* RMR Bit Fields */
+#define I2S_RMR_RWM_MASK 0x3u
+#define I2S_RMR_RWM_SHIFT 0
+#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
+/* MCR Bit Fields */
+#define I2S_MCR_MICS_MASK 0x3000000u
+#define I2S_MCR_MICS_SHIFT 24
+#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK 0x40000000u
+#define I2S_MCR_MOE_SHIFT 30
+#define I2S_MCR_DUF_MASK 0x80000000u
+#define I2S_MCR_DUF_SHIFT 31
+/* MDR Bit Fields */
+#define I2S_MDR_DIVIDE_MASK 0xFFFu
+#define I2S_MDR_DIVIDE_SHIFT 0
+#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK 0xFF000u
+#define I2S_MDR_FRACT_SHIFT 12
+#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASES { I2S0 }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
+ * @{
+ */
+
+/** LCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */
+ __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */
+ __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */
+ __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */
+ __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
+ union { /* offset: 0x20 */
+ __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
+ __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
+ };
+} LCD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Register_Masks LCD Register Masks
+ * @{
+ */
+
+/* GCR Bit Fields */
+#define LCD_GCR_DUTY_MASK 0x7u
+#define LCD_GCR_DUTY_SHIFT 0
+#define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
+#define LCD_GCR_LCLK_MASK 0x38u
+#define LCD_GCR_LCLK_SHIFT 3
+#define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
+#define LCD_GCR_SOURCE_MASK 0x40u
+#define LCD_GCR_SOURCE_SHIFT 6
+#define LCD_GCR_LCDEN_MASK 0x80u
+#define LCD_GCR_LCDEN_SHIFT 7
+#define LCD_GCR_LCDSTP_MASK 0x100u
+#define LCD_GCR_LCDSTP_SHIFT 8
+#define LCD_GCR_LCDDOZE_MASK 0x200u
+#define LCD_GCR_LCDDOZE_SHIFT 9
+#define LCD_GCR_FFR_MASK 0x400u
+#define LCD_GCR_FFR_SHIFT 10
+#define LCD_GCR_ALTSOURCE_MASK 0x800u
+#define LCD_GCR_ALTSOURCE_SHIFT 11
+#define LCD_GCR_ALTDIV_MASK 0x3000u
+#define LCD_GCR_ALTDIV_SHIFT 12
+#define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
+#define LCD_GCR_FDCIEN_MASK 0x4000u
+#define LCD_GCR_FDCIEN_SHIFT 14
+#define LCD_GCR_PADSAFE_MASK 0x8000u
+#define LCD_GCR_PADSAFE_SHIFT 15
+#define LCD_GCR_VSUPPLY_MASK 0x20000u
+#define LCD_GCR_VSUPPLY_SHIFT 17
+#define LCD_GCR_LADJ_MASK 0x300000u
+#define LCD_GCR_LADJ_SHIFT 20
+#define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
+#define LCD_GCR_CPSEL_MASK 0x800000u
+#define LCD_GCR_CPSEL_SHIFT 23
+#define LCD_GCR_RVTRIM_MASK 0xF000000u
+#define LCD_GCR_RVTRIM_SHIFT 24
+#define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
+#define LCD_GCR_RVEN_MASK 0x80000000u
+#define LCD_GCR_RVEN_SHIFT 31
+/* AR Bit Fields */
+#define LCD_AR_BRATE_MASK 0x7u
+#define LCD_AR_BRATE_SHIFT 0
+#define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
+#define LCD_AR_BMODE_MASK 0x8u
+#define LCD_AR_BMODE_SHIFT 3
+#define LCD_AR_BLANK_MASK 0x20u
+#define LCD_AR_BLANK_SHIFT 5
+#define LCD_AR_ALT_MASK 0x40u
+#define LCD_AR_ALT_SHIFT 6
+#define LCD_AR_BLINK_MASK 0x80u
+#define LCD_AR_BLINK_SHIFT 7
+/* FDCR Bit Fields */
+#define LCD_FDCR_FDPINID_MASK 0x3Fu
+#define LCD_FDCR_FDPINID_SHIFT 0
+#define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
+#define LCD_FDCR_FDBPEN_MASK 0x40u
+#define LCD_FDCR_FDBPEN_SHIFT 6
+#define LCD_FDCR_FDEN_MASK 0x80u
+#define LCD_FDCR_FDEN_SHIFT 7
+#define LCD_FDCR_FDSWW_MASK 0xE00u
+#define LCD_FDCR_FDSWW_SHIFT 9
+#define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
+#define LCD_FDCR_FDPRS_MASK 0x7000u
+#define LCD_FDCR_FDPRS_SHIFT 12
+#define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
+/* FDSR Bit Fields */
+#define LCD_FDSR_FDCNT_MASK 0xFFu
+#define LCD_FDSR_FDCNT_SHIFT 0
+#define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
+#define LCD_FDSR_FDCF_MASK 0x8000u
+#define LCD_FDSR_FDCF_SHIFT 15
+/* PEN Bit Fields */
+#define LCD_PEN_PEN_MASK 0xFFFFFFFFu
+#define LCD_PEN_PEN_SHIFT 0
+#define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
+/* BPEN Bit Fields */
+#define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
+#define LCD_BPEN_BPEN_SHIFT 0
+#define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
+/* WF Bit Fields */
+#define LCD_WF_WF0_MASK 0xFFu
+#define LCD_WF_WF0_SHIFT 0
+#define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
+#define LCD_WF_WF60_MASK 0xFFu
+#define LCD_WF_WF60_SHIFT 0
+#define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
+#define LCD_WF_WF56_MASK 0xFFu
+#define LCD_WF_WF56_SHIFT 0
+#define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
+#define LCD_WF_WF52_MASK 0xFFu
+#define LCD_WF_WF52_SHIFT 0
+#define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
+#define LCD_WF_WF4_MASK 0xFFu
+#define LCD_WF_WF4_SHIFT 0
+#define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
+#define LCD_WF_WF48_MASK 0xFFu
+#define LCD_WF_WF48_SHIFT 0
+#define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
+#define LCD_WF_WF44_MASK 0xFFu
+#define LCD_WF_WF44_SHIFT 0
+#define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
+#define LCD_WF_WF40_MASK 0xFFu
+#define LCD_WF_WF40_SHIFT 0
+#define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
+#define LCD_WF_WF8_MASK 0xFFu
+#define LCD_WF_WF8_SHIFT 0
+#define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
+#define LCD_WF_WF36_MASK 0xFFu
+#define LCD_WF_WF36_SHIFT 0
+#define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
+#define LCD_WF_WF32_MASK 0xFFu
+#define LCD_WF_WF32_SHIFT 0
+#define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
+#define LCD_WF_WF28_MASK 0xFFu
+#define LCD_WF_WF28_SHIFT 0
+#define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
+#define LCD_WF_WF12_MASK 0xFFu
+#define LCD_WF_WF12_SHIFT 0
+#define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
+#define LCD_WF_WF24_MASK 0xFFu
+#define LCD_WF_WF24_SHIFT 0
+#define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
+#define LCD_WF_WF20_MASK 0xFFu
+#define LCD_WF_WF20_SHIFT 0
+#define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
+#define LCD_WF_WF16_MASK 0xFFu
+#define LCD_WF_WF16_SHIFT 0
+#define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
+#define LCD_WF_WF5_MASK 0xFF00u
+#define LCD_WF_WF5_SHIFT 8
+#define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
+#define LCD_WF_WF49_MASK 0xFF00u
+#define LCD_WF_WF49_SHIFT 8
+#define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
+#define LCD_WF_WF45_MASK 0xFF00u
+#define LCD_WF_WF45_SHIFT 8
+#define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
+#define LCD_WF_WF61_MASK 0xFF00u
+#define LCD_WF_WF61_SHIFT 8
+#define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
+#define LCD_WF_WF25_MASK 0xFF00u
+#define LCD_WF_WF25_SHIFT 8
+#define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
+#define LCD_WF_WF17_MASK 0xFF00u
+#define LCD_WF_WF17_SHIFT 8
+#define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
+#define LCD_WF_WF41_MASK 0xFF00u
+#define LCD_WF_WF41_SHIFT 8
+#define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
+#define LCD_WF_WF13_MASK 0xFF00u
+#define LCD_WF_WF13_SHIFT 8
+#define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
+#define LCD_WF_WF57_MASK 0xFF00u
+#define LCD_WF_WF57_SHIFT 8
+#define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
+#define LCD_WF_WF53_MASK 0xFF00u
+#define LCD_WF_WF53_SHIFT 8
+#define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
+#define LCD_WF_WF37_MASK 0xFF00u
+#define LCD_WF_WF37_SHIFT 8
+#define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
+#define LCD_WF_WF9_MASK 0xFF00u
+#define LCD_WF_WF9_SHIFT 8
+#define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
+#define LCD_WF_WF1_MASK 0xFF00u
+#define LCD_WF_WF1_SHIFT 8
+#define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
+#define LCD_WF_WF29_MASK 0xFF00u
+#define LCD_WF_WF29_SHIFT 8
+#define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
+#define LCD_WF_WF33_MASK 0xFF00u
+#define LCD_WF_WF33_SHIFT 8
+#define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
+#define LCD_WF_WF21_MASK 0xFF00u
+#define LCD_WF_WF21_SHIFT 8
+#define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
+#define LCD_WF_WF26_MASK 0xFF0000u
+#define LCD_WF_WF26_SHIFT 16
+#define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
+#define LCD_WF_WF46_MASK 0xFF0000u
+#define LCD_WF_WF46_SHIFT 16
+#define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
+#define LCD_WF_WF6_MASK 0xFF0000u
+#define LCD_WF_WF6_SHIFT 16
+#define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
+#define LCD_WF_WF42_MASK 0xFF0000u
+#define LCD_WF_WF42_SHIFT 16
+#define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
+#define LCD_WF_WF18_MASK 0xFF0000u
+#define LCD_WF_WF18_SHIFT 16
+#define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
+#define LCD_WF_WF38_MASK 0xFF0000u
+#define LCD_WF_WF38_SHIFT 16
+#define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
+#define LCD_WF_WF22_MASK 0xFF0000u
+#define LCD_WF_WF22_SHIFT 16
+#define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
+#define LCD_WF_WF34_MASK 0xFF0000u
+#define LCD_WF_WF34_SHIFT 16
+#define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
+#define LCD_WF_WF50_MASK 0xFF0000u
+#define LCD_WF_WF50_SHIFT 16
+#define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
+#define LCD_WF_WF14_MASK 0xFF0000u
+#define LCD_WF_WF14_SHIFT 16
+#define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
+#define LCD_WF_WF54_MASK 0xFF0000u
+#define LCD_WF_WF54_SHIFT 16
+#define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
+#define LCD_WF_WF2_MASK 0xFF0000u
+#define LCD_WF_WF2_SHIFT 16
+#define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
+#define LCD_WF_WF58_MASK 0xFF0000u
+#define LCD_WF_WF58_SHIFT 16
+#define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
+#define LCD_WF_WF30_MASK 0xFF0000u
+#define LCD_WF_WF30_SHIFT 16
+#define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
+#define LCD_WF_WF62_MASK 0xFF0000u
+#define LCD_WF_WF62_SHIFT 16
+#define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
+#define LCD_WF_WF10_MASK 0xFF0000u
+#define LCD_WF_WF10_SHIFT 16
+#define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
+#define LCD_WF_WF63_MASK 0xFF000000u
+#define LCD_WF_WF63_SHIFT 24
+#define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
+#define LCD_WF_WF59_MASK 0xFF000000u
+#define LCD_WF_WF59_SHIFT 24
+#define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
+#define LCD_WF_WF55_MASK 0xFF000000u
+#define LCD_WF_WF55_SHIFT 24
+#define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
+#define LCD_WF_WF3_MASK 0xFF000000u
+#define LCD_WF_WF3_SHIFT 24
+#define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
+#define LCD_WF_WF51_MASK 0xFF000000u
+#define LCD_WF_WF51_SHIFT 24
+#define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
+#define LCD_WF_WF47_MASK 0xFF000000u
+#define LCD_WF_WF47_SHIFT 24
+#define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
+#define LCD_WF_WF43_MASK 0xFF000000u
+#define LCD_WF_WF43_SHIFT 24
+#define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
+#define LCD_WF_WF7_MASK 0xFF000000u
+#define LCD_WF_WF7_SHIFT 24
+#define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
+#define LCD_WF_WF39_MASK 0xFF000000u
+#define LCD_WF_WF39_SHIFT 24
+#define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
+#define LCD_WF_WF35_MASK 0xFF000000u
+#define LCD_WF_WF35_SHIFT 24
+#define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
+#define LCD_WF_WF31_MASK 0xFF000000u
+#define LCD_WF_WF31_SHIFT 24
+#define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
+#define LCD_WF_WF11_MASK 0xFF000000u
+#define LCD_WF_WF11_SHIFT 24
+#define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
+#define LCD_WF_WF27_MASK 0xFF000000u
+#define LCD_WF_WF27_SHIFT 24
+#define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
+#define LCD_WF_WF23_MASK 0xFF000000u
+#define LCD_WF_WF23_SHIFT 24
+#define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
+#define LCD_WF_WF19_MASK 0xFF000000u
+#define LCD_WF_WF19_SHIFT 24
+#define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
+#define LCD_WF_WF15_MASK 0xFF000000u
+#define LCD_WF_WF15_SHIFT 24
+#define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
+/* WF8B Bit Fields */
+#define LCD_WF8B_BPALCD0_MASK 0x1u
+#define LCD_WF8B_BPALCD0_SHIFT 0
+#define LCD_WF8B_BPALCD63_MASK 0x1u
+#define LCD_WF8B_BPALCD63_SHIFT 0
+#define LCD_WF8B_BPALCD62_MASK 0x1u
+#define LCD_WF8B_BPALCD62_SHIFT 0
+#define LCD_WF8B_BPALCD61_MASK 0x1u
+#define LCD_WF8B_BPALCD61_SHIFT 0
+#define LCD_WF8B_BPALCD60_MASK 0x1u
+#define LCD_WF8B_BPALCD60_SHIFT 0
+#define LCD_WF8B_BPALCD59_MASK 0x1u
+#define LCD_WF8B_BPALCD59_SHIFT 0
+#define LCD_WF8B_BPALCD58_MASK 0x1u
+#define LCD_WF8B_BPALCD58_SHIFT 0
+#define LCD_WF8B_BPALCD57_MASK 0x1u
+#define LCD_WF8B_BPALCD57_SHIFT 0
+#define LCD_WF8B_BPALCD1_MASK 0x1u
+#define LCD_WF8B_BPALCD1_SHIFT 0
+#define LCD_WF8B_BPALCD56_MASK 0x1u
+#define LCD_WF8B_BPALCD56_SHIFT 0
+#define LCD_WF8B_BPALCD55_MASK 0x1u
+#define LCD_WF8B_BPALCD55_SHIFT 0
+#define LCD_WF8B_BPALCD54_MASK 0x1u
+#define LCD_WF8B_BPALCD54_SHIFT 0
+#define LCD_WF8B_BPALCD53_MASK 0x1u
+#define LCD_WF8B_BPALCD53_SHIFT 0
+#define LCD_WF8B_BPALCD52_MASK 0x1u
+#define LCD_WF8B_BPALCD52_SHIFT 0
+#define LCD_WF8B_BPALCD51_MASK 0x1u
+#define LCD_WF8B_BPALCD51_SHIFT 0
+#define LCD_WF8B_BPALCD50_MASK 0x1u
+#define LCD_WF8B_BPALCD50_SHIFT 0
+#define LCD_WF8B_BPALCD2_MASK 0x1u
+#define LCD_WF8B_BPALCD2_SHIFT 0
+#define LCD_WF8B_BPALCD49_MASK 0x1u
+#define LCD_WF8B_BPALCD49_SHIFT 0
+#define LCD_WF8B_BPALCD48_MASK 0x1u
+#define LCD_WF8B_BPALCD48_SHIFT 0
+#define LCD_WF8B_BPALCD47_MASK 0x1u
+#define LCD_WF8B_BPALCD47_SHIFT 0
+#define LCD_WF8B_BPALCD46_MASK 0x1u
+#define LCD_WF8B_BPALCD46_SHIFT 0
+#define LCD_WF8B_BPALCD45_MASK 0x1u
+#define LCD_WF8B_BPALCD45_SHIFT 0
+#define LCD_WF8B_BPALCD44_MASK 0x1u
+#define LCD_WF8B_BPALCD44_SHIFT 0
+#define LCD_WF8B_BPALCD43_MASK 0x1u
+#define LCD_WF8B_BPALCD43_SHIFT 0
+#define LCD_WF8B_BPALCD3_MASK 0x1u
+#define LCD_WF8B_BPALCD3_SHIFT 0
+#define LCD_WF8B_BPALCD42_MASK 0x1u
+#define LCD_WF8B_BPALCD42_SHIFT 0
+#define LCD_WF8B_BPALCD41_MASK 0x1u
+#define LCD_WF8B_BPALCD41_SHIFT 0
+#define LCD_WF8B_BPALCD40_MASK 0x1u
+#define LCD_WF8B_BPALCD40_SHIFT 0
+#define LCD_WF8B_BPALCD39_MASK 0x1u
+#define LCD_WF8B_BPALCD39_SHIFT 0
+#define LCD_WF8B_BPALCD38_MASK 0x1u
+#define LCD_WF8B_BPALCD38_SHIFT 0
+#define LCD_WF8B_BPALCD37_MASK 0x1u
+#define LCD_WF8B_BPALCD37_SHIFT 0
+#define LCD_WF8B_BPALCD36_MASK 0x1u
+#define LCD_WF8B_BPALCD36_SHIFT 0
+#define LCD_WF8B_BPALCD4_MASK 0x1u
+#define LCD_WF8B_BPALCD4_SHIFT 0
+#define LCD_WF8B_BPALCD35_MASK 0x1u
+#define LCD_WF8B_BPALCD35_SHIFT 0
+#define LCD_WF8B_BPALCD34_MASK 0x1u
+#define LCD_WF8B_BPALCD34_SHIFT 0
+#define LCD_WF8B_BPALCD33_MASK 0x1u
+#define LCD_WF8B_BPALCD33_SHIFT 0
+#define LCD_WF8B_BPALCD32_MASK 0x1u
+#define LCD_WF8B_BPALCD32_SHIFT 0
+#define LCD_WF8B_BPALCD31_MASK 0x1u
+#define LCD_WF8B_BPALCD31_SHIFT 0
+#define LCD_WF8B_BPALCD30_MASK 0x1u
+#define LCD_WF8B_BPALCD30_SHIFT 0
+#define LCD_WF8B_BPALCD29_MASK 0x1u
+#define LCD_WF8B_BPALCD29_SHIFT 0
+#define LCD_WF8B_BPALCD5_MASK 0x1u
+#define LCD_WF8B_BPALCD5_SHIFT 0
+#define LCD_WF8B_BPALCD28_MASK 0x1u
+#define LCD_WF8B_BPALCD28_SHIFT 0
+#define LCD_WF8B_BPALCD27_MASK 0x1u
+#define LCD_WF8B_BPALCD27_SHIFT 0
+#define LCD_WF8B_BPALCD26_MASK 0x1u
+#define LCD_WF8B_BPALCD26_SHIFT 0
+#define LCD_WF8B_BPALCD25_MASK 0x1u
+#define LCD_WF8B_BPALCD25_SHIFT 0
+#define LCD_WF8B_BPALCD24_MASK 0x1u
+#define LCD_WF8B_BPALCD24_SHIFT 0
+#define LCD_WF8B_BPALCD23_MASK 0x1u
+#define LCD_WF8B_BPALCD23_SHIFT 0
+#define LCD_WF8B_BPALCD22_MASK 0x1u
+#define LCD_WF8B_BPALCD22_SHIFT 0
+#define LCD_WF8B_BPALCD6_MASK 0x1u
+#define LCD_WF8B_BPALCD6_SHIFT 0
+#define LCD_WF8B_BPALCD21_MASK 0x1u
+#define LCD_WF8B_BPALCD21_SHIFT 0
+#define LCD_WF8B_BPALCD20_MASK 0x1u
+#define LCD_WF8B_BPALCD20_SHIFT 0
+#define LCD_WF8B_BPALCD19_MASK 0x1u
+#define LCD_WF8B_BPALCD19_SHIFT 0
+#define LCD_WF8B_BPALCD18_MASK 0x1u
+#define LCD_WF8B_BPALCD18_SHIFT 0
+#define LCD_WF8B_BPALCD17_MASK 0x1u
+#define LCD_WF8B_BPALCD17_SHIFT 0
+#define LCD_WF8B_BPALCD16_MASK 0x1u
+#define LCD_WF8B_BPALCD16_SHIFT 0
+#define LCD_WF8B_BPALCD15_MASK 0x1u
+#define LCD_WF8B_BPALCD15_SHIFT 0
+#define LCD_WF8B_BPALCD7_MASK 0x1u
+#define LCD_WF8B_BPALCD7_SHIFT 0
+#define LCD_WF8B_BPALCD14_MASK 0x1u
+#define LCD_WF8B_BPALCD14_SHIFT 0
+#define LCD_WF8B_BPALCD13_MASK 0x1u
+#define LCD_WF8B_BPALCD13_SHIFT 0
+#define LCD_WF8B_BPALCD12_MASK 0x1u
+#define LCD_WF8B_BPALCD12_SHIFT 0
+#define LCD_WF8B_BPALCD11_MASK 0x1u
+#define LCD_WF8B_BPALCD11_SHIFT 0
+#define LCD_WF8B_BPALCD10_MASK 0x1u
+#define LCD_WF8B_BPALCD10_SHIFT 0
+#define LCD_WF8B_BPALCD9_MASK 0x1u
+#define LCD_WF8B_BPALCD9_SHIFT 0
+#define LCD_WF8B_BPALCD8_MASK 0x1u
+#define LCD_WF8B_BPALCD8_SHIFT 0
+#define LCD_WF8B_BPBLCD1_MASK 0x2u
+#define LCD_WF8B_BPBLCD1_SHIFT 1
+#define LCD_WF8B_BPBLCD32_MASK 0x2u
+#define LCD_WF8B_BPBLCD32_SHIFT 1
+#define LCD_WF8B_BPBLCD30_MASK 0x2u
+#define LCD_WF8B_BPBLCD30_SHIFT 1
+#define LCD_WF8B_BPBLCD60_MASK 0x2u
+#define LCD_WF8B_BPBLCD60_SHIFT 1
+#define LCD_WF8B_BPBLCD24_MASK 0x2u
+#define LCD_WF8B_BPBLCD24_SHIFT 1
+#define LCD_WF8B_BPBLCD28_MASK 0x2u
+#define LCD_WF8B_BPBLCD28_SHIFT 1
+#define LCD_WF8B_BPBLCD23_MASK 0x2u
+#define LCD_WF8B_BPBLCD23_SHIFT 1
+#define LCD_WF8B_BPBLCD48_MASK 0x2u
+#define LCD_WF8B_BPBLCD48_SHIFT 1
+#define LCD_WF8B_BPBLCD10_MASK 0x2u
+#define LCD_WF8B_BPBLCD10_SHIFT 1
+#define LCD_WF8B_BPBLCD15_MASK 0x2u
+#define LCD_WF8B_BPBLCD15_SHIFT 1
+#define LCD_WF8B_BPBLCD36_MASK 0x2u
+#define LCD_WF8B_BPBLCD36_SHIFT 1
+#define LCD_WF8B_BPBLCD44_MASK 0x2u
+#define LCD_WF8B_BPBLCD44_SHIFT 1
+#define LCD_WF8B_BPBLCD62_MASK 0x2u
+#define LCD_WF8B_BPBLCD62_SHIFT 1
+#define LCD_WF8B_BPBLCD53_MASK 0x2u
+#define LCD_WF8B_BPBLCD53_SHIFT 1
+#define LCD_WF8B_BPBLCD22_MASK 0x2u
+#define LCD_WF8B_BPBLCD22_SHIFT 1
+#define LCD_WF8B_BPBLCD47_MASK 0x2u
+#define LCD_WF8B_BPBLCD47_SHIFT 1
+#define LCD_WF8B_BPBLCD33_MASK 0x2u
+#define LCD_WF8B_BPBLCD33_SHIFT 1
+#define LCD_WF8B_BPBLCD2_MASK 0x2u
+#define LCD_WF8B_BPBLCD2_SHIFT 1
+#define LCD_WF8B_BPBLCD49_MASK 0x2u
+#define LCD_WF8B_BPBLCD49_SHIFT 1
+#define LCD_WF8B_BPBLCD0_MASK 0x2u
+#define LCD_WF8B_BPBLCD0_SHIFT 1
+#define LCD_WF8B_BPBLCD55_MASK 0x2u
+#define LCD_WF8B_BPBLCD55_SHIFT 1
+#define LCD_WF8B_BPBLCD56_MASK 0x2u
+#define LCD_WF8B_BPBLCD56_SHIFT 1
+#define LCD_WF8B_BPBLCD21_MASK 0x2u
+#define LCD_WF8B_BPBLCD21_SHIFT 1
+#define LCD_WF8B_BPBLCD6_MASK 0x2u
+#define LCD_WF8B_BPBLCD6_SHIFT 1
+#define LCD_WF8B_BPBLCD29_MASK 0x2u
+#define LCD_WF8B_BPBLCD29_SHIFT 1
+#define LCD_WF8B_BPBLCD25_MASK 0x2u
+#define LCD_WF8B_BPBLCD25_SHIFT 1
+#define LCD_WF8B_BPBLCD8_MASK 0x2u
+#define LCD_WF8B_BPBLCD8_SHIFT 1
+#define LCD_WF8B_BPBLCD54_MASK 0x2u
+#define LCD_WF8B_BPBLCD54_SHIFT 1
+#define LCD_WF8B_BPBLCD38_MASK 0x2u
+#define LCD_WF8B_BPBLCD38_SHIFT 1
+#define LCD_WF8B_BPBLCD43_MASK 0x2u
+#define LCD_WF8B_BPBLCD43_SHIFT 1
+#define LCD_WF8B_BPBLCD20_MASK 0x2u
+#define LCD_WF8B_BPBLCD20_SHIFT 1
+#define LCD_WF8B_BPBLCD9_MASK 0x2u
+#define LCD_WF8B_BPBLCD9_SHIFT 1
+#define LCD_WF8B_BPBLCD7_MASK 0x2u
+#define LCD_WF8B_BPBLCD7_SHIFT 1
+#define LCD_WF8B_BPBLCD50_MASK 0x2u
+#define LCD_WF8B_BPBLCD50_SHIFT 1
+#define LCD_WF8B_BPBLCD40_MASK 0x2u
+#define LCD_WF8B_BPBLCD40_SHIFT 1
+#define LCD_WF8B_BPBLCD63_MASK 0x2u
+#define LCD_WF8B_BPBLCD63_SHIFT 1
+#define LCD_WF8B_BPBLCD26_MASK 0x2u
+#define LCD_WF8B_BPBLCD26_SHIFT 1
+#define LCD_WF8B_BPBLCD12_MASK 0x2u
+#define LCD_WF8B_BPBLCD12_SHIFT 1
+#define LCD_WF8B_BPBLCD19_MASK 0x2u
+#define LCD_WF8B_BPBLCD19_SHIFT 1
+#define LCD_WF8B_BPBLCD34_MASK 0x2u
+#define LCD_WF8B_BPBLCD34_SHIFT 1
+#define LCD_WF8B_BPBLCD39_MASK 0x2u
+#define LCD_WF8B_BPBLCD39_SHIFT 1
+#define LCD_WF8B_BPBLCD59_MASK 0x2u
+#define LCD_WF8B_BPBLCD59_SHIFT 1
+#define LCD_WF8B_BPBLCD61_MASK 0x2u
+#define LCD_WF8B_BPBLCD61_SHIFT 1
+#define LCD_WF8B_BPBLCD37_MASK 0x2u
+#define LCD_WF8B_BPBLCD37_SHIFT 1
+#define LCD_WF8B_BPBLCD31_MASK 0x2u
+#define LCD_WF8B_BPBLCD31_SHIFT 1
+#define LCD_WF8B_BPBLCD58_MASK 0x2u
+#define LCD_WF8B_BPBLCD58_SHIFT 1
+#define LCD_WF8B_BPBLCD18_MASK 0x2u
+#define LCD_WF8B_BPBLCD18_SHIFT 1
+#define LCD_WF8B_BPBLCD45_MASK 0x2u
+#define LCD_WF8B_BPBLCD45_SHIFT 1
+#define LCD_WF8B_BPBLCD27_MASK 0x2u
+#define LCD_WF8B_BPBLCD27_SHIFT 1
+#define LCD_WF8B_BPBLCD14_MASK 0x2u
+#define LCD_WF8B_BPBLCD14_SHIFT 1
+#define LCD_WF8B_BPBLCD51_MASK 0x2u
+#define LCD_WF8B_BPBLCD51_SHIFT 1
+#define LCD_WF8B_BPBLCD52_MASK 0x2u
+#define LCD_WF8B_BPBLCD52_SHIFT 1
+#define LCD_WF8B_BPBLCD4_MASK 0x2u
+#define LCD_WF8B_BPBLCD4_SHIFT 1
+#define LCD_WF8B_BPBLCD35_MASK 0x2u
+#define LCD_WF8B_BPBLCD35_SHIFT 1
+#define LCD_WF8B_BPBLCD17_MASK 0x2u
+#define LCD_WF8B_BPBLCD17_SHIFT 1
+#define LCD_WF8B_BPBLCD41_MASK 0x2u
+#define LCD_WF8B_BPBLCD41_SHIFT 1
+#define LCD_WF8B_BPBLCD11_MASK 0x2u
+#define LCD_WF8B_BPBLCD11_SHIFT 1
+#define LCD_WF8B_BPBLCD46_MASK 0x2u
+#define LCD_WF8B_BPBLCD46_SHIFT 1
+#define LCD_WF8B_BPBLCD57_MASK 0x2u
+#define LCD_WF8B_BPBLCD57_SHIFT 1
+#define LCD_WF8B_BPBLCD42_MASK 0x2u
+#define LCD_WF8B_BPBLCD42_SHIFT 1
+#define LCD_WF8B_BPBLCD5_MASK 0x2u
+#define LCD_WF8B_BPBLCD5_SHIFT 1
+#define LCD_WF8B_BPBLCD3_MASK 0x2u
+#define LCD_WF8B_BPBLCD3_SHIFT 1
+#define LCD_WF8B_BPBLCD16_MASK 0x2u
+#define LCD_WF8B_BPBLCD16_SHIFT 1
+#define LCD_WF8B_BPBLCD13_MASK 0x2u
+#define LCD_WF8B_BPBLCD13_SHIFT 1
+#define LCD_WF8B_BPCLCD10_MASK 0x4u
+#define LCD_WF8B_BPCLCD10_SHIFT 2
+#define LCD_WF8B_BPCLCD55_MASK 0x4u
+#define LCD_WF8B_BPCLCD55_SHIFT 2
+#define LCD_WF8B_BPCLCD2_MASK 0x4u
+#define LCD_WF8B_BPCLCD2_SHIFT 2
+#define LCD_WF8B_BPCLCD23_MASK 0x4u
+#define LCD_WF8B_BPCLCD23_SHIFT 2
+#define LCD_WF8B_BPCLCD48_MASK 0x4u
+#define LCD_WF8B_BPCLCD48_SHIFT 2
+#define LCD_WF8B_BPCLCD24_MASK 0x4u
+#define LCD_WF8B_BPCLCD24_SHIFT 2
+#define LCD_WF8B_BPCLCD60_MASK 0x4u
+#define LCD_WF8B_BPCLCD60_SHIFT 2
+#define LCD_WF8B_BPCLCD47_MASK 0x4u
+#define LCD_WF8B_BPCLCD47_SHIFT 2
+#define LCD_WF8B_BPCLCD22_MASK 0x4u
+#define LCD_WF8B_BPCLCD22_SHIFT 2
+#define LCD_WF8B_BPCLCD8_MASK 0x4u
+#define LCD_WF8B_BPCLCD8_SHIFT 2
+#define LCD_WF8B_BPCLCD21_MASK 0x4u
+#define LCD_WF8B_BPCLCD21_SHIFT 2
+#define LCD_WF8B_BPCLCD49_MASK 0x4u
+#define LCD_WF8B_BPCLCD49_SHIFT 2
+#define LCD_WF8B_BPCLCD25_MASK 0x4u
+#define LCD_WF8B_BPCLCD25_SHIFT 2
+#define LCD_WF8B_BPCLCD1_MASK 0x4u
+#define LCD_WF8B_BPCLCD1_SHIFT 2
+#define LCD_WF8B_BPCLCD20_MASK 0x4u
+#define LCD_WF8B_BPCLCD20_SHIFT 2
+#define LCD_WF8B_BPCLCD50_MASK 0x4u
+#define LCD_WF8B_BPCLCD50_SHIFT 2
+#define LCD_WF8B_BPCLCD19_MASK 0x4u
+#define LCD_WF8B_BPCLCD19_SHIFT 2
+#define LCD_WF8B_BPCLCD26_MASK 0x4u
+#define LCD_WF8B_BPCLCD26_SHIFT 2
+#define LCD_WF8B_BPCLCD59_MASK 0x4u
+#define LCD_WF8B_BPCLCD59_SHIFT 2
+#define LCD_WF8B_BPCLCD61_MASK 0x4u
+#define LCD_WF8B_BPCLCD61_SHIFT 2
+#define LCD_WF8B_BPCLCD46_MASK 0x4u
+#define LCD_WF8B_BPCLCD46_SHIFT 2
+#define LCD_WF8B_BPCLCD18_MASK 0x4u
+#define LCD_WF8B_BPCLCD18_SHIFT 2
+#define LCD_WF8B_BPCLCD5_MASK 0x4u
+#define LCD_WF8B_BPCLCD5_SHIFT 2
+#define LCD_WF8B_BPCLCD63_MASK 0x4u
+#define LCD_WF8B_BPCLCD63_SHIFT 2
+#define LCD_WF8B_BPCLCD27_MASK 0x4u
+#define LCD_WF8B_BPCLCD27_SHIFT 2
+#define LCD_WF8B_BPCLCD17_MASK 0x4u
+#define LCD_WF8B_BPCLCD17_SHIFT 2
+#define LCD_WF8B_BPCLCD51_MASK 0x4u
+#define LCD_WF8B_BPCLCD51_SHIFT 2
+#define LCD_WF8B_BPCLCD9_MASK 0x4u
+#define LCD_WF8B_BPCLCD9_SHIFT 2
+#define LCD_WF8B_BPCLCD54_MASK 0x4u
+#define LCD_WF8B_BPCLCD54_SHIFT 2
+#define LCD_WF8B_BPCLCD15_MASK 0x4u
+#define LCD_WF8B_BPCLCD15_SHIFT 2
+#define LCD_WF8B_BPCLCD16_MASK 0x4u
+#define LCD_WF8B_BPCLCD16_SHIFT 2
+#define LCD_WF8B_BPCLCD14_MASK 0x4u
+#define LCD_WF8B_BPCLCD14_SHIFT 2
+#define LCD_WF8B_BPCLCD32_MASK 0x4u
+#define LCD_WF8B_BPCLCD32_SHIFT 2
+#define LCD_WF8B_BPCLCD28_MASK 0x4u
+#define LCD_WF8B_BPCLCD28_SHIFT 2
+#define LCD_WF8B_BPCLCD53_MASK 0x4u
+#define LCD_WF8B_BPCLCD53_SHIFT 2
+#define LCD_WF8B_BPCLCD33_MASK 0x4u
+#define LCD_WF8B_BPCLCD33_SHIFT 2
+#define LCD_WF8B_BPCLCD0_MASK 0x4u
+#define LCD_WF8B_BPCLCD0_SHIFT 2
+#define LCD_WF8B_BPCLCD43_MASK 0x4u
+#define LCD_WF8B_BPCLCD43_SHIFT 2
+#define LCD_WF8B_BPCLCD7_MASK 0x4u
+#define LCD_WF8B_BPCLCD7_SHIFT 2
+#define LCD_WF8B_BPCLCD4_MASK 0x4u
+#define LCD_WF8B_BPCLCD4_SHIFT 2
+#define LCD_WF8B_BPCLCD34_MASK 0x4u
+#define LCD_WF8B_BPCLCD34_SHIFT 2
+#define LCD_WF8B_BPCLCD29_MASK 0x4u
+#define LCD_WF8B_BPCLCD29_SHIFT 2
+#define LCD_WF8B_BPCLCD45_MASK 0x4u
+#define LCD_WF8B_BPCLCD45_SHIFT 2
+#define LCD_WF8B_BPCLCD57_MASK 0x4u
+#define LCD_WF8B_BPCLCD57_SHIFT 2
+#define LCD_WF8B_BPCLCD42_MASK 0x4u
+#define LCD_WF8B_BPCLCD42_SHIFT 2
+#define LCD_WF8B_BPCLCD35_MASK 0x4u
+#define LCD_WF8B_BPCLCD35_SHIFT 2
+#define LCD_WF8B_BPCLCD13_MASK 0x4u
+#define LCD_WF8B_BPCLCD13_SHIFT 2
+#define LCD_WF8B_BPCLCD36_MASK 0x4u
+#define LCD_WF8B_BPCLCD36_SHIFT 2
+#define LCD_WF8B_BPCLCD30_MASK 0x4u
+#define LCD_WF8B_BPCLCD30_SHIFT 2
+#define LCD_WF8B_BPCLCD52_MASK 0x4u
+#define LCD_WF8B_BPCLCD52_SHIFT 2
+#define LCD_WF8B_BPCLCD58_MASK 0x4u
+#define LCD_WF8B_BPCLCD58_SHIFT 2
+#define LCD_WF8B_BPCLCD41_MASK 0x4u
+#define LCD_WF8B_BPCLCD41_SHIFT 2
+#define LCD_WF8B_BPCLCD37_MASK 0x4u
+#define LCD_WF8B_BPCLCD37_SHIFT 2
+#define LCD_WF8B_BPCLCD3_MASK 0x4u
+#define LCD_WF8B_BPCLCD3_SHIFT 2
+#define LCD_WF8B_BPCLCD12_MASK 0x4u
+#define LCD_WF8B_BPCLCD12_SHIFT 2
+#define LCD_WF8B_BPCLCD11_MASK 0x4u
+#define LCD_WF8B_BPCLCD11_SHIFT 2
+#define LCD_WF8B_BPCLCD38_MASK 0x4u
+#define LCD_WF8B_BPCLCD38_SHIFT 2
+#define LCD_WF8B_BPCLCD44_MASK 0x4u
+#define LCD_WF8B_BPCLCD44_SHIFT 2
+#define LCD_WF8B_BPCLCD31_MASK 0x4u
+#define LCD_WF8B_BPCLCD31_SHIFT 2
+#define LCD_WF8B_BPCLCD40_MASK 0x4u
+#define LCD_WF8B_BPCLCD40_SHIFT 2
+#define LCD_WF8B_BPCLCD62_MASK 0x4u
+#define LCD_WF8B_BPCLCD62_SHIFT 2
+#define LCD_WF8B_BPCLCD56_MASK 0x4u
+#define LCD_WF8B_BPCLCD56_SHIFT 2
+#define LCD_WF8B_BPCLCD39_MASK 0x4u
+#define LCD_WF8B_BPCLCD39_SHIFT 2
+#define LCD_WF8B_BPCLCD6_MASK 0x4u
+#define LCD_WF8B_BPCLCD6_SHIFT 2
+#define LCD_WF8B_BPDLCD47_MASK 0x8u
+#define LCD_WF8B_BPDLCD47_SHIFT 3
+#define LCD_WF8B_BPDLCD23_MASK 0x8u
+#define LCD_WF8B_BPDLCD23_SHIFT 3
+#define LCD_WF8B_BPDLCD48_MASK 0x8u
+#define LCD_WF8B_BPDLCD48_SHIFT 3
+#define LCD_WF8B_BPDLCD24_MASK 0x8u
+#define LCD_WF8B_BPDLCD24_SHIFT 3
+#define LCD_WF8B_BPDLCD15_MASK 0x8u
+#define LCD_WF8B_BPDLCD15_SHIFT 3
+#define LCD_WF8B_BPDLCD22_MASK 0x8u
+#define LCD_WF8B_BPDLCD22_SHIFT 3
+#define LCD_WF8B_BPDLCD60_MASK 0x8u
+#define LCD_WF8B_BPDLCD60_SHIFT 3
+#define LCD_WF8B_BPDLCD10_MASK 0x8u
+#define LCD_WF8B_BPDLCD10_SHIFT 3
+#define LCD_WF8B_BPDLCD21_MASK 0x8u
+#define LCD_WF8B_BPDLCD21_SHIFT 3
+#define LCD_WF8B_BPDLCD49_MASK 0x8u
+#define LCD_WF8B_BPDLCD49_SHIFT 3
+#define LCD_WF8B_BPDLCD1_MASK 0x8u
+#define LCD_WF8B_BPDLCD1_SHIFT 3
+#define LCD_WF8B_BPDLCD25_MASK 0x8u
+#define LCD_WF8B_BPDLCD25_SHIFT 3
+#define LCD_WF8B_BPDLCD20_MASK 0x8u
+#define LCD_WF8B_BPDLCD20_SHIFT 3
+#define LCD_WF8B_BPDLCD2_MASK 0x8u
+#define LCD_WF8B_BPDLCD2_SHIFT 3
+#define LCD_WF8B_BPDLCD55_MASK 0x8u
+#define LCD_WF8B_BPDLCD55_SHIFT 3
+#define LCD_WF8B_BPDLCD59_MASK 0x8u
+#define LCD_WF8B_BPDLCD59_SHIFT 3
+#define LCD_WF8B_BPDLCD5_MASK 0x8u
+#define LCD_WF8B_BPDLCD5_SHIFT 3
+#define LCD_WF8B_BPDLCD19_MASK 0x8u
+#define LCD_WF8B_BPDLCD19_SHIFT 3
+#define LCD_WF8B_BPDLCD6_MASK 0x8u
+#define LCD_WF8B_BPDLCD6_SHIFT 3
+#define LCD_WF8B_BPDLCD26_MASK 0x8u
+#define LCD_WF8B_BPDLCD26_SHIFT 3
+#define LCD_WF8B_BPDLCD0_MASK 0x8u
+#define LCD_WF8B_BPDLCD0_SHIFT 3
+#define LCD_WF8B_BPDLCD50_MASK 0x8u
+#define LCD_WF8B_BPDLCD50_SHIFT 3
+#define LCD_WF8B_BPDLCD46_MASK 0x8u
+#define LCD_WF8B_BPDLCD46_SHIFT 3
+#define LCD_WF8B_BPDLCD18_MASK 0x8u
+#define LCD_WF8B_BPDLCD18_SHIFT 3
+#define LCD_WF8B_BPDLCD61_MASK 0x8u
+#define LCD_WF8B_BPDLCD61_SHIFT 3
+#define LCD_WF8B_BPDLCD9_MASK 0x8u
+#define LCD_WF8B_BPDLCD9_SHIFT 3
+#define LCD_WF8B_BPDLCD17_MASK 0x8u
+#define LCD_WF8B_BPDLCD17_SHIFT 3
+#define LCD_WF8B_BPDLCD27_MASK 0x8u
+#define LCD_WF8B_BPDLCD27_SHIFT 3
+#define LCD_WF8B_BPDLCD53_MASK 0x8u
+#define LCD_WF8B_BPDLCD53_SHIFT 3
+#define LCD_WF8B_BPDLCD51_MASK 0x8u
+#define LCD_WF8B_BPDLCD51_SHIFT 3
+#define LCD_WF8B_BPDLCD54_MASK 0x8u
+#define LCD_WF8B_BPDLCD54_SHIFT 3
+#define LCD_WF8B_BPDLCD13_MASK 0x8u
+#define LCD_WF8B_BPDLCD13_SHIFT 3
+#define LCD_WF8B_BPDLCD16_MASK 0x8u
+#define LCD_WF8B_BPDLCD16_SHIFT 3
+#define LCD_WF8B_BPDLCD32_MASK 0x8u
+#define LCD_WF8B_BPDLCD32_SHIFT 3
+#define LCD_WF8B_BPDLCD14_MASK 0x8u
+#define LCD_WF8B_BPDLCD14_SHIFT 3
+#define LCD_WF8B_BPDLCD28_MASK 0x8u
+#define LCD_WF8B_BPDLCD28_SHIFT 3
+#define LCD_WF8B_BPDLCD43_MASK 0x8u
+#define LCD_WF8B_BPDLCD43_SHIFT 3
+#define LCD_WF8B_BPDLCD4_MASK 0x8u
+#define LCD_WF8B_BPDLCD4_SHIFT 3
+#define LCD_WF8B_BPDLCD45_MASK 0x8u
+#define LCD_WF8B_BPDLCD45_SHIFT 3
+#define LCD_WF8B_BPDLCD8_MASK 0x8u
+#define LCD_WF8B_BPDLCD8_SHIFT 3
+#define LCD_WF8B_BPDLCD62_MASK 0x8u
+#define LCD_WF8B_BPDLCD62_SHIFT 3
+#define LCD_WF8B_BPDLCD33_MASK 0x8u
+#define LCD_WF8B_BPDLCD33_SHIFT 3
+#define LCD_WF8B_BPDLCD34_MASK 0x8u
+#define LCD_WF8B_BPDLCD34_SHIFT 3
+#define LCD_WF8B_BPDLCD29_MASK 0x8u
+#define LCD_WF8B_BPDLCD29_SHIFT 3
+#define LCD_WF8B_BPDLCD58_MASK 0x8u
+#define LCD_WF8B_BPDLCD58_SHIFT 3
+#define LCD_WF8B_BPDLCD57_MASK 0x8u
+#define LCD_WF8B_BPDLCD57_SHIFT 3
+#define LCD_WF8B_BPDLCD42_MASK 0x8u
+#define LCD_WF8B_BPDLCD42_SHIFT 3
+#define LCD_WF8B_BPDLCD35_MASK 0x8u
+#define LCD_WF8B_BPDLCD35_SHIFT 3
+#define LCD_WF8B_BPDLCD52_MASK 0x8u
+#define LCD_WF8B_BPDLCD52_SHIFT 3
+#define LCD_WF8B_BPDLCD7_MASK 0x8u
+#define LCD_WF8B_BPDLCD7_SHIFT 3
+#define LCD_WF8B_BPDLCD36_MASK 0x8u
+#define LCD_WF8B_BPDLCD36_SHIFT 3
+#define LCD_WF8B_BPDLCD30_MASK 0x8u
+#define LCD_WF8B_BPDLCD30_SHIFT 3
+#define LCD_WF8B_BPDLCD41_MASK 0x8u
+#define LCD_WF8B_BPDLCD41_SHIFT 3
+#define LCD_WF8B_BPDLCD37_MASK 0x8u
+#define LCD_WF8B_BPDLCD37_SHIFT 3
+#define LCD_WF8B_BPDLCD44_MASK 0x8u
+#define LCD_WF8B_BPDLCD44_SHIFT 3
+#define LCD_WF8B_BPDLCD63_MASK 0x8u
+#define LCD_WF8B_BPDLCD63_SHIFT 3
+#define LCD_WF8B_BPDLCD38_MASK 0x8u
+#define LCD_WF8B_BPDLCD38_SHIFT 3
+#define LCD_WF8B_BPDLCD56_MASK 0x8u
+#define LCD_WF8B_BPDLCD56_SHIFT 3
+#define LCD_WF8B_BPDLCD40_MASK 0x8u
+#define LCD_WF8B_BPDLCD40_SHIFT 3
+#define LCD_WF8B_BPDLCD31_MASK 0x8u
+#define LCD_WF8B_BPDLCD31_SHIFT 3
+#define LCD_WF8B_BPDLCD12_MASK 0x8u
+#define LCD_WF8B_BPDLCD12_SHIFT 3
+#define LCD_WF8B_BPDLCD39_MASK 0x8u
+#define LCD_WF8B_BPDLCD39_SHIFT 3
+#define LCD_WF8B_BPDLCD3_MASK 0x8u
+#define LCD_WF8B_BPDLCD3_SHIFT 3
+#define LCD_WF8B_BPDLCD11_MASK 0x8u
+#define LCD_WF8B_BPDLCD11_SHIFT 3
+#define LCD_WF8B_BPELCD12_MASK 0x10u
+#define LCD_WF8B_BPELCD12_SHIFT 4
+#define LCD_WF8B_BPELCD39_MASK 0x10u
+#define LCD_WF8B_BPELCD39_SHIFT 4
+#define LCD_WF8B_BPELCD3_MASK 0x10u
+#define LCD_WF8B_BPELCD3_SHIFT 4
+#define LCD_WF8B_BPELCD38_MASK 0x10u
+#define LCD_WF8B_BPELCD38_SHIFT 4
+#define LCD_WF8B_BPELCD40_MASK 0x10u
+#define LCD_WF8B_BPELCD40_SHIFT 4
+#define LCD_WF8B_BPELCD37_MASK 0x10u
+#define LCD_WF8B_BPELCD37_SHIFT 4
+#define LCD_WF8B_BPELCD41_MASK 0x10u
+#define LCD_WF8B_BPELCD41_SHIFT 4
+#define LCD_WF8B_BPELCD36_MASK 0x10u
+#define LCD_WF8B_BPELCD36_SHIFT 4
+#define LCD_WF8B_BPELCD8_MASK 0x10u
+#define LCD_WF8B_BPELCD8_SHIFT 4
+#define LCD_WF8B_BPELCD35_MASK 0x10u
+#define LCD_WF8B_BPELCD35_SHIFT 4
+#define LCD_WF8B_BPELCD42_MASK 0x10u
+#define LCD_WF8B_BPELCD42_SHIFT 4
+#define LCD_WF8B_BPELCD34_MASK 0x10u
+#define LCD_WF8B_BPELCD34_SHIFT 4
+#define LCD_WF8B_BPELCD33_MASK 0x10u
+#define LCD_WF8B_BPELCD33_SHIFT 4
+#define LCD_WF8B_BPELCD11_MASK 0x10u
+#define LCD_WF8B_BPELCD11_SHIFT 4
+#define LCD_WF8B_BPELCD43_MASK 0x10u
+#define LCD_WF8B_BPELCD43_SHIFT 4
+#define LCD_WF8B_BPELCD32_MASK 0x10u
+#define LCD_WF8B_BPELCD32_SHIFT 4
+#define LCD_WF8B_BPELCD31_MASK 0x10u
+#define LCD_WF8B_BPELCD31_SHIFT 4
+#define LCD_WF8B_BPELCD44_MASK 0x10u
+#define LCD_WF8B_BPELCD44_SHIFT 4
+#define LCD_WF8B_BPELCD30_MASK 0x10u
+#define LCD_WF8B_BPELCD30_SHIFT 4
+#define LCD_WF8B_BPELCD29_MASK 0x10u
+#define LCD_WF8B_BPELCD29_SHIFT 4
+#define LCD_WF8B_BPELCD7_MASK 0x10u
+#define LCD_WF8B_BPELCD7_SHIFT 4
+#define LCD_WF8B_BPELCD45_MASK 0x10u
+#define LCD_WF8B_BPELCD45_SHIFT 4
+#define LCD_WF8B_BPELCD28_MASK 0x10u
+#define LCD_WF8B_BPELCD28_SHIFT 4
+#define LCD_WF8B_BPELCD2_MASK 0x10u
+#define LCD_WF8B_BPELCD2_SHIFT 4
+#define LCD_WF8B_BPELCD27_MASK 0x10u
+#define LCD_WF8B_BPELCD27_SHIFT 4
+#define LCD_WF8B_BPELCD46_MASK 0x10u
+#define LCD_WF8B_BPELCD46_SHIFT 4
+#define LCD_WF8B_BPELCD26_MASK 0x10u
+#define LCD_WF8B_BPELCD26_SHIFT 4
+#define LCD_WF8B_BPELCD10_MASK 0x10u
+#define LCD_WF8B_BPELCD10_SHIFT 4
+#define LCD_WF8B_BPELCD13_MASK 0x10u
+#define LCD_WF8B_BPELCD13_SHIFT 4
+#define LCD_WF8B_BPELCD25_MASK 0x10u
+#define LCD_WF8B_BPELCD25_SHIFT 4
+#define LCD_WF8B_BPELCD5_MASK 0x10u
+#define LCD_WF8B_BPELCD5_SHIFT 4
+#define LCD_WF8B_BPELCD24_MASK 0x10u
+#define LCD_WF8B_BPELCD24_SHIFT 4
+#define LCD_WF8B_BPELCD47_MASK 0x10u
+#define LCD_WF8B_BPELCD47_SHIFT 4
+#define LCD_WF8B_BPELCD23_MASK 0x10u
+#define LCD_WF8B_BPELCD23_SHIFT 4
+#define LCD_WF8B_BPELCD22_MASK 0x10u
+#define LCD_WF8B_BPELCD22_SHIFT 4
+#define LCD_WF8B_BPELCD48_MASK 0x10u
+#define LCD_WF8B_BPELCD48_SHIFT 4
+#define LCD_WF8B_BPELCD21_MASK 0x10u
+#define LCD_WF8B_BPELCD21_SHIFT 4
+#define LCD_WF8B_BPELCD49_MASK 0x10u
+#define LCD_WF8B_BPELCD49_SHIFT 4
+#define LCD_WF8B_BPELCD20_MASK 0x10u
+#define LCD_WF8B_BPELCD20_SHIFT 4
+#define LCD_WF8B_BPELCD19_MASK 0x10u
+#define LCD_WF8B_BPELCD19_SHIFT 4
+#define LCD_WF8B_BPELCD9_MASK 0x10u
+#define LCD_WF8B_BPELCD9_SHIFT 4
+#define LCD_WF8B_BPELCD50_MASK 0x10u
+#define LCD_WF8B_BPELCD50_SHIFT 4
+#define LCD_WF8B_BPELCD18_MASK 0x10u
+#define LCD_WF8B_BPELCD18_SHIFT 4
+#define LCD_WF8B_BPELCD6_MASK 0x10u
+#define LCD_WF8B_BPELCD6_SHIFT 4
+#define LCD_WF8B_BPELCD17_MASK 0x10u
+#define LCD_WF8B_BPELCD17_SHIFT 4
+#define LCD_WF8B_BPELCD51_MASK 0x10u
+#define LCD_WF8B_BPELCD51_SHIFT 4
+#define LCD_WF8B_BPELCD16_MASK 0x10u
+#define LCD_WF8B_BPELCD16_SHIFT 4
+#define LCD_WF8B_BPELCD56_MASK 0x10u
+#define LCD_WF8B_BPELCD56_SHIFT 4
+#define LCD_WF8B_BPELCD57_MASK 0x10u
+#define LCD_WF8B_BPELCD57_SHIFT 4
+#define LCD_WF8B_BPELCD52_MASK 0x10u
+#define LCD_WF8B_BPELCD52_SHIFT 4
+#define LCD_WF8B_BPELCD1_MASK 0x10u
+#define LCD_WF8B_BPELCD1_SHIFT 4
+#define LCD_WF8B_BPELCD58_MASK 0x10u
+#define LCD_WF8B_BPELCD58_SHIFT 4
+#define LCD_WF8B_BPELCD59_MASK 0x10u
+#define LCD_WF8B_BPELCD59_SHIFT 4
+#define LCD_WF8B_BPELCD53_MASK 0x10u
+#define LCD_WF8B_BPELCD53_SHIFT 4
+#define LCD_WF8B_BPELCD14_MASK 0x10u
+#define LCD_WF8B_BPELCD14_SHIFT 4
+#define LCD_WF8B_BPELCD0_MASK 0x10u
+#define LCD_WF8B_BPELCD0_SHIFT 4
+#define LCD_WF8B_BPELCD60_MASK 0x10u
+#define LCD_WF8B_BPELCD60_SHIFT 4
+#define LCD_WF8B_BPELCD15_MASK 0x10u
+#define LCD_WF8B_BPELCD15_SHIFT 4
+#define LCD_WF8B_BPELCD61_MASK 0x10u
+#define LCD_WF8B_BPELCD61_SHIFT 4
+#define LCD_WF8B_BPELCD54_MASK 0x10u
+#define LCD_WF8B_BPELCD54_SHIFT 4
+#define LCD_WF8B_BPELCD62_MASK 0x10u
+#define LCD_WF8B_BPELCD62_SHIFT 4
+#define LCD_WF8B_BPELCD63_MASK 0x10u
+#define LCD_WF8B_BPELCD63_SHIFT 4
+#define LCD_WF8B_BPELCD55_MASK 0x10u
+#define LCD_WF8B_BPELCD55_SHIFT 4
+#define LCD_WF8B_BPELCD4_MASK 0x10u
+#define LCD_WF8B_BPELCD4_SHIFT 4
+#define LCD_WF8B_BPFLCD13_MASK 0x20u
+#define LCD_WF8B_BPFLCD13_SHIFT 5
+#define LCD_WF8B_BPFLCD39_MASK 0x20u
+#define LCD_WF8B_BPFLCD39_SHIFT 5
+#define LCD_WF8B_BPFLCD55_MASK 0x20u
+#define LCD_WF8B_BPFLCD55_SHIFT 5
+#define LCD_WF8B_BPFLCD47_MASK 0x20u
+#define LCD_WF8B_BPFLCD47_SHIFT 5
+#define LCD_WF8B_BPFLCD63_MASK 0x20u
+#define LCD_WF8B_BPFLCD63_SHIFT 5
+#define LCD_WF8B_BPFLCD43_MASK 0x20u
+#define LCD_WF8B_BPFLCD43_SHIFT 5
+#define LCD_WF8B_BPFLCD5_MASK 0x20u
+#define LCD_WF8B_BPFLCD5_SHIFT 5
+#define LCD_WF8B_BPFLCD62_MASK 0x20u
+#define LCD_WF8B_BPFLCD62_SHIFT 5
+#define LCD_WF8B_BPFLCD14_MASK 0x20u
+#define LCD_WF8B_BPFLCD14_SHIFT 5
+#define LCD_WF8B_BPFLCD24_MASK 0x20u
+#define LCD_WF8B_BPFLCD24_SHIFT 5
+#define LCD_WF8B_BPFLCD54_MASK 0x20u
+#define LCD_WF8B_BPFLCD54_SHIFT 5
+#define LCD_WF8B_BPFLCD15_MASK 0x20u
+#define LCD_WF8B_BPFLCD15_SHIFT 5
+#define LCD_WF8B_BPFLCD32_MASK 0x20u
+#define LCD_WF8B_BPFLCD32_SHIFT 5
+#define LCD_WF8B_BPFLCD61_MASK 0x20u
+#define LCD_WF8B_BPFLCD61_SHIFT 5
+#define LCD_WF8B_BPFLCD25_MASK 0x20u
+#define LCD_WF8B_BPFLCD25_SHIFT 5
+#define LCD_WF8B_BPFLCD60_MASK 0x20u
+#define LCD_WF8B_BPFLCD60_SHIFT 5
+#define LCD_WF8B_BPFLCD41_MASK 0x20u
+#define LCD_WF8B_BPFLCD41_SHIFT 5
+#define LCD_WF8B_BPFLCD33_MASK 0x20u
+#define LCD_WF8B_BPFLCD33_SHIFT 5
+#define LCD_WF8B_BPFLCD53_MASK 0x20u
+#define LCD_WF8B_BPFLCD53_SHIFT 5
+#define LCD_WF8B_BPFLCD59_MASK 0x20u
+#define LCD_WF8B_BPFLCD59_SHIFT 5
+#define LCD_WF8B_BPFLCD0_MASK 0x20u
+#define LCD_WF8B_BPFLCD0_SHIFT 5
+#define LCD_WF8B_BPFLCD46_MASK 0x20u
+#define LCD_WF8B_BPFLCD46_SHIFT 5
+#define LCD_WF8B_BPFLCD58_MASK 0x20u
+#define LCD_WF8B_BPFLCD58_SHIFT 5
+#define LCD_WF8B_BPFLCD26_MASK 0x20u
+#define LCD_WF8B_BPFLCD26_SHIFT 5
+#define LCD_WF8B_BPFLCD36_MASK 0x20u
+#define LCD_WF8B_BPFLCD36_SHIFT 5
+#define LCD_WF8B_BPFLCD10_MASK 0x20u
+#define LCD_WF8B_BPFLCD10_SHIFT 5
+#define LCD_WF8B_BPFLCD52_MASK 0x20u
+#define LCD_WF8B_BPFLCD52_SHIFT 5
+#define LCD_WF8B_BPFLCD57_MASK 0x20u
+#define LCD_WF8B_BPFLCD57_SHIFT 5
+#define LCD_WF8B_BPFLCD27_MASK 0x20u
+#define LCD_WF8B_BPFLCD27_SHIFT 5
+#define LCD_WF8B_BPFLCD11_MASK 0x20u
+#define LCD_WF8B_BPFLCD11_SHIFT 5
+#define LCD_WF8B_BPFLCD56_MASK 0x20u
+#define LCD_WF8B_BPFLCD56_SHIFT 5
+#define LCD_WF8B_BPFLCD1_MASK 0x20u
+#define LCD_WF8B_BPFLCD1_SHIFT 5
+#define LCD_WF8B_BPFLCD8_MASK 0x20u
+#define LCD_WF8B_BPFLCD8_SHIFT 5
+#define LCD_WF8B_BPFLCD40_MASK 0x20u
+#define LCD_WF8B_BPFLCD40_SHIFT 5
+#define LCD_WF8B_BPFLCD51_MASK 0x20u
+#define LCD_WF8B_BPFLCD51_SHIFT 5
+#define LCD_WF8B_BPFLCD16_MASK 0x20u
+#define LCD_WF8B_BPFLCD16_SHIFT 5
+#define LCD_WF8B_BPFLCD45_MASK 0x20u
+#define LCD_WF8B_BPFLCD45_SHIFT 5
+#define LCD_WF8B_BPFLCD6_MASK 0x20u
+#define LCD_WF8B_BPFLCD6_SHIFT 5
+#define LCD_WF8B_BPFLCD17_MASK 0x20u
+#define LCD_WF8B_BPFLCD17_SHIFT 5
+#define LCD_WF8B_BPFLCD28_MASK 0x20u
+#define LCD_WF8B_BPFLCD28_SHIFT 5
+#define LCD_WF8B_BPFLCD42_MASK 0x20u
+#define LCD_WF8B_BPFLCD42_SHIFT 5
+#define LCD_WF8B_BPFLCD29_MASK 0x20u
+#define LCD_WF8B_BPFLCD29_SHIFT 5
+#define LCD_WF8B_BPFLCD50_MASK 0x20u
+#define LCD_WF8B_BPFLCD50_SHIFT 5
+#define LCD_WF8B_BPFLCD18_MASK 0x20u
+#define LCD_WF8B_BPFLCD18_SHIFT 5
+#define LCD_WF8B_BPFLCD34_MASK 0x20u
+#define LCD_WF8B_BPFLCD34_SHIFT 5
+#define LCD_WF8B_BPFLCD19_MASK 0x20u
+#define LCD_WF8B_BPFLCD19_SHIFT 5
+#define LCD_WF8B_BPFLCD2_MASK 0x20u
+#define LCD_WF8B_BPFLCD2_SHIFT 5
+#define LCD_WF8B_BPFLCD9_MASK 0x20u
+#define LCD_WF8B_BPFLCD9_SHIFT 5
+#define LCD_WF8B_BPFLCD3_MASK 0x20u
+#define LCD_WF8B_BPFLCD3_SHIFT 5
+#define LCD_WF8B_BPFLCD37_MASK 0x20u
+#define LCD_WF8B_BPFLCD37_SHIFT 5
+#define LCD_WF8B_BPFLCD49_MASK 0x20u
+#define LCD_WF8B_BPFLCD49_SHIFT 5
+#define LCD_WF8B_BPFLCD20_MASK 0x20u
+#define LCD_WF8B_BPFLCD20_SHIFT 5
+#define LCD_WF8B_BPFLCD44_MASK 0x20u
+#define LCD_WF8B_BPFLCD44_SHIFT 5
+#define LCD_WF8B_BPFLCD30_MASK 0x20u
+#define LCD_WF8B_BPFLCD30_SHIFT 5
+#define LCD_WF8B_BPFLCD21_MASK 0x20u
+#define LCD_WF8B_BPFLCD21_SHIFT 5
+#define LCD_WF8B_BPFLCD35_MASK 0x20u
+#define LCD_WF8B_BPFLCD35_SHIFT 5
+#define LCD_WF8B_BPFLCD4_MASK 0x20u
+#define LCD_WF8B_BPFLCD4_SHIFT 5
+#define LCD_WF8B_BPFLCD31_MASK 0x20u
+#define LCD_WF8B_BPFLCD31_SHIFT 5
+#define LCD_WF8B_BPFLCD48_MASK 0x20u
+#define LCD_WF8B_BPFLCD48_SHIFT 5
+#define LCD_WF8B_BPFLCD7_MASK 0x20u
+#define LCD_WF8B_BPFLCD7_SHIFT 5
+#define LCD_WF8B_BPFLCD22_MASK 0x20u
+#define LCD_WF8B_BPFLCD22_SHIFT 5
+#define LCD_WF8B_BPFLCD38_MASK 0x20u
+#define LCD_WF8B_BPFLCD38_SHIFT 5
+#define LCD_WF8B_BPFLCD12_MASK 0x20u
+#define LCD_WF8B_BPFLCD12_SHIFT 5
+#define LCD_WF8B_BPFLCD23_MASK 0x20u
+#define LCD_WF8B_BPFLCD23_SHIFT 5
+#define LCD_WF8B_BPGLCD14_MASK 0x40u
+#define LCD_WF8B_BPGLCD14_SHIFT 6
+#define LCD_WF8B_BPGLCD55_MASK 0x40u
+#define LCD_WF8B_BPGLCD55_SHIFT 6
+#define LCD_WF8B_BPGLCD63_MASK 0x40u
+#define LCD_WF8B_BPGLCD63_SHIFT 6
+#define LCD_WF8B_BPGLCD15_MASK 0x40u
+#define LCD_WF8B_BPGLCD15_SHIFT 6
+#define LCD_WF8B_BPGLCD62_MASK 0x40u
+#define LCD_WF8B_BPGLCD62_SHIFT 6
+#define LCD_WF8B_BPGLCD54_MASK 0x40u
+#define LCD_WF8B_BPGLCD54_SHIFT 6
+#define LCD_WF8B_BPGLCD61_MASK 0x40u
+#define LCD_WF8B_BPGLCD61_SHIFT 6
+#define LCD_WF8B_BPGLCD60_MASK 0x40u
+#define LCD_WF8B_BPGLCD60_SHIFT 6
+#define LCD_WF8B_BPGLCD59_MASK 0x40u
+#define LCD_WF8B_BPGLCD59_SHIFT 6
+#define LCD_WF8B_BPGLCD53_MASK 0x40u
+#define LCD_WF8B_BPGLCD53_SHIFT 6
+#define LCD_WF8B_BPGLCD58_MASK 0x40u
+#define LCD_WF8B_BPGLCD58_SHIFT 6
+#define LCD_WF8B_BPGLCD0_MASK 0x40u
+#define LCD_WF8B_BPGLCD0_SHIFT 6
+#define LCD_WF8B_BPGLCD57_MASK 0x40u
+#define LCD_WF8B_BPGLCD57_SHIFT 6
+#define LCD_WF8B_BPGLCD52_MASK 0x40u
+#define LCD_WF8B_BPGLCD52_SHIFT 6
+#define LCD_WF8B_BPGLCD7_MASK 0x40u
+#define LCD_WF8B_BPGLCD7_SHIFT 6
+#define LCD_WF8B_BPGLCD56_MASK 0x40u
+#define LCD_WF8B_BPGLCD56_SHIFT 6
+#define LCD_WF8B_BPGLCD6_MASK 0x40u
+#define LCD_WF8B_BPGLCD6_SHIFT 6
+#define LCD_WF8B_BPGLCD51_MASK 0x40u
+#define LCD_WF8B_BPGLCD51_SHIFT 6
+#define LCD_WF8B_BPGLCD16_MASK 0x40u
+#define LCD_WF8B_BPGLCD16_SHIFT 6
+#define LCD_WF8B_BPGLCD1_MASK 0x40u
+#define LCD_WF8B_BPGLCD1_SHIFT 6
+#define LCD_WF8B_BPGLCD17_MASK 0x40u
+#define LCD_WF8B_BPGLCD17_SHIFT 6
+#define LCD_WF8B_BPGLCD50_MASK 0x40u
+#define LCD_WF8B_BPGLCD50_SHIFT 6
+#define LCD_WF8B_BPGLCD18_MASK 0x40u
+#define LCD_WF8B_BPGLCD18_SHIFT 6
+#define LCD_WF8B_BPGLCD19_MASK 0x40u
+#define LCD_WF8B_BPGLCD19_SHIFT 6
+#define LCD_WF8B_BPGLCD8_MASK 0x40u
+#define LCD_WF8B_BPGLCD8_SHIFT 6
+#define LCD_WF8B_BPGLCD49_MASK 0x40u
+#define LCD_WF8B_BPGLCD49_SHIFT 6
+#define LCD_WF8B_BPGLCD20_MASK 0x40u
+#define LCD_WF8B_BPGLCD20_SHIFT 6
+#define LCD_WF8B_BPGLCD9_MASK 0x40u
+#define LCD_WF8B_BPGLCD9_SHIFT 6
+#define LCD_WF8B_BPGLCD21_MASK 0x40u
+#define LCD_WF8B_BPGLCD21_SHIFT 6
+#define LCD_WF8B_BPGLCD13_MASK 0x40u
+#define LCD_WF8B_BPGLCD13_SHIFT 6
+#define LCD_WF8B_BPGLCD48_MASK 0x40u
+#define LCD_WF8B_BPGLCD48_SHIFT 6
+#define LCD_WF8B_BPGLCD22_MASK 0x40u
+#define LCD_WF8B_BPGLCD22_SHIFT 6
+#define LCD_WF8B_BPGLCD5_MASK 0x40u
+#define LCD_WF8B_BPGLCD5_SHIFT 6
+#define LCD_WF8B_BPGLCD47_MASK 0x40u
+#define LCD_WF8B_BPGLCD47_SHIFT 6
+#define LCD_WF8B_BPGLCD23_MASK 0x40u
+#define LCD_WF8B_BPGLCD23_SHIFT 6
+#define LCD_WF8B_BPGLCD24_MASK 0x40u
+#define LCD_WF8B_BPGLCD24_SHIFT 6
+#define LCD_WF8B_BPGLCD25_MASK 0x40u
+#define LCD_WF8B_BPGLCD25_SHIFT 6
+#define LCD_WF8B_BPGLCD46_MASK 0x40u
+#define LCD_WF8B_BPGLCD46_SHIFT 6
+#define LCD_WF8B_BPGLCD26_MASK 0x40u
+#define LCD_WF8B_BPGLCD26_SHIFT 6
+#define LCD_WF8B_BPGLCD27_MASK 0x40u
+#define LCD_WF8B_BPGLCD27_SHIFT 6
+#define LCD_WF8B_BPGLCD10_MASK 0x40u
+#define LCD_WF8B_BPGLCD10_SHIFT 6
+#define LCD_WF8B_BPGLCD45_MASK 0x40u
+#define LCD_WF8B_BPGLCD45_SHIFT 6
+#define LCD_WF8B_BPGLCD28_MASK 0x40u
+#define LCD_WF8B_BPGLCD28_SHIFT 6
+#define LCD_WF8B_BPGLCD29_MASK 0x40u
+#define LCD_WF8B_BPGLCD29_SHIFT 6
+#define LCD_WF8B_BPGLCD4_MASK 0x40u
+#define LCD_WF8B_BPGLCD4_SHIFT 6
+#define LCD_WF8B_BPGLCD44_MASK 0x40u
+#define LCD_WF8B_BPGLCD44_SHIFT 6
+#define LCD_WF8B_BPGLCD30_MASK 0x40u
+#define LCD_WF8B_BPGLCD30_SHIFT 6
+#define LCD_WF8B_BPGLCD2_MASK 0x40u
+#define LCD_WF8B_BPGLCD2_SHIFT 6
+#define LCD_WF8B_BPGLCD31_MASK 0x40u
+#define LCD_WF8B_BPGLCD31_SHIFT 6
+#define LCD_WF8B_BPGLCD43_MASK 0x40u
+#define LCD_WF8B_BPGLCD43_SHIFT 6
+#define LCD_WF8B_BPGLCD32_MASK 0x40u
+#define LCD_WF8B_BPGLCD32_SHIFT 6
+#define LCD_WF8B_BPGLCD33_MASK 0x40u
+#define LCD_WF8B_BPGLCD33_SHIFT 6
+#define LCD_WF8B_BPGLCD42_MASK 0x40u
+#define LCD_WF8B_BPGLCD42_SHIFT 6
+#define LCD_WF8B_BPGLCD34_MASK 0x40u
+#define LCD_WF8B_BPGLCD34_SHIFT 6
+#define LCD_WF8B_BPGLCD11_MASK 0x40u
+#define LCD_WF8B_BPGLCD11_SHIFT 6
+#define LCD_WF8B_BPGLCD35_MASK 0x40u
+#define LCD_WF8B_BPGLCD35_SHIFT 6
+#define LCD_WF8B_BPGLCD12_MASK 0x40u
+#define LCD_WF8B_BPGLCD12_SHIFT 6
+#define LCD_WF8B_BPGLCD41_MASK 0x40u
+#define LCD_WF8B_BPGLCD41_SHIFT 6
+#define LCD_WF8B_BPGLCD36_MASK 0x40u
+#define LCD_WF8B_BPGLCD36_SHIFT 6
+#define LCD_WF8B_BPGLCD3_MASK 0x40u
+#define LCD_WF8B_BPGLCD3_SHIFT 6
+#define LCD_WF8B_BPGLCD37_MASK 0x40u
+#define LCD_WF8B_BPGLCD37_SHIFT 6
+#define LCD_WF8B_BPGLCD40_MASK 0x40u
+#define LCD_WF8B_BPGLCD40_SHIFT 6
+#define LCD_WF8B_BPGLCD38_MASK 0x40u
+#define LCD_WF8B_BPGLCD38_SHIFT 6
+#define LCD_WF8B_BPGLCD39_MASK 0x40u
+#define LCD_WF8B_BPGLCD39_SHIFT 6
+#define LCD_WF8B_BPHLCD63_MASK 0x80u
+#define LCD_WF8B_BPHLCD63_SHIFT 7
+#define LCD_WF8B_BPHLCD62_MASK 0x80u
+#define LCD_WF8B_BPHLCD62_SHIFT 7
+#define LCD_WF8B_BPHLCD61_MASK 0x80u
+#define LCD_WF8B_BPHLCD61_SHIFT 7
+#define LCD_WF8B_BPHLCD60_MASK 0x80u
+#define LCD_WF8B_BPHLCD60_SHIFT 7
+#define LCD_WF8B_BPHLCD59_MASK 0x80u
+#define LCD_WF8B_BPHLCD59_SHIFT 7
+#define LCD_WF8B_BPHLCD58_MASK 0x80u
+#define LCD_WF8B_BPHLCD58_SHIFT 7
+#define LCD_WF8B_BPHLCD57_MASK 0x80u
+#define LCD_WF8B_BPHLCD57_SHIFT 7
+#define LCD_WF8B_BPHLCD0_MASK 0x80u
+#define LCD_WF8B_BPHLCD0_SHIFT 7
+#define LCD_WF8B_BPHLCD56_MASK 0x80u
+#define LCD_WF8B_BPHLCD56_SHIFT 7
+#define LCD_WF8B_BPHLCD55_MASK 0x80u
+#define LCD_WF8B_BPHLCD55_SHIFT 7
+#define LCD_WF8B_BPHLCD54_MASK 0x80u
+#define LCD_WF8B_BPHLCD54_SHIFT 7
+#define LCD_WF8B_BPHLCD53_MASK 0x80u
+#define LCD_WF8B_BPHLCD53_SHIFT 7
+#define LCD_WF8B_BPHLCD52_MASK 0x80u
+#define LCD_WF8B_BPHLCD52_SHIFT 7
+#define LCD_WF8B_BPHLCD51_MASK 0x80u
+#define LCD_WF8B_BPHLCD51_SHIFT 7
+#define LCD_WF8B_BPHLCD50_MASK 0x80u
+#define LCD_WF8B_BPHLCD50_SHIFT 7
+#define LCD_WF8B_BPHLCD1_MASK 0x80u
+#define LCD_WF8B_BPHLCD1_SHIFT 7
+#define LCD_WF8B_BPHLCD49_MASK 0x80u
+#define LCD_WF8B_BPHLCD49_SHIFT 7
+#define LCD_WF8B_BPHLCD48_MASK 0x80u
+#define LCD_WF8B_BPHLCD48_SHIFT 7
+#define LCD_WF8B_BPHLCD47_MASK 0x80u
+#define LCD_WF8B_BPHLCD47_SHIFT 7
+#define LCD_WF8B_BPHLCD46_MASK 0x80u
+#define LCD_WF8B_BPHLCD46_SHIFT 7
+#define LCD_WF8B_BPHLCD45_MASK 0x80u
+#define LCD_WF8B_BPHLCD45_SHIFT 7
+#define LCD_WF8B_BPHLCD44_MASK 0x80u
+#define LCD_WF8B_BPHLCD44_SHIFT 7
+#define LCD_WF8B_BPHLCD43_MASK 0x80u
+#define LCD_WF8B_BPHLCD43_SHIFT 7
+#define LCD_WF8B_BPHLCD2_MASK 0x80u
+#define LCD_WF8B_BPHLCD2_SHIFT 7
+#define LCD_WF8B_BPHLCD42_MASK 0x80u
+#define LCD_WF8B_BPHLCD42_SHIFT 7
+#define LCD_WF8B_BPHLCD41_MASK 0x80u
+#define LCD_WF8B_BPHLCD41_SHIFT 7
+#define LCD_WF8B_BPHLCD40_MASK 0x80u
+#define LCD_WF8B_BPHLCD40_SHIFT 7
+#define LCD_WF8B_BPHLCD39_MASK 0x80u
+#define LCD_WF8B_BPHLCD39_SHIFT 7
+#define LCD_WF8B_BPHLCD38_MASK 0x80u
+#define LCD_WF8B_BPHLCD38_SHIFT 7
+#define LCD_WF8B_BPHLCD37_MASK 0x80u
+#define LCD_WF8B_BPHLCD37_SHIFT 7
+#define LCD_WF8B_BPHLCD36_MASK 0x80u
+#define LCD_WF8B_BPHLCD36_SHIFT 7
+#define LCD_WF8B_BPHLCD3_MASK 0x80u
+#define LCD_WF8B_BPHLCD3_SHIFT 7
+#define LCD_WF8B_BPHLCD35_MASK 0x80u
+#define LCD_WF8B_BPHLCD35_SHIFT 7
+#define LCD_WF8B_BPHLCD34_MASK 0x80u
+#define LCD_WF8B_BPHLCD34_SHIFT 7
+#define LCD_WF8B_BPHLCD33_MASK 0x80u
+#define LCD_WF8B_BPHLCD33_SHIFT 7
+#define LCD_WF8B_BPHLCD32_MASK 0x80u
+#define LCD_WF8B_BPHLCD32_SHIFT 7
+#define LCD_WF8B_BPHLCD31_MASK 0x80u
+#define LCD_WF8B_BPHLCD31_SHIFT 7
+#define LCD_WF8B_BPHLCD30_MASK 0x80u
+#define LCD_WF8B_BPHLCD30_SHIFT 7
+#define LCD_WF8B_BPHLCD29_MASK 0x80u
+#define LCD_WF8B_BPHLCD29_SHIFT 7
+#define LCD_WF8B_BPHLCD4_MASK 0x80u
+#define LCD_WF8B_BPHLCD4_SHIFT 7
+#define LCD_WF8B_BPHLCD28_MASK 0x80u
+#define LCD_WF8B_BPHLCD28_SHIFT 7
+#define LCD_WF8B_BPHLCD27_MASK 0x80u
+#define LCD_WF8B_BPHLCD27_SHIFT 7
+#define LCD_WF8B_BPHLCD26_MASK 0x80u
+#define LCD_WF8B_BPHLCD26_SHIFT 7
+#define LCD_WF8B_BPHLCD25_MASK 0x80u
+#define LCD_WF8B_BPHLCD25_SHIFT 7
+#define LCD_WF8B_BPHLCD24_MASK 0x80u
+#define LCD_WF8B_BPHLCD24_SHIFT 7
+#define LCD_WF8B_BPHLCD23_MASK 0x80u
+#define LCD_WF8B_BPHLCD23_SHIFT 7
+#define LCD_WF8B_BPHLCD22_MASK 0x80u
+#define LCD_WF8B_BPHLCD22_SHIFT 7
+#define LCD_WF8B_BPHLCD5_MASK 0x80u
+#define LCD_WF8B_BPHLCD5_SHIFT 7
+#define LCD_WF8B_BPHLCD21_MASK 0x80u
+#define LCD_WF8B_BPHLCD21_SHIFT 7
+#define LCD_WF8B_BPHLCD20_MASK 0x80u
+#define LCD_WF8B_BPHLCD20_SHIFT 7
+#define LCD_WF8B_BPHLCD19_MASK 0x80u
+#define LCD_WF8B_BPHLCD19_SHIFT 7
+#define LCD_WF8B_BPHLCD18_MASK 0x80u
+#define LCD_WF8B_BPHLCD18_SHIFT 7
+#define LCD_WF8B_BPHLCD17_MASK 0x80u
+#define LCD_WF8B_BPHLCD17_SHIFT 7
+#define LCD_WF8B_BPHLCD16_MASK 0x80u
+#define LCD_WF8B_BPHLCD16_SHIFT 7
+#define LCD_WF8B_BPHLCD15_MASK 0x80u
+#define LCD_WF8B_BPHLCD15_SHIFT 7
+#define LCD_WF8B_BPHLCD6_MASK 0x80u
+#define LCD_WF8B_BPHLCD6_SHIFT 7
+#define LCD_WF8B_BPHLCD14_MASK 0x80u
+#define LCD_WF8B_BPHLCD14_SHIFT 7
+#define LCD_WF8B_BPHLCD13_MASK 0x80u
+#define LCD_WF8B_BPHLCD13_SHIFT 7
+#define LCD_WF8B_BPHLCD12_MASK 0x80u
+#define LCD_WF8B_BPHLCD12_SHIFT 7
+#define LCD_WF8B_BPHLCD11_MASK 0x80u
+#define LCD_WF8B_BPHLCD11_SHIFT 7
+#define LCD_WF8B_BPHLCD10_MASK 0x80u
+#define LCD_WF8B_BPHLCD10_SHIFT 7
+#define LCD_WF8B_BPHLCD9_MASK 0x80u
+#define LCD_WF8B_BPHLCD9_SHIFT 7
+#define LCD_WF8B_BPHLCD8_MASK 0x80u
+#define LCD_WF8B_BPHLCD8_SHIFT 7
+#define LCD_WF8B_BPHLCD7_MASK 0x80u
+#define LCD_WF8B_BPHLCD7_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group LCD_Register_Masks */
+
+
+/* LCD - Peripheral instance base addresses */
+/** Peripheral LCD base address */
+#define LCD_BASE (0x40053000u)
+/** Peripheral LCD base pointer */
+#define LCD ((LCD_Type *)LCD_BASE)
+/** Array initializer of LCD peripheral base pointers */
+#define LCD_BASES { LCD }
+
+/*!
+ * @}
+ */ /* end of group LCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
+ __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
+ __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
+ __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
+ __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
+ __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
+ __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
+ __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
+ __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
+ __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LLWU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK 0x3u
+#define LLWU_PE1_WUPE0_SHIFT 0
+#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK 0xCu
+#define LLWU_PE1_WUPE1_SHIFT 2
+#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK 0x30u
+#define LLWU_PE1_WUPE2_SHIFT 4
+#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK 0xC0u
+#define LLWU_PE1_WUPE3_SHIFT 6
+#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK 0x3u
+#define LLWU_PE2_WUPE4_SHIFT 0
+#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK 0xCu
+#define LLWU_PE2_WUPE5_SHIFT 2
+#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK 0x30u
+#define LLWU_PE2_WUPE6_SHIFT 4
+#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK 0xC0u
+#define LLWU_PE2_WUPE7_SHIFT 6
+#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK 0x3u
+#define LLWU_PE3_WUPE8_SHIFT 0
+#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK 0xCu
+#define LLWU_PE3_WUPE9_SHIFT 2
+#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK 0x30u
+#define LLWU_PE3_WUPE10_SHIFT 4
+#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK 0xC0u
+#define LLWU_PE3_WUPE11_SHIFT 6
+#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK 0x3u
+#define LLWU_PE4_WUPE12_SHIFT 0
+#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK 0xCu
+#define LLWU_PE4_WUPE13_SHIFT 2
+#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK 0x30u
+#define LLWU_PE4_WUPE14_SHIFT 4
+#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK 0xC0u
+#define LLWU_PE4_WUPE15_SHIFT 6
+#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK 0x1u
+#define LLWU_ME_WUME0_SHIFT 0
+#define LLWU_ME_WUME1_MASK 0x2u
+#define LLWU_ME_WUME1_SHIFT 1
+#define LLWU_ME_WUME2_MASK 0x4u
+#define LLWU_ME_WUME2_SHIFT 2
+#define LLWU_ME_WUME3_MASK 0x8u
+#define LLWU_ME_WUME3_SHIFT 3
+#define LLWU_ME_WUME4_MASK 0x10u
+#define LLWU_ME_WUME4_SHIFT 4
+#define LLWU_ME_WUME5_MASK 0x20u
+#define LLWU_ME_WUME5_SHIFT 5
+#define LLWU_ME_WUME6_MASK 0x40u
+#define LLWU_ME_WUME6_SHIFT 6
+#define LLWU_ME_WUME7_MASK 0x80u
+#define LLWU_ME_WUME7_SHIFT 7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK 0x1u
+#define LLWU_F1_WUF0_SHIFT 0
+#define LLWU_F1_WUF1_MASK 0x2u
+#define LLWU_F1_WUF1_SHIFT 1
+#define LLWU_F1_WUF2_MASK 0x4u
+#define LLWU_F1_WUF2_SHIFT 2
+#define LLWU_F1_WUF3_MASK 0x8u
+#define LLWU_F1_WUF3_SHIFT 3
+#define LLWU_F1_WUF4_MASK 0x10u
+#define LLWU_F1_WUF4_SHIFT 4
+#define LLWU_F1_WUF5_MASK 0x20u
+#define LLWU_F1_WUF5_SHIFT 5
+#define LLWU_F1_WUF6_MASK 0x40u
+#define LLWU_F1_WUF6_SHIFT 6
+#define LLWU_F1_WUF7_MASK 0x80u
+#define LLWU_F1_WUF7_SHIFT 7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK 0x1u
+#define LLWU_F2_WUF8_SHIFT 0
+#define LLWU_F2_WUF9_MASK 0x2u
+#define LLWU_F2_WUF9_SHIFT 1
+#define LLWU_F2_WUF10_MASK 0x4u
+#define LLWU_F2_WUF10_SHIFT 2
+#define LLWU_F2_WUF11_MASK 0x8u
+#define LLWU_F2_WUF11_SHIFT 3
+#define LLWU_F2_WUF12_MASK 0x10u
+#define LLWU_F2_WUF12_SHIFT 4
+#define LLWU_F2_WUF13_MASK 0x20u
+#define LLWU_F2_WUF13_SHIFT 5
+#define LLWU_F2_WUF14_MASK 0x40u
+#define LLWU_F2_WUF14_SHIFT 6
+#define LLWU_F2_WUF15_MASK 0x80u
+#define LLWU_F2_WUF15_SHIFT 7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK 0x1u
+#define LLWU_F3_MWUF0_SHIFT 0
+#define LLWU_F3_MWUF1_MASK 0x2u
+#define LLWU_F3_MWUF1_SHIFT 1
+#define LLWU_F3_MWUF2_MASK 0x4u
+#define LLWU_F3_MWUF2_SHIFT 2
+#define LLWU_F3_MWUF3_MASK 0x8u
+#define LLWU_F3_MWUF3_SHIFT 3
+#define LLWU_F3_MWUF4_MASK 0x10u
+#define LLWU_F3_MWUF4_SHIFT 4
+#define LLWU_F3_MWUF5_MASK 0x20u
+#define LLWU_F3_MWUF5_SHIFT 5
+#define LLWU_F3_MWUF6_MASK 0x40u
+#define LLWU_F3_MWUF6_SHIFT 6
+#define LLWU_F3_MWUF7_MASK 0x80u
+#define LLWU_F3_MWUF7_SHIFT 7
+/* FILT1 Bit Fields */
+#define LLWU_FILT1_FILTSEL_MASK 0xFu
+#define LLWU_FILT1_FILTSEL_SHIFT 0
+#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK 0x60u
+#define LLWU_FILT1_FILTE_SHIFT 5
+#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK 0x80u
+#define LLWU_FILT1_FILTF_SHIFT 7
+/* FILT2 Bit Fields */
+#define LLWU_FILT2_FILTSEL_MASK 0xFu
+#define LLWU_FILT2_FILTSEL_SHIFT 0
+#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK 0x60u
+#define LLWU_FILT2_FILTE_SHIFT 5
+#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK 0x80u
+#define LLWU_FILT2_FILTF_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASES { LLWU }
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
+ __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
+ __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
+ __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LPTMR Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK 0x1u
+#define LPTMR_CSR_TEN_SHIFT 0
+#define LPTMR_CSR_TMS_MASK 0x2u
+#define LPTMR_CSR_TMS_SHIFT 1
+#define LPTMR_CSR_TFC_MASK 0x4u
+#define LPTMR_CSR_TFC_SHIFT 2
+#define LPTMR_CSR_TPP_MASK 0x8u
+#define LPTMR_CSR_TPP_SHIFT 3
+#define LPTMR_CSR_TPS_MASK 0x30u
+#define LPTMR_CSR_TPS_SHIFT 4
+#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK 0x40u
+#define LPTMR_CSR_TIE_SHIFT 6
+#define LPTMR_CSR_TCF_MASK 0x80u
+#define LPTMR_CSR_TCF_SHIFT 7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK 0x3u
+#define LPTMR_PSR_PCS_SHIFT 0
+#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK 0x4u
+#define LPTMR_PSR_PBYP_SHIFT 2
+#define LPTMR_PSR_PRESCALE_MASK 0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT 3
+#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT 0
+#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT 0
+#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASES { LPTMR0 }
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
+ __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
+ __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
+ __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
+ __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
+ __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
+ __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
+ uint8_t RESERVED_0[1];
+ __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
+ uint8_t RESERVED_1[1];
+ __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+ __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+ __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
+ __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
+ __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
+ __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK 0x1u
+#define MCG_C1_IREFSTEN_SHIFT 0
+#define MCG_C1_IRCLKEN_MASK 0x2u
+#define MCG_C1_IRCLKEN_SHIFT 1
+#define MCG_C1_IREFS_MASK 0x4u
+#define MCG_C1_IREFS_SHIFT 2
+#define MCG_C1_FRDIV_MASK 0x38u
+#define MCG_C1_FRDIV_SHIFT 3
+#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK 0xC0u
+#define MCG_C1_CLKS_SHIFT 6
+#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK 0x1u
+#define MCG_C2_IRCS_SHIFT 0
+#define MCG_C2_LP_MASK 0x2u
+#define MCG_C2_LP_SHIFT 1
+#define MCG_C2_EREFS0_MASK 0x4u
+#define MCG_C2_EREFS0_SHIFT 2
+#define MCG_C2_HGO0_MASK 0x8u
+#define MCG_C2_HGO0_SHIFT 3
+#define MCG_C2_RANGE0_MASK 0x30u
+#define MCG_C2_RANGE0_SHIFT 4
+#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
+#define MCG_C2_FCFTRIM_MASK 0x40u
+#define MCG_C2_FCFTRIM_SHIFT 6
+#define MCG_C2_LOCRE0_MASK 0x80u
+#define MCG_C2_LOCRE0_SHIFT 7
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK 0xFFu
+#define MCG_C3_SCTRIM_SHIFT 0
+#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK 0x1u
+#define MCG_C4_SCFTRIM_SHIFT 0
+#define MCG_C4_FCTRIM_MASK 0x1Eu
+#define MCG_C4_FCTRIM_SHIFT 1
+#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK 0x60u
+#define MCG_C4_DRST_DRS_SHIFT 5
+#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK 0x80u
+#define MCG_C4_DMX32_SHIFT 7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV0_MASK 0x1Fu
+#define MCG_C5_PRDIV0_SHIFT 0
+#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0_MASK 0x20u
+#define MCG_C5_PLLSTEN0_SHIFT 5
+#define MCG_C5_PLLCLKEN0_MASK 0x40u
+#define MCG_C5_PLLCLKEN0_SHIFT 6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV0_MASK 0x1Fu
+#define MCG_C6_VDIV0_SHIFT 0
+#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0_MASK 0x20u
+#define MCG_C6_CME0_SHIFT 5
+#define MCG_C6_PLLS_MASK 0x40u
+#define MCG_C6_PLLS_SHIFT 6
+#define MCG_C6_LOLIE0_MASK 0x80u
+#define MCG_C6_LOLIE0_SHIFT 7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK 0x1u
+#define MCG_S_IRCST_SHIFT 0
+#define MCG_S_OSCINIT0_MASK 0x2u
+#define MCG_S_OSCINIT0_SHIFT 1
+#define MCG_S_CLKST_MASK 0xCu
+#define MCG_S_CLKST_SHIFT 2
+#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK 0x10u
+#define MCG_S_IREFST_SHIFT 4
+#define MCG_S_PLLST_MASK 0x20u
+#define MCG_S_PLLST_SHIFT 5
+#define MCG_S_LOCK0_MASK 0x40u
+#define MCG_S_LOCK0_SHIFT 6
+#define MCG_S_LOLS_MASK 0x80u
+#define MCG_S_LOLS_SHIFT 7
+/* SC Bit Fields */
+#define MCG_SC_LOCS0_MASK 0x1u
+#define MCG_SC_LOCS0_SHIFT 0
+#define MCG_SC_FCRDIV_MASK 0xEu
+#define MCG_SC_FCRDIV_SHIFT 1
+#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK 0x10u
+#define MCG_SC_FLTPRSRV_SHIFT 4
+#define MCG_SC_ATMF_MASK 0x20u
+#define MCG_SC_ATMF_SHIFT 5
+#define MCG_SC_ATMS_MASK 0x40u
+#define MCG_SC_ATMS_SHIFT 6
+#define MCG_SC_ATME_MASK 0x80u
+#define MCG_SC_ATME_SHIFT 7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK 0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT 0
+#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK 0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT 0
+#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+/* C8 Bit Fields */
+#define MCG_C8_LOLRE_MASK 0x40u
+#define MCG_C8_LOLRE_SHIFT 6
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASES { MCG }
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[8];
+ __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+ __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+ __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK 0xFFu
+#define MCM_PLASC_ASC_SHIFT 0
+#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK 0xFFu
+#define MCM_PLAMC_AMC_SHIFT 0
+#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* PLACR Bit Fields */
+#define MCM_PLACR_ARB_MASK 0x200u
+#define MCM_PLACR_ARB_SHIFT 9
+#define MCM_PLACR_CFCC_MASK 0x400u
+#define MCM_PLACR_CFCC_SHIFT 10
+#define MCM_PLACR_DFCDA_MASK 0x800u
+#define MCM_PLACR_DFCDA_SHIFT 11
+#define MCM_PLACR_DFCIC_MASK 0x1000u
+#define MCM_PLACR_DFCIC_SHIFT 12
+#define MCM_PLACR_DFCC_MASK 0x2000u
+#define MCM_PLACR_DFCC_SHIFT 13
+#define MCM_PLACR_EFDS_MASK 0x4000u
+#define MCM_PLACR_EFDS_SHIFT 14
+#define MCM_PLACR_DFCS_MASK 0x8000u
+#define MCM_PLACR_DFCS_SHIFT 15
+#define MCM_PLACR_ESFC_MASK 0x10000u
+#define MCM_PLACR_ESFC_SHIFT 16
+/* CPO Bit Fields */
+#define MCM_CPO_CPOREQ_MASK 0x1u
+#define MCM_CPO_CPOREQ_SHIFT 0
+#define MCM_CPO_CPOACK_MASK 0x2u
+#define MCM_CPO_CPOACK_SHIFT 1
+#define MCM_CPO_CPOWOI_MASK 0x4u
+#define MCM_CPO_CPOWOI_SHIFT 2
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE (0xF0003000u)
+/** Peripheral MCM base pointer */
+#define MCM ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASES { MCM }
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
+ * @{
+ */
+
+/** MTB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
+ __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
+ __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
+ __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
+ uint8_t RESERVED_0[3824];
+ __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
+ uint8_t RESERVED_1[156];
+ __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
+ __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
+ uint8_t RESERVED_2[8];
+ __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
+ __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
+ __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
+ __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
+ uint8_t RESERVED_3[8];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTB_Register_Masks MTB Register Masks
+ * @{
+ */
+
+/* POSITION Bit Fields */
+#define MTB_POSITION_WRAP_MASK 0x4u
+#define MTB_POSITION_WRAP_SHIFT 2
+#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
+#define MTB_POSITION_POINTER_SHIFT 3
+#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
+/* MASTER Bit Fields */
+#define MTB_MASTER_MASK_MASK 0x1Fu
+#define MTB_MASTER_MASK_SHIFT 0
+#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
+#define MTB_MASTER_TSTARTEN_MASK 0x20u
+#define MTB_MASTER_TSTARTEN_SHIFT 5
+#define MTB_MASTER_TSTOPEN_MASK 0x40u
+#define MTB_MASTER_TSTOPEN_SHIFT 6
+#define MTB_MASTER_SFRWPRIV_MASK 0x80u
+#define MTB_MASTER_SFRWPRIV_SHIFT 7
+#define MTB_MASTER_RAMPRIV_MASK 0x100u
+#define MTB_MASTER_RAMPRIV_SHIFT 8
+#define MTB_MASTER_HALTREQ_MASK 0x200u
+#define MTB_MASTER_HALTREQ_SHIFT 9
+#define MTB_MASTER_EN_MASK 0x80000000u
+#define MTB_MASTER_EN_SHIFT 31
+/* FLOW Bit Fields */
+#define MTB_FLOW_AUTOSTOP_MASK 0x1u
+#define MTB_FLOW_AUTOSTOP_SHIFT 0
+#define MTB_FLOW_AUTOHALT_MASK 0x2u
+#define MTB_FLOW_AUTOHALT_SHIFT 1
+#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
+#define MTB_FLOW_WATERMARK_SHIFT 3
+#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
+/* BASE Bit Fields */
+#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
+#define MTB_BASE_BASEADDR_SHIFT 0
+#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
+/* MODECTRL Bit Fields */
+#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
+#define MTB_MODECTRL_MODECTRL_SHIFT 0
+#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
+/* TAGSET Bit Fields */
+#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
+#define MTB_TAGSET_TAGSET_SHIFT 0
+#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
+/* TAGCLEAR Bit Fields */
+#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
+#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
+#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
+/* LOCKACCESS Bit Fields */
+#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
+#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
+#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
+/* LOCKSTAT Bit Fields */
+#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
+#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
+#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
+/* AUTHSTAT Bit Fields */
+#define MTB_AUTHSTAT_BIT0_MASK 0x1u
+#define MTB_AUTHSTAT_BIT0_SHIFT 0
+#define MTB_AUTHSTAT_BIT1_MASK 0x2u
+#define MTB_AUTHSTAT_BIT1_SHIFT 1
+#define MTB_AUTHSTAT_BIT2_MASK 0x4u
+#define MTB_AUTHSTAT_BIT2_SHIFT 2
+#define MTB_AUTHSTAT_BIT3_MASK 0x8u
+#define MTB_AUTHSTAT_BIT3_SHIFT 3
+/* DEVICEARCH Bit Fields */
+#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
+#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
+#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
+/* DEVICECFG Bit Fields */
+#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTB_PERIPHID_PERIPHID_SHIFT 0
+#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTB_COMPID_COMPID_SHIFT 0
+#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MTB_Register_Masks */
+
+
+/* MTB - Peripheral instance base addresses */
+/** Peripheral MTB base address */
+#define MTB_BASE (0xF0000000u)
+/** Peripheral MTB base pointer */
+#define MTB ((MTB_Type *)MTB_BASE)
+/** Array initializer of MTB peripheral base pointers */
+#define MTB_BASES { MTB }
+
+/*!
+ * @}
+ */ /* end of group MTB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
+ * @{
+ */
+
+/** MTBDWT - Register Layout Typedef */
+typedef struct {
+ __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ struct { /* offset: 0x20, array step: 0x10 */
+ __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
+ __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
+ __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } COMPARATOR[2];
+ uint8_t RESERVED_1[448];
+ __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
+ uint8_t RESERVED_2[3524];
+ __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
+ __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
+ __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} MTBDWT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MTBDWT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
+ * @{
+ */
+
+/* CTRL Bit Fields */
+#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
+#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
+#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
+#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
+#define MTBDWT_CTRL_NUMCMP_SHIFT 28
+#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
+/* COMP Bit Fields */
+#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
+#define MTBDWT_COMP_COMP_SHIFT 0
+#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
+/* MASK Bit Fields */
+#define MTBDWT_MASK_MASK_MASK 0x1Fu
+#define MTBDWT_MASK_MASK_SHIFT 0
+#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
+/* FCT Bit Fields */
+#define MTBDWT_FCT_FUNCTION_MASK 0xFu
+#define MTBDWT_FCT_FUNCTION_SHIFT 0
+#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
+#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
+#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
+#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
+#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
+#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
+#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
+#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
+#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
+#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
+#define MTBDWT_FCT_MATCHED_SHIFT 24
+/* TBCTRL Bit Fields */
+#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
+#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
+#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
+#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
+#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
+#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
+#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
+/* DEVICECFG Bit Fields */
+#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
+#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
+/* DEVICETYPID Bit Fields */
+#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
+#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
+#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
+/* PERIPHID Bit Fields */
+#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
+#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
+#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define MTBDWT_COMPID_COMPID_SHIFT 0
+#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Register_Masks */
+
+
+/* MTBDWT - Peripheral instance base addresses */
+/** Peripheral MTBDWT base address */
+#define MTBDWT_BASE (0xF0001000u)
+/** Peripheral MTBDWT base pointer */
+#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
+/** Array initializer of MTBDWT peripheral base pointers */
+#define MTBDWT_BASES { MTBDWT }
+
+/*!
+ * @}
+ */ /* end of group MTBDWT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- NV Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+ __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
+ __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
+ __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
+ __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
+ __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
+ __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
+ __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
+ __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
+ __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+ __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+ __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+ __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+ __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
+ __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+ -- NV Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK 0xFFu
+#define NV_BACKKEY3_KEY_SHIFT 0
+#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK 0xFFu
+#define NV_BACKKEY2_KEY_SHIFT 0
+#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK 0xFFu
+#define NV_BACKKEY1_KEY_SHIFT 0
+#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK 0xFFu
+#define NV_BACKKEY0_KEY_SHIFT 0
+#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK 0xFFu
+#define NV_BACKKEY7_KEY_SHIFT 0
+#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK 0xFFu
+#define NV_BACKKEY6_KEY_SHIFT 0
+#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK 0xFFu
+#define NV_BACKKEY5_KEY_SHIFT 0
+#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK 0xFFu
+#define NV_BACKKEY4_KEY_SHIFT 0
+#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK 0xFFu
+#define NV_FPROT3_PROT_SHIFT 0
+#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK 0xFFu
+#define NV_FPROT2_PROT_SHIFT 0
+#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK 0xFFu
+#define NV_FPROT1_PROT_SHIFT 0
+#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK 0xFFu
+#define NV_FPROT0_PROT_SHIFT 0
+#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK 0x3u
+#define NV_FSEC_SEC_SHIFT 0
+#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK 0xCu
+#define NV_FSEC_FSLACC_SHIFT 2
+#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK 0x30u
+#define NV_FSEC_MEEN_SHIFT 4
+#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK 0xC0u
+#define NV_FSEC_KEYEN_SHIFT 6
+#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT0_MASK 0x1u
+#define NV_FOPT_LPBOOT0_SHIFT 0
+#define NV_FOPT_NMI_DIS_MASK 0x4u
+#define NV_FOPT_NMI_DIS_SHIFT 2
+#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
+#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
+#define NV_FOPT_LPBOOT1_MASK 0x10u
+#define NV_FOPT_LPBOOT1_SHIFT 4
+#define NV_FOPT_FAST_INIT_MASK 0x20u
+#define NV_FOPT_FAST_INIT_SHIFT 5
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFA_FlashConfig base address */
+#define FTFA_FlashConfig_BASE (0x400u)
+/** Peripheral FTFA_FlashConfig base pointer */
+#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASES { FTFA_FlashConfig }
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OSC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OSC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK 0x1u
+#define OSC_CR_SC16P_SHIFT 0
+#define OSC_CR_SC8P_MASK 0x2u
+#define OSC_CR_SC8P_SHIFT 1
+#define OSC_CR_SC4P_MASK 0x4u
+#define OSC_CR_SC4P_SHIFT 2
+#define OSC_CR_SC2P_MASK 0x8u
+#define OSC_CR_SC2P_SHIFT 3
+#define OSC_CR_EREFSTEN_MASK 0x20u
+#define OSC_CR_EREFSTEN_SHIFT 5
+#define OSC_CR_ERCLKEN_MASK 0x80u
+#define OSC_CR_ERCLKEN_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC0 base address */
+#define OSC0_BASE (0x40065000u)
+/** Peripheral OSC0 base pointer */
+#define OSC0 ((OSC_Type *)OSC0_BASE)
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASES { OSC0 }
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[220];
+ __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+ __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+ uint8_t RESERVED_1[24];
+ struct { /* offset: 0x100, array step: 0x10 */
+ __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+ __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+ __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+ __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+ } CHANNEL[2];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK 0x1u
+#define PIT_MCR_FRZ_SHIFT 0
+#define PIT_MCR_MDIS_MASK 0x2u
+#define PIT_MCR_MDIS_SHIFT 1
+/* LTMR64H Bit Fields */
+#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
+#define PIT_LTMR64H_LTH_SHIFT 0
+#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
+/* LTMR64L Bit Fields */
+#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
+#define PIT_LTMR64L_LTL_SHIFT 0
+#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT 0
+#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT 0
+#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK 0x1u
+#define PIT_TCTRL_TEN_SHIFT 0
+#define PIT_TCTRL_TIE_MASK 0x2u
+#define PIT_TCTRL_TIE_SHIFT 1
+#define PIT_TCTRL_CHN_MASK 0x4u
+#define PIT_TCTRL_CHN_SHIFT 2
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK 0x1u
+#define PIT_TFLG_TIF_SHIFT 0
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASES { PIT }
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+ __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+ __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK 0x3u
+#define PMC_LVDSC1_LVDV_SHIFT 0
+#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK 0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT 4
+#define PMC_LVDSC1_LVDIE_MASK 0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT 5
+#define PMC_LVDSC1_LVDACK_MASK 0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT 6
+#define PMC_LVDSC1_LVDF_MASK 0x80u
+#define PMC_LVDSC1_LVDF_SHIFT 7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK 0x3u
+#define PMC_LVDSC2_LVWV_SHIFT 0
+#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK 0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT 5
+#define PMC_LVDSC2_LVWACK_MASK 0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT 6
+#define PMC_LVDSC2_LVWF_MASK 0x80u
+#define PMC_LVDSC2_LVWF_SHIFT 7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK 0x1u
+#define PMC_REGSC_BGBE_SHIFT 0
+#define PMC_REGSC_REGONS_MASK 0x4u
+#define PMC_REGSC_REGONS_SHIFT 2
+#define PMC_REGSC_ACKISO_MASK 0x8u
+#define PMC_REGSC_ACKISO_SHIFT 3
+#define PMC_REGSC_BGEN_MASK 0x10u
+#define PMC_REGSC_BGEN_SHIFT 4
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASES { PMC }
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PORT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+ __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
+ __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
+ uint8_t RESERVED_0[24];
+ __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PORT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK 0x1u
+#define PORT_PCR_PS_SHIFT 0
+#define PORT_PCR_PE_MASK 0x2u
+#define PORT_PCR_PE_SHIFT 1
+#define PORT_PCR_SRE_MASK 0x4u
+#define PORT_PCR_SRE_SHIFT 2
+#define PORT_PCR_PFE_MASK 0x10u
+#define PORT_PCR_PFE_SHIFT 4
+#define PORT_PCR_DSE_MASK 0x40u
+#define PORT_PCR_DSE_SHIFT 6
+#define PORT_PCR_MUX_MASK 0x700u
+#define PORT_PCR_MUX_SHIFT 8
+#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_IRQC_MASK 0xF0000u
+#define PORT_PCR_IRQC_SHIFT 16
+#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK 0x1000000u
+#define PORT_PCR_ISF_SHIFT 24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK 0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT 0
+#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT 16
+#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK 0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT 0
+#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT 16
+#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT 0
+#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA ((PORT_Type *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB ((PORT_Type *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC ((PORT_Type *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD ((PORT_Type *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE ((PORT_Type *)PORTE_BASE)
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+ __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
+ __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
+ __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/* SRS0 Bit Fields */
+#define RCM_SRS0_WAKEUP_MASK 0x1u
+#define RCM_SRS0_WAKEUP_SHIFT 0
+#define RCM_SRS0_LVD_MASK 0x2u
+#define RCM_SRS0_LVD_SHIFT 1
+#define RCM_SRS0_LOC_MASK 0x4u
+#define RCM_SRS0_LOC_SHIFT 2
+#define RCM_SRS0_LOL_MASK 0x8u
+#define RCM_SRS0_LOL_SHIFT 3
+#define RCM_SRS0_WDOG_MASK 0x20u
+#define RCM_SRS0_WDOG_SHIFT 5
+#define RCM_SRS0_PIN_MASK 0x40u
+#define RCM_SRS0_PIN_SHIFT 6
+#define RCM_SRS0_POR_MASK 0x80u
+#define RCM_SRS0_POR_SHIFT 7
+/* SRS1 Bit Fields */
+#define RCM_SRS1_LOCKUP_MASK 0x2u
+#define RCM_SRS1_LOCKUP_SHIFT 1
+#define RCM_SRS1_SW_MASK 0x4u
+#define RCM_SRS1_SW_SHIFT 2
+#define RCM_SRS1_MDM_AP_MASK 0x8u
+#define RCM_SRS1_MDM_AP_SHIFT 3
+#define RCM_SRS1_SACKERR_MASK 0x20u
+#define RCM_SRS1_SACKERR_SHIFT 5
+/* RPFC Bit Fields */
+#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
+#define RCM_RPFC_RSTFLTSRW_SHIFT 0
+#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK 0x4u
+#define RCM_RPFC_RSTFLTSS_SHIFT 2
+/* RPFW Bit Fields */
+#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
+#define RCM_RPFW_RSTFLTSEL_SHIFT 0
+#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASES { RCM }
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ROM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
+ * @{
+ */
+
+/** ROM - Register Layout Typedef */
+typedef struct {
+ __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
+ __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
+ uint8_t RESERVED_0[4028];
+ __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
+ __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
+ __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
+ __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
+ __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
+ __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
+ __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
+ __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
+ __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
+ __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
+} ROM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ROM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ROM_Register_Masks ROM Register Masks
+ * @{
+ */
+
+/* ENTRY Bit Fields */
+#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
+#define ROM_ENTRY_ENTRY_SHIFT 0
+#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
+/* TABLEMARK Bit Fields */
+#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
+#define ROM_TABLEMARK_MARK_SHIFT 0
+#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
+/* SYSACCESS Bit Fields */
+#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
+#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
+#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
+/* PERIPHID4 Bit Fields */
+#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID4_PERIPHID_SHIFT 0
+#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
+/* PERIPHID5 Bit Fields */
+#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID5_PERIPHID_SHIFT 0
+#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
+/* PERIPHID6 Bit Fields */
+#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID6_PERIPHID_SHIFT 0
+#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
+/* PERIPHID7 Bit Fields */
+#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID7_PERIPHID_SHIFT 0
+#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
+/* PERIPHID0 Bit Fields */
+#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID0_PERIPHID_SHIFT 0
+#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
+/* PERIPHID1 Bit Fields */
+#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID1_PERIPHID_SHIFT 0
+#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
+/* PERIPHID2 Bit Fields */
+#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID2_PERIPHID_SHIFT 0
+#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
+/* PERIPHID3 Bit Fields */
+#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
+#define ROM_PERIPHID3_PERIPHID_SHIFT 0
+#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
+/* COMPID Bit Fields */
+#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
+#define ROM_COMPID_COMPID_SHIFT 0
+#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
+
+/*!
+ * @}
+ */ /* end of group ROM_Register_Masks */
+
+
+/* ROM - Peripheral instance base addresses */
+/** Peripheral ROM base address */
+#define ROM_BASE (0xF0002000u)
+/** Peripheral ROM base pointer */
+#define ROM ((ROM_Type *)ROM_BASE)
+/** Array initializer of ROM peripheral base pointers */
+#define ROM_BASES { ROM }
+
+/*!
+ * @}
+ */ /* end of group ROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
+ __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
+ __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
+ __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
+ __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
+ __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
+ __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
+ __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT 0
+#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK 0xFFFFu
+#define RTC_TPR_TPR_SHIFT 0
+#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT 0
+#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK 0xFFu
+#define RTC_TCR_TCR_SHIFT 0
+#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK 0xFF00u
+#define RTC_TCR_CIR_SHIFT 8
+#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK 0xFF0000u
+#define RTC_TCR_TCV_SHIFT 16
+#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK 0xFF000000u
+#define RTC_TCR_CIC_SHIFT 24
+#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK 0x1u
+#define RTC_CR_SWR_SHIFT 0
+#define RTC_CR_WPE_MASK 0x2u
+#define RTC_CR_WPE_SHIFT 1
+#define RTC_CR_SUP_MASK 0x4u
+#define RTC_CR_SUP_SHIFT 2
+#define RTC_CR_UM_MASK 0x8u
+#define RTC_CR_UM_SHIFT 3
+#define RTC_CR_OSCE_MASK 0x100u
+#define RTC_CR_OSCE_SHIFT 8
+#define RTC_CR_CLKO_MASK 0x200u
+#define RTC_CR_CLKO_SHIFT 9
+#define RTC_CR_SC16P_MASK 0x400u
+#define RTC_CR_SC16P_SHIFT 10
+#define RTC_CR_SC8P_MASK 0x800u
+#define RTC_CR_SC8P_SHIFT 11
+#define RTC_CR_SC4P_MASK 0x1000u
+#define RTC_CR_SC4P_SHIFT 12
+#define RTC_CR_SC2P_MASK 0x2000u
+#define RTC_CR_SC2P_SHIFT 13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK 0x1u
+#define RTC_SR_TIF_SHIFT 0
+#define RTC_SR_TOF_MASK 0x2u
+#define RTC_SR_TOF_SHIFT 1
+#define RTC_SR_TAF_MASK 0x4u
+#define RTC_SR_TAF_SHIFT 2
+#define RTC_SR_TCE_MASK 0x10u
+#define RTC_SR_TCE_SHIFT 4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK 0x8u
+#define RTC_LR_TCL_SHIFT 3
+#define RTC_LR_CRL_MASK 0x10u
+#define RTC_LR_CRL_SHIFT 4
+#define RTC_LR_SRL_MASK 0x20u
+#define RTC_LR_SRL_SHIFT 5
+#define RTC_LR_LRL_MASK 0x40u
+#define RTC_LR_LRL_SHIFT 6
+/* IER Bit Fields */
+#define RTC_IER_TIIE_MASK 0x1u
+#define RTC_IER_TIIE_SHIFT 0
+#define RTC_IER_TOIE_MASK 0x2u
+#define RTC_IER_TOIE_SHIFT 1
+#define RTC_IER_TAIE_MASK 0x4u
+#define RTC_IER_TAIE_SHIFT 2
+#define RTC_IER_TSIE_MASK 0x10u
+#define RTC_IER_TSIE_SHIFT 4
+#define RTC_IER_WPON_MASK 0x80u
+#define RTC_IER_WPON_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASES { RTC }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SIM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
+ __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
+ uint8_t RESERVED_0[4092];
+ __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
+ __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
+ uint8_t RESERVED_3[8];
+ __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
+ __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
+ __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
+ __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
+ __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
+ __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
+ uint8_t RESERVED_6[4];
+ __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
+ __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
+ __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
+ uint8_t RESERVED_7[156];
+ __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
+ __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SIM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT 18
+#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
+#define SIM_SOPT1_USBVSTBY_SHIFT 29
+#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
+#define SIM_SOPT1_USBSSTBY_SHIFT 30
+#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT 31
+/* SOPT1CFG Bit Fields */
+#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
+#define SIM_SOPT1CFG_URWE_SHIFT 24
+#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
+#define SIM_SOPT1CFG_UVSWE_SHIFT 25
+#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
+#define SIM_SOPT1CFG_USSWE_SHIFT 26
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
+#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
+#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
+#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
+#define SIM_SOPT2_USBSRC_MASK 0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT 18
+#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
+#define SIM_SOPT2_TPMSRC_SHIFT 24
+#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
+#define SIM_SOPT2_UART0SRC_SHIFT 26
+#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
+#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
+#define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
+#define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
+#define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
+#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
+#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
+#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
+#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
+#define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
+#define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT 0
+#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
+#define SIM_SOPT5_UART0RXSRC_SHIFT 2
+#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
+#define SIM_SOPT5_UART1TXSRC_SHIFT 4
+#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK 0x40u
+#define SIM_SOPT5_UART1RXSRC_SHIFT 6
+#define SIM_SOPT5_UART0ODE_MASK 0x10000u
+#define SIM_SOPT5_UART0ODE_SHIFT 16
+#define SIM_SOPT5_UART1ODE_MASK 0x20000u
+#define SIM_SOPT5_UART1ODE_SHIFT 17
+#define SIM_SOPT5_UART2ODE_MASK 0x40000u
+#define SIM_SOPT5_UART2ODE_SHIFT 18
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
+#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK 0xFu
+#define SIM_SDID_PINID_SHIFT 0
+#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_DIEID_MASK 0xF80u
+#define SIM_SDID_DIEID_SHIFT 7
+#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK 0xF000u
+#define SIM_SDID_REVID_SHIFT 12
+#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
+#define SIM_SDID_SRAMSIZE_SHIFT 16
+#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
+#define SIM_SDID_SERIESID_MASK 0xF00000u
+#define SIM_SDID_SERIESID_SHIFT 20
+#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK 0xF000000u
+#define SIM_SDID_SUBFAMID_SHIFT 24
+#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMID_MASK 0xF0000000u
+#define SIM_SDID_FAMID_SHIFT 28
+#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_I2C0_MASK 0x40u
+#define SIM_SCGC4_I2C0_SHIFT 6
+#define SIM_SCGC4_I2C1_MASK 0x80u
+#define SIM_SCGC4_I2C1_SHIFT 7
+#define SIM_SCGC4_UART0_MASK 0x400u
+#define SIM_SCGC4_UART0_SHIFT 10
+#define SIM_SCGC4_UART1_MASK 0x800u
+#define SIM_SCGC4_UART1_SHIFT 11
+#define SIM_SCGC4_UART2_MASK 0x1000u
+#define SIM_SCGC4_UART2_SHIFT 12
+#define SIM_SCGC4_USBOTG_MASK 0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT 18
+#define SIM_SCGC4_CMP_MASK 0x80000u
+#define SIM_SCGC4_CMP_SHIFT 19
+#define SIM_SCGC4_SPI0_MASK 0x400000u
+#define SIM_SCGC4_SPI0_SHIFT 22
+#define SIM_SCGC4_SPI1_MASK 0x800000u
+#define SIM_SCGC4_SPI1_SHIFT 23
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTMR_MASK 0x1u
+#define SIM_SCGC5_LPTMR_SHIFT 0
+#define SIM_SCGC5_TSI_MASK 0x20u
+#define SIM_SCGC5_TSI_SHIFT 5
+#define SIM_SCGC5_PORTA_MASK 0x200u
+#define SIM_SCGC5_PORTA_SHIFT 9
+#define SIM_SCGC5_PORTB_MASK 0x400u
+#define SIM_SCGC5_PORTB_SHIFT 10
+#define SIM_SCGC5_PORTC_MASK 0x800u
+#define SIM_SCGC5_PORTC_SHIFT 11
+#define SIM_SCGC5_PORTD_MASK 0x1000u
+#define SIM_SCGC5_PORTD_SHIFT 12
+#define SIM_SCGC5_PORTE_MASK 0x2000u
+#define SIM_SCGC5_PORTE_SHIFT 13
+#define SIM_SCGC5_SLCD_MASK 0x80000u
+#define SIM_SCGC5_SLCD_SHIFT 19
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTF_MASK 0x1u
+#define SIM_SCGC6_FTF_SHIFT 0
+#define SIM_SCGC6_DMAMUX_MASK 0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT 1
+#define SIM_SCGC6_I2S_MASK 0x8000u
+#define SIM_SCGC6_I2S_SHIFT 15
+#define SIM_SCGC6_PIT_MASK 0x800000u
+#define SIM_SCGC6_PIT_SHIFT 23
+#define SIM_SCGC6_TPM0_MASK 0x1000000u
+#define SIM_SCGC6_TPM0_SHIFT 24
+#define SIM_SCGC6_TPM1_MASK 0x2000000u
+#define SIM_SCGC6_TPM1_SHIFT 25
+#define SIM_SCGC6_TPM2_MASK 0x4000000u
+#define SIM_SCGC6_TPM2_SHIFT 26
+#define SIM_SCGC6_ADC0_MASK 0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT 27
+#define SIM_SCGC6_RTC_MASK 0x20000000u
+#define SIM_SCGC6_RTC_SHIFT 29
+#define SIM_SCGC6_DAC0_MASK 0x80000000u
+#define SIM_SCGC6_DAC0_SHIFT 31
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_DMA_MASK 0x100u
+#define SIM_SCGC7_DMA_SHIFT 8
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
+#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
+#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_FLASHDIS_MASK 0x1u
+#define SIM_FCFG1_FLASHDIS_SHIFT 0
+#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
+#define SIM_FCFG1_FLASHDOZE_SHIFT 1
+#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
+#define SIM_FCFG1_PFSIZE_SHIFT 24
+#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT 16
+#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT 24
+#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK 0xFFFFu
+#define SIM_UIDMH_UID_SHIFT 0
+#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT 0
+#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT 0
+#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+/* COPC Bit Fields */
+#define SIM_COPC_COPW_MASK 0x1u
+#define SIM_COPC_COPW_SHIFT 0
+#define SIM_COPC_COPCLKS_MASK 0x2u
+#define SIM_COPC_COPCLKS_SHIFT 1
+#define SIM_COPC_COPT_MASK 0xCu
+#define SIM_COPC_COPT_SHIFT 2
+#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
+/* SRVCOP Bit Fields */
+#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
+#define SIM_SRVCOP_SRVCOP_SHIFT 0
+#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASES { SIM }
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
+ __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
+ __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
+ __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/* PMPROT Bit Fields */
+#define SMC_PMPROT_AVLLS_MASK 0x2u
+#define SMC_PMPROT_AVLLS_SHIFT 1
+#define SMC_PMPROT_ALLS_MASK 0x8u
+#define SMC_PMPROT_ALLS_SHIFT 3
+#define SMC_PMPROT_AVLP_MASK 0x20u
+#define SMC_PMPROT_AVLP_SHIFT 5
+/* PMCTRL Bit Fields */
+#define SMC_PMCTRL_STOPM_MASK 0x7u
+#define SMC_PMCTRL_STOPM_SHIFT 0
+#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK 0x8u
+#define SMC_PMCTRL_STOPA_SHIFT 3
+#define SMC_PMCTRL_RUNM_MASK 0x60u
+#define SMC_PMCTRL_RUNM_SHIFT 5
+#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
+/* STOPCTRL Bit Fields */
+#define SMC_STOPCTRL_VLLSM_MASK 0x7u
+#define SMC_STOPCTRL_VLLSM_SHIFT 0
+#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
+#define SMC_STOPCTRL_PORPO_MASK 0x20u
+#define SMC_STOPCTRL_PORPO_SHIFT 5
+#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
+#define SMC_STOPCTRL_PSTOPO_SHIFT 6
+#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
+/* PMSTAT Bit Fields */
+#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
+#define SMC_PMSTAT_PMSTAT_SHIFT 0
+#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASES { SMC }
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ __I uint8_t S; /**< SPI status register, offset: 0x0 */
+ __IO uint8_t BR; /**< SPI baud rate register, offset: 0x1 */
+ __IO uint8_t C2; /**< SPI control register 2, offset: 0x2 */
+ __IO uint8_t C1; /**< SPI control register 1, offset: 0x3 */
+ __IO uint8_t ML; /**< SPI match register low, offset: 0x4 */
+ __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
+ __IO uint8_t DL; /**< SPI data register low, offset: 0x6 */
+ __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
+ uint8_t RESERVED_0[2];
+ __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
+ __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/* S Bit Fields */
+#define SPI_S_RFIFOEF_MASK 0x1u
+#define SPI_S_RFIFOEF_SHIFT 0
+#define SPI_S_TXFULLF_MASK 0x2u
+#define SPI_S_TXFULLF_SHIFT 1
+#define SPI_S_TNEAREF_MASK 0x4u
+#define SPI_S_TNEAREF_SHIFT 2
+#define SPI_S_RNFULLF_MASK 0x8u
+#define SPI_S_RNFULLF_SHIFT 3
+#define SPI_S_MODF_MASK 0x10u
+#define SPI_S_MODF_SHIFT 4
+#define SPI_S_SPTEF_MASK 0x20u
+#define SPI_S_SPTEF_SHIFT 5
+#define SPI_S_SPMF_MASK 0x40u
+#define SPI_S_SPMF_SHIFT 6
+#define SPI_S_SPRF_MASK 0x80u
+#define SPI_S_SPRF_SHIFT 7
+/* BR Bit Fields */
+#define SPI_BR_SPR_MASK 0xFu
+#define SPI_BR_SPR_SHIFT 0
+#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
+#define SPI_BR_SPPR_MASK 0x70u
+#define SPI_BR_SPPR_SHIFT 4
+#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
+/* C2 Bit Fields */
+#define SPI_C2_SPC0_MASK 0x1u
+#define SPI_C2_SPC0_SHIFT 0
+#define SPI_C2_SPISWAI_MASK 0x2u
+#define SPI_C2_SPISWAI_SHIFT 1
+#define SPI_C2_RXDMAE_MASK 0x4u
+#define SPI_C2_RXDMAE_SHIFT 2
+#define SPI_C2_BIDIROE_MASK 0x8u
+#define SPI_C2_BIDIROE_SHIFT 3
+#define SPI_C2_MODFEN_MASK 0x10u
+#define SPI_C2_MODFEN_SHIFT 4
+#define SPI_C2_TXDMAE_MASK 0x20u
+#define SPI_C2_TXDMAE_SHIFT 5
+#define SPI_C2_SPIMODE_MASK 0x40u
+#define SPI_C2_SPIMODE_SHIFT 6
+#define SPI_C2_SPMIE_MASK 0x80u
+#define SPI_C2_SPMIE_SHIFT 7
+/* C1 Bit Fields */
+#define SPI_C1_LSBFE_MASK 0x1u
+#define SPI_C1_LSBFE_SHIFT 0
+#define SPI_C1_SSOE_MASK 0x2u
+#define SPI_C1_SSOE_SHIFT 1
+#define SPI_C1_CPHA_MASK 0x4u
+#define SPI_C1_CPHA_SHIFT 2
+#define SPI_C1_CPOL_MASK 0x8u
+#define SPI_C1_CPOL_SHIFT 3
+#define SPI_C1_MSTR_MASK 0x10u
+#define SPI_C1_MSTR_SHIFT 4
+#define SPI_C1_SPTIE_MASK 0x20u
+#define SPI_C1_SPTIE_SHIFT 5
+#define SPI_C1_SPE_MASK 0x40u
+#define SPI_C1_SPE_SHIFT 6
+#define SPI_C1_SPIE_MASK 0x80u
+#define SPI_C1_SPIE_SHIFT 7
+/* ML Bit Fields */
+#define SPI_ML_Bits_MASK 0xFFu
+#define SPI_ML_Bits_SHIFT 0
+#define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
+/* MH Bit Fields */
+#define SPI_MH_Bits_MASK 0xFFu
+#define SPI_MH_Bits_SHIFT 0
+#define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
+/* DL Bit Fields */
+#define SPI_DL_Bits_MASK 0xFFu
+#define SPI_DL_Bits_SHIFT 0
+#define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
+/* DH Bit Fields */
+#define SPI_DH_Bits_MASK 0xFFu
+#define SPI_DH_Bits_SHIFT 0
+#define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
+/* CI Bit Fields */
+#define SPI_CI_SPRFCI_MASK 0x1u
+#define SPI_CI_SPRFCI_SHIFT 0
+#define SPI_CI_SPTEFCI_MASK 0x2u
+#define SPI_CI_SPTEFCI_SHIFT 1
+#define SPI_CI_RNFULLFCI_MASK 0x4u
+#define SPI_CI_RNFULLFCI_SHIFT 2
+#define SPI_CI_TNEAREFCI_MASK 0x8u
+#define SPI_CI_TNEAREFCI_SHIFT 3
+#define SPI_CI_RXFOF_MASK 0x10u
+#define SPI_CI_RXFOF_SHIFT 4
+#define SPI_CI_TXFOF_MASK 0x20u
+#define SPI_CI_TXFOF_SHIFT 5
+#define SPI_CI_RXFERR_MASK 0x40u
+#define SPI_CI_RXFERR_SHIFT 6
+#define SPI_CI_TXFERR_MASK 0x80u
+#define SPI_CI_TXFERR_SHIFT 7
+/* C3 Bit Fields */
+#define SPI_C3_FIFOMODE_MASK 0x1u
+#define SPI_C3_FIFOMODE_SHIFT 0
+#define SPI_C3_RNFULLIEN_MASK 0x2u
+#define SPI_C3_RNFULLIEN_SHIFT 1
+#define SPI_C3_TNEARIEN_MASK 0x4u
+#define SPI_C3_TNEARIEN_SHIFT 2
+#define SPI_C3_INTCLR_MASK 0x8u
+#define SPI_C3_INTCLR_SHIFT 3
+#define SPI_C3_RNFULLF_MARK_MASK 0x10u
+#define SPI_C3_RNFULLF_MARK_SHIFT 4
+#define SPI_C3_TNEAREF_MARK_MASK 0x20u
+#define SPI_C3_TNEAREF_MARK_SHIFT 5
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x40076000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x40077000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASES { SPI0, SPI1 }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TPM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
+ __IO uint32_t CNT; /**< Counter, offset: 0x4 */
+ __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
+ struct { /* offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+ __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+ } CONTROLS[6];
+ uint8_t RESERVED_0[20];
+ __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
+ uint8_t RESERVED_1[48];
+ __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TPM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/* SC Bit Fields */
+#define TPM_SC_PS_MASK 0x7u
+#define TPM_SC_PS_SHIFT 0
+#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK 0x18u
+#define TPM_SC_CMOD_SHIFT 3
+#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK 0x20u
+#define TPM_SC_CPWMS_SHIFT 5
+#define TPM_SC_TOIE_MASK 0x40u
+#define TPM_SC_TOIE_SHIFT 6
+#define TPM_SC_TOF_MASK 0x80u
+#define TPM_SC_TOF_SHIFT 7
+#define TPM_SC_DMA_MASK 0x100u
+#define TPM_SC_DMA_SHIFT 8
+/* CNT Bit Fields */
+#define TPM_CNT_COUNT_MASK 0xFFFFu
+#define TPM_CNT_COUNT_SHIFT 0
+#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define TPM_MOD_MOD_MASK 0xFFFFu
+#define TPM_MOD_MOD_SHIFT 0
+#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define TPM_CnSC_DMA_MASK 0x1u
+#define TPM_CnSC_DMA_SHIFT 0
+#define TPM_CnSC_ELSA_MASK 0x4u
+#define TPM_CnSC_ELSA_SHIFT 2
+#define TPM_CnSC_ELSB_MASK 0x8u
+#define TPM_CnSC_ELSB_SHIFT 3
+#define TPM_CnSC_MSA_MASK 0x10u
+#define TPM_CnSC_MSA_SHIFT 4
+#define TPM_CnSC_MSB_MASK 0x20u
+#define TPM_CnSC_MSB_SHIFT 5
+#define TPM_CnSC_CHIE_MASK 0x40u
+#define TPM_CnSC_CHIE_SHIFT 6
+#define TPM_CnSC_CHF_MASK 0x80u
+#define TPM_CnSC_CHF_SHIFT 7
+/* CnV Bit Fields */
+#define TPM_CnV_VAL_MASK 0xFFFFu
+#define TPM_CnV_VAL_SHIFT 0
+#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
+/* STATUS Bit Fields */
+#define TPM_STATUS_CH0F_MASK 0x1u
+#define TPM_STATUS_CH0F_SHIFT 0
+#define TPM_STATUS_CH1F_MASK 0x2u
+#define TPM_STATUS_CH1F_SHIFT 1
+#define TPM_STATUS_CH2F_MASK 0x4u
+#define TPM_STATUS_CH2F_SHIFT 2
+#define TPM_STATUS_CH3F_MASK 0x8u
+#define TPM_STATUS_CH3F_SHIFT 3
+#define TPM_STATUS_CH4F_MASK 0x10u
+#define TPM_STATUS_CH4F_SHIFT 4
+#define TPM_STATUS_CH5F_MASK 0x20u
+#define TPM_STATUS_CH5F_SHIFT 5
+#define TPM_STATUS_TOF_MASK 0x100u
+#define TPM_STATUS_TOF_SHIFT 8
+/* CONF Bit Fields */
+#define TPM_CONF_DOZEEN_MASK 0x20u
+#define TPM_CONF_DOZEEN_SHIFT 5
+#define TPM_CONF_DBGMODE_MASK 0xC0u
+#define TPM_CONF_DBGMODE_SHIFT 6
+#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBEEN_MASK 0x200u
+#define TPM_CONF_GTBEEN_SHIFT 9
+#define TPM_CONF_CSOT_MASK 0x10000u
+#define TPM_CONF_CSOT_SHIFT 16
+#define TPM_CONF_CSOO_MASK 0x20000u
+#define TPM_CONF_CSOO_SHIFT 17
+#define TPM_CONF_CROT_MASK 0x40000u
+#define TPM_CONF_CROT_SHIFT 18
+#define TPM_CONF_TRGSEL_MASK 0xF000000u
+#define TPM_CONF_TRGSEL_SHIFT 24
+#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM0 base address */
+#define TPM0_BASE (0x40038000u)
+/** Peripheral TPM0 base pointer */
+#define TPM0 ((TPM_Type *)TPM0_BASE)
+/** Peripheral TPM1 base address */
+#define TPM1_BASE (0x40039000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1 ((TPM_Type *)TPM1_BASE)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE (0x4003A000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2 ((TPM_Type *)TPM2_BASE)
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASES { TPM0, TPM1, TPM2 }
+
+/*!
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- TSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
+ __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
+ __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- TSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/* GENCS Bit Fields */
+#define TSI_GENCS_CURSW_MASK 0x2u
+#define TSI_GENCS_CURSW_SHIFT 1
+#define TSI_GENCS_EOSF_MASK 0x4u
+#define TSI_GENCS_EOSF_SHIFT 2
+#define TSI_GENCS_SCNIP_MASK 0x8u
+#define TSI_GENCS_SCNIP_SHIFT 3
+#define TSI_GENCS_STM_MASK 0x10u
+#define TSI_GENCS_STM_SHIFT 4
+#define TSI_GENCS_STPE_MASK 0x20u
+#define TSI_GENCS_STPE_SHIFT 5
+#define TSI_GENCS_TSIIEN_MASK 0x40u
+#define TSI_GENCS_TSIIEN_SHIFT 6
+#define TSI_GENCS_TSIEN_MASK 0x80u
+#define TSI_GENCS_TSIEN_SHIFT 7
+#define TSI_GENCS_NSCN_MASK 0x1F00u
+#define TSI_GENCS_NSCN_SHIFT 8
+#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_PS_MASK 0xE000u
+#define TSI_GENCS_PS_SHIFT 13
+#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
+#define TSI_GENCS_EXTCHRG_MASK 0x70000u
+#define TSI_GENCS_EXTCHRG_SHIFT 16
+#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_DVOLT_MASK 0x180000u
+#define TSI_GENCS_DVOLT_SHIFT 19
+#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_REFCHRG_MASK 0xE00000u
+#define TSI_GENCS_REFCHRG_SHIFT 21
+#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_MODE_MASK 0xF000000u
+#define TSI_GENCS_MODE_SHIFT 24
+#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_ESOR_MASK 0x10000000u
+#define TSI_GENCS_ESOR_SHIFT 28
+#define TSI_GENCS_OUTRGF_MASK 0x80000000u
+#define TSI_GENCS_OUTRGF_SHIFT 31
+/* DATA Bit Fields */
+#define TSI_DATA_TSICNT_MASK 0xFFFFu
+#define TSI_DATA_TSICNT_SHIFT 0
+#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_SWTS_MASK 0x400000u
+#define TSI_DATA_SWTS_SHIFT 22
+#define TSI_DATA_DMAEN_MASK 0x800000u
+#define TSI_DATA_DMAEN_SHIFT 23
+#define TSI_DATA_TSICH_MASK 0xF0000000u
+#define TSI_DATA_TSICH_SHIFT 28
+#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
+/* TSHD Bit Fields */
+#define TSI_TSHD_THRESL_MASK 0xFFFFu
+#define TSI_TSHD_THRESL_SHIFT 0
+#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
+#define TSI_TSHD_THRESH_SHIFT 16
+#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
+
+/*!
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0 ((TSI_Type *)TSI0_BASE)
+/** Array initializer of TSI peripheral base pointers */
+#define TSI_BASES { TSI0 }
+
+/*!
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK 0x1Fu
+#define UART_BDH_SBR_SHIFT 0
+#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK 0x20u
+#define UART_BDH_SBNS_SHIFT 5
+#define UART_BDH_RXEDGIE_MASK 0x40u
+#define UART_BDH_RXEDGIE_SHIFT 6
+#define UART_BDH_LBKDIE_MASK 0x80u
+#define UART_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK 0xFFu
+#define UART_BDL_SBR_SHIFT 0
+#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK 0x1u
+#define UART_C1_PT_SHIFT 0
+#define UART_C1_PE_MASK 0x2u
+#define UART_C1_PE_SHIFT 1
+#define UART_C1_ILT_MASK 0x4u
+#define UART_C1_ILT_SHIFT 2
+#define UART_C1_WAKE_MASK 0x8u
+#define UART_C1_WAKE_SHIFT 3
+#define UART_C1_M_MASK 0x10u
+#define UART_C1_M_SHIFT 4
+#define UART_C1_RSRC_MASK 0x20u
+#define UART_C1_RSRC_SHIFT 5
+#define UART_C1_UARTSWAI_MASK 0x40u
+#define UART_C1_UARTSWAI_SHIFT 6
+#define UART_C1_LOOPS_MASK 0x80u
+#define UART_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK 0x1u
+#define UART_C2_SBK_SHIFT 0
+#define UART_C2_RWU_MASK 0x2u
+#define UART_C2_RWU_SHIFT 1
+#define UART_C2_RE_MASK 0x4u
+#define UART_C2_RE_SHIFT 2
+#define UART_C2_TE_MASK 0x8u
+#define UART_C2_TE_SHIFT 3
+#define UART_C2_ILIE_MASK 0x10u
+#define UART_C2_ILIE_SHIFT 4
+#define UART_C2_RIE_MASK 0x20u
+#define UART_C2_RIE_SHIFT 5
+#define UART_C2_TCIE_MASK 0x40u
+#define UART_C2_TCIE_SHIFT 6
+#define UART_C2_TIE_MASK 0x80u
+#define UART_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK 0x1u
+#define UART_S1_PF_SHIFT 0
+#define UART_S1_FE_MASK 0x2u
+#define UART_S1_FE_SHIFT 1
+#define UART_S1_NF_MASK 0x4u
+#define UART_S1_NF_SHIFT 2
+#define UART_S1_OR_MASK 0x8u
+#define UART_S1_OR_SHIFT 3
+#define UART_S1_IDLE_MASK 0x10u
+#define UART_S1_IDLE_SHIFT 4
+#define UART_S1_RDRF_MASK 0x20u
+#define UART_S1_RDRF_SHIFT 5
+#define UART_S1_TC_MASK 0x40u
+#define UART_S1_TC_SHIFT 6
+#define UART_S1_TDRE_MASK 0x80u
+#define UART_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK 0x1u
+#define UART_S2_RAF_SHIFT 0
+#define UART_S2_LBKDE_MASK 0x2u
+#define UART_S2_LBKDE_SHIFT 1
+#define UART_S2_BRK13_MASK 0x4u
+#define UART_S2_BRK13_SHIFT 2
+#define UART_S2_RWUID_MASK 0x8u
+#define UART_S2_RWUID_SHIFT 3
+#define UART_S2_RXINV_MASK 0x10u
+#define UART_S2_RXINV_SHIFT 4
+#define UART_S2_RXEDGIF_MASK 0x40u
+#define UART_S2_RXEDGIF_SHIFT 6
+#define UART_S2_LBKDIF_MASK 0x80u
+#define UART_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK 0x1u
+#define UART_C3_PEIE_SHIFT 0
+#define UART_C3_FEIE_MASK 0x2u
+#define UART_C3_FEIE_SHIFT 1
+#define UART_C3_NEIE_MASK 0x4u
+#define UART_C3_NEIE_SHIFT 2
+#define UART_C3_ORIE_MASK 0x8u
+#define UART_C3_ORIE_SHIFT 3
+#define UART_C3_TXINV_MASK 0x10u
+#define UART_C3_TXINV_SHIFT 4
+#define UART_C3_TXDIR_MASK 0x20u
+#define UART_C3_TXDIR_SHIFT 5
+#define UART_C3_T8_MASK 0x40u
+#define UART_C3_T8_SHIFT 6
+#define UART_C3_R8_MASK 0x80u
+#define UART_C3_R8_SHIFT 7
+/* D Bit Fields */
+#define UART_D_R0T0_MASK 0x1u
+#define UART_D_R0T0_SHIFT 0
+#define UART_D_R1T1_MASK 0x2u
+#define UART_D_R1T1_SHIFT 1
+#define UART_D_R2T2_MASK 0x4u
+#define UART_D_R2T2_SHIFT 2
+#define UART_D_R3T3_MASK 0x8u
+#define UART_D_R3T3_SHIFT 3
+#define UART_D_R4T4_MASK 0x10u
+#define UART_D_R4T4_SHIFT 4
+#define UART_D_R5T5_MASK 0x20u
+#define UART_D_R5T5_SHIFT 5
+#define UART_D_R6T6_MASK 0x40u
+#define UART_D_R6T6_SHIFT 6
+#define UART_D_R7T7_MASK 0x80u
+#define UART_D_R7T7_SHIFT 7
+/* C4 Bit Fields */
+#define UART_C4_RDMAS_MASK 0x20u
+#define UART_C4_RDMAS_SHIFT 5
+#define UART_C4_TDMAS_MASK 0x80u
+#define UART_C4_TDMAS_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART1 base address */
+#define UART1_BASE (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1 ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2 ((UART_Type *)UART2_BASE)
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASES { UART1, UART2 }
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UART0 Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer
+ * @{
+ */
+
+/** UART0 - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */
+ __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */
+ __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
+ __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
+ __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
+ __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
+ __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
+ __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
+ __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
+ __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
+ __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
+ __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
+} UART0_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UART0 Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART0_Register_Masks UART0 Register Masks
+ * @{
+ */
+
+/* BDH Bit Fields */
+#define UART0_BDH_SBR_MASK 0x1Fu
+#define UART0_BDH_SBR_SHIFT 0
+#define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK)
+#define UART0_BDH_SBNS_MASK 0x20u
+#define UART0_BDH_SBNS_SHIFT 5
+#define UART0_BDH_RXEDGIE_MASK 0x40u
+#define UART0_BDH_RXEDGIE_SHIFT 6
+#define UART0_BDH_LBKDIE_MASK 0x80u
+#define UART0_BDH_LBKDIE_SHIFT 7
+/* BDL Bit Fields */
+#define UART0_BDL_SBR_MASK 0xFFu
+#define UART0_BDL_SBR_SHIFT 0
+#define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART0_C1_PT_MASK 0x1u
+#define UART0_C1_PT_SHIFT 0
+#define UART0_C1_PE_MASK 0x2u
+#define UART0_C1_PE_SHIFT 1
+#define UART0_C1_ILT_MASK 0x4u
+#define UART0_C1_ILT_SHIFT 2
+#define UART0_C1_WAKE_MASK 0x8u
+#define UART0_C1_WAKE_SHIFT 3
+#define UART0_C1_M_MASK 0x10u
+#define UART0_C1_M_SHIFT 4
+#define UART0_C1_RSRC_MASK 0x20u
+#define UART0_C1_RSRC_SHIFT 5
+#define UART0_C1_DOZEEN_MASK 0x40u
+#define UART0_C1_DOZEEN_SHIFT 6
+#define UART0_C1_LOOPS_MASK 0x80u
+#define UART0_C1_LOOPS_SHIFT 7
+/* C2 Bit Fields */
+#define UART0_C2_SBK_MASK 0x1u
+#define UART0_C2_SBK_SHIFT 0
+#define UART0_C2_RWU_MASK 0x2u
+#define UART0_C2_RWU_SHIFT 1
+#define UART0_C2_RE_MASK 0x4u
+#define UART0_C2_RE_SHIFT 2
+#define UART0_C2_TE_MASK 0x8u
+#define UART0_C2_TE_SHIFT 3
+#define UART0_C2_ILIE_MASK 0x10u
+#define UART0_C2_ILIE_SHIFT 4
+#define UART0_C2_RIE_MASK 0x20u
+#define UART0_C2_RIE_SHIFT 5
+#define UART0_C2_TCIE_MASK 0x40u
+#define UART0_C2_TCIE_SHIFT 6
+#define UART0_C2_TIE_MASK 0x80u
+#define UART0_C2_TIE_SHIFT 7
+/* S1 Bit Fields */
+#define UART0_S1_PF_MASK 0x1u
+#define UART0_S1_PF_SHIFT 0
+#define UART0_S1_FE_MASK 0x2u
+#define UART0_S1_FE_SHIFT 1
+#define UART0_S1_NF_MASK 0x4u
+#define UART0_S1_NF_SHIFT 2
+#define UART0_S1_OR_MASK 0x8u
+#define UART0_S1_OR_SHIFT 3
+#define UART0_S1_IDLE_MASK 0x10u
+#define UART0_S1_IDLE_SHIFT 4
+#define UART0_S1_RDRF_MASK 0x20u
+#define UART0_S1_RDRF_SHIFT 5
+#define UART0_S1_TC_MASK 0x40u
+#define UART0_S1_TC_SHIFT 6
+#define UART0_S1_TDRE_MASK 0x80u
+#define UART0_S1_TDRE_SHIFT 7
+/* S2 Bit Fields */
+#define UART0_S2_RAF_MASK 0x1u
+#define UART0_S2_RAF_SHIFT 0
+#define UART0_S2_LBKDE_MASK 0x2u
+#define UART0_S2_LBKDE_SHIFT 1
+#define UART0_S2_BRK13_MASK 0x4u
+#define UART0_S2_BRK13_SHIFT 2
+#define UART0_S2_RWUID_MASK 0x8u
+#define UART0_S2_RWUID_SHIFT 3
+#define UART0_S2_RXINV_MASK 0x10u
+#define UART0_S2_RXINV_SHIFT 4
+#define UART0_S2_MSBF_MASK 0x20u
+#define UART0_S2_MSBF_SHIFT 5
+#define UART0_S2_RXEDGIF_MASK 0x40u
+#define UART0_S2_RXEDGIF_SHIFT 6
+#define UART0_S2_LBKDIF_MASK 0x80u
+#define UART0_S2_LBKDIF_SHIFT 7
+/* C3 Bit Fields */
+#define UART0_C3_PEIE_MASK 0x1u
+#define UART0_C3_PEIE_SHIFT 0
+#define UART0_C3_FEIE_MASK 0x2u
+#define UART0_C3_FEIE_SHIFT 1
+#define UART0_C3_NEIE_MASK 0x4u
+#define UART0_C3_NEIE_SHIFT 2
+#define UART0_C3_ORIE_MASK 0x8u
+#define UART0_C3_ORIE_SHIFT 3
+#define UART0_C3_TXINV_MASK 0x10u
+#define UART0_C3_TXINV_SHIFT 4
+#define UART0_C3_TXDIR_MASK 0x20u
+#define UART0_C3_TXDIR_SHIFT 5
+#define UART0_C3_R9T8_MASK 0x40u
+#define UART0_C3_R9T8_SHIFT 6
+#define UART0_C3_R8T9_MASK 0x80u
+#define UART0_C3_R8T9_SHIFT 7
+/* D Bit Fields */
+#define UART0_D_R0T0_MASK 0x1u
+#define UART0_D_R0T0_SHIFT 0
+#define UART0_D_R1T1_MASK 0x2u
+#define UART0_D_R1T1_SHIFT 1
+#define UART0_D_R2T2_MASK 0x4u
+#define UART0_D_R2T2_SHIFT 2
+#define UART0_D_R3T3_MASK 0x8u
+#define UART0_D_R3T3_SHIFT 3
+#define UART0_D_R4T4_MASK 0x10u
+#define UART0_D_R4T4_SHIFT 4
+#define UART0_D_R5T5_MASK 0x20u
+#define UART0_D_R5T5_SHIFT 5
+#define UART0_D_R6T6_MASK 0x40u
+#define UART0_D_R6T6_SHIFT 6
+#define UART0_D_R7T7_MASK 0x80u
+#define UART0_D_R7T7_SHIFT 7
+/* MA1 Bit Fields */
+#define UART0_MA1_MA_MASK 0xFFu
+#define UART0_MA1_MA_SHIFT 0
+#define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART0_MA2_MA_MASK 0xFFu
+#define UART0_MA2_MA_SHIFT 0
+#define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART0_C4_OSR_MASK 0x1Fu
+#define UART0_C4_OSR_SHIFT 0
+#define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK)
+#define UART0_C4_M10_MASK 0x20u
+#define UART0_C4_M10_SHIFT 5
+#define UART0_C4_MAEN2_MASK 0x40u
+#define UART0_C4_MAEN2_SHIFT 6
+#define UART0_C4_MAEN1_MASK 0x80u
+#define UART0_C4_MAEN1_SHIFT 7
+/* C5 Bit Fields */
+#define UART0_C5_RESYNCDIS_MASK 0x1u
+#define UART0_C5_RESYNCDIS_SHIFT 0
+#define UART0_C5_BOTHEDGE_MASK 0x2u
+#define UART0_C5_BOTHEDGE_SHIFT 1
+#define UART0_C5_RDMAE_MASK 0x20u
+#define UART0_C5_RDMAE_SHIFT 5
+#define UART0_C5_TDMAE_MASK 0x80u
+#define UART0_C5_TDMAE_SHIFT 7
+
+/*!
+ * @}
+ */ /* end of group UART0_Register_Masks */
+
+
+/* UART0 - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0 ((UART0_Type *)UART0_BASE)
+/** Array initializer of UART0 peripheral base pointers */
+#define UART0_BASES { UART0 }
+
+/*!
+ * @}
+ */ /* end of group UART0_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
+ uint8_t RESERVED_0[3];
+ __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
+ uint8_t RESERVED_1[3];
+ __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
+ uint8_t RESERVED_2[3];
+ __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
+ uint8_t RESERVED_3[3];
+ __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
+ uint8_t RESERVED_4[3];
+ __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */
+ uint8_t RESERVED_5[3];
+ __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
+ uint8_t RESERVED_6[3];
+ __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
+ uint8_t RESERVED_7[99];
+ __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
+ uint8_t RESERVED_8[3];
+ __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
+ uint8_t RESERVED_9[3];
+ __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
+ uint8_t RESERVED_10[3];
+ __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
+ uint8_t RESERVED_11[3];
+ __I uint8_t STAT; /**< Status register, offset: 0x90 */
+ uint8_t RESERVED_12[3];
+ __IO uint8_t CTL; /**< Control register, offset: 0x94 */
+ uint8_t RESERVED_13[3];
+ __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
+ uint8_t RESERVED_14[3];
+ __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */
+ uint8_t RESERVED_15[3];
+ __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */
+ uint8_t RESERVED_16[3];
+ __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */
+ uint8_t RESERVED_17[3];
+ __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
+ uint8_t RESERVED_18[3];
+ __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */
+ uint8_t RESERVED_19[3];
+ __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
+ uint8_t RESERVED_20[3];
+ __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
+ uint8_t RESERVED_21[11];
+ struct { /* offset: 0xC0, array step: 0x4 */
+ __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_0[3];
+ } ENDPOINT[16];
+ __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
+ uint8_t RESERVED_22[3];
+ __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
+ uint8_t RESERVED_23[3];
+ __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
+ uint8_t RESERVED_24[3];
+ __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */
+ uint8_t RESERVED_25[7];
+ __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK 0x3Fu
+#define USB_PERID_ID_SHIFT 0
+#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK 0x3Fu
+#define USB_IDCOMP_NID_SHIFT 0
+#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK 0xFFu
+#define USB_REV_REV_SHIFT 0
+#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK 0x1u
+#define USB_ADDINFO_IEHOST_SHIFT 0
+#define USB_ADDINFO_IRQNUM_MASK 0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT 3
+#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
+#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
+#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
+#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT 6
+#define USB_OTGISTAT_IDCHG_MASK 0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK 0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT 0
+#define USB_OTGICR_BSESSEN_MASK 0x4u
+#define USB_OTGICR_BSESSEN_SHIFT 2
+#define USB_OTGICR_SESSVLDEN_MASK 0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT 3
+#define USB_OTGICR_LINESTATEEN_MASK 0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT 5
+#define USB_OTGICR_ONEMSECEN_MASK 0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT 6
+#define USB_OTGICR_IDEN_MASK 0x80u
+#define USB_OTGICR_IDEN_SHIFT 7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
+#define USB_OTGSTAT_BSESSEND_MASK 0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT 2
+#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT 3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
+#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
+#define USB_OTGSTAT_ID_MASK 0x80u
+#define USB_OTGSTAT_ID_SHIFT 7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK 0x4u
+#define USB_OTGCTL_OTGEN_SHIFT 2
+#define USB_OTGCTL_DMLOW_MASK 0x10u
+#define USB_OTGCTL_DMLOW_SHIFT 4
+#define USB_OTGCTL_DPLOW_MASK 0x20u
+#define USB_OTGCTL_DPLOW_SHIFT 5
+#define USB_OTGCTL_DPHIGH_MASK 0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT 7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK 0x1u
+#define USB_ISTAT_USBRST_SHIFT 0
+#define USB_ISTAT_ERROR_MASK 0x2u
+#define USB_ISTAT_ERROR_SHIFT 1
+#define USB_ISTAT_SOFTOK_MASK 0x4u
+#define USB_ISTAT_SOFTOK_SHIFT 2
+#define USB_ISTAT_TOKDNE_MASK 0x8u
+#define USB_ISTAT_TOKDNE_SHIFT 3
+#define USB_ISTAT_SLEEP_MASK 0x10u
+#define USB_ISTAT_SLEEP_SHIFT 4
+#define USB_ISTAT_RESUME_MASK 0x20u
+#define USB_ISTAT_RESUME_SHIFT 5
+#define USB_ISTAT_ATTACH_MASK 0x40u
+#define USB_ISTAT_ATTACH_SHIFT 6
+#define USB_ISTAT_STALL_MASK 0x80u
+#define USB_ISTAT_STALL_SHIFT 7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK 0x1u
+#define USB_INTEN_USBRSTEN_SHIFT 0
+#define USB_INTEN_ERROREN_MASK 0x2u
+#define USB_INTEN_ERROREN_SHIFT 1
+#define USB_INTEN_SOFTOKEN_MASK 0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT 2
+#define USB_INTEN_TOKDNEEN_MASK 0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT 3
+#define USB_INTEN_SLEEPEN_MASK 0x10u
+#define USB_INTEN_SLEEPEN_SHIFT 4
+#define USB_INTEN_RESUMEEN_MASK 0x20u
+#define USB_INTEN_RESUMEEN_SHIFT 5
+#define USB_INTEN_ATTACHEN_MASK 0x40u
+#define USB_INTEN_ATTACHEN_SHIFT 6
+#define USB_INTEN_STALLEN_MASK 0x80u
+#define USB_INTEN_STALLEN_SHIFT 7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK 0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT 0
+#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT 1
+#define USB_ERRSTAT_CRC16_MASK 0x4u
+#define USB_ERRSTAT_CRC16_SHIFT 2
+#define USB_ERRSTAT_DFN8_MASK 0x8u
+#define USB_ERRSTAT_DFN8_SHIFT 3
+#define USB_ERRSTAT_BTOERR_MASK 0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT 4
+#define USB_ERRSTAT_DMAERR_MASK 0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT 5
+#define USB_ERRSTAT_BTSERR_MASK 0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK 0x1u
+#define USB_ERREN_PIDERREN_SHIFT 0
+#define USB_ERREN_CRC5EOFEN_MASK 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT 1
+#define USB_ERREN_CRC16EN_MASK 0x4u
+#define USB_ERREN_CRC16EN_SHIFT 2
+#define USB_ERREN_DFN8EN_MASK 0x8u
+#define USB_ERREN_DFN8EN_SHIFT 3
+#define USB_ERREN_BTOERREN_MASK 0x10u
+#define USB_ERREN_BTOERREN_SHIFT 4
+#define USB_ERREN_DMAERREN_MASK 0x20u
+#define USB_ERREN_DMAERREN_SHIFT 5
+#define USB_ERREN_BTSERREN_MASK 0x80u
+#define USB_ERREN_BTSERREN_SHIFT 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK 0x4u
+#define USB_STAT_ODD_SHIFT 2
+#define USB_STAT_TX_MASK 0x8u
+#define USB_STAT_TX_SHIFT 3
+#define USB_STAT_ENDP_MASK 0xF0u
+#define USB_STAT_ENDP_SHIFT 4
+#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK 0x1u
+#define USB_CTL_USBENSOFEN_SHIFT 0
+#define USB_CTL_ODDRST_MASK 0x2u
+#define USB_CTL_ODDRST_SHIFT 1
+#define USB_CTL_RESUME_MASK 0x4u
+#define USB_CTL_RESUME_SHIFT 2
+#define USB_CTL_HOSTMODEEN_MASK 0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT 3
+#define USB_CTL_RESET_MASK 0x10u
+#define USB_CTL_RESET_SHIFT 4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
+#define USB_CTL_SE0_MASK 0x40u
+#define USB_CTL_SE0_SHIFT 6
+#define USB_CTL_JSTATE_MASK 0x80u
+#define USB_CTL_JSTATE_SHIFT 7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK 0x7Fu
+#define USB_ADDR_ADDR_SHIFT 0
+#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK 0x80u
+#define USB_ADDR_LSEN_SHIFT 7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT 1
+#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK 0xFFu
+#define USB_FRMNUML_FRM_SHIFT 0
+#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK 0x7u
+#define USB_FRMNUMH_FRM_SHIFT 0
+#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK 0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT 0
+#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK 0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT 4
+#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK 0xFFu
+#define USB_SOFTHLD_CNT_SHIFT 0
+#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT 0
+#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT 0
+#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK 0x1u
+#define USB_ENDPT_EPHSHK_SHIFT 0
+#define USB_ENDPT_EPSTALL_MASK 0x2u
+#define USB_ENDPT_EPSTALL_SHIFT 1
+#define USB_ENDPT_EPTXEN_MASK 0x4u
+#define USB_ENDPT_EPTXEN_SHIFT 2
+#define USB_ENDPT_EPRXEN_MASK 0x8u
+#define USB_ENDPT_EPRXEN_SHIFT 3
+#define USB_ENDPT_EPCTLDIS_MASK 0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT 4
+#define USB_ENDPT_RETRYDIS_MASK 0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT 6
+#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT 7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK 0x40u
+#define USB_USBCTRL_PDE_SHIFT 6
+#define USB_USBCTRL_SUSP_MASK 0x80u
+#define USB_USBCTRL_SUSP_SHIFT 7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK 0x10u
+#define USB_OBSERVE_DMPD_SHIFT 4
+#define USB_OBSERVE_DPPD_MASK 0x40u
+#define USB_OBSERVE_DPPD_SHIFT 6
+#define USB_OBSERVE_DPPU_MASK 0x80u
+#define USB_OBSERVE_DPPU_SHIFT 7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
+#define USB_USBTRC0_SYNC_DET_MASK 0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT 1
+#define USB_USBTRC0_USBRESMEN_MASK 0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT 5
+#define USB_USBTRC0_USBRESET_MASK 0x80u
+#define USB_USBTRC0_USBRESET_SHIFT 7
+/* USBFRMADJUST Bit Fields */
+#define USB_USBFRMADJUST_ADJ_MASK 0xFFu
+#define USB_USBFRMADJUST_ADJ_SHIFT 0
+#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASES { USB0 }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__CWCC__)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Backward Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
+ * @{
+ */
+
+/* No backward compatibility issues. */
+
+/*!
+ * @}
+ */ /* end of group Backward_Compatibility_Symbols */
+
+
+#endif /* #if !defined(MKL46Z4_H_) */
+
+/* MKL46Z4.h, eof. */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/MKL46Z4.sct b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/MKL46Z4.sct
new file mode 100644
index 000000000..82ddfb878
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/MKL46Z4.sct
@@ -0,0 +1,14 @@
+
+LR_IROM1 0x00000000 0x40000 { ; load region size_region (256k)
+ ER_IROM1 0x00000000 0x40000 { ; load address = execution address
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+ ; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0
+ ; 0x8000 - 0xC0 = 0x7F40
+ RW_IRAM1 0x1FFFE0C0 0x7F40 {
+ .ANY (+RW +ZI)
+ }
+}
+
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/startup_MKL46Z4.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/startup_MKL46Z4.s
new file mode 100644
index 000000000..b690a22a6
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/startup_MKL46Z4.s
@@ -0,0 +1,332 @@
+;/*****************************************************************************
+; * @file: startup_MKL46Z4.s
+; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
+; * MKL46Z4
+; * @version: 2.0
+; * @date: 2012-12-12
+; *
+; * Copyright: 1997 - 2013 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+__initial_sp EQU 0x20006000 ; Top of RAM
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
+ DCD Reserved20_IRQHandler ; Reserved interrupt 20
+ DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C0 interrupt 25
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD SPI1_IRQHandler ; SPI1 interrupt
+ DCD UART0_IRQHandler ; UART0 status/error interrupt
+ DCD UART1_IRQHandler ; UART1 status/error interrupt
+ DCD UART2_IRQHandler ; UART2 status/error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
+ DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
+ DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT_IRQHandler ; PIT timer interrupt
+ DCD I2S0_IRQHandler ; I2S0 transmit interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD LCD_IRQHandler ; Segment LCD Interrupt
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+; <h> Flash Configuration
+; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+; <i> and security information that allows the MCU to restrict acces to the FTFL module.
+; <h> Backdoor Comparison Key
+; <o0> Backdoor Key 0 <0x0-0xFF:2>
+; <o1> Backdoor Key 1 <0x0-0xFF:2>
+; <o2> Backdoor Key 2 <0x0-0xFF:2>
+; <o3> Backdoor Key 3 <0x0-0xFF:2>
+; <o4> Backdoor Key 4 <0x0-0xFF:2>
+; <o5> Backdoor Key 5 <0x0-0xFF:2>
+; <o6> Backdoor Key 6 <0x0-0xFF:2>
+; <o7> Backdoor Key 7 <0x0-0xFF:2>
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+; </h>
+; <h> Program flash protection bytes (FPROT)
+; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+; <i> Each bit protects a 1/32 region of the program flash memory.
+; <h> FPROT0
+; <i> Program flash protection bytes
+; <i> 1/32 - 8/32 region
+; <o.0> FPROT0.0
+; <o.1> FPROT0.1
+; <o.2> FPROT0.2
+; <o.3> FPROT0.3
+; <o.4> FPROT0.4
+; <o.5> FPROT0.5
+; <o.6> FPROT0.6
+; <o.7> FPROT0.7
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0:EOR:0xFF
+; </h>
+; <h> FPROT1
+; <i> Program Flash Region Protect Register 1
+; <i> 9/32 - 16/32 region
+; <o.0> FPROT1.0
+; <o.1> FPROT1.1
+; <o.2> FPROT1.2
+; <o.3> FPROT1.3
+; <o.4> FPROT1.4
+; <o.5> FPROT1.5
+; <o.6> FPROT1.6
+; <o.7> FPROT1.7
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1:EOR:0xFF
+; </h>
+; <h> FPROT2
+; <i> Program Flash Region Protect Register 2
+; <i> 17/32 - 24/32 region
+; <o.0> FPROT2.0
+; <o.1> FPROT2.1
+; <o.2> FPROT2.2
+; <o.3> FPROT2.3
+; <o.4> FPROT2.4
+; <o.5> FPROT2.5
+; <o.6> FPROT2.6
+; <o.7> FPROT2.7
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2:EOR:0xFF
+; </h>
+; <h> FPROT3
+; <i> Program Flash Region Protect Register 3
+; <i> 25/32 - 32/32 region
+; <o.0> FPROT3.0
+; <o.1> FPROT3.1
+; <o.2> FPROT3.2
+; <o.3> FPROT3.3
+; <o.4> FPROT3.4
+; <o.5> FPROT3.5
+; <o.6> FPROT3.6
+; <o.7> FPROT3.7
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3:EOR:0xFF
+; </h>
+; </h>
+; </h>
+; <h> Flash nonvolatile option byte (FOPT)
+; <i> Allows the user to customize the operation of the MCU at boot time.
+; <o.0> LPBOOT0
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
+; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
+; <o.4> LPBOOT1
+; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
+; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
+; <o.2> NMI_DIS
+; <0=> NMI interrupts are always blocked
+; <1=> NMI pin/interrupts reset default to enabled
+; <o.3> RESET_PIN_CFG
+; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
+; <1=> RESET pin is dedicated
+; <o.3> FAST_INIT
+; <0=> Slower initialization
+; <1=> Fast Initialization
+FOPT EQU 0xFF
+; </h>
+; <h> Flash security byte (FSEC)
+; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+; <o.0..1> SEC
+; <2=> MCU security status is unsecure
+; <3=> MCU security status is secure
+; <i> Flash Security
+; <i> This bits define the security state of the MCU.
+; <o.2..3> FSLACC
+; <2=> Freescale factory access denied
+; <3=> Freescale factory access granted
+; <i> Freescale Failure Analysis Access Code
+; <i> This bits define the security state of the MCU.
+; <o.4..5> MEEN
+; <2=> Mass erase is disabled
+; <3=> Mass erase is enabled
+; <i> Mass Erase Enable Bits
+; <i> Enables and disables mass erase capability of the FTFL module
+; <o.6..7> KEYEN
+; <2=> Backdoor key access enabled
+; <3=> Backdoor key access disabled
+; <i> Backdoor key Security Enable
+; <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC EQU 0xFE
+; </h>
+
+ IF :LNOT::DEF:RAM_TARGET
+ AREA |.ARM.__at_0x400|, CODE, READONLY
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+ EXPORT DMA0_IRQHandler [WEAK]
+ EXPORT DMA1_IRQHandler [WEAK]
+ EXPORT DMA2_IRQHandler [WEAK]
+ EXPORT DMA3_IRQHandler [WEAK]
+ EXPORT Reserved20_IRQHandler [WEAK]
+ EXPORT FTFA_IRQHandler [WEAK]
+ EXPORT LVD_LVW_IRQHandler [WEAK]
+ EXPORT LLW_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI0_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT CMP0_IRQHandler [WEAK]
+ EXPORT TPM0_IRQHandler [WEAK]
+ EXPORT TPM1_IRQHandler [WEAK]
+ EXPORT TPM2_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT RTC_Seconds_IRQHandler [WEAK]
+ EXPORT PIT_IRQHandler [WEAK]
+ EXPORT I2S0_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT DAC0_IRQHandler [WEAK]
+ EXPORT TSI0_IRQHandler [WEAK]
+ EXPORT MCG_IRQHandler [WEAK]
+ EXPORT LPTimer_IRQHandler [WEAK]
+ EXPORT LCD_IRQHandler [WEAK]
+ EXPORT PORTA_IRQHandler [WEAK]
+ EXPORT PORTD_IRQHandler [WEAK]
+ EXPORT DefaultISR [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+I2S0_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+LCD_IRQHandler
+PORTA_IRQHandler
+PORTD_IRQHandler
+DefaultISR
+
+ B .
+
+ ENDP
+
+
+ ALIGN
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/sys.cpp b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 000000000..2f1024ace
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * Setup a fixed single stack/heap memory model,
+ * between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+ uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+ uint32_t sp_limit = __current_sp();
+
+ zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
+
+ struct __initial_stackheap r;
+ r.heap_base = zi_limit;
+ r.heap_limit = sp_limit;
+ return r;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/MKL46Z4.ld b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/MKL46Z4.ld
new file mode 100644
index 000000000..6f20f3212
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/MKL46Z4.ld
@@ -0,0 +1,163 @@
+/*
+ * KL46Z ARM GCC linker script file
+ */
+
+MEMORY
+{
+ VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ FLASH_PROTECTION (rx) : ORIGIN = 0x00000400, LENGTH = 0x00000010
+ FLASH (rx) : ORIGIN = 0x00000410, LENGTH = 256K - 0x00000410
+ RAM (rwx) : ORIGIN = 0x1FFFE0C0, LENGTH = 32K - 0xC0
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * _reset_init : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .isr_vector :
+ {
+ __vector_table = .;
+ KEEP(*(.vector_table))
+ *(.text.Reset_Handler)
+ *(.text.System_Init)
+ . = ALIGN(4);
+ } > VECTORS
+
+ .flash_protect :
+ {
+ KEEP(*(.kinetis_flash_config_field))
+ . = ALIGN(4);
+ } > FLASH_PROTECTION
+
+ .text :
+ {
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM
+
+ .bss :
+ {
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ __bss_end__ = .;
+ } > RAM
+
+ .heap :
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy :
+ {
+ *(.stack)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/startup_MKL46Z4.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/startup_MKL46Z4.s
new file mode 100644
index 000000000..5d5eae6e5
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_GCC_ARM/startup_MKL46Z4.s
@@ -0,0 +1,241 @@
+/* KL46Z startup ARM GCC
+ * Purpose: startup file for Cortex-M0 devices. Should use with
+ * GCC for ARM Embedded Processors
+ * Version: V1.2
+ * Date: 15 Nov 2011
+ *
+ * Copyright (c) 2011, ARM Limited
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ * Neither the name of the ARM Limited nor the
+ names of its contributors may be used to endorse or promote products
+ derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+ .syntax unified
+ .arch armv6-m
+
+/* Memory Model
+ The HEAP starts at the end of the DATA section and grows upward.
+
+ The STACK starts at the end of the RAM and grows downward.
+
+ The HEAP and stack STACK are only checked at compile time:
+ (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
+
+ This is just a check for the bare minimum for the Heap+Stack area before
+ aborting compilation, it is not the run time limit:
+ Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
+ */
+ .section .stack
+ .align 3
+#ifdef __STACK_SIZE
+ .equ Stack_Size, __STACK_SIZE
+#else
+ .equ Stack_Size, 0x400
+#endif
+ .globl __StackTop
+ .globl __StackLimit
+__StackLimit:
+ .space Stack_Size
+ .size __StackLimit, . - __StackLimit
+__StackTop:
+ .size __StackTop, . - __StackTop
+
+ .section .heap
+ .align 3
+#ifdef __HEAP_SIZE
+ .equ Heap_Size, __HEAP_SIZE
+#else
+ .equ Heap_Size, 0x80
+#endif
+ .globl __HeapBase
+ .globl __HeapLimit
+__HeapBase:
+ .space Heap_Size
+ .size __HeapBase, . - __HeapBase
+__HeapLimit:
+ .size __HeapLimit, . - __HeapLimit
+
+ .section .vector_table,"a",%progbits
+ .align 2
+ .globl __isr_vector
+__isr_vector:
+ .long __StackTop /* Top of Stack */
+ .long Reset_Handler /* Reset Handler */
+ .long NMI_Handler /* NMI Handler */
+ .long HardFault_Handler /* Hard Fault Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long SVC_Handler /* SVCall Handler */
+ .long 0 /* Reserved */
+ .long 0 /* Reserved */
+ .long PendSV_Handler /* PendSV Handler */
+ .long SysTick_Handler /* SysTick Handler */
+
+ /* External interrupts */
+ .long DMA0_IRQHandler /* DMA channel 0 transfer complete interrupt */
+ .long DMA1_IRQHandler /* DMA channel 1 transfer complete interrupt */
+ .long DMA2_IRQHandler /* DMA channel 2 transfer complete interrupt */
+ .long DMA3_IRQHandler /* DMA channel 3 transfer complete interrupt */
+ .long Default_Handler /* Reserved interrupt 20 */
+ .long FTFA_IRQHandler /* FTFA interrupt */
+ .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning */
+ .long LLW_IRQHandler /* Low Leakage Wakeup */
+ .long I2C0_IRQHandler /* I2C0 interrupt */
+ .long I2C1_IRQHandler /* I2C0 interrupt 25 */
+ .long SPI0_IRQHandler /* SPI0 interrupt */
+ .long SPI1_IRQHandler /* SPI1 interrupt */
+ .long UART0_IRQHandler /* UART0 status/error interrupt */
+ .long UART1_IRQHandler /* UART1 status/error interrupt */
+ .long UART2_IRQHandler /* UART2 status/error interrupt */
+ .long ADC0_IRQHandler /* ADC0 interrupt */
+ .long CMP0_IRQHandler /* CMP0 interrupt */
+ .long TPM0_IRQHandler /* TPM0 fault, overflow and channels interrupt */
+ .long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt */
+ .long TPM2_IRQHandler /* TPM2 fault, overflow and channels interrupt */
+ .long RTC_IRQHandler /* RTC interrupt */
+ .long RTC_Seconds_IRQHandler /* RTC seconds interrupt */
+ .long PIT_IRQHandler /* PIT timer interrupt */
+ .long I2S_IRQHandler /* I2S transmit interrupt */
+ .long USB0_IRQHandler /* USB0 interrupt */
+ .long DAC0_IRQHandler /* DAC interrupt */
+ .long TSI0_IRQHandler /* TSI0 interrupt */
+ .long MCG_IRQHandler /* MCG interrupt */
+ .long LPTimer_IRQHandler /* LPTimer interrupt */
+ .long LCD_IRQHandler /* Segment LCD Interrupt*/
+ .long PORTA_IRQHandler /* Port A interrupt */
+ .long PORTD_IRQHandler /* Port D interrupt */
+
+ .size __isr_vector, . - __isr_vector
+
+ .section .text.Reset_Handler
+ .thumb
+ .thumb_func
+ .align 2
+ .globl Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+/* Loop to copy data from read only memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __etext: End of code section, i.e., begin of data sections to copy from.
+ * __data_start__/__data_end__: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__etext
+ ldr r2, =__data_start__
+ ldr r3, =__data_end__
+
+ subs r3, r2
+ ble .Lflash_to_ram_loop_end
+
+ movs r4, 0
+.Lflash_to_ram_loop:
+ ldr r0, [r1,r4]
+ str r0, [r2,r4]
+ adds r4, 4
+ cmp r4, r3
+ blt .Lflash_to_ram_loop
+.Lflash_to_ram_loop_end:
+
+ ldr r0, =SystemInit
+ blx r0
+ ldr r0, =_start
+ bx r0
+ .pool
+ .size Reset_Handler, . - Reset_Handler
+
+ .text
+/* Macro to define default handlers. Default handler
+ * will be weak symbol and just dead loops. They can be
+ * overwritten by other handlers */
+ .macro def_default_handler handler_name
+ .align 1
+ .thumb_func
+ .weak \handler_name
+ .type \handler_name, %function
+\handler_name :
+ b .
+ .size \handler_name, . - \handler_name
+ .endm
+
+ def_default_handler NMI_Handler
+ def_default_handler HardFault_Handler
+ def_default_handler SVC_Handler
+ def_default_handler PendSV_Handler
+ def_default_handler SysTick_Handler
+ def_default_handler Default_Handler
+
+ .macro def_irq_default_handler handler_name
+ .weak \handler_name
+ .set \handler_name, Default_Handler
+ .endm
+
+ def_irq_default_handler DMA0_IRQHandler
+ def_irq_default_handler DMA1_IRQHandler
+ def_irq_default_handler DMA2_IRQHandler
+ def_irq_default_handler DMA3_IRQHandler
+ def_irq_default_handler FTFA_IRQHandler
+ def_irq_default_handler LVD_LVW_IRQHandler
+ def_irq_default_handler LLW_IRQHandler
+ def_irq_default_handler I2C0_IRQHandler
+ def_irq_default_handler I2C1_IRQHandler
+ def_irq_default_handler SPI0_IRQHandler
+ def_irq_default_handler SPI1_IRQHandler
+ def_irq_default_handler UART0_IRQHandler
+ def_irq_default_handler UART1_IRQHandler
+ def_irq_default_handler UART2_IRQHandler
+ def_irq_default_handler ADC0_IRQHandler
+ def_irq_default_handler CMP0_IRQHandler
+ def_irq_default_handler TPM0_IRQHandler
+ def_irq_default_handler TPM1_IRQHandler
+ def_irq_default_handler TPM2_IRQHandler
+ def_irq_default_handler RTC_IRQHandler
+ def_irq_default_handler RTC_Seconds_IRQHandler
+ def_irq_default_handler PIT_IRQHandler
+ def_irq_default_handler I2S_IRQHandler
+ def_irq_default_handler USB0_IRQHandler
+ def_irq_default_handler DAC0_IRQHandler
+ def_irq_default_handler TSI0_IRQHandler
+ def_irq_default_handler MCG_IRQHandler
+ def_irq_default_handler LPTimer_IRQHandler
+ def_irq_default_handler LCD_IRQHandler
+ def_irq_default_handler PORTA_IRQHandler
+ def_irq_default_handler PORTD_IRQHandler
+ def_irq_default_handler DEF_IRQHandler
+
+/* Flash protection region, placed at 0x400 */
+ .text
+ .thumb
+ .align 2
+ .section .kinetis_flash_config_field,"a",%progbits
+kinetis_flash_config:
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xffffffff
+ .long 0xfffffffe
+
+ .end
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/MKL46Z4.icf b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/MKL46Z4.icf
new file mode 100644
index 000000000..673f212eb
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/MKL46Z4.icf
@@ -0,0 +1,43 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0002ffff;
+define symbol __ICFEDIT_region_NVIC_start__ = 0x1fffe000;
+define symbol __ICFEDIT_region_NVIC_end__ = 0x1fffe0bf;
+define symbol __ICFEDIT_region_RAM_start__ = 0x1fffe0c0;
+define symbol __ICFEDIT_region_RAM_end__ = 0x1fffffff;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __region_RAM2_start__ = 0x20000000;
+define symbol __region_RAM2_end__ = 0x20005fff;
+
+define symbol __FlashConfig_start__ = 0x00000400;
+define symbol __FlashConfig_end__ = 0x0000040f;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to (__FlashConfig_start__ - 1)] | mem:[from (__FlashConfig_end__+1) to __ICFEDIT_region_ROM_end__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__] | mem:[from __region_RAM2_start__ to __region_RAM2_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+define region FlashConfig_region = mem:[from __FlashConfig_start__ to __FlashConfig_end__];
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in FlashConfig_region {section FlashConfig};
+
+place in ROM_region { readonly };
+
+place in RAM_region { readwrite, block HEAP, block CSTACK };
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/startup_MKL46Z4.s b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/startup_MKL46Z4.s
new file mode 100644
index 000000000..618226746
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/TOOLCHAIN_IAR/startup_MKL46Z4.s
@@ -0,0 +1,217 @@
+/**************************************************
+ *
+ * Copyright 2010 IAR Systems. All rights reserved.
+ *
+ * $Revision: 16 $
+ *
+ **************************************************/
+
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:ROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK) ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+ ; External Interrupts
+ DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
+ DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
+ DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
+ DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
+ DCD 0 ; Reserved
+ DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
+ DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
+ DCD LLW_IRQHandler ; Low Leakage Wakeup
+ DCD I2C0_IRQHandler ; I2C0 interrupt
+ DCD I2C1_IRQHandler ; I2C0 interrupt 25
+ DCD SPI0_IRQHandler ; SPI0 interrupt
+ DCD SPI1_IRQHandler ; SPI1 interrupt
+ DCD UART0_IRQHandler ; UART0 status/error interrupt
+ DCD UART1_IRQHandler ; UART1 status/error interrupt
+ DCD UART2_IRQHandler ; UART2 status/error interrupt
+ DCD ADC0_IRQHandler ; ADC0 interrupt
+ DCD CMP0_IRQHandler ; CMP0 interrupt
+ DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
+ DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
+ DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
+ DCD RTC_IRQHandler ; RTC interrupt
+ DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
+ DCD PIT_IRQHandler ; PIT timer interrupt
+ DCD I2S0_IRQHandler ; I2S0 transmit interrupt
+ DCD USB0_IRQHandler ; USB0 interrupt
+ DCD DAC0_IRQHandler ; DAC0 interrupt
+ DCD TSI0_IRQHandler ; TSI0 interrupt
+ DCD MCG_IRQHandler ; MCG interrupt
+ DCD LPTimer_IRQHandler ; LPTimer interrupt
+ DCD LCD_IRQHandler ; Segment LCD Interrupt
+ DCD PORTA_IRQHandler ; Port A interrupt
+ DCD PORTD_IRQHandler ; Port D interrupt
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;Flash Configuration
+;;16-byte flash configuration field that stores default protection settings (loaded on reset)
+;;and security information that allows the MCU to restrict acces to the FTFL module.
+
+BackDoorK0 EQU 0xFF
+BackDoorK1 EQU 0xFF
+BackDoorK2 EQU 0xFF
+BackDoorK3 EQU 0xFF
+BackDoorK4 EQU 0xFF
+BackDoorK5 EQU 0xFF
+BackDoorK6 EQU 0xFF
+BackDoorK7 EQU 0xFF
+
+nFPROT0 EQU 0x00
+FPROT0 EQU nFPROT0^0xFF
+
+nFPROT1 EQU 0x00
+FPROT1 EQU nFPROT1^0xFF
+
+nFPROT2 EQU 0x00
+FPROT2 EQU nFPROT2^0xFF
+
+nFPROT3 EQU 0x00
+FPROT3 EQU nFPROT3^0xFF
+
+FOPT EQU 0xFF
+
+FSEC EQU 0xFE
+ SECTION FlashConfig:CONST:REORDER:ROOT(2)
+Config:
+ DATA
+ DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+ DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+ DCB FPROT0, FPROT1, FPROT2, FPROT3
+ DCB FSEC, FOPT, 0xFF, 0xFF
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ PUBWEAK HardFault_Handler
+ PUBWEAK SVC_Handler
+ PUBWEAK PendSV_Handler
+ PUBWEAK SysTick_Handler
+ PUBWEAK DMA0_IRQHandler
+ PUBWEAK DMA1_IRQHandler
+ PUBWEAK DMA2_IRQHandler
+ PUBWEAK DMA3_IRQHandler
+ PUBWEAK Reserved20_IRQHandler
+ PUBWEAK FTFA_IRQHandler
+ PUBWEAK LVD_LVW_IRQHandler
+ PUBWEAK LLW_IRQHandler
+ PUBWEAK I2C0_IRQHandler
+ PUBWEAK I2C1_IRQHandler
+ PUBWEAK SPI0_IRQHandler
+ PUBWEAK SPI1_IRQHandler
+ PUBWEAK UART0_IRQHandler
+ PUBWEAK UART1_IRQHandler
+ PUBWEAK UART2_IRQHandler
+ PUBWEAK ADC0_IRQHandler
+ PUBWEAK CMP0_IRQHandler
+ PUBWEAK TPM0_IRQHandler
+ PUBWEAK TPM1_IRQHandler
+ PUBWEAK TPM2_IRQHandler
+ PUBWEAK RTC_IRQHandler
+ PUBWEAK RTC_Seconds_IRQHandler
+ PUBWEAK PIT_IRQHandler
+ PUBWEAK I2S0_IRQHandler
+ PUBWEAK USB0_IRQHandler
+ PUBWEAK DAC0_IRQHandler
+ PUBWEAK TSI0_IRQHandler
+ PUBWEAK MCG_IRQHandler
+ PUBWEAK LPTimer_IRQHandler
+ PUBWEAK LCD_IRQHandler
+ PUBWEAK PORTA_IRQHandler
+ PUBWEAK PORTD_IRQHandler
+
+ SECTION .text:CODE:REORDER:NOROOT(1)
+ THUMB
+NMI_Handler
+HardFault_Handler
+SVC_Handler
+PendSV_Handler
+SysTick_Handler
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+Reserved20_IRQHandler
+FTFA_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+ADC0_IRQHandler
+CMP0_IRQHandler
+TPM0_IRQHandler
+TPM1_IRQHandler
+TPM2_IRQHandler
+RTC_IRQHandler
+RTC_Seconds_IRQHandler
+PIT_IRQHandler
+I2S0_IRQHandler
+USB0_IRQHandler
+DAC0_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+LCD_IRQHandler
+PORTA_IRQHandler
+PORTD_IRQHandler
+Default_Handler
+
+ B Default_Handler
+ END
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis.h
new file mode 100644
index 000000000..553b60775
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC11U24 specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "MKL46Z4.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.c
new file mode 100644
index 000000000..077924407
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.c
@@ -0,0 +1,55 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS (0x1FFFE000) // Vectors positioned at start of RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ uint32_t i;
+
+ // Copy and switch to dynamic vectors if the first time called
+ if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+ uint32_t *old_vectors = vectors;
+ vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+ for (i=0; i<NVIC_NUM_VECTORS; i++) {
+ vectors[i] = old_vectors[i];
+ }
+ SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+ }
+ vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+ uint32_t *vectors = (uint32_t*)SCB->VTOR;
+ return vectors[IRQn + 16];
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.h
new file mode 100644
index 000000000..64f36b316
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/cmsis_nvic.h
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.c b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.c
new file mode 100644
index 000000000..8a15912ac
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.c
@@ -0,0 +1,269 @@
+/*
+** ###################################################################
+** Processors: MKL46Z256VLH4
+** MKL46Z128VLH4
+** MKL46Z256VLL4
+** MKL46Z128VLL4
+** MKL46Z256VMC4
+** MKL46Z128VMC4
+**
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
+** Version: rev. 2.0, 2012-12-12
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2012 Freescale, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-10-16)
+** Initial version.
+** - rev. 2.0 (2012-12-12)
+** Update to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL46Z4
+ * @version 2.0
+ * @date 2012-12-12
+ * @brief Device specific configuration file for MKL46Z4 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "MKL46Z4.h"
+
+#define DISABLE_WDOG 1
+
+#define CLOCK_SETUP 1
+/* Predefined clock setups
+ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+ Reference clock source for MCG module is the slow internal clock source 32.768kHz
+ Core clock = 41.94MHz, BusClock = 13.98MHz
+ 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
+ Reference clock source for MCG module is an external crystal 8MHz
+ Core clock = 48MHz, BusClock = 24MHz
+ 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+ Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
+ Core clock = 8MHz, BusClock = 8MHz
+*/
+
+/*----------------------------------------------------------------------------
+ Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+ #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
+ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
+ #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+ /* Disable the WDOG module */
+ /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
+ SIM->COPC = (uint32_t)0x00u;
+#endif /* (DISABLE_WDOG) */
+#if (CLOCK_SETUP == 0)
+ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
+ /* Switch to FEI Mode */
+ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x06U;
+ /* MCG_C2: LOCRE0=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
+ MCG->C2 &= (uint8_t)~(uint8_t)0xBFU;
+ /* MCG->C4: DMX32=0,DRST_DRS=1 */
+ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x80U;
+ /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00U;
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
+ }
+#elif (CLOCK_SETUP == 1)
+ /* SIM->SCGC5: PORTA=1 */
+ SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
+ /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
+ /* PORTA->PCR18: ISF=0,MUX=0 */
+ PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+ /* PORTA->PCR19: ISF=0,MUX=0 */
+ PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
+ /* Switch to FBE Mode */
+ /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x9BU) | (uint8_t)0x24U);
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x80U;
+ /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9AU;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+ /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
+ MCG->C5 = (uint8_t)0x01U;
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to PBE Mode */
+ /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x40U;
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
+ }
+ /* Switch to PEE Mode */
+ /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x1AU;
+ while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
+ }
+#elif (CLOCK_SETUP == 2)
+ /* SIM->SCGC5: PORTA=1 */
+ SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */
+ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+ SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
+ /* PORTA->PCR18: ISF=0,MUX=0 */
+ PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
+ /* PORTA->PCR19: ISF=0,MUX=0 */
+ PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
+ /* Switch to FBE Mode */
+ /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
+ MCG->C2 = (uint8_t)0x24U;
+ /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=0 */
+ OSC0->CR = (uint8_t)0x80U;
+ /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+ MCG->C1 = (uint8_t)0x9AU;
+ /* MCG->C4: DMX32=0,DRST_DRS=0 */
+ MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
+ /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
+ MCG->C5 = (uint8_t)0x00U;
+ /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
+ MCG->C6 = (uint8_t)0x00U;
+ while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
+ }
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+ /* Switch to BLPE Mode */
+ /* MCG_C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
+ MCG->C2 = (uint8_t)((MCG->C2 & (uint8_t)~(uint8_t)0x99U) | (uint8_t)0x26U);
+ while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
+ }
+#endif /* (CLOCK_SETUP == 2) */
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+ uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
+ uint8_t Divider;
+
+ if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+ /* Output of FLL or PLL is selected */
+ if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
+ /* FLL is selected */
+ if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
+ if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
+ MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
+ } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
+ } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
+ } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+ /* Select correct multiplier to calculate the MCG output clock */
+ switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+ case 0x0u:
+ MCGOUTClock *= 640u;
+ break;
+ case 0x20u:
+ MCGOUTClock *= 1280u;
+ break;
+ case 0x40u:
+ MCGOUTClock *= 1920u;
+ break;
+ case 0x60u:
+ MCGOUTClock *= 2560u;
+ break;
+ case 0x80u:
+ MCGOUTClock *= 732u;
+ break;
+ case 0xA0u:
+ MCGOUTClock *= 1464u;
+ break;
+ case 0xC0u:
+ MCGOUTClock *= 2197u;
+ break;
+ case 0xE0u:
+ MCGOUTClock *= 2929u;
+ break;
+ default:
+ break;
+ }
+ } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ /* PLL is selected */
+ Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
+ MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
+ Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
+ MCGOUTClock *= Divider; /* Calculate the MCG output clock */
+ } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+ /* Internal reference clock is selected */
+ if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
+ } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
+ } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+ } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+ /* External reference clock is selected */
+ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
+ } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ /* Reserved value */
+ return;
+ } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+ SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.h
new file mode 100644
index 000000000..e88304711
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL46Z/system_MKL46Z4.h
@@ -0,0 +1,90 @@
+/*
+** ###################################################################
+** Processors: MKL46Z256VLH4
+** MKL46Z128VLH4
+** MKL46Z256VLL4
+** MKL46Z128VLL4
+** MKL46Z256VMC4
+** MKL46Z128VMC4
+**
+** Compilers: ARM Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: KL46P121M48SF4RM, Rev.1 Draft A, Aug 2012
+** Version: rev. 2.0, 2012-12-12
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright: 2012 Freescale, Inc. All Rights Reserved.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2012-10-16)
+** Initial version.
+** - rev. 2.0 (2012-12-12)
+** Update to reference manual rev. 1.
+**
+** ###################################################################
+*/
+
+/**
+ * @file MKL46Z4
+ * @version 2.0
+ * @date 2012-12-12
+ * @brief Device specific configuration file for MKL46Z4 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef SYSTEM_MKL46Z4_H_
+#define SYSTEM_MKL46Z4_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #if !defined(SYSTEM_MKL46Z4_H_) */
diff --git a/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/MK64F12.h b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/MK64F12.h
new file mode 100644
index 000000000..28a78cedc
--- /dev/null
+++ b/tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/MK64F12.h
@@ -0,0 +1,14420 @@
+/*
+** ###################################################################
+** Processors: MK64FN1M0VDC12
+** MK64FN1M0VLL12
+** MK64FN1M0VLQ12
+** MK64FN1M0VMD12
+**
+** Compilers: Keil ARM C/C++ Compiler
+** Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** GNU C Compiler - CodeSourcery Sourcery G++
+** IAR ANSI C/C++ Compiler for ARM
+**
+** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
+** Version: rev. 2.5, 2014-02-10
+** Build: b140604
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MK64F12
+**
+** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
+** All rights reserved.
+**
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** o Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** o Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.freescale.com
+** mail: support@freescale.com
+**
+** Revisions:
+** - rev. 1.0 (2013-08-12)
+** Initial version.
+** - rev. 2.0 (2013-10-29)
+** Register accessor macros added to the memory map.
+** Symbols for Processor Expert memory map compatibility added to the memory map.
+** Startup file for gcc has been updated according to CMSIS 3.2.
+** System initialization updated.
+** MCG - registers updated.
+** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+** - rev. 2.1 (2013-10-30)
+** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+** - rev. 2.2 (2013-12-09)
+** DMA - EARS register removed.
+** AIPS0, AIPS1 - MPRA register updated.
+** - rev. 2.3 (2014-01-24)
+** Update according to reference manual rev. 2
+** ENET, MCG, MCM, SIM, USB - registers updated
+** - rev. 2.4 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+** Update of SystemInit() and SystemCoreClockUpdate() functions.
+** - rev. 2.5 (2014-02-10)
+** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+** Update of SystemInit() and SystemCoreClockUpdate() functions.
+** Module access macro module_BASES replaced by module_BASE_PTRS.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12.h
+ * @version 2.5
+ * @date 2014-02-10
+ * @brief CMSIS Peripheral Access Layer for MK64F12
+ *
+ * CMSIS Peripheral Access Layer for MK64F12
+ */
+
+
+/* ----------------------------------------------------------------------------
+ -- MCU activation
+ ---------------------------------------------------------------------------- */
+
+/* Prevention from multiple including the same memory map */
+#if !defined(MK64F12_H_) /* Check if memory map has not been already included */
+#define MK64F12_H_
+#define MCU_MK64F12
+
+/* Check if another memory map has not been also included */
+#if (defined(MCU_ACTIVE))
+ #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
+#endif /* (defined(MCU_ACTIVE)) */
+#define MCU_ACTIVE
+
+#include <stdint.h>
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200u
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0005u
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ * bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ * 0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ * be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
+ DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
+ DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
+ DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
+ DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
+ DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
+ DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
+ DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
+ DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
+ DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
+ DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
+ DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
+ DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
+ DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
+ DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
+ DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
+ DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
+ MCM_IRQn = 17, /**< Normal Interrupt */
+ FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
+ Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
+ LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
+ LLW_IRQn = 21, /**< Low Leakage Wakeup */
+ Watchdog_IRQn = 22, /**< WDOG Interrupt */
+ RNG_IRQn = 23, /**< RNG Interrupt */
+ I2C0_IRQn = 24, /**< I2C0 interrupt */
+ I2C1_IRQn = 25, /**< I2C1 interrupt */
+ SPI0_IRQn = 26, /**< SPI0 Interrupt */
+ SPI1_IRQn = 27, /**< SPI1 Interrupt */
+ I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
+ I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
+ UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
+ UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
+ UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
+ UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
+ UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
+ UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
+ UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
+ UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
+ UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
+ ADC0_IRQn = 39, /**< ADC0 interrupt */
+ CMP0_IRQn = 40, /**< CMP0 interrupt */
+ CMP1_IRQn = 41, /**< CMP1 interrupt */
+ FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
+ FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
+ FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
+ CMT_IRQn = 45, /**< CMT interrupt */
+ RTC_IRQn = 46, /**< RTC interrupt */
+ RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
+ PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
+ PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
+ PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
+ PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
+ PDB0_IRQn = 52, /**< PDB0 Interrupt */
+ USB0_IRQn = 53, /**< USB0 interrupt */
+ USBDCD_IRQn = 54, /**< USBDCD Interrupt */
+ Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
+ DAC0_IRQn = 56, /**< DAC0 interrupt */
+ MCG_IRQn = 57, /**< MCG Interrupt */
+ LPTimer_IRQn = 58, /**< LPTimer interrupt */
+ PORTA_IRQn = 59, /**< Port A interrupt */
+ PORTB_IRQn = 60, /**< Port B interrupt */
+ PORTC_IRQn = 61, /**< Port C interrupt */
+ PORTD_IRQn = 62, /**< Port D interrupt */
+ PORTE_IRQn = 63, /**< Port E interrupt */
+ SWI_IRQn = 64, /**< Software interrupt */
+ SPI2_IRQn = 65, /**< SPI2 Interrupt */
+ UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
+ UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
+ UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
+ UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */
+ CMP2_IRQn = 70, /**< CMP2 interrupt */
+ FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
+ DAC1_IRQn = 72, /**< DAC1 interrupt */
+ ADC1_IRQn = 73, /**< ADC1 interrupt */
+ I2C2_IRQn = 74, /**< I2C2 interrupt */
+ CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
+ CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
+ CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
+ CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
+ CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
+ CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
+ SDHC_IRQn = 81, /**< SDHC interrupt */
+ ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
+ ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
+ ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
+ ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M4 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h" /* Core Peripheral Access Layer */
+#include "system_MK64F12.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
+ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
+ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
+ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
+ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
+ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
+ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
+ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
+ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
+ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type, *ADC_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register accessors */
+#define ADC_SC1_REG(base,index) ((base)->SC1[index])
+#define ADC_CFG1_REG(base) ((base)->CFG1)
+#define ADC_CFG2_REG(base) ((base)->CFG2)
+#define ADC_R_REG(base,index) ((base)->R[index])
+#define ADC_CV1_REG(base) ((base)->CV1)
+#define ADC_CV2_REG(base) ((base)->CV2)
+#define ADC_SC2_REG(base) ((base)->SC2)
+#define ADC_SC3_REG(base) ((base)->SC3)
+#define ADC_OFS_REG(base) ((base)->OFS)
+#define ADC_PG_REG(base) ((base)->PG)
+#define ADC_MG_REG(base) ((base)->MG)
+#define ADC_CLPD_REG(base) ((base)->CLPD)
+#define ADC_CLPS_REG(base) ((base)->CLPS)
+#define ADC_CLP4_REG(base) ((base)->CLP4)
+#define ADC_CLP3_REG(base) ((base)->CLP3)
+#define ADC_CLP2_REG(base) ((base)->CLP2)
+#define ADC_CLP1_REG(base) ((base)->CLP1)
+#define ADC_CLP0_REG(base) ((base)->CLP0)
+#define ADC_CLMD_REG(base) ((base)->CLMD)
+#define ADC_CLMS_REG(base) ((base)->CLMS)
+#define ADC_CLM4_REG(base) ((base)->CLM4)
+#define ADC_CLM3_REG(base) ((base)->CLM3)
+#define ADC_CLM2_REG(base) ((base)->CLM2)
+#define ADC_CLM1_REG(base) ((base)->CLM1)
+#define ADC_CLM0_REG(base) ((base)->CLM0)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK 0x1Fu
+#define ADC_SC1_ADCH_SHIFT 0
+#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK 0x20u
+#define ADC_SC1_DIFF_SHIFT 5
+#define ADC_SC1_AIEN_MASK 0x40u
+#define ADC_SC1_AIEN_SHIFT 6
+#define ADC_SC1_COCO_MASK 0x80u
+#define ADC_SC1_COCO_SHIFT 7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK 0x3u
+#define ADC_CFG1_ADICLK_SHIFT 0
+#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK 0xCu
+#define ADC_CFG1_MODE_SHIFT 2
+#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK 0x10u
+#define ADC_CFG1_ADLSMP_SHIFT 4
+#define ADC_CFG1_ADIV_MASK 0x60u
+#define ADC_CFG1_ADIV_SHIFT 5
+#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK 0x80u
+#define ADC_CFG1_ADLPC_SHIFT 7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK 0x3u
+#define ADC_CFG2_ADLSTS_SHIFT 0
+#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK 0x4u
+#define ADC_CFG2_ADHSC_SHIFT 2
+#define ADC_CFG2_ADACKEN_MASK 0x8u
+#define ADC_CFG2_ADACKEN_SHIFT 3
+#define ADC_CFG2_MUXSEL_MASK 0x10u
+#define ADC_CFG2_MUXSEL_SHIFT 4
+/* R Bit Fields */
+#define ADC_R_D_MASK 0xFFFFu
+#define ADC_R_D_SHIFT 0
+#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK 0xFFFFu
+#define ADC_CV1_CV_SHIFT 0
+#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK 0xFFFFu
+#define ADC_CV2_CV_SHIFT 0
+#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK 0x3u
+#define ADC_SC2_REFSEL_SHIFT 0
+#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK 0x4u
+#define ADC_SC2_DMAEN_SHIFT 2
+#define ADC_SC2_ACREN_MASK 0x8u
+#define ADC_SC2_ACREN_SHIFT 3
+#define ADC_SC2_ACFGT_MASK 0x10u
+#define ADC_SC2_ACFGT_SHIFT 4
+#define ADC_SC2_ACFE_MASK 0x20u
+#define ADC_SC2_ACFE_SHIFT 5
+#define ADC_SC2_ADTRG_MASK 0x40u
+#define ADC_SC2_ADTRG_SHIFT 6
+#define ADC_SC2_ADACT_MASK 0x80u
+#define ADC_SC2_ADACT_SHIFT 7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK 0x3u
+#define ADC_SC3_AVGS_SHIFT 0
+#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK 0x4u
+#define ADC_SC3_AVGE_SHIFT 2
+#define ADC_SC3_ADCO_MASK 0x8u
+#define ADC_SC3_ADCO_SHIFT 3
+#define ADC_SC3_CALF_MASK 0x40u
+#define ADC_SC3_CALF_SHIFT 6
+#define ADC_SC3_CAL_MASK 0x80u
+#define ADC_SC3_CAL_SHIFT 7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK 0xFFFFu
+#define ADC_OFS_OFS_SHIFT 0
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK 0xFFFFu
+#define ADC_PG_PG_SHIFT 0
+#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK 0xFFFFu
+#define ADC_MG_MG_SHIFT 0
+#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK 0x3Fu
+#define ADC_CLPD_CLPD_SHIFT 0
+#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK 0x3Fu
+#define ADC_CLPS_CLPS_SHIFT 0
+#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK 0x3FFu
+#define ADC_CLP4_CLP4_SHIFT 0
+#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK 0x1FFu
+#define ADC_CLP3_CLP3_SHIFT 0
+#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK 0xFFu
+#define ADC_CLP2_CLP2_SHIFT 0
+#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK 0x7Fu
+#define ADC_CLP1_CLP1_SHIFT 0
+#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK 0x3Fu
+#define ADC_CLP0_CLP0_SHIFT 0
+#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK 0x3Fu
+#define ADC_CLMD_CLMD_SHIFT 0
+#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK 0x3Fu
+#define ADC_CLMS_CLMS_SHIFT 0
+#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK 0x3FFu
+#define ADC_CLM4_CLM4_SHIFT 0
+#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK 0x1FFu
+#define ADC_CLM3_CLM3_SHIFT 0
+#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK 0xFFu
+#define ADC_CLM2_CLM2_SHIFT 0
+#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK 0x7Fu
+#define ADC_CLM1_CLM1_SHIFT 0
+#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK 0x3Fu
+#define ADC_CLM0_CLM0_SHIFT 0
+#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+#define ADC0_BASE_PTR (ADC0)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE (0x400BB000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1 ((ADC_Type *)ADC1_BASE)
+#define ADC1_BASE_PTR (ADC1)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
+
+/* ----------------------------------------------------------------------------
+ -- ADC - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
+ * @{
+ */
+
+
+/* ADC - Register instance definitions */
+/* ADC0 */
+#define ADC0_SC1A ADC_SC1_REG(ADC0,0)
+#define ADC0_SC1B ADC_SC1_REG(ADC0,1)
+#define ADC0_CFG1 ADC_CFG1_REG(ADC0)
+#define ADC0_CFG2 ADC_CFG2_REG(ADC0)
+#define ADC0_RA ADC_R_REG(ADC0,0)
+#define ADC0_RB ADC_R_REG(ADC0,1)
+#define ADC0_CV1 ADC_CV1_REG(ADC0)
+#define ADC0_CV2 ADC_CV2_REG(ADC0)
+#define ADC0_SC2 ADC_SC2_REG(ADC0)
+#define ADC0_SC3 ADC_SC3_REG(ADC0)
+#define ADC0_OFS ADC_OFS_REG(ADC0)
+#define ADC0_PG ADC_PG_REG(ADC0)
+#define ADC0_MG ADC_MG_REG(ADC0)
+#define ADC0_CLPD ADC_CLPD_REG(ADC0)
+#define ADC0_CLPS ADC_CLPS_REG(ADC0)
+#define ADC0_CLP4 ADC_CLP4_REG(ADC0)
+#define ADC0_CLP3 ADC_CLP3_REG(ADC0)
+#define ADC0_CLP2 ADC_CLP2_REG(ADC0)
+#define ADC0_CLP1 ADC_CLP1_REG(ADC0)
+#define ADC0_CLP0 ADC_CLP0_REG(ADC0)
+#define ADC0_CLMD ADC_CLMD_REG(ADC0)
+#define ADC0_CLMS ADC_CLMS_REG(ADC0)
+#define ADC0_CLM4 ADC_CLM4_REG(ADC0)
+#define ADC0_CLM3 ADC_CLM3_REG(ADC0)
+#define ADC0_CLM2 ADC_CLM2_REG(ADC0)
+#define ADC0_CLM1 ADC_CLM1_REG(ADC0)
+#define ADC0_CLM0 ADC_CLM0_REG(ADC0)
+/* ADC1 */
+#define ADC1_SC1A ADC_SC1_REG(ADC1,0)
+#define ADC1_SC1B ADC_SC1_REG(ADC1,1)
+#define ADC1_CFG1 ADC_CFG1_REG(ADC1)
+#define ADC1_CFG2 ADC_CFG2_REG(ADC1)
+#define ADC1_RA ADC_R_REG(ADC1,0)
+#define ADC1_RB ADC_R_REG(ADC1,1)
+#define ADC1_CV1 ADC_CV1_REG(ADC1)
+#define ADC1_CV2 ADC_CV2_REG(ADC1)
+#define ADC1_SC2 ADC_SC2_REG(ADC1)
+#define ADC1_SC3 ADC_SC3_REG(ADC1)
+#define ADC1_OFS ADC_OFS_REG(ADC1)
+#define ADC1_PG ADC_PG_REG(ADC1)
+#define ADC1_MG ADC_MG_REG(ADC1)
+#define ADC1_CLPD ADC_CLPD_REG(ADC1)
+#define ADC1_CLPS ADC_CLPS_REG(ADC1)
+#define ADC1_CLP4 ADC_CLP4_REG(ADC1)
+#define ADC1_CLP3 ADC_CLP3_REG(ADC1)
+#define ADC1_CLP2 ADC_CLP2_REG(ADC1)
+#define ADC1_CLP1 ADC_CLP1_REG(ADC1)
+#define ADC1_CLP0 ADC_CLP0_REG(ADC1)
+#define ADC1_CLMD ADC_CLMD_REG(ADC1)
+#define ADC1_CLMS ADC_CLMS_REG(ADC1)
+#define ADC1_CLM4 ADC_CLM4_REG(ADC1)
+#define ADC1_CLM3 ADC_CLM3_REG(ADC1)
+#define ADC1_CLM2 ADC_CLM2_REG(ADC1)
+#define ADC1_CLM1 ADC_CLM1_REG(ADC1)
+#define ADC1_CLM0 ADC_CLM0_REG(ADC1)
+
+/* ADC - Register array accessors */
+#define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
+#define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
+#define ADC0_R(index) ADC_R_REG(ADC0,index)
+#define ADC1_R(index) ADC_R_REG(ADC1,index)
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Accessor_Macros */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- AIPS Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
+ __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
+ __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
+ __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
+ __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
+ __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
+ __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
+ __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
+ __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
+ __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
+ __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
+ __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
+ __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
+ __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
+ __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
+ uint8_t RESERVED_2[16];
+ __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
+} AIPS_Type, *AIPS_MemMapPtr;
+
+/* ----------------------------------------------------------------------------
+ -- AIPS - Register accessor macros
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
+ * @{
+ */
+
+
+/* AIPS - Register accessors */
+#define AIPS_MPRA_REG(base) ((base)->MPRA)
+#define AIPS_PACRA_REG(base) ((base)->PACRA)
+#define AIPS_PACRB_REG(base) ((base)->PACRB)
+#define AIPS_PACRC_REG(base) ((base)->PACRC)
+#define AIPS_PACRD_REG(base) ((base)->PACRD)
+#define AIPS_PACRE_REG(base) ((base)->PACRE)
+#define AIPS_PACRF_REG(base) ((base)->PACRF)
+#define AIPS_PACRG_REG(base) ((base)->PACRG)
+#define AIPS_PACRH_REG(base) ((base)->PACRH)
+#define AIPS_PACRI_REG(base) ((base)->PACRI)
+#define AIPS_PACRJ_REG(base) ((base)->PACRJ)
+#define AIPS_PACRK_REG(base) ((base)->PACRK)
+#define AIPS_PACRL_REG(base) ((base)->PACRL)
+#define AIPS_PACRM_REG(base) ((base)->PACRM)
+#define AIPS_PACRN_REG(base) ((base)->PACRN)
+#define AIPS_PACRO_REG(base) ((base)->PACRO)
+#define AIPS_PACRP_REG(base) ((base)->PACRP)
+#define AIPS_PACRU_REG(base) ((base)->PACRU)
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Accessor_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- AIPS Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/* MPRA Bit Fields */
+#define AIPS_MPRA_MPL5_MASK 0x100u
+#define AIPS_MPRA_MPL5_SHIFT 8
+#define AIPS_MPRA_MTW5_MASK 0x200u
+#define AIPS_MPRA_MTW5_SHIFT 9
+#define AIPS_MPRA_MTR5_MASK 0x400u
+#define AIPS_MPRA_MTR5_SHIFT 10
+#define AIPS_MPRA_MPL4_MASK 0x1000u
+#define AIPS_MPRA_MPL4_SHIFT 12
+#define AIPS_MPRA_MTW4_MASK 0x2000u
+#define AIPS_MPRA_MTW4_SHIFT 13
+#define AIPS_MPRA_MTR4_MASK 0x4000u
+#define AIPS_MPRA_MTR4_SHIFT 14
+#define AIPS_MPRA_MPL3_MASK 0x10000u
+#define AIPS_MPRA_MPL3_SHIFT 16
+#define AIPS_MPRA_MTW3_MASK 0x20000u
+#define AIPS_MPRA_MTW3_SHIFT 17
+#define AIPS_MPRA_MTR3_MASK 0x40000u
+#define AIPS_MPRA_MTR3_SHIFT 18
+#define AIPS_MPRA_MPL2_MASK 0x100000u
+#define AIPS_MPRA_MPL2_SHIFT 20
+#define AIPS_MPRA_MTW2_MASK 0x200000u
+#define AIPS_MPRA_MTW2_SHIFT 21
+#define AIPS_MPRA_MTR2_MASK 0x400000u
+#define AIPS_MPRA_MTR2_SHIFT 22
+#define AIPS_MPRA_MPL1_MASK 0x1000000u
+#define AIPS_MPRA_MPL1_SHIFT 24
+#define AIPS_MPRA_MTW1_MASK 0x2000000u
+#define AIPS_MPRA_MTW1_SHIFT 25
+#define AIPS_MPRA_MTR1_MASK 0x4000000u
+#define AIPS_MPRA_MTR1_SHIFT 26
+#define AIPS_MPRA_MPL0_MASK 0x10000000u
+#define AIPS_MPRA_MPL0_SHIFT 28
+#define AIPS_MPRA_MTW0_MASK 0x20000000u
+#define AIPS_MPRA_MTW0_SHIFT 29
+#define AIPS_MPRA_MTR0_MASK 0x40000000u
+#define AIPS_MPRA_MTR0_SHIFT 30
+/* PACRA Bit Fields */
+#define AIPS_PACRA_TP7_MASK 0x1u
+#define AIPS_PACRA_TP7_SHIFT 0
+#define AIPS_PACRA_WP7_MASK 0x2u
+#define AIPS_PACRA_WP7_SHIFT 1
+#define AIPS_PACRA_SP7_MASK 0x4u
+#define AIPS_PACRA_SP7_SHIFT 2
+#define AIPS_PACRA_TP6_MASK 0x10u
+#define AIPS_PACRA_TP6_SHIFT 4
+#define AIPS_PACRA_WP6_MASK 0x20u
+#define AIPS_PACRA_WP6_SHIFT 5
+#define AIPS_PACRA_SP6_MASK 0x40u
+#define AIPS_PACRA_SP6_SHIFT 6
+#define AIPS_PACRA_TP5_MASK 0x100u
+#define AIPS_PACRA_TP5_SHIFT 8
+#define AIPS_PACRA_WP5_MASK 0x200u
+#define AIPS_PACRA_WP5_SHIFT 9
+#define AIPS_PACRA_SP5_MASK 0x400u
+#define AIPS_PACRA_SP5_SHIFT 10
+#define AIPS_PACRA_TP4_MASK 0x1000u
+#define AIPS_PACRA_TP4_SHIFT 12
+#define AIPS_PACRA_WP4_MASK 0x2000u
+#define AIPS_PACRA_WP4_SHIFT 13
+#define AIPS_PACRA_SP4_MASK 0x4000u
+#define AIPS_PACRA_SP4_SHIFT 14
+#define AIPS_PACRA_TP3_MASK 0x10000u
+#define AIPS_PACRA_TP3_SHIFT 16
+#define AIPS_PACRA_WP3_MASK 0x20000u
+#define AIPS_PACRA_WP3_SHIFT 17
+#define AIPS_PACRA_SP3_MASK 0x40000u
+#define AIPS_PACRA_SP3_SHIFT 18
+#define AIPS_PACRA_TP2_MASK 0x100000u
+#define AIPS_PACRA_TP2_SHIFT 20
+#define AIPS_PACRA_WP2_MASK 0x200000u
+#define AIPS_PACRA_WP2_SHIFT 21
+#define AIPS_PACRA_SP2_MASK 0x400000u
+#define AIPS_PACRA_SP2_SHIFT 22
+#define AIPS_PACRA_TP1_MASK 0x1000000u
+#define AIPS_PACRA_TP1_SHIFT 24
+#define AIPS_PACRA_WP1_MASK 0x2000000u
+#define AIPS_PACRA_WP1_SHIFT 25
+#define AIPS_PACRA_SP1_MASK 0x4000000u
+#define AIPS_PACRA_SP1_SHIFT 26
+#define AIPS_PACRA_TP0_MASK 0x10000000u
+#define AIPS_PACRA_TP0_SHIFT 28
+#define AIPS_PACRA_WP0_MASK 0x20000000u
+#define AIPS_PACRA_WP0_SHIFT 29
+#define AIPS_PACRA_SP0_MASK 0x40000000u
+#define AIPS_PACRA_SP0_SHIFT 30
+/* PACRB Bit Fields */
+#define AIPS_PACRB_TP7_MASK 0x1u
+#define AIPS_PACRB_TP7_SHIFT 0
+#define AIPS_PACRB_WP7_MASK 0x2u
+#define AIPS_PACRB_WP7_SHIFT 1
+#define AIPS_PACRB_SP7_MASK 0x4u
+#define AIPS_PACRB_SP7_SHIFT 2
+#define AIPS_PACRB_TP6_MASK 0x10u
+#define AIPS_PACRB_TP6_SHIFT 4
+#define AIPS_PACRB_WP6_MASK 0x20u
+#define AIPS_PACRB_WP6_SHIFT 5
+#define AIPS_PACRB_SP6_MASK 0x40u
+#define AIPS_PACRB_SP6_SHIFT 6
+#define AIPS_PACRB_TP5_MASK 0x100u
+#define AIPS_PACRB_TP5_SHIFT 8
+#define AIPS_PACRB_WP5_MASK 0x200u
+#define AIPS_PACRB_WP5_SHIFT 9
+#define AIPS_PACRB_SP5_MASK 0x400u
+#define AIPS_PACRB_SP5_SHIFT 10
+#define AIPS_PACRB_TP4_MASK 0x1000u
+#define AIPS_PACRB_TP4_SHIFT 12
+#define AIPS_PACRB_WP4_MASK 0x2000u
+#define AIPS_PACRB_WP4_SHIFT 13
+#define AIPS_PACRB_SP4_MASK 0x4000u
+#define AIPS_PACRB_SP4_SHIFT 14
+#define AIPS_PACRB_TP3_MASK 0x10000u
+#define AIPS_PACRB_TP3_SHIFT 16
+#define AIPS_PACRB_WP3_MASK 0x20000u
+#define AIPS_PACRB_WP3_SHIFT 17
+#define AIPS_PACRB_SP3_MASK 0x40000u
+#define AIPS_PACRB_SP3_SHIFT 18
+#define AIPS_PACRB_TP2_MASK 0x100000u
+#define AIPS_PACRB_TP2_SHIFT 20
+#define AIPS_PACRB_WP2_MASK 0x200000u
+#define AIPS_PACRB_WP2_SHIFT 21
+#define AIPS_PACRB_SP2_MASK 0x400000u
+#define AIPS_PACRB_SP2_SHIFT 22
+#define AIPS_PACRB_TP1_MASK 0x1000000u
+#define AIPS_PACRB_TP1_SHIFT 24
+#define AIPS_PACRB_WP1_MASK 0x2000000u
+#define AIPS_PACRB_WP1_SHIFT 25
+#define AIPS_PACRB_SP1_MASK 0x4000000u
+#define AIPS_PACRB_SP1_SHIFT 26
+#define AIPS_PACRB_TP0_MASK 0x10000000u
+#define AIPS_PACRB_TP0_SHIFT 28
+#define AIPS_PACRB_WP0_MASK 0x20000000u
+#define AIPS_PACRB_WP0_SHIFT 29
+#define AIPS_PACRB_SP0_MASK 0x40000000u
+#define AIPS_PACRB_SP0_SHIFT 30
+/* PACRC Bit Fields */
+#define AIPS_PACRC_TP7_MASK 0x1u
+#define AIPS_PACRC_TP7_SHIFT 0
+#define AIPS_PACRC_WP7_MASK 0x2u
+#define AIPS_PACRC_WP7_SHIFT 1
+#define AIPS_PACRC_SP7_MASK 0x4u
+#define AIPS_PACRC_SP7_SHIFT 2
+#define AIPS_PACRC_TP6_MASK 0x10u
+#define AIPS_PACRC_TP6_SHIFT 4
+#define AIPS_PACRC_WP6_MASK 0x20u
+#define AIPS_PACRC_WP6_SHIFT 5
+#define AIPS_PACRC_SP6_MASK 0x40u
+#define AIPS_PACRC_SP6_SHIFT 6
+#define AIPS_PACRC_TP5_MASK 0x100u
+#define AIPS_PACRC_TP5_SHIFT 8
+#define AIPS_PACRC_WP5_MASK 0x200u
+#define AIPS_PACRC_WP5_SHIFT 9
+#define AIPS_PACRC_SP5_MASK 0x400u
+#define AIPS_PACRC_SP5_SHIFT 10
+#define AIPS_PACRC_TP4_MASK 0x1000u
+#define AIPS_PACRC_TP4_SHIFT 12
+#define AIPS_PACRC_WP4_MASK 0x2000u
+#define AIPS_PACRC_WP4_SHIFT 13
+#define AIPS_PACRC_SP4_MASK 0x4000u
+#define AIPS_PACRC_SP4_SHIFT 14
+#define AIPS_PACRC_TP3_MASK 0x10000u
+#define AIPS_PACRC_TP3_SHIFT 16
+#define AIPS_PACRC_WP3_MASK 0x20000u
+#define AIPS_PACRC_WP3_SHIFT 17
+#define AIPS_PACRC_SP3_MASK 0x40000u
+#define AIPS_PACRC_SP3_SHIFT 18
+#define AIPS_PACRC_TP2_MASK 0x100000u
+#define AIPS_PACRC_TP2_SHIFT 20
+#define AIPS_PACRC_WP2_MASK 0x200000u
+#define AIPS_PACRC_WP2_SHIFT 21
+#define AIPS_PACRC_SP2_MASK 0x400000u
+#define AIPS_PACRC_SP2_SHIFT 22
+#define AIPS_PACRC_TP1_MASK 0x1000000u
+#define AIPS_PACRC_TP1_SHIFT 24
+#define AIPS_PACRC_WP1_MASK 0x2000000u
+#define AIPS_PACRC_WP1_SHIFT 25
+#define AIPS_PACRC_SP1_MASK 0x4000000u
+#define AIPS_PACRC_SP1_SHIFT 26
+#define AIPS_PACRC_TP0_MASK 0x10000000u
+#define AIPS_PACRC_TP0_SHIFT 28
+#define AIPS_PACRC_WP0_MASK 0x20000000u
+#define AIPS_PACRC_WP0_SHIFT 29
+#define AIPS_PACRC_SP0_MASK 0x40000000u
+#define AIPS_PACRC_SP0_SHIFT 30
+/* PACRD Bit Fields */
+#define AIPS_PACRD_TP7_MASK 0x1u
+#define AIPS_PACRD_TP7_SHIFT 0
+#define AIPS_PACRD_WP7_MASK 0x2u
+#define AIPS_PACRD_WP7_SHIFT 1
+#define AIPS_PACRD_SP7_MASK 0x4u
+#define AIPS_PACRD_SP7_SHIFT 2
+#define AIPS_PACRD_TP6_MASK 0x10u
+#define AIPS_PACRD_TP6_SHIFT 4
+#define AIPS_PACRD_WP6_MASK 0x20u
+#define AIPS_PACRD_WP6_SHIFT 5
+#define AIPS_PACRD_SP6_MASK 0x40u
+#define AIPS_PACRD_SP6_SHIFT 6
+#define AIPS_PACRD_TP5_MASK 0x100u
+#define AIPS_PACRD_TP5_SHIFT 8
+#define AIPS_PACRD_WP5_MASK 0x200u
+#define AIPS_PACRD_WP5_SHIFT 9
+#define AIPS_PACRD_SP5_MASK 0x400u
+#define AIPS_PACRD_SP5_SHIFT 10
+#define AIPS_PACRD_TP4_MASK 0x1000u
+#define AIPS_PACRD_TP4_SHIFT 12
+#define AIPS_PACRD_WP4_MASK 0x2000u
+#define AIPS_PACRD_WP4_SHIFT 13
+#define AIPS_PACRD_SP4_MASK 0x4000u
+#define AIPS_PACRD_SP4_SHIFT 14
+#define AIPS_PACRD_TP3_MASK 0x10000u
+#define AIPS_PACRD_TP3_SHIFT 16
+#define AIPS_PACRD_WP3_MASK 0x20000u
+#define AIPS_PACRD_WP3_SHIFT 17
+#define AIPS_PACRD_SP3_MASK 0x40000u
+#define AIPS_PACRD_SP3_SHIFT 18
+#define AIPS_PACRD_TP2_MASK 0x100000u
+#define AIPS_PACRD_TP2_SHIFT 20
+#define AIPS_PACRD_WP2_MASK 0x200000u
+#define AIPS_PACRD_WP2_SHIFT 21
+#define AIPS_PACRD_SP2_MASK 0x400000u
+#define AIPS_PACRD_SP2_SHIFT 22
+#define AIPS_PACRD_TP1_MASK 0x1000000u
+#define AIPS_PACRD_TP1_SHIFT 24
+#define AIPS_PACRD_WP1_MASK 0x2000000u
+#define AIPS_PACRD_WP1_SHIFT 25
+#define AIPS_PACRD_SP1_MASK 0x4000000u
+#define AIPS_PACRD_SP1_SHIFT 26
+#define AIPS_PACRD_TP0_MASK 0x10000000u
+#define AIPS_PACRD_TP0_SHIFT 28
+#define AIPS_PACRD_WP0_MASK 0x20000000u
+#define AIPS_PACRD_WP0_SHIFT 29
+#define AIPS_PACRD_SP0_MASK 0x40000000u
+#define AIPS_PACRD_SP0_SHIFT 30
+/* PACRE Bit Fields */
+#define AIPS_PACRE_TP7_MASK 0x1u
+#define AIPS_PACRE_TP7_SHIFT 0
+#define AIPS_PACRE_WP7_MASK 0x2u
+#define AIPS_PACRE_WP7_SHIFT 1
+#define AIPS_PACRE_SP7_MASK 0x4u
+#define AIPS_PACRE_SP7_SHIFT 2
+#define AIPS_PACRE_TP6_MASK 0x10u
+#define AIPS_PACRE_TP6_SHIFT 4
+#define AIPS_PACRE_WP6_MASK 0x20u
+#define AIPS_PACRE_WP6_SHIFT 5
+#define AIPS_PACRE_SP6_MASK 0x40u
+#define AIPS_PACRE_SP6_SHIFT 6
+#define AIPS_PACRE_TP5_MASK 0x100u
+#define AIPS_PACRE_TP5_SHIFT 8
+#define AIPS_PACRE_WP5_MASK 0x200u
+#define AIPS_PACRE_WP5_SHIFT 9
+#define AIPS_PACRE_SP5_MASK 0x400u
+#define AIPS_PACRE_SP5_SHIFT 10
+#define AIPS_PACRE_TP4_MASK 0x1000u
+#define AIPS_PACRE_TP4_SHIFT 12
+#define AIPS_PACRE_WP4_MASK 0x2000u
+#define AIPS_PACRE_WP4_SHIFT 13
+#define AIPS_PACRE_SP4_MASK 0x4000u
+#define AIPS_PACRE_SP4_SHIFT 14
+#define AIPS_PACRE_TP3_MASK 0x10000u
+#define AIPS_PACRE_TP3_SHIFT 16
+#define AIPS_PACRE_WP3_MASK 0x20000u
+#define AIPS_PACRE_WP3_SHIFT 17
+#define AIPS_PACRE_SP3_MASK 0x40000u
+#define AIPS_PACRE_SP3_SHIFT 18
+#define AIPS_PACRE_TP2_MASK 0x100000u
+#define AIPS_PACRE_TP2_SHIFT 20
+#define AIPS_PACRE_WP2_MASK 0x200000u
+#define AIPS_PACRE_WP2_SHIFT 21
+#define AIPS_PACRE_SP2_MASK 0x400000u
+#define AIPS_PACRE_SP2_SHIFT 22
+#define AIPS_PACRE_TP1_MASK 0x1000000u
+#define AIPS_PACRE_TP1_SHIFT 24
+#define AIPS_PACRE_WP1_MASK 0x2000000u
+#define AIPS_PACRE_WP1_SHIFT 25
+#define AIPS_PACRE_SP1_MASK 0x4000000u
+#define AIPS_PACRE_SP1_SHIFT 26
+#define AIPS_PACRE_TP0_MASK 0x10000000u
+#define AIPS_PACRE_TP0_SHIFT 28
+#define AIPS_PACRE_WP0_MASK 0x20000000u
+#define AIPS_PACRE_WP0_SHIFT 29
+#define AIPS_PACRE_SP0_MASK 0x40000000u
+#define AIPS_PACRE_SP0_SHIFT 30
+/* PACRF Bit Fields */
+#define AIPS_PACRF_TP7_MASK 0x1u
+#define AIPS_PACRF_TP7_SHIFT 0
+#define AIPS_PACRF_WP7_MASK 0x2u
+#define AIPS_PACRF_WP7_SHIFT 1
+#define AIPS_PACRF_SP7_MASK 0x4u
+#define AIPS_PACRF_SP7_SHIFT 2
+#define AIPS_PACRF_TP6_MASK 0x10u
+#define AIPS_PACRF_TP6_SHIFT 4
+#define AIPS_PACRF_WP6_MASK 0x20u
+#define AIPS_PACRF_WP6_SHIFT 5
+#define AIPS_PACRF_SP6_MASK 0x40u
+#define AIPS_PACRF_SP6_SHIFT 6
+#define AIPS_PACRF_TP5_MASK 0x100u
+#define AIPS_PACRF_TP5_SHIFT 8
+#define AIPS_PACRF_WP5_MASK 0x200u
+#define AIPS_PACRF_WP5_SHIFT 9
+#define AIPS_PACRF_SP5_MASK 0x400u
+#define AIPS_PACRF_SP5_SHIFT 10
+#define AIPS_PACRF_TP4_MASK 0x1000u
+#define AIPS_PACRF_TP4_SHIFT 12
+#define AIPS_PACRF_WP4_MASK 0x2000u
+#define AIPS_PACRF_WP4_SHIFT 13
+#define AIPS_PACRF_SP4_MASK 0x4000u
+#define AIPS_PACRF_SP4_SHIFT 14
+#define AIPS_PACRF_TP3_MASK 0x10000u
+#define AIPS_PACRF_TP3_SHIFT 16
+#define AIPS_PACRF_WP3_MASK 0x20000u
+#define AIPS_PACRF_WP3_SHIFT 17
+#define AIPS_PACRF_SP3_MASK 0x40000u
+#define AIPS_PACRF_SP3_SHIFT 18
+#define AIPS_PACRF_TP2_MASK 0x100000u
+#define AIPS_PACRF_TP2_SHIFT 20
+#define AIPS_PACRF_WP2_MASK 0x200000u
+#define AIPS_PACRF_WP2_SHIFT 21
+#define AIPS_PACRF_SP2_MASK 0x400000u
+#define AIPS_PACRF_SP2_SHIFT 22
+#define AIPS_PACRF_TP1_MASK 0x1000000u
+#define AIPS_PACRF_TP1_SHIFT 24
+#define AIPS_PACRF_WP1_MASK 0x2000000u
+#define AIPS_PACRF_WP1_SHIFT 25
+#define AIPS_PACRF_SP1_MASK 0x4000000u
+#define AIPS_PACRF_SP1_SHIFT 26
+#define AIPS_PACRF_TP0_MASK 0x10000000u
+#define AIPS_PACRF_TP0_SHIFT 28
+#define AIPS_PACRF_WP0_MASK 0x20000000u
+#define AIPS_PACRF_WP0_SHIFT 29
+#define AIPS_PACRF_SP0_MASK 0x40000000u
+#define AIPS_PACRF_SP0_SHIFT 30
+/* PACRG Bit Fields */
+#define AIPS_PACRG_TP7_MASK 0x1u
+#define AIPS_PACRG_TP7_SHIFT 0
+#define AIPS_PACRG_WP7_MASK 0x2u
+#define AIPS_PACRG_WP7_SHIFT 1
+#define AIPS_PACRG_SP7_MASK 0x4u
+#define AIPS_PACRG_SP7_SHIFT 2
+#define AIPS_PACRG_TP6_MASK 0x10u
+#define AIPS_PACRG_TP6_SHIFT 4
+#define AIPS_PACRG_WP6_MASK 0x20u
+#define AIPS_PACRG_WP6_SHIFT 5
+#define AIPS_PACRG_SP6_MASK 0x40u
+#define AIPS_PACRG_SP6_SHIFT 6
+#define AIPS_PACRG_TP5_MASK 0x100u
+#define AIPS_PACRG_TP5_SHIFT 8
+#define AIPS_PACRG_WP5_MASK 0x200u
+#define AIPS_PACRG_WP5_SHIFT 9
+#define AIPS_PACRG_SP5_MASK 0x400u
+#define AIPS_PACRG_SP5_SHIFT 10
+#define AIPS_PACRG_TP4_MASK 0x1000u
+#define AIPS_PACRG_TP4_SHIFT 12
+#define AIPS_PACRG_WP4_MASK 0x2000u
+#define AIPS_PACRG_WP4_SHIFT 13
+#define AIPS_PACRG_SP4_MASK 0x4000u
+#define AIPS_PACRG_SP4_SHIFT 14
+#define AIPS_PACRG_TP3_MASK 0x10000u
+#define AIPS_PACRG_TP3_SHIFT 16
+#define AIPS_PACRG_WP3_MASK 0x20000u
+#define AIPS_PACRG_WP3_SHIFT 17
+#define AIPS_PACRG_SP3_MASK 0x40000u
+#define AIPS_PACRG_SP3_SHIFT 18
+#define AIPS_PACRG_TP2_MASK 0x100000u
+#define AIPS_PACRG_TP2_SHIFT 20
+#define AIPS_PACRG_WP2_MASK 0x200000u
+#define AIPS_PACRG_WP2_SHIFT 21
+#define AIPS_PACRG_SP2_MASK 0x400000u
+#define AIPS_PACRG_SP2_SHIFT 22
+#define AIPS_PACR